1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 //===----------------------------------------------------------------------===//
28 // Integer Result Promotion
29 //===----------------------------------------------------------------------===//
31 /// PromoteIntegerResult - This method is called when a result of a node is
32 /// found to be in need of promotion to a larger type. At this point, the node
33 /// may also have invalid operands or may have other results that need
34 /// expansion, we just know that (at least) one result needs promotion.
35 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
36 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
37 SDValue Res = SDValue();
39 // See if the target wants to custom expand this node.
40 if (CustomLowerNode(N, N->getValueType(ResNo), true))
43 switch (N->getOpcode()) {
46 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
47 N->dump(&DAG); dbgs() << "\n";
49 llvm_unreachable("Do not know how to promote this operator!");
50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
57 case ISD::CONVERT_RNDSAT:
58 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
59 case ISD::CTLZ_ZERO_UNDEF:
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
62 case ISD::CTTZ_ZERO_UNDEF:
63 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
64 case ISD::EXTRACT_VECTOR_ELT:
65 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
66 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
67 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
68 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
69 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
70 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
71 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
72 case ISD::SIGN_EXTEND_INREG:
73 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
74 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
76 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
77 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
78 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
80 case ISD::EXTRACT_SUBVECTOR:
81 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
82 case ISD::VECTOR_SHUFFLE:
83 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
84 case ISD::INSERT_VECTOR_ELT:
85 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
86 case ISD::BUILD_VECTOR:
87 Res = PromoteIntRes_BUILD_VECTOR(N); break;
88 case ISD::SCALAR_TO_VECTOR:
89 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
90 case ISD::CONCAT_VECTORS:
91 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
93 case ISD::SIGN_EXTEND:
94 case ISD::ZERO_EXTEND:
95 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
98 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
100 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
107 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
110 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
113 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
116 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
118 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
120 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
122 case ISD::ATOMIC_LOAD:
123 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
125 case ISD::ATOMIC_LOAD_ADD:
126 case ISD::ATOMIC_LOAD_SUB:
127 case ISD::ATOMIC_LOAD_AND:
128 case ISD::ATOMIC_LOAD_OR:
129 case ISD::ATOMIC_LOAD_XOR:
130 case ISD::ATOMIC_LOAD_NAND:
131 case ISD::ATOMIC_LOAD_MIN:
132 case ISD::ATOMIC_LOAD_MAX:
133 case ISD::ATOMIC_LOAD_UMIN:
134 case ISD::ATOMIC_LOAD_UMAX:
135 case ISD::ATOMIC_SWAP:
136 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
138 case ISD::ATOMIC_CMP_SWAP:
139 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
142 // If the result is null then the sub-method took care of registering it.
144 SetPromotedInteger(SDValue(N, ResNo), Res);
147 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
149 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
150 return GetPromotedInteger(Op);
153 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
154 // Sign-extend the new bits, and continue the assertion.
155 SDValue Op = SExtPromotedInteger(N->getOperand(0));
156 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
157 Op.getValueType(), Op, N->getOperand(1));
160 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
161 // Zero the new bits, and continue the assertion.
162 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
163 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
164 Op.getValueType(), Op, N->getOperand(1));
167 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
168 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
169 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
170 N->getMemoryVT(), ResVT,
171 N->getChain(), N->getBasePtr(),
172 N->getMemOperand(), N->getOrdering(),
174 // Legalized the chain result - switch anything that used the old chain to
176 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
180 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
181 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
182 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
184 N->getChain(), N->getBasePtr(),
185 Op2, N->getMemOperand(), N->getOrdering(),
187 // Legalized the chain result - switch anything that used the old chain to
189 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
193 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
194 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
195 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
196 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
197 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
198 Op2, Op3, N->getMemOperand(), N->getOrdering(),
200 // Legalized the chain result - switch anything that used the old chain to
202 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
206 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
207 SDValue InOp = N->getOperand(0);
208 EVT InVT = InOp.getValueType();
209 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
210 EVT OutVT = N->getValueType(0);
211 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
212 DebugLoc dl = N->getDebugLoc();
214 switch (getTypeAction(InVT)) {
215 case TargetLowering::TypeLegal:
217 case TargetLowering::TypePromoteInteger:
218 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
219 // The input promotes to the same size. Convert the promoted value.
220 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
222 case TargetLowering::TypeSoftenFloat:
223 // Promote the integer operand by hand.
224 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
225 case TargetLowering::TypeExpandInteger:
226 case TargetLowering::TypeExpandFloat:
228 case TargetLowering::TypeScalarizeVector:
229 // Convert the element to an integer and promote it by hand.
230 if (!NOutVT.isVector())
231 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
232 BitConvertToInteger(GetScalarizedVector(InOp)));
234 case TargetLowering::TypeSplitVector: {
235 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
236 // pieces of the input into integers and reassemble in the final type.
238 GetSplitVector(N->getOperand(0), Lo, Hi);
239 Lo = BitConvertToInteger(Lo);
240 Hi = BitConvertToInteger(Hi);
242 if (TLI.isBigEndian())
245 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
246 EVT::getIntegerVT(*DAG.getContext(),
247 NOutVT.getSizeInBits()),
248 JoinIntegers(Lo, Hi));
249 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
251 case TargetLowering::TypeWidenVector:
252 // The input is widened to the same size. Convert to the widened value.
253 // Make sure that the outgoing value is not a vector, because this would
254 // make us bitcast between two vectors which are legalized in different ways.
255 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
256 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260 CreateStackStoreLoad(InOp, OutVT));
263 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
264 SDValue Op = GetPromotedInteger(N->getOperand(0));
265 EVT OVT = N->getValueType(0);
266 EVT NVT = Op.getValueType();
267 DebugLoc dl = N->getDebugLoc();
269 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
270 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
271 DAG.getConstant(DiffBits, TLI.getPointerTy()));
274 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
275 // The pair element type may be legal, or may not promote to the same type as
276 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
277 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
278 TLI.getTypeToTransformTo(*DAG.getContext(),
279 N->getValueType(0)), JoinIntegers(N->getOperand(0),
283 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
284 EVT VT = N->getValueType(0);
285 // FIXME there is no actual debug info here
286 DebugLoc dl = N->getDebugLoc();
287 // Zero extend things like i1, sign extend everything else. It shouldn't
288 // matter in theory which one we pick, but this tends to give better code?
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
290 SDValue Result = DAG.getNode(Opc, dl,
291 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
293 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
297 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
298 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
299 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
300 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
301 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
302 "can only promote integers");
303 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
304 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
305 N->getOperand(1), N->getOperand(2),
306 N->getOperand(3), N->getOperand(4), CvtCode);
309 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
310 // Zero extend to the promoted type and do the count there.
311 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
312 DebugLoc dl = N->getDebugLoc();
313 EVT OVT = N->getValueType(0);
314 EVT NVT = Op.getValueType();
315 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
316 // Subtract off the extra leading bits in the bigger type.
317 return DAG.getNode(ISD::SUB, dl, NVT, Op,
318 DAG.getConstant(NVT.getSizeInBits() -
319 OVT.getSizeInBits(), NVT));
322 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
323 // Zero extend to the promoted type and do the count there.
324 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
325 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
328 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
329 SDValue Op = GetPromotedInteger(N->getOperand(0));
330 EVT OVT = N->getValueType(0);
331 EVT NVT = Op.getValueType();
332 DebugLoc dl = N->getDebugLoc();
333 if (N->getOpcode() == ISD::CTTZ) {
334 // The count is the same in the promoted type except if the original
335 // value was zero. This can be handled by setting the bit just off
336 // the top of the original type.
337 APInt TopBit(NVT.getSizeInBits(), 0);
338 TopBit.setBit(OVT.getSizeInBits());
339 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
341 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
344 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
345 DebugLoc dl = N->getDebugLoc();
346 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
347 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
351 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
352 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
353 unsigned NewOpc = N->getOpcode();
354 DebugLoc dl = N->getDebugLoc();
356 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
357 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
358 // and SINT conversions are Custom, there is no way to tell which is
359 // preferable. We choose SINT because that's the right thing on PPC.)
360 if (N->getOpcode() == ISD::FP_TO_UINT &&
361 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
362 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
363 NewOpc = ISD::FP_TO_SINT;
365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
367 // Assert that the converted value fits in the original type. If it doesn't
368 // (eg: because the value being converted is too big), then the result of the
369 // original operation was undefined anyway, so the assert is still correct.
370 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
371 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
372 DAG.getValueType(N->getValueType(0).getScalarType()));
375 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
376 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
377 DebugLoc dl = N->getDebugLoc();
379 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
381 return DAG.getNode(ISD::AssertZext, dl,
382 NVT, Res, DAG.getValueType(N->getValueType(0)));
385 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
386 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
387 DebugLoc dl = N->getDebugLoc();
389 if (getTypeAction(N->getOperand(0).getValueType())
390 == TargetLowering::TypePromoteInteger) {
391 SDValue Res = GetPromotedInteger(N->getOperand(0));
392 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
394 // If the result and operand types are the same after promotion, simplify
395 // to an in-register extension.
396 if (NVT == Res.getValueType()) {
397 // The high bits are not guaranteed to be anything. Insert an extend.
398 if (N->getOpcode() == ISD::SIGN_EXTEND)
399 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
400 DAG.getValueType(N->getOperand(0).getValueType()));
401 if (N->getOpcode() == ISD::ZERO_EXTEND)
402 return DAG.getZeroExtendInReg(Res, dl,
403 N->getOperand(0).getValueType().getScalarType());
404 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
409 // Otherwise, just extend the original operand all the way to the larger type.
410 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
413 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
414 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
416 ISD::LoadExtType ExtType =
417 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
418 DebugLoc dl = N->getDebugLoc();
419 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
421 N->getMemoryVT(), N->isVolatile(),
422 N->isNonTemporal(), N->getAlignment());
424 // Legalized the chain result - switch anything that used the old chain to
426 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
430 /// Promote the overflow flag of an overflowing arithmetic node.
431 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
432 // Simply change the return type of the boolean result.
433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
434 EVT ValueVTs[] = { N->getValueType(0), NVT };
435 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
436 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
437 DAG.getVTList(ValueVTs, 2), Ops, 2);
439 // Modified the sum result - switch anything that used the old sum to use
441 ReplaceValueWith(SDValue(N, 0), Res);
443 return SDValue(Res.getNode(), 1);
446 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
448 return PromoteIntRes_Overflow(N);
450 // The operation overflowed iff the result in the larger type is not the
451 // sign extension of its truncation to the original type.
452 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
453 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
454 EVT OVT = N->getOperand(0).getValueType();
455 EVT NVT = LHS.getValueType();
456 DebugLoc dl = N->getDebugLoc();
458 // Do the arithmetic in the larger type.
459 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
460 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
462 // Calculate the overflow flag: sign extend the arithmetic result from
463 // the original type.
464 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
465 DAG.getValueType(OVT));
466 // Overflowed if and only if this is not equal to Res.
467 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
469 // Use the calculated overflow everywhere.
470 ReplaceValueWith(SDValue(N, 1), Ofl);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
476 // Sign extend the input.
477 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
478 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
479 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
480 LHS.getValueType(), LHS, RHS);
483 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
484 SDValue LHS = GetPromotedInteger(N->getOperand(1));
485 SDValue RHS = GetPromotedInteger(N->getOperand(2));
486 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
487 LHS.getValueType(), N->getOperand(0),LHS,RHS);
490 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
491 SDValue Mask = N->getOperand(0);
492 EVT OpTy = N->getOperand(1).getValueType();
494 // Promote all the way up to the canonical SetCC type.
495 Mask = PromoteTargetBoolean(Mask, TLI.getSetCCResultType(OpTy));
496 SDValue LHS = GetPromotedInteger(N->getOperand(1));
497 SDValue RHS = GetPromotedInteger(N->getOperand(2));
498 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(),
499 LHS.getValueType(), Mask, LHS, RHS);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
503 SDValue LHS = GetPromotedInteger(N->getOperand(2));
504 SDValue RHS = GetPromotedInteger(N->getOperand(3));
505 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
506 LHS.getValueType(), N->getOperand(0),
507 N->getOperand(1), LHS, RHS, N->getOperand(4));
510 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
511 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
515 // Only use the result of getSetCCResultType if it is legal,
516 // otherwise just use the promoted result type (NVT).
517 if (!TLI.isTypeLegal(SVT))
520 DebugLoc dl = N->getDebugLoc();
521 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
522 "Vector compare must return a vector result!");
524 // Get the SETCC result using the canonical SETCC type.
525 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
526 N->getOperand(1), N->getOperand(2));
528 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
529 // Convert to the expected type.
530 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
533 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
534 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
535 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
536 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
539 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
540 SDValue Op = GetPromotedInteger(N->getOperand(0));
541 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
542 Op.getValueType(), Op, N->getOperand(1));
545 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
546 // The input may have strange things in the top bits of the registers, but
547 // these operations don't care. They may have weird bits going out, but
548 // that too is okay if they are integer operations.
549 SDValue LHS = GetPromotedInteger(N->getOperand(0));
550 SDValue RHS = GetPromotedInteger(N->getOperand(1));
551 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
552 LHS.getValueType(), LHS, RHS);
555 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
556 // The input value must be properly sign extended.
557 SDValue Res = SExtPromotedInteger(N->getOperand(0));
558 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
559 Res.getValueType(), Res, N->getOperand(1));
562 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
563 // The input value must be properly zero extended.
564 EVT VT = N->getValueType(0);
565 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
566 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
567 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
570 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
571 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
573 SDValue InOp = N->getOperand(0);
574 DebugLoc dl = N->getDebugLoc();
576 switch (getTypeAction(InOp.getValueType())) {
577 default: llvm_unreachable("Unknown type action!");
578 case TargetLowering::TypeLegal:
579 case TargetLowering::TypeExpandInteger:
582 case TargetLowering::TypePromoteInteger:
583 Res = GetPromotedInteger(InOp);
585 case TargetLowering::TypeSplitVector:
586 EVT InVT = InOp.getValueType();
587 assert(InVT.isVector() && "Cannot split scalar types");
588 unsigned NumElts = InVT.getVectorNumElements();
589 assert(NumElts == NVT.getVectorNumElements() &&
590 "Dst and Src must have the same number of elements");
591 EVT EltVT = InVT.getScalarType();
592 assert(isPowerOf2_32(NumElts) &&
593 "Promoted vector type must be a power of two");
595 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2);
596 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
599 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
600 DAG.getIntPtrConstant(0));
601 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
602 DAG.getIntPtrConstant(NumElts/2));
603 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
604 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
606 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
609 // Truncate to NVT instead of VT
610 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
613 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
615 return PromoteIntRes_Overflow(N);
617 // The operation overflowed iff the result in the larger type is not the
618 // zero extension of its truncation to the original type.
619 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
620 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
621 EVT OVT = N->getOperand(0).getValueType();
622 EVT NVT = LHS.getValueType();
623 DebugLoc dl = N->getDebugLoc();
625 // Do the arithmetic in the larger type.
626 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
627 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
629 // Calculate the overflow flag: zero extend the arithmetic result from
630 // the original type.
631 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
632 // Overflowed if and only if this is not equal to Res.
633 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
635 // Use the calculated overflow everywhere.
636 ReplaceValueWith(SDValue(N, 1), Ofl);
641 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
642 // Promote the overflow bit trivially.
644 return PromoteIntRes_Overflow(N);
646 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
647 DebugLoc DL = N->getDebugLoc();
648 EVT SmallVT = LHS.getValueType();
650 // To determine if the result overflowed in a larger type, we extend the
651 // input to the larger type, do the multiply, then check the high bits of
652 // the result to see if the overflow happened.
653 if (N->getOpcode() == ISD::SMULO) {
654 LHS = SExtPromotedInteger(LHS);
655 RHS = SExtPromotedInteger(RHS);
657 LHS = ZExtPromotedInteger(LHS);
658 RHS = ZExtPromotedInteger(RHS);
660 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
662 // Overflow occurred iff the high part of the result does not
663 // zero/sign-extend the low part.
665 if (N->getOpcode() == ISD::UMULO) {
666 // Unsigned overflow occurred iff the high part is non-zero.
667 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
668 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
669 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
670 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
672 // Signed overflow occurred iff the high part does not sign extend the low.
673 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
674 Mul, DAG.getValueType(SmallVT));
675 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
678 // Use the calculated overflow everywhere.
679 ReplaceValueWith(SDValue(N, 1), Overflow);
683 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
684 // Zero extend the input.
685 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
686 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
687 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
688 LHS.getValueType(), LHS, RHS);
691 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
692 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
693 N->getValueType(0)));
696 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
697 SDValue Chain = N->getOperand(0); // Get the chain.
698 SDValue Ptr = N->getOperand(1); // Get the pointer.
699 EVT VT = N->getValueType(0);
700 DebugLoc dl = N->getDebugLoc();
702 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
703 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
704 // The argument is passed as NumRegs registers of type RegVT.
706 SmallVector<SDValue, 8> Parts(NumRegs);
707 for (unsigned i = 0; i < NumRegs; ++i) {
708 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
709 N->getConstantOperandVal(3));
710 Chain = Parts[i].getValue(1);
713 // Handle endianness of the load.
714 if (TLI.isBigEndian())
715 std::reverse(Parts.begin(), Parts.end());
717 // Assemble the parts in the promoted type.
718 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
719 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
720 for (unsigned i = 1; i < NumRegs; ++i) {
721 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
722 // Shift it to the right position and "or" it in.
723 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
724 DAG.getConstant(i * RegVT.getSizeInBits(),
725 TLI.getPointerTy()));
726 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
729 // Modified the chain result - switch anything that used the old chain to
731 ReplaceValueWith(SDValue(N, 1), Chain);
736 //===----------------------------------------------------------------------===//
737 // Integer Operand Promotion
738 //===----------------------------------------------------------------------===//
740 /// PromoteIntegerOperand - This method is called when the specified operand of
741 /// the specified node is found to need promotion. At this point, all of the
742 /// result types of the node are known to be legal, but other operands of the
743 /// node may need promotion or expansion as well as the specified one.
744 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
745 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
746 SDValue Res = SDValue();
748 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
751 switch (N->getOpcode()) {
754 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
755 N->dump(&DAG); dbgs() << "\n";
757 llvm_unreachable("Do not know how to promote this operator's operand!");
759 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
760 case ISD::ATOMIC_STORE:
761 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
763 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
764 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
765 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
766 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
767 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
768 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
769 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
770 case ISD::CONVERT_RNDSAT:
771 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
772 case ISD::INSERT_VECTOR_ELT:
773 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
774 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
775 case ISD::SCALAR_TO_VECTOR:
776 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
778 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
779 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
780 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
781 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
782 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
783 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
785 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
786 case ISD::FP16_TO_FP32:
787 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
788 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
794 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
797 // If the result is null, the sub-method took care of registering results etc.
798 if (!Res.getNode()) return false;
800 // If the result is N, the sub-method updated N in place. Tell the legalizer
802 if (Res.getNode() == N)
805 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
806 "Invalid operand expansion");
808 ReplaceValueWith(SDValue(N, 0), Res);
812 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
813 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
814 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
815 ISD::CondCode CCCode) {
816 // We have to insert explicit sign or zero extends. Note that we could
817 // insert sign extends for ALL conditions, but zero extend is cheaper on
818 // many machines (an AND instead of two shifts), so prefer it.
820 default: llvm_unreachable("Unknown integer comparison!");
827 // ALL of these operations will work if we either sign or zero extend
828 // the operands (including the unsigned comparisons!). Zero extend is
829 // usually a simpler/cheaper operation, so prefer it.
830 NewLHS = ZExtPromotedInteger(NewLHS);
831 NewRHS = ZExtPromotedInteger(NewRHS);
837 NewLHS = SExtPromotedInteger(NewLHS);
838 NewRHS = SExtPromotedInteger(NewRHS);
843 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
844 SDValue Op = GetPromotedInteger(N->getOperand(0));
845 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
848 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
849 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
850 return DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), N->getMemoryVT(),
851 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
852 N->getOrdering(), N->getSynchScope());
855 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
856 // This should only occur in unusual situations like bitcasting to an
857 // x86_fp80, so just turn it into a store+load
858 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
861 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
862 assert(OpNo == 2 && "Don't know how to promote this operand!");
864 SDValue LHS = N->getOperand(2);
865 SDValue RHS = N->getOperand(3);
866 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
868 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
870 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
871 N->getOperand(1), LHS, RHS, N->getOperand(4)),
875 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
876 assert(OpNo == 1 && "only know how to promote condition");
878 // Promote all the way up to the canonical SetCC type.
879 EVT SVT = TLI.getSetCCResultType(MVT::Other);
880 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
882 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
883 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
884 N->getOperand(2)), 0);
887 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
888 // Since the result type is legal, the operands must promote to it.
889 EVT OVT = N->getOperand(0).getValueType();
890 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
891 SDValue Hi = GetPromotedInteger(N->getOperand(1));
892 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
893 DebugLoc dl = N->getDebugLoc();
895 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
896 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
897 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
900 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
901 // The vector type is legal but the element type is not. This implies
902 // that the vector is a power-of-two in length and that the element
903 // type does not have a strange size (eg: it is not i1).
904 EVT VecVT = N->getValueType(0);
905 unsigned NumElts = VecVT.getVectorNumElements();
906 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
908 // Promote the inserted value. The type does not need to match the
909 // vector element type. Check that any extra bits introduced will be
911 assert(N->getOperand(0).getValueType().getSizeInBits() >=
912 N->getValueType(0).getVectorElementType().getSizeInBits() &&
913 "Type of inserted value narrower than vector element type!");
915 SmallVector<SDValue, 16> NewOps;
916 for (unsigned i = 0; i < NumElts; ++i)
917 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
919 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
922 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
923 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
924 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
925 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
926 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
927 "can only promote integer arguments");
928 SDValue InOp = GetPromotedInteger(N->getOperand(0));
929 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
930 N->getOperand(1), N->getOperand(2),
931 N->getOperand(3), N->getOperand(4), CvtCode);
934 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
937 // Promote the inserted value. This is valid because the type does not
938 // have to match the vector element type.
940 // Check that any extra bits introduced will be truncated away.
941 assert(N->getOperand(1).getValueType().getSizeInBits() >=
942 N->getValueType(0).getVectorElementType().getSizeInBits() &&
943 "Type of inserted value narrower than vector element type!");
944 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
945 GetPromotedInteger(N->getOperand(1)),
950 assert(OpNo == 2 && "Different operand and result vector types?");
952 // Promote the index.
953 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
954 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
955 N->getOperand(1), Idx), 0);
958 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
960 DebugLoc dl = N->getDebugLoc();
961 NewOps[0] = N->getOperand(0);
962 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
963 SDValue Flag = GetPromotedInteger(N->getOperand(i));
964 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
966 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
969 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
970 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
971 // the operand in place.
972 return SDValue(DAG.UpdateNodeOperands(N,
973 GetPromotedInteger(N->getOperand(0))), 0);
976 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
977 assert(OpNo == 0 && "Only know how to promote the condition!");
978 SDValue Cond = N->getOperand(0);
979 EVT OpTy = N->getOperand(1).getValueType();
981 // Promote all the way up to the canonical SetCC type.
982 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
983 OpTy.getScalarType() : OpTy);
984 Cond = PromoteTargetBoolean(Cond, SVT);
986 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
987 N->getOperand(2)), 0);
990 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
991 assert(OpNo == 0 && "Don't know how to promote this operand!");
993 SDValue LHS = N->getOperand(0);
994 SDValue RHS = N->getOperand(1);
995 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
997 // The CC (#4) and the possible return values (#2 and #3) have legal types.
998 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
999 N->getOperand(3), N->getOperand(4)), 0);
1002 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1003 assert(OpNo == 0 && "Don't know how to promote this operand!");
1005 SDValue LHS = N->getOperand(0);
1006 SDValue RHS = N->getOperand(1);
1007 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1009 // The CC (#2) is always legal.
1010 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1013 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1014 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1015 ZExtPromotedInteger(N->getOperand(1))), 0);
1018 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1019 SDValue Op = GetPromotedInteger(N->getOperand(0));
1020 DebugLoc dl = N->getDebugLoc();
1021 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1022 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1023 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1026 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1027 return SDValue(DAG.UpdateNodeOperands(N,
1028 SExtPromotedInteger(N->getOperand(0))), 0);
1031 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1032 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1033 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1034 unsigned Alignment = N->getAlignment();
1035 bool isVolatile = N->isVolatile();
1036 bool isNonTemporal = N->isNonTemporal();
1037 DebugLoc dl = N->getDebugLoc();
1039 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1041 // Truncate the value and store the result.
1042 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
1044 isVolatile, isNonTemporal, Alignment);
1047 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1048 SDValue Op = GetPromotedInteger(N->getOperand(0));
1049 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
1052 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1053 return SDValue(DAG.UpdateNodeOperands(N,
1054 ZExtPromotedInteger(N->getOperand(0))), 0);
1057 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1058 DebugLoc dl = N->getDebugLoc();
1059 SDValue Op = GetPromotedInteger(N->getOperand(0));
1060 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1061 return DAG.getZeroExtendInReg(Op, dl,
1062 N->getOperand(0).getValueType().getScalarType());
1066 //===----------------------------------------------------------------------===//
1067 // Integer Result Expansion
1068 //===----------------------------------------------------------------------===//
1070 /// ExpandIntegerResult - This method is called when the specified result of the
1071 /// specified node is found to need expansion. At this point, the node may also
1072 /// have invalid operands or may have other results that need promotion, we just
1073 /// know that (at least) one result needs expansion.
1074 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1075 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1077 Lo = Hi = SDValue();
1079 // See if the target wants to custom expand this node.
1080 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1083 switch (N->getOpcode()) {
1086 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1087 N->dump(&DAG); dbgs() << "\n";
1089 llvm_unreachable("Do not know how to expand the result of this operator!");
1091 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1092 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1093 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1094 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1096 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1097 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1098 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1099 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1100 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1102 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1103 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1104 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1105 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1106 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1107 case ISD::CTLZ_ZERO_UNDEF:
1108 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1109 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1110 case ISD::CTTZ_ZERO_UNDEF:
1111 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1112 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1113 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1114 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1115 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1116 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1117 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1118 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1119 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1120 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1121 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1122 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1123 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1124 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1126 case ISD::ATOMIC_LOAD_ADD:
1127 case ISD::ATOMIC_LOAD_SUB:
1128 case ISD::ATOMIC_LOAD_AND:
1129 case ISD::ATOMIC_LOAD_OR:
1130 case ISD::ATOMIC_LOAD_XOR:
1131 case ISD::ATOMIC_LOAD_NAND:
1132 case ISD::ATOMIC_LOAD_MIN:
1133 case ISD::ATOMIC_LOAD_MAX:
1134 case ISD::ATOMIC_LOAD_UMIN:
1135 case ISD::ATOMIC_LOAD_UMAX:
1136 case ISD::ATOMIC_SWAP: {
1137 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1138 SplitInteger(Tmp.first, Lo, Hi);
1139 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1145 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1148 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1151 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1154 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1158 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1161 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1163 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1165 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1168 // If Lo/Hi is null, the sub-method took care of registering results etc.
1170 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1173 /// Lower an atomic node to the appropriate builtin call.
1174 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1175 unsigned Opc = Node->getOpcode();
1176 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1181 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1182 case ISD::ATOMIC_SWAP:
1183 switch (VT.SimpleTy) {
1184 default: llvm_unreachable("Unexpected value type for atomic!");
1185 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1186 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1187 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1188 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1191 case ISD::ATOMIC_CMP_SWAP:
1192 switch (VT.SimpleTy) {
1193 default: llvm_unreachable("Unexpected value type for atomic!");
1194 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1195 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1196 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1197 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1200 case ISD::ATOMIC_LOAD_ADD:
1201 switch (VT.SimpleTy) {
1202 default: llvm_unreachable("Unexpected value type for atomic!");
1203 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1204 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1205 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1206 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1209 case ISD::ATOMIC_LOAD_SUB:
1210 switch (VT.SimpleTy) {
1211 default: llvm_unreachable("Unexpected value type for atomic!");
1212 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1213 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1214 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1215 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1218 case ISD::ATOMIC_LOAD_AND:
1219 switch (VT.SimpleTy) {
1220 default: llvm_unreachable("Unexpected value type for atomic!");
1221 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1222 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1223 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1224 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1227 case ISD::ATOMIC_LOAD_OR:
1228 switch (VT.SimpleTy) {
1229 default: llvm_unreachable("Unexpected value type for atomic!");
1230 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1231 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1232 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1233 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1236 case ISD::ATOMIC_LOAD_XOR:
1237 switch (VT.SimpleTy) {
1238 default: llvm_unreachable("Unexpected value type for atomic!");
1239 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1240 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1241 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1242 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1245 case ISD::ATOMIC_LOAD_NAND:
1246 switch (VT.SimpleTy) {
1247 default: llvm_unreachable("Unexpected value type for atomic!");
1248 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1249 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1250 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1251 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1256 return ExpandChainLibCall(LC, Node, false);
1259 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1260 /// and the shift amount is a constant 'Amt'. Expand the operation.
1261 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1262 SDValue &Lo, SDValue &Hi) {
1263 DebugLoc DL = N->getDebugLoc();
1264 // Expand the incoming operand to be shifted, so that we have its parts
1266 GetExpandedInteger(N->getOperand(0), InL, InH);
1268 EVT NVT = InL.getValueType();
1269 unsigned VTBits = N->getValueType(0).getSizeInBits();
1270 unsigned NVTBits = NVT.getSizeInBits();
1271 EVT ShTy = N->getOperand(1).getValueType();
1273 if (N->getOpcode() == ISD::SHL) {
1275 Lo = Hi = DAG.getConstant(0, NVT);
1276 } else if (Amt > NVTBits) {
1277 Lo = DAG.getConstant(0, NVT);
1278 Hi = DAG.getNode(ISD::SHL, DL,
1279 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1280 } else if (Amt == NVTBits) {
1281 Lo = DAG.getConstant(0, NVT);
1283 } else if (Amt == 1 &&
1284 TLI.isOperationLegalOrCustom(ISD::ADDC,
1285 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1286 // Emit this X << 1 as X+X.
1287 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1288 SDValue LoOps[2] = { InL, InL };
1289 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1290 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1291 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1293 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1294 Hi = DAG.getNode(ISD::OR, DL, NVT,
1295 DAG.getNode(ISD::SHL, DL, NVT, InH,
1296 DAG.getConstant(Amt, ShTy)),
1297 DAG.getNode(ISD::SRL, DL, NVT, InL,
1298 DAG.getConstant(NVTBits-Amt, ShTy)));
1303 if (N->getOpcode() == ISD::SRL) {
1305 Lo = DAG.getConstant(0, NVT);
1306 Hi = DAG.getConstant(0, NVT);
1307 } else if (Amt > NVTBits) {
1308 Lo = DAG.getNode(ISD::SRL, DL,
1309 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1310 Hi = DAG.getConstant(0, NVT);
1311 } else if (Amt == NVTBits) {
1313 Hi = DAG.getConstant(0, NVT);
1315 Lo = DAG.getNode(ISD::OR, DL, NVT,
1316 DAG.getNode(ISD::SRL, DL, NVT, InL,
1317 DAG.getConstant(Amt, ShTy)),
1318 DAG.getNode(ISD::SHL, DL, NVT, InH,
1319 DAG.getConstant(NVTBits-Amt, ShTy)));
1320 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1325 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1327 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1328 DAG.getConstant(NVTBits-1, ShTy));
1329 } else if (Amt > NVTBits) {
1330 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1331 DAG.getConstant(Amt-NVTBits, ShTy));
1332 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1333 DAG.getConstant(NVTBits-1, ShTy));
1334 } else if (Amt == NVTBits) {
1336 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1337 DAG.getConstant(NVTBits-1, ShTy));
1339 Lo = DAG.getNode(ISD::OR, DL, NVT,
1340 DAG.getNode(ISD::SRL, DL, NVT, InL,
1341 DAG.getConstant(Amt, ShTy)),
1342 DAG.getNode(ISD::SHL, DL, NVT, InH,
1343 DAG.getConstant(NVTBits-Amt, ShTy)));
1344 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1348 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1349 /// this shift based on knowledge of the high bit of the shift amount. If we
1350 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1352 bool DAGTypeLegalizer::
1353 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1354 SDValue Amt = N->getOperand(1);
1355 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1356 EVT ShTy = Amt.getValueType();
1357 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1358 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1359 assert(isPowerOf2_32(NVTBits) &&
1360 "Expanded integer type size not a power of two!");
1361 DebugLoc dl = N->getDebugLoc();
1363 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1364 APInt KnownZero, KnownOne;
1365 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1367 // If we don't know anything about the high bits, exit.
1368 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1371 // Get the incoming operand to be shifted.
1373 GetExpandedInteger(N->getOperand(0), InL, InH);
1375 // If we know that any of the high bits of the shift amount are one, then we
1376 // can do this as a couple of simple shifts.
1377 if (KnownOne.intersects(HighBitMask)) {
1378 // Mask out the high bit, which we know is set.
1379 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1380 DAG.getConstant(~HighBitMask, ShTy));
1382 switch (N->getOpcode()) {
1383 default: llvm_unreachable("Unknown shift");
1385 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1386 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1389 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1390 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1393 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1394 DAG.getConstant(NVTBits-1, ShTy));
1395 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1401 // FIXME: This code is broken for shifts with a zero amount!
1402 // If we know that all of the high bits of the shift amount are zero, then we
1403 // can do this as a couple of simple shifts.
1404 if ((KnownZero & HighBitMask) == HighBitMask) {
1406 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1407 DAG.getConstant(NVTBits, ShTy),
1410 switch (N->getOpcode()) {
1411 default: llvm_unreachable("Unknown shift");
1412 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1414 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1417 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1418 Hi = DAG.getNode(ISD::OR, NVT,
1419 DAG.getNode(Op1, NVT, InH, Amt),
1420 DAG.getNode(Op2, NVT, InL, Amt2));
1428 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1430 bool DAGTypeLegalizer::
1431 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1432 SDValue Amt = N->getOperand(1);
1433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1434 EVT ShTy = Amt.getValueType();
1435 unsigned NVTBits = NVT.getSizeInBits();
1436 assert(isPowerOf2_32(NVTBits) &&
1437 "Expanded integer type size not a power of two!");
1438 DebugLoc dl = N->getDebugLoc();
1440 // Get the incoming operand to be shifted.
1442 GetExpandedInteger(N->getOperand(0), InL, InH);
1444 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1445 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1446 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1447 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1448 Amt, NVBitsNode, ISD::SETULT);
1450 SDValue LoS, HiS, LoL, HiL;
1451 switch (N->getOpcode()) {
1452 default: llvm_unreachable("Unknown shift");
1454 // Short: ShAmt < NVTBits
1455 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1456 HiS = DAG.getNode(ISD::OR, dl, NVT,
1457 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1458 // FIXME: If Amt is zero, the following shift generates an undefined result
1459 // on some architectures.
1460 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1462 // Long: ShAmt >= NVTBits
1463 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1464 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1466 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1467 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1470 // Short: ShAmt < NVTBits
1471 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1472 LoS = DAG.getNode(ISD::OR, dl, NVT,
1473 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1474 // FIXME: If Amt is zero, the following shift generates an undefined result
1475 // on some architectures.
1476 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1478 // Long: ShAmt >= NVTBits
1479 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1480 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1482 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1483 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1486 // Short: ShAmt < NVTBits
1487 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1488 LoS = DAG.getNode(ISD::OR, dl, NVT,
1489 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1490 // FIXME: If Amt is zero, the following shift generates an undefined result
1491 // on some architectures.
1492 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1494 // Long: ShAmt >= NVTBits
1495 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1496 DAG.getConstant(NVTBits-1, ShTy));
1497 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1499 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1500 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1505 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1506 SDValue &Lo, SDValue &Hi) {
1507 DebugLoc dl = N->getDebugLoc();
1508 // Expand the subcomponents.
1509 SDValue LHSL, LHSH, RHSL, RHSH;
1510 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1511 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1513 EVT NVT = LHSL.getValueType();
1514 SDValue LoOps[2] = { LHSL, RHSL };
1515 SDValue HiOps[3] = { LHSH, RHSH };
1517 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1518 // them. TODO: Teach operation legalization how to expand unsupported
1519 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1520 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1521 // generate a value of this type in the expanded code sequence.
1523 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1524 ISD::ADDC : ISD::SUBC,
1525 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1528 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1529 if (N->getOpcode() == ISD::ADD) {
1530 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1531 HiOps[2] = Lo.getValue(1);
1532 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1534 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1535 HiOps[2] = Lo.getValue(1);
1536 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1541 if (N->getOpcode() == ISD::ADD) {
1542 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1543 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1544 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1546 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1547 DAG.getConstant(1, NVT),
1548 DAG.getConstant(0, NVT));
1549 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1551 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1552 DAG.getConstant(1, NVT), Carry1);
1553 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1555 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1556 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1558 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1559 LoOps[0], LoOps[1], ISD::SETULT);
1560 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1561 DAG.getConstant(1, NVT),
1562 DAG.getConstant(0, NVT));
1563 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1567 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1568 SDValue &Lo, SDValue &Hi) {
1569 // Expand the subcomponents.
1570 SDValue LHSL, LHSH, RHSL, RHSH;
1571 DebugLoc dl = N->getDebugLoc();
1572 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1573 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1574 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1575 SDValue LoOps[2] = { LHSL, RHSL };
1576 SDValue HiOps[3] = { LHSH, RHSH };
1578 if (N->getOpcode() == ISD::ADDC) {
1579 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1580 HiOps[2] = Lo.getValue(1);
1581 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1583 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1584 HiOps[2] = Lo.getValue(1);
1585 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1588 // Legalized the flag result - switch anything that used the old flag to
1590 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1593 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1594 SDValue &Lo, SDValue &Hi) {
1595 // Expand the subcomponents.
1596 SDValue LHSL, LHSH, RHSL, RHSH;
1597 DebugLoc dl = N->getDebugLoc();
1598 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1599 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1600 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1601 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1602 SDValue HiOps[3] = { LHSH, RHSH };
1604 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1605 HiOps[2] = Lo.getValue(1);
1606 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1608 // Legalized the flag result - switch anything that used the old flag to
1610 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1613 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1614 SDValue &Lo, SDValue &Hi) {
1615 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1616 SplitInteger(Res, Lo, Hi);
1619 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1620 SDValue &Lo, SDValue &Hi) {
1621 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1622 DebugLoc dl = N->getDebugLoc();
1623 SDValue Op = N->getOperand(0);
1624 if (Op.getValueType().bitsLE(NVT)) {
1625 // The low part is any extension of the input (which degenerates to a copy).
1626 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1627 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1629 // For example, extension of an i48 to an i64. The operand type necessarily
1630 // promotes to the result type, so will end up being expanded too.
1631 assert(getTypeAction(Op.getValueType()) ==
1632 TargetLowering::TypePromoteInteger &&
1633 "Only know how to promote this result!");
1634 SDValue Res = GetPromotedInteger(Op);
1635 assert(Res.getValueType() == N->getValueType(0) &&
1636 "Operand over promoted?");
1637 // Split the promoted operand. This will simplify when it is expanded.
1638 SplitInteger(Res, Lo, Hi);
1642 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1643 SDValue &Lo, SDValue &Hi) {
1644 DebugLoc dl = N->getDebugLoc();
1645 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1646 EVT NVT = Lo.getValueType();
1647 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1648 unsigned NVTBits = NVT.getSizeInBits();
1649 unsigned EVTBits = EVT.getSizeInBits();
1651 if (NVTBits < EVTBits) {
1652 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1653 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1654 EVTBits - NVTBits)));
1656 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1657 // The high part replicates the sign bit of Lo, make it explicit.
1658 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1659 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1663 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1664 SDValue &Lo, SDValue &Hi) {
1665 DebugLoc dl = N->getDebugLoc();
1666 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1667 EVT NVT = Lo.getValueType();
1668 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1669 unsigned NVTBits = NVT.getSizeInBits();
1670 unsigned EVTBits = EVT.getSizeInBits();
1672 if (NVTBits < EVTBits) {
1673 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1674 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1675 EVTBits - NVTBits)));
1677 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1678 // The high part must be zero, make it explicit.
1679 Hi = DAG.getConstant(0, NVT);
1683 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1684 SDValue &Lo, SDValue &Hi) {
1685 DebugLoc dl = N->getDebugLoc();
1686 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1687 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1688 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1691 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1692 SDValue &Lo, SDValue &Hi) {
1693 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1694 unsigned NBitWidth = NVT.getSizeInBits();
1695 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1696 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1697 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1700 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1701 SDValue &Lo, SDValue &Hi) {
1702 DebugLoc dl = N->getDebugLoc();
1703 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1704 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1705 EVT NVT = Lo.getValueType();
1707 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1708 DAG.getConstant(0, NVT), ISD::SETNE);
1710 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1711 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1713 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1714 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1715 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1716 Hi = DAG.getConstant(0, NVT);
1719 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1720 SDValue &Lo, SDValue &Hi) {
1721 DebugLoc dl = N->getDebugLoc();
1722 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1723 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1724 EVT NVT = Lo.getValueType();
1725 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1726 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1727 Hi = DAG.getConstant(0, NVT);
1730 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1731 SDValue &Lo, SDValue &Hi) {
1732 DebugLoc dl = N->getDebugLoc();
1733 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1734 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1735 EVT NVT = Lo.getValueType();
1737 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1738 DAG.getConstant(0, NVT), ISD::SETNE);
1740 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1741 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1743 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1744 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1745 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1746 Hi = DAG.getConstant(0, NVT);
1749 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1751 DebugLoc dl = N->getDebugLoc();
1752 EVT VT = N->getValueType(0);
1753 SDValue Op = N->getOperand(0);
1754 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1755 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1756 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1759 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1761 DebugLoc dl = N->getDebugLoc();
1762 EVT VT = N->getValueType(0);
1763 SDValue Op = N->getOperand(0);
1764 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1765 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1766 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1769 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1770 SDValue &Lo, SDValue &Hi) {
1771 if (ISD::isNormalLoad(N)) {
1772 ExpandRes_NormalLoad(N, Lo, Hi);
1776 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1778 EVT VT = N->getValueType(0);
1779 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1780 SDValue Ch = N->getChain();
1781 SDValue Ptr = N->getBasePtr();
1782 ISD::LoadExtType ExtType = N->getExtensionType();
1783 unsigned Alignment = N->getAlignment();
1784 bool isVolatile = N->isVolatile();
1785 bool isNonTemporal = N->isNonTemporal();
1786 bool isInvariant = N->isInvariant();
1787 DebugLoc dl = N->getDebugLoc();
1789 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1791 if (N->getMemoryVT().bitsLE(NVT)) {
1792 EVT MemVT = N->getMemoryVT();
1794 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1795 MemVT, isVolatile, isNonTemporal, Alignment);
1797 // Remember the chain.
1798 Ch = Lo.getValue(1);
1800 if (ExtType == ISD::SEXTLOAD) {
1801 // The high part is obtained by SRA'ing all but one of the bits of the
1803 unsigned LoSize = Lo.getValueType().getSizeInBits();
1804 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1805 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1806 } else if (ExtType == ISD::ZEXTLOAD) {
1807 // The high part is just a zero.
1808 Hi = DAG.getConstant(0, NVT);
1810 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1811 // The high part is undefined.
1812 Hi = DAG.getUNDEF(NVT);
1814 } else if (TLI.isLittleEndian()) {
1815 // Little-endian - low bits are at low addresses.
1816 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1817 isVolatile, isNonTemporal, isInvariant, Alignment);
1819 unsigned ExcessBits =
1820 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1821 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1823 // Increment the pointer to the other half.
1824 unsigned IncrementSize = NVT.getSizeInBits()/8;
1825 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1826 DAG.getIntPtrConstant(IncrementSize));
1827 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1828 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1829 isVolatile, isNonTemporal,
1830 MinAlign(Alignment, IncrementSize));
1832 // Build a factor node to remember that this load is independent of the
1834 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1837 // Big-endian - high bits are at low addresses. Favor aligned loads at
1838 // the cost of some bit-fiddling.
1839 EVT MemVT = N->getMemoryVT();
1840 unsigned EBytes = MemVT.getStoreSize();
1841 unsigned IncrementSize = NVT.getSizeInBits()/8;
1842 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1844 // Load both the high bits and maybe some of the low bits.
1845 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1846 EVT::getIntegerVT(*DAG.getContext(),
1847 MemVT.getSizeInBits() - ExcessBits),
1848 isVolatile, isNonTemporal, Alignment);
1850 // Increment the pointer to the other half.
1851 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1852 DAG.getIntPtrConstant(IncrementSize));
1853 // Load the rest of the low bits.
1854 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1855 N->getPointerInfo().getWithOffset(IncrementSize),
1856 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1857 isVolatile, isNonTemporal,
1858 MinAlign(Alignment, IncrementSize));
1860 // Build a factor node to remember that this load is independent of the
1862 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1865 if (ExcessBits < NVT.getSizeInBits()) {
1866 // Transfer low bits from the bottom of Hi to the top of Lo.
1867 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1868 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1869 DAG.getConstant(ExcessBits,
1870 TLI.getPointerTy())));
1871 // Move high bits to the right position in Hi.
1872 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1874 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1875 TLI.getPointerTy()));
1879 // Legalized the chain result - switch anything that used the old chain to
1881 ReplaceValueWith(SDValue(N, 1), Ch);
1884 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1885 SDValue &Lo, SDValue &Hi) {
1886 DebugLoc dl = N->getDebugLoc();
1887 SDValue LL, LH, RL, RH;
1888 GetExpandedInteger(N->getOperand(0), LL, LH);
1889 GetExpandedInteger(N->getOperand(1), RL, RH);
1890 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1891 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1894 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1895 SDValue &Lo, SDValue &Hi) {
1896 EVT VT = N->getValueType(0);
1897 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1898 DebugLoc dl = N->getDebugLoc();
1900 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1901 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1902 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1903 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1904 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1905 SDValue LL, LH, RL, RH;
1906 GetExpandedInteger(N->getOperand(0), LL, LH);
1907 GetExpandedInteger(N->getOperand(1), RL, RH);
1908 unsigned OuterBitSize = VT.getSizeInBits();
1909 unsigned InnerBitSize = NVT.getSizeInBits();
1910 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1911 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1913 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1914 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1915 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1916 // The inputs are both zero-extended.
1918 // We can emit a umul_lohi.
1919 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1920 Hi = SDValue(Lo.getNode(), 1);
1924 // We can emit a mulhu+mul.
1925 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1926 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1930 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1931 // The input values are both sign-extended.
1933 // We can emit a smul_lohi.
1934 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1935 Hi = SDValue(Lo.getNode(), 1);
1939 // We can emit a mulhs+mul.
1940 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1941 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1946 // Lo,Hi = umul LHS, RHS.
1947 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1948 DAG.getVTList(NVT, NVT), LL, RL);
1950 Hi = UMulLOHI.getValue(1);
1951 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1952 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1953 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1954 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1958 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1959 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1960 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1961 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1962 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1963 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1968 // If nothing else, we can make a libcall.
1969 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1971 LC = RTLIB::MUL_I16;
1972 else if (VT == MVT::i32)
1973 LC = RTLIB::MUL_I32;
1974 else if (VT == MVT::i64)
1975 LC = RTLIB::MUL_I64;
1976 else if (VT == MVT::i128)
1977 LC = RTLIB::MUL_I128;
1978 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1980 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1981 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1984 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1985 SDValue &Lo, SDValue &Hi) {
1986 SDValue LHS = Node->getOperand(0);
1987 SDValue RHS = Node->getOperand(1);
1988 DebugLoc dl = Node->getDebugLoc();
1990 // Expand the result by simply replacing it with the equivalent
1991 // non-overflow-checking operation.
1992 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1993 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1995 SplitInteger(Sum, Lo, Hi);
1997 // Compute the overflow.
1999 // LHSSign -> LHS >= 0
2000 // RHSSign -> RHS >= 0
2001 // SumSign -> Sum >= 0
2004 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2006 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2008 EVT OType = Node->getValueType(1);
2009 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2011 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2012 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2013 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2014 Node->getOpcode() == ISD::SADDO ?
2015 ISD::SETEQ : ISD::SETNE);
2017 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2018 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2020 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2022 // Use the calculated overflow everywhere.
2023 ReplaceValueWith(SDValue(Node, 1), Cmp);
2026 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2027 SDValue &Lo, SDValue &Hi) {
2028 EVT VT = N->getValueType(0);
2029 DebugLoc dl = N->getDebugLoc();
2031 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2033 LC = RTLIB::SDIV_I16;
2034 else if (VT == MVT::i32)
2035 LC = RTLIB::SDIV_I32;
2036 else if (VT == MVT::i64)
2037 LC = RTLIB::SDIV_I64;
2038 else if (VT == MVT::i128)
2039 LC = RTLIB::SDIV_I128;
2040 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2042 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2043 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2046 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2047 SDValue &Lo, SDValue &Hi) {
2048 EVT VT = N->getValueType(0);
2049 DebugLoc dl = N->getDebugLoc();
2051 // If we can emit an efficient shift operation, do so now. Check to see if
2052 // the RHS is a constant.
2053 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2054 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2056 // If we can determine that the high bit of the shift is zero or one, even if
2057 // the low bits are variable, emit this shift in an optimized form.
2058 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2061 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2063 if (N->getOpcode() == ISD::SHL) {
2064 PartsOpc = ISD::SHL_PARTS;
2065 } else if (N->getOpcode() == ISD::SRL) {
2066 PartsOpc = ISD::SRL_PARTS;
2068 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2069 PartsOpc = ISD::SRA_PARTS;
2072 // Next check to see if the target supports this SHL_PARTS operation or if it
2073 // will custom expand it.
2074 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2075 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2076 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2077 Action == TargetLowering::Custom) {
2078 // Expand the subcomponents.
2080 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2082 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
2083 EVT VT = LHSL.getValueType();
2084 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
2085 Hi = Lo.getValue(1);
2089 // Otherwise, emit a libcall.
2090 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2092 if (N->getOpcode() == ISD::SHL) {
2093 isSigned = false; /*sign irrelevant*/
2095 LC = RTLIB::SHL_I16;
2096 else if (VT == MVT::i32)
2097 LC = RTLIB::SHL_I32;
2098 else if (VT == MVT::i64)
2099 LC = RTLIB::SHL_I64;
2100 else if (VT == MVT::i128)
2101 LC = RTLIB::SHL_I128;
2102 } else if (N->getOpcode() == ISD::SRL) {
2105 LC = RTLIB::SRL_I16;
2106 else if (VT == MVT::i32)
2107 LC = RTLIB::SRL_I32;
2108 else if (VT == MVT::i64)
2109 LC = RTLIB::SRL_I64;
2110 else if (VT == MVT::i128)
2111 LC = RTLIB::SRL_I128;
2113 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2116 LC = RTLIB::SRA_I16;
2117 else if (VT == MVT::i32)
2118 LC = RTLIB::SRA_I32;
2119 else if (VT == MVT::i64)
2120 LC = RTLIB::SRA_I64;
2121 else if (VT == MVT::i128)
2122 LC = RTLIB::SRA_I128;
2125 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2126 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2127 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2131 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2132 llvm_unreachable("Unsupported shift!");
2135 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2136 SDValue &Lo, SDValue &Hi) {
2137 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2138 DebugLoc dl = N->getDebugLoc();
2139 SDValue Op = N->getOperand(0);
2140 if (Op.getValueType().bitsLE(NVT)) {
2141 // The low part is sign extension of the input (degenerates to a copy).
2142 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2143 // The high part is obtained by SRA'ing all but one of the bits of low part.
2144 unsigned LoSize = NVT.getSizeInBits();
2145 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2146 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2148 // For example, extension of an i48 to an i64. The operand type necessarily
2149 // promotes to the result type, so will end up being expanded too.
2150 assert(getTypeAction(Op.getValueType()) ==
2151 TargetLowering::TypePromoteInteger &&
2152 "Only know how to promote this result!");
2153 SDValue Res = GetPromotedInteger(Op);
2154 assert(Res.getValueType() == N->getValueType(0) &&
2155 "Operand over promoted?");
2156 // Split the promoted operand. This will simplify when it is expanded.
2157 SplitInteger(Res, Lo, Hi);
2158 unsigned ExcessBits =
2159 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2160 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2161 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2166 void DAGTypeLegalizer::
2167 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2168 DebugLoc dl = N->getDebugLoc();
2169 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2170 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2172 if (EVT.bitsLE(Lo.getValueType())) {
2173 // sext_inreg the low part if needed.
2174 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2177 // The high part gets the sign extension from the lo-part. This handles
2178 // things like sextinreg V:i64 from i8.
2179 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2180 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2181 TLI.getPointerTy()));
2183 // For example, extension of an i48 to an i64. Leave the low part alone,
2184 // sext_inreg the high part.
2185 unsigned ExcessBits =
2186 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2187 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2188 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2193 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2194 SDValue &Lo, SDValue &Hi) {
2195 EVT VT = N->getValueType(0);
2196 DebugLoc dl = N->getDebugLoc();
2198 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2200 LC = RTLIB::SREM_I16;
2201 else if (VT == MVT::i32)
2202 LC = RTLIB::SREM_I32;
2203 else if (VT == MVT::i64)
2204 LC = RTLIB::SREM_I64;
2205 else if (VT == MVT::i128)
2206 LC = RTLIB::SREM_I128;
2207 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2209 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2210 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2213 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2214 SDValue &Lo, SDValue &Hi) {
2215 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2216 DebugLoc dl = N->getDebugLoc();
2217 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2218 Hi = DAG.getNode(ISD::SRL, dl,
2219 N->getOperand(0).getValueType(), N->getOperand(0),
2220 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2221 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2224 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2225 SDValue &Lo, SDValue &Hi) {
2226 SDValue LHS = N->getOperand(0);
2227 SDValue RHS = N->getOperand(1);
2228 DebugLoc dl = N->getDebugLoc();
2230 // Expand the result by simply replacing it with the equivalent
2231 // non-overflow-checking operation.
2232 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2233 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2235 SplitInteger(Sum, Lo, Hi);
2237 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2238 // overflows iff a - b > a.
2239 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2240 N->getOpcode () == ISD::UADDO ?
2241 ISD::SETULT : ISD::SETUGT);
2243 // Use the calculated overflow everywhere.
2244 ReplaceValueWith(SDValue(N, 1), Ofl);
2247 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2248 SDValue &Lo, SDValue &Hi) {
2249 EVT VT = N->getValueType(0);
2250 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2251 EVT PtrVT = TLI.getPointerTy();
2252 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2253 DebugLoc dl = N->getDebugLoc();
2255 // A divide for UMULO should be faster than a function call.
2256 if (N->getOpcode() == ISD::UMULO) {
2257 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2258 DebugLoc DL = N->getDebugLoc();
2260 SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
2261 SplitInteger(MUL, Lo, Hi);
2263 // A divide for UMULO will be faster than a function call. Select to
2264 // make sure we aren't using 0.
2265 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2266 RHS, DAG.getConstant(0, VT), ISD::SETNE);
2267 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
2268 DAG.getConstant(1, VT), RHS);
2269 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
2271 Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
2272 ReplaceValueWith(SDValue(N, 1), Overflow);
2276 // Replace this with a libcall that will check overflow.
2277 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2279 LC = RTLIB::MULO_I32;
2280 else if (VT == MVT::i64)
2281 LC = RTLIB::MULO_I64;
2282 else if (VT == MVT::i128)
2283 LC = RTLIB::MULO_I128;
2284 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2286 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2287 // Temporary for the overflow value, default it to zero.
2288 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2289 DAG.getConstant(0, PtrVT), Temp,
2290 MachinePointerInfo(), false, false, 0);
2292 TargetLowering::ArgListTy Args;
2293 TargetLowering::ArgListEntry Entry;
2294 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2295 EVT ArgVT = N->getOperand(i).getValueType();
2296 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2297 Entry.Node = N->getOperand(i);
2299 Entry.isSExt = true;
2300 Entry.isZExt = false;
2301 Args.push_back(Entry);
2304 // Also pass the address of the overflow check.
2306 Entry.Ty = PtrTy->getPointerTo();
2307 Entry.isSExt = true;
2308 Entry.isZExt = false;
2309 Args.push_back(Entry);
2311 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2312 std::pair<SDValue, SDValue> CallInfo =
2313 TLI.LowerCallTo(Chain, RetTy, true, false, false, false,
2314 0, TLI.getLibcallCallingConv(LC), false,
2315 true, Func, Args, DAG, dl);
2317 SplitInteger(CallInfo.first, Lo, Hi);
2318 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2319 MachinePointerInfo(), false, false, false, 0);
2320 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2321 DAG.getConstant(0, PtrVT),
2323 // Use the overflow from the libcall everywhere.
2324 ReplaceValueWith(SDValue(N, 1), Ofl);
2327 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2328 SDValue &Lo, SDValue &Hi) {
2329 EVT VT = N->getValueType(0);
2330 DebugLoc dl = N->getDebugLoc();
2332 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2334 LC = RTLIB::UDIV_I16;
2335 else if (VT == MVT::i32)
2336 LC = RTLIB::UDIV_I32;
2337 else if (VT == MVT::i64)
2338 LC = RTLIB::UDIV_I64;
2339 else if (VT == MVT::i128)
2340 LC = RTLIB::UDIV_I128;
2341 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2343 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2344 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2347 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2348 SDValue &Lo, SDValue &Hi) {
2349 EVT VT = N->getValueType(0);
2350 DebugLoc dl = N->getDebugLoc();
2352 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2354 LC = RTLIB::UREM_I16;
2355 else if (VT == MVT::i32)
2356 LC = RTLIB::UREM_I32;
2357 else if (VT == MVT::i64)
2358 LC = RTLIB::UREM_I64;
2359 else if (VT == MVT::i128)
2360 LC = RTLIB::UREM_I128;
2361 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2363 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2364 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2367 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2368 SDValue &Lo, SDValue &Hi) {
2369 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2370 DebugLoc dl = N->getDebugLoc();
2371 SDValue Op = N->getOperand(0);
2372 if (Op.getValueType().bitsLE(NVT)) {
2373 // The low part is zero extension of the input (degenerates to a copy).
2374 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2375 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2377 // For example, extension of an i48 to an i64. The operand type necessarily
2378 // promotes to the result type, so will end up being expanded too.
2379 assert(getTypeAction(Op.getValueType()) ==
2380 TargetLowering::TypePromoteInteger &&
2381 "Only know how to promote this result!");
2382 SDValue Res = GetPromotedInteger(Op);
2383 assert(Res.getValueType() == N->getValueType(0) &&
2384 "Operand over promoted?");
2385 // Split the promoted operand. This will simplify when it is expanded.
2386 SplitInteger(Res, Lo, Hi);
2387 unsigned ExcessBits =
2388 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2389 Hi = DAG.getZeroExtendInReg(Hi, dl,
2390 EVT::getIntegerVT(*DAG.getContext(),
2395 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2396 SDValue &Lo, SDValue &Hi) {
2397 DebugLoc dl = N->getDebugLoc();
2398 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2399 SDValue Zero = DAG.getConstant(0, VT);
2400 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
2402 N->getOperand(1), Zero, Zero,
2403 cast<AtomicSDNode>(N)->getMemOperand(),
2404 cast<AtomicSDNode>(N)->getOrdering(),
2405 cast<AtomicSDNode>(N)->getSynchScope());
2406 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2407 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1));
2410 //===----------------------------------------------------------------------===//
2411 // Integer Operand Expansion
2412 //===----------------------------------------------------------------------===//
2414 /// ExpandIntegerOperand - This method is called when the specified operand of
2415 /// the specified node is found to need expansion. At this point, all of the
2416 /// result types of the node are known to be legal, but other operands of the
2417 /// node may need promotion or expansion as well as the specified one.
2418 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2419 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2420 SDValue Res = SDValue();
2422 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2425 switch (N->getOpcode()) {
2428 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2429 N->dump(&DAG); dbgs() << "\n";
2431 llvm_unreachable("Do not know how to expand this operator's operand!");
2433 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2434 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2435 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2436 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2437 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2438 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2439 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2440 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2441 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2442 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2443 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2444 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2450 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2451 case ISD::RETURNADDR:
2452 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2454 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2457 // If the result is null, the sub-method took care of registering results etc.
2458 if (!Res.getNode()) return false;
2460 // If the result is N, the sub-method updated N in place. Tell the legalizer
2462 if (Res.getNode() == N)
2465 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2466 "Invalid operand expansion");
2468 ReplaceValueWith(SDValue(N, 0), Res);
2472 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2473 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2474 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2476 ISD::CondCode &CCCode,
2478 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2479 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2480 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2482 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2483 if (RHSLo == RHSHi) {
2484 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2485 if (RHSCST->isAllOnesValue()) {
2486 // Equality comparison to -1.
2487 NewLHS = DAG.getNode(ISD::AND, dl,
2488 LHSLo.getValueType(), LHSLo, LHSHi);
2495 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2496 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2497 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2498 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2502 // If this is a comparison of the sign bit, just look at the top part.
2504 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2505 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2506 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2512 // FIXME: This generated code sucks.
2513 ISD::CondCode LowCC;
2515 default: llvm_unreachable("Unknown integer setcc!");
2517 case ISD::SETULT: LowCC = ISD::SETULT; break;
2519 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2521 case ISD::SETULE: LowCC = ISD::SETULE; break;
2523 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2526 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2527 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2528 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2530 // NOTE: on targets without efficient SELECT of bools, we can always use
2531 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2532 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2534 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2535 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2536 if (!Tmp1.getNode())
2537 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2538 LHSLo, RHSLo, LowCC);
2539 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2540 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2541 if (!Tmp2.getNode())
2542 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2543 TLI.getSetCCResultType(LHSHi.getValueType()),
2544 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2546 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2547 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2548 if ((Tmp1C && Tmp1C->isNullValue()) ||
2549 (Tmp2C && Tmp2C->isNullValue() &&
2550 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2551 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2552 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2553 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2554 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2555 // low part is known false, returns high part.
2556 // For LE / GE, if high part is known false, ignore the low part.
2557 // For LT / GT, if high part is known true, ignore the low part.
2563 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2564 LHSHi, RHSHi, ISD::SETEQ, false,
2565 DagCombineInfo, dl);
2566 if (!NewLHS.getNode())
2567 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2568 LHSHi, RHSHi, ISD::SETEQ);
2569 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2570 NewLHS, Tmp1, Tmp2);
2574 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2575 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2576 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2577 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2579 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2580 // against zero to select between true and false values.
2581 if (NewRHS.getNode() == 0) {
2582 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2583 CCCode = ISD::SETNE;
2586 // Update N to have the operands specified.
2587 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2588 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2589 N->getOperand(4)), 0);
2592 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2593 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2594 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2595 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2597 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2598 // against zero to select between true and false values.
2599 if (NewRHS.getNode() == 0) {
2600 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2601 CCCode = ISD::SETNE;
2604 // Update N to have the operands specified.
2605 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2606 N->getOperand(2), N->getOperand(3),
2607 DAG.getCondCode(CCCode)), 0);
2610 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2611 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2612 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2613 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2615 // If ExpandSetCCOperands returned a scalar, use it.
2616 if (NewRHS.getNode() == 0) {
2617 assert(NewLHS.getValueType() == N->getValueType(0) &&
2618 "Unexpected setcc expansion!");
2622 // Otherwise, update N to have the operands specified.
2623 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2624 DAG.getCondCode(CCCode)), 0);
2627 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2628 // The value being shifted is legal, but the shift amount is too big.
2629 // It follows that either the result of the shift is undefined, or the
2630 // upper half of the shift amount is zero. Just use the lower half.
2632 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2633 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2636 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2637 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2638 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2639 // constant to valid type.
2641 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2642 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2645 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2646 SDValue Op = N->getOperand(0);
2647 EVT DstVT = N->getValueType(0);
2648 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2649 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2650 "Don't know how to expand this SINT_TO_FP!");
2651 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2654 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2655 if (ISD::isNormalStore(N))
2656 return ExpandOp_NormalStore(N, OpNo);
2658 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2659 assert(OpNo == 1 && "Can only expand the stored value so far");
2661 EVT VT = N->getOperand(1).getValueType();
2662 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2663 SDValue Ch = N->getChain();
2664 SDValue Ptr = N->getBasePtr();
2665 unsigned Alignment = N->getAlignment();
2666 bool isVolatile = N->isVolatile();
2667 bool isNonTemporal = N->isNonTemporal();
2668 DebugLoc dl = N->getDebugLoc();
2671 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2673 if (N->getMemoryVT().bitsLE(NVT)) {
2674 GetExpandedInteger(N->getValue(), Lo, Hi);
2675 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2676 N->getMemoryVT(), isVolatile, isNonTemporal,
2680 if (TLI.isLittleEndian()) {
2681 // Little-endian - low bits are at low addresses.
2682 GetExpandedInteger(N->getValue(), Lo, Hi);
2684 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2685 isVolatile, isNonTemporal, Alignment);
2687 unsigned ExcessBits =
2688 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2689 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2691 // Increment the pointer to the other half.
2692 unsigned IncrementSize = NVT.getSizeInBits()/8;
2693 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2694 DAG.getIntPtrConstant(IncrementSize));
2695 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2696 N->getPointerInfo().getWithOffset(IncrementSize),
2697 NEVT, isVolatile, isNonTemporal,
2698 MinAlign(Alignment, IncrementSize));
2699 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2702 // Big-endian - high bits are at low addresses. Favor aligned stores at
2703 // the cost of some bit-fiddling.
2704 GetExpandedInteger(N->getValue(), Lo, Hi);
2706 EVT ExtVT = N->getMemoryVT();
2707 unsigned EBytes = ExtVT.getStoreSize();
2708 unsigned IncrementSize = NVT.getSizeInBits()/8;
2709 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2710 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2711 ExtVT.getSizeInBits() - ExcessBits);
2713 if (ExcessBits < NVT.getSizeInBits()) {
2714 // Transfer high bits from the top of Lo to the bottom of Hi.
2715 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2716 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2717 TLI.getPointerTy()));
2718 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2719 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2720 DAG.getConstant(ExcessBits,
2721 TLI.getPointerTy())));
2724 // Store both the high bits and maybe some of the low bits.
2725 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2726 HiVT, isVolatile, isNonTemporal, Alignment);
2728 // Increment the pointer to the other half.
2729 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2730 DAG.getIntPtrConstant(IncrementSize));
2731 // Store the lowest ExcessBits bits in the second half.
2732 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2733 N->getPointerInfo().getWithOffset(IncrementSize),
2734 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2735 isVolatile, isNonTemporal,
2736 MinAlign(Alignment, IncrementSize));
2737 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2740 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2742 GetExpandedInteger(N->getOperand(0), InL, InH);
2743 // Just truncate the low part of the source.
2744 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2747 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2748 switch (VT.getSimpleVT().SimpleTy) {
2749 default: llvm_unreachable("Unknown FP format");
2750 case MVT::f32: return &APFloat::IEEEsingle;
2751 case MVT::f64: return &APFloat::IEEEdouble;
2752 case MVT::f80: return &APFloat::x87DoubleExtended;
2753 case MVT::f128: return &APFloat::IEEEquad;
2754 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2758 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2759 SDValue Op = N->getOperand(0);
2760 EVT SrcVT = Op.getValueType();
2761 EVT DstVT = N->getValueType(0);
2762 DebugLoc dl = N->getDebugLoc();
2764 // The following optimization is valid only if every value in SrcVT (when
2765 // treated as signed) is representable in DstVT. Check that the mantissa
2766 // size of DstVT is >= than the number of bits in SrcVT -1.
2767 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2768 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2769 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2770 // Do a signed conversion then adjust the result.
2771 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2772 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2774 // The result of the signed conversion needs adjusting if the 'sign bit' of
2775 // the incoming integer was set. To handle this, we dynamically test to see
2776 // if it is set, and, if so, add a fudge factor.
2778 const uint64_t F32TwoE32 = 0x4F800000ULL;
2779 const uint64_t F32TwoE64 = 0x5F800000ULL;
2780 const uint64_t F32TwoE128 = 0x7F800000ULL;
2783 if (SrcVT == MVT::i32)
2784 FF = APInt(32, F32TwoE32);
2785 else if (SrcVT == MVT::i64)
2786 FF = APInt(32, F32TwoE64);
2787 else if (SrcVT == MVT::i128)
2788 FF = APInt(32, F32TwoE128);
2790 llvm_unreachable("Unsupported UINT_TO_FP!");
2792 // Check whether the sign bit is set.
2794 GetExpandedInteger(Op, Lo, Hi);
2795 SDValue SignSet = DAG.getSetCC(dl,
2796 TLI.getSetCCResultType(Hi.getValueType()),
2797 Hi, DAG.getConstant(0, Hi.getValueType()),
2800 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2801 SDValue FudgePtr = DAG.getConstantPool(
2802 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2803 TLI.getPointerTy());
2805 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2806 SDValue Zero = DAG.getIntPtrConstant(0);
2807 SDValue Four = DAG.getIntPtrConstant(4);
2808 if (TLI.isBigEndian()) std::swap(Zero, Four);
2809 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2811 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2812 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2813 Alignment = std::min(Alignment, 4u);
2815 // Load the value out, extending it from f32 to the destination float type.
2816 // FIXME: Avoid the extend by constructing the right constant pool?
2817 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2819 MachinePointerInfo::getConstantPool(),
2821 false, false, Alignment);
2822 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2825 // Otherwise, use a libcall.
2826 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2827 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2828 "Don't know how to expand this UINT_TO_FP!");
2829 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2832 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2833 DebugLoc dl = N->getDebugLoc();
2834 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2835 cast<AtomicSDNode>(N)->getMemoryVT(),
2837 N->getOperand(1), N->getOperand(2),
2838 cast<AtomicSDNode>(N)->getMemOperand(),
2839 cast<AtomicSDNode>(N)->getOrdering(),
2840 cast<AtomicSDNode>(N)->getSynchScope());
2841 return Swap.getValue(1);
2845 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2846 SDValue InOp0 = N->getOperand(0);
2847 EVT InVT = InOp0.getValueType();
2849 EVT OutVT = N->getValueType(0);
2850 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2851 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2852 unsigned OutNumElems = OutVT.getVectorNumElements();
2853 EVT NOutVTElem = NOutVT.getVectorElementType();
2855 DebugLoc dl = N->getDebugLoc();
2856 SDValue BaseIdx = N->getOperand(1);
2858 SmallVector<SDValue, 8> Ops;
2859 Ops.reserve(OutNumElems);
2860 for (unsigned i = 0; i != OutNumElems; ++i) {
2862 // Extract the element from the original vector.
2863 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2864 BaseIdx, DAG.getIntPtrConstant(i));
2865 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2866 InVT.getVectorElementType(), N->getOperand(0), Index);
2868 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2869 // Insert the converted element to the new vector.
2873 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2877 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2878 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2879 EVT VT = N->getValueType(0);
2880 DebugLoc dl = N->getDebugLoc();
2882 unsigned NumElts = VT.getVectorNumElements();
2883 SmallVector<int, 8> NewMask;
2884 for (unsigned i = 0; i != NumElts; ++i) {
2885 NewMask.push_back(SV->getMaskElt(i));
2888 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2889 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2890 EVT OutVT = V0.getValueType();
2892 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2896 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2897 EVT OutVT = N->getValueType(0);
2898 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2899 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2900 unsigned NumElems = N->getNumOperands();
2901 EVT NOutVTElem = NOutVT.getVectorElementType();
2903 DebugLoc dl = N->getDebugLoc();
2905 SmallVector<SDValue, 8> Ops;
2906 Ops.reserve(NumElems);
2907 for (unsigned i = 0; i != NumElems; ++i) {
2908 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2912 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2915 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2917 DebugLoc dl = N->getDebugLoc();
2919 assert(!N->getOperand(0).getValueType().isVector() &&
2920 "Input must be a scalar");
2922 EVT OutVT = N->getValueType(0);
2923 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2924 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2925 EVT NOutVTElem = NOutVT.getVectorElementType();
2927 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2929 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2932 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
2933 DebugLoc dl = N->getDebugLoc();
2935 EVT OutVT = N->getValueType(0);
2936 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2937 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2939 EVT InElemTy = OutVT.getVectorElementType();
2940 EVT OutElemTy = NOutVT.getVectorElementType();
2942 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
2943 unsigned NumOutElem = NOutVT.getVectorNumElements();
2944 unsigned NumOperands = N->getNumOperands();
2945 assert(NumElem * NumOperands == NumOutElem &&
2946 "Unexpected number of elements");
2948 // Take the elements from the first vector.
2949 SmallVector<SDValue, 8> Ops(NumOutElem);
2950 for (unsigned i = 0; i < NumOperands; ++i) {
2951 SDValue Op = N->getOperand(i);
2952 for (unsigned j = 0; j < NumElem; ++j) {
2953 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2954 InElemTy, Op, DAG.getIntPtrConstant(j));
2955 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
2959 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2962 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
2963 EVT OutVT = N->getValueType(0);
2964 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2965 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2967 EVT NOutVTElem = NOutVT.getVectorElementType();
2969 DebugLoc dl = N->getDebugLoc();
2970 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2972 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2973 NOutVTElem, N->getOperand(1));
2974 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
2975 V0, ConvElem, N->getOperand(2));
2978 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2979 DebugLoc dl = N->getDebugLoc();
2980 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2981 SDValue V1 = N->getOperand(1);
2982 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2983 V0->getValueType(0).getScalarType(), V0, V1);
2985 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
2986 // element types. If this is the case then we need to expand the outgoing
2987 // value and not truncate it.
2988 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
2991 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
2992 DebugLoc dl = N->getDebugLoc();
2993 unsigned NumElems = N->getNumOperands();
2995 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
2997 SmallVector<SDValue, 8> NewOps;
2998 NewOps.reserve(NumElems);
3000 // For each incoming vector
3001 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3002 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3003 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3004 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3006 for (unsigned i=0; i<NumElem; ++i) {
3007 // Extract element from incoming vector
3008 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3009 Incoming, DAG.getIntPtrConstant(i));
3010 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3011 NewOps.push_back(Tr);
3015 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
3016 &NewOps[0], NewOps.size());