1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N));break;
70 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
71 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
72 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
73 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
77 case ISD::UMAX: Res = PromoteIntRes_SimpleIntBinOp(N); break;
78 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
79 case ISD::SIGN_EXTEND_INREG:
80 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
81 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
82 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
83 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
84 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
85 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
87 case ISD::EXTRACT_SUBVECTOR:
88 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
89 case ISD::VECTOR_SHUFFLE:
90 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
91 case ISD::INSERT_VECTOR_ELT:
92 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
93 case ISD::BUILD_VECTOR:
94 Res = PromoteIntRes_BUILD_VECTOR(N); break;
95 case ISD::SCALAR_TO_VECTOR:
96 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
97 case ISD::CONCAT_VECTORS:
98 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
100 case ISD::SIGN_EXTEND:
101 case ISD::ZERO_EXTEND:
102 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
104 case ISD::FP_TO_SINT:
105 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
107 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
114 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
117 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
120 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
123 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
125 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
127 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
129 case ISD::ATOMIC_LOAD:
130 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
132 case ISD::ATOMIC_LOAD_ADD:
133 case ISD::ATOMIC_LOAD_SUB:
134 case ISD::ATOMIC_LOAD_AND:
135 case ISD::ATOMIC_LOAD_OR:
136 case ISD::ATOMIC_LOAD_XOR:
137 case ISD::ATOMIC_LOAD_NAND:
138 case ISD::ATOMIC_LOAD_MIN:
139 case ISD::ATOMIC_LOAD_MAX:
140 case ISD::ATOMIC_LOAD_UMIN:
141 case ISD::ATOMIC_LOAD_UMAX:
142 case ISD::ATOMIC_SWAP:
143 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
145 case ISD::ATOMIC_CMP_SWAP:
146 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
147 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
151 // If the result is null then the sub-method took care of registering it.
153 SetPromotedInteger(SDValue(N, ResNo), Res);
156 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
158 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
159 return GetPromotedInteger(Op);
162 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
163 // Sign-extend the new bits, and continue the assertion.
164 SDValue Op = SExtPromotedInteger(N->getOperand(0));
165 return DAG.getNode(ISD::AssertSext, SDLoc(N),
166 Op.getValueType(), Op, N->getOperand(1));
169 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
170 // Zero the new bits, and continue the assertion.
171 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
172 return DAG.getNode(ISD::AssertZext, SDLoc(N),
173 Op.getValueType(), Op, N->getOperand(1));
176 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
177 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
178 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
179 N->getMemoryVT(), ResVT,
180 N->getChain(), N->getBasePtr(),
181 N->getMemOperand(), N->getOrdering(),
183 // Legalized the chain result - switch anything that used the old chain to
185 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
189 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
190 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
191 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
193 N->getChain(), N->getBasePtr(),
194 Op2, N->getMemOperand(), N->getOrdering(),
196 // Legalized the chain result - switch anything that used the old chain to
198 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
202 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
205 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
206 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
207 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
209 // Only use the result of getSetCCResultType if it is legal,
210 // otherwise just use the promoted result type (NVT).
211 if (!TLI.isTypeLegal(SVT))
214 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
215 SDValue Res = DAG.getAtomicCmpSwap(
216 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
217 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
218 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
220 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
221 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
222 return Res.getValue(1);
225 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
226 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
228 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
229 SDValue Res = DAG.getAtomicCmpSwap(
230 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
231 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
232 N->getFailureOrdering(), N->getSynchScope());
233 // Update the use to N with the newly created Res.
234 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
235 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
240 SDValue InOp = N->getOperand(0);
241 EVT InVT = InOp.getValueType();
242 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
243 EVT OutVT = N->getValueType(0);
244 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
247 switch (getTypeAction(InVT)) {
248 case TargetLowering::TypeLegal:
250 case TargetLowering::TypePromoteInteger:
251 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
252 // The input promotes to the same size. Convert the promoted value.
253 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
255 case TargetLowering::TypeSoftenFloat:
256 // Promote the integer operand by hand.
257 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
258 case TargetLowering::TypePromoteFloat: {
259 // Convert the promoted float by hand.
260 if (NOutVT.bitsEq(NInVT)) {
261 SDValue PromotedOp = GetPromotedFloat(InOp);
262 SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);
263 return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,
264 DAG.getValueType(OutVT));
268 case TargetLowering::TypeExpandInteger:
269 case TargetLowering::TypeExpandFloat:
271 case TargetLowering::TypeScalarizeVector:
272 // Convert the element to an integer and promote it by hand.
273 if (!NOutVT.isVector())
274 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
275 BitConvertToInteger(GetScalarizedVector(InOp)));
277 case TargetLowering::TypeSplitVector: {
278 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
279 // pieces of the input into integers and reassemble in the final type.
281 GetSplitVector(N->getOperand(0), Lo, Hi);
282 Lo = BitConvertToInteger(Lo);
283 Hi = BitConvertToInteger(Hi);
285 if (TLI.isBigEndian())
288 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
289 EVT::getIntegerVT(*DAG.getContext(),
290 NOutVT.getSizeInBits()),
291 JoinIntegers(Lo, Hi));
292 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
294 case TargetLowering::TypeWidenVector:
295 // The input is widened to the same size. Convert to the widened value.
296 // Make sure that the outgoing value is not a vector, because this would
297 // make us bitcast between two vectors which are legalized in different ways.
298 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
299 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
302 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
303 CreateStackStoreLoad(InOp, OutVT));
306 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
307 SDValue Op = GetPromotedInteger(N->getOperand(0));
308 EVT OVT = N->getValueType(0);
309 EVT NVT = Op.getValueType();
312 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
313 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
314 DAG.getConstant(DiffBits, dl, TLI.getShiftAmountTy(NVT)));
317 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
318 // The pair element type may be legal, or may not promote to the same type as
319 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
320 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
321 TLI.getTypeToTransformTo(*DAG.getContext(),
322 N->getValueType(0)), JoinIntegers(N->getOperand(0),
326 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
327 EVT VT = N->getValueType(0);
328 // FIXME there is no actual debug info here
330 // Zero extend things like i1, sign extend everything else. It shouldn't
331 // matter in theory which one we pick, but this tends to give better code?
332 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
333 SDValue Result = DAG.getNode(Opc, dl,
334 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
336 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
340 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
341 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
342 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
343 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
344 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
345 "can only promote integers");
346 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
347 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
348 N->getOperand(1), N->getOperand(2),
349 N->getOperand(3), N->getOperand(4), CvtCode);
352 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
353 // Zero extend to the promoted type and do the count there.
354 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
356 EVT OVT = N->getValueType(0);
357 EVT NVT = Op.getValueType();
358 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
359 // Subtract off the extra leading bits in the bigger type.
361 ISD::SUB, dl, NVT, Op,
362 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(), dl,
366 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
367 // Zero extend to the promoted type and do the count there.
368 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
369 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
372 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
373 SDValue Op = GetPromotedInteger(N->getOperand(0));
374 EVT OVT = N->getValueType(0);
375 EVT NVT = Op.getValueType();
377 if (N->getOpcode() == ISD::CTTZ) {
378 // The count is the same in the promoted type except if the original
379 // value was zero. This can be handled by setting the bit just off
380 // the top of the original type.
381 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
382 OVT.getScalarSizeInBits());
383 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, dl, NVT));
385 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
388 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
390 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
391 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
395 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
396 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
397 unsigned NewOpc = N->getOpcode();
400 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
401 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
402 // and SINT conversions are Custom, there is no way to tell which is
403 // preferable. We choose SINT because that's the right thing on PPC.)
404 if (N->getOpcode() == ISD::FP_TO_UINT &&
405 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
406 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
407 NewOpc = ISD::FP_TO_SINT;
409 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
411 // Assert that the converted value fits in the original type. If it doesn't
412 // (eg: because the value being converted is too big), then the result of the
413 // original operation was undefined anyway, so the assert is still correct.
414 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
415 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
416 DAG.getValueType(N->getValueType(0).getScalarType()));
419 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
420 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
423 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
425 return DAG.getNode(ISD::AssertZext, dl,
426 NVT, Res, DAG.getValueType(N->getValueType(0)));
429 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
430 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
433 if (getTypeAction(N->getOperand(0).getValueType())
434 == TargetLowering::TypePromoteInteger) {
435 SDValue Res = GetPromotedInteger(N->getOperand(0));
436 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
438 // If the result and operand types are the same after promotion, simplify
439 // to an in-register extension.
440 if (NVT == Res.getValueType()) {
441 // The high bits are not guaranteed to be anything. Insert an extend.
442 if (N->getOpcode() == ISD::SIGN_EXTEND)
443 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
444 DAG.getValueType(N->getOperand(0).getValueType()));
445 if (N->getOpcode() == ISD::ZERO_EXTEND)
446 return DAG.getZeroExtendInReg(Res, dl,
447 N->getOperand(0).getValueType().getScalarType());
448 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
453 // Otherwise, just extend the original operand all the way to the larger type.
454 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
457 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
458 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
459 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
460 ISD::LoadExtType ExtType =
461 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
463 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
464 N->getMemoryVT(), N->getMemOperand());
466 // Legalized the chain result - switch anything that used the old chain to
468 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
472 SDValue DAGTypeLegalizer::PromoteIntRes_MLOAD(MaskedLoadSDNode *N) {
473 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
474 SDValue ExtSrc0 = GetPromotedInteger(N->getSrc0());
476 SDValue Mask = N->getMask();
477 EVT NewMaskVT = getSetCCResultType(NVT);
478 if (NewMaskVT != N->getMask().getValueType())
479 Mask = PromoteTargetBoolean(Mask, NewMaskVT);
482 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(),
483 Mask, ExtSrc0, N->getMemoryVT(),
484 N->getMemOperand(), ISD::SEXTLOAD);
485 // Legalized the chain result - switch anything that used the old chain to
487 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
490 /// Promote the overflow flag of an overflowing arithmetic node.
491 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
492 // Simply change the return type of the boolean result.
493 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
494 EVT ValueVTs[] = { N->getValueType(0), NVT };
495 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
496 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
497 DAG.getVTList(ValueVTs), Ops);
499 // Modified the sum result - switch anything that used the old sum to use
501 ReplaceValueWith(SDValue(N, 0), Res);
503 return SDValue(Res.getNode(), 1);
506 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
508 return PromoteIntRes_Overflow(N);
510 // The operation overflowed iff the result in the larger type is not the
511 // sign extension of its truncation to the original type.
512 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
513 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
514 EVT OVT = N->getOperand(0).getValueType();
515 EVT NVT = LHS.getValueType();
518 // Do the arithmetic in the larger type.
519 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
520 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
522 // Calculate the overflow flag: sign extend the arithmetic result from
523 // the original type.
524 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
525 DAG.getValueType(OVT));
526 // Overflowed if and only if this is not equal to Res.
527 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
529 // Use the calculated overflow everywhere.
530 ReplaceValueWith(SDValue(N, 1), Ofl);
535 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
536 // Sign extend the input.
537 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
538 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
539 return DAG.getNode(N->getOpcode(), SDLoc(N),
540 LHS.getValueType(), LHS, RHS);
543 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
544 SDValue LHS = GetPromotedInteger(N->getOperand(1));
545 SDValue RHS = GetPromotedInteger(N->getOperand(2));
546 return DAG.getSelect(SDLoc(N),
547 LHS.getValueType(), N->getOperand(0), LHS, RHS);
550 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
551 SDValue Mask = N->getOperand(0);
552 EVT OpTy = N->getOperand(1).getValueType();
554 // Promote all the way up to the canonical SetCC type.
555 Mask = PromoteTargetBoolean(Mask, OpTy);
556 SDValue LHS = GetPromotedInteger(N->getOperand(1));
557 SDValue RHS = GetPromotedInteger(N->getOperand(2));
558 return DAG.getNode(ISD::VSELECT, SDLoc(N),
559 LHS.getValueType(), Mask, LHS, RHS);
562 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
563 SDValue LHS = GetPromotedInteger(N->getOperand(2));
564 SDValue RHS = GetPromotedInteger(N->getOperand(3));
565 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
566 LHS.getValueType(), N->getOperand(0),
567 N->getOperand(1), LHS, RHS, N->getOperand(4));
570 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
571 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
573 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
575 // Only use the result of getSetCCResultType if it is legal,
576 // otherwise just use the promoted result type (NVT).
577 if (!TLI.isTypeLegal(SVT))
581 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
582 "Vector compare must return a vector result!");
584 SDValue LHS = N->getOperand(0);
585 SDValue RHS = N->getOperand(1);
586 if (LHS.getValueType() != RHS.getValueType()) {
587 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
588 !LHS.getValueType().isVector())
589 LHS = GetPromotedInteger(LHS);
590 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
591 !RHS.getValueType().isVector())
592 RHS = GetPromotedInteger(RHS);
595 // Get the SETCC result using the canonical SETCC type.
596 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
599 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
600 // Convert to the expected type.
601 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
604 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
605 SDValue Res = GetPromotedInteger(N->getOperand(0));
606 SDValue Amt = N->getOperand(1);
607 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
608 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
611 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
612 SDValue Op = GetPromotedInteger(N->getOperand(0));
613 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
614 Op.getValueType(), Op, N->getOperand(1));
617 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
618 // The input may have strange things in the top bits of the registers, but
619 // these operations don't care. They may have weird bits going out, but
620 // that too is okay if they are integer operations.
621 SDValue LHS = GetPromotedInteger(N->getOperand(0));
622 SDValue RHS = GetPromotedInteger(N->getOperand(1));
623 return DAG.getNode(N->getOpcode(), SDLoc(N),
624 LHS.getValueType(), LHS, RHS);
627 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
628 // The input value must be properly sign extended.
629 SDValue Res = SExtPromotedInteger(N->getOperand(0));
630 SDValue Amt = N->getOperand(1);
631 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
632 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
635 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
636 // The input value must be properly zero extended.
637 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
638 SDValue Amt = N->getOperand(1);
639 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
640 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
643 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
644 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
646 SDValue InOp = N->getOperand(0);
649 switch (getTypeAction(InOp.getValueType())) {
650 default: llvm_unreachable("Unknown type action!");
651 case TargetLowering::TypeLegal:
652 case TargetLowering::TypeExpandInteger:
655 case TargetLowering::TypePromoteInteger:
656 Res = GetPromotedInteger(InOp);
658 case TargetLowering::TypeSplitVector:
659 EVT InVT = InOp.getValueType();
660 assert(InVT.isVector() && "Cannot split scalar types");
661 unsigned NumElts = InVT.getVectorNumElements();
662 assert(NumElts == NVT.getVectorNumElements() &&
663 "Dst and Src must have the same number of elements");
664 assert(isPowerOf2_32(NumElts) &&
665 "Promoted vector type must be a power of two");
668 GetSplitVector(InOp, EOp1, EOp2);
670 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
672 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
673 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
675 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
678 // Truncate to NVT instead of VT
679 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
682 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
684 return PromoteIntRes_Overflow(N);
686 // The operation overflowed iff the result in the larger type is not the
687 // zero extension of its truncation to the original type.
688 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
689 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
690 EVT OVT = N->getOperand(0).getValueType();
691 EVT NVT = LHS.getValueType();
694 // Do the arithmetic in the larger type.
695 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
696 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
698 // Calculate the overflow flag: zero extend the arithmetic result from
699 // the original type.
700 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
701 // Overflowed if and only if this is not equal to Res.
702 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
704 // Use the calculated overflow everywhere.
705 ReplaceValueWith(SDValue(N, 1), Ofl);
710 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
711 // Promote the overflow bit trivially.
713 return PromoteIntRes_Overflow(N);
715 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
717 EVT SmallVT = LHS.getValueType();
719 // To determine if the result overflowed in a larger type, we extend the
720 // input to the larger type, do the multiply (checking if it overflows),
721 // then also check the high bits of the result to see if overflow happened
723 if (N->getOpcode() == ISD::SMULO) {
724 LHS = SExtPromotedInteger(LHS);
725 RHS = SExtPromotedInteger(RHS);
727 LHS = ZExtPromotedInteger(LHS);
728 RHS = ZExtPromotedInteger(RHS);
730 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
731 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
733 // Overflow occurred if it occurred in the larger type, or if the high part
734 // of the result does not zero/sign-extend the low part. Check this second
735 // possibility first.
737 if (N->getOpcode() == ISD::UMULO) {
738 // Unsigned overflow occurred if the high part is non-zero.
739 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
740 DAG.getIntPtrConstant(SmallVT.getSizeInBits(),
742 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
743 DAG.getConstant(0, DL, Hi.getValueType()),
746 // Signed overflow occurred if the high part does not sign extend the low.
747 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
748 Mul, DAG.getValueType(SmallVT));
749 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
752 // The only other way for overflow to occur is if the multiplication in the
753 // larger type itself overflowed.
754 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
755 SDValue(Mul.getNode(), 1));
757 // Use the calculated overflow everywhere.
758 ReplaceValueWith(SDValue(N, 1), Overflow);
762 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
763 // Zero extend the input.
764 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
765 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
766 return DAG.getNode(N->getOpcode(), SDLoc(N),
767 LHS.getValueType(), LHS, RHS);
770 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
771 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
772 N->getValueType(0)));
775 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
776 SDValue Chain = N->getOperand(0); // Get the chain.
777 SDValue Ptr = N->getOperand(1); // Get the pointer.
778 EVT VT = N->getValueType(0);
781 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
782 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
783 // The argument is passed as NumRegs registers of type RegVT.
785 SmallVector<SDValue, 8> Parts(NumRegs);
786 for (unsigned i = 0; i < NumRegs; ++i) {
787 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
788 N->getConstantOperandVal(3));
789 Chain = Parts[i].getValue(1);
792 // Handle endianness of the load.
793 if (TLI.isBigEndian())
794 std::reverse(Parts.begin(), Parts.end());
796 // Assemble the parts in the promoted type.
797 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
798 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
799 for (unsigned i = 1; i < NumRegs; ++i) {
800 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
801 // Shift it to the right position and "or" it in.
802 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
803 DAG.getConstant(i*RegVT.getSizeInBits(), dl,
804 TLI.getPointerTy()));
805 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
808 // Modified the chain result - switch anything that used the old chain to
810 ReplaceValueWith(SDValue(N, 1), Chain);
815 //===----------------------------------------------------------------------===//
816 // Integer Operand Promotion
817 //===----------------------------------------------------------------------===//
819 /// PromoteIntegerOperand - This method is called when the specified operand of
820 /// the specified node is found to need promotion. At this point, all of the
821 /// result types of the node are known to be legal, but other operands of the
822 /// node may need promotion or expansion as well as the specified one.
823 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
824 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
825 SDValue Res = SDValue();
827 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
830 switch (N->getOpcode()) {
833 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
834 N->dump(&DAG); dbgs() << "\n";
836 llvm_unreachable("Do not know how to promote this operator's operand!");
838 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
839 case ISD::ATOMIC_STORE:
840 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
842 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
843 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
844 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
845 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
846 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
847 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
848 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
849 case ISD::CONVERT_RNDSAT:
850 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
851 case ISD::INSERT_VECTOR_ELT:
852 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
853 case ISD::SCALAR_TO_VECTOR:
854 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
856 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
857 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
858 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
859 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
860 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
861 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
863 case ISD::MSTORE: Res = PromoteIntOp_MSTORE(cast<MaskedStoreSDNode>(N),
865 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N),
867 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
868 case ISD::FP16_TO_FP:
869 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
870 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
876 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
879 // If the result is null, the sub-method took care of registering results etc.
880 if (!Res.getNode()) return false;
882 // If the result is N, the sub-method updated N in place. Tell the legalizer
884 if (Res.getNode() == N)
887 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
888 "Invalid operand expansion");
890 ReplaceValueWith(SDValue(N, 0), Res);
894 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
895 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
896 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
897 ISD::CondCode CCCode) {
898 // We have to insert explicit sign or zero extends. Note that we could
899 // insert sign extends for ALL conditions, but zero extend is cheaper on
900 // many machines (an AND instead of two shifts), so prefer it.
902 default: llvm_unreachable("Unknown integer comparison!");
905 SDValue OpL = GetPromotedInteger(NewLHS);
906 SDValue OpR = GetPromotedInteger(NewRHS);
908 // We would prefer to promote the comparison operand with sign extension,
909 // if we find the operand is actually to truncate an AssertSext. With this
910 // optimization, we can avoid inserting real truncate instruction, which
911 // is redudant eventually.
912 if (OpL->getOpcode() == ISD::AssertSext &&
913 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
914 OpR->getOpcode() == ISD::AssertSext &&
915 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
919 NewLHS = ZExtPromotedInteger(NewLHS);
920 NewRHS = ZExtPromotedInteger(NewRHS);
928 // ALL of these operations will work if we either sign or zero extend
929 // the operands (including the unsigned comparisons!). Zero extend is
930 // usually a simpler/cheaper operation, so prefer it.
931 NewLHS = ZExtPromotedInteger(NewLHS);
932 NewRHS = ZExtPromotedInteger(NewRHS);
938 NewLHS = SExtPromotedInteger(NewLHS);
939 NewRHS = SExtPromotedInteger(NewRHS);
944 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
945 SDValue Op = GetPromotedInteger(N->getOperand(0));
946 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
949 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
950 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
951 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
952 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
953 N->getOrdering(), N->getSynchScope());
956 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
957 // This should only occur in unusual situations like bitcasting to an
958 // x86_fp80, so just turn it into a store+load
959 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
962 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
963 assert(OpNo == 2 && "Don't know how to promote this operand!");
965 SDValue LHS = N->getOperand(2);
966 SDValue RHS = N->getOperand(3);
967 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
969 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
971 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
972 N->getOperand(1), LHS, RHS, N->getOperand(4)),
976 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
977 assert(OpNo == 1 && "only know how to promote condition");
979 // Promote all the way up to the canonical SetCC type.
980 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
982 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
983 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
984 N->getOperand(2)), 0);
987 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
988 // Since the result type is legal, the operands must promote to it.
989 EVT OVT = N->getOperand(0).getValueType();
990 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
991 SDValue Hi = GetPromotedInteger(N->getOperand(1));
992 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
995 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
996 DAG.getConstant(OVT.getSizeInBits(), dl,
997 TLI.getPointerTy()));
998 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
1001 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
1002 // The vector type is legal but the element type is not. This implies
1003 // that the vector is a power-of-two in length and that the element
1004 // type does not have a strange size (eg: it is not i1).
1005 EVT VecVT = N->getValueType(0);
1006 unsigned NumElts = VecVT.getVectorNumElements();
1007 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
1008 "Legal vector of one illegal element?");
1010 // Promote the inserted value. The type does not need to match the
1011 // vector element type. Check that any extra bits introduced will be
1013 assert(N->getOperand(0).getValueType().getSizeInBits() >=
1014 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1015 "Type of inserted value narrower than vector element type!");
1017 SmallVector<SDValue, 16> NewOps;
1018 for (unsigned i = 0; i < NumElts; ++i)
1019 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
1021 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1024 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
1025 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
1026 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
1027 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
1028 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
1029 "can only promote integer arguments");
1030 SDValue InOp = GetPromotedInteger(N->getOperand(0));
1031 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
1032 N->getOperand(1), N->getOperand(2),
1033 N->getOperand(3), N->getOperand(4), CvtCode);
1036 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
1039 // Promote the inserted value. This is valid because the type does not
1040 // have to match the vector element type.
1042 // Check that any extra bits introduced will be truncated away.
1043 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1044 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1045 "Type of inserted value narrower than vector element type!");
1046 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1047 GetPromotedInteger(N->getOperand(1)),
1052 assert(OpNo == 2 && "Different operand and result vector types?");
1054 // Promote the index.
1055 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1056 TLI.getVectorIdxTy());
1057 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1058 N->getOperand(1), Idx), 0);
1061 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1062 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1063 // the operand in place.
1064 return SDValue(DAG.UpdateNodeOperands(N,
1065 GetPromotedInteger(N->getOperand(0))), 0);
1068 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1069 assert(OpNo == 0 && "Only know how to promote the condition!");
1070 SDValue Cond = N->getOperand(0);
1071 EVT OpTy = N->getOperand(1).getValueType();
1073 // Promote all the way up to the canonical SetCC type.
1074 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1075 Cond = PromoteTargetBoolean(Cond, OpVT);
1077 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1078 N->getOperand(2)), 0);
1081 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1082 assert(OpNo == 0 && "Don't know how to promote this operand!");
1084 SDValue LHS = N->getOperand(0);
1085 SDValue RHS = N->getOperand(1);
1086 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1088 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1089 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1090 N->getOperand(3), N->getOperand(4)), 0);
1093 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1094 assert(OpNo == 0 && "Don't know how to promote this operand!");
1096 SDValue LHS = N->getOperand(0);
1097 SDValue RHS = N->getOperand(1);
1098 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1100 // The CC (#2) is always legal.
1101 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1104 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1105 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1106 ZExtPromotedInteger(N->getOperand(1))), 0);
1109 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1110 SDValue Op = GetPromotedInteger(N->getOperand(0));
1112 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1113 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1114 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1117 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1118 return SDValue(DAG.UpdateNodeOperands(N,
1119 SExtPromotedInteger(N->getOperand(0))), 0);
1122 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1123 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1124 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1127 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1129 // Truncate the value and store the result.
1130 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1131 N->getMemoryVT(), N->getMemOperand());
1134 SDValue DAGTypeLegalizer::PromoteIntOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo){
1136 SDValue DataOp = N->getValue();
1137 EVT DataVT = DataOp.getValueType();
1138 SDValue Mask = N->getMask();
1139 EVT MaskVT = Mask.getValueType();
1142 bool TruncateStore = false;
1143 if (!TLI.isTypeLegal(DataVT)) {
1144 if (getTypeAction(DataVT) == TargetLowering::TypePromoteInteger) {
1145 DataOp = GetPromotedInteger(DataOp);
1146 if (!TLI.isTypeLegal(MaskVT))
1147 Mask = PromoteTargetBoolean(Mask, DataOp.getValueType());
1148 TruncateStore = true;
1151 assert(getTypeAction(DataVT) == TargetLowering::TypeWidenVector &&
1152 "Unexpected data legalization in MSTORE");
1153 DataOp = GetWidenedVector(DataOp);
1155 if (getTypeAction(MaskVT) == TargetLowering::TypeWidenVector)
1156 Mask = GetWidenedVector(Mask);
1158 EVT BoolVT = getSetCCResultType(DataOp.getValueType());
1160 // We can't use ModifyToType() because we should fill the mask with
1162 unsigned WidenNumElts = BoolVT.getVectorNumElements();
1163 unsigned MaskNumElts = MaskVT.getVectorNumElements();
1165 unsigned NumConcat = WidenNumElts / MaskNumElts;
1166 SmallVector<SDValue, 16> Ops(NumConcat);
1167 SDValue ZeroVal = DAG.getConstant(0, dl, MaskVT);
1169 for (unsigned i = 1; i != NumConcat; ++i)
1172 Mask = DAG.getNode(ISD::CONCAT_VECTORS, dl, BoolVT, Ops);
1177 Mask = PromoteTargetBoolean(N->getMask(), DataOp.getValueType());
1178 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), Mask,
1179 N->getMemoryVT(), N->getMemOperand(),
1183 SDValue DAGTypeLegalizer::PromoteIntOp_MLOAD(MaskedLoadSDNode *N, unsigned OpNo){
1184 assert(OpNo == 2 && "Only know how to promote the mask!");
1185 EVT DataVT = N->getValueType(0);
1186 SDValue Mask = PromoteTargetBoolean(N->getOperand(OpNo), DataVT);
1187 SmallVector<SDValue, 4> NewOps(N->op_begin(), N->op_end());
1188 NewOps[OpNo] = Mask;
1189 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
1192 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1193 SDValue Op = GetPromotedInteger(N->getOperand(0));
1194 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1197 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1198 return SDValue(DAG.UpdateNodeOperands(N,
1199 ZExtPromotedInteger(N->getOperand(0))), 0);
1202 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1204 SDValue Op = GetPromotedInteger(N->getOperand(0));
1205 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1206 return DAG.getZeroExtendInReg(Op, dl,
1207 N->getOperand(0).getValueType().getScalarType());
1211 //===----------------------------------------------------------------------===//
1212 // Integer Result Expansion
1213 //===----------------------------------------------------------------------===//
1215 /// ExpandIntegerResult - This method is called when the specified result of the
1216 /// specified node is found to need expansion. At this point, the node may also
1217 /// have invalid operands or may have other results that need promotion, we just
1218 /// know that (at least) one result needs expansion.
1219 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1220 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1222 Lo = Hi = SDValue();
1224 // See if the target wants to custom expand this node.
1225 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1228 switch (N->getOpcode()) {
1231 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1232 N->dump(&DAG); dbgs() << "\n";
1234 llvm_unreachable("Do not know how to expand the result of this operator!");
1236 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1237 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1238 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1239 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1241 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1242 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1243 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1244 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1245 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1247 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1248 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1249 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1250 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1251 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1252 case ISD::CTLZ_ZERO_UNDEF:
1253 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1254 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1255 case ISD::CTTZ_ZERO_UNDEF:
1256 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1257 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1258 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1259 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1260 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1261 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1262 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1263 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1264 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1265 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1266 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1267 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1268 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1269 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1271 case ISD::ATOMIC_LOAD_ADD:
1272 case ISD::ATOMIC_LOAD_SUB:
1273 case ISD::ATOMIC_LOAD_AND:
1274 case ISD::ATOMIC_LOAD_OR:
1275 case ISD::ATOMIC_LOAD_XOR:
1276 case ISD::ATOMIC_LOAD_NAND:
1277 case ISD::ATOMIC_LOAD_MIN:
1278 case ISD::ATOMIC_LOAD_MAX:
1279 case ISD::ATOMIC_LOAD_UMIN:
1280 case ISD::ATOMIC_LOAD_UMAX:
1281 case ISD::ATOMIC_SWAP:
1282 case ISD::ATOMIC_CMP_SWAP: {
1283 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1284 SplitInteger(Tmp.first, Lo, Hi);
1285 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1288 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1289 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1290 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1291 SDValue Tmp = DAG.getAtomicCmpSwap(
1292 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1293 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1294 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1295 AN->getSynchScope());
1297 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1298 // success simply by comparing the loaded value against the ingoing
1300 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1301 N->getOperand(2), ISD::SETEQ);
1303 SplitInteger(Tmp, Lo, Hi);
1304 ReplaceValueWith(SDValue(N, 1), Success);
1305 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1311 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1314 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1317 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1320 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1324 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1327 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1329 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1331 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1334 // If Lo/Hi is null, the sub-method took care of registering results etc.
1336 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1339 /// Lower an atomic node to the appropriate builtin call.
1340 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1341 unsigned Opc = Node->getOpcode();
1342 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1343 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
1344 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
1346 return ExpandChainLibCall(LC, Node, false);
1349 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1350 /// and the shift amount is a constant 'Amt'. Expand the operation.
1351 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1352 SDValue &Lo, SDValue &Hi) {
1354 // Expand the incoming operand to be shifted, so that we have its parts
1356 GetExpandedInteger(N->getOperand(0), InL, InH);
1358 // Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
1359 // splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
1366 EVT NVT = InL.getValueType();
1367 unsigned VTBits = N->getValueType(0).getSizeInBits();
1368 unsigned NVTBits = NVT.getSizeInBits();
1369 EVT ShTy = N->getOperand(1).getValueType();
1371 if (N->getOpcode() == ISD::SHL) {
1373 Lo = Hi = DAG.getConstant(0, DL, NVT);
1374 } else if (Amt > NVTBits) {
1375 Lo = DAG.getConstant(0, DL, NVT);
1376 Hi = DAG.getNode(ISD::SHL, DL,
1377 NVT, InL, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1378 } else if (Amt == NVTBits) {
1379 Lo = DAG.getConstant(0, DL, NVT);
1381 } else if (Amt == 1 &&
1382 TLI.isOperationLegalOrCustom(ISD::ADDC,
1383 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1384 // Emit this X << 1 as X+X.
1385 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1386 SDValue LoOps[2] = { InL, InL };
1387 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1388 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1389 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1391 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, DL, ShTy));
1392 Hi = DAG.getNode(ISD::OR, DL, NVT,
1393 DAG.getNode(ISD::SHL, DL, NVT, InH,
1394 DAG.getConstant(Amt, DL, ShTy)),
1395 DAG.getNode(ISD::SRL, DL, NVT, InL,
1396 DAG.getConstant(NVTBits - Amt, DL, ShTy)));
1401 if (N->getOpcode() == ISD::SRL) {
1403 Lo = DAG.getConstant(0, DL, NVT);
1404 Hi = DAG.getConstant(0, DL, NVT);
1405 } else if (Amt > NVTBits) {
1406 Lo = DAG.getNode(ISD::SRL, DL,
1407 NVT, InH, DAG.getConstant(Amt - NVTBits, DL, ShTy));
1408 Hi = DAG.getConstant(0, DL, NVT);
1409 } else if (Amt == NVTBits) {
1411 Hi = DAG.getConstant(0, DL, NVT);
1413 Lo = DAG.getNode(ISD::OR, DL, NVT,
1414 DAG.getNode(ISD::SRL, DL, NVT, InL,
1415 DAG.getConstant(Amt, DL, ShTy)),
1416 DAG.getNode(ISD::SHL, DL, NVT, InH,
1417 DAG.getConstant(NVTBits - Amt, DL, ShTy)));
1418 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1423 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1425 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1426 DAG.getConstant(NVTBits - 1, DL, ShTy));
1427 } else if (Amt > NVTBits) {
1428 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1429 DAG.getConstant(Amt-NVTBits, DL, ShTy));
1430 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1431 DAG.getConstant(NVTBits - 1, DL, ShTy));
1432 } else if (Amt == NVTBits) {
1434 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1435 DAG.getConstant(NVTBits - 1, DL, ShTy));
1437 Lo = DAG.getNode(ISD::OR, DL, NVT,
1438 DAG.getNode(ISD::SRL, DL, NVT, InL,
1439 DAG.getConstant(Amt, DL, ShTy)),
1440 DAG.getNode(ISD::SHL, DL, NVT, InH,
1441 DAG.getConstant(NVTBits - Amt, DL, ShTy)));
1442 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1446 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1447 /// this shift based on knowledge of the high bit of the shift amount. If we
1448 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1450 bool DAGTypeLegalizer::
1451 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1452 SDValue Amt = N->getOperand(1);
1453 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1454 EVT ShTy = Amt.getValueType();
1455 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1456 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1457 assert(isPowerOf2_32(NVTBits) &&
1458 "Expanded integer type size not a power of two!");
1461 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1462 APInt KnownZero, KnownOne;
1463 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1465 // If we don't know anything about the high bits, exit.
1466 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1469 // Get the incoming operand to be shifted.
1471 GetExpandedInteger(N->getOperand(0), InL, InH);
1473 // If we know that any of the high bits of the shift amount are one, then we
1474 // can do this as a couple of simple shifts.
1475 if (KnownOne.intersects(HighBitMask)) {
1476 // Mask out the high bit, which we know is set.
1477 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1478 DAG.getConstant(~HighBitMask, dl, ShTy));
1480 switch (N->getOpcode()) {
1481 default: llvm_unreachable("Unknown shift");
1483 Lo = DAG.getConstant(0, dl, NVT); // Low part is zero.
1484 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1487 Hi = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1488 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1491 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1492 DAG.getConstant(NVTBits - 1, dl, ShTy));
1493 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1498 // If we know that all of the high bits of the shift amount are zero, then we
1499 // can do this as a couple of simple shifts.
1500 if ((KnownZero & HighBitMask) == HighBitMask) {
1501 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1502 // shift if x is zero. We can use XOR here because x is known to be smaller
1504 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1505 DAG.getConstant(NVTBits - 1, dl, ShTy));
1508 switch (N->getOpcode()) {
1509 default: llvm_unreachable("Unknown shift");
1510 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1512 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1515 // When shifting right the arithmetic for Lo and Hi is swapped.
1516 if (N->getOpcode() != ISD::SHL)
1517 std::swap(InL, InH);
1519 // Use a little trick to get the bits that move from Lo to Hi. First
1520 // shift by one bit.
1521 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, dl, ShTy));
1522 // Then compute the remaining shift with amount-1.
1523 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1525 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1526 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1528 if (N->getOpcode() != ISD::SHL)
1536 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1538 bool DAGTypeLegalizer::
1539 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1540 SDValue Amt = N->getOperand(1);
1541 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1542 EVT ShTy = Amt.getValueType();
1543 unsigned NVTBits = NVT.getSizeInBits();
1544 assert(isPowerOf2_32(NVTBits) &&
1545 "Expanded integer type size not a power of two!");
1548 // Get the incoming operand to be shifted.
1550 GetExpandedInteger(N->getOperand(0), InL, InH);
1552 SDValue NVBitsNode = DAG.getConstant(NVTBits, dl, ShTy);
1553 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1554 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1555 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1556 Amt, NVBitsNode, ISD::SETULT);
1557 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1558 Amt, DAG.getConstant(0, dl, ShTy),
1561 SDValue LoS, HiS, LoL, HiL;
1562 switch (N->getOpcode()) {
1563 default: llvm_unreachable("Unknown shift");
1565 // Short: ShAmt < NVTBits
1566 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1567 HiS = DAG.getNode(ISD::OR, dl, NVT,
1568 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1569 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1571 // Long: ShAmt >= NVTBits
1572 LoL = DAG.getConstant(0, dl, NVT); // Lo part is zero.
1573 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1575 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1576 Hi = DAG.getSelect(dl, NVT, isZero, InH,
1577 DAG.getSelect(dl, NVT, isShort, HiS, HiL));
1580 // Short: ShAmt < NVTBits
1581 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1582 LoS = DAG.getNode(ISD::OR, dl, NVT,
1583 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1584 // FIXME: If Amt is zero, the following shift generates an undefined result
1585 // on some architectures.
1586 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1588 // Long: ShAmt >= NVTBits
1589 HiL = DAG.getConstant(0, dl, NVT); // Hi part is zero.
1590 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1592 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1593 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1594 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1597 // Short: ShAmt < NVTBits
1598 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1599 LoS = DAG.getNode(ISD::OR, dl, NVT,
1600 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1601 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1603 // Long: ShAmt >= NVTBits
1604 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1605 DAG.getConstant(NVTBits - 1, dl, ShTy));
1606 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1608 Lo = DAG.getSelect(dl, NVT, isZero, InL,
1609 DAG.getSelect(dl, NVT, isShort, LoS, LoL));
1610 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1615 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1616 SDValue &Lo, SDValue &Hi) {
1618 // Expand the subcomponents.
1619 SDValue LHSL, LHSH, RHSL, RHSH;
1620 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1621 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1623 EVT NVT = LHSL.getValueType();
1624 SDValue LoOps[2] = { LHSL, RHSL };
1625 SDValue HiOps[3] = { LHSH, RHSH };
1627 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1628 // them. TODO: Teach operation legalization how to expand unsupported
1629 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1630 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1631 // generate a value of this type in the expanded code sequence.
1633 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1634 ISD::ADDC : ISD::SUBC,
1635 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1638 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1639 if (N->getOpcode() == ISD::ADD) {
1640 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1641 HiOps[2] = Lo.getValue(1);
1642 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1644 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1645 HiOps[2] = Lo.getValue(1);
1646 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1652 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1653 ISD::UADDO : ISD::USUBO,
1654 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1656 SDVTList VTList = DAG.getVTList(NVT, NVT);
1657 TargetLoweringBase::BooleanContent BoolType = TLI.getBooleanContents(NVT);
1659 if (N->getOpcode() == ISD::ADD) {
1661 Lo = DAG.getNode(ISD::UADDO, dl, VTList, LoOps);
1662 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1665 Lo = DAG.getNode(ISD::USUBO, dl, VTList, LoOps);
1666 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1668 SDValue OVF = Lo.getValue(1);
1671 case TargetLoweringBase::UndefinedBooleanContent:
1672 OVF = DAG.getNode(ISD::AND, dl, NVT, DAG.getConstant(1, dl, NVT), OVF);
1674 case TargetLoweringBase::ZeroOrOneBooleanContent:
1675 Hi = DAG.getNode(N->getOpcode(), dl, NVT, Hi, OVF);
1677 case TargetLoweringBase::ZeroOrNegativeOneBooleanContent:
1678 Hi = DAG.getNode(RevOpc, dl, NVT, Hi, OVF);
1683 if (N->getOpcode() == ISD::ADD) {
1684 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1685 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1686 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1688 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1689 DAG.getConstant(1, dl, NVT),
1690 DAG.getConstant(0, dl, NVT));
1691 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1693 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1694 DAG.getConstant(1, dl, NVT), Carry1);
1695 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1697 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1698 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1700 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1701 LoOps[0], LoOps[1], ISD::SETULT);
1702 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1703 DAG.getConstant(1, dl, NVT),
1704 DAG.getConstant(0, dl, NVT));
1705 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1709 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1710 SDValue &Lo, SDValue &Hi) {
1711 // Expand the subcomponents.
1712 SDValue LHSL, LHSH, RHSL, RHSH;
1714 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1715 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1716 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1717 SDValue LoOps[2] = { LHSL, RHSL };
1718 SDValue HiOps[3] = { LHSH, RHSH };
1720 if (N->getOpcode() == ISD::ADDC) {
1721 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1722 HiOps[2] = Lo.getValue(1);
1723 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1725 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1726 HiOps[2] = Lo.getValue(1);
1727 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1730 // Legalized the flag result - switch anything that used the old flag to
1732 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1735 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1736 SDValue &Lo, SDValue &Hi) {
1737 // Expand the subcomponents.
1738 SDValue LHSL, LHSH, RHSL, RHSH;
1740 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1741 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1742 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1743 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1744 SDValue HiOps[3] = { LHSH, RHSH };
1746 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1747 HiOps[2] = Lo.getValue(1);
1748 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1750 // Legalized the flag result - switch anything that used the old flag to
1752 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1755 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1756 SDValue &Lo, SDValue &Hi) {
1757 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1758 SplitInteger(Res, Lo, Hi);
1761 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1762 SDValue &Lo, SDValue &Hi) {
1763 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1765 SDValue Op = N->getOperand(0);
1766 if (Op.getValueType().bitsLE(NVT)) {
1767 // The low part is any extension of the input (which degenerates to a copy).
1768 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1769 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1771 // For example, extension of an i48 to an i64. The operand type necessarily
1772 // promotes to the result type, so will end up being expanded too.
1773 assert(getTypeAction(Op.getValueType()) ==
1774 TargetLowering::TypePromoteInteger &&
1775 "Only know how to promote this result!");
1776 SDValue Res = GetPromotedInteger(Op);
1777 assert(Res.getValueType() == N->getValueType(0) &&
1778 "Operand over promoted?");
1779 // Split the promoted operand. This will simplify when it is expanded.
1780 SplitInteger(Res, Lo, Hi);
1784 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1785 SDValue &Lo, SDValue &Hi) {
1787 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1788 EVT NVT = Lo.getValueType();
1789 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1790 unsigned NVTBits = NVT.getSizeInBits();
1791 unsigned EVTBits = EVT.getSizeInBits();
1793 if (NVTBits < EVTBits) {
1794 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1795 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1796 EVTBits - NVTBits)));
1798 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1799 // The high part replicates the sign bit of Lo, make it explicit.
1800 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1801 DAG.getConstant(NVTBits - 1, dl, TLI.getPointerTy()));
1805 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1806 SDValue &Lo, SDValue &Hi) {
1808 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1809 EVT NVT = Lo.getValueType();
1810 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1811 unsigned NVTBits = NVT.getSizeInBits();
1812 unsigned EVTBits = EVT.getSizeInBits();
1814 if (NVTBits < EVTBits) {
1815 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1816 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1817 EVTBits - NVTBits)));
1819 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1820 // The high part must be zero, make it explicit.
1821 Hi = DAG.getConstant(0, dl, NVT);
1825 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1826 SDValue &Lo, SDValue &Hi) {
1828 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1829 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1830 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1833 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1834 SDValue &Lo, SDValue &Hi) {
1835 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1836 unsigned NBitWidth = NVT.getSizeInBits();
1837 auto Constant = cast<ConstantSDNode>(N);
1838 const APInt &Cst = Constant->getAPIntValue();
1839 bool IsTarget = Constant->isTargetOpcode();
1840 bool IsOpaque = Constant->isOpaque();
1842 Lo = DAG.getConstant(Cst.trunc(NBitWidth), dl, NVT, IsTarget, IsOpaque);
1843 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), dl, NVT, IsTarget,
1847 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1848 SDValue &Lo, SDValue &Hi) {
1850 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1851 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1852 EVT NVT = Lo.getValueType();
1854 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1855 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1857 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1858 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1860 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1861 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1862 DAG.getConstant(NVT.getSizeInBits(), dl,
1864 Hi = DAG.getConstant(0, dl, NVT);
1867 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1868 SDValue &Lo, SDValue &Hi) {
1870 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1871 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1872 EVT NVT = Lo.getValueType();
1873 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1874 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1875 Hi = DAG.getConstant(0, dl, NVT);
1878 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1879 SDValue &Lo, SDValue &Hi) {
1881 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1882 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1883 EVT NVT = Lo.getValueType();
1885 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1886 DAG.getConstant(0, dl, NVT), ISD::SETNE);
1888 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1889 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1891 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1892 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1893 DAG.getConstant(NVT.getSizeInBits(), dl,
1895 Hi = DAG.getConstant(0, dl, NVT);
1898 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1901 EVT VT = N->getValueType(0);
1903 SDValue Op = N->getOperand(0);
1904 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1905 Op = GetPromotedFloat(Op);
1907 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1908 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1909 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1914 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1917 EVT VT = N->getValueType(0);
1919 SDValue Op = N->getOperand(0);
1920 if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)
1921 Op = GetPromotedFloat(Op);
1923 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1924 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1925 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1930 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1931 SDValue &Lo, SDValue &Hi) {
1932 if (ISD::isNormalLoad(N)) {
1933 ExpandRes_NormalLoad(N, Lo, Hi);
1937 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1939 EVT VT = N->getValueType(0);
1940 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1941 SDValue Ch = N->getChain();
1942 SDValue Ptr = N->getBasePtr();
1943 ISD::LoadExtType ExtType = N->getExtensionType();
1944 unsigned Alignment = N->getAlignment();
1945 bool isVolatile = N->isVolatile();
1946 bool isNonTemporal = N->isNonTemporal();
1947 bool isInvariant = N->isInvariant();
1948 AAMDNodes AAInfo = N->getAAInfo();
1951 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1953 if (N->getMemoryVT().bitsLE(NVT)) {
1954 EVT MemVT = N->getMemoryVT();
1956 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1957 MemVT, isVolatile, isNonTemporal, isInvariant,
1960 // Remember the chain.
1961 Ch = Lo.getValue(1);
1963 if (ExtType == ISD::SEXTLOAD) {
1964 // The high part is obtained by SRA'ing all but one of the bits of the
1966 unsigned LoSize = Lo.getValueType().getSizeInBits();
1967 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1968 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy()));
1969 } else if (ExtType == ISD::ZEXTLOAD) {
1970 // The high part is just a zero.
1971 Hi = DAG.getConstant(0, dl, NVT);
1973 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1974 // The high part is undefined.
1975 Hi = DAG.getUNDEF(NVT);
1977 } else if (TLI.isLittleEndian()) {
1978 // Little-endian - low bits are at low addresses.
1979 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1980 isVolatile, isNonTemporal, isInvariant, Alignment,
1983 unsigned ExcessBits =
1984 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1985 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1987 // Increment the pointer to the other half.
1988 unsigned IncrementSize = NVT.getSizeInBits()/8;
1989 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1990 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
1991 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1992 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1993 isVolatile, isNonTemporal, isInvariant,
1994 MinAlign(Alignment, IncrementSize), AAInfo);
1996 // Build a factor node to remember that this load is independent of the
1998 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2001 // Big-endian - high bits are at low addresses. Favor aligned loads at
2002 // the cost of some bit-fiddling.
2003 EVT MemVT = N->getMemoryVT();
2004 unsigned EBytes = MemVT.getStoreSize();
2005 unsigned IncrementSize = NVT.getSizeInBits()/8;
2006 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2008 // Load both the high bits and maybe some of the low bits.
2009 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
2010 EVT::getIntegerVT(*DAG.getContext(),
2011 MemVT.getSizeInBits() - ExcessBits),
2012 isVolatile, isNonTemporal, isInvariant, Alignment,
2015 // Increment the pointer to the other half.
2016 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2017 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2018 // Load the rest of the low bits.
2019 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
2020 N->getPointerInfo().getWithOffset(IncrementSize),
2021 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2022 isVolatile, isNonTemporal, isInvariant,
2023 MinAlign(Alignment, IncrementSize), AAInfo);
2025 // Build a factor node to remember that this load is independent of the
2027 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2030 if (ExcessBits < NVT.getSizeInBits()) {
2031 // Transfer low bits from the bottom of Hi to the top of Lo.
2032 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
2033 DAG.getNode(ISD::SHL, dl, NVT, Hi,
2034 DAG.getConstant(ExcessBits, dl,
2035 TLI.getPointerTy())));
2036 // Move high bits to the right position in Hi.
2037 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
2039 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2040 TLI.getPointerTy()));
2044 // Legalized the chain result - switch anything that used the old chain to
2046 ReplaceValueWith(SDValue(N, 1), Ch);
2049 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
2050 SDValue &Lo, SDValue &Hi) {
2052 SDValue LL, LH, RL, RH;
2053 GetExpandedInteger(N->getOperand(0), LL, LH);
2054 GetExpandedInteger(N->getOperand(1), RL, RH);
2055 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
2056 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
2059 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
2060 SDValue &Lo, SDValue &Hi) {
2061 EVT VT = N->getValueType(0);
2062 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2065 SDValue LL, LH, RL, RH;
2066 GetExpandedInteger(N->getOperand(0), LL, LH);
2067 GetExpandedInteger(N->getOperand(1), RL, RH);
2069 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2072 // If nothing else, we can make a libcall.
2073 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2075 LC = RTLIB::MUL_I16;
2076 else if (VT == MVT::i32)
2077 LC = RTLIB::MUL_I32;
2078 else if (VT == MVT::i64)
2079 LC = RTLIB::MUL_I64;
2080 else if (VT == MVT::i128)
2081 LC = RTLIB::MUL_I128;
2082 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2084 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2085 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2090 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2091 SDValue &Lo, SDValue &Hi) {
2092 SDValue LHS = Node->getOperand(0);
2093 SDValue RHS = Node->getOperand(1);
2096 // Expand the result by simply replacing it with the equivalent
2097 // non-overflow-checking operation.
2098 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2099 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2101 SplitInteger(Sum, Lo, Hi);
2103 // Compute the overflow.
2105 // LHSSign -> LHS >= 0
2106 // RHSSign -> RHS >= 0
2107 // SumSign -> Sum >= 0
2110 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2112 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2114 EVT OType = Node->getValueType(1);
2115 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
2117 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2118 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2119 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2120 Node->getOpcode() == ISD::SADDO ?
2121 ISD::SETEQ : ISD::SETNE);
2123 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2124 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2126 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2128 // Use the calculated overflow everywhere.
2129 ReplaceValueWith(SDValue(Node, 1), Cmp);
2132 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2133 SDValue &Lo, SDValue &Hi) {
2134 EVT VT = N->getValueType(0);
2137 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2139 LC = RTLIB::SDIV_I16;
2140 else if (VT == MVT::i32)
2141 LC = RTLIB::SDIV_I32;
2142 else if (VT == MVT::i64)
2143 LC = RTLIB::SDIV_I64;
2144 else if (VT == MVT::i128)
2145 LC = RTLIB::SDIV_I128;
2146 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2148 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2149 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2152 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2153 SDValue &Lo, SDValue &Hi) {
2154 EVT VT = N->getValueType(0);
2157 // If we can emit an efficient shift operation, do so now. Check to see if
2158 // the RHS is a constant.
2159 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2160 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2162 // If we can determine that the high bit of the shift is zero or one, even if
2163 // the low bits are variable, emit this shift in an optimized form.
2164 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2167 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2169 if (N->getOpcode() == ISD::SHL) {
2170 PartsOpc = ISD::SHL_PARTS;
2171 } else if (N->getOpcode() == ISD::SRL) {
2172 PartsOpc = ISD::SRL_PARTS;
2174 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2175 PartsOpc = ISD::SRA_PARTS;
2178 // Next check to see if the target supports this SHL_PARTS operation or if it
2179 // will custom expand it.
2180 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2181 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2182 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2183 Action == TargetLowering::Custom) {
2184 // Expand the subcomponents.
2186 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2187 EVT VT = LHSL.getValueType();
2189 // If the shift amount operand is coming from a vector legalization it may
2190 // have an illegal type. Fix that first by casting the operand, otherwise
2191 // the new SHL_PARTS operation would need further legalization.
2192 SDValue ShiftOp = N->getOperand(1);
2193 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2194 assert(ShiftTy.getScalarType().getSizeInBits() >=
2195 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2196 "ShiftAmountTy is too small to cover the range of this type!");
2197 if (ShiftOp.getValueType() != ShiftTy)
2198 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2200 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2201 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2202 Hi = Lo.getValue(1);
2206 // Otherwise, emit a libcall.
2207 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2209 if (N->getOpcode() == ISD::SHL) {
2210 isSigned = false; /*sign irrelevant*/
2212 LC = RTLIB::SHL_I16;
2213 else if (VT == MVT::i32)
2214 LC = RTLIB::SHL_I32;
2215 else if (VT == MVT::i64)
2216 LC = RTLIB::SHL_I64;
2217 else if (VT == MVT::i128)
2218 LC = RTLIB::SHL_I128;
2219 } else if (N->getOpcode() == ISD::SRL) {
2222 LC = RTLIB::SRL_I16;
2223 else if (VT == MVT::i32)
2224 LC = RTLIB::SRL_I32;
2225 else if (VT == MVT::i64)
2226 LC = RTLIB::SRL_I64;
2227 else if (VT == MVT::i128)
2228 LC = RTLIB::SRL_I128;
2230 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2233 LC = RTLIB::SRA_I16;
2234 else if (VT == MVT::i32)
2235 LC = RTLIB::SRA_I32;
2236 else if (VT == MVT::i64)
2237 LC = RTLIB::SRA_I64;
2238 else if (VT == MVT::i128)
2239 LC = RTLIB::SRA_I128;
2242 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2243 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2244 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2249 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2250 llvm_unreachable("Unsupported shift!");
2253 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2254 SDValue &Lo, SDValue &Hi) {
2255 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2257 SDValue Op = N->getOperand(0);
2258 if (Op.getValueType().bitsLE(NVT)) {
2259 // The low part is sign extension of the input (degenerates to a copy).
2260 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2261 // The high part is obtained by SRA'ing all but one of the bits of low part.
2262 unsigned LoSize = NVT.getSizeInBits();
2263 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2264 DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy()));
2266 // For example, extension of an i48 to an i64. The operand type necessarily
2267 // promotes to the result type, so will end up being expanded too.
2268 assert(getTypeAction(Op.getValueType()) ==
2269 TargetLowering::TypePromoteInteger &&
2270 "Only know how to promote this result!");
2271 SDValue Res = GetPromotedInteger(Op);
2272 assert(Res.getValueType() == N->getValueType(0) &&
2273 "Operand over promoted?");
2274 // Split the promoted operand. This will simplify when it is expanded.
2275 SplitInteger(Res, Lo, Hi);
2276 unsigned ExcessBits =
2277 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2278 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2279 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2284 void DAGTypeLegalizer::
2285 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2287 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2288 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2290 if (EVT.bitsLE(Lo.getValueType())) {
2291 // sext_inreg the low part if needed.
2292 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2295 // The high part gets the sign extension from the lo-part. This handles
2296 // things like sextinreg V:i64 from i8.
2297 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2298 DAG.getConstant(Hi.getValueType().getSizeInBits() - 1, dl,
2299 TLI.getPointerTy()));
2301 // For example, extension of an i48 to an i64. Leave the low part alone,
2302 // sext_inreg the high part.
2303 unsigned ExcessBits =
2304 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2305 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2306 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2311 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2312 SDValue &Lo, SDValue &Hi) {
2313 EVT VT = N->getValueType(0);
2316 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2318 LC = RTLIB::SREM_I16;
2319 else if (VT == MVT::i32)
2320 LC = RTLIB::SREM_I32;
2321 else if (VT == MVT::i64)
2322 LC = RTLIB::SREM_I64;
2323 else if (VT == MVT::i128)
2324 LC = RTLIB::SREM_I128;
2325 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2327 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2328 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2331 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2332 SDValue &Lo, SDValue &Hi) {
2333 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2335 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2336 Hi = DAG.getNode(ISD::SRL, dl,
2337 N->getOperand(0).getValueType(), N->getOperand(0),
2338 DAG.getConstant(NVT.getSizeInBits(), dl,
2339 TLI.getPointerTy()));
2340 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2343 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2344 SDValue &Lo, SDValue &Hi) {
2345 SDValue LHS = N->getOperand(0);
2346 SDValue RHS = N->getOperand(1);
2349 // Expand the result by simply replacing it with the equivalent
2350 // non-overflow-checking operation.
2351 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2352 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2354 SplitInteger(Sum, Lo, Hi);
2356 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2357 // overflows iff a - b > a.
2358 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2359 N->getOpcode () == ISD::UADDO ?
2360 ISD::SETULT : ISD::SETUGT);
2362 // Use the calculated overflow everywhere.
2363 ReplaceValueWith(SDValue(N, 1), Ofl);
2366 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2367 SDValue &Lo, SDValue &Hi) {
2368 EVT VT = N->getValueType(0);
2371 // A divide for UMULO should be faster than a function call.
2372 if (N->getOpcode() == ISD::UMULO) {
2373 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2375 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2376 SplitInteger(MUL, Lo, Hi);
2378 // A divide for UMULO will be faster than a function call. Select to
2379 // make sure we aren't using 0.
2380 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2381 RHS, DAG.getConstant(0, dl, VT), ISD::SETEQ);
2382 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2383 DAG.getConstant(1, dl, VT), RHS);
2384 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2385 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2387 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2388 DAG.getConstant(0, dl, N->getValueType(1)),
2390 ReplaceValueWith(SDValue(N, 1), Overflow);
2394 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2395 EVT PtrVT = TLI.getPointerTy();
2396 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2398 // Replace this with a libcall that will check overflow.
2399 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2401 LC = RTLIB::MULO_I32;
2402 else if (VT == MVT::i64)
2403 LC = RTLIB::MULO_I64;
2404 else if (VT == MVT::i128)
2405 LC = RTLIB::MULO_I128;
2406 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2408 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2409 // Temporary for the overflow value, default it to zero.
2410 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2411 DAG.getConstant(0, dl, PtrVT), Temp,
2412 MachinePointerInfo(), false, false, 0);
2414 TargetLowering::ArgListTy Args;
2415 TargetLowering::ArgListEntry Entry;
2416 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2417 EVT ArgVT = N->getOperand(i).getValueType();
2418 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2419 Entry.Node = N->getOperand(i);
2421 Entry.isSExt = true;
2422 Entry.isZExt = false;
2423 Args.push_back(Entry);
2426 // Also pass the address of the overflow check.
2428 Entry.Ty = PtrTy->getPointerTo();
2429 Entry.isSExt = true;
2430 Entry.isZExt = false;
2431 Args.push_back(Entry);
2433 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2435 TargetLowering::CallLoweringInfo CLI(DAG);
2436 CLI.setDebugLoc(dl).setChain(Chain)
2437 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2440 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2442 SplitInteger(CallInfo.first, Lo, Hi);
2443 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2444 MachinePointerInfo(), false, false, false, 0);
2445 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2446 DAG.getConstant(0, dl, PtrVT),
2448 // Use the overflow from the libcall everywhere.
2449 ReplaceValueWith(SDValue(N, 1), Ofl);
2452 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2453 SDValue &Lo, SDValue &Hi) {
2454 EVT VT = N->getValueType(0);
2457 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2459 LC = RTLIB::UDIV_I16;
2460 else if (VT == MVT::i32)
2461 LC = RTLIB::UDIV_I32;
2462 else if (VT == MVT::i64)
2463 LC = RTLIB::UDIV_I64;
2464 else if (VT == MVT::i128)
2465 LC = RTLIB::UDIV_I128;
2466 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2468 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2469 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2472 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2473 SDValue &Lo, SDValue &Hi) {
2474 EVT VT = N->getValueType(0);
2477 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2479 LC = RTLIB::UREM_I16;
2480 else if (VT == MVT::i32)
2481 LC = RTLIB::UREM_I32;
2482 else if (VT == MVT::i64)
2483 LC = RTLIB::UREM_I64;
2484 else if (VT == MVT::i128)
2485 LC = RTLIB::UREM_I128;
2486 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2488 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2489 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2492 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2493 SDValue &Lo, SDValue &Hi) {
2494 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2496 SDValue Op = N->getOperand(0);
2497 if (Op.getValueType().bitsLE(NVT)) {
2498 // The low part is zero extension of the input (degenerates to a copy).
2499 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2500 Hi = DAG.getConstant(0, dl, NVT); // The high part is just a zero.
2502 // For example, extension of an i48 to an i64. The operand type necessarily
2503 // promotes to the result type, so will end up being expanded too.
2504 assert(getTypeAction(Op.getValueType()) ==
2505 TargetLowering::TypePromoteInteger &&
2506 "Only know how to promote this result!");
2507 SDValue Res = GetPromotedInteger(Op);
2508 assert(Res.getValueType() == N->getValueType(0) &&
2509 "Operand over promoted?");
2510 // Split the promoted operand. This will simplify when it is expanded.
2511 SplitInteger(Res, Lo, Hi);
2512 unsigned ExcessBits =
2513 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2514 Hi = DAG.getZeroExtendInReg(Hi, dl,
2515 EVT::getIntegerVT(*DAG.getContext(),
2520 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2521 SDValue &Lo, SDValue &Hi) {
2523 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2524 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2525 SDValue Zero = DAG.getConstant(0, dl, VT);
2526 SDValue Swap = DAG.getAtomicCmpSwap(
2527 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2528 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2529 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2530 cast<AtomicSDNode>(N)->getOrdering(),
2531 cast<AtomicSDNode>(N)->getOrdering(),
2532 cast<AtomicSDNode>(N)->getSynchScope());
2534 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2535 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2538 //===----------------------------------------------------------------------===//
2539 // Integer Operand Expansion
2540 //===----------------------------------------------------------------------===//
2542 /// ExpandIntegerOperand - This method is called when the specified operand of
2543 /// the specified node is found to need expansion. At this point, all of the
2544 /// result types of the node are known to be legal, but other operands of the
2545 /// node may need promotion or expansion as well as the specified one.
2546 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2547 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2548 SDValue Res = SDValue();
2550 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2553 switch (N->getOpcode()) {
2556 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2557 N->dump(&DAG); dbgs() << "\n";
2559 llvm_unreachable("Do not know how to expand this operator's operand!");
2561 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2562 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2563 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2564 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2565 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2566 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2567 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2568 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2569 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2570 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2571 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2572 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2578 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2579 case ISD::RETURNADDR:
2580 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2582 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2585 // If the result is null, the sub-method took care of registering results etc.
2586 if (!Res.getNode()) return false;
2588 // If the result is N, the sub-method updated N in place. Tell the legalizer
2590 if (Res.getNode() == N)
2593 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2594 "Invalid operand expansion");
2596 ReplaceValueWith(SDValue(N, 0), Res);
2600 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2601 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2602 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2604 ISD::CondCode &CCCode,
2606 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2607 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2608 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2610 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2611 if (RHSLo == RHSHi) {
2612 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2613 if (RHSCST->isAllOnesValue()) {
2614 // Equality comparison to -1.
2615 NewLHS = DAG.getNode(ISD::AND, dl,
2616 LHSLo.getValueType(), LHSLo, LHSHi);
2623 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2624 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2625 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2626 NewRHS = DAG.getConstant(0, dl, NewLHS.getValueType());
2630 // If this is a comparison of the sign bit, just look at the top part.
2632 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2633 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2634 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2640 // FIXME: This generated code sucks.
2641 ISD::CondCode LowCC;
2643 default: llvm_unreachable("Unknown integer setcc!");
2645 case ISD::SETULT: LowCC = ISD::SETULT; break;
2647 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2649 case ISD::SETULE: LowCC = ISD::SETULE; break;
2651 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2654 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2655 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2656 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2658 // NOTE: on targets without efficient SELECT of bools, we can always use
2659 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2660 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2663 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2664 TLI.isTypeLegal(RHSLo.getValueType()))
2665 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2666 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2667 if (!Tmp1.getNode())
2668 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2669 LHSLo, RHSLo, LowCC);
2670 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2671 TLI.isTypeLegal(RHSHi.getValueType()))
2672 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2673 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2674 if (!Tmp2.getNode())
2675 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2676 getSetCCResultType(LHSHi.getValueType()),
2677 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2679 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2680 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2681 if ((Tmp1C && Tmp1C->isNullValue()) ||
2682 (Tmp2C && Tmp2C->isNullValue() &&
2683 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2684 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2685 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2686 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2687 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2688 // low part is known false, returns high part.
2689 // For LE / GE, if high part is known false, ignore the low part.
2690 // For LT / GT, if high part is known true, ignore the low part.
2696 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2697 LHSHi, RHSHi, ISD::SETEQ, false,
2698 DagCombineInfo, dl);
2699 if (!NewLHS.getNode())
2700 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2701 LHSHi, RHSHi, ISD::SETEQ);
2702 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2703 NewLHS, Tmp1, Tmp2);
2707 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2708 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2709 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2710 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2712 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2713 // against zero to select between true and false values.
2714 if (!NewRHS.getNode()) {
2715 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2716 CCCode = ISD::SETNE;
2719 // Update N to have the operands specified.
2720 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2721 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2722 N->getOperand(4)), 0);
2725 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2726 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2727 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2728 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2730 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2731 // against zero to select between true and false values.
2732 if (!NewRHS.getNode()) {
2733 NewRHS = DAG.getConstant(0, SDLoc(N), NewLHS.getValueType());
2734 CCCode = ISD::SETNE;
2737 // Update N to have the operands specified.
2738 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2739 N->getOperand(2), N->getOperand(3),
2740 DAG.getCondCode(CCCode)), 0);
2743 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2744 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2745 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2746 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2748 // If ExpandSetCCOperands returned a scalar, use it.
2749 if (!NewRHS.getNode()) {
2750 assert(NewLHS.getValueType() == N->getValueType(0) &&
2751 "Unexpected setcc expansion!");
2755 // Otherwise, update N to have the operands specified.
2756 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2757 DAG.getCondCode(CCCode)), 0);
2760 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2761 // The value being shifted is legal, but the shift amount is too big.
2762 // It follows that either the result of the shift is undefined, or the
2763 // upper half of the shift amount is zero. Just use the lower half.
2765 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2766 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2769 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2770 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2771 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2772 // constant to valid type.
2774 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2775 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2778 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2779 SDValue Op = N->getOperand(0);
2780 EVT DstVT = N->getValueType(0);
2781 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2782 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2783 "Don't know how to expand this SINT_TO_FP!");
2784 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2787 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2788 if (ISD::isNormalStore(N))
2789 return ExpandOp_NormalStore(N, OpNo);
2791 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2792 assert(OpNo == 1 && "Can only expand the stored value so far");
2794 EVT VT = N->getOperand(1).getValueType();
2795 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2796 SDValue Ch = N->getChain();
2797 SDValue Ptr = N->getBasePtr();
2798 unsigned Alignment = N->getAlignment();
2799 bool isVolatile = N->isVolatile();
2800 bool isNonTemporal = N->isNonTemporal();
2801 AAMDNodes AAInfo = N->getAAInfo();
2805 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2807 if (N->getMemoryVT().bitsLE(NVT)) {
2808 GetExpandedInteger(N->getValue(), Lo, Hi);
2809 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2810 N->getMemoryVT(), isVolatile, isNonTemporal,
2814 if (TLI.isLittleEndian()) {
2815 // Little-endian - low bits are at low addresses.
2816 GetExpandedInteger(N->getValue(), Lo, Hi);
2818 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2819 isVolatile, isNonTemporal, Alignment, AAInfo);
2821 unsigned ExcessBits =
2822 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2823 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2825 // Increment the pointer to the other half.
2826 unsigned IncrementSize = NVT.getSizeInBits()/8;
2827 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2828 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2829 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2830 N->getPointerInfo().getWithOffset(IncrementSize),
2831 NEVT, isVolatile, isNonTemporal,
2832 MinAlign(Alignment, IncrementSize), AAInfo);
2833 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2836 // Big-endian - high bits are at low addresses. Favor aligned stores at
2837 // the cost of some bit-fiddling.
2838 GetExpandedInteger(N->getValue(), Lo, Hi);
2840 EVT ExtVT = N->getMemoryVT();
2841 unsigned EBytes = ExtVT.getStoreSize();
2842 unsigned IncrementSize = NVT.getSizeInBits()/8;
2843 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2844 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2845 ExtVT.getSizeInBits() - ExcessBits);
2847 if (ExcessBits < NVT.getSizeInBits()) {
2848 // Transfer high bits from the top of Lo to the bottom of Hi.
2849 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2850 DAG.getConstant(NVT.getSizeInBits() - ExcessBits, dl,
2851 TLI.getPointerTy()));
2852 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2853 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2854 DAG.getConstant(ExcessBits, dl,
2855 TLI.getPointerTy())));
2858 // Store both the high bits and maybe some of the low bits.
2859 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2860 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2862 // Increment the pointer to the other half.
2863 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2864 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
2865 // Store the lowest ExcessBits bits in the second half.
2866 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2867 N->getPointerInfo().getWithOffset(IncrementSize),
2868 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2869 isVolatile, isNonTemporal,
2870 MinAlign(Alignment, IncrementSize), AAInfo);
2871 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2874 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2876 GetExpandedInteger(N->getOperand(0), InL, InH);
2877 // Just truncate the low part of the source.
2878 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2881 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2882 SDValue Op = N->getOperand(0);
2883 EVT SrcVT = Op.getValueType();
2884 EVT DstVT = N->getValueType(0);
2887 // The following optimization is valid only if every value in SrcVT (when
2888 // treated as signed) is representable in DstVT. Check that the mantissa
2889 // size of DstVT is >= than the number of bits in SrcVT -1.
2890 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2891 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2892 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2893 // Do a signed conversion then adjust the result.
2894 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2895 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2897 // The result of the signed conversion needs adjusting if the 'sign bit' of
2898 // the incoming integer was set. To handle this, we dynamically test to see
2899 // if it is set, and, if so, add a fudge factor.
2901 const uint64_t F32TwoE32 = 0x4F800000ULL;
2902 const uint64_t F32TwoE64 = 0x5F800000ULL;
2903 const uint64_t F32TwoE128 = 0x7F800000ULL;
2906 if (SrcVT == MVT::i32)
2907 FF = APInt(32, F32TwoE32);
2908 else if (SrcVT == MVT::i64)
2909 FF = APInt(32, F32TwoE64);
2910 else if (SrcVT == MVT::i128)
2911 FF = APInt(32, F32TwoE128);
2913 llvm_unreachable("Unsupported UINT_TO_FP!");
2915 // Check whether the sign bit is set.
2917 GetExpandedInteger(Op, Lo, Hi);
2918 SDValue SignSet = DAG.getSetCC(dl,
2919 getSetCCResultType(Hi.getValueType()),
2921 DAG.getConstant(0, dl, Hi.getValueType()),
2924 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2925 SDValue FudgePtr = DAG.getConstantPool(
2926 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2927 TLI.getPointerTy());
2929 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2930 SDValue Zero = DAG.getIntPtrConstant(0, dl);
2931 SDValue Four = DAG.getIntPtrConstant(4, dl);
2932 if (TLI.isBigEndian()) std::swap(Zero, Four);
2933 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2935 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2936 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2938 Alignment = std::min(Alignment, 4u);
2940 // Load the value out, extending it from f32 to the destination float type.
2941 // FIXME: Avoid the extend by constructing the right constant pool?
2942 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2944 MachinePointerInfo::getConstantPool(),
2946 false, false, false, Alignment);
2947 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2950 // Otherwise, use a libcall.
2951 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2952 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2953 "Don't know how to expand this UINT_TO_FP!");
2954 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2957 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2959 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2960 cast<AtomicSDNode>(N)->getMemoryVT(),
2962 N->getOperand(1), N->getOperand(2),
2963 cast<AtomicSDNode>(N)->getMemOperand(),
2964 cast<AtomicSDNode>(N)->getOrdering(),
2965 cast<AtomicSDNode>(N)->getSynchScope());
2966 return Swap.getValue(1);
2970 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2971 SDValue InOp0 = N->getOperand(0);
2972 EVT InVT = InOp0.getValueType();
2974 EVT OutVT = N->getValueType(0);
2975 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2976 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2977 unsigned OutNumElems = OutVT.getVectorNumElements();
2978 EVT NOutVTElem = NOutVT.getVectorElementType();
2981 SDValue BaseIdx = N->getOperand(1);
2983 SmallVector<SDValue, 8> Ops;
2984 Ops.reserve(OutNumElems);
2985 for (unsigned i = 0; i != OutNumElems; ++i) {
2987 // Extract the element from the original vector.
2988 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2989 BaseIdx, DAG.getConstant(i, dl, BaseIdx.getValueType()));
2990 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2991 InVT.getVectorElementType(), N->getOperand(0), Index);
2993 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2994 // Insert the converted element to the new vector.
2998 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3002 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
3003 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
3004 EVT VT = N->getValueType(0);
3007 ArrayRef<int> NewMask = SV->getMask().slice(0, VT.getVectorNumElements());
3009 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3010 SDValue V1 = GetPromotedInteger(N->getOperand(1));
3011 EVT OutVT = V0.getValueType();
3013 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask);
3017 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
3018 EVT OutVT = N->getValueType(0);
3019 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3020 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3021 unsigned NumElems = N->getNumOperands();
3022 EVT NOutVTElem = NOutVT.getVectorElementType();
3026 SmallVector<SDValue, 8> Ops;
3027 Ops.reserve(NumElems);
3028 for (unsigned i = 0; i != NumElems; ++i) {
3030 // BUILD_VECTOR integer operand types are allowed to be larger than the
3031 // result's element type. This may still be true after the promotion. For
3032 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
3033 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
3034 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
3035 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
3037 Op = N->getOperand(i);
3041 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3044 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
3048 assert(!N->getOperand(0).getValueType().isVector() &&
3049 "Input must be a scalar");
3051 EVT OutVT = N->getValueType(0);
3052 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3053 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3054 EVT NOutVTElem = NOutVT.getVectorElementType();
3056 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
3058 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
3061 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3064 EVT OutVT = N->getValueType(0);
3065 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3066 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3068 EVT InElemTy = OutVT.getVectorElementType();
3069 EVT OutElemTy = NOutVT.getVectorElementType();
3071 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3072 unsigned NumOutElem = NOutVT.getVectorNumElements();
3073 unsigned NumOperands = N->getNumOperands();
3074 assert(NumElem * NumOperands == NumOutElem &&
3075 "Unexpected number of elements");
3077 // Take the elements from the first vector.
3078 SmallVector<SDValue, 8> Ops(NumOutElem);
3079 for (unsigned i = 0; i < NumOperands; ++i) {
3080 SDValue Op = N->getOperand(i);
3081 for (unsigned j = 0; j < NumElem; ++j) {
3082 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3083 InElemTy, Op, DAG.getConstant(j, dl,
3084 TLI.getVectorIdxTy()));
3085 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3089 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3092 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3093 EVT OutVT = N->getValueType(0);
3094 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3095 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3097 EVT NOutVTElem = NOutVT.getVectorElementType();
3100 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3102 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3103 NOutVTElem, N->getOperand(1));
3104 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3105 V0, ConvElem, N->getOperand(2));
3108 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3110 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3111 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3112 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3113 V0->getValueType(0).getScalarType(), V0, V1);
3115 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3116 // element types. If this is the case then we need to expand the outgoing
3117 // value and not truncate it.
3118 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3121 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3123 unsigned NumElems = N->getNumOperands();
3125 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3127 SmallVector<SDValue, 8> NewOps;
3128 NewOps.reserve(NumElems);
3130 // For each incoming vector
3131 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3132 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3133 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3134 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3136 for (unsigned i=0; i<NumElem; ++i) {
3137 // Extract element from incoming vector
3138 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3139 Incoming, DAG.getConstant(i, dl, TLI.getVectorIdxTy()));
3140 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3141 NewOps.push_back(Tr);
3145 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);