1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/IR/DerivedTypes.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/raw_ostream.h"
27 #define DEBUG_TYPE "legalize-types"
29 //===----------------------------------------------------------------------===//
30 // Integer Result Promotion
31 //===----------------------------------------------------------------------===//
33 /// PromoteIntegerResult - This method is called when a result of a node is
34 /// found to be in need of promotion to a larger type. At this point, the node
35 /// may also have invalid operands or may have other results that need
36 /// expansion, we just know that (at least) one result needs promotion.
37 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
38 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
39 SDValue Res = SDValue();
41 // See if the target wants to custom expand this node.
42 if (CustomLowerNode(N, N->getValueType(ResNo), true))
45 switch (N->getOpcode()) {
48 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
49 N->dump(&DAG); dbgs() << "\n";
51 llvm_unreachable("Do not know how to promote this operator!");
52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
53 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
54 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
55 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
56 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
57 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
59 case ISD::CONVERT_RNDSAT:
60 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
61 case ISD::CTLZ_ZERO_UNDEF:
62 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
63 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
64 case ISD::CTTZ_ZERO_UNDEF:
65 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
66 case ISD::EXTRACT_VECTOR_ELT:
67 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
68 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
69 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
70 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
71 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
72 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
73 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
74 case ISD::SIGN_EXTEND_INREG:
75 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
76 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
77 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
78 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
79 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
80 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
82 case ISD::EXTRACT_SUBVECTOR:
83 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
84 case ISD::VECTOR_SHUFFLE:
85 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
86 case ISD::INSERT_VECTOR_ELT:
87 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
88 case ISD::BUILD_VECTOR:
89 Res = PromoteIntRes_BUILD_VECTOR(N); break;
90 case ISD::SCALAR_TO_VECTOR:
91 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
92 case ISD::CONCAT_VECTORS:
93 Res = PromoteIntRes_CONCAT_VECTORS(N); break;
95 case ISD::SIGN_EXTEND:
96 case ISD::ZERO_EXTEND:
97 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
100 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
102 case ISD::FP_TO_FP16: Res = PromoteIntRes_FP_TO_FP16(N); break;
109 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
112 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
115 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
118 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
120 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
122 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
124 case ISD::ATOMIC_LOAD:
125 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
127 case ISD::ATOMIC_LOAD_ADD:
128 case ISD::ATOMIC_LOAD_SUB:
129 case ISD::ATOMIC_LOAD_AND:
130 case ISD::ATOMIC_LOAD_OR:
131 case ISD::ATOMIC_LOAD_XOR:
132 case ISD::ATOMIC_LOAD_NAND:
133 case ISD::ATOMIC_LOAD_MIN:
134 case ISD::ATOMIC_LOAD_MAX:
135 case ISD::ATOMIC_LOAD_UMIN:
136 case ISD::ATOMIC_LOAD_UMAX:
137 case ISD::ATOMIC_SWAP:
138 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
140 case ISD::ATOMIC_CMP_SWAP:
141 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
142 Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);
146 // If the result is null then the sub-method took care of registering it.
148 SetPromotedInteger(SDValue(N, ResNo), Res);
151 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
153 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
154 return GetPromotedInteger(Op);
157 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
158 // Sign-extend the new bits, and continue the assertion.
159 SDValue Op = SExtPromotedInteger(N->getOperand(0));
160 return DAG.getNode(ISD::AssertSext, SDLoc(N),
161 Op.getValueType(), Op, N->getOperand(1));
164 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
165 // Zero the new bits, and continue the assertion.
166 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
167 return DAG.getNode(ISD::AssertZext, SDLoc(N),
168 Op.getValueType(), Op, N->getOperand(1));
171 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
172 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
173 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
174 N->getMemoryVT(), ResVT,
175 N->getChain(), N->getBasePtr(),
176 N->getMemOperand(), N->getOrdering(),
178 // Legalized the chain result - switch anything that used the old chain to
180 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
184 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
185 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
186 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
188 N->getChain(), N->getBasePtr(),
189 Op2, N->getMemOperand(), N->getOrdering(),
191 // Legalized the chain result - switch anything that used the old chain to
193 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
197 SDValue DAGTypeLegalizer::PromoteIntRes_AtomicCmpSwap(AtomicSDNode *N,
200 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
201 EVT SVT = getSetCCResultType(N->getOperand(2).getValueType());
202 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
204 // Only use the result of getSetCCResultType if it is legal,
205 // otherwise just use the promoted result type (NVT).
206 if (!TLI.isTypeLegal(SVT))
209 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other);
210 SDValue Res = DAG.getAtomicCmpSwap(
211 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, SDLoc(N), N->getMemoryVT(), VTs,
212 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3),
213 N->getMemOperand(), N->getSuccessOrdering(), N->getFailureOrdering(),
215 ReplaceValueWith(SDValue(N, 0), Res.getValue(0));
216 ReplaceValueWith(SDValue(N, 2), Res.getValue(2));
217 return Res.getValue(1);
220 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
221 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
223 DAG.getVTList(Op2.getValueType(), N->getValueType(1), MVT::Other);
224 SDValue Res = DAG.getAtomicCmpSwap(
225 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
226 N->getBasePtr(), Op2, Op3, N->getMemOperand(), N->getSuccessOrdering(),
227 N->getFailureOrdering(), N->getSynchScope());
228 // Update the use to N with the newly created Res.
229 for (unsigned i = 1, NumResults = N->getNumValues(); i < NumResults; ++i)
230 ReplaceValueWith(SDValue(N, i), Res.getValue(i));
234 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
235 SDValue InOp = N->getOperand(0);
236 EVT InVT = InOp.getValueType();
237 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
238 EVT OutVT = N->getValueType(0);
239 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
242 switch (getTypeAction(InVT)) {
243 case TargetLowering::TypeLegal:
245 case TargetLowering::TypePromoteInteger:
246 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector() && !NInVT.isVector())
247 // The input promotes to the same size. Convert the promoted value.
248 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
250 case TargetLowering::TypeSoftenFloat:
251 // Promote the integer operand by hand.
252 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
253 case TargetLowering::TypeExpandInteger:
254 case TargetLowering::TypeExpandFloat:
256 case TargetLowering::TypeScalarizeVector:
257 // Convert the element to an integer and promote it by hand.
258 if (!NOutVT.isVector())
259 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
260 BitConvertToInteger(GetScalarizedVector(InOp)));
262 case TargetLowering::TypeSplitVector: {
263 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
264 // pieces of the input into integers and reassemble in the final type.
266 GetSplitVector(N->getOperand(0), Lo, Hi);
267 Lo = BitConvertToInteger(Lo);
268 Hi = BitConvertToInteger(Hi);
270 if (TLI.isBigEndian())
273 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
274 EVT::getIntegerVT(*DAG.getContext(),
275 NOutVT.getSizeInBits()),
276 JoinIntegers(Lo, Hi));
277 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
279 case TargetLowering::TypeWidenVector:
280 // The input is widened to the same size. Convert to the widened value.
281 // Make sure that the outgoing value is not a vector, because this would
282 // make us bitcast between two vectors which are legalized in different ways.
283 if (NOutVT.bitsEq(NInVT) && !NOutVT.isVector())
284 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetWidenedVector(InOp));
287 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
288 CreateStackStoreLoad(InOp, OutVT));
291 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 EVT OVT = N->getValueType(0);
294 EVT NVT = Op.getValueType();
297 unsigned DiffBits = NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits();
298 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
299 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
302 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
303 // The pair element type may be legal, or may not promote to the same type as
304 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
305 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N),
306 TLI.getTypeToTransformTo(*DAG.getContext(),
307 N->getValueType(0)), JoinIntegers(N->getOperand(0),
311 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
312 EVT VT = N->getValueType(0);
313 // FIXME there is no actual debug info here
315 // Zero extend things like i1, sign extend everything else. It shouldn't
316 // matter in theory which one we pick, but this tends to give better code?
317 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
318 SDValue Result = DAG.getNode(Opc, dl,
319 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
321 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
325 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
326 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
327 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
328 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
329 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
330 "can only promote integers");
331 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
332 return DAG.getConvertRndSat(OutVT, SDLoc(N), N->getOperand(0),
333 N->getOperand(1), N->getOperand(2),
334 N->getOperand(3), N->getOperand(4), CvtCode);
337 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
338 // Zero extend to the promoted type and do the count there.
339 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
341 EVT OVT = N->getValueType(0);
342 EVT NVT = Op.getValueType();
343 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
344 // Subtract off the extra leading bits in the bigger type.
346 ISD::SUB, dl, NVT, Op,
347 DAG.getConstant(NVT.getScalarSizeInBits() - OVT.getScalarSizeInBits(),
351 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
352 // Zero extend to the promoted type and do the count there.
353 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
354 return DAG.getNode(ISD::CTPOP, SDLoc(N), Op.getValueType(), Op);
357 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
358 SDValue Op = GetPromotedInteger(N->getOperand(0));
359 EVT OVT = N->getValueType(0);
360 EVT NVT = Op.getValueType();
362 if (N->getOpcode() == ISD::CTTZ) {
363 // The count is the same in the promoted type except if the original
364 // value was zero. This can be handled by setting the bit just off
365 // the top of the original type.
366 auto TopBit = APInt::getOneBitSet(NVT.getScalarSizeInBits(),
367 OVT.getScalarSizeInBits());
368 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
370 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
373 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
375 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
376 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
380 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
381 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
382 unsigned NewOpc = N->getOpcode();
385 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
386 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
387 // and SINT conversions are Custom, there is no way to tell which is
388 // preferable. We choose SINT because that's the right thing on PPC.)
389 if (N->getOpcode() == ISD::FP_TO_UINT &&
390 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
391 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
392 NewOpc = ISD::FP_TO_SINT;
394 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
396 // Assert that the converted value fits in the original type. If it doesn't
397 // (eg: because the value being converted is too big), then the result of the
398 // original operation was undefined anyway, so the assert is still correct.
399 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
400 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
401 DAG.getValueType(N->getValueType(0).getScalarType()));
404 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
405 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
408 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
410 return DAG.getNode(ISD::AssertZext, dl,
411 NVT, Res, DAG.getValueType(N->getValueType(0)));
414 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
415 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
418 if (getTypeAction(N->getOperand(0).getValueType())
419 == TargetLowering::TypePromoteInteger) {
420 SDValue Res = GetPromotedInteger(N->getOperand(0));
421 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
423 // If the result and operand types are the same after promotion, simplify
424 // to an in-register extension.
425 if (NVT == Res.getValueType()) {
426 // The high bits are not guaranteed to be anything. Insert an extend.
427 if (N->getOpcode() == ISD::SIGN_EXTEND)
428 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
429 DAG.getValueType(N->getOperand(0).getValueType()));
430 if (N->getOpcode() == ISD::ZERO_EXTEND)
431 return DAG.getZeroExtendInReg(Res, dl,
432 N->getOperand(0).getValueType().getScalarType());
433 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
438 // Otherwise, just extend the original operand all the way to the larger type.
439 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
442 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
443 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
444 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
445 ISD::LoadExtType ExtType =
446 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
448 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
449 N->getMemoryVT(), N->getMemOperand());
451 // Legalized the chain result - switch anything that used the old chain to
453 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
457 /// Promote the overflow flag of an overflowing arithmetic node.
458 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
459 // Simply change the return type of the boolean result.
460 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
461 EVT ValueVTs[] = { N->getValueType(0), NVT };
462 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
463 SDValue Res = DAG.getNode(N->getOpcode(), SDLoc(N),
464 DAG.getVTList(ValueVTs), Ops);
466 // Modified the sum result - switch anything that used the old sum to use
468 ReplaceValueWith(SDValue(N, 0), Res);
470 return SDValue(Res.getNode(), 1);
473 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
475 return PromoteIntRes_Overflow(N);
477 // The operation overflowed iff the result in the larger type is not the
478 // sign extension of its truncation to the original type.
479 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
480 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
481 EVT OVT = N->getOperand(0).getValueType();
482 EVT NVT = LHS.getValueType();
485 // Do the arithmetic in the larger type.
486 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
487 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
489 // Calculate the overflow flag: sign extend the arithmetic result from
490 // the original type.
491 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
492 DAG.getValueType(OVT));
493 // Overflowed if and only if this is not equal to Res.
494 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
496 // Use the calculated overflow everywhere.
497 ReplaceValueWith(SDValue(N, 1), Ofl);
502 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
503 // Sign extend the input.
504 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
505 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
506 return DAG.getNode(N->getOpcode(), SDLoc(N),
507 LHS.getValueType(), LHS, RHS);
510 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
511 SDValue LHS = GetPromotedInteger(N->getOperand(1));
512 SDValue RHS = GetPromotedInteger(N->getOperand(2));
513 return DAG.getSelect(SDLoc(N),
514 LHS.getValueType(), N->getOperand(0), LHS, RHS);
517 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
518 SDValue Mask = N->getOperand(0);
519 EVT OpTy = N->getOperand(1).getValueType();
521 // Promote all the way up to the canonical SetCC type.
522 Mask = PromoteTargetBoolean(Mask, OpTy);
523 SDValue LHS = GetPromotedInteger(N->getOperand(1));
524 SDValue RHS = GetPromotedInteger(N->getOperand(2));
525 return DAG.getNode(ISD::VSELECT, SDLoc(N),
526 LHS.getValueType(), Mask, LHS, RHS);
529 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
530 SDValue LHS = GetPromotedInteger(N->getOperand(2));
531 SDValue RHS = GetPromotedInteger(N->getOperand(3));
532 return DAG.getNode(ISD::SELECT_CC, SDLoc(N),
533 LHS.getValueType(), N->getOperand(0),
534 N->getOperand(1), LHS, RHS, N->getOperand(4));
537 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
538 EVT SVT = getSetCCResultType(N->getOperand(0).getValueType());
540 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
542 // Only use the result of getSetCCResultType if it is legal,
543 // otherwise just use the promoted result type (NVT).
544 if (!TLI.isTypeLegal(SVT))
548 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
549 "Vector compare must return a vector result!");
551 SDValue LHS = N->getOperand(0);
552 SDValue RHS = N->getOperand(1);
553 if (LHS.getValueType() != RHS.getValueType()) {
554 if (getTypeAction(LHS.getValueType()) == TargetLowering::TypePromoteInteger &&
555 !LHS.getValueType().isVector())
556 LHS = GetPromotedInteger(LHS);
557 if (getTypeAction(RHS.getValueType()) == TargetLowering::TypePromoteInteger &&
558 !RHS.getValueType().isVector())
559 RHS = GetPromotedInteger(RHS);
562 // Get the SETCC result using the canonical SETCC type.
563 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, LHS, RHS,
566 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
567 // Convert to the expected type.
568 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
571 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
572 SDValue Res = GetPromotedInteger(N->getOperand(0));
573 SDValue Amt = N->getOperand(1);
574 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
575 return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
578 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
579 SDValue Op = GetPromotedInteger(N->getOperand(0));
580 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N),
581 Op.getValueType(), Op, N->getOperand(1));
584 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
585 // The input may have strange things in the top bits of the registers, but
586 // these operations don't care. They may have weird bits going out, but
587 // that too is okay if they are integer operations.
588 SDValue LHS = GetPromotedInteger(N->getOperand(0));
589 SDValue RHS = GetPromotedInteger(N->getOperand(1));
590 return DAG.getNode(N->getOpcode(), SDLoc(N),
591 LHS.getValueType(), LHS, RHS);
594 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
595 // The input value must be properly sign extended.
596 SDValue Res = SExtPromotedInteger(N->getOperand(0));
597 SDValue Amt = N->getOperand(1);
598 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
599 return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
602 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
603 // The input value must be properly zero extended.
604 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
605 SDValue Amt = N->getOperand(1);
606 Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
607 return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
610 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
611 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
613 SDValue InOp = N->getOperand(0);
616 switch (getTypeAction(InOp.getValueType())) {
617 default: llvm_unreachable("Unknown type action!");
618 case TargetLowering::TypeLegal:
619 case TargetLowering::TypeExpandInteger:
622 case TargetLowering::TypePromoteInteger:
623 Res = GetPromotedInteger(InOp);
625 case TargetLowering::TypeSplitVector:
626 EVT InVT = InOp.getValueType();
627 assert(InVT.isVector() && "Cannot split scalar types");
628 unsigned NumElts = InVT.getVectorNumElements();
629 assert(NumElts == NVT.getVectorNumElements() &&
630 "Dst and Src must have the same number of elements");
631 assert(isPowerOf2_32(NumElts) &&
632 "Promoted vector type must be a power of two");
635 GetSplitVector(InOp, EOp1, EOp2);
637 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
639 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
640 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
642 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
645 // Truncate to NVT instead of VT
646 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
649 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
651 return PromoteIntRes_Overflow(N);
653 // The operation overflowed iff the result in the larger type is not the
654 // zero extension of its truncation to the original type.
655 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
656 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
657 EVT OVT = N->getOperand(0).getValueType();
658 EVT NVT = LHS.getValueType();
661 // Do the arithmetic in the larger type.
662 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
663 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
665 // Calculate the overflow flag: zero extend the arithmetic result from
666 // the original type.
667 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
668 // Overflowed if and only if this is not equal to Res.
669 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
671 // Use the calculated overflow everywhere.
672 ReplaceValueWith(SDValue(N, 1), Ofl);
677 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
678 // Promote the overflow bit trivially.
680 return PromoteIntRes_Overflow(N);
682 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
684 EVT SmallVT = LHS.getValueType();
686 // To determine if the result overflowed in a larger type, we extend the
687 // input to the larger type, do the multiply (checking if it overflows),
688 // then also check the high bits of the result to see if overflow happened
690 if (N->getOpcode() == ISD::SMULO) {
691 LHS = SExtPromotedInteger(LHS);
692 RHS = SExtPromotedInteger(RHS);
694 LHS = ZExtPromotedInteger(LHS);
695 RHS = ZExtPromotedInteger(RHS);
697 SDVTList VTs = DAG.getVTList(LHS.getValueType(), N->getValueType(1));
698 SDValue Mul = DAG.getNode(N->getOpcode(), DL, VTs, LHS, RHS);
700 // Overflow occurred if it occurred in the larger type, or if the high part
701 // of the result does not zero/sign-extend the low part. Check this second
702 // possibility first.
704 if (N->getOpcode() == ISD::UMULO) {
705 // Unsigned overflow occurred if the high part is non-zero.
706 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
707 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
708 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
709 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
711 // Signed overflow occurred if the high part does not sign extend the low.
712 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
713 Mul, DAG.getValueType(SmallVT));
714 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
717 // The only other way for overflow to occur is if the multiplication in the
718 // larger type itself overflowed.
719 Overflow = DAG.getNode(ISD::OR, DL, N->getValueType(1), Overflow,
720 SDValue(Mul.getNode(), 1));
722 // Use the calculated overflow everywhere.
723 ReplaceValueWith(SDValue(N, 1), Overflow);
727 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
728 // Zero extend the input.
729 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
730 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
731 return DAG.getNode(N->getOpcode(), SDLoc(N),
732 LHS.getValueType(), LHS, RHS);
735 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
736 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
737 N->getValueType(0)));
740 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
741 SDValue Chain = N->getOperand(0); // Get the chain.
742 SDValue Ptr = N->getOperand(1); // Get the pointer.
743 EVT VT = N->getValueType(0);
746 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
747 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
748 // The argument is passed as NumRegs registers of type RegVT.
750 SmallVector<SDValue, 8> Parts(NumRegs);
751 for (unsigned i = 0; i < NumRegs; ++i) {
752 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
753 N->getConstantOperandVal(3));
754 Chain = Parts[i].getValue(1);
757 // Handle endianness of the load.
758 if (TLI.isBigEndian())
759 std::reverse(Parts.begin(), Parts.end());
761 // Assemble the parts in the promoted type.
762 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
763 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
764 for (unsigned i = 1; i < NumRegs; ++i) {
765 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
766 // Shift it to the right position and "or" it in.
767 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
768 DAG.getConstant(i * RegVT.getSizeInBits(),
769 TLI.getPointerTy()));
770 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
773 // Modified the chain result - switch anything that used the old chain to
775 ReplaceValueWith(SDValue(N, 1), Chain);
780 //===----------------------------------------------------------------------===//
781 // Integer Operand Promotion
782 //===----------------------------------------------------------------------===//
784 /// PromoteIntegerOperand - This method is called when the specified operand of
785 /// the specified node is found to need promotion. At this point, all of the
786 /// result types of the node are known to be legal, but other operands of the
787 /// node may need promotion or expansion as well as the specified one.
788 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
789 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
790 SDValue Res = SDValue();
792 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
795 switch (N->getOpcode()) {
798 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
799 N->dump(&DAG); dbgs() << "\n";
801 llvm_unreachable("Do not know how to promote this operator's operand!");
803 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
804 case ISD::ATOMIC_STORE:
805 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
807 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
808 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
809 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
810 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
811 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
812 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
813 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
814 case ISD::CONVERT_RNDSAT:
815 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
816 case ISD::INSERT_VECTOR_ELT:
817 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
818 case ISD::SCALAR_TO_VECTOR:
819 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
821 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
822 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
823 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
824 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
825 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
826 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
828 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
829 case ISD::FP16_TO_FP:
830 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
831 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
837 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
840 // If the result is null, the sub-method took care of registering results etc.
841 if (!Res.getNode()) return false;
843 // If the result is N, the sub-method updated N in place. Tell the legalizer
845 if (Res.getNode() == N)
848 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
849 "Invalid operand expansion");
851 ReplaceValueWith(SDValue(N, 0), Res);
855 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
856 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
857 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
858 ISD::CondCode CCCode) {
859 // We have to insert explicit sign or zero extends. Note that we could
860 // insert sign extends for ALL conditions, but zero extend is cheaper on
861 // many machines (an AND instead of two shifts), so prefer it.
863 default: llvm_unreachable("Unknown integer comparison!");
866 SDValue OpL = GetPromotedInteger(NewLHS);
867 SDValue OpR = GetPromotedInteger(NewRHS);
869 // We would prefer to promote the comparison operand with sign extension,
870 // if we find the operand is actually to truncate an AssertSext. With this
871 // optimization, we can avoid inserting real truncate instruction, which
872 // is redudant eventually.
873 if (OpL->getOpcode() == ISD::AssertSext &&
874 cast<VTSDNode>(OpL->getOperand(1))->getVT() == NewLHS.getValueType() &&
875 OpR->getOpcode() == ISD::AssertSext &&
876 cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
880 NewLHS = ZExtPromotedInteger(NewLHS);
881 NewRHS = ZExtPromotedInteger(NewRHS);
889 // ALL of these operations will work if we either sign or zero extend
890 // the operands (including the unsigned comparisons!). Zero extend is
891 // usually a simpler/cheaper operation, so prefer it.
892 NewLHS = ZExtPromotedInteger(NewLHS);
893 NewRHS = ZExtPromotedInteger(NewRHS);
899 NewLHS = SExtPromotedInteger(NewLHS);
900 NewRHS = SExtPromotedInteger(NewRHS);
905 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
906 SDValue Op = GetPromotedInteger(N->getOperand(0));
907 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);
910 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
911 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
912 return DAG.getAtomic(N->getOpcode(), SDLoc(N), N->getMemoryVT(),
913 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
914 N->getOrdering(), N->getSynchScope());
917 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
918 // This should only occur in unusual situations like bitcasting to an
919 // x86_fp80, so just turn it into a store+load
920 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
923 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
924 assert(OpNo == 2 && "Don't know how to promote this operand!");
926 SDValue LHS = N->getOperand(2);
927 SDValue RHS = N->getOperand(3);
928 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
930 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
932 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
933 N->getOperand(1), LHS, RHS, N->getOperand(4)),
937 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
938 assert(OpNo == 1 && "only know how to promote condition");
940 // Promote all the way up to the canonical SetCC type.
941 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), MVT::Other);
943 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
944 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
945 N->getOperand(2)), 0);
948 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
949 // Since the result type is legal, the operands must promote to it.
950 EVT OVT = N->getOperand(0).getValueType();
951 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
952 SDValue Hi = GetPromotedInteger(N->getOperand(1));
953 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
956 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
957 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
958 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
961 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
962 // The vector type is legal but the element type is not. This implies
963 // that the vector is a power-of-two in length and that the element
964 // type does not have a strange size (eg: it is not i1).
965 EVT VecVT = N->getValueType(0);
966 unsigned NumElts = VecVT.getVectorNumElements();
967 assert(!((NumElts & 1) && (!TLI.isTypeLegal(VecVT))) &&
968 "Legal vector of one illegal element?");
970 // Promote the inserted value. The type does not need to match the
971 // vector element type. Check that any extra bits introduced will be
973 assert(N->getOperand(0).getValueType().getSizeInBits() >=
974 N->getValueType(0).getVectorElementType().getSizeInBits() &&
975 "Type of inserted value narrower than vector element type!");
977 SmallVector<SDValue, 16> NewOps;
978 for (unsigned i = 0; i < NumElts; ++i)
979 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
981 return SDValue(DAG.UpdateNodeOperands(N, NewOps), 0);
984 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
985 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
986 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
987 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
988 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
989 "can only promote integer arguments");
990 SDValue InOp = GetPromotedInteger(N->getOperand(0));
991 return DAG.getConvertRndSat(N->getValueType(0), SDLoc(N), InOp,
992 N->getOperand(1), N->getOperand(2),
993 N->getOperand(3), N->getOperand(4), CvtCode);
996 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
999 // Promote the inserted value. This is valid because the type does not
1000 // have to match the vector element type.
1002 // Check that any extra bits introduced will be truncated away.
1003 assert(N->getOperand(1).getValueType().getSizeInBits() >=
1004 N->getValueType(0).getVectorElementType().getSizeInBits() &&
1005 "Type of inserted value narrower than vector element type!");
1006 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1007 GetPromotedInteger(N->getOperand(1)),
1012 assert(OpNo == 2 && "Different operand and result vector types?");
1014 // Promote the index.
1015 SDValue Idx = DAG.getZExtOrTrunc(N->getOperand(2), SDLoc(N),
1016 TLI.getVectorIdxTy());
1017 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1018 N->getOperand(1), Idx), 0);
1021 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
1022 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
1023 // the operand in place.
1024 return SDValue(DAG.UpdateNodeOperands(N,
1025 GetPromotedInteger(N->getOperand(0))), 0);
1028 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
1029 assert(OpNo == 0 && "Only know how to promote the condition!");
1030 SDValue Cond = N->getOperand(0);
1031 EVT OpTy = N->getOperand(1).getValueType();
1033 // Promote all the way up to the canonical SetCC type.
1034 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1035 Cond = PromoteTargetBoolean(Cond, OpVT);
1037 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
1038 N->getOperand(2)), 0);
1041 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
1042 assert(OpNo == 0 && "Don't know how to promote this operand!");
1044 SDValue LHS = N->getOperand(0);
1045 SDValue RHS = N->getOperand(1);
1046 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
1048 // The CC (#4) and the possible return values (#2 and #3) have legal types.
1049 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
1050 N->getOperand(3), N->getOperand(4)), 0);
1053 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
1054 assert(OpNo == 0 && "Don't know how to promote this operand!");
1056 SDValue LHS = N->getOperand(0);
1057 SDValue RHS = N->getOperand(1);
1058 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
1060 // The CC (#2) is always legal.
1061 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
1064 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
1065 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1066 ZExtPromotedInteger(N->getOperand(1))), 0);
1069 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1070 SDValue Op = GetPromotedInteger(N->getOperand(0));
1072 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1073 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1074 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1077 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1078 return SDValue(DAG.UpdateNodeOperands(N,
1079 SExtPromotedInteger(N->getOperand(0))), 0);
1082 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1083 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1084 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1087 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1089 // Truncate the value and store the result.
1090 return DAG.getTruncStore(Ch, dl, Val, Ptr,
1091 N->getMemoryVT(), N->getMemOperand());
1094 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1095 SDValue Op = GetPromotedInteger(N->getOperand(0));
1096 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), Op);
1099 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1100 return SDValue(DAG.UpdateNodeOperands(N,
1101 ZExtPromotedInteger(N->getOperand(0))), 0);
1104 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1106 SDValue Op = GetPromotedInteger(N->getOperand(0));
1107 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1108 return DAG.getZeroExtendInReg(Op, dl,
1109 N->getOperand(0).getValueType().getScalarType());
1113 //===----------------------------------------------------------------------===//
1114 // Integer Result Expansion
1115 //===----------------------------------------------------------------------===//
1117 /// ExpandIntegerResult - This method is called when the specified result of the
1118 /// specified node is found to need expansion. At this point, the node may also
1119 /// have invalid operands or may have other results that need promotion, we just
1120 /// know that (at least) one result needs expansion.
1121 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1122 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1124 Lo = Hi = SDValue();
1126 // See if the target wants to custom expand this node.
1127 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1130 switch (N->getOpcode()) {
1133 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1134 N->dump(&DAG); dbgs() << "\n";
1136 llvm_unreachable("Do not know how to expand the result of this operator!");
1138 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
1139 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1140 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1141 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1143 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1144 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1145 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1146 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1147 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1149 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1150 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1151 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1152 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1153 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1154 case ISD::CTLZ_ZERO_UNDEF:
1155 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1156 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1157 case ISD::CTTZ_ZERO_UNDEF:
1158 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1159 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1160 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1161 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1162 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1163 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1164 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1165 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1166 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1167 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1168 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1169 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1170 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1171 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1173 case ISD::ATOMIC_LOAD_ADD:
1174 case ISD::ATOMIC_LOAD_SUB:
1175 case ISD::ATOMIC_LOAD_AND:
1176 case ISD::ATOMIC_LOAD_OR:
1177 case ISD::ATOMIC_LOAD_XOR:
1178 case ISD::ATOMIC_LOAD_NAND:
1179 case ISD::ATOMIC_LOAD_MIN:
1180 case ISD::ATOMIC_LOAD_MAX:
1181 case ISD::ATOMIC_LOAD_UMIN:
1182 case ISD::ATOMIC_LOAD_UMAX:
1183 case ISD::ATOMIC_SWAP:
1184 case ISD::ATOMIC_CMP_SWAP: {
1185 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1186 SplitInteger(Tmp.first, Lo, Hi);
1187 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1190 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
1191 AtomicSDNode *AN = cast<AtomicSDNode>(N);
1192 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::Other);
1193 SDValue Tmp = DAG.getAtomicCmpSwap(
1194 ISD::ATOMIC_CMP_SWAP, SDLoc(N), AN->getMemoryVT(), VTs,
1195 N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3),
1196 AN->getMemOperand(), AN->getSuccessOrdering(), AN->getFailureOrdering(),
1197 AN->getSynchScope());
1199 // Expanding to the strong ATOMIC_CMP_SWAP node means we can determine
1200 // success simply by comparing the loaded value against the ingoing
1202 SDValue Success = DAG.getSetCC(SDLoc(N), N->getValueType(1), Tmp,
1203 N->getOperand(2), ISD::SETEQ);
1205 SplitInteger(Tmp, Lo, Hi);
1206 ReplaceValueWith(SDValue(N, 1), Success);
1207 ReplaceValueWith(SDValue(N, 2), Tmp.getValue(1));
1213 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1216 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1219 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1222 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1226 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1229 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1231 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1233 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1236 // If Lo/Hi is null, the sub-method took care of registering results etc.
1238 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1241 /// Lower an atomic node to the appropriate builtin call.
1242 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1243 unsigned Opc = Node->getOpcode();
1244 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1249 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1250 case ISD::ATOMIC_SWAP:
1251 switch (VT.SimpleTy) {
1252 default: llvm_unreachable("Unexpected value type for atomic!");
1253 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1254 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1255 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1256 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1257 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
1260 case ISD::ATOMIC_CMP_SWAP:
1261 switch (VT.SimpleTy) {
1262 default: llvm_unreachable("Unexpected value type for atomic!");
1263 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1264 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1265 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1266 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1267 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
1270 case ISD::ATOMIC_LOAD_ADD:
1271 switch (VT.SimpleTy) {
1272 default: llvm_unreachable("Unexpected value type for atomic!");
1273 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1274 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1275 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1276 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1277 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
1280 case ISD::ATOMIC_LOAD_SUB:
1281 switch (VT.SimpleTy) {
1282 default: llvm_unreachable("Unexpected value type for atomic!");
1283 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1284 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1285 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1286 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1287 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
1290 case ISD::ATOMIC_LOAD_AND:
1291 switch (VT.SimpleTy) {
1292 default: llvm_unreachable("Unexpected value type for atomic!");
1293 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1294 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1295 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1296 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1297 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
1300 case ISD::ATOMIC_LOAD_OR:
1301 switch (VT.SimpleTy) {
1302 default: llvm_unreachable("Unexpected value type for atomic!");
1303 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1304 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1305 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1306 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1307 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
1310 case ISD::ATOMIC_LOAD_XOR:
1311 switch (VT.SimpleTy) {
1312 default: llvm_unreachable("Unexpected value type for atomic!");
1313 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1314 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1315 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1316 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1317 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
1320 case ISD::ATOMIC_LOAD_NAND:
1321 switch (VT.SimpleTy) {
1322 default: llvm_unreachable("Unexpected value type for atomic!");
1323 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1324 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1325 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1326 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1327 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
1332 return ExpandChainLibCall(LC, Node, false);
1335 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1336 /// and the shift amount is a constant 'Amt'. Expand the operation.
1337 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1338 SDValue &Lo, SDValue &Hi) {
1339 assert(Amt && "Expected zero shifts to be already optimized away.");
1341 // Expand the incoming operand to be shifted, so that we have its parts
1343 GetExpandedInteger(N->getOperand(0), InL, InH);
1345 EVT NVT = InL.getValueType();
1346 unsigned VTBits = N->getValueType(0).getSizeInBits();
1347 unsigned NVTBits = NVT.getSizeInBits();
1348 EVT ShTy = N->getOperand(1).getValueType();
1350 if (N->getOpcode() == ISD::SHL) {
1352 Lo = Hi = DAG.getConstant(0, NVT);
1353 } else if (Amt > NVTBits) {
1354 Lo = DAG.getConstant(0, NVT);
1355 Hi = DAG.getNode(ISD::SHL, DL,
1356 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1357 } else if (Amt == NVTBits) {
1358 Lo = DAG.getConstant(0, NVT);
1360 } else if (Amt == 1 &&
1361 TLI.isOperationLegalOrCustom(ISD::ADDC,
1362 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1363 // Emit this X << 1 as X+X.
1364 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1365 SDValue LoOps[2] = { InL, InL };
1366 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps);
1367 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1368 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps);
1370 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1371 Hi = DAG.getNode(ISD::OR, DL, NVT,
1372 DAG.getNode(ISD::SHL, DL, NVT, InH,
1373 DAG.getConstant(Amt, ShTy)),
1374 DAG.getNode(ISD::SRL, DL, NVT, InL,
1375 DAG.getConstant(NVTBits-Amt, ShTy)));
1380 if (N->getOpcode() == ISD::SRL) {
1382 Lo = DAG.getConstant(0, NVT);
1383 Hi = DAG.getConstant(0, NVT);
1384 } else if (Amt > NVTBits) {
1385 Lo = DAG.getNode(ISD::SRL, DL,
1386 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1387 Hi = DAG.getConstant(0, NVT);
1388 } else if (Amt == NVTBits) {
1390 Hi = DAG.getConstant(0, NVT);
1392 Lo = DAG.getNode(ISD::OR, DL, NVT,
1393 DAG.getNode(ISD::SRL, DL, NVT, InL,
1394 DAG.getConstant(Amt, ShTy)),
1395 DAG.getNode(ISD::SHL, DL, NVT, InH,
1396 DAG.getConstant(NVTBits-Amt, ShTy)));
1397 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1402 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1404 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1405 DAG.getConstant(NVTBits-1, ShTy));
1406 } else if (Amt > NVTBits) {
1407 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1408 DAG.getConstant(Amt-NVTBits, ShTy));
1409 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1410 DAG.getConstant(NVTBits-1, ShTy));
1411 } else if (Amt == NVTBits) {
1413 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1414 DAG.getConstant(NVTBits-1, ShTy));
1416 Lo = DAG.getNode(ISD::OR, DL, NVT,
1417 DAG.getNode(ISD::SRL, DL, NVT, InL,
1418 DAG.getConstant(Amt, ShTy)),
1419 DAG.getNode(ISD::SHL, DL, NVT, InH,
1420 DAG.getConstant(NVTBits-Amt, ShTy)));
1421 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1425 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1426 /// this shift based on knowledge of the high bit of the shift amount. If we
1427 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1429 bool DAGTypeLegalizer::
1430 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1431 SDValue Amt = N->getOperand(1);
1432 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1433 EVT ShTy = Amt.getValueType();
1434 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1435 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1436 assert(isPowerOf2_32(NVTBits) &&
1437 "Expanded integer type size not a power of two!");
1440 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1441 APInt KnownZero, KnownOne;
1442 DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
1444 // If we don't know anything about the high bits, exit.
1445 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1448 // Get the incoming operand to be shifted.
1450 GetExpandedInteger(N->getOperand(0), InL, InH);
1452 // If we know that any of the high bits of the shift amount are one, then we
1453 // can do this as a couple of simple shifts.
1454 if (KnownOne.intersects(HighBitMask)) {
1455 // Mask out the high bit, which we know is set.
1456 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1457 DAG.getConstant(~HighBitMask, ShTy));
1459 switch (N->getOpcode()) {
1460 default: llvm_unreachable("Unknown shift");
1462 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1463 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1466 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1467 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1470 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1471 DAG.getConstant(NVTBits-1, ShTy));
1472 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1477 // If we know that all of the high bits of the shift amount are zero, then we
1478 // can do this as a couple of simple shifts.
1479 if ((KnownZero & HighBitMask) == HighBitMask) {
1480 // Calculate 31-x. 31 is used instead of 32 to avoid creating an undefined
1481 // shift if x is zero. We can use XOR here because x is known to be smaller
1483 SDValue Amt2 = DAG.getNode(ISD::XOR, dl, ShTy, Amt,
1484 DAG.getConstant(NVTBits-1, ShTy));
1487 switch (N->getOpcode()) {
1488 default: llvm_unreachable("Unknown shift");
1489 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1491 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1494 // When shifting right the arithmetic for Lo and Hi is swapped.
1495 if (N->getOpcode() != ISD::SHL)
1496 std::swap(InL, InH);
1498 // Use a little trick to get the bits that move from Lo to Hi. First
1499 // shift by one bit.
1500 SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
1501 // Then compute the remaining shift with amount-1.
1502 SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
1504 Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
1505 Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);
1507 if (N->getOpcode() != ISD::SHL)
1515 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1517 bool DAGTypeLegalizer::
1518 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1519 SDValue Amt = N->getOperand(1);
1520 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1521 EVT ShTy = Amt.getValueType();
1522 unsigned NVTBits = NVT.getSizeInBits();
1523 assert(isPowerOf2_32(NVTBits) &&
1524 "Expanded integer type size not a power of two!");
1527 // Get the incoming operand to be shifted.
1529 GetExpandedInteger(N->getOperand(0), InL, InH);
1531 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1532 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1533 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1534 SDValue isShort = DAG.getSetCC(dl, getSetCCResultType(ShTy),
1535 Amt, NVBitsNode, ISD::SETULT);
1537 SDValue LoS, HiS, LoL, HiL;
1538 switch (N->getOpcode()) {
1539 default: llvm_unreachable("Unknown shift");
1541 // Short: ShAmt < NVTBits
1542 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1543 HiS = DAG.getNode(ISD::OR, dl, NVT,
1544 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1545 // FIXME: If Amt is zero, the following shift generates an undefined result
1546 // on some architectures.
1547 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1549 // Long: ShAmt >= NVTBits
1550 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1551 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1553 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1554 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1557 // Short: ShAmt < NVTBits
1558 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1559 LoS = DAG.getNode(ISD::OR, dl, NVT,
1560 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1561 // FIXME: If Amt is zero, the following shift generates an undefined result
1562 // on some architectures.
1563 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1565 // Long: ShAmt >= NVTBits
1566 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1567 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1569 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1570 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1573 // Short: ShAmt < NVTBits
1574 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1575 LoS = DAG.getNode(ISD::OR, dl, NVT,
1576 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1577 // FIXME: If Amt is zero, the following shift generates an undefined result
1578 // on some architectures.
1579 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1581 // Long: ShAmt >= NVTBits
1582 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1583 DAG.getConstant(NVTBits-1, ShTy));
1584 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1586 Lo = DAG.getSelect(dl, NVT, isShort, LoS, LoL);
1587 Hi = DAG.getSelect(dl, NVT, isShort, HiS, HiL);
1592 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1593 SDValue &Lo, SDValue &Hi) {
1595 // Expand the subcomponents.
1596 SDValue LHSL, LHSH, RHSL, RHSH;
1597 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1598 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1600 EVT NVT = LHSL.getValueType();
1601 SDValue LoOps[2] = { LHSL, RHSL };
1602 SDValue HiOps[3] = { LHSH, RHSH };
1604 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1605 // them. TODO: Teach operation legalization how to expand unsupported
1606 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1607 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1608 // generate a value of this type in the expanded code sequence.
1610 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1611 ISD::ADDC : ISD::SUBC,
1612 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1615 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1616 if (N->getOpcode() == ISD::ADD) {
1617 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1618 HiOps[2] = Lo.getValue(1);
1619 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1621 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1622 HiOps[2] = Lo.getValue(1);
1623 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1628 if (N->getOpcode() == ISD::ADD) {
1629 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps);
1630 Hi = DAG.getNode(ISD::ADD, dl, NVT, makeArrayRef(HiOps, 2));
1631 SDValue Cmp1 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[0],
1633 SDValue Carry1 = DAG.getSelect(dl, NVT, Cmp1,
1634 DAG.getConstant(1, NVT),
1635 DAG.getConstant(0, NVT));
1636 SDValue Cmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo, LoOps[1],
1638 SDValue Carry2 = DAG.getSelect(dl, NVT, Cmp2,
1639 DAG.getConstant(1, NVT), Carry1);
1640 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1642 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps);
1643 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2));
1645 DAG.getSetCC(dl, getSetCCResultType(LoOps[0].getValueType()),
1646 LoOps[0], LoOps[1], ISD::SETULT);
1647 SDValue Borrow = DAG.getSelect(dl, NVT, Cmp,
1648 DAG.getConstant(1, NVT),
1649 DAG.getConstant(0, NVT));
1650 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1654 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1655 SDValue &Lo, SDValue &Hi) {
1656 // Expand the subcomponents.
1657 SDValue LHSL, LHSH, RHSL, RHSH;
1659 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1660 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1661 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1662 SDValue LoOps[2] = { LHSL, RHSL };
1663 SDValue HiOps[3] = { LHSH, RHSH };
1665 if (N->getOpcode() == ISD::ADDC) {
1666 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps);
1667 HiOps[2] = Lo.getValue(1);
1668 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps);
1670 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
1671 HiOps[2] = Lo.getValue(1);
1672 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1675 // Legalized the flag result - switch anything that used the old flag to
1677 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1680 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1681 SDValue &Lo, SDValue &Hi) {
1682 // Expand the subcomponents.
1683 SDValue LHSL, LHSH, RHSL, RHSH;
1685 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1686 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1687 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1688 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1689 SDValue HiOps[3] = { LHSH, RHSH };
1691 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps);
1692 HiOps[2] = Lo.getValue(1);
1693 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps);
1695 // Legalized the flag result - switch anything that used the old flag to
1697 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1700 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N, unsigned ResNo,
1701 SDValue &Lo, SDValue &Hi) {
1702 SDValue Res = DisintegrateMERGE_VALUES(N, ResNo);
1703 SplitInteger(Res, Lo, Hi);
1706 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1707 SDValue &Lo, SDValue &Hi) {
1708 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1710 SDValue Op = N->getOperand(0);
1711 if (Op.getValueType().bitsLE(NVT)) {
1712 // The low part is any extension of the input (which degenerates to a copy).
1713 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1714 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1716 // For example, extension of an i48 to an i64. The operand type necessarily
1717 // promotes to the result type, so will end up being expanded too.
1718 assert(getTypeAction(Op.getValueType()) ==
1719 TargetLowering::TypePromoteInteger &&
1720 "Only know how to promote this result!");
1721 SDValue Res = GetPromotedInteger(Op);
1722 assert(Res.getValueType() == N->getValueType(0) &&
1723 "Operand over promoted?");
1724 // Split the promoted operand. This will simplify when it is expanded.
1725 SplitInteger(Res, Lo, Hi);
1729 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1730 SDValue &Lo, SDValue &Hi) {
1732 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1733 EVT NVT = Lo.getValueType();
1734 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1735 unsigned NVTBits = NVT.getSizeInBits();
1736 unsigned EVTBits = EVT.getSizeInBits();
1738 if (NVTBits < EVTBits) {
1739 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1740 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1741 EVTBits - NVTBits)));
1743 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1744 // The high part replicates the sign bit of Lo, make it explicit.
1745 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1746 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1750 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1751 SDValue &Lo, SDValue &Hi) {
1753 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1754 EVT NVT = Lo.getValueType();
1755 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1756 unsigned NVTBits = NVT.getSizeInBits();
1757 unsigned EVTBits = EVT.getSizeInBits();
1759 if (NVTBits < EVTBits) {
1760 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1761 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1762 EVTBits - NVTBits)));
1764 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1765 // The high part must be zero, make it explicit.
1766 Hi = DAG.getConstant(0, NVT);
1770 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1771 SDValue &Lo, SDValue &Hi) {
1773 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1774 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1775 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1778 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1779 SDValue &Lo, SDValue &Hi) {
1780 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1781 unsigned NBitWidth = NVT.getSizeInBits();
1782 auto Constant = cast<ConstantSDNode>(N);
1783 const APInt &Cst = Constant->getAPIntValue();
1784 bool IsTarget = Constant->isTargetOpcode();
1785 bool IsOpaque = Constant->isOpaque();
1786 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT, IsTarget, IsOpaque);
1787 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT, IsTarget,
1791 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1792 SDValue &Lo, SDValue &Hi) {
1794 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1795 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1796 EVT NVT = Lo.getValueType();
1798 SDValue HiNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Hi,
1799 DAG.getConstant(0, NVT), ISD::SETNE);
1801 SDValue LoLZ = DAG.getNode(N->getOpcode(), dl, NVT, Lo);
1802 SDValue HiLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, NVT, Hi);
1804 Lo = DAG.getSelect(dl, NVT, HiNotZero, HiLZ,
1805 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1806 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1807 Hi = DAG.getConstant(0, NVT);
1810 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1811 SDValue &Lo, SDValue &Hi) {
1813 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1814 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1815 EVT NVT = Lo.getValueType();
1816 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1817 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1818 Hi = DAG.getConstant(0, NVT);
1821 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1822 SDValue &Lo, SDValue &Hi) {
1824 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1825 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1826 EVT NVT = Lo.getValueType();
1828 SDValue LoNotZero = DAG.getSetCC(dl, getSetCCResultType(NVT), Lo,
1829 DAG.getConstant(0, NVT), ISD::SETNE);
1831 SDValue LoLZ = DAG.getNode(ISD::CTTZ_ZERO_UNDEF, dl, NVT, Lo);
1832 SDValue HiLZ = DAG.getNode(N->getOpcode(), dl, NVT, Hi);
1834 Lo = DAG.getSelect(dl, NVT, LoNotZero, LoLZ,
1835 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1836 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1837 Hi = DAG.getConstant(0, NVT);
1840 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1843 EVT VT = N->getValueType(0);
1844 SDValue Op = N->getOperand(0);
1845 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1846 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1847 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,
1852 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1855 EVT VT = N->getValueType(0);
1856 SDValue Op = N->getOperand(0);
1857 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1858 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1859 SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,
1864 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1865 SDValue &Lo, SDValue &Hi) {
1866 if (ISD::isNormalLoad(N)) {
1867 ExpandRes_NormalLoad(N, Lo, Hi);
1871 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1873 EVT VT = N->getValueType(0);
1874 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1875 SDValue Ch = N->getChain();
1876 SDValue Ptr = N->getBasePtr();
1877 ISD::LoadExtType ExtType = N->getExtensionType();
1878 unsigned Alignment = N->getAlignment();
1879 bool isVolatile = N->isVolatile();
1880 bool isNonTemporal = N->isNonTemporal();
1881 bool isInvariant = N->isInvariant();
1882 AAMDNodes AAInfo = N->getAAInfo();
1885 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1887 if (N->getMemoryVT().bitsLE(NVT)) {
1888 EVT MemVT = N->getMemoryVT();
1890 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1891 MemVT, isVolatile, isNonTemporal, isInvariant,
1894 // Remember the chain.
1895 Ch = Lo.getValue(1);
1897 if (ExtType == ISD::SEXTLOAD) {
1898 // The high part is obtained by SRA'ing all but one of the bits of the
1900 unsigned LoSize = Lo.getValueType().getSizeInBits();
1901 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1902 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1903 } else if (ExtType == ISD::ZEXTLOAD) {
1904 // The high part is just a zero.
1905 Hi = DAG.getConstant(0, NVT);
1907 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1908 // The high part is undefined.
1909 Hi = DAG.getUNDEF(NVT);
1911 } else if (TLI.isLittleEndian()) {
1912 // Little-endian - low bits are at low addresses.
1913 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1914 isVolatile, isNonTemporal, isInvariant, Alignment,
1917 unsigned ExcessBits =
1918 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1919 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1921 // Increment the pointer to the other half.
1922 unsigned IncrementSize = NVT.getSizeInBits()/8;
1923 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1924 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1925 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1926 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1927 isVolatile, isNonTemporal, isInvariant,
1928 MinAlign(Alignment, IncrementSize), AAInfo);
1930 // Build a factor node to remember that this load is independent of the
1932 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1935 // Big-endian - high bits are at low addresses. Favor aligned loads at
1936 // the cost of some bit-fiddling.
1937 EVT MemVT = N->getMemoryVT();
1938 unsigned EBytes = MemVT.getStoreSize();
1939 unsigned IncrementSize = NVT.getSizeInBits()/8;
1940 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1942 // Load both the high bits and maybe some of the low bits.
1943 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1944 EVT::getIntegerVT(*DAG.getContext(),
1945 MemVT.getSizeInBits() - ExcessBits),
1946 isVolatile, isNonTemporal, isInvariant, Alignment,
1949 // Increment the pointer to the other half.
1950 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1951 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1952 // Load the rest of the low bits.
1953 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1954 N->getPointerInfo().getWithOffset(IncrementSize),
1955 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1956 isVolatile, isNonTemporal, isInvariant,
1957 MinAlign(Alignment, IncrementSize), AAInfo);
1959 // Build a factor node to remember that this load is independent of the
1961 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1964 if (ExcessBits < NVT.getSizeInBits()) {
1965 // Transfer low bits from the bottom of Hi to the top of Lo.
1966 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1967 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1968 DAG.getConstant(ExcessBits,
1969 TLI.getPointerTy())));
1970 // Move high bits to the right position in Hi.
1971 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1973 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1974 TLI.getPointerTy()));
1978 // Legalized the chain result - switch anything that used the old chain to
1980 ReplaceValueWith(SDValue(N, 1), Ch);
1983 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1984 SDValue &Lo, SDValue &Hi) {
1986 SDValue LL, LH, RL, RH;
1987 GetExpandedInteger(N->getOperand(0), LL, LH);
1988 GetExpandedInteger(N->getOperand(1), RL, RH);
1989 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1990 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1993 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1994 SDValue &Lo, SDValue &Hi) {
1995 EVT VT = N->getValueType(0);
1996 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1999 SDValue LL, LH, RL, RH;
2000 GetExpandedInteger(N->getOperand(0), LL, LH);
2001 GetExpandedInteger(N->getOperand(1), RL, RH);
2003 if (TLI.expandMUL(N, Lo, Hi, NVT, DAG, LL, LH, RL, RH))
2006 // If nothing else, we can make a libcall.
2007 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2009 LC = RTLIB::MUL_I16;
2010 else if (VT == MVT::i32)
2011 LC = RTLIB::MUL_I32;
2012 else if (VT == MVT::i64)
2013 LC = RTLIB::MUL_I64;
2014 else if (VT == MVT::i128)
2015 LC = RTLIB::MUL_I128;
2016 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
2018 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2019 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true/*irrelevant*/,
2024 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
2025 SDValue &Lo, SDValue &Hi) {
2026 SDValue LHS = Node->getOperand(0);
2027 SDValue RHS = Node->getOperand(1);
2030 // Expand the result by simply replacing it with the equivalent
2031 // non-overflow-checking operation.
2032 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2033 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2035 SplitInteger(Sum, Lo, Hi);
2037 // Compute the overflow.
2039 // LHSSign -> LHS >= 0
2040 // RHSSign -> RHS >= 0
2041 // SumSign -> Sum >= 0
2044 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2046 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2048 EVT OType = Node->getValueType(1);
2049 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2051 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2052 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2053 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2054 Node->getOpcode() == ISD::SADDO ?
2055 ISD::SETEQ : ISD::SETNE);
2057 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2058 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2060 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2062 // Use the calculated overflow everywhere.
2063 ReplaceValueWith(SDValue(Node, 1), Cmp);
2066 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2067 SDValue &Lo, SDValue &Hi) {
2068 EVT VT = N->getValueType(0);
2071 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2073 LC = RTLIB::SDIV_I16;
2074 else if (VT == MVT::i32)
2075 LC = RTLIB::SDIV_I32;
2076 else if (VT == MVT::i64)
2077 LC = RTLIB::SDIV_I64;
2078 else if (VT == MVT::i128)
2079 LC = RTLIB::SDIV_I128;
2080 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2082 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2083 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2086 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2087 SDValue &Lo, SDValue &Hi) {
2088 EVT VT = N->getValueType(0);
2091 // If we can emit an efficient shift operation, do so now. Check to see if
2092 // the RHS is a constant.
2093 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2094 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2096 // If we can determine that the high bit of the shift is zero or one, even if
2097 // the low bits are variable, emit this shift in an optimized form.
2098 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2101 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2103 if (N->getOpcode() == ISD::SHL) {
2104 PartsOpc = ISD::SHL_PARTS;
2105 } else if (N->getOpcode() == ISD::SRL) {
2106 PartsOpc = ISD::SRL_PARTS;
2108 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2109 PartsOpc = ISD::SRA_PARTS;
2112 // Next check to see if the target supports this SHL_PARTS operation or if it
2113 // will custom expand it.
2114 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2115 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2116 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2117 Action == TargetLowering::Custom) {
2118 // Expand the subcomponents.
2120 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2121 EVT VT = LHSL.getValueType();
2123 // If the shift amount operand is coming from a vector legalization it may
2124 // have an illegal type. Fix that first by casting the operand, otherwise
2125 // the new SHL_PARTS operation would need further legalization.
2126 SDValue ShiftOp = N->getOperand(1);
2127 EVT ShiftTy = TLI.getShiftAmountTy(VT);
2128 assert(ShiftTy.getScalarType().getSizeInBits() >=
2129 Log2_32_Ceil(VT.getScalarType().getSizeInBits()) &&
2130 "ShiftAmountTy is too small to cover the range of this type!");
2131 if (ShiftOp.getValueType() != ShiftTy)
2132 ShiftOp = DAG.getZExtOrTrunc(ShiftOp, dl, ShiftTy);
2134 SDValue Ops[] = { LHSL, LHSH, ShiftOp };
2135 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops);
2136 Hi = Lo.getValue(1);
2140 // Otherwise, emit a libcall.
2141 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2143 if (N->getOpcode() == ISD::SHL) {
2144 isSigned = false; /*sign irrelevant*/
2146 LC = RTLIB::SHL_I16;
2147 else if (VT == MVT::i32)
2148 LC = RTLIB::SHL_I32;
2149 else if (VT == MVT::i64)
2150 LC = RTLIB::SHL_I64;
2151 else if (VT == MVT::i128)
2152 LC = RTLIB::SHL_I128;
2153 } else if (N->getOpcode() == ISD::SRL) {
2156 LC = RTLIB::SRL_I16;
2157 else if (VT == MVT::i32)
2158 LC = RTLIB::SRL_I32;
2159 else if (VT == MVT::i64)
2160 LC = RTLIB::SRL_I64;
2161 else if (VT == MVT::i128)
2162 LC = RTLIB::SRL_I128;
2164 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2167 LC = RTLIB::SRA_I16;
2168 else if (VT == MVT::i32)
2169 LC = RTLIB::SRA_I32;
2170 else if (VT == MVT::i64)
2171 LC = RTLIB::SRA_I64;
2172 else if (VT == MVT::i128)
2173 LC = RTLIB::SRA_I128;
2176 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2177 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2178 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, isSigned, dl).first, Lo,
2183 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2184 llvm_unreachable("Unsupported shift!");
2187 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2188 SDValue &Lo, SDValue &Hi) {
2189 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2191 SDValue Op = N->getOperand(0);
2192 if (Op.getValueType().bitsLE(NVT)) {
2193 // The low part is sign extension of the input (degenerates to a copy).
2194 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2195 // The high part is obtained by SRA'ing all but one of the bits of low part.
2196 unsigned LoSize = NVT.getSizeInBits();
2197 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2198 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2200 // For example, extension of an i48 to an i64. The operand type necessarily
2201 // promotes to the result type, so will end up being expanded too.
2202 assert(getTypeAction(Op.getValueType()) ==
2203 TargetLowering::TypePromoteInteger &&
2204 "Only know how to promote this result!");
2205 SDValue Res = GetPromotedInteger(Op);
2206 assert(Res.getValueType() == N->getValueType(0) &&
2207 "Operand over promoted?");
2208 // Split the promoted operand. This will simplify when it is expanded.
2209 SplitInteger(Res, Lo, Hi);
2210 unsigned ExcessBits =
2211 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2212 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2213 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2218 void DAGTypeLegalizer::
2219 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2221 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2222 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2224 if (EVT.bitsLE(Lo.getValueType())) {
2225 // sext_inreg the low part if needed.
2226 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2229 // The high part gets the sign extension from the lo-part. This handles
2230 // things like sextinreg V:i64 from i8.
2231 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2232 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2233 TLI.getPointerTy()));
2235 // For example, extension of an i48 to an i64. Leave the low part alone,
2236 // sext_inreg the high part.
2237 unsigned ExcessBits =
2238 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2239 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2240 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2245 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2246 SDValue &Lo, SDValue &Hi) {
2247 EVT VT = N->getValueType(0);
2250 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2252 LC = RTLIB::SREM_I16;
2253 else if (VT == MVT::i32)
2254 LC = RTLIB::SREM_I32;
2255 else if (VT == MVT::i64)
2256 LC = RTLIB::SREM_I64;
2257 else if (VT == MVT::i128)
2258 LC = RTLIB::SREM_I128;
2259 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2261 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2262 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, true, dl).first, Lo, Hi);
2265 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2266 SDValue &Lo, SDValue &Hi) {
2267 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2269 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2270 Hi = DAG.getNode(ISD::SRL, dl,
2271 N->getOperand(0).getValueType(), N->getOperand(0),
2272 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2273 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2276 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2277 SDValue &Lo, SDValue &Hi) {
2278 SDValue LHS = N->getOperand(0);
2279 SDValue RHS = N->getOperand(1);
2282 // Expand the result by simply replacing it with the equivalent
2283 // non-overflow-checking operation.
2284 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2285 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2287 SplitInteger(Sum, Lo, Hi);
2289 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2290 // overflows iff a - b > a.
2291 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2292 N->getOpcode () == ISD::UADDO ?
2293 ISD::SETULT : ISD::SETUGT);
2295 // Use the calculated overflow everywhere.
2296 ReplaceValueWith(SDValue(N, 1), Ofl);
2299 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2300 SDValue &Lo, SDValue &Hi) {
2301 EVT VT = N->getValueType(0);
2304 // A divide for UMULO should be faster than a function call.
2305 if (N->getOpcode() == ISD::UMULO) {
2306 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2308 SDValue MUL = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
2309 SplitInteger(MUL, Lo, Hi);
2311 // A divide for UMULO will be faster than a function call. Select to
2312 // make sure we aren't using 0.
2313 SDValue isZero = DAG.getSetCC(dl, getSetCCResultType(VT),
2314 RHS, DAG.getConstant(0, VT), ISD::SETEQ);
2315 SDValue NotZero = DAG.getSelect(dl, VT, isZero,
2316 DAG.getConstant(1, VT), RHS);
2317 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero);
2318 SDValue Overflow = DAG.getSetCC(dl, N->getValueType(1), DIV, LHS,
2320 Overflow = DAG.getSelect(dl, N->getValueType(1), isZero,
2321 DAG.getConstant(0, N->getValueType(1)),
2323 ReplaceValueWith(SDValue(N, 1), Overflow);
2327 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2328 EVT PtrVT = TLI.getPointerTy();
2329 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2331 // Replace this with a libcall that will check overflow.
2332 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2334 LC = RTLIB::MULO_I32;
2335 else if (VT == MVT::i64)
2336 LC = RTLIB::MULO_I64;
2337 else if (VT == MVT::i128)
2338 LC = RTLIB::MULO_I128;
2339 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2341 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2342 // Temporary for the overflow value, default it to zero.
2343 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2344 DAG.getConstant(0, PtrVT), Temp,
2345 MachinePointerInfo(), false, false, 0);
2347 TargetLowering::ArgListTy Args;
2348 TargetLowering::ArgListEntry Entry;
2349 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2350 EVT ArgVT = N->getOperand(i).getValueType();
2351 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2352 Entry.Node = N->getOperand(i);
2354 Entry.isSExt = true;
2355 Entry.isZExt = false;
2356 Args.push_back(Entry);
2359 // Also pass the address of the overflow check.
2361 Entry.Ty = PtrTy->getPointerTo();
2362 Entry.isSExt = true;
2363 Entry.isZExt = false;
2364 Args.push_back(Entry);
2366 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2368 TargetLowering::CallLoweringInfo CLI(DAG);
2369 CLI.setDebugLoc(dl).setChain(Chain)
2370 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Func, std::move(Args), 0)
2373 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2375 SplitInteger(CallInfo.first, Lo, Hi);
2376 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2377 MachinePointerInfo(), false, false, false, 0);
2378 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2379 DAG.getConstant(0, PtrVT),
2381 // Use the overflow from the libcall everywhere.
2382 ReplaceValueWith(SDValue(N, 1), Ofl);
2385 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2386 SDValue &Lo, SDValue &Hi) {
2387 EVT VT = N->getValueType(0);
2390 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2392 LC = RTLIB::UDIV_I16;
2393 else if (VT == MVT::i32)
2394 LC = RTLIB::UDIV_I32;
2395 else if (VT == MVT::i64)
2396 LC = RTLIB::UDIV_I64;
2397 else if (VT == MVT::i128)
2398 LC = RTLIB::UDIV_I128;
2399 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2401 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2402 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2405 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2406 SDValue &Lo, SDValue &Hi) {
2407 EVT VT = N->getValueType(0);
2410 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2412 LC = RTLIB::UREM_I16;
2413 else if (VT == MVT::i32)
2414 LC = RTLIB::UREM_I32;
2415 else if (VT == MVT::i64)
2416 LC = RTLIB::UREM_I64;
2417 else if (VT == MVT::i128)
2418 LC = RTLIB::UREM_I128;
2419 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2421 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2422 SplitInteger(TLI.makeLibCall(DAG, LC, VT, Ops, 2, false, dl).first, Lo, Hi);
2425 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2426 SDValue &Lo, SDValue &Hi) {
2427 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2429 SDValue Op = N->getOperand(0);
2430 if (Op.getValueType().bitsLE(NVT)) {
2431 // The low part is zero extension of the input (degenerates to a copy).
2432 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2433 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2435 // For example, extension of an i48 to an i64. The operand type necessarily
2436 // promotes to the result type, so will end up being expanded too.
2437 assert(getTypeAction(Op.getValueType()) ==
2438 TargetLowering::TypePromoteInteger &&
2439 "Only know how to promote this result!");
2440 SDValue Res = GetPromotedInteger(Op);
2441 assert(Res.getValueType() == N->getValueType(0) &&
2442 "Operand over promoted?");
2443 // Split the promoted operand. This will simplify when it is expanded.
2444 SplitInteger(Res, Lo, Hi);
2445 unsigned ExcessBits =
2446 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2447 Hi = DAG.getZeroExtendInReg(Hi, dl,
2448 EVT::getIntegerVT(*DAG.getContext(),
2453 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2454 SDValue &Lo, SDValue &Hi) {
2456 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2457 SDVTList VTs = DAG.getVTList(VT, MVT::i1, MVT::Other);
2458 SDValue Zero = DAG.getConstant(0, VT);
2459 SDValue Swap = DAG.getAtomicCmpSwap(
2460 ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, dl,
2461 cast<AtomicSDNode>(N)->getMemoryVT(), VTs, N->getOperand(0),
2462 N->getOperand(1), Zero, Zero, cast<AtomicSDNode>(N)->getMemOperand(),
2463 cast<AtomicSDNode>(N)->getOrdering(),
2464 cast<AtomicSDNode>(N)->getOrdering(),
2465 cast<AtomicSDNode>(N)->getSynchScope());
2467 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2468 ReplaceValueWith(SDValue(N, 1), Swap.getValue(2));
2471 //===----------------------------------------------------------------------===//
2472 // Integer Operand Expansion
2473 //===----------------------------------------------------------------------===//
2475 /// ExpandIntegerOperand - This method is called when the specified operand of
2476 /// the specified node is found to need expansion. At this point, all of the
2477 /// result types of the node are known to be legal, but other operands of the
2478 /// node may need promotion or expansion as well as the specified one.
2479 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2480 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2481 SDValue Res = SDValue();
2483 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2486 switch (N->getOpcode()) {
2489 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2490 N->dump(&DAG); dbgs() << "\n";
2492 llvm_unreachable("Do not know how to expand this operator's operand!");
2494 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2495 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2496 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2497 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2498 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2499 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2500 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2501 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2502 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2503 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2504 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2505 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2511 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2512 case ISD::RETURNADDR:
2513 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2515 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2518 // If the result is null, the sub-method took care of registering results etc.
2519 if (!Res.getNode()) return false;
2521 // If the result is N, the sub-method updated N in place. Tell the legalizer
2523 if (Res.getNode() == N)
2526 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2527 "Invalid operand expansion");
2529 ReplaceValueWith(SDValue(N, 0), Res);
2533 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2534 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2535 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2537 ISD::CondCode &CCCode,
2539 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2540 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2541 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2543 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2544 if (RHSLo == RHSHi) {
2545 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2546 if (RHSCST->isAllOnesValue()) {
2547 // Equality comparison to -1.
2548 NewLHS = DAG.getNode(ISD::AND, dl,
2549 LHSLo.getValueType(), LHSLo, LHSHi);
2556 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2557 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2558 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2559 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2563 // If this is a comparison of the sign bit, just look at the top part.
2565 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2566 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2567 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2573 // FIXME: This generated code sucks.
2574 ISD::CondCode LowCC;
2576 default: llvm_unreachable("Unknown integer setcc!");
2578 case ISD::SETULT: LowCC = ISD::SETULT; break;
2580 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2582 case ISD::SETULE: LowCC = ISD::SETULE; break;
2584 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2587 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2588 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2589 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2591 // NOTE: on targets without efficient SELECT of bools, we can always use
2592 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2593 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, AfterLegalizeTypes, true,
2596 if (TLI.isTypeLegal(LHSLo.getValueType()) &&
2597 TLI.isTypeLegal(RHSLo.getValueType()))
2598 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2599 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2600 if (!Tmp1.getNode())
2601 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2602 LHSLo, RHSLo, LowCC);
2603 if (TLI.isTypeLegal(LHSHi.getValueType()) &&
2604 TLI.isTypeLegal(RHSHi.getValueType()))
2605 Tmp2 = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2606 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2607 if (!Tmp2.getNode())
2608 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2609 getSetCCResultType(LHSHi.getValueType()),
2610 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2612 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2613 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2614 if ((Tmp1C && Tmp1C->isNullValue()) ||
2615 (Tmp2C && Tmp2C->isNullValue() &&
2616 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2617 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2618 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2619 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2620 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2621 // low part is known false, returns high part.
2622 // For LE / GE, if high part is known false, ignore the low part.
2623 // For LT / GT, if high part is known true, ignore the low part.
2629 NewLHS = TLI.SimplifySetCC(getSetCCResultType(LHSHi.getValueType()),
2630 LHSHi, RHSHi, ISD::SETEQ, false,
2631 DagCombineInfo, dl);
2632 if (!NewLHS.getNode())
2633 NewLHS = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
2634 LHSHi, RHSHi, ISD::SETEQ);
2635 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2636 NewLHS, Tmp1, Tmp2);
2640 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2641 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2642 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2643 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2645 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2646 // against zero to select between true and false values.
2647 if (!NewRHS.getNode()) {
2648 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2649 CCCode = ISD::SETNE;
2652 // Update N to have the operands specified.
2653 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2654 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2655 N->getOperand(4)), 0);
2658 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2659 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2660 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2661 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2663 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2664 // against zero to select between true and false values.
2665 if (!NewRHS.getNode()) {
2666 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2667 CCCode = ISD::SETNE;
2670 // Update N to have the operands specified.
2671 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2672 N->getOperand(2), N->getOperand(3),
2673 DAG.getCondCode(CCCode)), 0);
2676 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2677 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2678 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2679 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, SDLoc(N));
2681 // If ExpandSetCCOperands returned a scalar, use it.
2682 if (!NewRHS.getNode()) {
2683 assert(NewLHS.getValueType() == N->getValueType(0) &&
2684 "Unexpected setcc expansion!");
2688 // Otherwise, update N to have the operands specified.
2689 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2690 DAG.getCondCode(CCCode)), 0);
2693 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2694 // The value being shifted is legal, but the shift amount is too big.
2695 // It follows that either the result of the shift is undefined, or the
2696 // upper half of the shift amount is zero. Just use the lower half.
2698 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2699 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2702 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2703 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2704 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2705 // constant to valid type.
2707 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2708 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2711 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2712 SDValue Op = N->getOperand(0);
2713 EVT DstVT = N->getValueType(0);
2714 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2715 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2716 "Don't know how to expand this SINT_TO_FP!");
2717 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, SDLoc(N)).first;
2720 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2721 if (ISD::isNormalStore(N))
2722 return ExpandOp_NormalStore(N, OpNo);
2724 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2725 assert(OpNo == 1 && "Can only expand the stored value so far");
2727 EVT VT = N->getOperand(1).getValueType();
2728 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2729 SDValue Ch = N->getChain();
2730 SDValue Ptr = N->getBasePtr();
2731 unsigned Alignment = N->getAlignment();
2732 bool isVolatile = N->isVolatile();
2733 bool isNonTemporal = N->isNonTemporal();
2734 AAMDNodes AAInfo = N->getAAInfo();
2738 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2740 if (N->getMemoryVT().bitsLE(NVT)) {
2741 GetExpandedInteger(N->getValue(), Lo, Hi);
2742 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2743 N->getMemoryVT(), isVolatile, isNonTemporal,
2747 if (TLI.isLittleEndian()) {
2748 // Little-endian - low bits are at low addresses.
2749 GetExpandedInteger(N->getValue(), Lo, Hi);
2751 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2752 isVolatile, isNonTemporal, Alignment, AAInfo);
2754 unsigned ExcessBits =
2755 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2756 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2758 // Increment the pointer to the other half.
2759 unsigned IncrementSize = NVT.getSizeInBits()/8;
2760 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2761 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2762 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2763 N->getPointerInfo().getWithOffset(IncrementSize),
2764 NEVT, isVolatile, isNonTemporal,
2765 MinAlign(Alignment, IncrementSize), AAInfo);
2766 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2769 // Big-endian - high bits are at low addresses. Favor aligned stores at
2770 // the cost of some bit-fiddling.
2771 GetExpandedInteger(N->getValue(), Lo, Hi);
2773 EVT ExtVT = N->getMemoryVT();
2774 unsigned EBytes = ExtVT.getStoreSize();
2775 unsigned IncrementSize = NVT.getSizeInBits()/8;
2776 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2777 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2778 ExtVT.getSizeInBits() - ExcessBits);
2780 if (ExcessBits < NVT.getSizeInBits()) {
2781 // Transfer high bits from the top of Lo to the bottom of Hi.
2782 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2783 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2784 TLI.getPointerTy()));
2785 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2786 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2787 DAG.getConstant(ExcessBits,
2788 TLI.getPointerTy())));
2791 // Store both the high bits and maybe some of the low bits.
2792 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2793 HiVT, isVolatile, isNonTemporal, Alignment, AAInfo);
2795 // Increment the pointer to the other half.
2796 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2797 DAG.getConstant(IncrementSize, Ptr.getValueType()));
2798 // Store the lowest ExcessBits bits in the second half.
2799 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2800 N->getPointerInfo().getWithOffset(IncrementSize),
2801 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2802 isVolatile, isNonTemporal,
2803 MinAlign(Alignment, IncrementSize), AAInfo);
2804 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2807 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2809 GetExpandedInteger(N->getOperand(0), InL, InH);
2810 // Just truncate the low part of the source.
2811 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), InL);
2814 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2815 SDValue Op = N->getOperand(0);
2816 EVT SrcVT = Op.getValueType();
2817 EVT DstVT = N->getValueType(0);
2820 // The following optimization is valid only if every value in SrcVT (when
2821 // treated as signed) is representable in DstVT. Check that the mantissa
2822 // size of DstVT is >= than the number of bits in SrcVT -1.
2823 const fltSemantics &sem = DAG.EVTToAPFloatSemantics(DstVT);
2824 if (APFloat::semanticsPrecision(sem) >= SrcVT.getSizeInBits()-1 &&
2825 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2826 // Do a signed conversion then adjust the result.
2827 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2828 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2830 // The result of the signed conversion needs adjusting if the 'sign bit' of
2831 // the incoming integer was set. To handle this, we dynamically test to see
2832 // if it is set, and, if so, add a fudge factor.
2834 const uint64_t F32TwoE32 = 0x4F800000ULL;
2835 const uint64_t F32TwoE64 = 0x5F800000ULL;
2836 const uint64_t F32TwoE128 = 0x7F800000ULL;
2839 if (SrcVT == MVT::i32)
2840 FF = APInt(32, F32TwoE32);
2841 else if (SrcVT == MVT::i64)
2842 FF = APInt(32, F32TwoE64);
2843 else if (SrcVT == MVT::i128)
2844 FF = APInt(32, F32TwoE128);
2846 llvm_unreachable("Unsupported UINT_TO_FP!");
2848 // Check whether the sign bit is set.
2850 GetExpandedInteger(Op, Lo, Hi);
2851 SDValue SignSet = DAG.getSetCC(dl,
2852 getSetCCResultType(Hi.getValueType()),
2853 Hi, DAG.getConstant(0, Hi.getValueType()),
2856 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2857 SDValue FudgePtr = DAG.getConstantPool(
2858 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2859 TLI.getPointerTy());
2861 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2862 SDValue Zero = DAG.getIntPtrConstant(0);
2863 SDValue Four = DAG.getIntPtrConstant(4);
2864 if (TLI.isBigEndian()) std::swap(Zero, Four);
2865 SDValue Offset = DAG.getSelect(dl, Zero.getValueType(), SignSet,
2867 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2868 FudgePtr = DAG.getNode(ISD::ADD, dl, FudgePtr.getValueType(),
2870 Alignment = std::min(Alignment, 4u);
2872 // Load the value out, extending it from f32 to the destination float type.
2873 // FIXME: Avoid the extend by constructing the right constant pool?
2874 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2876 MachinePointerInfo::getConstantPool(),
2878 false, false, false, Alignment);
2879 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2882 // Otherwise, use a libcall.
2883 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2884 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2885 "Don't know how to expand this UINT_TO_FP!");
2886 return TLI.makeLibCall(DAG, LC, DstVT, &Op, 1, true, dl).first;
2889 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2891 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2892 cast<AtomicSDNode>(N)->getMemoryVT(),
2894 N->getOperand(1), N->getOperand(2),
2895 cast<AtomicSDNode>(N)->getMemOperand(),
2896 cast<AtomicSDNode>(N)->getOrdering(),
2897 cast<AtomicSDNode>(N)->getSynchScope());
2898 return Swap.getValue(1);
2902 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2903 SDValue InOp0 = N->getOperand(0);
2904 EVT InVT = InOp0.getValueType();
2906 EVT OutVT = N->getValueType(0);
2907 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2908 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2909 unsigned OutNumElems = OutVT.getVectorNumElements();
2910 EVT NOutVTElem = NOutVT.getVectorElementType();
2913 SDValue BaseIdx = N->getOperand(1);
2915 SmallVector<SDValue, 8> Ops;
2916 Ops.reserve(OutNumElems);
2917 for (unsigned i = 0; i != OutNumElems; ++i) {
2919 // Extract the element from the original vector.
2920 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2921 BaseIdx, DAG.getConstant(i, BaseIdx.getValueType()));
2922 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2923 InVT.getVectorElementType(), N->getOperand(0), Index);
2925 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2926 // Insert the converted element to the new vector.
2930 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2934 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2935 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2936 EVT VT = N->getValueType(0);
2939 unsigned NumElts = VT.getVectorNumElements();
2940 SmallVector<int, 8> NewMask;
2941 for (unsigned i = 0; i != NumElts; ++i) {
2942 NewMask.push_back(SV->getMaskElt(i));
2945 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2946 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2947 EVT OutVT = V0.getValueType();
2949 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2953 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2954 EVT OutVT = N->getValueType(0);
2955 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2956 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2957 unsigned NumElems = N->getNumOperands();
2958 EVT NOutVTElem = NOutVT.getVectorElementType();
2962 SmallVector<SDValue, 8> Ops;
2963 Ops.reserve(NumElems);
2964 for (unsigned i = 0; i != NumElems; ++i) {
2966 // BUILD_VECTOR integer operand types are allowed to be larger than the
2967 // result's element type. This may still be true after the promotion. For
2968 // example, we might be promoting (<v?i1> = BV <i32>, <i32>, ...) to
2969 // (v?i16 = BV <i32>, <i32>, ...), and we can't any_extend <i32> to <i16>.
2970 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem))
2971 Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2973 Op = N->getOperand(i);
2977 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
2980 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2984 assert(!N->getOperand(0).getValueType().isVector() &&
2985 "Input must be a scalar");
2987 EVT OutVT = N->getValueType(0);
2988 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2989 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2990 EVT NOutVTElem = NOutVT.getVectorElementType();
2992 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2994 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2997 SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
3000 EVT OutVT = N->getValueType(0);
3001 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3002 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3004 EVT InElemTy = OutVT.getVectorElementType();
3005 EVT OutElemTy = NOutVT.getVectorElementType();
3007 unsigned NumElem = N->getOperand(0).getValueType().getVectorNumElements();
3008 unsigned NumOutElem = NOutVT.getVectorNumElements();
3009 unsigned NumOperands = N->getNumOperands();
3010 assert(NumElem * NumOperands == NumOutElem &&
3011 "Unexpected number of elements");
3013 // Take the elements from the first vector.
3014 SmallVector<SDValue, 8> Ops(NumOutElem);
3015 for (unsigned i = 0; i < NumOperands; ++i) {
3016 SDValue Op = N->getOperand(i);
3017 for (unsigned j = 0; j < NumElem; ++j) {
3018 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3019 InElemTy, Op, DAG.getConstant(j,
3020 TLI.getVectorIdxTy()));
3021 Ops[i * NumElem + j] = DAG.getNode(ISD::ANY_EXTEND, dl, OutElemTy, Ext);
3025 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
3028 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
3029 EVT OutVT = N->getValueType(0);
3030 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
3031 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
3033 EVT NOutVTElem = NOutVT.getVectorElementType();
3036 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3038 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
3039 NOutVTElem, N->getOperand(1));
3040 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
3041 V0, ConvElem, N->getOperand(2));
3044 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
3046 SDValue V0 = GetPromotedInteger(N->getOperand(0));
3047 SDValue V1 = DAG.getZExtOrTrunc(N->getOperand(1), dl, TLI.getVectorIdxTy());
3048 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3049 V0->getValueType(0).getScalarType(), V0, V1);
3051 // EXTRACT_VECTOR_ELT can return types which are wider than the incoming
3052 // element types. If this is the case then we need to expand the outgoing
3053 // value and not truncate it.
3054 return DAG.getAnyExtOrTrunc(Ext, dl, N->getValueType(0));
3057 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
3059 unsigned NumElems = N->getNumOperands();
3061 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
3063 SmallVector<SDValue, 8> NewOps;
3064 NewOps.reserve(NumElems);
3066 // For each incoming vector
3067 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
3068 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
3069 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
3070 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
3072 for (unsigned i=0; i<NumElem; ++i) {
3073 // Extract element from incoming vector
3074 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
3075 Incoming, DAG.getConstant(i, TLI.getVectorIdxTy()));
3076 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
3077 NewOps.push_back(Tr);
3081 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0), NewOps);