1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
23 #include "llvm/Support/ErrorHandling.h"
26 //===----------------------------------------------------------------------===//
27 // Integer Result Promotion
28 //===----------------------------------------------------------------------===//
30 /// PromoteIntegerResult - This method is called when a result of a node is
31 /// found to be in need of promotion to a larger type. At this point, the node
32 /// may also have invalid operands or may have other results that need
33 /// expansion, we just know that (at least) one result needs promotion.
34 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
35 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
36 SDValue Res = SDValue();
38 // See if the target wants to custom expand this node.
39 if (CustomLowerNode(N, N->getValueType(ResNo), true))
42 switch (N->getOpcode()) {
45 cerr << "PromoteIntegerResult #" << ResNo << ": ";
46 N->dump(&DAG); cerr << "\n";
48 LLVM_UNREACHABLE("Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
215 CreateStackStoreLoad(InOp, OutVT));
218 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
219 SDValue Op = GetPromotedInteger(N->getOperand(0));
220 MVT OVT = N->getValueType(0);
221 MVT NVT = Op.getValueType();
222 DebugLoc dl = N->getDebugLoc();
224 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
225 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
226 DAG.getConstant(DiffBits, TLI.getPointerTy()));
229 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
230 // The pair element type may be legal, or may not promote to the same type as
231 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
232 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
233 TLI.getTypeToTransformTo(N->getValueType(0)),
234 JoinIntegers(N->getOperand(0), N->getOperand(1)));
237 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
238 MVT VT = N->getValueType(0);
239 // FIXME there is no actual debug info here
240 DebugLoc dl = N->getDebugLoc();
241 // Zero extend things like i1, sign extend everything else. It shouldn't
242 // matter in theory which one we pick, but this tends to give better code?
243 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
244 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
246 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
250 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
251 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
252 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
253 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
254 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
255 "can only promote integers");
256 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
257 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
258 N->getOperand(1), N->getOperand(2),
259 N->getOperand(3), N->getOperand(4), CvtCode);
262 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
263 // Zero extend to the promoted type and do the count there.
264 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
265 DebugLoc dl = N->getDebugLoc();
266 MVT OVT = N->getValueType(0);
267 MVT NVT = Op.getValueType();
268 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
269 // Subtract off the extra leading bits in the bigger type.
270 return DAG.getNode(ISD::SUB, dl, NVT, Op,
271 DAG.getConstant(NVT.getSizeInBits() -
272 OVT.getSizeInBits(), NVT));
275 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
276 // Zero extend to the promoted type and do the count there.
277 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
278 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
281 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
282 SDValue Op = GetPromotedInteger(N->getOperand(0));
283 MVT OVT = N->getValueType(0);
284 MVT NVT = Op.getValueType();
285 DebugLoc dl = N->getDebugLoc();
286 // The count is the same in the promoted type except if the original
287 // value was zero. This can be handled by setting the bit just off
288 // the top of the original type.
289 APInt TopBit(NVT.getSizeInBits(), 0);
290 TopBit.set(OVT.getSizeInBits());
291 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
292 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
295 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
296 DebugLoc dl = N->getDebugLoc();
297 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
298 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
302 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
303 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
304 unsigned NewOpc = N->getOpcode();
305 DebugLoc dl = N->getDebugLoc();
307 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
308 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
309 // and SINT conversions are Custom, there is no way to tell which is preferable.
310 // We choose SINT because that's the right thing on PPC.)
311 if (N->getOpcode() == ISD::FP_TO_UINT &&
312 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
313 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
314 NewOpc = ISD::FP_TO_SINT;
316 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
318 // Assert that the converted value fits in the original type. If it doesn't
319 // (eg: because the value being converted is too big), then the result of the
320 // original operation was undefined anyway, so the assert is still correct.
321 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
322 ISD::AssertZext : ISD::AssertSext, dl,
323 NVT, Res, DAG.getValueType(N->getValueType(0)));
326 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
327 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
328 DebugLoc dl = N->getDebugLoc();
330 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
331 SDValue Res = GetPromotedInteger(N->getOperand(0));
332 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
334 // If the result and operand types are the same after promotion, simplify
335 // to an in-register extension.
336 if (NVT == Res.getValueType()) {
337 // The high bits are not guaranteed to be anything. Insert an extend.
338 if (N->getOpcode() == ISD::SIGN_EXTEND)
339 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
340 DAG.getValueType(N->getOperand(0).getValueType()));
341 if (N->getOpcode() == ISD::ZERO_EXTEND)
342 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
343 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
348 // Otherwise, just extend the original operand all the way to the larger type.
349 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
352 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
353 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
354 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
355 ISD::LoadExtType ExtType =
356 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
357 DebugLoc dl = N->getDebugLoc();
358 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
359 N->getSrcValue(), N->getSrcValueOffset(),
360 N->getMemoryVT(), N->isVolatile(),
363 // Legalized the chain result - switch anything that used the old chain to
365 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
369 /// Promote the overflow flag of an overflowing arithmetic node.
370 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
371 // Simply change the return type of the boolean result.
372 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
373 MVT ValueVTs[] = { N->getValueType(0), NVT };
374 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
375 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
376 DAG.getVTList(ValueVTs, 2), Ops, 2);
378 // Modified the sum result - switch anything that used the old sum to use
380 ReplaceValueWith(SDValue(N, 0), Res);
382 return SDValue(Res.getNode(), 1);
385 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
387 return PromoteIntRes_Overflow(N);
389 // The operation overflowed iff the result in the larger type is not the
390 // sign extension of its truncation to the original type.
391 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
392 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
393 MVT OVT = N->getOperand(0).getValueType();
394 MVT NVT = LHS.getValueType();
395 DebugLoc dl = N->getDebugLoc();
397 // Do the arithmetic in the larger type.
398 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
399 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
401 // Calculate the overflow flag: sign extend the arithmetic result from
402 // the original type.
403 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
404 DAG.getValueType(OVT));
405 // Overflowed if and only if this is not equal to Res.
406 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
408 // Use the calculated overflow everywhere.
409 ReplaceValueWith(SDValue(N, 1), Ofl);
414 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
415 // Sign extend the input.
416 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
417 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
418 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
419 LHS.getValueType(), LHS, RHS);
422 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
423 SDValue LHS = GetPromotedInteger(N->getOperand(1));
424 SDValue RHS = GetPromotedInteger(N->getOperand(2));
425 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
426 LHS.getValueType(), N->getOperand(0),LHS,RHS);
429 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
430 SDValue LHS = GetPromotedInteger(N->getOperand(2));
431 SDValue RHS = GetPromotedInteger(N->getOperand(3));
432 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
433 LHS.getValueType(), N->getOperand(0),
434 N->getOperand(1), LHS, RHS, N->getOperand(4));
437 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
438 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
439 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
440 DebugLoc dl = N->getDebugLoc();
442 // Get the SETCC result using the canonical SETCC type.
443 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
444 N->getOperand(1), N->getOperand(2));
446 // Convert to the expected type.
447 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
448 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
449 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
452 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
453 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
454 TLI.getTypeToTransformTo(N->getValueType(0)),
455 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
458 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
459 SDValue Op = GetPromotedInteger(N->getOperand(0));
460 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
461 Op.getValueType(), Op, N->getOperand(1));
464 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
465 // The input may have strange things in the top bits of the registers, but
466 // these operations don't care. They may have weird bits going out, but
467 // that too is okay if they are integer operations.
468 SDValue LHS = GetPromotedInteger(N->getOperand(0));
469 SDValue RHS = GetPromotedInteger(N->getOperand(1));
470 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
471 LHS.getValueType(), LHS, RHS);
474 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
475 // The input value must be properly sign extended.
476 SDValue Res = SExtPromotedInteger(N->getOperand(0));
477 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
478 Res.getValueType(), Res, N->getOperand(1));
481 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
482 // The input value must be properly zero extended.
483 MVT VT = N->getValueType(0);
484 MVT NVT = TLI.getTypeToTransformTo(VT);
485 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
486 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
489 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
490 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
493 switch (getTypeAction(N->getOperand(0).getValueType())) {
494 default: LLVM_UNREACHABLE("Unknown type action!");
497 Res = N->getOperand(0);
500 Res = GetPromotedInteger(N->getOperand(0));
504 // Truncate to NVT instead of VT
505 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
508 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
510 return PromoteIntRes_Overflow(N);
512 // The operation overflowed iff the result in the larger type is not the
513 // zero extension of its truncation to the original type.
514 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
515 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
516 MVT OVT = N->getOperand(0).getValueType();
517 MVT NVT = LHS.getValueType();
518 DebugLoc dl = N->getDebugLoc();
520 // Do the arithmetic in the larger type.
521 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
522 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
524 // Calculate the overflow flag: zero extend the arithmetic result from
525 // the original type.
526 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
527 // Overflowed if and only if this is not equal to Res.
528 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
530 // Use the calculated overflow everywhere.
531 ReplaceValueWith(SDValue(N, 1), Ofl);
536 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
537 // Zero extend the input.
538 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
539 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
540 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
541 LHS.getValueType(), LHS, RHS);
544 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
545 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
548 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
549 SDValue Chain = N->getOperand(0); // Get the chain.
550 SDValue Ptr = N->getOperand(1); // Get the pointer.
551 MVT VT = N->getValueType(0);
552 DebugLoc dl = N->getDebugLoc();
554 MVT RegVT = TLI.getRegisterType(VT);
555 unsigned NumRegs = TLI.getNumRegisters(VT);
556 // The argument is passed as NumRegs registers of type RegVT.
558 SmallVector<SDValue, 8> Parts(NumRegs);
559 for (unsigned i = 0; i < NumRegs; ++i) {
560 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
561 Chain = Parts[i].getValue(1);
564 // Handle endianness of the load.
565 if (TLI.isBigEndian())
566 std::reverse(Parts.begin(), Parts.end());
568 // Assemble the parts in the promoted type.
569 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
570 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
571 for (unsigned i = 1; i < NumRegs; ++i) {
572 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
573 // Shift it to the right position and "or" it in.
574 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
575 DAG.getConstant(i * RegVT.getSizeInBits(),
576 TLI.getPointerTy()));
577 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
580 // Modified the chain result - switch anything that used the old chain to
582 ReplaceValueWith(SDValue(N, 1), Chain);
587 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
588 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
589 return PromoteIntRes_Overflow(N);
592 //===----------------------------------------------------------------------===//
593 // Integer Operand Promotion
594 //===----------------------------------------------------------------------===//
596 /// PromoteIntegerOperand - This method is called when the specified operand of
597 /// the specified node is found to need promotion. At this point, all of the
598 /// result types of the node are known to be legal, but other operands of the
599 /// node may need promotion or expansion as well as the specified one.
600 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
601 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
602 SDValue Res = SDValue();
604 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
607 switch (N->getOpcode()) {
610 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
611 N->dump(&DAG); cerr << "\n";
613 LLVM_UNREACHABLE("Do not know how to promote this operator's operand!");
615 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
616 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
617 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
618 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
619 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
620 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
621 case ISD::CONVERT_RNDSAT:
622 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
623 case ISD::INSERT_VECTOR_ELT:
624 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
625 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
626 case ISD::SCALAR_TO_VECTOR:
627 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
628 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
629 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
630 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
631 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
632 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
633 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
635 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
636 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
637 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
643 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
646 // If the result is null, the sub-method took care of registering results etc.
647 if (!Res.getNode()) return false;
649 // If the result is N, the sub-method updated N in place. Tell the legalizer
651 if (Res.getNode() == N)
654 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
655 "Invalid operand expansion");
657 ReplaceValueWith(SDValue(N, 0), Res);
661 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
662 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
663 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
664 ISD::CondCode CCCode) {
665 // We have to insert explicit sign or zero extends. Note that we could
666 // insert sign extends for ALL conditions, but zero extend is cheaper on
667 // many machines (an AND instead of two shifts), so prefer it.
669 default: LLVM_UNREACHABLE("Unknown integer comparison!");
676 // ALL of these operations will work if we either sign or zero extend
677 // the operands (including the unsigned comparisons!). Zero extend is
678 // usually a simpler/cheaper operation, so prefer it.
679 NewLHS = ZExtPromotedInteger(NewLHS);
680 NewRHS = ZExtPromotedInteger(NewRHS);
686 NewLHS = SExtPromotedInteger(NewLHS);
687 NewRHS = SExtPromotedInteger(NewRHS);
692 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
693 SDValue Op = GetPromotedInteger(N->getOperand(0));
694 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
697 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
698 // This should only occur in unusual situations like bitcasting to an
699 // x86_fp80, so just turn it into a store+load
700 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
703 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
704 assert(OpNo == 2 && "Don't know how to promote this operand!");
706 SDValue LHS = N->getOperand(2);
707 SDValue RHS = N->getOperand(3);
708 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
710 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
712 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
713 N->getOperand(1), LHS, RHS, N->getOperand(4));
716 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
717 assert(OpNo == 1 && "only know how to promote condition");
719 // Promote all the way up to the canonical SetCC type.
720 MVT SVT = TLI.getSetCCResultType(MVT::Other);
721 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
723 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
724 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
728 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
729 // Since the result type is legal, the operands must promote to it.
730 MVT OVT = N->getOperand(0).getValueType();
731 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
732 SDValue Hi = GetPromotedInteger(N->getOperand(1));
733 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
734 DebugLoc dl = N->getDebugLoc();
736 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
737 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
738 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
741 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
742 // The vector type is legal but the element type is not. This implies
743 // that the vector is a power-of-two in length and that the element
744 // type does not have a strange size (eg: it is not i1).
745 MVT VecVT = N->getValueType(0);
746 unsigned NumElts = VecVT.getVectorNumElements();
747 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
749 // Promote the inserted value. The type does not need to match the
750 // vector element type. Check that any extra bits introduced will be
752 assert(N->getOperand(0).getValueType().getSizeInBits() >=
753 N->getValueType(0).getVectorElementType().getSizeInBits() &&
754 "Type of inserted value narrower than vector element type!");
756 SmallVector<SDValue, 16> NewOps;
757 for (unsigned i = 0; i < NumElts; ++i)
758 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
760 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
763 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
764 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
765 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
766 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
767 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
768 "can only promote integer arguments");
769 SDValue InOp = GetPromotedInteger(N->getOperand(0));
770 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
771 N->getOperand(1), N->getOperand(2),
772 N->getOperand(3), N->getOperand(4), CvtCode);
775 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
778 // Promote the inserted value. This is valid because the type does not
779 // have to match the vector element type.
781 // Check that any extra bits introduced will be truncated away.
782 assert(N->getOperand(1).getValueType().getSizeInBits() >=
783 N->getValueType(0).getVectorElementType().getSizeInBits() &&
784 "Type of inserted value narrower than vector element type!");
785 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
786 GetPromotedInteger(N->getOperand(1)),
790 assert(OpNo == 2 && "Different operand and result vector types?");
792 // Promote the index.
793 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
794 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
795 N->getOperand(1), Idx);
798 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
800 DebugLoc dl = N->getDebugLoc();
801 NewOps[0] = N->getOperand(0);
802 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
803 SDValue Flag = GetPromotedInteger(N->getOperand(i));
804 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
806 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
807 array_lengthof(NewOps));
810 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
811 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
812 // the operand in place.
813 return DAG.UpdateNodeOperands(SDValue(N, 0),
814 GetPromotedInteger(N->getOperand(0)));
817 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
818 assert(OpNo == 0 && "Only know how to promote condition");
820 // Promote all the way up to the canonical SetCC type.
821 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
822 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
824 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
825 N->getOperand(1), N->getOperand(2));
828 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
829 assert(OpNo == 0 && "Don't know how to promote this operand!");
831 SDValue LHS = N->getOperand(0);
832 SDValue RHS = N->getOperand(1);
833 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
835 // The CC (#4) and the possible return values (#2 and #3) have legal types.
836 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
837 N->getOperand(3), N->getOperand(4));
840 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
841 assert(OpNo == 0 && "Don't know how to promote this operand!");
843 SDValue LHS = N->getOperand(0);
844 SDValue RHS = N->getOperand(1);
845 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
847 // The CC (#2) is always legal.
848 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
851 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
852 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
853 ZExtPromotedInteger(N->getOperand(1)));
856 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
857 SDValue Op = GetPromotedInteger(N->getOperand(0));
858 DebugLoc dl = N->getDebugLoc();
859 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
860 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
861 Op, DAG.getValueType(N->getOperand(0).getValueType()));
864 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
865 return DAG.UpdateNodeOperands(SDValue(N, 0),
866 SExtPromotedInteger(N->getOperand(0)));
869 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
870 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
871 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
872 int SVOffset = N->getSrcValueOffset();
873 unsigned Alignment = N->getAlignment();
874 bool isVolatile = N->isVolatile();
875 DebugLoc dl = N->getDebugLoc();
877 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
879 // Truncate the value and store the result.
880 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
881 SVOffset, N->getMemoryVT(),
882 isVolatile, Alignment);
885 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
886 SDValue Op = GetPromotedInteger(N->getOperand(0));
887 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
890 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
891 return DAG.UpdateNodeOperands(SDValue(N, 0),
892 ZExtPromotedInteger(N->getOperand(0)));
895 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
896 DebugLoc dl = N->getDebugLoc();
897 SDValue Op = GetPromotedInteger(N->getOperand(0));
898 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
899 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
903 //===----------------------------------------------------------------------===//
904 // Integer Result Expansion
905 //===----------------------------------------------------------------------===//
907 /// ExpandIntegerResult - This method is called when the specified result of the
908 /// specified node is found to need expansion. At this point, the node may also
909 /// have invalid operands or may have other results that need promotion, we just
910 /// know that (at least) one result needs expansion.
911 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
912 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
916 // See if the target wants to custom expand this node.
917 if (CustomLowerNode(N, N->getValueType(ResNo), true))
920 switch (N->getOpcode()) {
923 cerr << "ExpandIntegerResult #" << ResNo << ": ";
924 N->dump(&DAG); cerr << "\n";
926 LLVM_UNREACHABLE("Do not know how to expand the result of this operator!");
928 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
929 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
930 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
931 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
933 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
934 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
935 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
936 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
937 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
939 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
940 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
941 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
942 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
943 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
944 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
945 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
946 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
947 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
948 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
949 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
950 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
951 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
952 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
953 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
954 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
955 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
956 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
957 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
958 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
962 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
965 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
968 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
971 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
975 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
978 // If Lo/Hi is null, the sub-method took care of registering results etc.
980 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
983 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
984 /// and the shift amount is a constant 'Amt'. Expand the operation.
985 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
986 SDValue &Lo, SDValue &Hi) {
987 DebugLoc dl = N->getDebugLoc();
988 // Expand the incoming operand to be shifted, so that we have its parts
990 GetExpandedInteger(N->getOperand(0), InL, InH);
992 MVT NVT = InL.getValueType();
993 unsigned VTBits = N->getValueType(0).getSizeInBits();
994 unsigned NVTBits = NVT.getSizeInBits();
995 MVT ShTy = N->getOperand(1).getValueType();
997 if (N->getOpcode() == ISD::SHL) {
999 Lo = Hi = DAG.getConstant(0, NVT);
1000 } else if (Amt > NVTBits) {
1001 Lo = DAG.getConstant(0, NVT);
1002 Hi = DAG.getNode(ISD::SHL, dl,
1003 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1004 } else if (Amt == NVTBits) {
1005 Lo = DAG.getConstant(0, NVT);
1007 } else if (Amt == 1 &&
1008 TLI.isOperationLegalOrCustom(ISD::ADDC,
1009 TLI.getTypeToExpandTo(NVT))) {
1010 // Emit this X << 1 as X+X.
1011 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1012 SDValue LoOps[2] = { InL, InL };
1013 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1014 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1015 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1017 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1018 Hi = DAG.getNode(ISD::OR, dl, NVT,
1019 DAG.getNode(ISD::SHL, dl, NVT, InH,
1020 DAG.getConstant(Amt, ShTy)),
1021 DAG.getNode(ISD::SRL, dl, NVT, InL,
1022 DAG.getConstant(NVTBits-Amt, ShTy)));
1027 if (N->getOpcode() == ISD::SRL) {
1029 Lo = DAG.getConstant(0, NVT);
1030 Hi = DAG.getConstant(0, NVT);
1031 } else if (Amt > NVTBits) {
1032 Lo = DAG.getNode(ISD::SRL, dl,
1033 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1034 Hi = DAG.getConstant(0, NVT);
1035 } else if (Amt == NVTBits) {
1037 Hi = DAG.getConstant(0, NVT);
1039 Lo = DAG.getNode(ISD::OR, dl, NVT,
1040 DAG.getNode(ISD::SRL, dl, NVT, InL,
1041 DAG.getConstant(Amt, ShTy)),
1042 DAG.getNode(ISD::SHL, dl, NVT, InH,
1043 DAG.getConstant(NVTBits-Amt, ShTy)));
1044 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1049 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1051 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1052 DAG.getConstant(NVTBits-1, ShTy));
1053 } else if (Amt > NVTBits) {
1054 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1055 DAG.getConstant(Amt-NVTBits, ShTy));
1056 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1057 DAG.getConstant(NVTBits-1, ShTy));
1058 } else if (Amt == NVTBits) {
1060 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1061 DAG.getConstant(NVTBits-1, ShTy));
1063 Lo = DAG.getNode(ISD::OR, dl, NVT,
1064 DAG.getNode(ISD::SRL, dl, NVT, InL,
1065 DAG.getConstant(Amt, ShTy)),
1066 DAG.getNode(ISD::SHL, dl, NVT, InH,
1067 DAG.getConstant(NVTBits-Amt, ShTy)));
1068 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1072 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1073 /// this shift based on knowledge of the high bit of the shift amount. If we
1074 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1076 bool DAGTypeLegalizer::
1077 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1078 SDValue Amt = N->getOperand(1);
1079 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1080 MVT ShTy = Amt.getValueType();
1081 unsigned ShBits = ShTy.getSizeInBits();
1082 unsigned NVTBits = NVT.getSizeInBits();
1083 assert(isPowerOf2_32(NVTBits) &&
1084 "Expanded integer type size not a power of two!");
1085 DebugLoc dl = N->getDebugLoc();
1087 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1088 APInt KnownZero, KnownOne;
1089 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1091 // If we don't know anything about the high bits, exit.
1092 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1095 // Get the incoming operand to be shifted.
1097 GetExpandedInteger(N->getOperand(0), InL, InH);
1099 // If we know that any of the high bits of the shift amount are one, then we
1100 // can do this as a couple of simple shifts.
1101 if (KnownOne.intersects(HighBitMask)) {
1102 // Mask out the high bit, which we know is set.
1103 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1104 DAG.getConstant(~HighBitMask, ShTy));
1106 switch (N->getOpcode()) {
1107 default: LLVM_UNREACHABLE("Unknown shift");
1109 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1110 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1113 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1114 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1117 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1118 DAG.getConstant(NVTBits-1, ShTy));
1119 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1125 // FIXME: This code is broken for shifts with a zero amount!
1126 // If we know that all of the high bits of the shift amount are zero, then we
1127 // can do this as a couple of simple shifts.
1128 if ((KnownZero & HighBitMask) == HighBitMask) {
1130 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1131 DAG.getConstant(NVTBits, ShTy),
1134 switch (N->getOpcode()) {
1135 default: LLVM_UNREACHABLE("Unknown shift");
1136 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1138 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1141 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1142 Hi = DAG.getNode(ISD::OR, NVT,
1143 DAG.getNode(Op1, NVT, InH, Amt),
1144 DAG.getNode(Op2, NVT, InL, Amt2));
1152 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1154 bool DAGTypeLegalizer::
1155 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1156 SDValue Amt = N->getOperand(1);
1157 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1158 MVT ShTy = Amt.getValueType();
1159 unsigned NVTBits = NVT.getSizeInBits();
1160 assert(isPowerOf2_32(NVTBits) &&
1161 "Expanded integer type size not a power of two!");
1162 DebugLoc dl = N->getDebugLoc();
1164 // Get the incoming operand to be shifted.
1166 GetExpandedInteger(N->getOperand(0), InL, InH);
1168 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1169 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1170 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1171 Amt, NVBitsNode, ISD::SETULT);
1173 SDValue Lo1, Hi1, Lo2, Hi2;
1174 switch (N->getOpcode()) {
1175 default: LLVM_UNREACHABLE("Unknown shift");
1178 Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
1179 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1182 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1183 Hi2 = DAG.getNode(ISD::OR, dl, NVT,
1184 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1185 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
1187 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1188 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1192 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
1193 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1196 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1197 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1198 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1199 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1201 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1202 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1206 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1207 DAG.getConstant(NVTBits-1, ShTy));
1208 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1211 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1212 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1213 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1214 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1216 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1217 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1224 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1225 SDValue &Lo, SDValue &Hi) {
1226 DebugLoc dl = N->getDebugLoc();
1227 // Expand the subcomponents.
1228 SDValue LHSL, LHSH, RHSL, RHSH;
1229 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1230 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1232 MVT NVT = LHSL.getValueType();
1233 SDValue LoOps[2] = { LHSL, RHSL };
1234 SDValue HiOps[3] = { LHSH, RHSH };
1236 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1237 // them. TODO: Teach operation legalization how to expand unsupported
1238 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1239 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1240 // generate a value of this type in the expanded code sequence.
1242 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1243 ISD::ADDC : ISD::SUBC,
1244 TLI.getTypeToExpandTo(NVT));
1247 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1248 if (N->getOpcode() == ISD::ADD) {
1249 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1250 HiOps[2] = Lo.getValue(1);
1251 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1253 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1254 HiOps[2] = Lo.getValue(1);
1255 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1258 if (N->getOpcode() == ISD::ADD) {
1259 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1260 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1261 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1263 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1264 DAG.getConstant(1, NVT),
1265 DAG.getConstant(0, NVT));
1266 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1268 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1269 DAG.getConstant(1, NVT), Carry1);
1270 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1272 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1273 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1275 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1276 LoOps[0], LoOps[1], ISD::SETULT);
1277 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1278 DAG.getConstant(1, NVT),
1279 DAG.getConstant(0, NVT));
1280 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1285 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1286 SDValue &Lo, SDValue &Hi) {
1287 // Expand the subcomponents.
1288 SDValue LHSL, LHSH, RHSL, RHSH;
1289 DebugLoc dl = N->getDebugLoc();
1290 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1291 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1292 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1293 SDValue LoOps[2] = { LHSL, RHSL };
1294 SDValue HiOps[3] = { LHSH, RHSH };
1296 if (N->getOpcode() == ISD::ADDC) {
1297 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1298 HiOps[2] = Lo.getValue(1);
1299 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1301 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1302 HiOps[2] = Lo.getValue(1);
1303 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1306 // Legalized the flag result - switch anything that used the old flag to
1308 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1311 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1312 SDValue &Lo, SDValue &Hi) {
1313 // Expand the subcomponents.
1314 SDValue LHSL, LHSH, RHSL, RHSH;
1315 DebugLoc dl = N->getDebugLoc();
1316 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1317 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1318 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1319 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1320 SDValue HiOps[3] = { LHSH, RHSH };
1322 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1323 HiOps[2] = Lo.getValue(1);
1324 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1326 // Legalized the flag result - switch anything that used the old flag to
1328 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1331 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1332 SDValue &Lo, SDValue &Hi) {
1333 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1334 DebugLoc dl = N->getDebugLoc();
1335 SDValue Op = N->getOperand(0);
1336 if (Op.getValueType().bitsLE(NVT)) {
1337 // The low part is any extension of the input (which degenerates to a copy).
1338 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1339 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1341 // For example, extension of an i48 to an i64. The operand type necessarily
1342 // promotes to the result type, so will end up being expanded too.
1343 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1344 "Only know how to promote this result!");
1345 SDValue Res = GetPromotedInteger(Op);
1346 assert(Res.getValueType() == N->getValueType(0) &&
1347 "Operand over promoted?");
1348 // Split the promoted operand. This will simplify when it is expanded.
1349 SplitInteger(Res, Lo, Hi);
1353 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1354 SDValue &Lo, SDValue &Hi) {
1355 DebugLoc dl = N->getDebugLoc();
1356 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1357 MVT NVT = Lo.getValueType();
1358 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1359 unsigned NVTBits = NVT.getSizeInBits();
1360 unsigned EVTBits = EVT.getSizeInBits();
1362 if (NVTBits < EVTBits) {
1363 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1364 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1366 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1367 // The high part replicates the sign bit of Lo, make it explicit.
1368 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1369 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1373 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1374 SDValue &Lo, SDValue &Hi) {
1375 DebugLoc dl = N->getDebugLoc();
1376 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1377 MVT NVT = Lo.getValueType();
1378 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1379 unsigned NVTBits = NVT.getSizeInBits();
1380 unsigned EVTBits = EVT.getSizeInBits();
1382 if (NVTBits < EVTBits) {
1383 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1384 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1386 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1387 // The high part must be zero, make it explicit.
1388 Hi = DAG.getConstant(0, NVT);
1392 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1393 SDValue &Lo, SDValue &Hi) {
1394 DebugLoc dl = N->getDebugLoc();
1395 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1396 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1397 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1400 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1401 SDValue &Lo, SDValue &Hi) {
1402 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1403 unsigned NBitWidth = NVT.getSizeInBits();
1404 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1405 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1406 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1409 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1410 SDValue &Lo, SDValue &Hi) {
1411 DebugLoc dl = N->getDebugLoc();
1412 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1413 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1414 MVT NVT = Lo.getValueType();
1416 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1417 DAG.getConstant(0, NVT), ISD::SETNE);
1419 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1420 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1422 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1423 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1424 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1425 Hi = DAG.getConstant(0, NVT);
1428 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1429 SDValue &Lo, SDValue &Hi) {
1430 DebugLoc dl = N->getDebugLoc();
1431 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1432 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1433 MVT NVT = Lo.getValueType();
1434 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1435 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1436 Hi = DAG.getConstant(0, NVT);
1439 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1440 SDValue &Lo, SDValue &Hi) {
1441 DebugLoc dl = N->getDebugLoc();
1442 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1443 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1444 MVT NVT = Lo.getValueType();
1446 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1447 DAG.getConstant(0, NVT), ISD::SETNE);
1449 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1450 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1452 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1453 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1454 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1455 Hi = DAG.getConstant(0, NVT);
1458 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1460 DebugLoc dl = N->getDebugLoc();
1461 MVT VT = N->getValueType(0);
1462 SDValue Op = N->getOperand(0);
1463 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1464 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1465 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1468 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1470 DebugLoc dl = N->getDebugLoc();
1471 MVT VT = N->getValueType(0);
1472 SDValue Op = N->getOperand(0);
1473 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1474 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1475 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1478 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1479 SDValue &Lo, SDValue &Hi) {
1480 if (ISD::isNormalLoad(N)) {
1481 ExpandRes_NormalLoad(N, Lo, Hi);
1485 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1487 MVT VT = N->getValueType(0);
1488 MVT NVT = TLI.getTypeToTransformTo(VT);
1489 SDValue Ch = N->getChain();
1490 SDValue Ptr = N->getBasePtr();
1491 ISD::LoadExtType ExtType = N->getExtensionType();
1492 int SVOffset = N->getSrcValueOffset();
1493 unsigned Alignment = N->getAlignment();
1494 bool isVolatile = N->isVolatile();
1495 DebugLoc dl = N->getDebugLoc();
1497 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1499 if (N->getMemoryVT().bitsLE(NVT)) {
1500 MVT EVT = N->getMemoryVT();
1502 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1503 EVT, isVolatile, Alignment);
1505 // Remember the chain.
1506 Ch = Lo.getValue(1);
1508 if (ExtType == ISD::SEXTLOAD) {
1509 // The high part is obtained by SRA'ing all but one of the bits of the
1511 unsigned LoSize = Lo.getValueType().getSizeInBits();
1512 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1513 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1514 } else if (ExtType == ISD::ZEXTLOAD) {
1515 // The high part is just a zero.
1516 Hi = DAG.getConstant(0, NVT);
1518 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1519 // The high part is undefined.
1520 Hi = DAG.getUNDEF(NVT);
1522 } else if (TLI.isLittleEndian()) {
1523 // Little-endian - low bits are at low addresses.
1524 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1525 isVolatile, Alignment);
1527 unsigned ExcessBits =
1528 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1529 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1531 // Increment the pointer to the other half.
1532 unsigned IncrementSize = NVT.getSizeInBits()/8;
1533 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1534 DAG.getIntPtrConstant(IncrementSize));
1535 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1536 SVOffset+IncrementSize, NEVT,
1537 isVolatile, MinAlign(Alignment, IncrementSize));
1539 // Build a factor node to remember that this load is independent of the
1541 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1544 // Big-endian - high bits are at low addresses. Favor aligned loads at
1545 // the cost of some bit-fiddling.
1546 MVT EVT = N->getMemoryVT();
1547 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1548 unsigned IncrementSize = NVT.getSizeInBits()/8;
1549 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1551 // Load both the high bits and maybe some of the low bits.
1552 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1553 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1554 isVolatile, Alignment);
1556 // Increment the pointer to the other half.
1557 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1558 DAG.getIntPtrConstant(IncrementSize));
1559 // Load the rest of the low bits.
1560 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1561 SVOffset+IncrementSize,
1562 MVT::getIntegerVT(ExcessBits),
1563 isVolatile, MinAlign(Alignment, IncrementSize));
1565 // Build a factor node to remember that this load is independent of the
1567 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1570 if (ExcessBits < NVT.getSizeInBits()) {
1571 // Transfer low bits from the bottom of Hi to the top of Lo.
1572 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1573 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1574 DAG.getConstant(ExcessBits,
1575 TLI.getPointerTy())));
1576 // Move high bits to the right position in Hi.
1577 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1579 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1580 TLI.getPointerTy()));
1584 // Legalized the chain result - switch anything that used the old chain to
1586 ReplaceValueWith(SDValue(N, 1), Ch);
1589 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1590 SDValue &Lo, SDValue &Hi) {
1591 DebugLoc dl = N->getDebugLoc();
1592 SDValue LL, LH, RL, RH;
1593 GetExpandedInteger(N->getOperand(0), LL, LH);
1594 GetExpandedInteger(N->getOperand(1), RL, RH);
1595 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1596 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1599 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1600 SDValue &Lo, SDValue &Hi) {
1601 MVT VT = N->getValueType(0);
1602 MVT NVT = TLI.getTypeToTransformTo(VT);
1603 DebugLoc dl = N->getDebugLoc();
1605 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1606 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1607 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1608 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1609 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1610 SDValue LL, LH, RL, RH;
1611 GetExpandedInteger(N->getOperand(0), LL, LH);
1612 GetExpandedInteger(N->getOperand(1), RL, RH);
1613 unsigned OuterBitSize = VT.getSizeInBits();
1614 unsigned InnerBitSize = NVT.getSizeInBits();
1615 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1616 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1618 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1619 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1620 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1621 // The inputs are both zero-extended.
1623 // We can emit a umul_lohi.
1624 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1625 Hi = SDValue(Lo.getNode(), 1);
1629 // We can emit a mulhu+mul.
1630 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1631 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1635 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1636 // The input values are both sign-extended.
1638 // We can emit a smul_lohi.
1639 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1640 Hi = SDValue(Lo.getNode(), 1);
1644 // We can emit a mulhs+mul.
1645 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1646 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1651 // Lo,Hi = umul LHS, RHS.
1652 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1653 DAG.getVTList(NVT, NVT), LL, RL);
1655 Hi = UMulLOHI.getValue(1);
1656 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1657 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1658 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1659 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1663 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1664 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1665 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1666 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1667 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1668 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1673 // If nothing else, we can make a libcall.
1674 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1676 LC = RTLIB::MUL_I16;
1677 else if (VT == MVT::i32)
1678 LC = RTLIB::MUL_I32;
1679 else if (VT == MVT::i64)
1680 LC = RTLIB::MUL_I64;
1681 else if (VT == MVT::i128)
1682 LC = RTLIB::MUL_I128;
1683 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1685 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1686 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1689 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1690 SDValue &Lo, SDValue &Hi) {
1691 MVT VT = N->getValueType(0);
1692 DebugLoc dl = N->getDebugLoc();
1694 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1696 LC = RTLIB::SDIV_I16;
1697 else if (VT == MVT::i32)
1698 LC = RTLIB::SDIV_I32;
1699 else if (VT == MVT::i64)
1700 LC = RTLIB::SDIV_I64;
1701 else if (VT == MVT::i128)
1702 LC = RTLIB::SDIV_I128;
1703 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1705 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1706 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1709 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1710 SDValue &Lo, SDValue &Hi) {
1711 MVT VT = N->getValueType(0);
1712 DebugLoc dl = N->getDebugLoc();
1714 // If we can emit an efficient shift operation, do so now. Check to see if
1715 // the RHS is a constant.
1716 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1717 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1719 // If we can determine that the high bit of the shift is zero or one, even if
1720 // the low bits are variable, emit this shift in an optimized form.
1721 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1724 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1726 if (N->getOpcode() == ISD::SHL) {
1727 PartsOpc = ISD::SHL_PARTS;
1728 } else if (N->getOpcode() == ISD::SRL) {
1729 PartsOpc = ISD::SRL_PARTS;
1731 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1732 PartsOpc = ISD::SRA_PARTS;
1735 // Next check to see if the target supports this SHL_PARTS operation or if it
1736 // will custom expand it.
1737 MVT NVT = TLI.getTypeToTransformTo(VT);
1738 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1739 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1740 Action == TargetLowering::Custom) {
1741 // Expand the subcomponents.
1743 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1745 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1746 MVT VT = LHSL.getValueType();
1747 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1748 Hi = Lo.getValue(1);
1752 // Otherwise, emit a libcall.
1753 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1755 if (N->getOpcode() == ISD::SHL) {
1756 isSigned = false; /*sign irrelevant*/
1758 LC = RTLIB::SHL_I16;
1759 else if (VT == MVT::i32)
1760 LC = RTLIB::SHL_I32;
1761 else if (VT == MVT::i64)
1762 LC = RTLIB::SHL_I64;
1763 else if (VT == MVT::i128)
1764 LC = RTLIB::SHL_I128;
1765 } else if (N->getOpcode() == ISD::SRL) {
1768 LC = RTLIB::SRL_I16;
1769 else if (VT == MVT::i32)
1770 LC = RTLIB::SRL_I32;
1771 else if (VT == MVT::i64)
1772 LC = RTLIB::SRL_I64;
1773 else if (VT == MVT::i128)
1774 LC = RTLIB::SRL_I128;
1776 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1779 LC = RTLIB::SRA_I16;
1780 else if (VT == MVT::i32)
1781 LC = RTLIB::SRA_I32;
1782 else if (VT == MVT::i64)
1783 LC = RTLIB::SRA_I64;
1784 else if (VT == MVT::i128)
1785 LC = RTLIB::SRA_I128;
1788 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1789 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1790 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1794 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1795 LLVM_UNREACHABLE("Unsupported shift!");
1798 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1799 SDValue &Lo, SDValue &Hi) {
1800 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1801 DebugLoc dl = N->getDebugLoc();
1802 SDValue Op = N->getOperand(0);
1803 if (Op.getValueType().bitsLE(NVT)) {
1804 // The low part is sign extension of the input (degenerates to a copy).
1805 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1806 // The high part is obtained by SRA'ing all but one of the bits of low part.
1807 unsigned LoSize = NVT.getSizeInBits();
1808 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1809 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1811 // For example, extension of an i48 to an i64. The operand type necessarily
1812 // promotes to the result type, so will end up being expanded too.
1813 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1814 "Only know how to promote this result!");
1815 SDValue Res = GetPromotedInteger(Op);
1816 assert(Res.getValueType() == N->getValueType(0) &&
1817 "Operand over promoted?");
1818 // Split the promoted operand. This will simplify when it is expanded.
1819 SplitInteger(Res, Lo, Hi);
1820 unsigned ExcessBits =
1821 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1822 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1823 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1827 void DAGTypeLegalizer::
1828 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1829 DebugLoc dl = N->getDebugLoc();
1830 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1831 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1833 if (EVT.bitsLE(Lo.getValueType())) {
1834 // sext_inreg the low part if needed.
1835 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1838 // The high part gets the sign extension from the lo-part. This handles
1839 // things like sextinreg V:i64 from i8.
1840 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1841 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1842 TLI.getPointerTy()));
1844 // For example, extension of an i48 to an i64. Leave the low part alone,
1845 // sext_inreg the high part.
1846 unsigned ExcessBits =
1847 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1848 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1849 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1853 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1854 SDValue &Lo, SDValue &Hi) {
1855 MVT VT = N->getValueType(0);
1856 DebugLoc dl = N->getDebugLoc();
1858 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1860 LC = RTLIB::SREM_I16;
1861 else if (VT == MVT::i32)
1862 LC = RTLIB::SREM_I32;
1863 else if (VT == MVT::i64)
1864 LC = RTLIB::SREM_I64;
1865 else if (VT == MVT::i128)
1866 LC = RTLIB::SREM_I128;
1867 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1869 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1870 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1873 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1874 SDValue &Lo, SDValue &Hi) {
1875 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1876 DebugLoc dl = N->getDebugLoc();
1877 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1878 Hi = DAG.getNode(ISD::SRL, dl,
1879 N->getOperand(0).getValueType(), N->getOperand(0),
1880 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1881 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1884 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1885 SDValue &Lo, SDValue &Hi) {
1886 MVT VT = N->getValueType(0);
1887 DebugLoc dl = N->getDebugLoc();
1889 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1891 LC = RTLIB::UDIV_I16;
1892 else if (VT == MVT::i32)
1893 LC = RTLIB::UDIV_I32;
1894 else if (VT == MVT::i64)
1895 LC = RTLIB::UDIV_I64;
1896 else if (VT == MVT::i128)
1897 LC = RTLIB::UDIV_I128;
1898 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1900 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1901 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1904 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1905 SDValue &Lo, SDValue &Hi) {
1906 MVT VT = N->getValueType(0);
1907 DebugLoc dl = N->getDebugLoc();
1909 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1911 LC = RTLIB::UREM_I16;
1912 else if (VT == MVT::i32)
1913 LC = RTLIB::UREM_I32;
1914 else if (VT == MVT::i64)
1915 LC = RTLIB::UREM_I64;
1916 else if (VT == MVT::i128)
1917 LC = RTLIB::UREM_I128;
1918 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1920 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1921 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1924 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1925 SDValue &Lo, SDValue &Hi) {
1926 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1927 DebugLoc dl = N->getDebugLoc();
1928 SDValue Op = N->getOperand(0);
1929 if (Op.getValueType().bitsLE(NVT)) {
1930 // The low part is zero extension of the input (degenerates to a copy).
1931 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1932 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1934 // For example, extension of an i48 to an i64. The operand type necessarily
1935 // promotes to the result type, so will end up being expanded too.
1936 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1937 "Only know how to promote this result!");
1938 SDValue Res = GetPromotedInteger(Op);
1939 assert(Res.getValueType() == N->getValueType(0) &&
1940 "Operand over promoted?");
1941 // Split the promoted operand. This will simplify when it is expanded.
1942 SplitInteger(Res, Lo, Hi);
1943 unsigned ExcessBits =
1944 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1945 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
1950 //===----------------------------------------------------------------------===//
1951 // Integer Operand Expansion
1952 //===----------------------------------------------------------------------===//
1954 /// ExpandIntegerOperand - This method is called when the specified operand of
1955 /// the specified node is found to need expansion. At this point, all of the
1956 /// result types of the node are known to be legal, but other operands of the
1957 /// node may need promotion or expansion as well as the specified one.
1958 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1959 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1960 SDValue Res = SDValue();
1962 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
1965 switch (N->getOpcode()) {
1968 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1969 N->dump(&DAG); cerr << "\n";
1971 LLVM_UNREACHABLE("Do not know how to expand this operator's operand!");
1973 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1974 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1975 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1976 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1977 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1978 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1979 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1980 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1981 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1982 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
1983 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1984 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1990 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
1993 // If the result is null, the sub-method took care of registering results etc.
1994 if (!Res.getNode()) return false;
1996 // If the result is N, the sub-method updated N in place. Tell the legalizer
1998 if (Res.getNode() == N)
2001 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2002 "Invalid operand expansion");
2004 ReplaceValueWith(SDValue(N, 0), Res);
2008 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2009 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2010 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2012 ISD::CondCode &CCCode,
2014 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2015 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2016 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2018 MVT VT = NewLHS.getValueType();
2020 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2021 if (RHSLo == RHSHi) {
2022 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2023 if (RHSCST->isAllOnesValue()) {
2024 // Equality comparison to -1.
2025 NewLHS = DAG.getNode(ISD::AND, dl,
2026 LHSLo.getValueType(), LHSLo, LHSHi);
2033 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2034 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2035 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2036 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2040 // If this is a comparison of the sign bit, just look at the top part.
2042 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2043 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2044 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2050 // FIXME: This generated code sucks.
2051 ISD::CondCode LowCC;
2053 default: LLVM_UNREACHABLE("Unknown integer setcc!");
2055 case ISD::SETULT: LowCC = ISD::SETULT; break;
2057 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2059 case ISD::SETULE: LowCC = ISD::SETULE; break;
2061 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2064 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2065 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2066 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2068 // NOTE: on targets without efficient SELECT of bools, we can always use
2069 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2070 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2072 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2073 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2074 if (!Tmp1.getNode())
2075 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2076 LHSLo, RHSLo, LowCC);
2077 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2078 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2079 if (!Tmp2.getNode())
2080 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2081 TLI.getSetCCResultType(LHSHi.getValueType()),
2082 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2084 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2085 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2086 if ((Tmp1C && Tmp1C->isNullValue()) ||
2087 (Tmp2C && Tmp2C->isNullValue() &&
2088 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2089 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2090 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2091 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2092 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2093 // low part is known false, returns high part.
2094 // For LE / GE, if high part is known false, ignore the low part.
2095 // For LT / GT, if high part is known true, ignore the low part.
2101 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2102 LHSHi, RHSHi, ISD::SETEQ, false,
2103 DagCombineInfo, dl);
2104 if (!NewLHS.getNode())
2105 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2106 LHSHi, RHSHi, ISD::SETEQ);
2107 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2108 NewLHS, Tmp1, Tmp2);
2112 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2113 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2114 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2115 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2117 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2118 // against zero to select between true and false values.
2119 if (NewRHS.getNode() == 0) {
2120 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2121 CCCode = ISD::SETNE;
2124 // Update N to have the operands specified.
2125 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2126 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2130 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2131 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2132 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2133 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2135 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2136 // against zero to select between true and false values.
2137 if (NewRHS.getNode() == 0) {
2138 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2139 CCCode = ISD::SETNE;
2142 // Update N to have the operands specified.
2143 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2144 N->getOperand(2), N->getOperand(3),
2145 DAG.getCondCode(CCCode));
2148 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2149 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2150 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2151 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2153 // If ExpandSetCCOperands returned a scalar, use it.
2154 if (NewRHS.getNode() == 0) {
2155 assert(NewLHS.getValueType() == N->getValueType(0) &&
2156 "Unexpected setcc expansion!");
2160 // Otherwise, update N to have the operands specified.
2161 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2162 DAG.getCondCode(CCCode));
2165 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2166 // The value being shifted is legal, but the shift amount is too big.
2167 // It follows that either the result of the shift is undefined, or the
2168 // upper half of the shift amount is zero. Just use the lower half.
2170 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2171 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2174 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2175 SDValue Op = N->getOperand(0);
2176 MVT DstVT = N->getValueType(0);
2177 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2178 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2179 "Don't know how to expand this SINT_TO_FP!");
2180 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2183 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2184 if (ISD::isNormalStore(N))
2185 return ExpandOp_NormalStore(N, OpNo);
2187 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2188 assert(OpNo == 1 && "Can only expand the stored value so far");
2190 MVT VT = N->getOperand(1).getValueType();
2191 MVT NVT = TLI.getTypeToTransformTo(VT);
2192 SDValue Ch = N->getChain();
2193 SDValue Ptr = N->getBasePtr();
2194 int SVOffset = N->getSrcValueOffset();
2195 unsigned Alignment = N->getAlignment();
2196 bool isVolatile = N->isVolatile();
2197 DebugLoc dl = N->getDebugLoc();
2200 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2202 if (N->getMemoryVT().bitsLE(NVT)) {
2203 GetExpandedInteger(N->getValue(), Lo, Hi);
2204 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2205 N->getMemoryVT(), isVolatile, Alignment);
2206 } else if (TLI.isLittleEndian()) {
2207 // Little-endian - low bits are at low addresses.
2208 GetExpandedInteger(N->getValue(), Lo, Hi);
2210 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2211 isVolatile, Alignment);
2213 unsigned ExcessBits =
2214 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2215 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2217 // Increment the pointer to the other half.
2218 unsigned IncrementSize = NVT.getSizeInBits()/8;
2219 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2220 DAG.getIntPtrConstant(IncrementSize));
2221 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2222 SVOffset+IncrementSize, NEVT,
2223 isVolatile, MinAlign(Alignment, IncrementSize));
2224 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2226 // Big-endian - high bits are at low addresses. Favor aligned stores at
2227 // the cost of some bit-fiddling.
2228 GetExpandedInteger(N->getValue(), Lo, Hi);
2230 MVT EVT = N->getMemoryVT();
2231 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2232 unsigned IncrementSize = NVT.getSizeInBits()/8;
2233 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2234 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2236 if (ExcessBits < NVT.getSizeInBits()) {
2237 // Transfer high bits from the top of Lo to the bottom of Hi.
2238 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2239 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2240 TLI.getPointerTy()));
2241 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2242 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2243 DAG.getConstant(ExcessBits,
2244 TLI.getPointerTy())));
2247 // Store both the high bits and maybe some of the low bits.
2248 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2249 SVOffset, HiVT, isVolatile, Alignment);
2251 // Increment the pointer to the other half.
2252 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2253 DAG.getIntPtrConstant(IncrementSize));
2254 // Store the lowest ExcessBits bits in the second half.
2255 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2256 SVOffset+IncrementSize,
2257 MVT::getIntegerVT(ExcessBits),
2258 isVolatile, MinAlign(Alignment, IncrementSize));
2259 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2263 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2265 GetExpandedInteger(N->getOperand(0), InL, InH);
2266 // Just truncate the low part of the source.
2267 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2270 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2271 SDValue Op = N->getOperand(0);
2272 MVT SrcVT = Op.getValueType();
2273 MVT DstVT = N->getValueType(0);
2274 DebugLoc dl = N->getDebugLoc();
2276 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2277 // Do a signed conversion then adjust the result.
2278 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2279 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2281 // The result of the signed conversion needs adjusting if the 'sign bit' of
2282 // the incoming integer was set. To handle this, we dynamically test to see
2283 // if it is set, and, if so, add a fudge factor.
2285 const uint64_t F32TwoE32 = 0x4F800000ULL;
2286 const uint64_t F32TwoE64 = 0x5F800000ULL;
2287 const uint64_t F32TwoE128 = 0x7F800000ULL;
2290 if (SrcVT == MVT::i32)
2291 FF = APInt(32, F32TwoE32);
2292 else if (SrcVT == MVT::i64)
2293 FF = APInt(32, F32TwoE64);
2294 else if (SrcVT == MVT::i128)
2295 FF = APInt(32, F32TwoE128);
2297 assert(false && "Unsupported UINT_TO_FP!");
2299 // Check whether the sign bit is set.
2301 GetExpandedInteger(Op, Lo, Hi);
2302 SDValue SignSet = DAG.getSetCC(dl,
2303 TLI.getSetCCResultType(Hi.getValueType()),
2304 Hi, DAG.getConstant(0, Hi.getValueType()),
2307 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2308 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2309 TLI.getPointerTy());
2311 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2312 SDValue Zero = DAG.getIntPtrConstant(0);
2313 SDValue Four = DAG.getIntPtrConstant(4);
2314 if (TLI.isBigEndian()) std::swap(Zero, Four);
2315 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2317 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2318 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2319 Alignment = std::min(Alignment, 4u);
2321 // Load the value out, extending it from f32 to the destination float type.
2322 // FIXME: Avoid the extend by constructing the right constant pool?
2323 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2324 FudgePtr, NULL, 0, MVT::f32,
2326 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2329 // Otherwise, use a libcall.
2330 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2331 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2332 "Don't know how to expand this UINT_TO_FP!");
2333 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);