1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
24 //===----------------------------------------------------------------------===//
25 // Integer Result Promotion
26 //===----------------------------------------------------------------------===//
28 /// PromoteIntegerResult - This method is called when a result of a node is
29 /// found to be in need of promotion to a larger type. At this point, the node
30 /// may also have invalid operands or may have other results that need
31 /// expansion, we just know that (at least) one result needs promotion.
32 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
33 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
34 SDValue Result = SDValue();
36 // See if the target wants to custom expand this node.
37 if (CustomLowerResults(N, ResNo))
40 switch (N->getOpcode()) {
43 cerr << "PromoteIntegerResult #" << ResNo << ": ";
44 N->dump(&DAG); cerr << "\n";
46 assert(0 && "Do not know how to promote this operator!");
48 case ISD::AssertSext: Result = PromoteIntRes_AssertSext(N); break;
49 case ISD::AssertZext: Result = PromoteIntRes_AssertZext(N); break;
50 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
51 case ISD::BSWAP: Result = PromoteIntRes_BSWAP(N); break;
52 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
53 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
54 case ISD::CONVERT_RNDSAT:
55 Result = PromoteIntRes_CONVERT_RNDSAT(N); break;
56 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
57 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
58 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
59 case ISD::EXTRACT_VECTOR_ELT:
60 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
61 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
62 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
63 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
64 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
65 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
66 case ISD::SIGN_EXTEND_INREG:
67 Result = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
68 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
69 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
70 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
71 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
72 case ISD::VAARG: Result = PromoteIntRes_VAARG(N); break;
74 case ISD::SIGN_EXTEND:
75 case ISD::ZERO_EXTEND:
76 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
79 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
86 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
89 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
92 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
95 case ISD::SSUBO: Result = PromoteIntRes_SADDSUBO(N, ResNo); break;
97 case ISD::USUBO: Result = PromoteIntRes_UADDSUBO(N, ResNo); break;
99 case ISD::UMULO: Result = PromoteIntRes_XMULO(N, ResNo); break;
101 case ISD::ATOMIC_LOAD_ADD_8:
102 case ISD::ATOMIC_LOAD_SUB_8:
103 case ISD::ATOMIC_LOAD_AND_8:
104 case ISD::ATOMIC_LOAD_OR_8:
105 case ISD::ATOMIC_LOAD_XOR_8:
106 case ISD::ATOMIC_LOAD_NAND_8:
107 case ISD::ATOMIC_LOAD_MIN_8:
108 case ISD::ATOMIC_LOAD_MAX_8:
109 case ISD::ATOMIC_LOAD_UMIN_8:
110 case ISD::ATOMIC_LOAD_UMAX_8:
111 case ISD::ATOMIC_SWAP_8:
112 case ISD::ATOMIC_LOAD_ADD_16:
113 case ISD::ATOMIC_LOAD_SUB_16:
114 case ISD::ATOMIC_LOAD_AND_16:
115 case ISD::ATOMIC_LOAD_OR_16:
116 case ISD::ATOMIC_LOAD_XOR_16:
117 case ISD::ATOMIC_LOAD_NAND_16:
118 case ISD::ATOMIC_LOAD_MIN_16:
119 case ISD::ATOMIC_LOAD_MAX_16:
120 case ISD::ATOMIC_LOAD_UMIN_16:
121 case ISD::ATOMIC_LOAD_UMAX_16:
122 case ISD::ATOMIC_SWAP_16:
123 case ISD::ATOMIC_LOAD_ADD_32:
124 case ISD::ATOMIC_LOAD_SUB_32:
125 case ISD::ATOMIC_LOAD_AND_32:
126 case ISD::ATOMIC_LOAD_OR_32:
127 case ISD::ATOMIC_LOAD_XOR_32:
128 case ISD::ATOMIC_LOAD_NAND_32:
129 case ISD::ATOMIC_LOAD_MIN_32:
130 case ISD::ATOMIC_LOAD_MAX_32:
131 case ISD::ATOMIC_LOAD_UMIN_32:
132 case ISD::ATOMIC_LOAD_UMAX_32:
133 case ISD::ATOMIC_SWAP_32:
134 case ISD::ATOMIC_LOAD_ADD_64:
135 case ISD::ATOMIC_LOAD_SUB_64:
136 case ISD::ATOMIC_LOAD_AND_64:
137 case ISD::ATOMIC_LOAD_OR_64:
138 case ISD::ATOMIC_LOAD_XOR_64:
139 case ISD::ATOMIC_LOAD_NAND_64:
140 case ISD::ATOMIC_LOAD_MIN_64:
141 case ISD::ATOMIC_LOAD_MAX_64:
142 case ISD::ATOMIC_LOAD_UMIN_64:
143 case ISD::ATOMIC_LOAD_UMAX_64:
144 case ISD::ATOMIC_SWAP_64:
145 Result = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
147 case ISD::ATOMIC_CMP_SWAP_8:
148 case ISD::ATOMIC_CMP_SWAP_16:
149 case ISD::ATOMIC_CMP_SWAP_32:
150 case ISD::ATOMIC_CMP_SWAP_64:
151 Result = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
154 // If Result is null, the sub-method took care of registering the result.
155 if (Result.getNode())
156 SetPromotedInteger(SDValue(N, ResNo), Result);
159 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
160 // Sign-extend the new bits, and continue the assertion.
161 SDValue Op = SExtPromotedInteger(N->getOperand(0));
162 return DAG.getNode(ISD::AssertSext, Op.getValueType(), Op, N->getOperand(1));
165 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
166 // Zero the new bits, and continue the assertion.
167 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
168 return DAG.getNode(ISD::AssertZext, Op.getValueType(), Op, N->getOperand(1));
171 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
172 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
173 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
174 Op2, N->getSrcValue(), N->getAlignment());
175 // Legalized the chain result - switch anything that used the old chain to
177 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
181 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
182 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
183 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
184 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getChain(), N->getBasePtr(),
185 Op2, Op3, N->getSrcValue(), N->getAlignment());
186 // Legalized the chain result - switch anything that used the old chain to
188 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
192 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
193 SDValue InOp = N->getOperand(0);
194 MVT InVT = InOp.getValueType();
195 MVT NInVT = TLI.getTypeToTransformTo(InVT);
196 MVT OutVT = N->getValueType(0);
197 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
199 switch (getTypeAction(InVT)) {
201 assert(false && "Unknown type action!");
206 if (NOutVT.bitsEq(NInVT))
207 // The input promotes to the same size. Convert the promoted value.
208 return DAG.getNode(ISD::BIT_CONVERT, NOutVT, GetPromotedInteger(InOp));
211 // Promote the integer operand by hand.
212 return DAG.getNode(ISD::ANY_EXTEND, NOutVT, GetSoftenedFloat(InOp));
216 case ScalarizeVector:
217 // Convert the element to an integer and promote it by hand.
218 return DAG.getNode(ISD::ANY_EXTEND, NOutVT,
219 BitConvertToInteger(GetScalarizedVector(InOp)));
221 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
222 // pieces of the input into integers and reassemble in the final type.
224 GetSplitVector(N->getOperand(0), Lo, Hi);
225 Lo = BitConvertToInteger(Lo);
226 Hi = BitConvertToInteger(Hi);
228 if (TLI.isBigEndian())
231 InOp = DAG.getNode(ISD::ANY_EXTEND,
232 MVT::getIntegerVT(NOutVT.getSizeInBits()),
233 JoinIntegers(Lo, Hi));
234 return DAG.getNode(ISD::BIT_CONVERT, NOutVT, InOp);
237 if (OutVT.bitsEq(NInVT))
238 // The input is widened to the same size. Convert to the widened value.
239 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetWidenedVector(InOp));
242 // Otherwise, lower the bit-convert to a store/load from the stack.
243 // Create the stack frame object. Make sure it is aligned for both
244 // the source and destination types.
245 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
247 // Emit a store to the stack slot.
248 SDValue Store = DAG.getStore(DAG.getEntryNode(), InOp, FIPtr, NULL, 0);
250 // Result is an extending load from the stack slot.
251 return DAG.getExtLoad(ISD::EXTLOAD, NOutVT, Store, FIPtr, NULL, 0, OutVT);
254 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
255 SDValue Op = GetPromotedInteger(N->getOperand(0));
256 MVT OVT = N->getValueType(0);
257 MVT NVT = Op.getValueType();
259 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
260 return DAG.getNode(ISD::SRL, NVT, DAG.getNode(ISD::BSWAP, NVT, Op),
261 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
264 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
265 // The pair element type may be legal, or may not promote to the same type as
266 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
267 return DAG.getNode(ISD::ANY_EXTEND,
268 TLI.getTypeToTransformTo(N->getValueType(0)),
269 JoinIntegers(N->getOperand(0), N->getOperand(1)));
272 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
273 MVT VT = N->getValueType(0);
274 // Zero extend things like i1, sign extend everything else. It shouldn't
275 // matter in theory which one we pick, but this tends to give better code?
276 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
277 SDValue Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
279 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
283 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
284 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
285 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
286 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
287 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
288 "can only promote integers");
289 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
290 return DAG.getConvertRndSat(OutVT, N->getOperand(0),
291 N->getOperand(1), N->getOperand(2),
292 N->getOperand(3), N->getOperand(4), CvtCode);
295 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
296 // Zero extend to the promoted type and do the count there.
297 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
298 MVT OVT = N->getValueType(0);
299 MVT NVT = Op.getValueType();
300 Op = DAG.getNode(ISD::CTLZ, NVT, Op);
301 // Subtract off the extra leading bits in the bigger type.
302 return DAG.getNode(ISD::SUB, NVT, Op,
303 DAG.getConstant(NVT.getSizeInBits() -
304 OVT.getSizeInBits(), NVT));
307 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
308 // Zero extend to the promoted type and do the count there.
309 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
310 return DAG.getNode(ISD::CTPOP, Op.getValueType(), Op);
313 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
314 SDValue Op = GetPromotedInteger(N->getOperand(0));
315 MVT OVT = N->getValueType(0);
316 MVT NVT = Op.getValueType();
317 // The count is the same in the promoted type except if the original
318 // value was zero. This can be handled by setting the bit just off
319 // the top of the original type.
320 APInt TopBit(NVT.getSizeInBits(), 0);
321 TopBit.set(OVT.getSizeInBits());
322 Op = DAG.getNode(ISD::OR, NVT, Op, DAG.getConstant(TopBit, NVT));
323 return DAG.getNode(ISD::CTTZ, NVT, Op);
326 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
327 MVT OldVT = N->getValueType(0);
328 SDValue OldVec = N->getOperand(0);
329 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
332 assert(!isTypeLegal(OldVec.getValueType()) &&
333 "Legal one-element vector of a type needing promotion!");
334 // It is tempting to follow GetScalarizedVector by a call to
335 // GetPromotedInteger, but this would be wrong because the
336 // scalarized value may not yet have been processed.
337 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
338 GetScalarizedVector(OldVec));
341 // Convert to a vector half as long with an element type of twice the width,
342 // for example <4 x i16> -> <2 x i32>.
343 assert(!(OldElts & 1) && "Odd length vectors not supported!");
344 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
345 assert(OldVT.isSimple() && NewVT.isSimple());
347 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT,
348 MVT::getVectorVT(NewVT, OldElts / 2),
351 // Extract the element at OldIdx / 2 from the new vector.
352 SDValue OldIdx = N->getOperand(1);
353 SDValue NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
354 DAG.getConstant(1, TLI.getShiftAmountTy()));
355 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
357 // Select the appropriate half of the element: Lo if OldIdx was even,
360 SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
361 DAG.getConstant(OldVT.getSizeInBits(),
362 TLI.getShiftAmountTy()));
363 if (TLI.isBigEndian())
366 // Signed extend to the promoted type.
367 SDValue Odd = DAG.getNode(ISD::TRUNCATE, MVT::i1, OldIdx);
368 SDValue Res = DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
369 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT), Res);
372 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
373 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
374 unsigned NewOpc = N->getOpcode();
376 // If we're promoting a UINT to a larger size, check to see if the new node
377 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
378 // we can use that instead. This allows us to generate better code for
379 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
380 // legal, such as PowerPC.
381 if (N->getOpcode() == ISD::FP_TO_UINT &&
382 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
383 TLI.isOperationLegal(ISD::FP_TO_SINT, NVT))
384 NewOpc = ISD::FP_TO_SINT;
386 SDValue Res = DAG.getNode(NewOpc, NVT, N->getOperand(0));
388 // Assert that the converted value fits in the original type. If it doesn't
389 // (eg: because the value being converted is too big), then the result of the
390 // original operation was undefined anyway, so the assert is still correct.
391 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
392 ISD::AssertZext : ISD::AssertSext,
393 NVT, Res, DAG.getValueType(N->getValueType(0)));
396 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
397 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
399 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
400 SDValue Res = GetPromotedInteger(N->getOperand(0));
401 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
403 // If the result and operand types are the same after promotion, simplify
404 // to an in-register extension.
405 if (NVT == Res.getValueType()) {
406 // The high bits are not guaranteed to be anything. Insert an extend.
407 if (N->getOpcode() == ISD::SIGN_EXTEND)
408 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
409 DAG.getValueType(N->getOperand(0).getValueType()));
410 if (N->getOpcode() == ISD::ZERO_EXTEND)
411 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
412 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
417 // Otherwise, just extend the original operand all the way to the larger type.
418 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
421 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
422 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
423 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
424 ISD::LoadExtType ExtType =
425 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
426 SDValue Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
427 N->getSrcValue(), N->getSrcValueOffset(),
428 N->getMemoryVT(), N->isVolatile(),
431 // Legalized the chain result - switch anything that used the old chain to
433 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
437 /// Promote the overflow flag of an overflowing arithmetic node.
438 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
439 // Simply change the return type of the boolean result.
440 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
441 MVT ValueVTs[] = { N->getValueType(0), NVT };
442 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
443 SDValue Res = DAG.getNode(N->getOpcode(), DAG.getVTList(ValueVTs, 2), Ops, 2);
445 // Modified the sum result - switch anything that used the old sum to use
447 ReplaceValueWith(SDValue(N, 0), Res);
449 return SDValue(Res.getNode(), 1);
452 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
454 return PromoteIntRes_Overflow(N);
456 // The operation overflowed iff the result in the larger type is not the
457 // sign extension of its truncation to the original type.
458 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
459 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
460 MVT OVT = N->getOperand(0).getValueType();
461 MVT NVT = LHS.getValueType();
463 // Do the arithmetic in the larger type.
464 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
465 SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS);
467 // Calculate the overflow flag: sign extend the arithmetic result from
468 // the original type.
469 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
470 DAG.getValueType(OVT));
471 // Overflowed if and only if this is not equal to Res.
472 Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE);
474 // Use the calculated overflow everywhere.
475 ReplaceValueWith(SDValue(N, 1), Ofl);
480 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
481 // Sign extend the input.
482 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
483 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
484 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
487 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
488 SDValue LHS = GetPromotedInteger(N->getOperand(1));
489 SDValue RHS = GetPromotedInteger(N->getOperand(2));
490 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
493 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
494 SDValue LHS = GetPromotedInteger(N->getOperand(2));
495 SDValue RHS = GetPromotedInteger(N->getOperand(3));
496 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
497 N->getOperand(1), LHS, RHS, N->getOperand(4));
500 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
501 MVT SVT = TLI.getSetCCResultType(N->getOperand(0));
502 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
504 // Get the SETCC result using the canonical SETCC type.
505 SDValue SetCC = DAG.getNode(ISD::SETCC, SVT, N->getOperand(0),
506 N->getOperand(1), N->getOperand(2));
508 // Convert to the expected type.
509 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
510 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
511 return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
514 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
515 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
516 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
519 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
520 SDValue Op = GetPromotedInteger(N->getOperand(0));
521 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(), Op,
525 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
526 // The input may have strange things in the top bits of the registers, but
527 // these operations don't care. They may have weird bits going out, but
528 // that too is okay if they are integer operations.
529 SDValue LHS = GetPromotedInteger(N->getOperand(0));
530 SDValue RHS = GetPromotedInteger(N->getOperand(1));
531 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
534 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
535 // The input value must be properly sign extended.
536 SDValue Res = SExtPromotedInteger(N->getOperand(0));
537 return DAG.getNode(ISD::SRA, Res.getValueType(), Res, N->getOperand(1));
540 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
541 // The input value must be properly zero extended.
542 MVT VT = N->getValueType(0);
543 MVT NVT = TLI.getTypeToTransformTo(VT);
544 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
545 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
548 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
549 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
552 switch (getTypeAction(N->getOperand(0).getValueType())) {
553 default: assert(0 && "Unknown type action!");
556 Res = N->getOperand(0);
559 Res = GetPromotedInteger(N->getOperand(0));
563 // Truncate to NVT instead of VT
564 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
567 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
569 return PromoteIntRes_Overflow(N);
571 // The operation overflowed iff the result in the larger type is not the
572 // zero extension of its truncation to the original type.
573 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
574 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
575 MVT OVT = N->getOperand(0).getValueType();
576 MVT NVT = LHS.getValueType();
578 // Do the arithmetic in the larger type.
579 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
580 SDValue Res = DAG.getNode(Opcode, NVT, LHS, RHS);
582 // Calculate the overflow flag: zero extend the arithmetic result from
583 // the original type.
584 SDValue Ofl = DAG.getZeroExtendInReg(Res, OVT);
585 // Overflowed if and only if this is not equal to Res.
586 Ofl = DAG.getSetCC(N->getValueType(1), Ofl, Res, ISD::SETNE);
588 // Use the calculated overflow everywhere.
589 ReplaceValueWith(SDValue(N, 1), Ofl);
594 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
595 // Zero extend the input.
596 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
597 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
598 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
601 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
602 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
605 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
606 SDValue Chain = N->getOperand(0); // Get the chain.
607 SDValue Ptr = N->getOperand(1); // Get the pointer.
608 MVT VT = N->getValueType(0);
610 MVT RegVT = TLI.getRegisterType(VT);
611 unsigned NumRegs = TLI.getNumRegisters(VT);
612 // The argument is passed as NumRegs registers of type RegVT.
614 SmallVector<SDValue, 8> Parts(NumRegs);
615 for (unsigned i = 0; i < NumRegs; ++i) {
616 Parts[i] = DAG.getVAArg(RegVT, Chain, Ptr, N->getOperand(2));
617 Chain = Parts[i].getValue(1);
620 // Handle endianness of the load.
621 if (TLI.isBigEndian())
622 std::reverse(Parts.begin(), Parts.end());
624 // Assemble the parts in the promoted type.
625 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
626 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[0]);
627 for (unsigned i = 1; i < NumRegs; ++i) {
628 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, NVT, Parts[i]);
629 // Shift it to the right position and "or" it in.
630 Part = DAG.getNode(ISD::SHL, NVT, Part,
631 DAG.getConstant(i * RegVT.getSizeInBits(),
632 TLI.getShiftAmountTy()));
633 Res = DAG.getNode(ISD::OR, NVT, Res, Part);
636 // Modified the chain result - switch anything that used the old chain to
638 ReplaceValueWith(SDValue(N, 1), Chain);
643 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
644 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
645 return PromoteIntRes_Overflow(N);
648 //===----------------------------------------------------------------------===//
649 // Integer Operand Promotion
650 //===----------------------------------------------------------------------===//
652 /// PromoteIntegerOperand - This method is called when the specified operand of
653 /// the specified node is found to need promotion. At this point, all of the
654 /// result types of the node are known to be legal, but other operands of the
655 /// node may need promotion or expansion as well as the specified one.
656 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
657 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
658 SDValue Res = SDValue();
660 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
661 == TargetLowering::Custom)
662 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
664 if (Res.getNode() == 0) {
665 switch (N->getOpcode()) {
668 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
669 N->dump(&DAG); cerr << "\n";
671 assert(0 && "Do not know how to promote this operator's operand!");
674 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
675 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
676 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
677 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
678 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
679 case ISD::CONVERT_RNDSAT:
680 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
681 case ISD::INSERT_VECTOR_ELT:
682 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
683 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
684 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
685 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
686 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
687 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
688 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
689 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
691 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
692 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
693 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
697 // If the result is null, the sub-method took care of registering results etc.
698 if (!Res.getNode()) return false;
700 // If the result is N, the sub-method updated N in place. Tell the legalizer
702 if (Res.getNode() == N)
705 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
706 "Invalid operand expansion");
708 ReplaceValueWith(SDValue(N, 0), Res);
712 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
713 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
714 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
715 ISD::CondCode CCCode) {
716 // We have to insert explicit sign or zero extends. Note that we could
717 // insert sign extends for ALL conditions, but zero extend is cheaper on
718 // many machines (an AND instead of two shifts), so prefer it.
720 default: assert(0 && "Unknown integer comparison!");
727 // ALL of these operations will work if we either sign or zero extend
728 // the operands (including the unsigned comparisons!). Zero extend is
729 // usually a simpler/cheaper operation, so prefer it.
730 NewLHS = ZExtPromotedInteger(NewLHS);
731 NewRHS = ZExtPromotedInteger(NewRHS);
737 NewLHS = SExtPromotedInteger(NewLHS);
738 NewRHS = SExtPromotedInteger(NewRHS);
743 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
744 SDValue Op = GetPromotedInteger(N->getOperand(0));
745 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
748 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
749 assert(OpNo == 2 && "Don't know how to promote this operand!");
751 SDValue LHS = N->getOperand(2);
752 SDValue RHS = N->getOperand(3);
753 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
755 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
757 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
758 N->getOperand(1), LHS, RHS, N->getOperand(4));
761 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
762 assert(OpNo == 1 && "only know how to promote condition");
763 SDValue Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
765 // Make sure the extra bits coming from type promotion conform to
766 // getBooleanContents.
767 unsigned CondBits = Cond.getValueSizeInBits();
768 switch (TLI.getBooleanContents()) {
770 assert(false && "Unknown BooleanContent!");
771 case TargetLowering::UndefinedBooleanContent:
772 // The promoted value, which may contain rubbish in the upper bits, is fine.
774 case TargetLowering::ZeroOrOneBooleanContent:
775 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
776 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
778 case TargetLowering::ZeroOrNegativeOneBooleanContent:
779 if (DAG.ComputeNumSignBits(Cond) != CondBits)
780 Cond = DAG.getNode(ISD::SIGN_EXTEND_INREG, Cond.getValueType(), Cond,
781 DAG.getValueType(MVT::i1));
785 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
786 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
790 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
791 // Since the result type is legal, the operands must promote to it.
792 MVT OVT = N->getOperand(0).getValueType();
793 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
794 SDValue Hi = GetPromotedInteger(N->getOperand(1));
795 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
797 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
798 DAG.getConstant(OVT.getSizeInBits(),
799 TLI.getShiftAmountTy()));
800 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
803 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
804 // The vector type is legal but the element type is not. This implies
805 // that the vector is a power-of-two in length and that the element
806 // type does not have a strange size (eg: it is not i1).
807 MVT VecVT = N->getValueType(0);
808 unsigned NumElts = VecVT.getVectorNumElements();
809 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
811 // Build a vector of half the length out of elements of twice the bitwidth.
812 // For example <4 x i16> -> <2 x i32>.
813 MVT OldVT = N->getOperand(0).getValueType();
814 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
815 assert(OldVT.isSimple() && NewVT.isSimple());
817 std::vector<SDValue> NewElts;
818 NewElts.reserve(NumElts/2);
820 for (unsigned i = 0; i < NumElts; i += 2) {
821 // Combine two successive elements into one promoted element.
822 SDValue Lo = N->getOperand(i);
823 SDValue Hi = N->getOperand(i+1);
824 if (TLI.isBigEndian())
826 NewElts.push_back(JoinIntegers(Lo, Hi));
829 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR,
830 MVT::getVectorVT(NewVT, NewElts.size()),
831 &NewElts[0], NewElts.size());
833 // Convert the new vector to the old vector type.
834 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
837 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
838 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
839 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
840 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
841 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
842 "can only promote integer arguments");
843 SDValue InOp = GetPromotedInteger(N->getOperand(0));
844 return DAG.getConvertRndSat(N->getValueType(0), InOp,
845 N->getOperand(1), N->getOperand(2),
846 N->getOperand(3), N->getOperand(4), CvtCode);
849 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
852 // Promote the inserted value. This is valid because the type does not
853 // have to match the vector element type.
855 // Check that any extra bits introduced will be truncated away.
856 assert(N->getOperand(1).getValueType().getSizeInBits() >=
857 N->getValueType(0).getVectorElementType().getSizeInBits() &&
858 "Type of inserted value narrower than vector element type!");
859 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
860 GetPromotedInteger(N->getOperand(1)),
864 assert(OpNo == 2 && "Different operand and result vector types?");
866 // Promote the index.
867 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
868 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
869 N->getOperand(1), Idx);
872 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
874 NewOps[0] = N->getOperand(0);
875 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
876 SDValue Flag = GetPromotedInteger(N->getOperand(i));
877 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
879 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
880 array_lengthof(NewOps));
883 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
884 assert(OpNo == 0 && "Only know how to promote condition");
885 SDValue Cond = GetPromotedInteger(N->getOperand(0));
887 // Promote all the way up to SVT, the canonical SetCC type.
888 // FIXME: Not clear what value to pass to getSetCCResultType.
889 // [This only matters for CellSPU since all other targets
890 // ignore the argument.] We used to pass Cond, resulting in
891 // SVT = MVT::i8, but CellSPU has no select patterns for i8,
892 // causing an abort later. Passing the result type works
893 // around the problem.
894 MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
895 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
896 assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
898 // Make sure the extra bits conform to getBooleanContents. There are
899 // two sets of extra bits: those in Cond, which come from type promotion,
900 // and those we need to add to have the final type be SVT (for most targets
901 // this last set of bits is empty).
902 unsigned CondBits = Cond.getValueSizeInBits();
903 ISD::NodeType ExtendCode;
904 switch (TLI.getBooleanContents()) {
906 assert(false && "Unknown BooleanContent!");
907 case TargetLowering::UndefinedBooleanContent:
908 // Extend to SVT by adding rubbish.
909 ExtendCode = ISD::ANY_EXTEND;
911 case TargetLowering::ZeroOrOneBooleanContent:
912 ExtendCode = ISD::ZERO_EXTEND;
913 if (!DAG.MaskedValueIsZero(Cond,APInt::getHighBitsSet(CondBits,CondBits-1)))
914 // All extra bits need to be cleared. Do this by zero extending the
915 // original condition value all the way to SVT.
916 Cond = N->getOperand(0);
918 case TargetLowering::ZeroOrNegativeOneBooleanContent: {
919 ExtendCode = ISD::SIGN_EXTEND;
920 unsigned SignBits = DAG.ComputeNumSignBits(Cond);
921 if (SignBits != CondBits)
922 // All extra bits need to be sign extended. Do this by sign extending the
923 // original condition value all the way to SVT.
924 Cond = N->getOperand(0);
928 Cond = DAG.getNode(ExtendCode, SVT, Cond);
930 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
931 N->getOperand(1), N->getOperand(2));
934 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
935 assert(OpNo == 0 && "Don't know how to promote this operand!");
937 SDValue LHS = N->getOperand(0);
938 SDValue RHS = N->getOperand(1);
939 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
941 // The CC (#4) and the possible return values (#2 and #3) have legal types.
942 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
943 N->getOperand(3), N->getOperand(4));
946 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
947 assert(OpNo == 0 && "Don't know how to promote this operand!");
949 SDValue LHS = N->getOperand(0);
950 SDValue RHS = N->getOperand(1);
951 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
953 // The CC (#2) is always legal.
954 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
957 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
958 SDValue Op = GetPromotedInteger(N->getOperand(0));
959 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
960 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
961 Op, DAG.getValueType(N->getOperand(0).getValueType()));
964 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
965 return DAG.UpdateNodeOperands(SDValue(N, 0),
966 SExtPromotedInteger(N->getOperand(0)));
969 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
970 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
971 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
972 int SVOffset = N->getSrcValueOffset();
973 unsigned Alignment = N->getAlignment();
974 bool isVolatile = N->isVolatile();
976 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
978 // Truncate the value and store the result.
979 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
980 SVOffset, N->getMemoryVT(),
981 isVolatile, Alignment);
984 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
985 SDValue Op = GetPromotedInteger(N->getOperand(0));
986 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
989 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
990 return DAG.UpdateNodeOperands(SDValue(N, 0),
991 ZExtPromotedInteger(N->getOperand(0)));
994 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
995 SDValue Op = GetPromotedInteger(N->getOperand(0));
996 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
997 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
1001 //===----------------------------------------------------------------------===//
1002 // Integer Result Expansion
1003 //===----------------------------------------------------------------------===//
1005 /// ExpandIntegerResult - This method is called when the specified result of the
1006 /// specified node is found to need expansion. At this point, the node may also
1007 /// have invalid operands or may have other results that need promotion, we just
1008 /// know that (at least) one result needs expansion.
1009 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1010 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
1012 Lo = Hi = SDValue();
1014 // See if the target wants to custom expand this node.
1015 if (CustomLowerResults(N, ResNo))
1018 switch (N->getOpcode()) {
1021 cerr << "ExpandIntegerResult #" << ResNo << ": ";
1022 N->dump(&DAG); cerr << "\n";
1024 assert(0 && "Do not know how to expand the result of this operator!");
1027 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
1028 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1029 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1030 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1032 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
1033 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1034 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1035 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1036 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1038 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1039 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1040 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1041 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1042 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1043 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1044 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1045 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1046 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1047 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1048 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1049 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1050 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1051 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1052 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1053 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1054 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1055 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1056 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1057 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1061 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1064 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1067 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1070 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1074 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1077 // If Lo/Hi is null, the sub-method took care of registering results etc.
1079 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1082 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1083 /// and the shift amount is a constant 'Amt'. Expand the operation.
1084 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1085 SDValue &Lo, SDValue &Hi) {
1086 // Expand the incoming operand to be shifted, so that we have its parts
1088 GetExpandedInteger(N->getOperand(0), InL, InH);
1090 MVT NVT = InL.getValueType();
1091 unsigned VTBits = N->getValueType(0).getSizeInBits();
1092 unsigned NVTBits = NVT.getSizeInBits();
1093 MVT ShTy = N->getOperand(1).getValueType();
1095 if (N->getOpcode() == ISD::SHL) {
1097 Lo = Hi = DAG.getConstant(0, NVT);
1098 } else if (Amt > NVTBits) {
1099 Lo = DAG.getConstant(0, NVT);
1100 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1101 } else if (Amt == NVTBits) {
1102 Lo = DAG.getConstant(0, NVT);
1104 } else if (Amt == 1 &&
1105 TLI.isOperationLegal(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) {
1106 // Emit this X << 1 as X+X.
1107 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1108 SDValue LoOps[2] = { InL, InL };
1109 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1110 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1111 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1113 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1114 Hi = DAG.getNode(ISD::OR, NVT,
1115 DAG.getNode(ISD::SHL, NVT, InH,
1116 DAG.getConstant(Amt, ShTy)),
1117 DAG.getNode(ISD::SRL, NVT, InL,
1118 DAG.getConstant(NVTBits-Amt, ShTy)));
1123 if (N->getOpcode() == ISD::SRL) {
1125 Lo = DAG.getConstant(0, NVT);
1126 Hi = DAG.getConstant(0, NVT);
1127 } else if (Amt > NVTBits) {
1128 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1129 Hi = DAG.getConstant(0, NVT);
1130 } else if (Amt == NVTBits) {
1132 Hi = DAG.getConstant(0, NVT);
1134 Lo = DAG.getNode(ISD::OR, NVT,
1135 DAG.getNode(ISD::SRL, NVT, InL,
1136 DAG.getConstant(Amt, ShTy)),
1137 DAG.getNode(ISD::SHL, NVT, InH,
1138 DAG.getConstant(NVTBits-Amt, ShTy)));
1139 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1144 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1146 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1147 DAG.getConstant(NVTBits-1, ShTy));
1148 } else if (Amt > NVTBits) {
1149 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1150 DAG.getConstant(Amt-NVTBits, ShTy));
1151 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1152 DAG.getConstant(NVTBits-1, ShTy));
1153 } else if (Amt == NVTBits) {
1155 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1156 DAG.getConstant(NVTBits-1, ShTy));
1158 Lo = DAG.getNode(ISD::OR, NVT,
1159 DAG.getNode(ISD::SRL, NVT, InL,
1160 DAG.getConstant(Amt, ShTy)),
1161 DAG.getNode(ISD::SHL, NVT, InH,
1162 DAG.getConstant(NVTBits-Amt, ShTy)));
1163 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1167 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1168 /// this shift based on knowledge of the high bit of the shift amount. If we
1169 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1171 bool DAGTypeLegalizer::
1172 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1173 SDValue Amt = N->getOperand(1);
1174 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1175 MVT ShTy = Amt.getValueType();
1176 unsigned ShBits = ShTy.getSizeInBits();
1177 unsigned NVTBits = NVT.getSizeInBits();
1178 assert(isPowerOf2_32(NVTBits) &&
1179 "Expanded integer type size not a power of two!");
1181 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1182 APInt KnownZero, KnownOne;
1183 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1185 // If we don't know anything about the high bits, exit.
1186 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1189 // Get the incoming operand to be shifted.
1191 GetExpandedInteger(N->getOperand(0), InL, InH);
1193 // If we know that any of the high bits of the shift amount are one, then we
1194 // can do this as a couple of simple shifts.
1195 if (KnownOne.intersects(HighBitMask)) {
1196 // Mask out the high bit, which we know is set.
1197 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1198 DAG.getConstant(~HighBitMask, ShTy));
1200 switch (N->getOpcode()) {
1201 default: assert(0 && "Unknown shift");
1203 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1204 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1207 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1208 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1211 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1212 DAG.getConstant(NVTBits-1, ShTy));
1213 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1219 // FIXME: This code is broken for shifts with a zero amount!
1220 // If we know that all of the high bits of the shift amount are zero, then we
1221 // can do this as a couple of simple shifts.
1222 if ((KnownZero & HighBitMask) == HighBitMask) {
1224 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1225 DAG.getConstant(NVTBits, ShTy),
1228 switch (N->getOpcode()) {
1229 default: assert(0 && "Unknown shift");
1230 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1232 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1235 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1236 Hi = DAG.getNode(ISD::OR, NVT,
1237 DAG.getNode(Op1, NVT, InH, Amt),
1238 DAG.getNode(Op2, NVT, InL, Amt2));
1246 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1247 SDValue &Lo, SDValue &Hi) {
1248 // Expand the subcomponents.
1249 SDValue LHSL, LHSH, RHSL, RHSH;
1250 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1251 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1253 MVT NVT = LHSL.getValueType();
1254 SDValue LoOps[2] = { LHSL, RHSL };
1255 SDValue HiOps[3] = { LHSH, RHSH };
1257 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1258 // them. TODO: Teach operation legalization how to expand unsupported
1259 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1260 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1261 // generate a value of this type in the expanded code sequence.
1263 TLI.isOperationLegal(N->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC,
1264 TLI.getTypeToExpandTo(NVT));
1267 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1268 if (N->getOpcode() == ISD::ADD) {
1269 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1270 HiOps[2] = Lo.getValue(1);
1271 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1273 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1274 HiOps[2] = Lo.getValue(1);
1275 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1278 if (N->getOpcode() == ISD::ADD) {
1279 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
1280 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
1281 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[0],
1283 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
1284 DAG.getConstant(1, NVT),
1285 DAG.getConstant(0, NVT));
1286 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo, LoOps[1],
1288 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
1289 DAG.getConstant(1, NVT), Carry1);
1290 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
1292 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
1293 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
1294 SDValue Cmp = DAG.getSetCC(TLI.getSetCCResultType(LoOps[0]),
1295 LoOps[0], LoOps[1], ISD::SETULT);
1296 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
1297 DAG.getConstant(1, NVT),
1298 DAG.getConstant(0, NVT));
1299 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
1304 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1305 SDValue &Lo, SDValue &Hi) {
1306 // Expand the subcomponents.
1307 SDValue LHSL, LHSH, RHSL, RHSH;
1308 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1309 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1310 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1311 SDValue LoOps[2] = { LHSL, RHSL };
1312 SDValue HiOps[3] = { LHSH, RHSH };
1314 if (N->getOpcode() == ISD::ADDC) {
1315 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1316 HiOps[2] = Lo.getValue(1);
1317 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1319 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1320 HiOps[2] = Lo.getValue(1);
1321 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1324 // Legalized the flag result - switch anything that used the old flag to
1326 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1329 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1330 SDValue &Lo, SDValue &Hi) {
1331 // Expand the subcomponents.
1332 SDValue LHSL, LHSH, RHSL, RHSH;
1333 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1334 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1335 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1336 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1337 SDValue HiOps[3] = { LHSH, RHSH };
1339 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1340 HiOps[2] = Lo.getValue(1);
1341 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1343 // Legalized the flag result - switch anything that used the old flag to
1345 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1348 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1349 SDValue &Lo, SDValue &Hi) {
1350 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1351 SDValue Op = N->getOperand(0);
1352 if (Op.getValueType().bitsLE(NVT)) {
1353 // The low part is any extension of the input (which degenerates to a copy).
1354 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
1355 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
1357 // For example, extension of an i48 to an i64. The operand type necessarily
1358 // promotes to the result type, so will end up being expanded too.
1359 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1360 "Only know how to promote this result!");
1361 SDValue Res = GetPromotedInteger(Op);
1362 assert(Res.getValueType() == N->getValueType(0) &&
1363 "Operand over promoted?");
1364 // Split the promoted operand. This will simplify when it is expanded.
1365 SplitInteger(Res, Lo, Hi);
1369 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1370 SDValue &Lo, SDValue &Hi) {
1371 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1372 MVT NVT = Lo.getValueType();
1373 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1374 unsigned NVTBits = NVT.getSizeInBits();
1375 unsigned EVTBits = EVT.getSizeInBits();
1377 if (NVTBits < EVTBits) {
1378 Hi = DAG.getNode(ISD::AssertSext, NVT, Hi,
1379 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1381 Lo = DAG.getNode(ISD::AssertSext, NVT, Lo, DAG.getValueType(EVT));
1382 // The high part replicates the sign bit of Lo, make it explicit.
1383 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1384 DAG.getConstant(NVTBits-1, TLI.getShiftAmountTy()));
1388 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1389 SDValue &Lo, SDValue &Hi) {
1390 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1391 MVT NVT = Lo.getValueType();
1392 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1393 unsigned NVTBits = NVT.getSizeInBits();
1394 unsigned EVTBits = EVT.getSizeInBits();
1396 if (NVTBits < EVTBits) {
1397 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
1398 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1400 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
1401 // The high part must be zero, make it explicit.
1402 Hi = DAG.getConstant(0, NVT);
1406 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1407 SDValue &Lo, SDValue &Hi) {
1408 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1409 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1410 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1413 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1414 SDValue &Lo, SDValue &Hi) {
1415 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1416 unsigned NBitWidth = NVT.getSizeInBits();
1417 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1418 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1419 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1422 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1423 SDValue &Lo, SDValue &Hi) {
1424 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1425 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1426 MVT NVT = Lo.getValueType();
1428 SDValue HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1429 DAG.getConstant(0, NVT), ISD::SETNE);
1431 SDValue LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1432 SDValue HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1434 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1435 DAG.getNode(ISD::ADD, NVT, LoLZ,
1436 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1437 Hi = DAG.getConstant(0, NVT);
1440 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1441 SDValue &Lo, SDValue &Hi) {
1442 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1443 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1444 MVT NVT = Lo.getValueType();
1445 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1446 DAG.getNode(ISD::CTPOP, NVT, Hi));
1447 Hi = DAG.getConstant(0, NVT);
1450 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1451 SDValue &Lo, SDValue &Hi) {
1452 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1453 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1454 MVT NVT = Lo.getValueType();
1456 SDValue LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1457 DAG.getConstant(0, NVT), ISD::SETNE);
1459 SDValue LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1460 SDValue HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1462 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1463 DAG.getNode(ISD::ADD, NVT, HiLZ,
1464 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1465 Hi = DAG.getConstant(0, NVT);
1468 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1470 MVT VT = N->getValueType(0);
1471 SDValue Op = N->getOperand(0);
1472 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1473 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1474 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1477 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1479 MVT VT = N->getValueType(0);
1480 SDValue Op = N->getOperand(0);
1481 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1482 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1483 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1486 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1487 SDValue &Lo, SDValue &Hi) {
1488 if (ISD::isNormalLoad(N)) {
1489 ExpandRes_NormalLoad(N, Lo, Hi);
1493 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1495 MVT VT = N->getValueType(0);
1496 MVT NVT = TLI.getTypeToTransformTo(VT);
1497 SDValue Ch = N->getChain();
1498 SDValue Ptr = N->getBasePtr();
1499 ISD::LoadExtType ExtType = N->getExtensionType();
1500 int SVOffset = N->getSrcValueOffset();
1501 unsigned Alignment = N->getAlignment();
1502 bool isVolatile = N->isVolatile();
1504 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1506 if (N->getMemoryVT().bitsLE(NVT)) {
1507 MVT EVT = N->getMemoryVT();
1509 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1510 isVolatile, Alignment);
1512 // Remember the chain.
1513 Ch = Lo.getValue(1);
1515 if (ExtType == ISD::SEXTLOAD) {
1516 // The high part is obtained by SRA'ing all but one of the bits of the
1518 unsigned LoSize = Lo.getValueType().getSizeInBits();
1519 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1520 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1521 } else if (ExtType == ISD::ZEXTLOAD) {
1522 // The high part is just a zero.
1523 Hi = DAG.getConstant(0, NVT);
1525 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1526 // The high part is undefined.
1527 Hi = DAG.getNode(ISD::UNDEF, NVT);
1529 } else if (TLI.isLittleEndian()) {
1530 // Little-endian - low bits are at low addresses.
1531 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1532 isVolatile, Alignment);
1534 unsigned ExcessBits =
1535 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1536 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1538 // Increment the pointer to the other half.
1539 unsigned IncrementSize = NVT.getSizeInBits()/8;
1540 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1541 DAG.getIntPtrConstant(IncrementSize));
1542 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1543 SVOffset+IncrementSize, NEVT,
1544 isVolatile, MinAlign(Alignment, IncrementSize));
1546 // Build a factor node to remember that this load is independent of the
1548 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1551 // Big-endian - high bits are at low addresses. Favor aligned loads at
1552 // the cost of some bit-fiddling.
1553 MVT EVT = N->getMemoryVT();
1554 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1555 unsigned IncrementSize = NVT.getSizeInBits()/8;
1556 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1558 // Load both the high bits and maybe some of the low bits.
1559 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1560 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1561 isVolatile, Alignment);
1563 // Increment the pointer to the other half.
1564 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1565 DAG.getIntPtrConstant(IncrementSize));
1566 // Load the rest of the low bits.
1567 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1568 SVOffset+IncrementSize,
1569 MVT::getIntegerVT(ExcessBits),
1570 isVolatile, MinAlign(Alignment, IncrementSize));
1572 // Build a factor node to remember that this load is independent of the
1574 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1577 if (ExcessBits < NVT.getSizeInBits()) {
1578 // Transfer low bits from the bottom of Hi to the top of Lo.
1579 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1580 DAG.getNode(ISD::SHL, NVT, Hi,
1581 DAG.getConstant(ExcessBits,
1582 TLI.getShiftAmountTy())));
1583 // Move high bits to the right position in Hi.
1584 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1585 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1586 TLI.getShiftAmountTy()));
1590 // Legalized the chain result - switch anything that used the old chain to
1592 ReplaceValueWith(SDValue(N, 1), Ch);
1595 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1596 SDValue &Lo, SDValue &Hi) {
1597 SDValue LL, LH, RL, RH;
1598 GetExpandedInteger(N->getOperand(0), LL, LH);
1599 GetExpandedInteger(N->getOperand(1), RL, RH);
1600 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1601 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1604 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1605 SDValue &Lo, SDValue &Hi) {
1606 MVT VT = N->getValueType(0);
1607 MVT NVT = TLI.getTypeToTransformTo(VT);
1609 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1610 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1611 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1612 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1613 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1614 SDValue LL, LH, RL, RH;
1615 GetExpandedInteger(N->getOperand(0), LL, LH);
1616 GetExpandedInteger(N->getOperand(1), RL, RH);
1617 unsigned OuterBitSize = VT.getSizeInBits();
1618 unsigned InnerBitSize = NVT.getSizeInBits();
1619 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1620 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1622 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1623 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1624 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1625 // The inputs are both zero-extended.
1627 // We can emit a umul_lohi.
1628 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1629 Hi = SDValue(Lo.getNode(), 1);
1633 // We can emit a mulhu+mul.
1634 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1635 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1639 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1640 // The input values are both sign-extended.
1642 // We can emit a smul_lohi.
1643 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1644 Hi = SDValue(Lo.getNode(), 1);
1648 // We can emit a mulhs+mul.
1649 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1650 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1655 // Lo,Hi = umul LHS, RHS.
1656 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1657 DAG.getVTList(NVT, NVT), LL, RL);
1659 Hi = UMulLOHI.getValue(1);
1660 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1661 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1662 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1663 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1667 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1668 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1669 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1670 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1671 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1672 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1677 // If nothing else, we can make a libcall.
1678 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1680 LC = RTLIB::MUL_I32;
1681 else if (VT == MVT::i64)
1682 LC = RTLIB::MUL_I64;
1683 else if (VT == MVT::i128)
1684 LC = RTLIB::MUL_I128;
1685 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1687 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1688 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1691 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1692 SDValue &Lo, SDValue &Hi) {
1693 MVT VT = N->getValueType(0);
1695 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1697 LC = RTLIB::SDIV_I32;
1698 else if (VT == MVT::i64)
1699 LC = RTLIB::SDIV_I64;
1700 else if (VT == MVT::i128)
1701 LC = RTLIB::SDIV_I128;
1702 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1704 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1705 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1708 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1709 SDValue &Lo, SDValue &Hi) {
1710 MVT VT = N->getValueType(0);
1712 // If we can emit an efficient shift operation, do so now. Check to see if
1713 // the RHS is a constant.
1714 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1715 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1717 // If we can determine that the high bit of the shift is zero or one, even if
1718 // the low bits are variable, emit this shift in an optimized form.
1719 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1722 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1724 if (N->getOpcode() == ISD::SHL) {
1725 PartsOpc = ISD::SHL_PARTS;
1726 } else if (N->getOpcode() == ISD::SRL) {
1727 PartsOpc = ISD::SRL_PARTS;
1729 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1730 PartsOpc = ISD::SRA_PARTS;
1733 // Next check to see if the target supports this SHL_PARTS operation or if it
1734 // will custom expand it.
1735 MVT NVT = TLI.getTypeToTransformTo(VT);
1736 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1737 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1738 Action == TargetLowering::Custom) {
1739 // Expand the subcomponents.
1741 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1743 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1744 MVT VT = LHSL.getValueType();
1745 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1746 Hi = Lo.getValue(1);
1750 // Otherwise, emit a libcall.
1751 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1753 if (N->getOpcode() == ISD::SHL) {
1754 isSigned = false; /*sign irrelevant*/
1756 LC = RTLIB::SHL_I32;
1757 else if (VT == MVT::i64)
1758 LC = RTLIB::SHL_I64;
1759 else if (VT == MVT::i128)
1760 LC = RTLIB::SHL_I128;
1761 } else if (N->getOpcode() == ISD::SRL) {
1764 LC = RTLIB::SRL_I32;
1765 else if (VT == MVT::i64)
1766 LC = RTLIB::SRL_I64;
1767 else if (VT == MVT::i128)
1768 LC = RTLIB::SRL_I128;
1770 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1773 LC = RTLIB::SRA_I32;
1774 else if (VT == MVT::i64)
1775 LC = RTLIB::SRA_I64;
1776 else if (VT == MVT::i128)
1777 LC = RTLIB::SRA_I128;
1779 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported shift!");
1781 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1782 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1785 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1786 SDValue &Lo, SDValue &Hi) {
1787 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1788 SDValue Op = N->getOperand(0);
1789 if (Op.getValueType().bitsLE(NVT)) {
1790 // The low part is sign extension of the input (degenerates to a copy).
1791 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
1792 // The high part is obtained by SRA'ing all but one of the bits of low part.
1793 unsigned LoSize = NVT.getSizeInBits();
1794 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1795 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1797 // For example, extension of an i48 to an i64. The operand type necessarily
1798 // promotes to the result type, so will end up being expanded too.
1799 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1800 "Only know how to promote this result!");
1801 SDValue Res = GetPromotedInteger(Op);
1802 assert(Res.getValueType() == N->getValueType(0) &&
1803 "Operand over promoted?");
1804 // Split the promoted operand. This will simplify when it is expanded.
1805 SplitInteger(Res, Lo, Hi);
1806 unsigned ExcessBits =
1807 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1808 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1809 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1813 void DAGTypeLegalizer::
1814 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1815 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1816 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1818 if (EVT.bitsLE(Lo.getValueType())) {
1819 // sext_inreg the low part if needed.
1820 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
1823 // The high part gets the sign extension from the lo-part. This handles
1824 // things like sextinreg V:i64 from i8.
1825 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
1826 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1827 TLI.getShiftAmountTy()));
1829 // For example, extension of an i48 to an i64. Leave the low part alone,
1830 // sext_inreg the high part.
1831 unsigned ExcessBits =
1832 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1833 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
1834 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1838 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1839 SDValue &Lo, SDValue &Hi) {
1840 MVT VT = N->getValueType(0);
1842 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1844 LC = RTLIB::SREM_I32;
1845 else if (VT == MVT::i64)
1846 LC = RTLIB::SREM_I64;
1847 else if (VT == MVT::i128)
1848 LC = RTLIB::SREM_I128;
1849 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1851 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1852 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true), Lo, Hi);
1855 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1856 SDValue &Lo, SDValue &Hi) {
1857 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1858 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
1859 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
1860 DAG.getConstant(NVT.getSizeInBits(),
1861 TLI.getShiftAmountTy()));
1862 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
1865 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1866 SDValue &Lo, SDValue &Hi) {
1867 MVT VT = N->getValueType(0);
1869 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1871 LC = RTLIB::UDIV_I32;
1872 else if (VT == MVT::i64)
1873 LC = RTLIB::UDIV_I64;
1874 else if (VT == MVT::i128)
1875 LC = RTLIB::UDIV_I128;
1876 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1878 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1879 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1882 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1883 SDValue &Lo, SDValue &Hi) {
1884 MVT VT = N->getValueType(0);
1886 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1888 LC = RTLIB::UREM_I32;
1889 else if (VT == MVT::i64)
1890 LC = RTLIB::UREM_I64;
1891 else if (VT == MVT::i128)
1892 LC = RTLIB::UREM_I128;
1893 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1895 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1896 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false), Lo, Hi);
1899 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1900 SDValue &Lo, SDValue &Hi) {
1901 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1902 SDValue Op = N->getOperand(0);
1903 if (Op.getValueType().bitsLE(NVT)) {
1904 // The low part is zero extension of the input (degenerates to a copy).
1905 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
1906 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1908 // For example, extension of an i48 to an i64. The operand type necessarily
1909 // promotes to the result type, so will end up being expanded too.
1910 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1911 "Only know how to promote this result!");
1912 SDValue Res = GetPromotedInteger(Op);
1913 assert(Res.getValueType() == N->getValueType(0) &&
1914 "Operand over promoted?");
1915 // Split the promoted operand. This will simplify when it is expanded.
1916 SplitInteger(Res, Lo, Hi);
1917 unsigned ExcessBits =
1918 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1919 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
1924 //===----------------------------------------------------------------------===//
1925 // Integer Operand Expansion
1926 //===----------------------------------------------------------------------===//
1928 /// ExpandIntegerOperand - This method is called when the specified operand of
1929 /// the specified node is found to need expansion. At this point, all of the
1930 /// result types of the node are known to be legal, but other operands of the
1931 /// node may need promotion or expansion as well as the specified one.
1932 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1933 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1934 SDValue Res = SDValue();
1936 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1937 == TargetLowering::Custom)
1938 Res = TLI.LowerOperation(SDValue(N, 0), DAG);
1940 if (Res.getNode() == 0) {
1941 switch (N->getOpcode()) {
1944 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1945 N->dump(&DAG); cerr << "\n";
1947 assert(0 && "Do not know how to expand this operator's operand!");
1950 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1951 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1952 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1953 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
1954 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
1956 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1957 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1958 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1959 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
1960 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1962 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1963 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
1967 // If the result is null, the sub-method took care of registering results etc.
1968 if (!Res.getNode()) return false;
1970 // If the result is N, the sub-method updated N in place. Tell the legalizer
1972 if (Res.getNode() == N)
1975 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1976 "Invalid operand expansion");
1978 ReplaceValueWith(SDValue(N, 0), Res);
1982 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1983 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1984 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
1986 ISD::CondCode &CCCode) {
1987 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
1988 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1989 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1991 MVT VT = NewLHS.getValueType();
1993 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1994 if (RHSLo == RHSHi) {
1995 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1996 if (RHSCST->isAllOnesValue()) {
1997 // Equality comparison to -1.
1998 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
2005 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
2006 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
2007 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
2008 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2012 // If this is a comparison of the sign bit, just look at the top part.
2014 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2015 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2016 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2022 // FIXME: This generated code sucks.
2023 ISD::CondCode LowCC;
2025 default: assert(0 && "Unknown integer setcc!");
2027 case ISD::SETULT: LowCC = ISD::SETULT; break;
2029 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2031 case ISD::SETULE: LowCC = ISD::SETULE; break;
2033 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2036 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2037 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2038 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2040 // NOTE: on targets without efficient SELECT of bools, we can always use
2041 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2042 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2044 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
2045 false, DagCombineInfo);
2046 if (!Tmp1.getNode())
2047 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
2048 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2049 CCCode, false, DagCombineInfo);
2050 if (!Tmp2.getNode())
2051 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2052 DAG.getCondCode(CCCode));
2054 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2055 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2056 if ((Tmp1C && Tmp1C->isNullValue()) ||
2057 (Tmp2C && Tmp2C->isNullValue() &&
2058 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2059 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2060 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2061 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2062 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2063 // low part is known false, returns high part.
2064 // For LE / GE, if high part is known false, ignore the low part.
2065 // For LT / GT, if high part is known true, ignore the low part.
2071 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2072 ISD::SETEQ, false, DagCombineInfo);
2073 if (!NewLHS.getNode())
2074 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
2076 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2077 NewLHS, Tmp1, Tmp2);
2081 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2082 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2083 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2084 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2086 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2087 // against zero to select between true and false values.
2088 if (NewRHS.getNode() == 0) {
2089 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2090 CCCode = ISD::SETNE;
2093 // Update N to have the operands specified.
2094 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2095 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2099 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2100 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2101 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2102 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2104 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2105 // against zero to select between true and false values.
2106 if (NewRHS.getNode() == 0) {
2107 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2108 CCCode = ISD::SETNE;
2111 // Update N to have the operands specified.
2112 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2113 N->getOperand(2), N->getOperand(3),
2114 DAG.getCondCode(CCCode));
2117 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2118 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2119 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2120 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
2122 // If ExpandSetCCOperands returned a scalar, use it.
2123 if (NewRHS.getNode() == 0) {
2124 assert(NewLHS.getValueType() == N->getValueType(0) &&
2125 "Unexpected setcc expansion!");
2129 // Otherwise, update N to have the operands specified.
2130 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2131 DAG.getCondCode(CCCode));
2134 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2135 SDValue Op = N->getOperand(0);
2136 MVT DstVT = N->getValueType(0);
2137 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2138 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2139 "Don't know how to expand this SINT_TO_FP!");
2140 return MakeLibCall(LC, DstVT, &Op, 1, true);
2143 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2144 if (ISD::isNormalStore(N))
2145 return ExpandOp_NormalStore(N, OpNo);
2147 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2148 assert(OpNo == 1 && "Can only expand the stored value so far");
2150 MVT VT = N->getOperand(1).getValueType();
2151 MVT NVT = TLI.getTypeToTransformTo(VT);
2152 SDValue Ch = N->getChain();
2153 SDValue Ptr = N->getBasePtr();
2154 int SVOffset = N->getSrcValueOffset();
2155 unsigned Alignment = N->getAlignment();
2156 bool isVolatile = N->isVolatile();
2159 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2161 if (N->getMemoryVT().bitsLE(NVT)) {
2162 GetExpandedInteger(N->getValue(), Lo, Hi);
2163 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2164 N->getMemoryVT(), isVolatile, Alignment);
2165 } else if (TLI.isLittleEndian()) {
2166 // Little-endian - low bits are at low addresses.
2167 GetExpandedInteger(N->getValue(), Lo, Hi);
2169 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
2170 isVolatile, Alignment);
2172 unsigned ExcessBits =
2173 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2174 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2176 // Increment the pointer to the other half.
2177 unsigned IncrementSize = NVT.getSizeInBits()/8;
2178 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2179 DAG.getIntPtrConstant(IncrementSize));
2180 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2181 SVOffset+IncrementSize, NEVT,
2182 isVolatile, MinAlign(Alignment, IncrementSize));
2183 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2185 // Big-endian - high bits are at low addresses. Favor aligned stores at
2186 // the cost of some bit-fiddling.
2187 GetExpandedInteger(N->getValue(), Lo, Hi);
2189 MVT EVT = N->getMemoryVT();
2190 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2191 unsigned IncrementSize = NVT.getSizeInBits()/8;
2192 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2193 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2195 if (ExcessBits < NVT.getSizeInBits()) {
2196 // Transfer high bits from the top of Lo to the bottom of Hi.
2197 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
2198 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2199 TLI.getShiftAmountTy()));
2200 Hi = DAG.getNode(ISD::OR, NVT, Hi,
2201 DAG.getNode(ISD::SRL, NVT, Lo,
2202 DAG.getConstant(ExcessBits,
2203 TLI.getShiftAmountTy())));
2206 // Store both the high bits and maybe some of the low bits.
2207 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
2208 SVOffset, HiVT, isVolatile, Alignment);
2210 // Increment the pointer to the other half.
2211 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2212 DAG.getIntPtrConstant(IncrementSize));
2213 // Store the lowest ExcessBits bits in the second half.
2214 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2215 SVOffset+IncrementSize,
2216 MVT::getIntegerVT(ExcessBits),
2217 isVolatile, MinAlign(Alignment, IncrementSize));
2218 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2222 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2224 GetExpandedInteger(N->getOperand(0), InL, InH);
2225 // Just truncate the low part of the source.
2226 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
2229 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2230 SDValue Op = N->getOperand(0);
2231 MVT SrcVT = Op.getValueType();
2232 MVT DstVT = N->getValueType(0);
2234 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2235 // Do a signed conversion then adjust the result.
2236 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, DstVT, Op);
2237 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2239 // The result of the signed conversion needs adjusting if the 'sign bit' of
2240 // the incoming integer was set. To handle this, we dynamically test to see
2241 // if it is set, and, if so, add a fudge factor.
2243 const uint64_t F32TwoE32 = 0x4F800000ULL;
2244 const uint64_t F32TwoE64 = 0x5F800000ULL;
2245 const uint64_t F32TwoE128 = 0x7F800000ULL;
2248 if (SrcVT == MVT::i32)
2249 FF = APInt(32, F32TwoE32);
2250 else if (SrcVT == MVT::i64)
2251 FF = APInt(32, F32TwoE64);
2252 else if (SrcVT == MVT::i128)
2253 FF = APInt(32, F32TwoE128);
2255 assert(false && "Unsupported UINT_TO_FP!");
2257 // Check whether the sign bit is set.
2259 GetExpandedInteger(Op, Lo, Hi);
2260 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
2261 DAG.getConstant(0, Hi.getValueType()),
2264 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2265 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2266 TLI.getPointerTy());
2268 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2269 SDValue Zero = DAG.getIntPtrConstant(0);
2270 SDValue Four = DAG.getIntPtrConstant(4);
2271 if (TLI.isBigEndian()) std::swap(Zero, Four);
2272 SDValue Offset = DAG.getNode(ISD::SELECT, Zero.getValueType(), SignSet,
2274 unsigned Alignment =
2275 1 << cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2276 FudgePtr = DAG.getNode(ISD::ADD, TLI.getPointerTy(), FudgePtr, Offset);
2277 Alignment = std::min(Alignment, 4u);
2279 // Load the value out, extending it from f32 to the destination float type.
2280 // FIXME: Avoid the extend by constructing the right constant pool?
2281 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, DstVT, DAG.getEntryNode(),
2282 FudgePtr, NULL, 0, MVT::f32,
2284 return DAG.getNode(ISD::FADD, DstVT, SignedConv, Fudge);
2287 // Otherwise, use a libcall.
2288 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2289 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2290 "Don't know how to expand this UINT_TO_FP!");
2291 return MakeLibCall(LC, DstVT, &Op, 1, true);