1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/CodeGen/PseudoSourceValue.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDValue Res = SDValue();
37 // See if the target wants to custom expand this node.
38 if (CustomLowerResults(N, N->getValueType(ResNo), true))
41 switch (N->getOpcode()) {
44 cerr << "PromoteIntegerResult #" << ResNo << ": ";
45 N->dump(&DAG); cerr << "\n";
47 assert(0 && "Do not know how to promote this operator!");
49 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
50 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
51 case ISD::BIT_CONVERT: Res = PromoteIntRes_BIT_CONVERT(N); break;
52 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
53 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
54 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
55 case ISD::CONVERT_RNDSAT:
56 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
57 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
58 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
59 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
60 case ISD::EXTRACT_VECTOR_ELT:
61 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
62 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
63 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
64 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
65 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
66 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
67 case ISD::SIGN_EXTEND_INREG:
68 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
69 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
70 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
71 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
72 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
73 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
75 case ISD::SIGN_EXTEND:
76 case ISD::ZERO_EXTEND:
77 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
80 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
87 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
90 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
93 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
96 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
98 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
100 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
102 case ISD::ATOMIC_LOAD_ADD:
103 case ISD::ATOMIC_LOAD_SUB:
104 case ISD::ATOMIC_LOAD_AND:
105 case ISD::ATOMIC_LOAD_OR:
106 case ISD::ATOMIC_LOAD_XOR:
107 case ISD::ATOMIC_LOAD_NAND:
108 case ISD::ATOMIC_LOAD_MIN:
109 case ISD::ATOMIC_LOAD_MAX:
110 case ISD::ATOMIC_LOAD_UMIN:
111 case ISD::ATOMIC_LOAD_UMAX:
112 case ISD::ATOMIC_SWAP:
113 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
115 case ISD::ATOMIC_CMP_SWAP:
116 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
119 // If the result is null then the sub-method took care of registering it.
121 SetPromotedInteger(SDValue(N, ResNo), Res);
124 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
125 // Sign-extend the new bits, and continue the assertion.
126 SDValue Op = SExtPromotedInteger(N->getOperand(0));
127 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
128 Op.getValueType(), Op, N->getOperand(1));
131 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
132 // Zero the new bits, and continue the assertion.
133 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
134 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
135 Op.getValueType(), Op, N->getOperand(1));
138 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
139 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
140 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
142 N->getChain(), N->getBasePtr(),
143 Op2, N->getSrcValue(), N->getAlignment());
144 // Legalized the chain result - switch anything that used the old chain to
146 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
150 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
151 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
152 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
153 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
154 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
155 Op2, Op3, N->getSrcValue(), N->getAlignment());
156 // Legalized the chain result - switch anything that used the old chain to
158 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
162 SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
163 SDValue InOp = N->getOperand(0);
164 MVT InVT = InOp.getValueType();
165 MVT NInVT = TLI.getTypeToTransformTo(InVT);
166 MVT OutVT = N->getValueType(0);
167 MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
168 DebugLoc dl = N->getDebugLoc();
170 switch (getTypeAction(InVT)) {
172 assert(false && "Unknown type action!");
177 if (NOutVT.bitsEq(NInVT))
178 // The input promotes to the same size. Convert the promoted value.
179 return DAG.getNode(ISD::BIT_CONVERT, dl,
180 NOutVT, GetPromotedInteger(InOp));
183 // Promote the integer operand by hand.
184 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
188 case ScalarizeVector:
189 // Convert the element to an integer and promote it by hand.
190 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
191 BitConvertToInteger(GetScalarizedVector(InOp)));
193 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
194 // pieces of the input into integers and reassemble in the final type.
196 GetSplitVector(N->getOperand(0), Lo, Hi);
197 Lo = BitConvertToInteger(Lo);
198 Hi = BitConvertToInteger(Hi);
200 if (TLI.isBigEndian())
203 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
204 MVT::getIntegerVT(NOutVT.getSizeInBits()),
205 JoinIntegers(Lo, Hi));
206 return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
209 if (OutVT.bitsEq(NInVT))
210 // The input is widened to the same size. Convert to the widened value.
211 return DAG.getNode(ISD::BIT_CONVERT, dl, OutVT, GetWidenedVector(InOp));
214 // Otherwise, lower the bit-convert to a store/load from the stack.
215 // Create the stack frame object. Make sure it is aligned for both
216 // the source and destination types.
217 SDValue FIPtr = DAG.CreateStackTemporary(InVT, OutVT);
218 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
219 const Value *SV = PseudoSourceValue::getFixedStack(FI);
221 // Emit a store to the stack slot.
222 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, InOp, FIPtr, SV, 0);
224 // Result is an extending load from the stack slot.
225 return DAG.getExtLoad(ISD::EXTLOAD, dl, NOutVT, Store, FIPtr, SV, 0, OutVT);
228 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
229 SDValue Op = GetPromotedInteger(N->getOperand(0));
230 MVT OVT = N->getValueType(0);
231 MVT NVT = Op.getValueType();
232 DebugLoc dl = N->getDebugLoc();
234 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
235 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
236 DAG.getConstant(DiffBits, TLI.getPointerTy()));
239 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
240 // The pair element type may be legal, or may not promote to the same type as
241 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
242 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
243 TLI.getTypeToTransformTo(N->getValueType(0)),
244 JoinIntegers(N->getOperand(0), N->getOperand(1)));
247 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
248 MVT VT = N->getValueType(0);
249 // FIXME there is no actual debug info here
250 DebugLoc dl = N->getDebugLoc();
251 // Zero extend things like i1, sign extend everything else. It shouldn't
252 // matter in theory which one we pick, but this tends to give better code?
253 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
254 SDValue Result = DAG.getNode(Opc, dl, TLI.getTypeToTransformTo(VT),
256 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
260 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
261 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
262 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
263 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
264 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
265 "can only promote integers");
266 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
267 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
268 N->getOperand(1), N->getOperand(2),
269 N->getOperand(3), N->getOperand(4), CvtCode);
272 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
273 // Zero extend to the promoted type and do the count there.
274 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
275 DebugLoc dl = N->getDebugLoc();
276 MVT OVT = N->getValueType(0);
277 MVT NVT = Op.getValueType();
278 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
279 // Subtract off the extra leading bits in the bigger type.
280 return DAG.getNode(ISD::SUB, dl, NVT, Op,
281 DAG.getConstant(NVT.getSizeInBits() -
282 OVT.getSizeInBits(), NVT));
285 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
286 // Zero extend to the promoted type and do the count there.
287 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
288 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
291 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
292 SDValue Op = GetPromotedInteger(N->getOperand(0));
293 MVT OVT = N->getValueType(0);
294 MVT NVT = Op.getValueType();
295 DebugLoc dl = N->getDebugLoc();
296 // The count is the same in the promoted type except if the original
297 // value was zero. This can be handled by setting the bit just off
298 // the top of the original type.
299 APInt TopBit(NVT.getSizeInBits(), 0);
300 TopBit.set(OVT.getSizeInBits());
301 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
302 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
305 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
306 MVT OldVT = N->getValueType(0);
307 SDValue OldVec = N->getOperand(0);
308 if (getTypeAction(OldVec.getValueType()) == WidenVector)
309 OldVec = GetWidenedVector(N->getOperand(0));
310 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
311 DebugLoc dl = N->getDebugLoc();
314 assert(!isTypeLegal(OldVec.getValueType()) &&
315 "Legal one-element vector of a type needing promotion!");
316 // It is tempting to follow GetScalarizedVector by a call to
317 // GetPromotedInteger, but this would be wrong because the
318 // scalarized value may not yet have been processed.
319 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT),
320 GetScalarizedVector(OldVec));
323 // Convert to a vector half as long with an element type of twice the width,
324 // for example <4 x i16> -> <2 x i32>.
325 assert(!(OldElts & 1) && "Odd length vectors not supported!");
326 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
327 assert(OldVT.isSimple() && NewVT.isSimple());
329 SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
330 MVT::getVectorVT(NewVT, OldElts / 2),
333 // Extract the element at OldIdx / 2 from the new vector.
334 SDValue OldIdx = N->getOperand(1);
335 SDValue NewIdx = DAG.getNode(ISD::SRL, dl, OldIdx.getValueType(), OldIdx,
336 DAG.getConstant(1, TLI.getPointerTy()));
337 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, NewIdx);
339 // Select the appropriate half of the element: Lo if OldIdx was even,
342 SDValue Hi = DAG.getNode(ISD::SRL, dl, NewVT, Elt,
343 DAG.getConstant(OldVT.getSizeInBits(),
344 TLI.getPointerTy()));
345 if (TLI.isBigEndian())
348 // Extend to the promoted type.
349 SDValue Odd = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, OldIdx);
350 SDValue Res = DAG.getNode(ISD::SELECT, dl, NewVT, Odd, Hi, Lo);
351 return DAG.getNode(ISD::ANY_EXTEND, dl, TLI.getTypeToTransformTo(OldVT), Res);
354 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
355 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
356 unsigned NewOpc = N->getOpcode();
357 DebugLoc dl = N->getDebugLoc();
359 // If we're promoting a UINT to a larger size, check to see if the new node
360 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
361 // we can use that instead. This allows us to generate better code for
362 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
363 // legal, such as PowerPC.
364 if (N->getOpcode() == ISD::FP_TO_UINT &&
365 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
366 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
367 NewOpc = ISD::FP_TO_SINT;
369 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
371 // Assert that the converted value fits in the original type. If it doesn't
372 // (eg: because the value being converted is too big), then the result of the
373 // original operation was undefined anyway, so the assert is still correct.
374 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
375 ISD::AssertZext : ISD::AssertSext, dl,
376 NVT, Res, DAG.getValueType(N->getValueType(0)));
379 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
380 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
381 DebugLoc dl = N->getDebugLoc();
383 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
384 SDValue Res = GetPromotedInteger(N->getOperand(0));
385 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
387 // If the result and operand types are the same after promotion, simplify
388 // to an in-register extension.
389 if (NVT == Res.getValueType()) {
390 // The high bits are not guaranteed to be anything. Insert an extend.
391 if (N->getOpcode() == ISD::SIGN_EXTEND)
392 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
393 DAG.getValueType(N->getOperand(0).getValueType()));
394 if (N->getOpcode() == ISD::ZERO_EXTEND)
395 return DAG.getZeroExtendInReg(Res, dl, N->getOperand(0).getValueType());
396 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
401 // Otherwise, just extend the original operand all the way to the larger type.
402 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
405 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
406 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
407 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
408 ISD::LoadExtType ExtType =
409 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
410 DebugLoc dl = N->getDebugLoc();
411 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
412 N->getSrcValue(), N->getSrcValueOffset(),
413 N->getMemoryVT(), N->isVolatile(),
416 // Legalized the chain result - switch anything that used the old chain to
418 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
422 /// Promote the overflow flag of an overflowing arithmetic node.
423 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
424 // Simply change the return type of the boolean result.
425 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
426 MVT ValueVTs[] = { N->getValueType(0), NVT };
427 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
428 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
429 DAG.getVTList(ValueVTs, 2), Ops, 2);
431 // Modified the sum result - switch anything that used the old sum to use
433 ReplaceValueWith(SDValue(N, 0), Res);
435 return SDValue(Res.getNode(), 1);
438 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
440 return PromoteIntRes_Overflow(N);
442 // The operation overflowed iff the result in the larger type is not the
443 // sign extension of its truncation to the original type.
444 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
445 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
446 MVT OVT = N->getOperand(0).getValueType();
447 MVT NVT = LHS.getValueType();
448 DebugLoc dl = N->getDebugLoc();
450 // Do the arithmetic in the larger type.
451 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
452 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
454 // Calculate the overflow flag: sign extend the arithmetic result from
455 // the original type.
456 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
457 DAG.getValueType(OVT));
458 // Overflowed if and only if this is not equal to Res.
459 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
461 // Use the calculated overflow everywhere.
462 ReplaceValueWith(SDValue(N, 1), Ofl);
467 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
468 // Sign extend the input.
469 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
470 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
471 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
472 LHS.getValueType(), LHS, RHS);
475 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
476 SDValue LHS = GetPromotedInteger(N->getOperand(1));
477 SDValue RHS = GetPromotedInteger(N->getOperand(2));
478 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
479 LHS.getValueType(), N->getOperand(0),LHS,RHS);
482 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
483 SDValue LHS = GetPromotedInteger(N->getOperand(2));
484 SDValue RHS = GetPromotedInteger(N->getOperand(3));
485 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
486 LHS.getValueType(), N->getOperand(0),
487 N->getOperand(1), LHS, RHS, N->getOperand(4));
490 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
491 MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
492 assert(isTypeLegal(SVT) && "Illegal SetCC type!");
493 DebugLoc dl = N->getDebugLoc();
495 // Get the SETCC result using the canonical SETCC type.
496 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, SVT, N->getOperand(0),
497 N->getOperand(1), N->getOperand(2));
499 // Convert to the expected type.
500 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
501 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
502 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
505 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
506 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
507 TLI.getTypeToTransformTo(N->getValueType(0)),
508 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
511 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
512 SDValue Op = GetPromotedInteger(N->getOperand(0));
513 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
514 Op.getValueType(), Op, N->getOperand(1));
517 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
518 // The input may have strange things in the top bits of the registers, but
519 // these operations don't care. They may have weird bits going out, but
520 // that too is okay if they are integer operations.
521 SDValue LHS = GetPromotedInteger(N->getOperand(0));
522 SDValue RHS = GetPromotedInteger(N->getOperand(1));
523 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
524 LHS.getValueType(), LHS, RHS);
527 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
528 // The input value must be properly sign extended.
529 SDValue Res = SExtPromotedInteger(N->getOperand(0));
530 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
531 Res.getValueType(), Res, N->getOperand(1));
534 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
535 // The input value must be properly zero extended.
536 MVT VT = N->getValueType(0);
537 MVT NVT = TLI.getTypeToTransformTo(VT);
538 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
539 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
542 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
543 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
546 switch (getTypeAction(N->getOperand(0).getValueType())) {
547 default: assert(0 && "Unknown type action!");
550 Res = N->getOperand(0);
553 Res = GetPromotedInteger(N->getOperand(0));
557 // Truncate to NVT instead of VT
558 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
561 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
563 return PromoteIntRes_Overflow(N);
565 // The operation overflowed iff the result in the larger type is not the
566 // zero extension of its truncation to the original type.
567 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
568 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
569 MVT OVT = N->getOperand(0).getValueType();
570 MVT NVT = LHS.getValueType();
571 DebugLoc dl = N->getDebugLoc();
573 // Do the arithmetic in the larger type.
574 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
575 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
577 // Calculate the overflow flag: zero extend the arithmetic result from
578 // the original type.
579 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
580 // Overflowed if and only if this is not equal to Res.
581 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
583 // Use the calculated overflow everywhere.
584 ReplaceValueWith(SDValue(N, 1), Ofl);
589 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
590 // Zero extend the input.
591 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
592 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
593 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
594 LHS.getValueType(), LHS, RHS);
597 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
598 return DAG.getUNDEF(TLI.getTypeToTransformTo(N->getValueType(0)));
601 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
602 SDValue Chain = N->getOperand(0); // Get the chain.
603 SDValue Ptr = N->getOperand(1); // Get the pointer.
604 MVT VT = N->getValueType(0);
605 DebugLoc dl = N->getDebugLoc();
607 MVT RegVT = TLI.getRegisterType(VT);
608 unsigned NumRegs = TLI.getNumRegisters(VT);
609 // The argument is passed as NumRegs registers of type RegVT.
611 SmallVector<SDValue, 8> Parts(NumRegs);
612 for (unsigned i = 0; i < NumRegs; ++i) {
613 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2));
614 Chain = Parts[i].getValue(1);
617 // Handle endianness of the load.
618 if (TLI.isBigEndian())
619 std::reverse(Parts.begin(), Parts.end());
621 // Assemble the parts in the promoted type.
622 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
623 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
624 for (unsigned i = 1; i < NumRegs; ++i) {
625 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
626 // Shift it to the right position and "or" it in.
627 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
628 DAG.getConstant(i * RegVT.getSizeInBits(),
629 TLI.getPointerTy()));
630 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
633 // Modified the chain result - switch anything that used the old chain to
635 ReplaceValueWith(SDValue(N, 1), Chain);
640 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
641 assert(ResNo == 1 && "Only boolean result promotion currently supported!");
642 return PromoteIntRes_Overflow(N);
645 //===----------------------------------------------------------------------===//
646 // Integer Operand Promotion
647 //===----------------------------------------------------------------------===//
649 /// PromoteIntegerOperand - This method is called when the specified operand of
650 /// the specified node is found to need promotion. At this point, all of the
651 /// result types of the node are known to be legal, but other operands of the
652 /// node may need promotion or expansion as well as the specified one.
653 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
654 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
655 SDValue Res = SDValue();
657 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
660 switch (N->getOpcode()) {
663 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
664 N->dump(&DAG); cerr << "\n";
666 assert(0 && "Do not know how to promote this operator's operand!");
669 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
670 case ISD::BIT_CONVERT: Res = PromoteIntOp_BIT_CONVERT(N); break;
671 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
672 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
673 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
674 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
675 case ISD::CONVERT_RNDSAT:
676 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
677 case ISD::INSERT_VECTOR_ELT:
678 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
679 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
680 case ISD::SCALAR_TO_VECTOR:
681 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
682 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
683 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
684 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
685 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
686 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
687 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
689 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
690 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
691 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
697 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
700 // If the result is null, the sub-method took care of registering results etc.
701 if (!Res.getNode()) return false;
703 // If the result is N, the sub-method updated N in place. Tell the legalizer
705 if (Res.getNode() == N)
708 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
709 "Invalid operand expansion");
711 ReplaceValueWith(SDValue(N, 0), Res);
715 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
716 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
717 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
718 ISD::CondCode CCCode) {
719 // We have to insert explicit sign or zero extends. Note that we could
720 // insert sign extends for ALL conditions, but zero extend is cheaper on
721 // many machines (an AND instead of two shifts), so prefer it.
723 default: assert(0 && "Unknown integer comparison!");
730 // ALL of these operations will work if we either sign or zero extend
731 // the operands (including the unsigned comparisons!). Zero extend is
732 // usually a simpler/cheaper operation, so prefer it.
733 NewLHS = ZExtPromotedInteger(NewLHS);
734 NewRHS = ZExtPromotedInteger(NewRHS);
740 NewLHS = SExtPromotedInteger(NewLHS);
741 NewRHS = SExtPromotedInteger(NewRHS);
746 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
747 SDValue Op = GetPromotedInteger(N->getOperand(0));
748 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
751 SDValue DAGTypeLegalizer::PromoteIntOp_BIT_CONVERT(SDNode *N) {
752 // This should only occur in unusual situations like bitcasting to an
753 // x86_fp80, so just turn it into a store+load
754 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
757 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
758 assert(OpNo == 2 && "Don't know how to promote this operand!");
760 SDValue LHS = N->getOperand(2);
761 SDValue RHS = N->getOperand(3);
762 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
764 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
766 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
767 N->getOperand(1), LHS, RHS, N->getOperand(4));
770 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
771 assert(OpNo == 1 && "only know how to promote condition");
773 // Promote all the way up to the canonical SetCC type.
774 MVT SVT = TLI.getSetCCResultType(MVT::Other);
775 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
777 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
778 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Cond,
782 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
783 // Since the result type is legal, the operands must promote to it.
784 MVT OVT = N->getOperand(0).getValueType();
785 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
786 SDValue Hi = GetPromotedInteger(N->getOperand(1));
787 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
788 DebugLoc dl = N->getDebugLoc();
790 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
791 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
792 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
795 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
796 // The vector type is legal but the element type is not. This implies
797 // that the vector is a power-of-two in length and that the element
798 // type does not have a strange size (eg: it is not i1).
799 MVT VecVT = N->getValueType(0);
800 unsigned NumElts = VecVT.getVectorNumElements();
801 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
803 // Promote the inserted value. The type does not need to match the
804 // vector element type. Check that any extra bits introduced will be
806 assert(N->getOperand(0).getValueType().getSizeInBits() >=
807 N->getValueType(0).getVectorElementType().getSizeInBits() &&
808 "Type of inserted value narrower than vector element type!");
810 SmallVector<SDValue, 16> NewOps;
811 for (unsigned i = 0; i < NumElts; ++i) {
812 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
815 return DAG.UpdateNodeOperands(SDValue(N, 0), &NewOps[0], NumElts);
818 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
819 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
820 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
821 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
822 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
823 "can only promote integer arguments");
824 SDValue InOp = GetPromotedInteger(N->getOperand(0));
825 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
826 N->getOperand(1), N->getOperand(2),
827 N->getOperand(3), N->getOperand(4), CvtCode);
830 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
833 // Promote the inserted value. This is valid because the type does not
834 // have to match the vector element type.
836 // Check that any extra bits introduced will be truncated away.
837 assert(N->getOperand(1).getValueType().getSizeInBits() >=
838 N->getValueType(0).getVectorElementType().getSizeInBits() &&
839 "Type of inserted value narrower than vector element type!");
840 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
841 GetPromotedInteger(N->getOperand(1)),
845 assert(OpNo == 2 && "Different operand and result vector types?");
847 // Promote the index.
848 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
849 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
850 N->getOperand(1), Idx);
853 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
855 DebugLoc dl = N->getDebugLoc();
856 NewOps[0] = N->getOperand(0);
857 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
858 SDValue Flag = GetPromotedInteger(N->getOperand(i));
859 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
861 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
862 array_lengthof(NewOps));
865 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
866 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
867 // the operand in place.
868 return DAG.UpdateNodeOperands(SDValue(N, 0),
869 GetPromotedInteger(N->getOperand(0)));
872 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
873 assert(OpNo == 0 && "Only know how to promote condition");
875 // Promote all the way up to the canonical SetCC type.
876 MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
877 SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
879 return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
880 N->getOperand(1), N->getOperand(2));
883 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
884 assert(OpNo == 0 && "Don't know how to promote this operand!");
886 SDValue LHS = N->getOperand(0);
887 SDValue RHS = N->getOperand(1);
888 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
890 // The CC (#4) and the possible return values (#2 and #3) have legal types.
891 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2),
892 N->getOperand(3), N->getOperand(4));
895 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
896 assert(OpNo == 0 && "Don't know how to promote this operand!");
898 SDValue LHS = N->getOperand(0);
899 SDValue RHS = N->getOperand(1);
900 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
902 // The CC (#2) is always legal.
903 return DAG.UpdateNodeOperands(SDValue(N, 0), LHS, RHS, N->getOperand(2));
906 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
907 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
908 ZExtPromotedInteger(N->getOperand(1)));
911 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
912 SDValue Op = GetPromotedInteger(N->getOperand(0));
913 DebugLoc dl = N->getDebugLoc();
914 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
915 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
916 Op, DAG.getValueType(N->getOperand(0).getValueType()));
919 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
920 return DAG.UpdateNodeOperands(SDValue(N, 0),
921 SExtPromotedInteger(N->getOperand(0)));
924 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
925 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
926 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
927 int SVOffset = N->getSrcValueOffset();
928 unsigned Alignment = N->getAlignment();
929 bool isVolatile = N->isVolatile();
930 DebugLoc dl = N->getDebugLoc();
932 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
934 // Truncate the value and store the result.
935 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getSrcValue(),
936 SVOffset, N->getMemoryVT(),
937 isVolatile, Alignment);
940 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
941 SDValue Op = GetPromotedInteger(N->getOperand(0));
942 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
945 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
946 return DAG.UpdateNodeOperands(SDValue(N, 0),
947 ZExtPromotedInteger(N->getOperand(0)));
950 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
951 DebugLoc dl = N->getDebugLoc();
952 SDValue Op = GetPromotedInteger(N->getOperand(0));
953 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
954 return DAG.getZeroExtendInReg(Op, dl, N->getOperand(0).getValueType());
958 //===----------------------------------------------------------------------===//
959 // Integer Result Expansion
960 //===----------------------------------------------------------------------===//
962 /// ExpandIntegerResult - This method is called when the specified result of the
963 /// specified node is found to need expansion. At this point, the node may also
964 /// have invalid operands or may have other results that need promotion, we just
965 /// know that (at least) one result needs expansion.
966 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
967 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
971 // See if the target wants to custom expand this node.
972 if (CustomLowerResults(N, N->getValueType(ResNo), true))
975 switch (N->getOpcode()) {
978 cerr << "ExpandIntegerResult #" << ResNo << ": ";
979 N->dump(&DAG); cerr << "\n";
981 assert(0 && "Do not know how to expand the result of this operator!");
984 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
985 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
986 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
987 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
989 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
990 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
991 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
992 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
993 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
995 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
996 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
997 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
998 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
999 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1000 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1001 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1002 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1003 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1004 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1005 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1006 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1007 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1008 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1009 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1010 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1011 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1012 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1013 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1014 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1018 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1021 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1024 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1027 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1031 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1034 // If Lo/Hi is null, the sub-method took care of registering results etc.
1036 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1039 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1040 /// and the shift amount is a constant 'Amt'. Expand the operation.
1041 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1042 SDValue &Lo, SDValue &Hi) {
1043 DebugLoc dl = N->getDebugLoc();
1044 // Expand the incoming operand to be shifted, so that we have its parts
1046 GetExpandedInteger(N->getOperand(0), InL, InH);
1048 MVT NVT = InL.getValueType();
1049 unsigned VTBits = N->getValueType(0).getSizeInBits();
1050 unsigned NVTBits = NVT.getSizeInBits();
1051 MVT ShTy = N->getOperand(1).getValueType();
1053 if (N->getOpcode() == ISD::SHL) {
1055 Lo = Hi = DAG.getConstant(0, NVT);
1056 } else if (Amt > NVTBits) {
1057 Lo = DAG.getConstant(0, NVT);
1058 Hi = DAG.getNode(ISD::SHL, dl,
1059 NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1060 } else if (Amt == NVTBits) {
1061 Lo = DAG.getConstant(0, NVT);
1063 } else if (Amt == 1 &&
1064 TLI.isOperationLegalOrCustom(ISD::ADDC,
1065 TLI.getTypeToExpandTo(NVT))) {
1066 // Emit this X << 1 as X+X.
1067 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1068 SDValue LoOps[2] = { InL, InL };
1069 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1070 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1071 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1073 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Amt, ShTy));
1074 Hi = DAG.getNode(ISD::OR, dl, NVT,
1075 DAG.getNode(ISD::SHL, dl, NVT, InH,
1076 DAG.getConstant(Amt, ShTy)),
1077 DAG.getNode(ISD::SRL, dl, NVT, InL,
1078 DAG.getConstant(NVTBits-Amt, ShTy)));
1083 if (N->getOpcode() == ISD::SRL) {
1085 Lo = DAG.getConstant(0, NVT);
1086 Hi = DAG.getConstant(0, NVT);
1087 } else if (Amt > NVTBits) {
1088 Lo = DAG.getNode(ISD::SRL, dl,
1089 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1090 Hi = DAG.getConstant(0, NVT);
1091 } else if (Amt == NVTBits) {
1093 Hi = DAG.getConstant(0, NVT);
1095 Lo = DAG.getNode(ISD::OR, dl, NVT,
1096 DAG.getNode(ISD::SRL, dl, NVT, InL,
1097 DAG.getConstant(Amt, ShTy)),
1098 DAG.getNode(ISD::SHL, dl, NVT, InH,
1099 DAG.getConstant(NVTBits-Amt, ShTy)));
1100 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1105 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1107 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1108 DAG.getConstant(NVTBits-1, ShTy));
1109 } else if (Amt > NVTBits) {
1110 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
1111 DAG.getConstant(Amt-NVTBits, ShTy));
1112 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1113 DAG.getConstant(NVTBits-1, ShTy));
1114 } else if (Amt == NVTBits) {
1116 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
1117 DAG.getConstant(NVTBits-1, ShTy));
1119 Lo = DAG.getNode(ISD::OR, dl, NVT,
1120 DAG.getNode(ISD::SRL, dl, NVT, InL,
1121 DAG.getConstant(Amt, ShTy)),
1122 DAG.getNode(ISD::SHL, dl, NVT, InH,
1123 DAG.getConstant(NVTBits-Amt, ShTy)));
1124 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Amt, ShTy));
1128 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1129 /// this shift based on knowledge of the high bit of the shift amount. If we
1130 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1132 bool DAGTypeLegalizer::
1133 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1134 SDValue Amt = N->getOperand(1);
1135 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1136 MVT ShTy = Amt.getValueType();
1137 unsigned ShBits = ShTy.getSizeInBits();
1138 unsigned NVTBits = NVT.getSizeInBits();
1139 assert(isPowerOf2_32(NVTBits) &&
1140 "Expanded integer type size not a power of two!");
1141 DebugLoc dl = N->getDebugLoc();
1143 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1144 APInt KnownZero, KnownOne;
1145 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1147 // If we don't know anything about the high bits, exit.
1148 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1151 // Get the incoming operand to be shifted.
1153 GetExpandedInteger(N->getOperand(0), InL, InH);
1155 // If we know that any of the high bits of the shift amount are one, then we
1156 // can do this as a couple of simple shifts.
1157 if (KnownOne.intersects(HighBitMask)) {
1158 // Mask out the high bit, which we know is set.
1159 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1160 DAG.getConstant(~HighBitMask, ShTy));
1162 switch (N->getOpcode()) {
1163 default: assert(0 && "Unknown shift");
1165 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1166 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1169 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1170 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1173 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1174 DAG.getConstant(NVTBits-1, ShTy));
1175 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1181 // FIXME: This code is broken for shifts with a zero amount!
1182 // If we know that all of the high bits of the shift amount are zero, then we
1183 // can do this as a couple of simple shifts.
1184 if ((KnownZero & HighBitMask) == HighBitMask) {
1186 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1187 DAG.getConstant(NVTBits, ShTy),
1190 switch (N->getOpcode()) {
1191 default: assert(0 && "Unknown shift");
1192 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1194 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1197 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1198 Hi = DAG.getNode(ISD::OR, NVT,
1199 DAG.getNode(Op1, NVT, InH, Amt),
1200 DAG.getNode(Op2, NVT, InL, Amt2));
1208 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1210 bool DAGTypeLegalizer::
1211 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1212 SDValue Amt = N->getOperand(1);
1213 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1214 MVT ShTy = Amt.getValueType();
1215 unsigned NVTBits = NVT.getSizeInBits();
1216 assert(isPowerOf2_32(NVTBits) &&
1217 "Expanded integer type size not a power of two!");
1218 DebugLoc dl = N->getDebugLoc();
1220 // Get the incoming operand to be shifted.
1222 GetExpandedInteger(N->getOperand(0), InL, InH);
1224 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1225 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1226 SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1227 Amt, NVBitsNode, ISD::SETULT);
1229 SDValue Lo1, Hi1, Lo2, Hi2;
1230 switch (N->getOpcode()) {
1231 default: assert(0 && "Unknown shift");
1234 Lo1 = DAG.getConstant(0, NVT); // Low part is zero.
1235 Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1238 Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1239 Hi2 = DAG.getNode(ISD::OR, dl, NVT,
1240 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1241 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
1243 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1244 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1248 Hi1 = DAG.getConstant(0, NVT); // Hi part is zero.
1249 Lo1 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1252 Hi2 = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1253 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1254 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1255 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1257 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1258 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1262 Hi1 = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1263 DAG.getConstant(NVTBits-1, ShTy));
1264 Lo1 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1267 Hi2 = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1268 Lo2 = DAG.getNode(ISD::OR, dl, NVT,
1269 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1270 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
1272 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Lo1, Lo2);
1273 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Cmp, Hi1, Hi2);
1280 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1281 SDValue &Lo, SDValue &Hi) {
1282 DebugLoc dl = N->getDebugLoc();
1283 // Expand the subcomponents.
1284 SDValue LHSL, LHSH, RHSL, RHSH;
1285 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1286 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1288 MVT NVT = LHSL.getValueType();
1289 SDValue LoOps[2] = { LHSL, RHSL };
1290 SDValue HiOps[3] = { LHSH, RHSH };
1292 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1293 // them. TODO: Teach operation legalization how to expand unsupported
1294 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1295 // a carry of type MVT::Flag, but there doesn't seem to be any way to
1296 // generate a value of this type in the expanded code sequence.
1298 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1299 ISD::ADDC : ISD::SUBC,
1300 TLI.getTypeToExpandTo(NVT));
1303 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
1304 if (N->getOpcode() == ISD::ADD) {
1305 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1306 HiOps[2] = Lo.getValue(1);
1307 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1309 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1310 HiOps[2] = Lo.getValue(1);
1311 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1314 if (N->getOpcode() == ISD::ADD) {
1315 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1316 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1317 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1319 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1320 DAG.getConstant(1, NVT),
1321 DAG.getConstant(0, NVT));
1322 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1324 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1325 DAG.getConstant(1, NVT), Carry1);
1326 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1328 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1329 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1331 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1332 LoOps[0], LoOps[1], ISD::SETULT);
1333 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1334 DAG.getConstant(1, NVT),
1335 DAG.getConstant(0, NVT));
1336 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1341 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1342 SDValue &Lo, SDValue &Hi) {
1343 // Expand the subcomponents.
1344 SDValue LHSL, LHSH, RHSL, RHSH;
1345 DebugLoc dl = N->getDebugLoc();
1346 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1347 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1348 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1349 SDValue LoOps[2] = { LHSL, RHSL };
1350 SDValue HiOps[3] = { LHSH, RHSH };
1352 if (N->getOpcode() == ISD::ADDC) {
1353 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1354 HiOps[2] = Lo.getValue(1);
1355 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1357 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1358 HiOps[2] = Lo.getValue(1);
1359 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1362 // Legalized the flag result - switch anything that used the old flag to
1364 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1367 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1368 SDValue &Lo, SDValue &Hi) {
1369 // Expand the subcomponents.
1370 SDValue LHSL, LHSH, RHSL, RHSH;
1371 DebugLoc dl = N->getDebugLoc();
1372 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1373 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1374 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1375 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1376 SDValue HiOps[3] = { LHSH, RHSH };
1378 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1379 HiOps[2] = Lo.getValue(1);
1380 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1382 // Legalized the flag result - switch anything that used the old flag to
1384 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1387 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1388 SDValue &Lo, SDValue &Hi) {
1389 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1390 DebugLoc dl = N->getDebugLoc();
1391 SDValue Op = N->getOperand(0);
1392 if (Op.getValueType().bitsLE(NVT)) {
1393 // The low part is any extension of the input (which degenerates to a copy).
1394 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1395 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1397 // For example, extension of an i48 to an i64. The operand type necessarily
1398 // promotes to the result type, so will end up being expanded too.
1399 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1400 "Only know how to promote this result!");
1401 SDValue Res = GetPromotedInteger(Op);
1402 assert(Res.getValueType() == N->getValueType(0) &&
1403 "Operand over promoted?");
1404 // Split the promoted operand. This will simplify when it is expanded.
1405 SplitInteger(Res, Lo, Hi);
1409 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1410 SDValue &Lo, SDValue &Hi) {
1411 DebugLoc dl = N->getDebugLoc();
1412 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1413 MVT NVT = Lo.getValueType();
1414 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1415 unsigned NVTBits = NVT.getSizeInBits();
1416 unsigned EVTBits = EVT.getSizeInBits();
1418 if (NVTBits < EVTBits) {
1419 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1420 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1422 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1423 // The high part replicates the sign bit of Lo, make it explicit.
1424 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1425 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1429 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1430 SDValue &Lo, SDValue &Hi) {
1431 DebugLoc dl = N->getDebugLoc();
1432 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1433 MVT NVT = Lo.getValueType();
1434 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1435 unsigned NVTBits = NVT.getSizeInBits();
1436 unsigned EVTBits = EVT.getSizeInBits();
1438 if (NVTBits < EVTBits) {
1439 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1440 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
1442 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1443 // The high part must be zero, make it explicit.
1444 Hi = DAG.getConstant(0, NVT);
1448 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1449 SDValue &Lo, SDValue &Hi) {
1450 DebugLoc dl = N->getDebugLoc();
1451 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1452 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1453 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1456 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1457 SDValue &Lo, SDValue &Hi) {
1458 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1459 unsigned NBitWidth = NVT.getSizeInBits();
1460 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1461 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
1462 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1465 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1466 SDValue &Lo, SDValue &Hi) {
1467 DebugLoc dl = N->getDebugLoc();
1468 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1469 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1470 MVT NVT = Lo.getValueType();
1472 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1473 DAG.getConstant(0, NVT), ISD::SETNE);
1475 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1476 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1478 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1479 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1480 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1481 Hi = DAG.getConstant(0, NVT);
1484 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1485 SDValue &Lo, SDValue &Hi) {
1486 DebugLoc dl = N->getDebugLoc();
1487 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1488 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1489 MVT NVT = Lo.getValueType();
1490 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1491 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1492 Hi = DAG.getConstant(0, NVT);
1495 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1496 SDValue &Lo, SDValue &Hi) {
1497 DebugLoc dl = N->getDebugLoc();
1498 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1499 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1500 MVT NVT = Lo.getValueType();
1502 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1503 DAG.getConstant(0, NVT), ISD::SETNE);
1505 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1506 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1508 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1509 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1510 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1511 Hi = DAG.getConstant(0, NVT);
1514 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1516 DebugLoc dl = N->getDebugLoc();
1517 MVT VT = N->getValueType(0);
1518 SDValue Op = N->getOperand(0);
1519 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1520 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1521 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1524 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1526 DebugLoc dl = N->getDebugLoc();
1527 MVT VT = N->getValueType(0);
1528 SDValue Op = N->getOperand(0);
1529 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1530 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1531 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1534 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1535 SDValue &Lo, SDValue &Hi) {
1536 if (ISD::isNormalLoad(N)) {
1537 ExpandRes_NormalLoad(N, Lo, Hi);
1541 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1543 MVT VT = N->getValueType(0);
1544 MVT NVT = TLI.getTypeToTransformTo(VT);
1545 SDValue Ch = N->getChain();
1546 SDValue Ptr = N->getBasePtr();
1547 ISD::LoadExtType ExtType = N->getExtensionType();
1548 int SVOffset = N->getSrcValueOffset();
1549 unsigned Alignment = N->getAlignment();
1550 bool isVolatile = N->isVolatile();
1551 DebugLoc dl = N->getDebugLoc();
1553 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1555 if (N->getMemoryVT().bitsLE(NVT)) {
1556 MVT EVT = N->getMemoryVT();
1558 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1559 EVT, isVolatile, Alignment);
1561 // Remember the chain.
1562 Ch = Lo.getValue(1);
1564 if (ExtType == ISD::SEXTLOAD) {
1565 // The high part is obtained by SRA'ing all but one of the bits of the
1567 unsigned LoSize = Lo.getValueType().getSizeInBits();
1568 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1569 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1570 } else if (ExtType == ISD::ZEXTLOAD) {
1571 // The high part is just a zero.
1572 Hi = DAG.getConstant(0, NVT);
1574 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1575 // The high part is undefined.
1576 Hi = DAG.getUNDEF(NVT);
1578 } else if (TLI.isLittleEndian()) {
1579 // Little-endian - low bits are at low addresses.
1580 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getSrcValue(), SVOffset,
1581 isVolatile, Alignment);
1583 unsigned ExcessBits =
1584 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1585 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1587 // Increment the pointer to the other half.
1588 unsigned IncrementSize = NVT.getSizeInBits()/8;
1589 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1590 DAG.getIntPtrConstant(IncrementSize));
1591 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(),
1592 SVOffset+IncrementSize, NEVT,
1593 isVolatile, MinAlign(Alignment, IncrementSize));
1595 // Build a factor node to remember that this load is independent of the
1597 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1600 // Big-endian - high bits are at low addresses. Favor aligned loads at
1601 // the cost of some bit-fiddling.
1602 MVT EVT = N->getMemoryVT();
1603 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1604 unsigned IncrementSize = NVT.getSizeInBits()/8;
1605 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1607 // Load both the high bits and maybe some of the low bits.
1608 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1609 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1610 isVolatile, Alignment);
1612 // Increment the pointer to the other half.
1613 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1614 DAG.getIntPtrConstant(IncrementSize));
1615 // Load the rest of the low bits.
1616 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
1617 SVOffset+IncrementSize,
1618 MVT::getIntegerVT(ExcessBits),
1619 isVolatile, MinAlign(Alignment, IncrementSize));
1621 // Build a factor node to remember that this load is independent of the
1623 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1626 if (ExcessBits < NVT.getSizeInBits()) {
1627 // Transfer low bits from the bottom of Hi to the top of Lo.
1628 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1629 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1630 DAG.getConstant(ExcessBits,
1631 TLI.getPointerTy())));
1632 // Move high bits to the right position in Hi.
1633 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1635 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1636 TLI.getPointerTy()));
1640 // Legalized the chain result - switch anything that used the old chain to
1642 ReplaceValueWith(SDValue(N, 1), Ch);
1645 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1646 SDValue &Lo, SDValue &Hi) {
1647 DebugLoc dl = N->getDebugLoc();
1648 SDValue LL, LH, RL, RH;
1649 GetExpandedInteger(N->getOperand(0), LL, LH);
1650 GetExpandedInteger(N->getOperand(1), RL, RH);
1651 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1652 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1655 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1656 SDValue &Lo, SDValue &Hi) {
1657 MVT VT = N->getValueType(0);
1658 MVT NVT = TLI.getTypeToTransformTo(VT);
1659 DebugLoc dl = N->getDebugLoc();
1661 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1662 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1663 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1664 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1665 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1666 SDValue LL, LH, RL, RH;
1667 GetExpandedInteger(N->getOperand(0), LL, LH);
1668 GetExpandedInteger(N->getOperand(1), RL, RH);
1669 unsigned OuterBitSize = VT.getSizeInBits();
1670 unsigned InnerBitSize = NVT.getSizeInBits();
1671 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1672 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1674 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1675 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1676 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1677 // The inputs are both zero-extended.
1679 // We can emit a umul_lohi.
1680 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1681 Hi = SDValue(Lo.getNode(), 1);
1685 // We can emit a mulhu+mul.
1686 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1687 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1691 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1692 // The input values are both sign-extended.
1694 // We can emit a smul_lohi.
1695 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1696 Hi = SDValue(Lo.getNode(), 1);
1700 // We can emit a mulhs+mul.
1701 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1702 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1707 // Lo,Hi = umul LHS, RHS.
1708 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1709 DAG.getVTList(NVT, NVT), LL, RL);
1711 Hi = UMulLOHI.getValue(1);
1712 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1713 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1714 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1715 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1719 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1720 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1721 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1722 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1723 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1724 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1729 // If nothing else, we can make a libcall.
1730 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1732 LC = RTLIB::MUL_I16;
1733 else if (VT == MVT::i32)
1734 LC = RTLIB::MUL_I32;
1735 else if (VT == MVT::i64)
1736 LC = RTLIB::MUL_I64;
1737 else if (VT == MVT::i128)
1738 LC = RTLIB::MUL_I128;
1739 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1741 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1742 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1745 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1746 SDValue &Lo, SDValue &Hi) {
1747 MVT VT = N->getValueType(0);
1748 DebugLoc dl = N->getDebugLoc();
1750 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1752 LC = RTLIB::SDIV_I32;
1753 else if (VT == MVT::i64)
1754 LC = RTLIB::SDIV_I64;
1755 else if (VT == MVT::i128)
1756 LC = RTLIB::SDIV_I128;
1757 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1759 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1760 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1763 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1764 SDValue &Lo, SDValue &Hi) {
1765 MVT VT = N->getValueType(0);
1766 DebugLoc dl = N->getDebugLoc();
1768 // If we can emit an efficient shift operation, do so now. Check to see if
1769 // the RHS is a constant.
1770 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1771 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
1773 // If we can determine that the high bit of the shift is zero or one, even if
1774 // the low bits are variable, emit this shift in an optimized form.
1775 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1778 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1780 if (N->getOpcode() == ISD::SHL) {
1781 PartsOpc = ISD::SHL_PARTS;
1782 } else if (N->getOpcode() == ISD::SRL) {
1783 PartsOpc = ISD::SRL_PARTS;
1785 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1786 PartsOpc = ISD::SRA_PARTS;
1789 // Next check to see if the target supports this SHL_PARTS operation or if it
1790 // will custom expand it.
1791 MVT NVT = TLI.getTypeToTransformTo(VT);
1792 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1793 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1794 Action == TargetLowering::Custom) {
1795 // Expand the subcomponents.
1797 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1799 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
1800 MVT VT = LHSL.getValueType();
1801 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
1802 Hi = Lo.getValue(1);
1806 // Otherwise, emit a libcall.
1807 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1809 if (N->getOpcode() == ISD::SHL) {
1810 isSigned = false; /*sign irrelevant*/
1812 LC = RTLIB::SHL_I16;
1813 else if (VT == MVT::i32)
1814 LC = RTLIB::SHL_I32;
1815 else if (VT == MVT::i64)
1816 LC = RTLIB::SHL_I64;
1817 else if (VT == MVT::i128)
1818 LC = RTLIB::SHL_I128;
1819 } else if (N->getOpcode() == ISD::SRL) {
1822 LC = RTLIB::SRL_I16;
1823 else if (VT == MVT::i32)
1824 LC = RTLIB::SRL_I32;
1825 else if (VT == MVT::i64)
1826 LC = RTLIB::SRL_I64;
1827 else if (VT == MVT::i128)
1828 LC = RTLIB::SRL_I128;
1830 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1833 LC = RTLIB::SRA_I16;
1834 else if (VT == MVT::i32)
1835 LC = RTLIB::SRA_I32;
1836 else if (VT == MVT::i64)
1837 LC = RTLIB::SRA_I64;
1838 else if (VT == MVT::i128)
1839 LC = RTLIB::SRA_I128;
1842 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
1843 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1844 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
1848 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
1849 assert(0 && "Unsupported shift!");
1852 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
1853 SDValue &Lo, SDValue &Hi) {
1854 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1855 DebugLoc dl = N->getDebugLoc();
1856 SDValue Op = N->getOperand(0);
1857 if (Op.getValueType().bitsLE(NVT)) {
1858 // The low part is sign extension of the input (degenerates to a copy).
1859 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
1860 // The high part is obtained by SRA'ing all but one of the bits of low part.
1861 unsigned LoSize = NVT.getSizeInBits();
1862 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1863 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1865 // For example, extension of an i48 to an i64. The operand type necessarily
1866 // promotes to the result type, so will end up being expanded too.
1867 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1868 "Only know how to promote this result!");
1869 SDValue Res = GetPromotedInteger(Op);
1870 assert(Res.getValueType() == N->getValueType(0) &&
1871 "Operand over promoted?");
1872 // Split the promoted operand. This will simplify when it is expanded.
1873 SplitInteger(Res, Lo, Hi);
1874 unsigned ExcessBits =
1875 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1876 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1877 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1881 void DAGTypeLegalizer::
1882 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
1883 DebugLoc dl = N->getDebugLoc();
1884 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1885 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1887 if (EVT.bitsLE(Lo.getValueType())) {
1888 // sext_inreg the low part if needed.
1889 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
1892 // The high part gets the sign extension from the lo-part. This handles
1893 // things like sextinreg V:i64 from i8.
1894 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
1895 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
1896 TLI.getPointerTy()));
1898 // For example, extension of an i48 to an i64. Leave the low part alone,
1899 // sext_inreg the high part.
1900 unsigned ExcessBits =
1901 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
1902 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
1903 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
1907 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1908 SDValue &Lo, SDValue &Hi) {
1909 MVT VT = N->getValueType(0);
1910 DebugLoc dl = N->getDebugLoc();
1912 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1914 LC = RTLIB::SREM_I32;
1915 else if (VT == MVT::i64)
1916 LC = RTLIB::SREM_I64;
1917 else if (VT == MVT::i128)
1918 LC = RTLIB::SREM_I128;
1919 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1921 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1922 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
1925 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
1926 SDValue &Lo, SDValue &Hi) {
1927 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1928 DebugLoc dl = N->getDebugLoc();
1929 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
1930 Hi = DAG.getNode(ISD::SRL, dl,
1931 N->getOperand(0).getValueType(), N->getOperand(0),
1932 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
1933 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
1936 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1937 SDValue &Lo, SDValue &Hi) {
1938 MVT VT = N->getValueType(0);
1939 DebugLoc dl = N->getDebugLoc();
1941 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1943 LC = RTLIB::UDIV_I32;
1944 else if (VT == MVT::i64)
1945 LC = RTLIB::UDIV_I64;
1946 else if (VT == MVT::i128)
1947 LC = RTLIB::UDIV_I128;
1948 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
1950 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1951 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1954 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1955 SDValue &Lo, SDValue &Hi) {
1956 MVT VT = N->getValueType(0);
1957 DebugLoc dl = N->getDebugLoc();
1959 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1961 LC = RTLIB::UREM_I32;
1962 else if (VT == MVT::i64)
1963 LC = RTLIB::UREM_I64;
1964 else if (VT == MVT::i128)
1965 LC = RTLIB::UREM_I128;
1966 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
1968 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1969 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
1972 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
1973 SDValue &Lo, SDValue &Hi) {
1974 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1975 DebugLoc dl = N->getDebugLoc();
1976 SDValue Op = N->getOperand(0);
1977 if (Op.getValueType().bitsLE(NVT)) {
1978 // The low part is zero extension of the input (degenerates to a copy).
1979 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
1980 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
1982 // For example, extension of an i48 to an i64. The operand type necessarily
1983 // promotes to the result type, so will end up being expanded too.
1984 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
1985 "Only know how to promote this result!");
1986 SDValue Res = GetPromotedInteger(Op);
1987 assert(Res.getValueType() == N->getValueType(0) &&
1988 "Operand over promoted?");
1989 // Split the promoted operand. This will simplify when it is expanded.
1990 SplitInteger(Res, Lo, Hi);
1991 unsigned ExcessBits =
1992 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
1993 Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
1998 //===----------------------------------------------------------------------===//
1999 // Integer Operand Expansion
2000 //===----------------------------------------------------------------------===//
2002 /// ExpandIntegerOperand - This method is called when the specified operand of
2003 /// the specified node is found to need expansion. At this point, all of the
2004 /// result types of the node are known to be legal, but other operands of the
2005 /// node may need promotion or expansion as well as the specified one.
2006 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2007 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
2008 SDValue Res = SDValue();
2010 if (CustomLowerResults(N, N->getOperand(OpNo).getValueType(), false))
2013 switch (N->getOpcode()) {
2016 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
2017 N->dump(&DAG); cerr << "\n";
2019 assert(0 && "Do not know how to expand this operator's operand!");
2022 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
2023 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2024 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2025 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2026 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2027 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2028 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2029 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2030 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2031 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2032 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2033 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2039 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2042 // If the result is null, the sub-method took care of registering results etc.
2043 if (!Res.getNode()) return false;
2045 // If the result is N, the sub-method updated N in place. Tell the legalizer
2047 if (Res.getNode() == N)
2050 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2051 "Invalid operand expansion");
2053 ReplaceValueWith(SDValue(N, 0), Res);
2057 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2058 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2059 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2061 ISD::CondCode &CCCode,
2063 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2064 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2065 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2067 MVT VT = NewLHS.getValueType();
2069 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2070 if (RHSLo == RHSHi) {
2071 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2072 if (RHSCST->isAllOnesValue()) {
2073 // Equality comparison to -1.
2074 NewLHS = DAG.getNode(ISD::AND, dl,
2075 LHSLo.getValueType(), LHSLo, LHSHi);
2082 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2083 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2084 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2085 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2089 // If this is a comparison of the sign bit, just look at the top part.
2091 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2092 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2093 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2099 // FIXME: This generated code sucks.
2100 ISD::CondCode LowCC;
2102 default: assert(0 && "Unknown integer setcc!");
2104 case ISD::SETULT: LowCC = ISD::SETULT; break;
2106 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2108 case ISD::SETULE: LowCC = ISD::SETULE; break;
2110 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2113 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2114 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2115 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2117 // NOTE: on targets without efficient SELECT of bools, we can always use
2118 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2119 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
2121 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2122 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2123 if (!Tmp1.getNode())
2124 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2125 LHSLo, RHSLo, LowCC);
2126 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2127 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2128 if (!Tmp2.getNode())
2129 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2130 TLI.getSetCCResultType(LHSHi.getValueType()),
2131 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2133 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2134 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2135 if ((Tmp1C && Tmp1C->isNullValue()) ||
2136 (Tmp2C && Tmp2C->isNullValue() &&
2137 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2138 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2139 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2140 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2141 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2142 // low part is known false, returns high part.
2143 // For LE / GE, if high part is known false, ignore the low part.
2144 // For LT / GT, if high part is known true, ignore the low part.
2150 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2151 LHSHi, RHSHi, ISD::SETEQ, false,
2152 DagCombineInfo, dl);
2153 if (!NewLHS.getNode())
2154 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2155 LHSHi, RHSHi, ISD::SETEQ);
2156 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2157 NewLHS, Tmp1, Tmp2);
2161 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2162 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2163 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2164 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2166 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2167 // against zero to select between true and false values.
2168 if (NewRHS.getNode() == 0) {
2169 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2170 CCCode = ISD::SETNE;
2173 // Update N to have the operands specified.
2174 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0),
2175 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2179 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2180 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2181 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2182 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2184 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2185 // against zero to select between true and false values.
2186 if (NewRHS.getNode() == 0) {
2187 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2188 CCCode = ISD::SETNE;
2191 // Update N to have the operands specified.
2192 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2193 N->getOperand(2), N->getOperand(3),
2194 DAG.getCondCode(CCCode));
2197 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2198 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2199 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2200 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2202 // If ExpandSetCCOperands returned a scalar, use it.
2203 if (NewRHS.getNode() == 0) {
2204 assert(NewLHS.getValueType() == N->getValueType(0) &&
2205 "Unexpected setcc expansion!");
2209 // Otherwise, update N to have the operands specified.
2210 return DAG.UpdateNodeOperands(SDValue(N, 0), NewLHS, NewRHS,
2211 DAG.getCondCode(CCCode));
2214 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2215 // The value being shifted is legal, but the shift amount is too big.
2216 // It follows that either the result of the shift is undefined, or the
2217 // upper half of the shift amount is zero. Just use the lower half.
2219 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2220 return DAG.UpdateNodeOperands(SDValue(N, 0), N->getOperand(0), Lo);
2223 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2224 SDValue Op = N->getOperand(0);
2225 MVT DstVT = N->getValueType(0);
2226 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2227 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2228 "Don't know how to expand this SINT_TO_FP!");
2229 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2232 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2233 if (ISD::isNormalStore(N))
2234 return ExpandOp_NormalStore(N, OpNo);
2236 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2237 assert(OpNo == 1 && "Can only expand the stored value so far");
2239 MVT VT = N->getOperand(1).getValueType();
2240 MVT NVT = TLI.getTypeToTransformTo(VT);
2241 SDValue Ch = N->getChain();
2242 SDValue Ptr = N->getBasePtr();
2243 int SVOffset = N->getSrcValueOffset();
2244 unsigned Alignment = N->getAlignment();
2245 bool isVolatile = N->isVolatile();
2246 DebugLoc dl = N->getDebugLoc();
2249 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2251 if (N->getMemoryVT().bitsLE(NVT)) {
2252 GetExpandedInteger(N->getValue(), Lo, Hi);
2253 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2254 N->getMemoryVT(), isVolatile, Alignment);
2255 } else if (TLI.isLittleEndian()) {
2256 // Little-endian - low bits are at low addresses.
2257 GetExpandedInteger(N->getValue(), Lo, Hi);
2259 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset,
2260 isVolatile, Alignment);
2262 unsigned ExcessBits =
2263 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2264 MVT NEVT = MVT::getIntegerVT(ExcessBits);
2266 // Increment the pointer to the other half.
2267 unsigned IncrementSize = NVT.getSizeInBits()/8;
2268 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2269 DAG.getIntPtrConstant(IncrementSize));
2270 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2271 SVOffset+IncrementSize, NEVT,
2272 isVolatile, MinAlign(Alignment, IncrementSize));
2273 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2275 // Big-endian - high bits are at low addresses. Favor aligned stores at
2276 // the cost of some bit-fiddling.
2277 GetExpandedInteger(N->getValue(), Lo, Hi);
2279 MVT EVT = N->getMemoryVT();
2280 unsigned EBytes = EVT.getStoreSizeInBits()/8;
2281 unsigned IncrementSize = NVT.getSizeInBits()/8;
2282 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2283 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
2285 if (ExcessBits < NVT.getSizeInBits()) {
2286 // Transfer high bits from the top of Lo to the bottom of Hi.
2287 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2288 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2289 TLI.getPointerTy()));
2290 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2291 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2292 DAG.getConstant(ExcessBits,
2293 TLI.getPointerTy())));
2296 // Store both the high bits and maybe some of the low bits.
2297 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
2298 SVOffset, HiVT, isVolatile, Alignment);
2300 // Increment the pointer to the other half.
2301 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2302 DAG.getIntPtrConstant(IncrementSize));
2303 // Store the lowest ExcessBits bits in the second half.
2304 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
2305 SVOffset+IncrementSize,
2306 MVT::getIntegerVT(ExcessBits),
2307 isVolatile, MinAlign(Alignment, IncrementSize));
2308 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2312 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2314 GetExpandedInteger(N->getOperand(0), InL, InH);
2315 // Just truncate the low part of the source.
2316 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2319 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2320 SDValue Op = N->getOperand(0);
2321 MVT SrcVT = Op.getValueType();
2322 MVT DstVT = N->getValueType(0);
2323 DebugLoc dl = N->getDebugLoc();
2325 if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2326 // Do a signed conversion then adjust the result.
2327 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2328 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2330 // The result of the signed conversion needs adjusting if the 'sign bit' of
2331 // the incoming integer was set. To handle this, we dynamically test to see
2332 // if it is set, and, if so, add a fudge factor.
2334 const uint64_t F32TwoE32 = 0x4F800000ULL;
2335 const uint64_t F32TwoE64 = 0x5F800000ULL;
2336 const uint64_t F32TwoE128 = 0x7F800000ULL;
2339 if (SrcVT == MVT::i32)
2340 FF = APInt(32, F32TwoE32);
2341 else if (SrcVT == MVT::i64)
2342 FF = APInt(32, F32TwoE64);
2343 else if (SrcVT == MVT::i128)
2344 FF = APInt(32, F32TwoE128);
2346 assert(false && "Unsupported UINT_TO_FP!");
2348 // Check whether the sign bit is set.
2350 GetExpandedInteger(Op, Lo, Hi);
2351 SDValue SignSet = DAG.getSetCC(dl,
2352 TLI.getSetCCResultType(Hi.getValueType()),
2353 Hi, DAG.getConstant(0, Hi.getValueType()),
2356 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2357 SDValue FudgePtr = DAG.getConstantPool(ConstantInt::get(FF.zext(64)),
2358 TLI.getPointerTy());
2360 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2361 SDValue Zero = DAG.getIntPtrConstant(0);
2362 SDValue Four = DAG.getIntPtrConstant(4);
2363 if (TLI.isBigEndian()) std::swap(Zero, Four);
2364 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2366 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2367 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2368 Alignment = std::min(Alignment, 4u);
2370 // Load the value out, extending it from f32 to the destination float type.
2371 // FIXME: Avoid the extend by constructing the right constant pool?
2372 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2373 FudgePtr, NULL, 0, MVT::f32,
2375 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2378 // Otherwise, use a libcall.
2379 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2380 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2381 "Don't know how to expand this UINT_TO_FP!");
2382 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);