1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
28 //===----------------------------------------------------------------------===//
29 // Integer Result Promotion
30 //===----------------------------------------------------------------------===//
32 /// PromoteIntegerResult - This method is called when a result of a node is
33 /// found to be in need of promotion to a larger type. At this point, the node
34 /// may also have invalid operands or may have other results that need
35 /// expansion, we just know that (at least) one result needs promotion.
36 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
37 DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG); dbgs() << "\n");
38 SDValue Res = SDValue();
40 // See if the target wants to custom expand this node.
41 if (CustomLowerNode(N, N->getValueType(ResNo), true))
44 switch (N->getOpcode()) {
47 dbgs() << "PromoteIntegerResult #" << ResNo << ": ";
48 N->dump(&DAG); dbgs() << "\n";
50 llvm_unreachable("Do not know how to promote this operator!");
51 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N); break;
52 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break;
53 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break;
54 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break;
55 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break;
56 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break;
57 case ISD::Constant: Res = PromoteIntRes_Constant(N); break;
58 case ISD::CONVERT_RNDSAT:
59 Res = PromoteIntRes_CONVERT_RNDSAT(N); break;
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break;
61 case ISD::CTPOP: Res = PromoteIntRes_CTPOP(N); break;
62 case ISD::CTTZ: Res = PromoteIntRes_CTTZ(N); break;
63 case ISD::EXTRACT_VECTOR_ELT:
64 Res = PromoteIntRes_EXTRACT_VECTOR_ELT(N); break;
65 case ISD::LOAD: Res = PromoteIntRes_LOAD(cast<LoadSDNode>(N));break;
66 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
67 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break;
68 case ISD::SELECT_CC: Res = PromoteIntRes_SELECT_CC(N); break;
69 case ISD::SETCC: Res = PromoteIntRes_SETCC(N); break;
70 case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
71 case ISD::SIGN_EXTEND_INREG:
72 Res = PromoteIntRes_SIGN_EXTEND_INREG(N); break;
73 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
74 case ISD::SRL: Res = PromoteIntRes_SRL(N); break;
75 case ISD::TRUNCATE: Res = PromoteIntRes_TRUNCATE(N); break;
76 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
77 case ISD::VAARG: Res = PromoteIntRes_VAARG(N); break;
79 case ISD::EXTRACT_SUBVECTOR:
80 Res = PromoteIntRes_EXTRACT_SUBVECTOR(N); break;
81 case ISD::VECTOR_SHUFFLE:
82 Res = PromoteIntRes_VECTOR_SHUFFLE(N); break;
83 case ISD::INSERT_VECTOR_ELT:
84 Res = PromoteIntRes_INSERT_VECTOR_ELT(N); break;
85 case ISD::BUILD_VECTOR:
86 Res = PromoteIntRes_BUILD_VECTOR(N); break;
87 case ISD::SCALAR_TO_VECTOR:
88 Res = PromoteIntRes_SCALAR_TO_VECTOR(N); break;
90 case ISD::SIGN_EXTEND:
91 case ISD::ZERO_EXTEND:
92 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break;
95 case ISD::FP_TO_UINT: Res = PromoteIntRes_FP_TO_XINT(N); break;
97 case ISD::FP32_TO_FP16:Res = PromoteIntRes_FP32_TO_FP16(N); break;
104 case ISD::MUL: Res = PromoteIntRes_SimpleIntBinOp(N); break;
107 case ISD::SREM: Res = PromoteIntRes_SDIV(N); break;
110 case ISD::UREM: Res = PromoteIntRes_UDIV(N); break;
113 case ISD::SSUBO: Res = PromoteIntRes_SADDSUBO(N, ResNo); break;
115 case ISD::USUBO: Res = PromoteIntRes_UADDSUBO(N, ResNo); break;
117 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
119 case ISD::ATOMIC_LOAD:
120 Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
122 case ISD::ATOMIC_LOAD_ADD:
123 case ISD::ATOMIC_LOAD_SUB:
124 case ISD::ATOMIC_LOAD_AND:
125 case ISD::ATOMIC_LOAD_OR:
126 case ISD::ATOMIC_LOAD_XOR:
127 case ISD::ATOMIC_LOAD_NAND:
128 case ISD::ATOMIC_LOAD_MIN:
129 case ISD::ATOMIC_LOAD_MAX:
130 case ISD::ATOMIC_LOAD_UMIN:
131 case ISD::ATOMIC_LOAD_UMAX:
132 case ISD::ATOMIC_SWAP:
133 Res = PromoteIntRes_Atomic1(cast<AtomicSDNode>(N)); break;
135 case ISD::ATOMIC_CMP_SWAP:
136 Res = PromoteIntRes_Atomic2(cast<AtomicSDNode>(N)); break;
139 // If the result is null then the sub-method took care of registering it.
141 SetPromotedInteger(SDValue(N, ResNo), Res);
144 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N) {
145 SDValue Op = DecomposeMERGE_VALUES(N);
146 return GetPromotedInteger(Op);
149 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
150 // Sign-extend the new bits, and continue the assertion.
151 SDValue Op = SExtPromotedInteger(N->getOperand(0));
152 return DAG.getNode(ISD::AssertSext, N->getDebugLoc(),
153 Op.getValueType(), Op, N->getOperand(1));
156 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
157 // Zero the new bits, and continue the assertion.
158 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
159 return DAG.getNode(ISD::AssertZext, N->getDebugLoc(),
160 Op.getValueType(), Op, N->getOperand(1));
163 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N) {
164 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
165 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
166 N->getMemoryVT(), ResVT,
167 N->getChain(), N->getBasePtr(),
168 N->getMemOperand(), N->getOrdering(),
170 // Legalized the chain result - switch anything that used the old chain to
172 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
176 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic1(AtomicSDNode *N) {
177 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
178 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
180 N->getChain(), N->getBasePtr(),
181 Op2, N->getMemOperand(), N->getOrdering(),
183 // Legalized the chain result - switch anything that used the old chain to
185 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
189 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) {
190 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
191 SDValue Op3 = GetPromotedInteger(N->getOperand(3));
192 SDValue Res = DAG.getAtomic(N->getOpcode(), N->getDebugLoc(),
193 N->getMemoryVT(), N->getChain(), N->getBasePtr(),
194 Op2, Op3, N->getMemOperand(), N->getOrdering(),
196 // Legalized the chain result - switch anything that used the old chain to
198 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
202 SDValue DAGTypeLegalizer::PromoteIntRes_BITCAST(SDNode *N) {
203 SDValue InOp = N->getOperand(0);
204 EVT InVT = InOp.getValueType();
205 EVT NInVT = TLI.getTypeToTransformTo(*DAG.getContext(), InVT);
206 EVT OutVT = N->getValueType(0);
207 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
208 DebugLoc dl = N->getDebugLoc();
210 switch (getTypeAction(InVT)) {
212 assert(false && "Unknown type action!");
214 case TargetLowering::TypeLegal:
216 case TargetLowering::TypePromoteInteger:
217 if (NOutVT.bitsEq(NInVT))
218 // The input promotes to the same size. Convert the promoted value.
219 return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp));
221 case TargetLowering::TypeSoftenFloat:
222 // Promote the integer operand by hand.
223 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));
224 case TargetLowering::TypeExpandInteger:
225 case TargetLowering::TypeExpandFloat:
227 case TargetLowering::TypeScalarizeVector:
228 // Convert the element to an integer and promote it by hand.
229 if (!NOutVT.isVector())
230 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
231 BitConvertToInteger(GetScalarizedVector(InOp)));
233 case TargetLowering::TypeSplitVector: {
234 // For example, i32 = BITCAST v2i16 on alpha. Convert the split
235 // pieces of the input into integers and reassemble in the final type.
237 GetSplitVector(N->getOperand(0), Lo, Hi);
238 Lo = BitConvertToInteger(Lo);
239 Hi = BitConvertToInteger(Hi);
241 if (TLI.isBigEndian())
244 InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
245 EVT::getIntegerVT(*DAG.getContext(),
246 NOutVT.getSizeInBits()),
247 JoinIntegers(Lo, Hi));
248 return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp);
250 case TargetLowering::TypeWidenVector:
251 if (OutVT.bitsEq(NInVT))
252 // The input is widened to the same size. Convert to the widened value.
253 return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp));
256 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
257 CreateStackStoreLoad(InOp, OutVT));
260 SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
261 SDValue Op = GetPromotedInteger(N->getOperand(0));
262 EVT OVT = N->getValueType(0);
263 EVT NVT = Op.getValueType();
264 DebugLoc dl = N->getDebugLoc();
266 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
267 return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
268 DAG.getConstant(DiffBits, TLI.getPointerTy()));
271 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
272 // The pair element type may be legal, or may not promote to the same type as
273 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
274 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(),
275 TLI.getTypeToTransformTo(*DAG.getContext(),
276 N->getValueType(0)), JoinIntegers(N->getOperand(0),
280 SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
281 EVT VT = N->getValueType(0);
282 // FIXME there is no actual debug info here
283 DebugLoc dl = N->getDebugLoc();
284 // Zero extend things like i1, sign extend everything else. It shouldn't
285 // matter in theory which one we pick, but this tends to give better code?
286 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
287 SDValue Result = DAG.getNode(Opc, dl,
288 TLI.getTypeToTransformTo(*DAG.getContext(), VT),
290 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
294 SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) {
295 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
296 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
297 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
298 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
299 "can only promote integers");
300 EVT OutVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
301 return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
302 N->getOperand(1), N->getOperand(2),
303 N->getOperand(3), N->getOperand(4), CvtCode);
306 SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
307 // Zero extend to the promoted type and do the count there.
308 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
309 DebugLoc dl = N->getDebugLoc();
310 EVT OVT = N->getValueType(0);
311 EVT NVT = Op.getValueType();
312 Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
313 // Subtract off the extra leading bits in the bigger type.
314 return DAG.getNode(ISD::SUB, dl, NVT, Op,
315 DAG.getConstant(NVT.getSizeInBits() -
316 OVT.getSizeInBits(), NVT));
319 SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
320 // Zero extend to the promoted type and do the count there.
321 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
322 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), Op.getValueType(), Op);
325 SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
326 SDValue Op = GetPromotedInteger(N->getOperand(0));
327 EVT OVT = N->getValueType(0);
328 EVT NVT = Op.getValueType();
329 DebugLoc dl = N->getDebugLoc();
330 // The count is the same in the promoted type except if the original
331 // value was zero. This can be handled by setting the bit just off
332 // the top of the original type.
333 APInt TopBit(NVT.getSizeInBits(), 0);
334 TopBit.setBit(OVT.getSizeInBits());
335 Op = DAG.getNode(ISD::OR, dl, NVT, Op, DAG.getConstant(TopBit, NVT));
336 return DAG.getNode(ISD::CTTZ, dl, NVT, Op);
339 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
340 DebugLoc dl = N->getDebugLoc();
341 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
342 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
346 SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
347 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
348 unsigned NewOpc = N->getOpcode();
349 DebugLoc dl = N->getDebugLoc();
351 // If we're promoting a UINT to a larger size and the larger FP_TO_UINT is
352 // not Legal, check to see if we can use FP_TO_SINT instead. (If both UINT
353 // and SINT conversions are Custom, there is no way to tell which is
354 // preferable. We choose SINT because that's the right thing on PPC.)
355 if (N->getOpcode() == ISD::FP_TO_UINT &&
356 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
357 TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT))
358 NewOpc = ISD::FP_TO_SINT;
360 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
362 // Assert that the converted value fits in the original type. If it doesn't
363 // (eg: because the value being converted is too big), then the result of the
364 // original operation was undefined anyway, so the assert is still correct.
365 return DAG.getNode(N->getOpcode() == ISD::FP_TO_UINT ?
366 ISD::AssertZext : ISD::AssertSext, dl, NVT, Res,
367 DAG.getValueType(N->getValueType(0).getScalarType()));
370 SDValue DAGTypeLegalizer::PromoteIntRes_FP32_TO_FP16(SDNode *N) {
371 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
372 DebugLoc dl = N->getDebugLoc();
374 SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
376 return DAG.getNode(ISD::AssertZext, dl,
377 NVT, Res, DAG.getValueType(N->getValueType(0)));
380 SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
381 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
382 DebugLoc dl = N->getDebugLoc();
384 if (getTypeAction(N->getOperand(0).getValueType())
385 == TargetLowering::TypePromoteInteger) {
386 SDValue Res = GetPromotedInteger(N->getOperand(0));
387 assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
389 // If the result and operand types are the same after promotion, simplify
390 // to an in-register extension.
391 if (NVT == Res.getValueType()) {
392 // The high bits are not guaranteed to be anything. Insert an extend.
393 if (N->getOpcode() == ISD::SIGN_EXTEND)
394 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
395 DAG.getValueType(N->getOperand(0).getValueType()));
396 if (N->getOpcode() == ISD::ZERO_EXTEND)
397 return DAG.getZeroExtendInReg(Res, dl,
398 N->getOperand(0).getValueType().getScalarType());
399 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
404 // Otherwise, just extend the original operand all the way to the larger type.
405 return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
408 SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
409 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
410 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
411 ISD::LoadExtType ExtType =
412 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
413 DebugLoc dl = N->getDebugLoc();
414 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
416 N->getMemoryVT(), N->isVolatile(),
417 N->isNonTemporal(), N->getAlignment());
419 // Legalized the chain result - switch anything that used the old chain to
421 ReplaceValueWith(SDValue(N, 1), Res.getValue(1));
425 /// Promote the overflow flag of an overflowing arithmetic node.
426 SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
427 // Simply change the return type of the boolean result.
428 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1));
429 EVT ValueVTs[] = { N->getValueType(0), NVT };
430 SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
431 SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
432 DAG.getVTList(ValueVTs, 2), Ops, 2);
434 // Modified the sum result - switch anything that used the old sum to use
436 ReplaceValueWith(SDValue(N, 0), Res);
438 return SDValue(Res.getNode(), 1);
441 SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
443 return PromoteIntRes_Overflow(N);
445 // The operation overflowed iff the result in the larger type is not the
446 // sign extension of its truncation to the original type.
447 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
448 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
449 EVT OVT = N->getOperand(0).getValueType();
450 EVT NVT = LHS.getValueType();
451 DebugLoc dl = N->getDebugLoc();
453 // Do the arithmetic in the larger type.
454 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
455 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
457 // Calculate the overflow flag: sign extend the arithmetic result from
458 // the original type.
459 SDValue Ofl = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Res,
460 DAG.getValueType(OVT));
461 // Overflowed if and only if this is not equal to Res.
462 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
464 // Use the calculated overflow everywhere.
465 ReplaceValueWith(SDValue(N, 1), Ofl);
470 SDValue DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
471 // Sign extend the input.
472 SDValue LHS = SExtPromotedInteger(N->getOperand(0));
473 SDValue RHS = SExtPromotedInteger(N->getOperand(1));
474 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
475 LHS.getValueType(), LHS, RHS);
478 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
479 SDValue LHS = GetPromotedInteger(N->getOperand(1));
480 SDValue RHS = GetPromotedInteger(N->getOperand(2));
481 return DAG.getNode(ISD::SELECT, N->getDebugLoc(),
482 LHS.getValueType(), N->getOperand(0),LHS,RHS);
485 SDValue DAGTypeLegalizer::PromoteIntRes_VSELECT(SDNode *N) {
486 SDValue Mask = GetPromotedInteger(N->getOperand(0));
487 SDValue LHS = GetPromotedInteger(N->getOperand(1));
488 SDValue RHS = GetPromotedInteger(N->getOperand(2));
489 return DAG.getNode(ISD::VSELECT, N->getDebugLoc(),
490 LHS.getValueType(), Mask, LHS, RHS);
493 SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
494 SDValue LHS = GetPromotedInteger(N->getOperand(2));
495 SDValue RHS = GetPromotedInteger(N->getOperand(3));
496 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(),
497 LHS.getValueType(), N->getOperand(0),
498 N->getOperand(1), LHS, RHS, N->getOperand(4));
501 SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
502 EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
504 DebugLoc dl = N->getDebugLoc();
505 assert(SVT.isVector() == N->getOperand(0).getValueType().isVector() &&
506 "Vector compare must return a vector result!");
508 // Get the SETCC result using the canonical SETCC type.
509 SDValue SetCC = DAG.getNode(N->getOpcode(), dl, SVT, N->getOperand(0),
510 N->getOperand(1), N->getOperand(2));
512 // Convert to the expected type.
513 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
514 assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
515 return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
518 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
519 return DAG.getNode(ISD::SHL, N->getDebugLoc(),
520 TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)),
521 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
524 SDValue DAGTypeLegalizer::PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N) {
525 SDValue Op = GetPromotedInteger(N->getOperand(0));
526 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(),
527 Op.getValueType(), Op, N->getOperand(1));
530 SDValue DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
531 // The input may have strange things in the top bits of the registers, but
532 // these operations don't care. They may have weird bits going out, but
533 // that too is okay if they are integer operations.
534 SDValue LHS = GetPromotedInteger(N->getOperand(0));
535 SDValue RHS = GetPromotedInteger(N->getOperand(1));
536 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
537 LHS.getValueType(), LHS, RHS);
540 SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
541 // The input value must be properly sign extended.
542 SDValue Res = SExtPromotedInteger(N->getOperand(0));
543 return DAG.getNode(ISD::SRA, N->getDebugLoc(),
544 Res.getValueType(), Res, N->getOperand(1));
547 SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
548 // The input value must be properly zero extended.
549 EVT VT = N->getValueType(0);
550 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
551 SDValue Res = ZExtPromotedInteger(N->getOperand(0));
552 return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
555 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
556 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
558 SDValue InOp = N->getOperand(0);
559 DebugLoc dl = N->getDebugLoc();
561 switch (getTypeAction(InOp.getValueType())) {
562 default: llvm_unreachable("Unknown type action!");
563 case TargetLowering::TypeLegal:
564 case TargetLowering::TypeExpandInteger:
567 case TargetLowering::TypePromoteInteger:
568 Res = GetPromotedInteger(InOp);
570 case TargetLowering::TypeSplitVector:
571 EVT InVT = InOp.getValueType();
572 assert(InVT.isVector() && "Cannot split scalar types");
573 unsigned NumElts = InVT.getVectorNumElements();
574 assert(NumElts == NVT.getVectorNumElements() &&
575 "Dst and Src must have the same number of elements");
576 EVT EltVT = InVT.getScalarType();
577 assert(isPowerOf2_32(NumElts) &&
578 "Promoted vector type must be a power of two");
580 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2);
581 EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
584 SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
585 DAG.getIntPtrConstant(0));
586 SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
587 DAG.getIntPtrConstant(NumElts/2));
588 EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
589 EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
591 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
594 // Truncate to NVT instead of VT
595 return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
598 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {
600 return PromoteIntRes_Overflow(N);
602 // The operation overflowed iff the result in the larger type is not the
603 // zero extension of its truncation to the original type.
604 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
605 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
606 EVT OVT = N->getOperand(0).getValueType();
607 EVT NVT = LHS.getValueType();
608 DebugLoc dl = N->getDebugLoc();
610 // Do the arithmetic in the larger type.
611 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
612 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
614 // Calculate the overflow flag: zero extend the arithmetic result from
615 // the original type.
616 SDValue Ofl = DAG.getZeroExtendInReg(Res, dl, OVT);
617 // Overflowed if and only if this is not equal to Res.
618 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE);
620 // Use the calculated overflow everywhere.
621 ReplaceValueWith(SDValue(N, 1), Ofl);
626 SDValue DAGTypeLegalizer::PromoteIntRes_XMULO(SDNode *N, unsigned ResNo) {
627 // Promote the overflow bit trivially.
629 return PromoteIntRes_Overflow(N);
631 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
632 DebugLoc DL = N->getDebugLoc();
633 EVT SmallVT = LHS.getValueType();
635 // To determine if the result overflowed in a larger type, we extend the
636 // input to the larger type, do the multiply, then check the high bits of
637 // the result to see if the overflow happened.
638 if (N->getOpcode() == ISD::SMULO) {
639 LHS = SExtPromotedInteger(LHS);
640 RHS = SExtPromotedInteger(RHS);
642 LHS = ZExtPromotedInteger(LHS);
643 RHS = ZExtPromotedInteger(RHS);
645 SDValue Mul = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
647 // Overflow occurred iff the high part of the result does not
648 // zero/sign-extend the low part.
650 if (N->getOpcode() == ISD::UMULO) {
651 // Unsigned overflow occurred iff the high part is non-zero.
652 SDValue Hi = DAG.getNode(ISD::SRL, DL, Mul.getValueType(), Mul,
653 DAG.getIntPtrConstant(SmallVT.getSizeInBits()));
654 Overflow = DAG.getSetCC(DL, N->getValueType(1), Hi,
655 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE);
657 // Signed overflow occurred iff the high part does not sign extend the low.
658 SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Mul.getValueType(),
659 Mul, DAG.getValueType(SmallVT));
660 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE);
663 // Use the calculated overflow everywhere.
664 ReplaceValueWith(SDValue(N, 1), Overflow);
668 SDValue DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
669 // Zero extend the input.
670 SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
671 SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
672 return DAG.getNode(N->getOpcode(), N->getDebugLoc(),
673 LHS.getValueType(), LHS, RHS);
676 SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
677 return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),
678 N->getValueType(0)));
681 SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
682 SDValue Chain = N->getOperand(0); // Get the chain.
683 SDValue Ptr = N->getOperand(1); // Get the pointer.
684 EVT VT = N->getValueType(0);
685 DebugLoc dl = N->getDebugLoc();
687 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), VT);
688 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), VT);
689 // The argument is passed as NumRegs registers of type RegVT.
691 SmallVector<SDValue, 8> Parts(NumRegs);
692 for (unsigned i = 0; i < NumRegs; ++i) {
693 Parts[i] = DAG.getVAArg(RegVT, dl, Chain, Ptr, N->getOperand(2),
694 N->getConstantOperandVal(3));
695 Chain = Parts[i].getValue(1);
698 // Handle endianness of the load.
699 if (TLI.isBigEndian())
700 std::reverse(Parts.begin(), Parts.end());
702 // Assemble the parts in the promoted type.
703 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
704 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
705 for (unsigned i = 1; i < NumRegs; ++i) {
706 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
707 // Shift it to the right position and "or" it in.
708 Part = DAG.getNode(ISD::SHL, dl, NVT, Part,
709 DAG.getConstant(i * RegVT.getSizeInBits(),
710 TLI.getPointerTy()));
711 Res = DAG.getNode(ISD::OR, dl, NVT, Res, Part);
714 // Modified the chain result - switch anything that used the old chain to
716 ReplaceValueWith(SDValue(N, 1), Chain);
721 //===----------------------------------------------------------------------===//
722 // Integer Operand Promotion
723 //===----------------------------------------------------------------------===//
725 /// PromoteIntegerOperand - This method is called when the specified operand of
726 /// the specified node is found to need promotion. At this point, all of the
727 /// result types of the node are known to be legal, but other operands of the
728 /// node may need promotion or expansion as well as the specified one.
729 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
730 DEBUG(dbgs() << "Promote integer operand: "; N->dump(&DAG); dbgs() << "\n");
731 SDValue Res = SDValue();
733 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
736 switch (N->getOpcode()) {
739 dbgs() << "PromoteIntegerOperand Op #" << OpNo << ": ";
740 N->dump(&DAG); dbgs() << "\n";
742 llvm_unreachable("Do not know how to promote this operator's operand!");
744 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
745 case ISD::ATOMIC_STORE:
746 Res = PromoteIntOp_ATOMIC_STORE(cast<AtomicSDNode>(N));
748 case ISD::BITCAST: Res = PromoteIntOp_BITCAST(N); break;
749 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
750 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
751 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
752 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
753 case ISD::CONCAT_VECTORS: Res = PromoteIntOp_CONCAT_VECTORS(N); break;
754 case ISD::EXTRACT_VECTOR_ELT: Res = PromoteIntOp_EXTRACT_VECTOR_ELT(N); break;
755 case ISD::CONVERT_RNDSAT:
756 Res = PromoteIntOp_CONVERT_RNDSAT(N); break;
757 case ISD::INSERT_VECTOR_ELT:
758 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);break;
759 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
760 case ISD::SCALAR_TO_VECTOR:
761 Res = PromoteIntOp_SCALAR_TO_VECTOR(N); break;
763 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
764 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
765 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
766 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
767 case ISD::SINT_TO_FP: Res = PromoteIntOp_SINT_TO_FP(N); break;
768 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
770 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
771 case ISD::FP16_TO_FP32:
772 case ISD::UINT_TO_FP: Res = PromoteIntOp_UINT_TO_FP(N); break;
773 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
779 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break;
782 // If the result is null, the sub-method took care of registering results etc.
783 if (!Res.getNode()) return false;
785 // If the result is N, the sub-method updated N in place. Tell the legalizer
787 if (Res.getNode() == N)
790 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
791 "Invalid operand expansion");
793 ReplaceValueWith(SDValue(N, 0), Res);
797 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
798 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
799 void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &NewLHS,SDValue &NewRHS,
800 ISD::CondCode CCCode) {
801 // We have to insert explicit sign or zero extends. Note that we could
802 // insert sign extends for ALL conditions, but zero extend is cheaper on
803 // many machines (an AND instead of two shifts), so prefer it.
805 default: llvm_unreachable("Unknown integer comparison!");
812 // ALL of these operations will work if we either sign or zero extend
813 // the operands (including the unsigned comparisons!). Zero extend is
814 // usually a simpler/cheaper operation, so prefer it.
815 NewLHS = ZExtPromotedInteger(NewLHS);
816 NewRHS = ZExtPromotedInteger(NewRHS);
822 NewLHS = SExtPromotedInteger(NewLHS);
823 NewRHS = SExtPromotedInteger(NewRHS);
828 SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
829 SDValue Op = GetPromotedInteger(N->getOperand(0));
830 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), N->getValueType(0), Op);
833 SDValue DAGTypeLegalizer::PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N) {
834 SDValue Op2 = GetPromotedInteger(N->getOperand(2));
835 return DAG.getAtomic(N->getOpcode(), N->getDebugLoc(), N->getMemoryVT(),
836 N->getChain(), N->getBasePtr(), Op2, N->getMemOperand(),
837 N->getOrdering(), N->getSynchScope());
840 SDValue DAGTypeLegalizer::PromoteIntOp_BITCAST(SDNode *N) {
841 // This should only occur in unusual situations like bitcasting to an
842 // x86_fp80, so just turn it into a store+load
843 return CreateStackStoreLoad(N->getOperand(0), N->getValueType(0));
846 SDValue DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
847 assert(OpNo == 2 && "Don't know how to promote this operand!");
849 SDValue LHS = N->getOperand(2);
850 SDValue RHS = N->getOperand(3);
851 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
853 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
855 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
856 N->getOperand(1), LHS, RHS, N->getOperand(4)),
860 SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
861 assert(OpNo == 1 && "only know how to promote condition");
863 // Promote all the way up to the canonical SetCC type.
864 EVT SVT = TLI.getSetCCResultType(MVT::Other);
865 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
867 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
868 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Cond,
869 N->getOperand(2)), 0);
872 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
873 // Since the result type is legal, the operands must promote to it.
874 EVT OVT = N->getOperand(0).getValueType();
875 SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
876 SDValue Hi = GetPromotedInteger(N->getOperand(1));
877 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
878 DebugLoc dl = N->getDebugLoc();
880 Hi = DAG.getNode(ISD::SHL, dl, N->getValueType(0), Hi,
881 DAG.getConstant(OVT.getSizeInBits(), TLI.getPointerTy()));
882 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi);
885 SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
886 // The vector type is legal but the element type is not. This implies
887 // that the vector is a power-of-two in length and that the element
888 // type does not have a strange size (eg: it is not i1).
889 EVT VecVT = N->getValueType(0);
890 unsigned NumElts = VecVT.getVectorNumElements();
891 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
893 // Promote the inserted value. The type does not need to match the
894 // vector element type. Check that any extra bits introduced will be
896 assert(N->getOperand(0).getValueType().getSizeInBits() >=
897 N->getValueType(0).getVectorElementType().getSizeInBits() &&
898 "Type of inserted value narrower than vector element type!");
900 SmallVector<SDValue, 16> NewOps;
901 for (unsigned i = 0; i < NumElts; ++i)
902 NewOps.push_back(GetPromotedInteger(N->getOperand(i)));
904 return SDValue(DAG.UpdateNodeOperands(N, &NewOps[0], NumElts), 0);
907 SDValue DAGTypeLegalizer::PromoteIntOp_CONVERT_RNDSAT(SDNode *N) {
908 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(N)->getCvtCode();
909 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
910 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
911 CvtCode == ISD::CVT_FS || CvtCode == ISD::CVT_FU) &&
912 "can only promote integer arguments");
913 SDValue InOp = GetPromotedInteger(N->getOperand(0));
914 return DAG.getConvertRndSat(N->getValueType(0), N->getDebugLoc(), InOp,
915 N->getOperand(1), N->getOperand(2),
916 N->getOperand(3), N->getOperand(4), CvtCode);
919 SDValue DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
922 // Promote the inserted value. This is valid because the type does not
923 // have to match the vector element type.
925 // Check that any extra bits introduced will be truncated away.
926 assert(N->getOperand(1).getValueType().getSizeInBits() >=
927 N->getValueType(0).getVectorElementType().getSizeInBits() &&
928 "Type of inserted value narrower than vector element type!");
929 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
930 GetPromotedInteger(N->getOperand(1)),
935 assert(OpNo == 2 && "Different operand and result vector types?");
937 // Promote the index.
938 SDValue Idx = ZExtPromotedInteger(N->getOperand(2));
939 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
940 N->getOperand(1), Idx), 0);
943 SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
945 DebugLoc dl = N->getDebugLoc();
946 NewOps[0] = N->getOperand(0);
947 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
948 SDValue Flag = GetPromotedInteger(N->getOperand(i));
949 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
951 return SDValue(DAG.UpdateNodeOperands(N, NewOps, array_lengthof(NewOps)), 0);
954 SDValue DAGTypeLegalizer::PromoteIntOp_SCALAR_TO_VECTOR(SDNode *N) {
955 // Integer SCALAR_TO_VECTOR operands are implicitly truncated, so just promote
956 // the operand in place.
957 return SDValue(DAG.UpdateNodeOperands(N,
958 GetPromotedInteger(N->getOperand(0))), 0);
961 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
962 assert(OpNo == 0 && "Only know how to promote the condition!");
963 SDValue Cond = N->getOperand(0);
964 EVT OpTy = N->getOperand(1).getValueType();
966 // Promote all the way up to the canonical SetCC type.
967 EVT SVT = TLI.getSetCCResultType(N->getOpcode() == ISD::SELECT ?
968 OpTy.getScalarType() : OpTy);
969 Cond = PromoteTargetBoolean(Cond, SVT);
971 return SDValue(DAG.UpdateNodeOperands(N, Cond, N->getOperand(1),
972 N->getOperand(2)), 0);
975 SDValue DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
976 assert(OpNo == 0 && "Don't know how to promote this operand!");
978 SDValue LHS = N->getOperand(0);
979 SDValue RHS = N->getOperand(1);
980 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
982 // The CC (#4) and the possible return values (#2 and #3) have legal types.
983 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2),
984 N->getOperand(3), N->getOperand(4)), 0);
987 SDValue DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
988 assert(OpNo == 0 && "Don't know how to promote this operand!");
990 SDValue LHS = N->getOperand(0);
991 SDValue RHS = N->getOperand(1);
992 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
994 // The CC (#2) is always legal.
995 return SDValue(DAG.UpdateNodeOperands(N, LHS, RHS, N->getOperand(2)), 0);
998 SDValue DAGTypeLegalizer::PromoteIntOp_Shift(SDNode *N) {
999 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
1000 ZExtPromotedInteger(N->getOperand(1))), 0);
1003 SDValue DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
1004 SDValue Op = GetPromotedInteger(N->getOperand(0));
1005 DebugLoc dl = N->getDebugLoc();
1006 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1007 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(),
1008 Op, DAG.getValueType(N->getOperand(0).getValueType()));
1011 SDValue DAGTypeLegalizer::PromoteIntOp_SINT_TO_FP(SDNode *N) {
1012 return SDValue(DAG.UpdateNodeOperands(N,
1013 SExtPromotedInteger(N->getOperand(0))), 0);
1016 SDValue DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
1017 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1018 SDValue Ch = N->getChain(), Ptr = N->getBasePtr();
1019 unsigned Alignment = N->getAlignment();
1020 bool isVolatile = N->isVolatile();
1021 bool isNonTemporal = N->isNonTemporal();
1022 DebugLoc dl = N->getDebugLoc();
1024 SDValue Val = GetPromotedInteger(N->getValue()); // Get promoted value.
1026 // Truncate the value and store the result.
1027 return DAG.getTruncStore(Ch, dl, Val, Ptr, N->getPointerInfo(),
1029 isVolatile, isNonTemporal, Alignment);
1032 SDValue DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
1033 SDValue Op = GetPromotedInteger(N->getOperand(0));
1034 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), Op);
1037 SDValue DAGTypeLegalizer::PromoteIntOp_UINT_TO_FP(SDNode *N) {
1038 return SDValue(DAG.UpdateNodeOperands(N,
1039 ZExtPromotedInteger(N->getOperand(0))), 0);
1042 SDValue DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
1043 DebugLoc dl = N->getDebugLoc();
1044 SDValue Op = GetPromotedInteger(N->getOperand(0));
1045 Op = DAG.getNode(ISD::ANY_EXTEND, dl, N->getValueType(0), Op);
1046 return DAG.getZeroExtendInReg(Op, dl,
1047 N->getOperand(0).getValueType().getScalarType());
1051 //===----------------------------------------------------------------------===//
1052 // Integer Result Expansion
1053 //===----------------------------------------------------------------------===//
1055 /// ExpandIntegerResult - This method is called when the specified result of the
1056 /// specified node is found to need expansion. At this point, the node may also
1057 /// have invalid operands or may have other results that need promotion, we just
1058 /// know that (at least) one result needs expansion.
1059 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
1060 DEBUG(dbgs() << "Expand integer result: "; N->dump(&DAG); dbgs() << "\n");
1062 Lo = Hi = SDValue();
1064 // See if the target wants to custom expand this node.
1065 if (CustomLowerNode(N, N->getValueType(ResNo), true))
1068 switch (N->getOpcode()) {
1071 dbgs() << "ExpandIntegerResult #" << ResNo << ": ";
1072 N->dump(&DAG); dbgs() << "\n";
1074 llvm_unreachable("Do not know how to expand the result of this operator!");
1076 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
1077 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
1078 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
1079 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
1081 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break;
1082 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
1083 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
1084 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
1085 case ISD::VAARG: ExpandRes_VAARG(N, Lo, Hi); break;
1087 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
1088 case ISD::AssertSext: ExpandIntRes_AssertSext(N, Lo, Hi); break;
1089 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
1090 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
1091 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
1092 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
1093 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
1094 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
1095 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
1096 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
1097 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
1098 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
1099 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
1100 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
1101 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
1102 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
1103 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
1104 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
1105 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
1106 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
1107 case ISD::ATOMIC_LOAD: ExpandIntRes_ATOMIC_LOAD(N, Lo, Hi); break;
1109 case ISD::ATOMIC_LOAD_ADD:
1110 case ISD::ATOMIC_LOAD_SUB:
1111 case ISD::ATOMIC_LOAD_AND:
1112 case ISD::ATOMIC_LOAD_OR:
1113 case ISD::ATOMIC_LOAD_XOR:
1114 case ISD::ATOMIC_LOAD_NAND:
1115 case ISD::ATOMIC_LOAD_MIN:
1116 case ISD::ATOMIC_LOAD_MAX:
1117 case ISD::ATOMIC_LOAD_UMIN:
1118 case ISD::ATOMIC_LOAD_UMAX:
1119 case ISD::ATOMIC_SWAP: {
1120 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(N);
1121 SplitInteger(Tmp.first, Lo, Hi);
1122 ReplaceValueWith(SDValue(N, 1), Tmp.second);
1128 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
1131 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
1134 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
1137 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1141 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
1144 case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
1146 case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
1148 case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
1151 // If Lo/Hi is null, the sub-method took care of registering results etc.
1153 SetExpandedInteger(SDValue(N, ResNo), Lo, Hi);
1156 /// Lower an atomic node to the appropriate builtin call.
1157 std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
1158 unsigned Opc = Node->getOpcode();
1159 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
1164 llvm_unreachable("Unhandled atomic intrinsic Expand!");
1166 case ISD::ATOMIC_SWAP:
1167 switch (VT.SimpleTy) {
1168 default: llvm_unreachable("Unexpected value type for atomic!");
1169 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
1170 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
1171 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
1172 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
1175 case ISD::ATOMIC_CMP_SWAP:
1176 switch (VT.SimpleTy) {
1177 default: llvm_unreachable("Unexpected value type for atomic!");
1178 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
1179 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
1180 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
1181 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
1184 case ISD::ATOMIC_LOAD_ADD:
1185 switch (VT.SimpleTy) {
1186 default: llvm_unreachable("Unexpected value type for atomic!");
1187 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
1188 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
1189 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
1190 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
1193 case ISD::ATOMIC_LOAD_SUB:
1194 switch (VT.SimpleTy) {
1195 default: llvm_unreachable("Unexpected value type for atomic!");
1196 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
1197 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
1198 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
1199 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
1202 case ISD::ATOMIC_LOAD_AND:
1203 switch (VT.SimpleTy) {
1204 default: llvm_unreachable("Unexpected value type for atomic!");
1205 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
1206 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
1207 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
1208 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
1211 case ISD::ATOMIC_LOAD_OR:
1212 switch (VT.SimpleTy) {
1213 default: llvm_unreachable("Unexpected value type for atomic!");
1214 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
1215 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
1216 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
1217 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
1220 case ISD::ATOMIC_LOAD_XOR:
1221 switch (VT.SimpleTy) {
1222 default: llvm_unreachable("Unexpected value type for atomic!");
1223 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
1224 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
1225 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
1226 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
1229 case ISD::ATOMIC_LOAD_NAND:
1230 switch (VT.SimpleTy) {
1231 default: llvm_unreachable("Unexpected value type for atomic!");
1232 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
1233 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
1234 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
1235 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
1240 return ExpandChainLibCall(LC, Node, false);
1243 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1244 /// and the shift amount is a constant 'Amt'. Expand the operation.
1245 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1246 SDValue &Lo, SDValue &Hi) {
1247 DebugLoc DL = N->getDebugLoc();
1248 // Expand the incoming operand to be shifted, so that we have its parts
1250 GetExpandedInteger(N->getOperand(0), InL, InH);
1252 EVT NVT = InL.getValueType();
1253 unsigned VTBits = N->getValueType(0).getSizeInBits();
1254 unsigned NVTBits = NVT.getSizeInBits();
1255 EVT ShTy = N->getOperand(1).getValueType();
1257 if (N->getOpcode() == ISD::SHL) {
1259 Lo = Hi = DAG.getConstant(0, NVT);
1260 } else if (Amt > NVTBits) {
1261 Lo = DAG.getConstant(0, NVT);
1262 Hi = DAG.getNode(ISD::SHL, DL,
1263 NVT, InL, DAG.getConstant(Amt-NVTBits, ShTy));
1264 } else if (Amt == NVTBits) {
1265 Lo = DAG.getConstant(0, NVT);
1267 } else if (Amt == 1 &&
1268 TLI.isOperationLegalOrCustom(ISD::ADDC,
1269 TLI.getTypeToExpandTo(*DAG.getContext(), NVT))) {
1270 // Emit this X << 1 as X+X.
1271 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1272 SDValue LoOps[2] = { InL, InL };
1273 Lo = DAG.getNode(ISD::ADDC, DL, VTList, LoOps, 2);
1274 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
1275 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3);
1277 Lo = DAG.getNode(ISD::SHL, DL, NVT, InL, DAG.getConstant(Amt, ShTy));
1278 Hi = DAG.getNode(ISD::OR, DL, NVT,
1279 DAG.getNode(ISD::SHL, DL, NVT, InH,
1280 DAG.getConstant(Amt, ShTy)),
1281 DAG.getNode(ISD::SRL, DL, NVT, InL,
1282 DAG.getConstant(NVTBits-Amt, ShTy)));
1287 if (N->getOpcode() == ISD::SRL) {
1289 Lo = DAG.getConstant(0, NVT);
1290 Hi = DAG.getConstant(0, NVT);
1291 } else if (Amt > NVTBits) {
1292 Lo = DAG.getNode(ISD::SRL, DL,
1293 NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1294 Hi = DAG.getConstant(0, NVT);
1295 } else if (Amt == NVTBits) {
1297 Hi = DAG.getConstant(0, NVT);
1299 Lo = DAG.getNode(ISD::OR, DL, NVT,
1300 DAG.getNode(ISD::SRL, DL, NVT, InL,
1301 DAG.getConstant(Amt, ShTy)),
1302 DAG.getNode(ISD::SHL, DL, NVT, InH,
1303 DAG.getConstant(NVTBits-Amt, ShTy)));
1304 Hi = DAG.getNode(ISD::SRL, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1309 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1311 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1312 DAG.getConstant(NVTBits-1, ShTy));
1313 } else if (Amt > NVTBits) {
1314 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1315 DAG.getConstant(Amt-NVTBits, ShTy));
1316 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1317 DAG.getConstant(NVTBits-1, ShTy));
1318 } else if (Amt == NVTBits) {
1320 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1321 DAG.getConstant(NVTBits-1, ShTy));
1323 Lo = DAG.getNode(ISD::OR, DL, NVT,
1324 DAG.getNode(ISD::SRL, DL, NVT, InL,
1325 DAG.getConstant(Amt, ShTy)),
1326 DAG.getNode(ISD::SHL, DL, NVT, InH,
1327 DAG.getConstant(NVTBits-Amt, ShTy)));
1328 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, ShTy));
1332 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1333 /// this shift based on knowledge of the high bit of the shift amount. If we
1334 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1336 bool DAGTypeLegalizer::
1337 ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1338 SDValue Amt = N->getOperand(1);
1339 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1340 EVT ShTy = Amt.getValueType();
1341 unsigned ShBits = ShTy.getScalarType().getSizeInBits();
1342 unsigned NVTBits = NVT.getScalarType().getSizeInBits();
1343 assert(isPowerOf2_32(NVTBits) &&
1344 "Expanded integer type size not a power of two!");
1345 DebugLoc dl = N->getDebugLoc();
1347 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1348 APInt KnownZero, KnownOne;
1349 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1351 // If we don't know anything about the high bits, exit.
1352 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1355 // Get the incoming operand to be shifted.
1357 GetExpandedInteger(N->getOperand(0), InL, InH);
1359 // If we know that any of the high bits of the shift amount are one, then we
1360 // can do this as a couple of simple shifts.
1361 if (KnownOne.intersects(HighBitMask)) {
1362 // Mask out the high bit, which we know is set.
1363 Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt,
1364 DAG.getConstant(~HighBitMask, ShTy));
1366 switch (N->getOpcode()) {
1367 default: llvm_unreachable("Unknown shift");
1369 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1370 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
1373 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1374 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
1377 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1378 DAG.getConstant(NVTBits-1, ShTy));
1379 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1385 // FIXME: This code is broken for shifts with a zero amount!
1386 // If we know that all of the high bits of the shift amount are zero, then we
1387 // can do this as a couple of simple shifts.
1388 if ((KnownZero & HighBitMask) == HighBitMask) {
1390 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy,
1391 DAG.getConstant(NVTBits, ShTy),
1394 switch (N->getOpcode()) {
1395 default: llvm_unreachable("Unknown shift");
1396 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1398 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1401 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1402 Hi = DAG.getNode(ISD::OR, NVT,
1403 DAG.getNode(Op1, NVT, InH, Amt),
1404 DAG.getNode(Op2, NVT, InL, Amt2));
1412 /// ExpandShiftWithUnknownAmountBit - Fully general expansion of integer shift
1414 bool DAGTypeLegalizer::
1415 ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
1416 SDValue Amt = N->getOperand(1);
1417 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1418 EVT ShTy = Amt.getValueType();
1419 unsigned NVTBits = NVT.getSizeInBits();
1420 assert(isPowerOf2_32(NVTBits) &&
1421 "Expanded integer type size not a power of two!");
1422 DebugLoc dl = N->getDebugLoc();
1424 // Get the incoming operand to be shifted.
1426 GetExpandedInteger(N->getOperand(0), InL, InH);
1428 SDValue NVBitsNode = DAG.getConstant(NVTBits, ShTy);
1429 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode);
1430 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt);
1431 SDValue isShort = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy),
1432 Amt, NVBitsNode, ISD::SETULT);
1434 SDValue LoS, HiS, LoL, HiL;
1435 switch (N->getOpcode()) {
1436 default: llvm_unreachable("Unknown shift");
1438 // Short: ShAmt < NVTBits
1439 LoS = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
1440 HiS = DAG.getNode(ISD::OR, dl, NVT,
1441 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
1442 // FIXME: If Amt is zero, the following shift generates an undefined result
1443 // on some architectures.
1444 DAG.getNode(ISD::SRL, dl, NVT, InL, AmtLack));
1446 // Long: ShAmt >= NVTBits
1447 LoL = DAG.getConstant(0, NVT); // Lo part is zero.
1448 HiL = DAG.getNode(ISD::SHL, dl, NVT, InL, AmtExcess); // Hi from Lo part.
1450 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1451 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1454 // Short: ShAmt < NVTBits
1455 HiS = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
1456 LoS = DAG.getNode(ISD::OR, dl, NVT,
1457 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1458 // FIXME: If Amt is zero, the following shift generates an undefined result
1459 // on some architectures.
1460 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1462 // Long: ShAmt >= NVTBits
1463 HiL = DAG.getConstant(0, NVT); // Hi part is zero.
1464 LoL = DAG.getNode(ISD::SRL, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1466 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1467 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1470 // Short: ShAmt < NVTBits
1471 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1472 LoS = DAG.getNode(ISD::OR, dl, NVT,
1473 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
1474 // FIXME: If Amt is zero, the following shift generates an undefined result
1475 // on some architectures.
1476 DAG.getNode(ISD::SHL, dl, NVT, InH, AmtLack));
1478 // Long: ShAmt >= NVTBits
1479 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1480 DAG.getConstant(NVTBits-1, ShTy));
1481 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1483 Lo = DAG.getNode(ISD::SELECT, dl, NVT, isShort, LoS, LoL);
1484 Hi = DAG.getNode(ISD::SELECT, dl, NVT, isShort, HiS, HiL);
1491 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1492 SDValue &Lo, SDValue &Hi) {
1493 DebugLoc dl = N->getDebugLoc();
1494 // Expand the subcomponents.
1495 SDValue LHSL, LHSH, RHSL, RHSH;
1496 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1497 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1499 EVT NVT = LHSL.getValueType();
1500 SDValue LoOps[2] = { LHSL, RHSL };
1501 SDValue HiOps[3] = { LHSH, RHSH };
1503 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1504 // them. TODO: Teach operation legalization how to expand unsupported
1505 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1506 // a carry of type MVT::Glue, but there doesn't seem to be any way to
1507 // generate a value of this type in the expanded code sequence.
1509 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
1510 ISD::ADDC : ISD::SUBC,
1511 TLI.getTypeToExpandTo(*DAG.getContext(), NVT));
1514 SDVTList VTList = DAG.getVTList(NVT, MVT::Glue);
1515 if (N->getOpcode() == ISD::ADD) {
1516 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1517 HiOps[2] = Lo.getValue(1);
1518 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1520 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1521 HiOps[2] = Lo.getValue(1);
1522 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1527 if (N->getOpcode() == ISD::ADD) {
1528 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
1529 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
1530 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[0],
1532 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
1533 DAG.getConstant(1, NVT),
1534 DAG.getConstant(0, NVT));
1535 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, LoOps[1],
1537 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
1538 DAG.getConstant(1, NVT), Carry1);
1539 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
1541 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
1542 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
1544 DAG.getSetCC(dl, TLI.getSetCCResultType(LoOps[0].getValueType()),
1545 LoOps[0], LoOps[1], ISD::SETULT);
1546 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
1547 DAG.getConstant(1, NVT),
1548 DAG.getConstant(0, NVT));
1549 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
1553 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1554 SDValue &Lo, SDValue &Hi) {
1555 // Expand the subcomponents.
1556 SDValue LHSL, LHSH, RHSL, RHSH;
1557 DebugLoc dl = N->getDebugLoc();
1558 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1559 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1560 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1561 SDValue LoOps[2] = { LHSL, RHSL };
1562 SDValue HiOps[3] = { LHSH, RHSH };
1564 if (N->getOpcode() == ISD::ADDC) {
1565 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
1566 HiOps[2] = Lo.getValue(1);
1567 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
1569 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
1570 HiOps[2] = Lo.getValue(1);
1571 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
1574 // Legalized the flag result - switch anything that used the old flag to
1576 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1579 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1580 SDValue &Lo, SDValue &Hi) {
1581 // Expand the subcomponents.
1582 SDValue LHSL, LHSH, RHSL, RHSH;
1583 DebugLoc dl = N->getDebugLoc();
1584 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1585 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1586 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Glue);
1587 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1588 SDValue HiOps[3] = { LHSH, RHSH };
1590 Lo = DAG.getNode(N->getOpcode(), dl, VTList, LoOps, 3);
1591 HiOps[2] = Lo.getValue(1);
1592 Hi = DAG.getNode(N->getOpcode(), dl, VTList, HiOps, 3);
1594 // Legalized the flag result - switch anything that used the old flag to
1596 ReplaceValueWith(SDValue(N, 1), Hi.getValue(1));
1599 void DAGTypeLegalizer::ExpandIntRes_MERGE_VALUES(SDNode *N,
1600 SDValue &Lo, SDValue &Hi) {
1601 SDValue Res = DecomposeMERGE_VALUES(N);
1602 SplitInteger(Res, Lo, Hi);
1605 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
1606 SDValue &Lo, SDValue &Hi) {
1607 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1608 DebugLoc dl = N->getDebugLoc();
1609 SDValue Op = N->getOperand(0);
1610 if (Op.getValueType().bitsLE(NVT)) {
1611 // The low part is any extension of the input (which degenerates to a copy).
1612 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Op);
1613 Hi = DAG.getUNDEF(NVT); // The high part is undefined.
1615 // For example, extension of an i48 to an i64. The operand type necessarily
1616 // promotes to the result type, so will end up being expanded too.
1617 assert(getTypeAction(Op.getValueType()) ==
1618 TargetLowering::TypePromoteInteger &&
1619 "Only know how to promote this result!");
1620 SDValue Res = GetPromotedInteger(Op);
1621 assert(Res.getValueType() == N->getValueType(0) &&
1622 "Operand over promoted?");
1623 // Split the promoted operand. This will simplify when it is expanded.
1624 SplitInteger(Res, Lo, Hi);
1628 void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N,
1629 SDValue &Lo, SDValue &Hi) {
1630 DebugLoc dl = N->getDebugLoc();
1631 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1632 EVT NVT = Lo.getValueType();
1633 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1634 unsigned NVTBits = NVT.getSizeInBits();
1635 unsigned EVTBits = EVT.getSizeInBits();
1637 if (NVTBits < EVTBits) {
1638 Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
1639 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1640 EVTBits - NVTBits)));
1642 Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
1643 // The high part replicates the sign bit of Lo, make it explicit.
1644 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1645 DAG.getConstant(NVTBits-1, TLI.getPointerTy()));
1649 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
1650 SDValue &Lo, SDValue &Hi) {
1651 DebugLoc dl = N->getDebugLoc();
1652 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1653 EVT NVT = Lo.getValueType();
1654 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1655 unsigned NVTBits = NVT.getSizeInBits();
1656 unsigned EVTBits = EVT.getSizeInBits();
1658 if (NVTBits < EVTBits) {
1659 Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
1660 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
1661 EVTBits - NVTBits)));
1663 Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
1664 // The high part must be zero, make it explicit.
1665 Hi = DAG.getConstant(0, NVT);
1669 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1670 SDValue &Lo, SDValue &Hi) {
1671 DebugLoc dl = N->getDebugLoc();
1672 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1673 Lo = DAG.getNode(ISD::BSWAP, dl, Lo.getValueType(), Lo);
1674 Hi = DAG.getNode(ISD::BSWAP, dl, Hi.getValueType(), Hi);
1677 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
1678 SDValue &Lo, SDValue &Hi) {
1679 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
1680 unsigned NBitWidth = NVT.getSizeInBits();
1681 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
1682 Lo = DAG.getConstant(Cst.trunc(NBitWidth), NVT);
1683 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
1686 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1687 SDValue &Lo, SDValue &Hi) {
1688 DebugLoc dl = N->getDebugLoc();
1689 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1690 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1691 EVT NVT = Lo.getValueType();
1693 SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
1694 DAG.getConstant(0, NVT), ISD::SETNE);
1696 SDValue LoLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
1697 SDValue HiLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
1699 Lo = DAG.getNode(ISD::SELECT, dl, NVT, HiNotZero, HiLZ,
1700 DAG.getNode(ISD::ADD, dl, NVT, LoLZ,
1701 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1702 Hi = DAG.getConstant(0, NVT);
1705 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1706 SDValue &Lo, SDValue &Hi) {
1707 DebugLoc dl = N->getDebugLoc();
1708 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1709 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1710 EVT NVT = Lo.getValueType();
1711 Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
1712 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
1713 Hi = DAG.getConstant(0, NVT);
1716 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1717 SDValue &Lo, SDValue &Hi) {
1718 DebugLoc dl = N->getDebugLoc();
1719 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1720 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1721 EVT NVT = Lo.getValueType();
1723 SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
1724 DAG.getConstant(0, NVT), ISD::SETNE);
1726 SDValue LoLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
1727 SDValue HiLZ = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
1729 Lo = DAG.getNode(ISD::SELECT, dl, NVT, LoNotZero, LoLZ,
1730 DAG.getNode(ISD::ADD, dl, NVT, HiLZ,
1731 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1732 Hi = DAG.getConstant(0, NVT);
1735 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
1737 DebugLoc dl = N->getDebugLoc();
1738 EVT VT = N->getValueType(0);
1739 SDValue Op = N->getOperand(0);
1740 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
1741 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
1742 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*irrelevant*/, dl), Lo, Hi);
1745 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
1747 DebugLoc dl = N->getDebugLoc();
1748 EVT VT = N->getValueType(0);
1749 SDValue Op = N->getOperand(0);
1750 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
1751 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
1752 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*irrelevant*/, dl), Lo, Hi);
1755 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1756 SDValue &Lo, SDValue &Hi) {
1757 if (ISD::isNormalLoad(N)) {
1758 ExpandRes_NormalLoad(N, Lo, Hi);
1762 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1764 EVT VT = N->getValueType(0);
1765 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1766 SDValue Ch = N->getChain();
1767 SDValue Ptr = N->getBasePtr();
1768 ISD::LoadExtType ExtType = N->getExtensionType();
1769 unsigned Alignment = N->getAlignment();
1770 bool isVolatile = N->isVolatile();
1771 bool isNonTemporal = N->isNonTemporal();
1772 DebugLoc dl = N->getDebugLoc();
1774 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1776 if (N->getMemoryVT().bitsLE(NVT)) {
1777 EVT MemVT = N->getMemoryVT();
1779 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1780 MemVT, isVolatile, isNonTemporal, Alignment);
1782 // Remember the chain.
1783 Ch = Lo.getValue(1);
1785 if (ExtType == ISD::SEXTLOAD) {
1786 // The high part is obtained by SRA'ing all but one of the bits of the
1788 unsigned LoSize = Lo.getValueType().getSizeInBits();
1789 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
1790 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
1791 } else if (ExtType == ISD::ZEXTLOAD) {
1792 // The high part is just a zero.
1793 Hi = DAG.getConstant(0, NVT);
1795 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1796 // The high part is undefined.
1797 Hi = DAG.getUNDEF(NVT);
1799 } else if (TLI.isLittleEndian()) {
1800 // Little-endian - low bits are at low addresses.
1801 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, N->getPointerInfo(),
1802 isVolatile, isNonTemporal, Alignment);
1804 unsigned ExcessBits =
1805 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1806 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
1808 // Increment the pointer to the other half.
1809 unsigned IncrementSize = NVT.getSizeInBits()/8;
1810 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1811 DAG.getIntPtrConstant(IncrementSize));
1812 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1813 N->getPointerInfo().getWithOffset(IncrementSize), NEVT,
1814 isVolatile, isNonTemporal,
1815 MinAlign(Alignment, IncrementSize));
1817 // Build a factor node to remember that this load is independent of the
1819 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1822 // Big-endian - high bits are at low addresses. Favor aligned loads at
1823 // the cost of some bit-fiddling.
1824 EVT MemVT = N->getMemoryVT();
1825 unsigned EBytes = MemVT.getStoreSize();
1826 unsigned IncrementSize = NVT.getSizeInBits()/8;
1827 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1829 // Load both the high bits and maybe some of the low bits.
1830 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1831 EVT::getIntegerVT(*DAG.getContext(),
1832 MemVT.getSizeInBits() - ExcessBits),
1833 isVolatile, isNonTemporal, Alignment);
1835 // Increment the pointer to the other half.
1836 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1837 DAG.getIntPtrConstant(IncrementSize));
1838 // Load the rest of the low bits.
1839 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
1840 N->getPointerInfo().getWithOffset(IncrementSize),
1841 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
1842 isVolatile, isNonTemporal,
1843 MinAlign(Alignment, IncrementSize));
1845 // Build a factor node to remember that this load is independent of the
1847 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1850 if (ExcessBits < NVT.getSizeInBits()) {
1851 // Transfer low bits from the bottom of Hi to the top of Lo.
1852 Lo = DAG.getNode(ISD::OR, dl, NVT, Lo,
1853 DAG.getNode(ISD::SHL, dl, NVT, Hi,
1854 DAG.getConstant(ExcessBits,
1855 TLI.getPointerTy())));
1856 // Move high bits to the right position in Hi.
1857 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl,
1859 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1860 TLI.getPointerTy()));
1864 // Legalized the chain result - switch anything that used the old chain to
1866 ReplaceValueWith(SDValue(N, 1), Ch);
1869 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1870 SDValue &Lo, SDValue &Hi) {
1871 DebugLoc dl = N->getDebugLoc();
1872 SDValue LL, LH, RL, RH;
1873 GetExpandedInteger(N->getOperand(0), LL, LH);
1874 GetExpandedInteger(N->getOperand(1), RL, RH);
1875 Lo = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LL, RL);
1876 Hi = DAG.getNode(N->getOpcode(), dl, LL.getValueType(), LH, RH);
1879 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1880 SDValue &Lo, SDValue &Hi) {
1881 EVT VT = N->getValueType(0);
1882 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
1883 DebugLoc dl = N->getDebugLoc();
1885 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
1886 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
1887 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
1888 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
1889 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1890 SDValue LL, LH, RL, RH;
1891 GetExpandedInteger(N->getOperand(0), LL, LH);
1892 GetExpandedInteger(N->getOperand(1), RL, RH);
1893 unsigned OuterBitSize = VT.getSizeInBits();
1894 unsigned InnerBitSize = NVT.getSizeInBits();
1895 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1896 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1898 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1899 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1900 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1901 // The inputs are both zero-extended.
1903 // We can emit a umul_lohi.
1904 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1905 Hi = SDValue(Lo.getNode(), 1);
1909 // We can emit a mulhu+mul.
1910 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1911 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1915 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1916 // The input values are both sign-extended.
1918 // We can emit a smul_lohi.
1919 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
1920 Hi = SDValue(Lo.getNode(), 1);
1924 // We can emit a mulhs+mul.
1925 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1926 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
1931 // Lo,Hi = umul LHS, RHS.
1932 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
1933 DAG.getVTList(NVT, NVT), LL, RL);
1935 Hi = UMulLOHI.getValue(1);
1936 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1937 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1938 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1939 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1943 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
1944 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
1945 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
1946 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
1947 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
1948 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
1953 // If nothing else, we can make a libcall.
1954 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1956 LC = RTLIB::MUL_I16;
1957 else if (VT == MVT::i32)
1958 LC = RTLIB::MUL_I32;
1959 else if (VT == MVT::i64)
1960 LC = RTLIB::MUL_I64;
1961 else if (VT == MVT::i128)
1962 LC = RTLIB::MUL_I128;
1963 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
1965 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
1966 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*irrelevant*/, dl), Lo, Hi);
1969 void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
1970 SDValue &Lo, SDValue &Hi) {
1971 SDValue LHS = Node->getOperand(0);
1972 SDValue RHS = Node->getOperand(1);
1973 DebugLoc dl = Node->getDebugLoc();
1975 // Expand the result by simply replacing it with the equivalent
1976 // non-overflow-checking operation.
1977 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
1978 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
1980 SplitInteger(Sum, Lo, Hi);
1982 // Compute the overflow.
1984 // LHSSign -> LHS >= 0
1985 // RHSSign -> RHS >= 0
1986 // SumSign -> Sum >= 0
1989 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
1991 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
1993 EVT OType = Node->getValueType(1);
1994 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
1996 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
1997 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
1998 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
1999 Node->getOpcode() == ISD::SADDO ?
2000 ISD::SETEQ : ISD::SETNE);
2002 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2003 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2005 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2007 // Use the calculated overflow everywhere.
2008 ReplaceValueWith(SDValue(Node, 1), Cmp);
2011 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
2012 SDValue &Lo, SDValue &Hi) {
2013 EVT VT = N->getValueType(0);
2014 DebugLoc dl = N->getDebugLoc();
2016 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2018 LC = RTLIB::SDIV_I16;
2019 else if (VT == MVT::i32)
2020 LC = RTLIB::SDIV_I32;
2021 else if (VT == MVT::i64)
2022 LC = RTLIB::SDIV_I64;
2023 else if (VT == MVT::i128)
2024 LC = RTLIB::SDIV_I128;
2025 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
2027 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2028 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2031 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
2032 SDValue &Lo, SDValue &Hi) {
2033 EVT VT = N->getValueType(0);
2034 DebugLoc dl = N->getDebugLoc();
2036 // If we can emit an efficient shift operation, do so now. Check to see if
2037 // the RHS is a constant.
2038 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2039 return ExpandShiftByConstant(N, CN->getZExtValue(), Lo, Hi);
2041 // If we can determine that the high bit of the shift is zero or one, even if
2042 // the low bits are variable, emit this shift in an optimized form.
2043 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
2046 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
2048 if (N->getOpcode() == ISD::SHL) {
2049 PartsOpc = ISD::SHL_PARTS;
2050 } else if (N->getOpcode() == ISD::SRL) {
2051 PartsOpc = ISD::SRL_PARTS;
2053 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2054 PartsOpc = ISD::SRA_PARTS;
2057 // Next check to see if the target supports this SHL_PARTS operation or if it
2058 // will custom expand it.
2059 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2060 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
2061 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
2062 Action == TargetLowering::Custom) {
2063 // Expand the subcomponents.
2065 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
2067 SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
2068 EVT VT = LHSL.getValueType();
2069 Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
2070 Hi = Lo.getValue(1);
2074 // Otherwise, emit a libcall.
2075 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2077 if (N->getOpcode() == ISD::SHL) {
2078 isSigned = false; /*sign irrelevant*/
2080 LC = RTLIB::SHL_I16;
2081 else if (VT == MVT::i32)
2082 LC = RTLIB::SHL_I32;
2083 else if (VT == MVT::i64)
2084 LC = RTLIB::SHL_I64;
2085 else if (VT == MVT::i128)
2086 LC = RTLIB::SHL_I128;
2087 } else if (N->getOpcode() == ISD::SRL) {
2090 LC = RTLIB::SRL_I16;
2091 else if (VT == MVT::i32)
2092 LC = RTLIB::SRL_I32;
2093 else if (VT == MVT::i64)
2094 LC = RTLIB::SRL_I64;
2095 else if (VT == MVT::i128)
2096 LC = RTLIB::SRL_I128;
2098 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2101 LC = RTLIB::SRA_I16;
2102 else if (VT == MVT::i32)
2103 LC = RTLIB::SRA_I32;
2104 else if (VT == MVT::i64)
2105 LC = RTLIB::SRA_I64;
2106 else if (VT == MVT::i128)
2107 LC = RTLIB::SRA_I128;
2110 if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
2111 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2112 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned, dl), Lo, Hi);
2116 if (!ExpandShiftWithUnknownAmountBit(N, Lo, Hi))
2117 llvm_unreachable("Unsupported shift!");
2120 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
2121 SDValue &Lo, SDValue &Hi) {
2122 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2123 DebugLoc dl = N->getDebugLoc();
2124 SDValue Op = N->getOperand(0);
2125 if (Op.getValueType().bitsLE(NVT)) {
2126 // The low part is sign extension of the input (degenerates to a copy).
2127 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
2128 // The high part is obtained by SRA'ing all but one of the bits of low part.
2129 unsigned LoSize = NVT.getSizeInBits();
2130 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2131 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
2133 // For example, extension of an i48 to an i64. The operand type necessarily
2134 // promotes to the result type, so will end up being expanded too.
2135 assert(getTypeAction(Op.getValueType()) ==
2136 TargetLowering::TypePromoteInteger &&
2137 "Only know how to promote this result!");
2138 SDValue Res = GetPromotedInteger(Op);
2139 assert(Res.getValueType() == N->getValueType(0) &&
2140 "Operand over promoted?");
2141 // Split the promoted operand. This will simplify when it is expanded.
2142 SplitInteger(Res, Lo, Hi);
2143 unsigned ExcessBits =
2144 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2145 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2146 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2151 void DAGTypeLegalizer::
2152 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
2153 DebugLoc dl = N->getDebugLoc();
2154 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2155 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
2157 if (EVT.bitsLE(Lo.getValueType())) {
2158 // sext_inreg the low part if needed.
2159 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Lo.getValueType(), Lo,
2162 // The high part gets the sign extension from the lo-part. This handles
2163 // things like sextinreg V:i64 from i8.
2164 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2165 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
2166 TLI.getPointerTy()));
2168 // For example, extension of an i48 to an i64. Leave the low part alone,
2169 // sext_inreg the high part.
2170 unsigned ExcessBits =
2171 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
2172 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
2173 DAG.getValueType(EVT::getIntegerVT(*DAG.getContext(),
2178 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
2179 SDValue &Lo, SDValue &Hi) {
2180 EVT VT = N->getValueType(0);
2181 DebugLoc dl = N->getDebugLoc();
2183 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2185 LC = RTLIB::SREM_I16;
2186 else if (VT == MVT::i32)
2187 LC = RTLIB::SREM_I32;
2188 else if (VT == MVT::i64)
2189 LC = RTLIB::SREM_I64;
2190 else if (VT == MVT::i128)
2191 LC = RTLIB::SREM_I128;
2192 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
2194 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2195 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true, dl), Lo, Hi);
2198 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
2199 SDValue &Lo, SDValue &Hi) {
2200 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2201 DebugLoc dl = N->getDebugLoc();
2202 Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
2203 Hi = DAG.getNode(ISD::SRL, dl,
2204 N->getOperand(0).getValueType(), N->getOperand(0),
2205 DAG.getConstant(NVT.getSizeInBits(), TLI.getPointerTy()));
2206 Hi = DAG.getNode(ISD::TRUNCATE, dl, NVT, Hi);
2209 void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
2210 SDValue &Lo, SDValue &Hi) {
2211 SDValue LHS = N->getOperand(0);
2212 SDValue RHS = N->getOperand(1);
2213 DebugLoc dl = N->getDebugLoc();
2215 // Expand the result by simply replacing it with the equivalent
2216 // non-overflow-checking operation.
2217 SDValue Sum = DAG.getNode(N->getOpcode() == ISD::UADDO ?
2218 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2220 SplitInteger(Sum, Lo, Hi);
2222 // Calculate the overflow: addition overflows iff a + b < a, and subtraction
2223 // overflows iff a - b > a.
2224 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Sum, LHS,
2225 N->getOpcode () == ISD::UADDO ?
2226 ISD::SETULT : ISD::SETUGT);
2228 // Use the calculated overflow everywhere.
2229 ReplaceValueWith(SDValue(N, 1), Ofl);
2232 void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
2233 SDValue &Lo, SDValue &Hi) {
2234 EVT VT = N->getValueType(0);
2235 Type *RetTy = VT.getTypeForEVT(*DAG.getContext());
2236 EVT PtrVT = TLI.getPointerTy();
2237 Type *PtrTy = PtrVT.getTypeForEVT(*DAG.getContext());
2238 DebugLoc dl = N->getDebugLoc();
2240 // A divide for UMULO should be faster than a function call.
2241 if (N->getOpcode() == ISD::UMULO) {
2242 SDValue LHS = N->getOperand(0), RHS = N->getOperand(1);
2243 DebugLoc DL = N->getDebugLoc();
2245 SDValue MUL = DAG.getNode(ISD::MUL, DL, LHS.getValueType(), LHS, RHS);
2246 SplitInteger(MUL, Lo, Hi);
2248 // A divide for UMULO will be faster than a function call. Select to
2249 // make sure we aren't using 0.
2250 SDValue isZero = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2251 RHS, DAG.getConstant(0, VT), ISD::SETNE);
2252 SDValue NotZero = DAG.getNode(ISD::SELECT, dl, VT, isZero,
2253 DAG.getConstant(1, VT), RHS);
2254 SDValue DIV = DAG.getNode(ISD::UDIV, DL, LHS.getValueType(), MUL, NotZero);
2256 Overflow = DAG.getSetCC(DL, N->getValueType(1), DIV, LHS, ISD::SETNE);
2257 ReplaceValueWith(SDValue(N, 1), Overflow);
2261 // Replace this with a libcall that will check overflow.
2262 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2264 LC = RTLIB::MULO_I32;
2265 else if (VT == MVT::i64)
2266 LC = RTLIB::MULO_I64;
2267 else if (VT == MVT::i128)
2268 LC = RTLIB::MULO_I128;
2269 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XMULO!");
2271 SDValue Temp = DAG.CreateStackTemporary(PtrVT);
2272 // Temporary for the overflow value, default it to zero.
2273 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl,
2274 DAG.getConstant(0, PtrVT), Temp,
2275 MachinePointerInfo(), false, false, 0);
2277 TargetLowering::ArgListTy Args;
2278 TargetLowering::ArgListEntry Entry;
2279 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
2280 EVT ArgVT = N->getOperand(i).getValueType();
2281 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2282 Entry.Node = N->getOperand(i);
2284 Entry.isSExt = true;
2285 Entry.isZExt = false;
2286 Args.push_back(Entry);
2289 // Also pass the address of the overflow check.
2291 Entry.Ty = PtrTy->getPointerTo();
2292 Entry.isSExt = true;
2293 Entry.isZExt = false;
2294 Args.push_back(Entry);
2296 SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
2297 std::pair<SDValue, SDValue> CallInfo =
2298 TLI.LowerCallTo(Chain, RetTy, true, false, false, false,
2299 0, TLI.getLibcallCallingConv(LC), false,
2300 true, Func, Args, DAG, dl);
2302 SplitInteger(CallInfo.first, Lo, Hi);
2303 SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
2304 MachinePointerInfo(), false, false, 0);
2305 SDValue Ofl = DAG.getSetCC(dl, N->getValueType(1), Temp2,
2306 DAG.getConstant(0, PtrVT),
2308 // Use the overflow from the libcall everywhere.
2309 ReplaceValueWith(SDValue(N, 1), Ofl);
2312 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
2313 SDValue &Lo, SDValue &Hi) {
2314 EVT VT = N->getValueType(0);
2315 DebugLoc dl = N->getDebugLoc();
2317 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2319 LC = RTLIB::UDIV_I16;
2320 else if (VT == MVT::i32)
2321 LC = RTLIB::UDIV_I32;
2322 else if (VT == MVT::i64)
2323 LC = RTLIB::UDIV_I64;
2324 else if (VT == MVT::i128)
2325 LC = RTLIB::UDIV_I128;
2326 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
2328 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2329 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2332 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
2333 SDValue &Lo, SDValue &Hi) {
2334 EVT VT = N->getValueType(0);
2335 DebugLoc dl = N->getDebugLoc();
2337 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2339 LC = RTLIB::UREM_I16;
2340 else if (VT == MVT::i32)
2341 LC = RTLIB::UREM_I32;
2342 else if (VT == MVT::i64)
2343 LC = RTLIB::UREM_I64;
2344 else if (VT == MVT::i128)
2345 LC = RTLIB::UREM_I128;
2346 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
2348 SDValue Ops[2] = { N->getOperand(0), N->getOperand(1) };
2349 SplitInteger(MakeLibCall(LC, VT, Ops, 2, false, dl), Lo, Hi);
2352 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
2353 SDValue &Lo, SDValue &Hi) {
2354 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
2355 DebugLoc dl = N->getDebugLoc();
2356 SDValue Op = N->getOperand(0);
2357 if (Op.getValueType().bitsLE(NVT)) {
2358 // The low part is zero extension of the input (degenerates to a copy).
2359 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0));
2360 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
2362 // For example, extension of an i48 to an i64. The operand type necessarily
2363 // promotes to the result type, so will end up being expanded too.
2364 assert(getTypeAction(Op.getValueType()) ==
2365 TargetLowering::TypePromoteInteger &&
2366 "Only know how to promote this result!");
2367 SDValue Res = GetPromotedInteger(Op);
2368 assert(Res.getValueType() == N->getValueType(0) &&
2369 "Operand over promoted?");
2370 // Split the promoted operand. This will simplify when it is expanded.
2371 SplitInteger(Res, Lo, Hi);
2372 unsigned ExcessBits =
2373 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
2374 Hi = DAG.getZeroExtendInReg(Hi, dl,
2375 EVT::getIntegerVT(*DAG.getContext(),
2380 void DAGTypeLegalizer::ExpandIntRes_ATOMIC_LOAD(SDNode *N,
2381 SDValue &Lo, SDValue &Hi) {
2382 DebugLoc dl = N->getDebugLoc();
2383 EVT VT = cast<AtomicSDNode>(N)->getMemoryVT();
2384 SDValue Zero = DAG.getConstant(0, VT);
2385 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT,
2387 N->getOperand(1), Zero, Zero,
2388 cast<AtomicSDNode>(N)->getMemOperand(),
2389 cast<AtomicSDNode>(N)->getOrdering(),
2390 cast<AtomicSDNode>(N)->getSynchScope());
2391 ReplaceValueWith(SDValue(N, 0), Swap.getValue(0));
2392 ReplaceValueWith(SDValue(N, 1), Swap.getValue(1));
2395 //===----------------------------------------------------------------------===//
2396 // Integer Operand Expansion
2397 //===----------------------------------------------------------------------===//
2399 /// ExpandIntegerOperand - This method is called when the specified operand of
2400 /// the specified node is found to need expansion. At this point, all of the
2401 /// result types of the node are known to be legal, but other operands of the
2402 /// node may need promotion or expansion as well as the specified one.
2403 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
2404 DEBUG(dbgs() << "Expand integer operand: "; N->dump(&DAG); dbgs() << "\n");
2405 SDValue Res = SDValue();
2407 if (CustomLowerNode(N, N->getOperand(OpNo).getValueType(), false))
2410 switch (N->getOpcode()) {
2413 dbgs() << "ExpandIntegerOperand Op #" << OpNo << ": ";
2414 N->dump(&DAG); dbgs() << "\n";
2416 llvm_unreachable("Do not know how to expand this operator's operand!");
2418 case ISD::BITCAST: Res = ExpandOp_BITCAST(N); break;
2419 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
2420 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
2421 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
2422 case ISD::INSERT_VECTOR_ELT: Res = ExpandOp_INSERT_VECTOR_ELT(N); break;
2423 case ISD::SCALAR_TO_VECTOR: Res = ExpandOp_SCALAR_TO_VECTOR(N); break;
2424 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
2425 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
2426 case ISD::SINT_TO_FP: Res = ExpandIntOp_SINT_TO_FP(N); break;
2427 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
2428 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
2429 case ISD::UINT_TO_FP: Res = ExpandIntOp_UINT_TO_FP(N); break;
2435 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break;
2436 case ISD::RETURNADDR:
2437 case ISD::FRAMEADDR: Res = ExpandIntOp_RETURNADDR(N); break;
2439 case ISD::ATOMIC_STORE: Res = ExpandIntOp_ATOMIC_STORE(N); break;
2442 // If the result is null, the sub-method took care of registering results etc.
2443 if (!Res.getNode()) return false;
2445 // If the result is N, the sub-method updated N in place. Tell the legalizer
2447 if (Res.getNode() == N)
2450 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
2451 "Invalid operand expansion");
2453 ReplaceValueWith(SDValue(N, 0), Res);
2457 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
2458 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
2459 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS,
2461 ISD::CondCode &CCCode,
2463 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
2464 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
2465 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
2467 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
2468 if (RHSLo == RHSHi) {
2469 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
2470 if (RHSCST->isAllOnesValue()) {
2471 // Equality comparison to -1.
2472 NewLHS = DAG.getNode(ISD::AND, dl,
2473 LHSLo.getValueType(), LHSLo, LHSHi);
2480 NewLHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
2481 NewRHS = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
2482 NewLHS = DAG.getNode(ISD::OR, dl, NewLHS.getValueType(), NewLHS, NewRHS);
2483 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2487 // If this is a comparison of the sign bit, just look at the top part.
2489 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
2490 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
2491 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
2497 // FIXME: This generated code sucks.
2498 ISD::CondCode LowCC;
2500 default: llvm_unreachable("Unknown integer setcc!");
2502 case ISD::SETULT: LowCC = ISD::SETULT; break;
2504 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2506 case ISD::SETULE: LowCC = ISD::SETULE; break;
2508 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2511 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2512 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2513 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2515 // NOTE: on targets without efficient SELECT of bools, we can always use
2516 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2517 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, true, NULL);
2519 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
2520 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
2521 if (!Tmp1.getNode())
2522 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
2523 LHSLo, RHSLo, LowCC);
2524 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2525 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
2526 if (!Tmp2.getNode())
2527 Tmp2 = DAG.getNode(ISD::SETCC, dl,
2528 TLI.getSetCCResultType(LHSHi.getValueType()),
2529 LHSHi, RHSHi, DAG.getCondCode(CCCode));
2531 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2532 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
2533 if ((Tmp1C && Tmp1C->isNullValue()) ||
2534 (Tmp2C && Tmp2C->isNullValue() &&
2535 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
2536 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
2537 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
2538 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
2539 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
2540 // low part is known false, returns high part.
2541 // For LE / GE, if high part is known false, ignore the low part.
2542 // For LT / GT, if high part is known true, ignore the low part.
2548 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
2549 LHSHi, RHSHi, ISD::SETEQ, false,
2550 DagCombineInfo, dl);
2551 if (!NewLHS.getNode())
2552 NewLHS = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
2553 LHSHi, RHSHi, ISD::SETEQ);
2554 NewLHS = DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
2555 NewLHS, Tmp1, Tmp2);
2559 SDValue DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
2560 SDValue NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
2561 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
2562 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2564 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2565 // against zero to select between true and false values.
2566 if (NewRHS.getNode() == 0) {
2567 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2568 CCCode = ISD::SETNE;
2571 // Update N to have the operands specified.
2572 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0),
2573 DAG.getCondCode(CCCode), NewLHS, NewRHS,
2574 N->getOperand(4)), 0);
2577 SDValue DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
2578 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2579 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
2580 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2582 // If ExpandSetCCOperands returned a scalar, we need to compare the result
2583 // against zero to select between true and false values.
2584 if (NewRHS.getNode() == 0) {
2585 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
2586 CCCode = ISD::SETNE;
2589 // Update N to have the operands specified.
2590 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2591 N->getOperand(2), N->getOperand(3),
2592 DAG.getCondCode(CCCode)), 0);
2595 SDValue DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
2596 SDValue NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
2597 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
2598 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode, N->getDebugLoc());
2600 // If ExpandSetCCOperands returned a scalar, use it.
2601 if (NewRHS.getNode() == 0) {
2602 assert(NewLHS.getValueType() == N->getValueType(0) &&
2603 "Unexpected setcc expansion!");
2607 // Otherwise, update N to have the operands specified.
2608 return SDValue(DAG.UpdateNodeOperands(N, NewLHS, NewRHS,
2609 DAG.getCondCode(CCCode)), 0);
2612 SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) {
2613 // The value being shifted is legal, but the shift amount is too big.
2614 // It follows that either the result of the shift is undefined, or the
2615 // upper half of the shift amount is zero. Just use the lower half.
2617 GetExpandedInteger(N->getOperand(1), Lo, Hi);
2618 return SDValue(DAG.UpdateNodeOperands(N, N->getOperand(0), Lo), 0);
2621 SDValue DAGTypeLegalizer::ExpandIntOp_RETURNADDR(SDNode *N) {
2622 // The argument of RETURNADDR / FRAMEADDR builtin is 32 bit contant. This
2623 // surely makes pretty nice problems on 8/16 bit targets. Just truncate this
2624 // constant to valid type.
2626 GetExpandedInteger(N->getOperand(0), Lo, Hi);
2627 return SDValue(DAG.UpdateNodeOperands(N, Lo), 0);
2630 SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
2631 SDValue Op = N->getOperand(0);
2632 EVT DstVT = N->getValueType(0);
2633 RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
2634 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2635 "Don't know how to expand this SINT_TO_FP!");
2636 return MakeLibCall(LC, DstVT, &Op, 1, true, N->getDebugLoc());
2639 SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
2640 if (ISD::isNormalStore(N))
2641 return ExpandOp_NormalStore(N, OpNo);
2643 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
2644 assert(OpNo == 1 && "Can only expand the stored value so far");
2646 EVT VT = N->getOperand(1).getValueType();
2647 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
2648 SDValue Ch = N->getChain();
2649 SDValue Ptr = N->getBasePtr();
2650 unsigned Alignment = N->getAlignment();
2651 bool isVolatile = N->isVolatile();
2652 bool isNonTemporal = N->isNonTemporal();
2653 DebugLoc dl = N->getDebugLoc();
2656 assert(NVT.isByteSized() && "Expanded type not byte sized!");
2658 if (N->getMemoryVT().bitsLE(NVT)) {
2659 GetExpandedInteger(N->getValue(), Lo, Hi);
2660 return DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2661 N->getMemoryVT(), isVolatile, isNonTemporal,
2665 if (TLI.isLittleEndian()) {
2666 // Little-endian - low bits are at low addresses.
2667 GetExpandedInteger(N->getValue(), Lo, Hi);
2669 Lo = DAG.getStore(Ch, dl, Lo, Ptr, N->getPointerInfo(),
2670 isVolatile, isNonTemporal, Alignment);
2672 unsigned ExcessBits =
2673 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
2674 EVT NEVT = EVT::getIntegerVT(*DAG.getContext(), ExcessBits);
2676 // Increment the pointer to the other half.
2677 unsigned IncrementSize = NVT.getSizeInBits()/8;
2678 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2679 DAG.getIntPtrConstant(IncrementSize));
2680 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr,
2681 N->getPointerInfo().getWithOffset(IncrementSize),
2682 NEVT, isVolatile, isNonTemporal,
2683 MinAlign(Alignment, IncrementSize));
2684 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2687 // Big-endian - high bits are at low addresses. Favor aligned stores at
2688 // the cost of some bit-fiddling.
2689 GetExpandedInteger(N->getValue(), Lo, Hi);
2691 EVT ExtVT = N->getMemoryVT();
2692 unsigned EBytes = ExtVT.getStoreSize();
2693 unsigned IncrementSize = NVT.getSizeInBits()/8;
2694 unsigned ExcessBits = (EBytes - IncrementSize)*8;
2695 EVT HiVT = EVT::getIntegerVT(*DAG.getContext(),
2696 ExtVT.getSizeInBits() - ExcessBits);
2698 if (ExcessBits < NVT.getSizeInBits()) {
2699 // Transfer high bits from the top of Lo to the bottom of Hi.
2700 Hi = DAG.getNode(ISD::SHL, dl, NVT, Hi,
2701 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
2702 TLI.getPointerTy()));
2703 Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
2704 DAG.getNode(ISD::SRL, dl, NVT, Lo,
2705 DAG.getConstant(ExcessBits,
2706 TLI.getPointerTy())));
2709 // Store both the high bits and maybe some of the low bits.
2710 Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getPointerInfo(),
2711 HiVT, isVolatile, isNonTemporal, Alignment);
2713 // Increment the pointer to the other half.
2714 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
2715 DAG.getIntPtrConstant(IncrementSize));
2716 // Store the lowest ExcessBits bits in the second half.
2717 Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr,
2718 N->getPointerInfo().getWithOffset(IncrementSize),
2719 EVT::getIntegerVT(*DAG.getContext(), ExcessBits),
2720 isVolatile, isNonTemporal,
2721 MinAlign(Alignment, IncrementSize));
2722 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2725 SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
2727 GetExpandedInteger(N->getOperand(0), InL, InH);
2728 // Just truncate the low part of the source.
2729 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), N->getValueType(0), InL);
2732 static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
2733 switch (VT.getSimpleVT().SimpleTy) {
2734 default: llvm_unreachable("Unknown FP format");
2735 case MVT::f32: return &APFloat::IEEEsingle;
2736 case MVT::f64: return &APFloat::IEEEdouble;
2737 case MVT::f80: return &APFloat::x87DoubleExtended;
2738 case MVT::f128: return &APFloat::IEEEquad;
2739 case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
2743 SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
2744 SDValue Op = N->getOperand(0);
2745 EVT SrcVT = Op.getValueType();
2746 EVT DstVT = N->getValueType(0);
2747 DebugLoc dl = N->getDebugLoc();
2749 // The following optimization is valid only if every value in SrcVT (when
2750 // treated as signed) is representable in DstVT. Check that the mantissa
2751 // size of DstVT is >= than the number of bits in SrcVT -1.
2752 const fltSemantics *sem = EVTToAPFloatSemantics(DstVT);
2753 if (APFloat::semanticsPrecision(*sem) >= SrcVT.getSizeInBits()-1 &&
2754 TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
2755 // Do a signed conversion then adjust the result.
2756 SDValue SignedConv = DAG.getNode(ISD::SINT_TO_FP, dl, DstVT, Op);
2757 SignedConv = TLI.LowerOperation(SignedConv, DAG);
2759 // The result of the signed conversion needs adjusting if the 'sign bit' of
2760 // the incoming integer was set. To handle this, we dynamically test to see
2761 // if it is set, and, if so, add a fudge factor.
2763 const uint64_t F32TwoE32 = 0x4F800000ULL;
2764 const uint64_t F32TwoE64 = 0x5F800000ULL;
2765 const uint64_t F32TwoE128 = 0x7F800000ULL;
2768 if (SrcVT == MVT::i32)
2769 FF = APInt(32, F32TwoE32);
2770 else if (SrcVT == MVT::i64)
2771 FF = APInt(32, F32TwoE64);
2772 else if (SrcVT == MVT::i128)
2773 FF = APInt(32, F32TwoE128);
2775 assert(false && "Unsupported UINT_TO_FP!");
2777 // Check whether the sign bit is set.
2779 GetExpandedInteger(Op, Lo, Hi);
2780 SDValue SignSet = DAG.getSetCC(dl,
2781 TLI.getSetCCResultType(Hi.getValueType()),
2782 Hi, DAG.getConstant(0, Hi.getValueType()),
2785 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.
2786 SDValue FudgePtr = DAG.getConstantPool(
2787 ConstantInt::get(*DAG.getContext(), FF.zext(64)),
2788 TLI.getPointerTy());
2790 // Get a pointer to FF if the sign bit was set, or to 0 otherwise.
2791 SDValue Zero = DAG.getIntPtrConstant(0);
2792 SDValue Four = DAG.getIntPtrConstant(4);
2793 if (TLI.isBigEndian()) std::swap(Zero, Four);
2794 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,
2796 unsigned Alignment = cast<ConstantPoolSDNode>(FudgePtr)->getAlignment();
2797 FudgePtr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), FudgePtr, Offset);
2798 Alignment = std::min(Alignment, 4u);
2800 // Load the value out, extending it from f32 to the destination float type.
2801 // FIXME: Avoid the extend by constructing the right constant pool?
2802 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
2804 MachinePointerInfo::getConstantPool(),
2806 false, false, Alignment);
2807 return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
2810 // Otherwise, use a libcall.
2811 RTLIB::Libcall LC = RTLIB::getUINTTOFP(SrcVT, DstVT);
2812 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
2813 "Don't know how to expand this UINT_TO_FP!");
2814 return MakeLibCall(LC, DstVT, &Op, 1, true, dl);
2817 SDValue DAGTypeLegalizer::ExpandIntOp_ATOMIC_STORE(SDNode *N) {
2818 DebugLoc dl = N->getDebugLoc();
2819 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2820 cast<AtomicSDNode>(N)->getMemoryVT(),
2822 N->getOperand(1), N->getOperand(2),
2823 cast<AtomicSDNode>(N)->getMemOperand(),
2824 cast<AtomicSDNode>(N)->getOrdering(),
2825 cast<AtomicSDNode>(N)->getSynchScope());
2826 return Swap.getValue(1);
2830 SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_SUBVECTOR(SDNode *N) {
2831 SDValue InOp0 = N->getOperand(0);
2832 EVT InVT = InOp0.getValueType();
2834 EVT OutVT = N->getValueType(0);
2835 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2836 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2837 unsigned OutNumElems = OutVT.getVectorNumElements();
2838 EVT NOutVTElem = NOutVT.getVectorElementType();
2840 DebugLoc dl = N->getDebugLoc();
2841 SDValue BaseIdx = N->getOperand(1);
2843 SmallVector<SDValue, 8> Ops;
2844 Ops.reserve(OutNumElems);
2845 for (unsigned i = 0; i != OutNumElems; ++i) {
2847 // Extract the element from the original vector.
2848 SDValue Index = DAG.getNode(ISD::ADD, dl, BaseIdx.getValueType(),
2849 BaseIdx, DAG.getIntPtrConstant(i));
2850 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2851 InVT.getVectorElementType(), N->getOperand(0), Index);
2853 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, Ext);
2854 // Insert the converted element to the new vector.
2858 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2862 SDValue DAGTypeLegalizer::PromoteIntRes_VECTOR_SHUFFLE(SDNode *N) {
2863 ShuffleVectorSDNode *SV = cast<ShuffleVectorSDNode>(N);
2864 EVT VT = N->getValueType(0);
2865 DebugLoc dl = N->getDebugLoc();
2867 unsigned NumElts = VT.getVectorNumElements();
2868 SmallVector<int, 8> NewMask;
2869 for (unsigned i = 0; i != NumElts; ++i) {
2870 NewMask.push_back(SV->getMaskElt(i));
2873 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2874 SDValue V1 = GetPromotedInteger(N->getOperand(1));
2875 EVT OutVT = V0.getValueType();
2877 return DAG.getVectorShuffle(OutVT, dl, V0, V1, &NewMask[0]);
2881 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
2882 EVT OutVT = N->getValueType(0);
2883 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2884 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2885 unsigned NumElems = N->getNumOperands();
2886 EVT NOutVTElem = NOutVT.getVectorElementType();
2888 DebugLoc dl = N->getDebugLoc();
2890 SmallVector<SDValue, 8> Ops;
2891 Ops.reserve(NumElems);
2892 for (unsigned i = 0; i != NumElems; ++i) {
2893 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
2897 return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, &Ops[0], Ops.size());
2900 SDValue DAGTypeLegalizer::PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N) {
2902 DebugLoc dl = N->getDebugLoc();
2904 assert(!N->getOperand(0).getValueType().isVector() &&
2905 "Input must be a scalar");
2907 EVT OutVT = N->getValueType(0);
2908 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2909 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2910 EVT NOutVTElem = NOutVT.getVectorElementType();
2912 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0));
2914 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NOutVT, Op);
2917 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
2918 EVT OutVT = N->getValueType(0);
2919 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
2920 assert(NOutVT.isVector() && "This type must be promoted to a vector type");
2922 EVT NOutVTElem = NOutVT.getVectorElementType();
2924 DebugLoc dl = N->getDebugLoc();
2925 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2927 SDValue ConvElem = DAG.getNode(ISD::ANY_EXTEND, dl,
2928 NOutVTElem, N->getOperand(1));
2929 return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NOutVT,
2930 V0, ConvElem, N->getOperand(2));
2933 SDValue DAGTypeLegalizer::PromoteIntOp_EXTRACT_VECTOR_ELT(SDNode *N) {
2934 DebugLoc dl = N->getDebugLoc();
2935 SDValue V0 = GetPromotedInteger(N->getOperand(0));
2936 SDValue V1 = N->getOperand(1);
2937 SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2938 V0->getValueType(0).getScalarType(), V0, V1);
2940 return DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), Ext);
2944 SDValue DAGTypeLegalizer::PromoteIntOp_CONCAT_VECTORS(SDNode *N) {
2945 DebugLoc dl = N->getDebugLoc();
2946 unsigned NumElems = N->getNumOperands();
2948 EVT RetSclrTy = N->getValueType(0).getVectorElementType();
2950 SmallVector<SDValue, 8> NewOps;
2951 NewOps.reserve(NumElems);
2953 // For each incoming vector
2954 for (unsigned VecIdx = 0; VecIdx != NumElems; ++VecIdx) {
2955 SDValue Incoming = GetPromotedInteger(N->getOperand(VecIdx));
2956 EVT SclrTy = Incoming->getValueType(0).getVectorElementType();
2957 unsigned NumElem = Incoming->getValueType(0).getVectorNumElements();
2959 for (unsigned i=0; i<NumElem; ++i) {
2960 // Extract element from incoming vector
2961 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SclrTy,
2962 Incoming, DAG.getIntPtrConstant(i));
2963 SDValue Tr = DAG.getNode(ISD::TRUNCATE, dl, RetSclrTy, Ex);
2964 NewOps.push_back(Tr);
2968 return DAG.getNode(ISD::BUILD_VECTOR, dl, N->getValueType(0),
2969 &NewOps[0], NewOps.size());