1 //===----- LegalizeIntegerTypes.cpp - Legalization of integer types -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements integer type expansion and promotion for LegalizeTypes.
11 // Promotion is the act of changing a computation in an illegal type into a
12 // computation in a larger type. For example, implementing i8 arithmetic in an
13 // i32 register (often needed on powerpc).
14 // Expansion is the act of changing a computation in an illegal type into a
15 // computation in two identical registers of a smaller type. For example,
16 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit
19 //===----------------------------------------------------------------------===//
21 #include "LegalizeTypes.h"
22 #include "llvm/Constants.h"
25 //===----------------------------------------------------------------------===//
26 // Integer Result Promotion
27 //===----------------------------------------------------------------------===//
29 /// PromoteIntegerResult - This method is called when a result of a node is
30 /// found to be in need of promotion to a larger type. At this point, the node
31 /// may also have invalid operands or may have other results that need
32 /// expansion, we just know that (at least) one result needs promotion.
33 void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
34 DEBUG(cerr << "Promote integer result: "; N->dump(&DAG); cerr << "\n");
35 SDOperand Result = SDOperand();
37 switch (N->getOpcode()) {
40 cerr << "PromoteIntegerResult #" << ResNo << ": ";
41 N->dump(&DAG); cerr << "\n";
43 assert(0 && "Do not know how to promote this operator!");
45 case ISD::UNDEF: Result = PromoteIntRes_UNDEF(N); break;
46 case ISD::Constant: Result = PromoteIntRes_Constant(N); break;
48 case ISD::TRUNCATE: Result = PromoteIntRes_TRUNCATE(N); break;
49 case ISD::SIGN_EXTEND:
50 case ISD::ZERO_EXTEND:
51 case ISD::ANY_EXTEND: Result = PromoteIntRes_INT_EXTEND(N); break;
52 case ISD::FP_ROUND: Result = PromoteIntRes_FP_ROUND(N); break;
54 case ISD::FP_TO_UINT: Result = PromoteIntRes_FP_TO_XINT(N); break;
55 case ISD::SETCC: Result = PromoteIntRes_SETCC(N); break;
56 case ISD::LOAD: Result = PromoteIntRes_LOAD(cast<LoadSDNode>(N)); break;
57 case ISD::BUILD_PAIR: Result = PromoteIntRes_BUILD_PAIR(N); break;
58 case ISD::BIT_CONVERT: Result = PromoteIntRes_BIT_CONVERT(N); break;
65 case ISD::MUL: Result = PromoteIntRes_SimpleIntBinOp(N); break;
68 case ISD::SREM: Result = PromoteIntRes_SDIV(N); break;
71 case ISD::UREM: Result = PromoteIntRes_UDIV(N); break;
73 case ISD::SHL: Result = PromoteIntRes_SHL(N); break;
74 case ISD::SRA: Result = PromoteIntRes_SRA(N); break;
75 case ISD::SRL: Result = PromoteIntRes_SRL(N); break;
77 case ISD::SELECT: Result = PromoteIntRes_SELECT(N); break;
78 case ISD::SELECT_CC: Result = PromoteIntRes_SELECT_CC(N); break;
80 case ISD::CTLZ: Result = PromoteIntRes_CTLZ(N); break;
81 case ISD::CTPOP: Result = PromoteIntRes_CTPOP(N); break;
82 case ISD::CTTZ: Result = PromoteIntRes_CTTZ(N); break;
84 case ISD::EXTRACT_VECTOR_ELT:
85 Result = PromoteIntRes_EXTRACT_VECTOR_ELT(N);
88 case ISD::VAARG : Result = PromoteIntRes_VAARG(N); break;
91 // If Result is null, the sub-method took care of registering the result.
93 SetPromotedInteger(SDOperand(N, ResNo), Result);
96 SDOperand DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) {
97 return DAG.getNode(ISD::UNDEF, TLI.getTypeToTransformTo(N->getValueType(0)));
100 SDOperand DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
101 MVT VT = N->getValueType(0);
102 // Zero extend things like i1, sign extend everything else. It shouldn't
103 // matter in theory which one we pick, but this tends to give better code?
104 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
105 SDOperand Result = DAG.getNode(Opc, TLI.getTypeToTransformTo(VT),
107 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
111 SDOperand DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
114 switch (getTypeAction(N->getOperand(0).getValueType())) {
115 default: assert(0 && "Unknown type action!");
118 Res = N->getOperand(0);
121 Res = GetPromotedInteger(N->getOperand(0));
125 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
126 assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
127 "Truncation doesn't make sense!");
128 if (Res.getValueType() == NVT)
131 // Truncate to NVT instead of VT
132 return DAG.getNode(ISD::TRUNCATE, NVT, Res);
135 SDOperand DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
136 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
138 if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
139 SDOperand Res = GetPromotedInteger(N->getOperand(0));
140 assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
141 "Extension doesn't make sense!");
143 // If the result and operand types are the same after promotion, simplify
144 // to an in-register extension.
145 if (NVT == Res.getValueType()) {
146 // The high bits are not guaranteed to be anything. Insert an extend.
147 if (N->getOpcode() == ISD::SIGN_EXTEND)
148 return DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res,
149 DAG.getValueType(N->getOperand(0).getValueType()));
150 if (N->getOpcode() == ISD::ZERO_EXTEND)
151 return DAG.getZeroExtendInReg(Res, N->getOperand(0).getValueType());
152 assert(N->getOpcode() == ISD::ANY_EXTEND && "Unknown integer extension!");
157 // Otherwise, just extend the original operand all the way to the larger type.
158 return DAG.getNode(N->getOpcode(), NVT, N->getOperand(0));
161 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_ROUND(SDNode *N) {
162 // NOTE: Assumes input is legal.
163 if (N->getConstantOperandVal(1) == 0)
164 return DAG.getNode(ISD::FP_ROUND_INREG, N->getOperand(0).getValueType(),
165 N->getOperand(0), DAG.getValueType(N->getValueType(0)));
166 // If the precision discard isn't needed, just return the operand unrounded.
167 return N->getOperand(0);
170 SDOperand DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
171 unsigned NewOpc = N->getOpcode();
172 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
174 // If we're promoting a UINT to a larger size, check to see if the new node
175 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
176 // we can use that instead. This allows us to generate better code for
177 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
178 // legal, such as PowerPC.
179 if (N->getOpcode() == ISD::FP_TO_UINT) {
180 if (!TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
181 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
182 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom))
183 NewOpc = ISD::FP_TO_SINT;
186 return DAG.getNode(NewOpc, NVT, N->getOperand(0));
189 SDOperand DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
190 assert(isTypeLegal(TLI.getSetCCResultType(N->getOperand(0)))
191 && "SetCC type is not legal??");
192 return DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(N->getOperand(0)),
193 N->getOperand(0), N->getOperand(1), N->getOperand(2));
196 SDOperand DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
197 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
198 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
199 ISD::LoadExtType ExtType =
200 ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
201 SDOperand Res = DAG.getExtLoad(ExtType, NVT, N->getChain(), N->getBasePtr(),
202 N->getSrcValue(), N->getSrcValueOffset(),
203 N->getMemoryVT(), N->isVolatile(),
206 // Legalized the chain result - switch anything that used the old chain to
208 ReplaceValueWith(SDOperand(N, 1), Res.getValue(1));
212 SDOperand DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {
213 // The pair element type may be legal, or may not promote to the same type as
214 // the result, for example i14 = BUILD_PAIR (i7, i7). Handle all cases.
215 return DAG.getNode(ISD::ANY_EXTEND,
216 TLI.getTypeToTransformTo(N->getValueType(0)),
217 JoinIntegers(N->getOperand(0), N->getOperand(1)));
220 SDOperand DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
221 SDOperand InOp = N->getOperand(0);
222 MVT InVT = InOp.getValueType();
223 MVT NInVT = TLI.getTypeToTransformTo(InVT);
224 MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
226 switch (getTypeAction(InVT)) {
228 assert(false && "Unknown type action!");
233 if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
234 // The input promotes to the same size. Convert the promoted value.
235 return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
238 // Promote the integer operand by hand.
239 return DAG.getNode(ISD::ANY_EXTEND, OutVT, GetSoftenedFloat(InOp));
244 // Convert the element to an integer and promote it by hand.
245 return DAG.getNode(ISD::ANY_EXTEND, OutVT,
246 BitConvertToInteger(GetScalarizedVector(InOp)));
248 // For example, i32 = BIT_CONVERT v2i16 on alpha. Convert the split
249 // pieces of the input into integers and reassemble in the final type.
251 GetSplitVector(N->getOperand(0), Lo, Hi);
252 Lo = BitConvertToInteger(Lo);
253 Hi = BitConvertToInteger(Hi);
255 if (TLI.isBigEndian())
258 InOp = DAG.getNode(ISD::ANY_EXTEND,
259 MVT::getIntegerVT(OutVT.getSizeInBits()),
260 JoinIntegers(Lo, Hi));
261 return DAG.getNode(ISD::BIT_CONVERT, OutVT, InOp);
264 // Otherwise, lower the bit-convert to a store/load from the stack, then
266 SDOperand Op = CreateStackStoreLoad(InOp, N->getValueType(0));
267 return PromoteIntRes_LOAD(cast<LoadSDNode>(Op.Val));
270 SDOperand DAGTypeLegalizer::PromoteIntRes_SimpleIntBinOp(SDNode *N) {
271 // The input may have strange things in the top bits of the registers, but
272 // these operations don't care. They may have weird bits going out, but
273 // that too is okay if they are integer operations.
274 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
275 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
276 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
279 SDOperand DAGTypeLegalizer::PromoteIntRes_SDIV(SDNode *N) {
280 // Sign extend the input.
281 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
282 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
283 MVT VT = N->getValueType(0);
284 LHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, LHS.getValueType(), LHS,
285 DAG.getValueType(VT));
286 RHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, RHS.getValueType(), RHS,
287 DAG.getValueType(VT));
289 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
292 SDOperand DAGTypeLegalizer::PromoteIntRes_UDIV(SDNode *N) {
293 // Zero extend the input.
294 SDOperand LHS = GetPromotedInteger(N->getOperand(0));
295 SDOperand RHS = GetPromotedInteger(N->getOperand(1));
296 MVT VT = N->getValueType(0);
297 LHS = DAG.getZeroExtendInReg(LHS, VT);
298 RHS = DAG.getZeroExtendInReg(RHS, VT);
300 return DAG.getNode(N->getOpcode(), LHS.getValueType(), LHS, RHS);
303 SDOperand DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
304 return DAG.getNode(ISD::SHL, TLI.getTypeToTransformTo(N->getValueType(0)),
305 GetPromotedInteger(N->getOperand(0)), N->getOperand(1));
308 SDOperand DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
309 // The input value must be properly sign extended.
310 MVT VT = N->getValueType(0);
311 MVT NVT = TLI.getTypeToTransformTo(VT);
312 SDOperand Res = GetPromotedInteger(N->getOperand(0));
313 Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Res, DAG.getValueType(VT));
314 return DAG.getNode(ISD::SRA, NVT, Res, N->getOperand(1));
317 SDOperand DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
318 // The input value must be properly zero extended.
319 MVT VT = N->getValueType(0);
320 MVT NVT = TLI.getTypeToTransformTo(VT);
321 SDOperand Res = ZExtPromotedInteger(N->getOperand(0));
322 return DAG.getNode(ISD::SRL, NVT, Res, N->getOperand(1));
325 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT(SDNode *N) {
326 SDOperand LHS = GetPromotedInteger(N->getOperand(1));
327 SDOperand RHS = GetPromotedInteger(N->getOperand(2));
328 return DAG.getNode(ISD::SELECT, LHS.getValueType(), N->getOperand(0),LHS,RHS);
331 SDOperand DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) {
332 SDOperand LHS = GetPromotedInteger(N->getOperand(2));
333 SDOperand RHS = GetPromotedInteger(N->getOperand(3));
334 return DAG.getNode(ISD::SELECT_CC, LHS.getValueType(), N->getOperand(0),
335 N->getOperand(1), LHS, RHS, N->getOperand(4));
338 SDOperand DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) {
339 SDOperand Op = GetPromotedInteger(N->getOperand(0));
340 MVT OVT = N->getValueType(0);
341 MVT NVT = Op.getValueType();
342 // Zero extend to the promoted type and do the count there.
343 Op = DAG.getNode(ISD::CTLZ, NVT, DAG.getZeroExtendInReg(Op, OVT));
344 // Subtract off the extra leading bits in the bigger type.
345 return DAG.getNode(ISD::SUB, NVT, Op,
346 DAG.getConstant(NVT.getSizeInBits() -
347 OVT.getSizeInBits(), NVT));
350 SDOperand DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) {
351 SDOperand Op = GetPromotedInteger(N->getOperand(0));
352 MVT OVT = N->getValueType(0);
353 MVT NVT = Op.getValueType();
354 // Zero extend to the promoted type and do the count there.
355 return DAG.getNode(ISD::CTPOP, NVT, DAG.getZeroExtendInReg(Op, OVT));
358 SDOperand DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
359 SDOperand Op = GetPromotedInteger(N->getOperand(0));
360 MVT OVT = N->getValueType(0);
361 MVT NVT = Op.getValueType();
362 // The count is the same in the promoted type except if the original
363 // value was zero. This can be handled by setting the bit just off
364 // the top of the original type.
365 Op = DAG.getNode(ISD::OR, NVT, Op,
366 // FIXME: Do this using an APINT constant.
367 DAG.getConstant(1UL << OVT.getSizeInBits(), NVT));
368 return DAG.getNode(ISD::CTTZ, NVT, Op);
371 SDOperand DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
372 MVT OldVT = N->getValueType(0);
373 SDOperand OldVec = N->getOperand(0);
374 unsigned OldElts = OldVec.getValueType().getVectorNumElements();
377 assert(!isTypeLegal(OldVec.getValueType()) &&
378 "Legal one-element vector of a type needing promotion!");
379 // It is tempting to follow GetScalarizedVector by a call to
380 // GetPromotedInteger, but this would be wrong because the
381 // scalarized value may not yet have been processed.
382 return DAG.getNode(ISD::ANY_EXTEND, TLI.getTypeToTransformTo(OldVT),
383 GetScalarizedVector(OldVec));
386 // Convert to a vector half as long with an element type of twice the width,
387 // for example <4 x i16> -> <2 x i32>.
388 assert(!(OldElts & 1) && "Odd length vectors not supported!");
389 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
390 assert(OldVT.isSimple() && NewVT.isSimple());
392 SDOperand NewVec = DAG.getNode(ISD::BIT_CONVERT,
393 MVT::getVectorVT(NewVT, OldElts / 2),
396 // Extract the element at OldIdx / 2 from the new vector.
397 SDOperand OldIdx = N->getOperand(1);
398 SDOperand NewIdx = DAG.getNode(ISD::SRL, OldIdx.getValueType(), OldIdx,
399 DAG.getConstant(1, TLI.getShiftAmountTy()));
400 SDOperand Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, NewVec, NewIdx);
402 // Select the appropriate half of the element: Lo if OldIdx was even,
405 SDOperand Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
406 DAG.getConstant(OldVT.getSizeInBits(),
407 TLI.getShiftAmountTy()));
408 if (TLI.isBigEndian())
411 SDOperand Odd = DAG.getNode(ISD::AND, OldIdx.getValueType(), OldIdx,
412 DAG.getConstant(1, TLI.getShiftAmountTy()));
413 return DAG.getNode(ISD::SELECT, NewVT, Odd, Hi, Lo);
416 SDOperand DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
417 SDOperand Chain = N->getOperand(0); // Get the chain.
418 SDOperand Ptr = N->getOperand(1); // Get the pointer.
419 MVT VT = N->getValueType(0);
421 const Value *V = cast<SrcValueSDNode>(N->getOperand(2))->getValue();
422 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Chain, Ptr, V, 0);
424 // Increment the arg pointer, VAList, to the next vaarg
425 // FIXME: should the ABI size be used for the increment? Think of
426 // x86 long double (10 bytes long, but aligned on 4 or 8 bytes) or
427 // integers of unusual size (such MVT::i1, which gives an increment
429 unsigned Increment = VT.getSizeInBits() / 8;
430 SDOperand Tmp = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
431 DAG.getConstant(Increment, TLI.getPointerTy()));
433 // Store the incremented VAList to the pointer.
434 Tmp = DAG.getStore(VAList.getValue(1), Tmp, Ptr, V, 0);
436 // Load the actual argument out of the arg pointer VAList.
437 Tmp = DAG.getExtLoad(ISD::EXTLOAD, TLI.getTypeToTransformTo(VT), Tmp,
438 VAList, NULL, 0, VT);
440 // Legalized the chain result - switch anything that used the old chain to
442 ReplaceValueWith(SDOperand(N, 1), Tmp.getValue(1));
446 //===----------------------------------------------------------------------===//
447 // Integer Operand Promotion
448 //===----------------------------------------------------------------------===//
450 /// PromoteIntegerOperand - This method is called when the specified operand of
451 /// the specified node is found to need promotion. At this point, all of the
452 /// result types of the node are known to be legal, but other operands of the
453 /// node may need promotion or expansion as well as the specified one.
454 bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
455 DEBUG(cerr << "Promote integer operand: "; N->dump(&DAG); cerr << "\n");
457 switch (N->getOpcode()) {
460 cerr << "PromoteIntegerOperand Op #" << OpNo << ": ";
461 N->dump(&DAG); cerr << "\n";
463 assert(0 && "Do not know how to promote this operator's operand!");
466 case ISD::ANY_EXTEND: Res = PromoteIntOp_ANY_EXTEND(N); break;
467 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break;
468 case ISD::SIGN_EXTEND: Res = PromoteIntOp_SIGN_EXTEND(N); break;
469 case ISD::TRUNCATE: Res = PromoteIntOp_TRUNCATE(N); break;
470 case ISD::FP_EXTEND: Res = PromoteIntOp_FP_EXTEND(N); break;
471 case ISD::FP_ROUND: Res = PromoteIntOp_FP_ROUND(N); break;
472 case ISD::SINT_TO_FP:
473 case ISD::UINT_TO_FP: Res = PromoteIntOp_INT_TO_FP(N); break;
474 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break;
476 case ISD::BRCOND: Res = PromoteIntOp_BRCOND(N, OpNo); break;
477 case ISD::BR_CC: Res = PromoteIntOp_BR_CC(N, OpNo); break;
478 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
479 case ISD::SELECT_CC: Res = PromoteIntOp_SELECT_CC(N, OpNo); break;
480 case ISD::SETCC: Res = PromoteIntOp_SETCC(N, OpNo); break;
482 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
485 case ISD::BUILD_VECTOR: Res = PromoteIntOp_BUILD_VECTOR(N); break;
486 case ISD::INSERT_VECTOR_ELT:
487 Res = PromoteIntOp_INSERT_VECTOR_ELT(N, OpNo);
490 case ISD::MEMBARRIER: Res = PromoteIntOp_MEMBARRIER(N); break;
493 // If the result is null, the sub-method took care of registering results etc.
494 if (!Res.Val) return false;
495 // If the result is N, the sub-method updated N in place.
497 // Mark N as new and remark N and its operands. This allows us to correctly
498 // revisit N if it needs another step of promotion and allows us to visit
499 // any new operands to N.
504 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
505 "Invalid operand expansion");
507 ReplaceValueWith(SDOperand(N, 0), Res);
511 SDOperand DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
512 SDOperand Op = GetPromotedInteger(N->getOperand(0));
513 return DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
516 SDOperand DAGTypeLegalizer::PromoteIntOp_ZERO_EXTEND(SDNode *N) {
517 SDOperand Op = GetPromotedInteger(N->getOperand(0));
518 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
519 return DAG.getZeroExtendInReg(Op, N->getOperand(0).getValueType());
522 SDOperand DAGTypeLegalizer::PromoteIntOp_SIGN_EXTEND(SDNode *N) {
523 SDOperand Op = GetPromotedInteger(N->getOperand(0));
524 Op = DAG.getNode(ISD::ANY_EXTEND, N->getValueType(0), Op);
525 return DAG.getNode(ISD::SIGN_EXTEND_INREG, Op.getValueType(),
526 Op, DAG.getValueType(N->getOperand(0).getValueType()));
529 SDOperand DAGTypeLegalizer::PromoteIntOp_TRUNCATE(SDNode *N) {
530 SDOperand Op = GetPromotedInteger(N->getOperand(0));
531 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), Op);
534 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_EXTEND(SDNode *N) {
535 SDOperand Op = GetPromotedInteger(N->getOperand(0));
536 return DAG.getNode(ISD::FP_EXTEND, N->getValueType(0), Op);
539 SDOperand DAGTypeLegalizer::PromoteIntOp_FP_ROUND(SDNode *N) {
540 SDOperand Op = GetPromotedInteger(N->getOperand(0));
541 return DAG.getNode(ISD::FP_ROUND, N->getValueType(0), Op,
542 DAG.getIntPtrConstant(0));
545 SDOperand DAGTypeLegalizer::PromoteIntOp_INT_TO_FP(SDNode *N) {
546 SDOperand In = GetPromotedInteger(N->getOperand(0));
547 MVT OpVT = N->getOperand(0).getValueType();
548 if (N->getOpcode() == ISD::UINT_TO_FP)
549 In = DAG.getZeroExtendInReg(In, OpVT);
551 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(),
552 In, DAG.getValueType(OpVT));
554 return DAG.UpdateNodeOperands(SDOperand(N, 0), In);
557 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
558 // Since the result type is legal, the operands must promote to it.
559 MVT OVT = N->getOperand(0).getValueType();
560 SDOperand Lo = GetPromotedInteger(N->getOperand(0));
561 SDOperand Hi = GetPromotedInteger(N->getOperand(1));
562 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
564 Lo = DAG.getZeroExtendInReg(Lo, OVT);
565 Hi = DAG.getNode(ISD::SHL, N->getValueType(0), Hi,
566 DAG.getConstant(OVT.getSizeInBits(),
567 TLI.getShiftAmountTy()));
568 return DAG.getNode(ISD::OR, N->getValueType(0), Lo, Hi);
571 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
572 assert(OpNo == 0 && "Only know how to promote condition");
573 SDOperand Cond = GetPromotedInteger(N->getOperand(0)); // Promote condition.
575 // The top bits of the promoted condition are not necessarily zero, ensure
576 // that the value is properly zero extended.
577 unsigned BitWidth = Cond.getValueSizeInBits();
578 if (!DAG.MaskedValueIsZero(Cond,
579 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
580 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
582 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
583 return DAG.UpdateNodeOperands(SDOperand(N, 0), Cond, N->getOperand(1),
587 SDOperand DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) {
588 assert(OpNo == 1 && "only know how to promote condition");
589 SDOperand Cond = GetPromotedInteger(N->getOperand(1)); // Promote condition.
591 // The top bits of the promoted condition are not necessarily zero, ensure
592 // that the value is properly zero extended.
593 unsigned BitWidth = Cond.getValueSizeInBits();
594 if (!DAG.MaskedValueIsZero(Cond,
595 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
596 Cond = DAG.getZeroExtendInReg(Cond, MVT::i1);
598 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
599 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0), Cond,
603 SDOperand DAGTypeLegalizer::PromoteIntOp_BR_CC(SDNode *N, unsigned OpNo) {
604 assert(OpNo == 2 && "Don't know how to promote this operand!");
606 SDOperand LHS = N->getOperand(2);
607 SDOperand RHS = N->getOperand(3);
608 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(1))->get());
610 // The chain (Op#0), CC (#1) and basic block destination (Op#4) are always
612 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
613 N->getOperand(1), LHS, RHS, N->getOperand(4));
616 SDOperand DAGTypeLegalizer::PromoteIntOp_SELECT_CC(SDNode *N, unsigned OpNo) {
617 assert(OpNo == 0 && "Don't know how to promote this operand!");
619 SDOperand LHS = N->getOperand(0);
620 SDOperand RHS = N->getOperand(1);
621 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(4))->get());
623 // The CC (#4) and the possible return values (#2 and #3) have legal types.
624 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2),
625 N->getOperand(3), N->getOperand(4));
628 SDOperand DAGTypeLegalizer::PromoteIntOp_SETCC(SDNode *N, unsigned OpNo) {
629 assert(OpNo == 0 && "Don't know how to promote this operand!");
631 SDOperand LHS = N->getOperand(0);
632 SDOperand RHS = N->getOperand(1);
633 PromoteSetCCOperands(LHS, RHS, cast<CondCodeSDNode>(N->getOperand(2))->get());
635 // The CC (#2) is always legal.
636 return DAG.UpdateNodeOperands(SDOperand(N, 0), LHS, RHS, N->getOperand(2));
639 /// PromoteSetCCOperands - Promote the operands of a comparison. This code is
640 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
641 void DAGTypeLegalizer::PromoteSetCCOperands(SDOperand &NewLHS,SDOperand &NewRHS,
642 ISD::CondCode CCCode) {
643 MVT VT = NewLHS.getValueType();
645 // Get the promoted values.
646 NewLHS = GetPromotedInteger(NewLHS);
647 NewRHS = GetPromotedInteger(NewRHS);
649 // Otherwise, we have to insert explicit sign or zero extends. Note
650 // that we could insert sign extends for ALL conditions, but zero extend
651 // is cheaper on many machines (an AND instead of two shifts), so prefer
654 default: assert(0 && "Unknown integer comparison!");
661 // ALL of these operations will work if we either sign or zero extend
662 // the operands (including the unsigned comparisons!). Zero extend is
663 // usually a simpler/cheaper operation, so prefer it.
664 NewLHS = DAG.getZeroExtendInReg(NewLHS, VT);
665 NewRHS = DAG.getZeroExtendInReg(NewRHS, VT);
671 NewLHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewLHS.getValueType(), NewLHS,
672 DAG.getValueType(VT));
673 NewRHS = DAG.getNode(ISD::SIGN_EXTEND_INREG, NewRHS.getValueType(), NewRHS,
674 DAG.getValueType(VT));
679 SDOperand DAGTypeLegalizer::PromoteIntOp_STORE(StoreSDNode *N, unsigned OpNo){
680 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
681 SDOperand Ch = N->getChain(), Ptr = N->getBasePtr();
682 int SVOffset = N->getSrcValueOffset();
683 unsigned Alignment = N->getAlignment();
684 bool isVolatile = N->isVolatile();
686 SDOperand Val = GetPromotedInteger(N->getValue()); // Get promoted value.
688 assert(!N->isTruncatingStore() && "Cannot promote this store operand!");
690 // Truncate the value and store the result.
691 return DAG.getTruncStore(Ch, Val, Ptr, N->getSrcValue(),
692 SVOffset, N->getMemoryVT(),
693 isVolatile, Alignment);
696 SDOperand DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) {
697 // The vector type is legal but the element type is not. This implies
698 // that the vector is a power-of-two in length and that the element
699 // type does not have a strange size (eg: it is not i1).
700 MVT VecVT = N->getValueType(0);
701 unsigned NumElts = VecVT.getVectorNumElements();
702 assert(!(NumElts & 1) && "Legal vector of one illegal element?");
704 // Build a vector of half the length out of elements of twice the bitwidth.
705 // For example <4 x i16> -> <2 x i32>.
706 MVT OldVT = N->getOperand(0).getValueType();
707 MVT NewVT = MVT::getIntegerVT(2 * OldVT.getSizeInBits());
708 assert(OldVT.isSimple() && NewVT.isSimple());
710 std::vector<SDOperand> NewElts;
711 NewElts.reserve(NumElts/2);
713 for (unsigned i = 0; i < NumElts; i += 2) {
714 // Combine two successive elements into one promoted element.
715 SDOperand Lo = N->getOperand(i);
716 SDOperand Hi = N->getOperand(i+1);
717 if (TLI.isBigEndian())
719 NewElts.push_back(JoinIntegers(Lo, Hi));
722 SDOperand NewVec = DAG.getNode(ISD::BUILD_VECTOR,
723 MVT::getVectorVT(NewVT, NewElts.size()),
724 &NewElts[0], NewElts.size());
726 // Convert the new vector to the old vector type.
727 return DAG.getNode(ISD::BIT_CONVERT, VecVT, NewVec);
730 SDOperand DAGTypeLegalizer::PromoteIntOp_INSERT_VECTOR_ELT(SDNode *N,
733 // Promote the inserted value. This is valid because the type does not
734 // have to match the vector element type.
736 // Check that any extra bits introduced will be truncated away.
737 assert(N->getOperand(1).getValueType().getSizeInBits() >=
738 N->getValueType(0).getVectorElementType().getSizeInBits() &&
739 "Type of inserted value narrower than vector element type!");
740 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
741 GetPromotedInteger(N->getOperand(1)),
745 assert(OpNo == 2 && "Different operand and result vector types?");
747 // Promote the index.
748 SDOperand Idx = N->getOperand(2);
749 Idx = DAG.getZeroExtendInReg(GetPromotedInteger(Idx), Idx.getValueType());
750 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
751 N->getOperand(1), Idx);
754 SDOperand DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) {
756 NewOps[0] = N->getOperand(0);
757 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
758 SDOperand Flag = GetPromotedInteger(N->getOperand(i));
759 NewOps[i] = DAG.getZeroExtendInReg(Flag, MVT::i1);
761 return DAG.UpdateNodeOperands(SDOperand (N, 0), NewOps,
762 array_lengthof(NewOps));
766 //===----------------------------------------------------------------------===//
767 // Integer Result Expansion
768 //===----------------------------------------------------------------------===//
770 /// ExpandIntegerResult - This method is called when the specified result of the
771 /// specified node is found to need expansion. At this point, the node may also
772 /// have invalid operands or may have other results that need promotion, we just
773 /// know that (at least) one result needs expansion.
774 void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
775 DEBUG(cerr << "Expand integer result: "; N->dump(&DAG); cerr << "\n");
777 Lo = Hi = SDOperand();
779 // See if the target wants to custom expand this node.
780 if (TLI.getOperationAction(N->getOpcode(), N->getValueType(0)) ==
781 TargetLowering::Custom) {
782 // If the target wants to, allow it to lower this itself.
783 if (SDNode *P = TLI.ExpandOperationResult(N, DAG)) {
784 // Everything that once used N now uses P. We are guaranteed that the
785 // result value types of N and the result value types of P match.
786 ReplaceNodeWith(N, P);
791 switch (N->getOpcode()) {
794 cerr << "ExpandIntegerResult #" << ResNo << ": ";
795 N->dump(&DAG); cerr << "\n";
797 assert(0 && "Do not know how to expand the result of this operator!");
800 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, Lo, Hi); break;
801 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
802 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break;
803 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
805 case ISD::BIT_CONVERT: ExpandRes_BIT_CONVERT(N, Lo, Hi); break;
806 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break;
807 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break;
808 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break;
810 case ISD::Constant: ExpandIntRes_Constant(N, Lo, Hi); break;
811 case ISD::ANY_EXTEND: ExpandIntRes_ANY_EXTEND(N, Lo, Hi); break;
812 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break;
813 case ISD::SIGN_EXTEND: ExpandIntRes_SIGN_EXTEND(N, Lo, Hi); break;
814 case ISD::AssertZext: ExpandIntRes_AssertZext(N, Lo, Hi); break;
815 case ISD::TRUNCATE: ExpandIntRes_TRUNCATE(N, Lo, Hi); break;
816 case ISD::SIGN_EXTEND_INREG: ExpandIntRes_SIGN_EXTEND_INREG(N, Lo, Hi); break;
817 case ISD::FP_TO_SINT: ExpandIntRes_FP_TO_SINT(N, Lo, Hi); break;
818 case ISD::FP_TO_UINT: ExpandIntRes_FP_TO_UINT(N, Lo, Hi); break;
819 case ISD::LOAD: ExpandIntRes_LOAD(cast<LoadSDNode>(N), Lo, Hi); break;
823 case ISD::XOR: ExpandIntRes_Logical(N, Lo, Hi); break;
824 case ISD::BSWAP: ExpandIntRes_BSWAP(N, Lo, Hi); break;
826 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break;
828 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
830 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
831 case ISD::MUL: ExpandIntRes_MUL(N, Lo, Hi); break;
832 case ISD::SDIV: ExpandIntRes_SDIV(N, Lo, Hi); break;
833 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
834 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break;
835 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
838 case ISD::SRL: ExpandIntRes_Shift(N, Lo, Hi); break;
840 case ISD::CTLZ: ExpandIntRes_CTLZ(N, Lo, Hi); break;
841 case ISD::CTPOP: ExpandIntRes_CTPOP(N, Lo, Hi); break;
842 case ISD::CTTZ: ExpandIntRes_CTTZ(N, Lo, Hi); break;
845 // If Lo/Hi is null, the sub-method took care of registering results etc.
847 SetExpandedInteger(SDOperand(N, ResNo), Lo, Hi);
850 void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
851 SDOperand &Lo, SDOperand &Hi) {
852 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
853 unsigned NBitWidth = NVT.getSizeInBits();
854 const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
855 Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
856 Hi = DAG.getConstant(Cst.lshr(NBitWidth).trunc(NBitWidth), NVT);
859 void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
860 SDOperand &Lo, SDOperand &Hi) {
861 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
862 SDOperand Op = N->getOperand(0);
863 if (Op.getValueType().bitsLE(NVT)) {
864 // The low part is any extension of the input (which degenerates to a copy).
865 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Op);
866 Hi = DAG.getNode(ISD::UNDEF, NVT); // The high part is undefined.
868 // For example, extension of an i48 to an i64. The operand type necessarily
869 // promotes to the result type, so will end up being expanded too.
870 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
871 "Only know how to promote this result!");
872 SDOperand Res = GetPromotedInteger(Op);
873 assert(Res.getValueType() == N->getValueType(0) &&
874 "Operand over promoted?");
875 // Split the promoted operand. This will simplify when it is expanded.
876 SplitInteger(Res, Lo, Hi);
880 void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
881 SDOperand &Lo, SDOperand &Hi) {
882 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
883 SDOperand Op = N->getOperand(0);
884 if (Op.getValueType().bitsLE(NVT)) {
885 // The low part is zero extension of the input (which degenerates to a copy).
886 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, N->getOperand(0));
887 Hi = DAG.getConstant(0, NVT); // The high part is just a zero.
889 // For example, extension of an i48 to an i64. The operand type necessarily
890 // promotes to the result type, so will end up being expanded too.
891 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
892 "Only know how to promote this result!");
893 SDOperand Res = GetPromotedInteger(Op);
894 assert(Res.getValueType() == N->getValueType(0) &&
895 "Operand over promoted?");
896 // Split the promoted operand. This will simplify when it is expanded.
897 SplitInteger(Res, Lo, Hi);
898 unsigned ExcessBits =
899 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
900 Hi = DAG.getZeroExtendInReg(Hi, MVT::getIntegerVT(ExcessBits));
904 void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
905 SDOperand &Lo, SDOperand &Hi) {
906 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
907 SDOperand Op = N->getOperand(0);
908 if (Op.getValueType().bitsLE(NVT)) {
909 // The low part is sign extension of the input (which degenerates to a copy).
910 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, N->getOperand(0));
911 // The high part is obtained by SRA'ing all but one of the bits of low part.
912 unsigned LoSize = NVT.getSizeInBits();
913 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
914 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
916 // For example, extension of an i48 to an i64. The operand type necessarily
917 // promotes to the result type, so will end up being expanded too.
918 assert(getTypeAction(Op.getValueType()) == PromoteInteger &&
919 "Only know how to promote this result!");
920 SDOperand Res = GetPromotedInteger(Op);
921 assert(Res.getValueType() == N->getValueType(0) &&
922 "Operand over promoted?");
923 // Split the promoted operand. This will simplify when it is expanded.
924 SplitInteger(Res, Lo, Hi);
925 unsigned ExcessBits =
926 Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
927 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
928 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
932 void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N,
933 SDOperand &Lo, SDOperand &Hi) {
934 GetExpandedInteger(N->getOperand(0), Lo, Hi);
935 MVT NVT = Lo.getValueType();
936 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
937 unsigned NVTBits = NVT.getSizeInBits();
938 unsigned EVTBits = EVT.getSizeInBits();
940 if (NVTBits < EVTBits) {
941 Hi = DAG.getNode(ISD::AssertZext, NVT, Hi,
942 DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
944 Lo = DAG.getNode(ISD::AssertZext, NVT, Lo, DAG.getValueType(EVT));
945 // The high part must be zero, make it explicit.
946 Hi = DAG.getConstant(0, NVT);
950 void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
951 SDOperand &Lo, SDOperand &Hi) {
952 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
953 Lo = DAG.getNode(ISD::TRUNCATE, NVT, N->getOperand(0));
954 Hi = DAG.getNode(ISD::SRL, N->getOperand(0).getValueType(), N->getOperand(0),
955 DAG.getConstant(NVT.getSizeInBits(),
956 TLI.getShiftAmountTy()));
957 Hi = DAG.getNode(ISD::TRUNCATE, NVT, Hi);
960 void DAGTypeLegalizer::
961 ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
962 GetExpandedInteger(N->getOperand(0), Lo, Hi);
963 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
965 if (EVT.bitsLE(Lo.getValueType())) {
966 // sext_inreg the low part if needed.
967 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, Lo.getValueType(), Lo,
970 // The high part gets the sign extension from the lo-part. This handles
971 // things like sextinreg V:i64 from i8.
972 Hi = DAG.getNode(ISD::SRA, Hi.getValueType(), Lo,
973 DAG.getConstant(Hi.getValueType().getSizeInBits()-1,
974 TLI.getShiftAmountTy()));
976 // For example, extension of an i48 to an i64. Leave the low part alone,
977 // sext_inreg the high part.
978 unsigned ExcessBits =
979 EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
980 Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, Hi.getValueType(), Hi,
981 DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
985 void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDOperand &Lo,
987 MVT VT = N->getValueType(0);
988 SDOperand Op = N->getOperand(0);
989 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
990 if (VT == MVT::i64) {
991 if (Op.getValueType() == MVT::f32)
992 LC = RTLIB::FPTOSINT_F32_I64;
993 else if (Op.getValueType() == MVT::f64)
994 LC = RTLIB::FPTOSINT_F64_I64;
995 else if (Op.getValueType() == MVT::f80)
996 LC = RTLIB::FPTOSINT_F80_I64;
997 else if (Op.getValueType() == MVT::ppcf128)
998 LC = RTLIB::FPTOSINT_PPCF128_I64;
999 } else if (VT == MVT::i128) {
1000 if (Op.getValueType() == MVT::f32)
1001 LC = RTLIB::FPTOSINT_F32_I128;
1002 else if (Op.getValueType() == MVT::f64)
1003 LC = RTLIB::FPTOSINT_F64_I128;
1004 else if (Op.getValueType() == MVT::f80)
1005 LC = RTLIB::FPTOSINT_F80_I128;
1006 else if (Op.getValueType() == MVT::ppcf128)
1007 LC = RTLIB::FPTOSINT_PPCF128_I128;
1009 assert(0 && "Unexpected fp-to-sint conversion!");
1011 SplitInteger(MakeLibCall(LC, VT, &Op, 1, true/*sign irrelevant*/), Lo, Hi);
1014 void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDOperand &Lo,
1016 MVT VT = N->getValueType(0);
1017 SDOperand Op = N->getOperand(0);
1018 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1019 if (VT == MVT::i64) {
1020 if (Op.getValueType() == MVT::f32)
1021 LC = RTLIB::FPTOUINT_F32_I64;
1022 else if (Op.getValueType() == MVT::f64)
1023 LC = RTLIB::FPTOUINT_F64_I64;
1024 else if (Op.getValueType() == MVT::f80)
1025 LC = RTLIB::FPTOUINT_F80_I64;
1026 else if (Op.getValueType() == MVT::ppcf128)
1027 LC = RTLIB::FPTOUINT_PPCF128_I64;
1028 } else if (VT == MVT::i128) {
1029 if (Op.getValueType() == MVT::f32)
1030 LC = RTLIB::FPTOUINT_F32_I128;
1031 else if (Op.getValueType() == MVT::f64)
1032 LC = RTLIB::FPTOUINT_F64_I128;
1033 else if (Op.getValueType() == MVT::f80)
1034 LC = RTLIB::FPTOUINT_F80_I128;
1035 else if (Op.getValueType() == MVT::ppcf128)
1036 LC = RTLIB::FPTOUINT_PPCF128_I128;
1038 assert(0 && "Unexpected fp-to-uint conversion!");
1040 SplitInteger(MakeLibCall(LC, VT, &Op, 1, false/*sign irrelevant*/), Lo, Hi);
1043 void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N,
1044 SDOperand &Lo, SDOperand &Hi) {
1045 if (ISD::isNormalLoad(N)) {
1046 ExpandRes_NormalLoad(N, Lo, Hi);
1050 assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
1052 MVT VT = N->getValueType(0);
1053 MVT NVT = TLI.getTypeToTransformTo(VT);
1054 SDOperand Ch = N->getChain(); // Legalize the chain.
1055 SDOperand Ptr = N->getBasePtr(); // Legalize the pointer.
1056 ISD::LoadExtType ExtType = N->getExtensionType();
1057 int SVOffset = N->getSrcValueOffset();
1058 unsigned Alignment = N->getAlignment();
1059 bool isVolatile = N->isVolatile();
1061 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1063 if (N->getMemoryVT().bitsLE(NVT)) {
1064 MVT EVT = N->getMemoryVT();
1066 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT,
1067 isVolatile, Alignment);
1069 // Remember the chain.
1070 Ch = Lo.getValue(1);
1072 if (ExtType == ISD::SEXTLOAD) {
1073 // The high part is obtained by SRA'ing all but one of the bits of the
1075 unsigned LoSize = Lo.getValueType().getSizeInBits();
1076 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
1077 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
1078 } else if (ExtType == ISD::ZEXTLOAD) {
1079 // The high part is just a zero.
1080 Hi = DAG.getConstant(0, NVT);
1082 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1083 // The high part is undefined.
1084 Hi = DAG.getNode(ISD::UNDEF, NVT);
1086 } else if (TLI.isLittleEndian()) {
1087 // Little-endian - low bits are at low addresses.
1088 Lo = DAG.getLoad(NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1089 isVolatile, Alignment);
1091 unsigned ExcessBits =
1092 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1093 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1095 // Increment the pointer to the other half.
1096 unsigned IncrementSize = NVT.getSizeInBits()/8;
1097 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1098 DAG.getIntPtrConstant(IncrementSize));
1099 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(),
1100 SVOffset+IncrementSize, NEVT,
1101 isVolatile, MinAlign(Alignment, IncrementSize));
1103 // Build a factor node to remember that this load is independent of the
1105 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1108 // Big-endian - high bits are at low addresses. Favor aligned loads at
1109 // the cost of some bit-fiddling.
1110 MVT EVT = N->getMemoryVT();
1111 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1112 unsigned IncrementSize = NVT.getSizeInBits()/8;
1113 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1115 // Load both the high bits and maybe some of the low bits.
1116 Hi = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
1117 MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
1118 isVolatile, Alignment);
1120 // Increment the pointer to the other half.
1121 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1122 DAG.getIntPtrConstant(IncrementSize));
1123 // Load the rest of the low bits.
1124 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Ch, Ptr, N->getSrcValue(),
1125 SVOffset+IncrementSize,
1126 MVT::getIntegerVT(ExcessBits),
1127 isVolatile, MinAlign(Alignment, IncrementSize));
1129 // Build a factor node to remember that this load is independent of the
1131 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
1134 if (ExcessBits < NVT.getSizeInBits()) {
1135 // Transfer low bits from the bottom of Hi to the top of Lo.
1136 Lo = DAG.getNode(ISD::OR, NVT, Lo,
1137 DAG.getNode(ISD::SHL, NVT, Hi,
1138 DAG.getConstant(ExcessBits,
1139 TLI.getShiftAmountTy())));
1140 // Move high bits to the right position in Hi.
1141 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, NVT, Hi,
1142 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1143 TLI.getShiftAmountTy()));
1147 // Legalized the chain result - switch anything that used the old chain to
1149 ReplaceValueWith(SDOperand(N, 1), Ch);
1152 void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N,
1153 SDOperand &Lo, SDOperand &Hi) {
1154 SDOperand LL, LH, RL, RH;
1155 GetExpandedInteger(N->getOperand(0), LL, LH);
1156 GetExpandedInteger(N->getOperand(1), RL, RH);
1157 Lo = DAG.getNode(N->getOpcode(), LL.getValueType(), LL, RL);
1158 Hi = DAG.getNode(N->getOpcode(), LL.getValueType(), LH, RH);
1161 void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N,
1162 SDOperand &Lo, SDOperand &Hi) {
1163 GetExpandedInteger(N->getOperand(0), Hi, Lo); // Note swapped operands.
1164 Lo = DAG.getNode(ISD::BSWAP, Lo.getValueType(), Lo);
1165 Hi = DAG.getNode(ISD::BSWAP, Hi.getValueType(), Hi);
1168 void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N,
1169 SDOperand &Lo, SDOperand &Hi) {
1170 // Expand the subcomponents.
1171 SDOperand LHSL, LHSH, RHSL, RHSH;
1172 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1173 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1174 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1175 SDOperand LoOps[2] = { LHSL, RHSL };
1176 SDOperand HiOps[3] = { LHSH, RHSH };
1178 if (N->getOpcode() == ISD::ADD) {
1179 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1180 HiOps[2] = Lo.getValue(1);
1181 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1183 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1184 HiOps[2] = Lo.getValue(1);
1185 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1189 void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N,
1190 SDOperand &Lo, SDOperand &Hi) {
1191 // Expand the subcomponents.
1192 SDOperand LHSL, LHSH, RHSL, RHSH;
1193 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1194 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1195 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1196 SDOperand LoOps[2] = { LHSL, RHSL };
1197 SDOperand HiOps[3] = { LHSH, RHSH };
1199 if (N->getOpcode() == ISD::ADDC) {
1200 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
1201 HiOps[2] = Lo.getValue(1);
1202 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
1204 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
1205 HiOps[2] = Lo.getValue(1);
1206 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
1209 // Legalized the flag result - switch anything that used the old flag to
1211 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1214 void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N,
1215 SDOperand &Lo, SDOperand &Hi) {
1216 // Expand the subcomponents.
1217 SDOperand LHSL, LHSH, RHSL, RHSH;
1218 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1219 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1220 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
1221 SDOperand LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
1222 SDOperand HiOps[3] = { LHSH, RHSH };
1224 Lo = DAG.getNode(N->getOpcode(), VTList, LoOps, 3);
1225 HiOps[2] = Lo.getValue(1);
1226 Hi = DAG.getNode(N->getOpcode(), VTList, HiOps, 3);
1228 // Legalized the flag result - switch anything that used the old flag to
1230 ReplaceValueWith(SDOperand(N, 1), Hi.getValue(1));
1233 void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
1234 SDOperand &Lo, SDOperand &Hi) {
1235 MVT VT = N->getValueType(0);
1236 MVT NVT = TLI.getTypeToTransformTo(VT);
1238 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
1239 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
1240 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
1241 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
1242 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
1243 SDOperand LL, LH, RL, RH;
1244 GetExpandedInteger(N->getOperand(0), LL, LH);
1245 GetExpandedInteger(N->getOperand(1), RL, RH);
1246 unsigned OuterBitSize = VT.getSizeInBits();
1247 unsigned InnerBitSize = NVT.getSizeInBits();
1248 unsigned LHSSB = DAG.ComputeNumSignBits(N->getOperand(0));
1249 unsigned RHSSB = DAG.ComputeNumSignBits(N->getOperand(1));
1251 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
1252 if (DAG.MaskedValueIsZero(N->getOperand(0), HighMask) &&
1253 DAG.MaskedValueIsZero(N->getOperand(1), HighMask)) {
1254 // The inputs are both zero-extended.
1256 // We can emit a umul_lohi.
1257 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1258 Hi = SDOperand(Lo.Val, 1);
1262 // We can emit a mulhu+mul.
1263 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1264 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1268 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
1269 // The input values are both sign-extended.
1271 // We can emit a smul_lohi.
1272 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
1273 Hi = SDOperand(Lo.Val, 1);
1277 // We can emit a mulhs+mul.
1278 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1279 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
1284 // Lo,Hi = umul LHS, RHS.
1285 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
1286 DAG.getVTList(NVT, NVT), LL, RL);
1288 Hi = UMulLOHI.getValue(1);
1289 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1290 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1291 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1292 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1296 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
1297 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
1298 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
1299 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
1300 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
1301 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
1306 // If nothing else, we can make a libcall.
1308 switch (VT.getSimpleVT()) {
1310 assert(false && "Unsupported MUL!");
1312 LC = RTLIB::MUL_I64;
1316 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1317 SplitInteger(MakeLibCall(LC, VT, Ops, 2, true/*sign irrelevant*/), Lo, Hi);
1320 void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
1321 SDOperand &Lo, SDOperand &Hi) {
1322 assert(N->getValueType(0) == MVT::i64 && "Unsupported sdiv!");
1323 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1324 SplitInteger(MakeLibCall(RTLIB::SDIV_I64, N->getValueType(0), Ops, 2, true),
1328 void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
1329 SDOperand &Lo, SDOperand &Hi) {
1330 assert(N->getValueType(0) == MVT::i64 && "Unsupported srem!");
1331 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1332 SplitInteger(MakeLibCall(RTLIB::SREM_I64, N->getValueType(0), Ops, 2, true),
1336 void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
1337 SDOperand &Lo, SDOperand &Hi) {
1338 assert(N->getValueType(0) == MVT::i64 && "Unsupported udiv!");
1339 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1340 SplitInteger(MakeLibCall(RTLIB::UDIV_I64, N->getValueType(0), Ops, 2, false),
1344 void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
1345 SDOperand &Lo, SDOperand &Hi) {
1346 assert(N->getValueType(0) == MVT::i64 && "Unsupported urem!");
1347 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1348 SplitInteger(MakeLibCall(RTLIB::UREM_I64, N->getValueType(0), Ops, 2, false),
1352 void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
1353 SDOperand &Lo, SDOperand &Hi) {
1354 MVT VT = N->getValueType(0);
1356 // If we can emit an efficient shift operation, do so now. Check to see if
1357 // the RHS is a constant.
1358 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1359 return ExpandShiftByConstant(N, CN->getValue(), Lo, Hi);
1361 // If we can determine that the high bit of the shift is zero or one, even if
1362 // the low bits are variable, emit this shift in an optimized form.
1363 if (ExpandShiftWithKnownAmountBit(N, Lo, Hi))
1366 // If this target supports shift_PARTS, use it. First, map to the _PARTS opc.
1368 if (N->getOpcode() == ISD::SHL) {
1369 PartsOpc = ISD::SHL_PARTS;
1370 } else if (N->getOpcode() == ISD::SRL) {
1371 PartsOpc = ISD::SRL_PARTS;
1373 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1374 PartsOpc = ISD::SRA_PARTS;
1377 // Next check to see if the target supports this SHL_PARTS operation or if it
1378 // will custom expand it.
1379 MVT NVT = TLI.getTypeToTransformTo(VT);
1380 TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
1381 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
1382 Action == TargetLowering::Custom) {
1383 // Expand the subcomponents.
1384 SDOperand LHSL, LHSH;
1385 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
1387 SDOperand Ops[] = { LHSL, LHSH, N->getOperand(1) };
1388 MVT VT = LHSL.getValueType();
1389 Lo = DAG.getNode(PartsOpc, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
1390 Hi = Lo.getValue(1);
1394 // Otherwise, emit a libcall.
1395 assert(VT == MVT::i64 && "Unsupported shift!");
1399 if (N->getOpcode() == ISD::SHL) {
1400 LC = RTLIB::SHL_I64;
1401 isSigned = false; /*sign irrelevant*/
1402 } else if (N->getOpcode() == ISD::SRL) {
1403 LC = RTLIB::SRL_I64;
1406 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1407 LC = RTLIB::SRA_I64;
1411 SDOperand Ops[2] = { N->getOperand(0), N->getOperand(1) };
1412 SplitInteger(MakeLibCall(LC, VT, Ops, 2, isSigned), Lo, Hi);
1415 void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
1416 SDOperand &Lo, SDOperand &Hi) {
1417 // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
1418 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1419 MVT NVT = Lo.getValueType();
1421 SDOperand HiNotZero = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1422 DAG.getConstant(0, NVT), ISD::SETNE);
1424 SDOperand LoLZ = DAG.getNode(ISD::CTLZ, NVT, Lo);
1425 SDOperand HiLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
1427 Lo = DAG.getNode(ISD::SELECT, NVT, HiNotZero, HiLZ,
1428 DAG.getNode(ISD::ADD, NVT, LoLZ,
1429 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1430 Hi = DAG.getConstant(0, NVT);
1433 void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
1434 SDOperand &Lo, SDOperand &Hi) {
1435 // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
1436 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1437 MVT NVT = Lo.getValueType();
1438 Lo = DAG.getNode(ISD::ADD, NVT, DAG.getNode(ISD::CTPOP, NVT, Lo),
1439 DAG.getNode(ISD::CTPOP, NVT, Hi));
1440 Hi = DAG.getConstant(0, NVT);
1443 void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
1444 SDOperand &Lo, SDOperand &Hi) {
1445 // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
1446 GetExpandedInteger(N->getOperand(0), Lo, Hi);
1447 MVT NVT = Lo.getValueType();
1449 SDOperand LoNotZero = DAG.getSetCC(TLI.getSetCCResultType(Lo), Lo,
1450 DAG.getConstant(0, NVT), ISD::SETNE);
1452 SDOperand LoLZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
1453 SDOperand HiLZ = DAG.getNode(ISD::CTTZ, NVT, Hi);
1455 Lo = DAG.getNode(ISD::SELECT, NVT, LoNotZero, LoLZ,
1456 DAG.getNode(ISD::ADD, NVT, HiLZ,
1457 DAG.getConstant(NVT.getSizeInBits(), NVT)));
1458 Hi = DAG.getConstant(0, NVT);
1461 /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded,
1462 /// and the shift amount is a constant 'Amt'. Expand the operation.
1463 void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
1464 SDOperand &Lo, SDOperand &Hi) {
1465 // Expand the incoming operand to be shifted, so that we have its parts
1467 GetExpandedInteger(N->getOperand(0), InL, InH);
1469 MVT NVT = InL.getValueType();
1470 unsigned VTBits = N->getValueType(0).getSizeInBits();
1471 unsigned NVTBits = NVT.getSizeInBits();
1472 MVT ShTy = N->getOperand(1).getValueType();
1474 if (N->getOpcode() == ISD::SHL) {
1476 Lo = Hi = DAG.getConstant(0, NVT);
1477 } else if (Amt > NVTBits) {
1478 Lo = DAG.getConstant(0, NVT);
1479 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt-NVTBits,ShTy));
1480 } else if (Amt == NVTBits) {
1481 Lo = DAG.getConstant(0, NVT);
1484 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Amt, ShTy));
1485 Hi = DAG.getNode(ISD::OR, NVT,
1486 DAG.getNode(ISD::SHL, NVT, InH,
1487 DAG.getConstant(Amt, ShTy)),
1488 DAG.getNode(ISD::SRL, NVT, InL,
1489 DAG.getConstant(NVTBits-Amt, ShTy)));
1494 if (N->getOpcode() == ISD::SRL) {
1496 Lo = DAG.getConstant(0, NVT);
1497 Hi = DAG.getConstant(0, NVT);
1498 } else if (Amt > NVTBits) {
1499 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt-NVTBits,ShTy));
1500 Hi = DAG.getConstant(0, NVT);
1501 } else if (Amt == NVTBits) {
1503 Hi = DAG.getConstant(0, NVT);
1505 Lo = DAG.getNode(ISD::OR, NVT,
1506 DAG.getNode(ISD::SRL, NVT, InL,
1507 DAG.getConstant(Amt, ShTy)),
1508 DAG.getNode(ISD::SHL, NVT, InH,
1509 DAG.getConstant(NVTBits-Amt, ShTy)));
1510 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Amt, ShTy));
1515 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1517 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1518 DAG.getConstant(NVTBits-1, ShTy));
1519 } else if (Amt > NVTBits) {
1520 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1521 DAG.getConstant(Amt-NVTBits, ShTy));
1522 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1523 DAG.getConstant(NVTBits-1, ShTy));
1524 } else if (Amt == NVTBits) {
1526 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1527 DAG.getConstant(NVTBits-1, ShTy));
1529 Lo = DAG.getNode(ISD::OR, NVT,
1530 DAG.getNode(ISD::SRL, NVT, InL,
1531 DAG.getConstant(Amt, ShTy)),
1532 DAG.getNode(ISD::SHL, NVT, InH,
1533 DAG.getConstant(NVTBits-Amt, ShTy)));
1534 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Amt, ShTy));
1538 /// ExpandShiftWithKnownAmountBit - Try to determine whether we can simplify
1539 /// this shift based on knowledge of the high bit of the shift amount. If we
1540 /// can tell this, we know that it is >= 32 or < 32, without knowing the actual
1542 bool DAGTypeLegalizer::
1543 ExpandShiftWithKnownAmountBit(SDNode *N, SDOperand &Lo, SDOperand &Hi) {
1544 SDOperand Amt = N->getOperand(1);
1545 MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
1546 MVT ShTy = Amt.getValueType();
1547 unsigned ShBits = ShTy.getSizeInBits();
1548 unsigned NVTBits = NVT.getSizeInBits();
1549 assert(isPowerOf2_32(NVTBits) &&
1550 "Expanded integer type size not a power of two!");
1552 APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
1553 APInt KnownZero, KnownOne;
1554 DAG.ComputeMaskedBits(N->getOperand(1), HighBitMask, KnownZero, KnownOne);
1556 // If we don't know anything about the high bits, exit.
1557 if (((KnownZero|KnownOne) & HighBitMask) == 0)
1560 // Get the incoming operand to be shifted.
1562 GetExpandedInteger(N->getOperand(0), InL, InH);
1564 // If we know that any of the high bits of the shift amount are one, then we
1565 // can do this as a couple of simple shifts.
1566 if (KnownOne.intersects(HighBitMask)) {
1567 // Mask out the high bit, which we know is set.
1568 Amt = DAG.getNode(ISD::AND, ShTy, Amt,
1569 DAG.getConstant(~HighBitMask, ShTy));
1571 switch (N->getOpcode()) {
1572 default: assert(0 && "Unknown shift");
1574 Lo = DAG.getConstant(0, NVT); // Low part is zero.
1575 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
1578 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
1579 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
1582 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
1583 DAG.getConstant(NVTBits-1, ShTy));
1584 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
1589 // If we know that all of the high bits of the shift amount are zero, then we
1590 // can do this as a couple of simple shifts.
1591 if ((KnownZero & HighBitMask) == HighBitMask) {
1593 SDOperand Amt2 = DAG.getNode(ISD::SUB, ShTy,
1594 DAG.getConstant(NVTBits, ShTy),
1597 switch (N->getOpcode()) {
1598 default: assert(0 && "Unknown shift");
1599 case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break;
1601 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1604 Lo = DAG.getNode(N->getOpcode(), NVT, InL, Amt);
1605 Hi = DAG.getNode(ISD::OR, NVT,
1606 DAG.getNode(Op1, NVT, InH, Amt),
1607 DAG.getNode(Op2, NVT, InL, Amt2));
1615 //===----------------------------------------------------------------------===//
1616 // Integer Operand Expansion
1617 //===----------------------------------------------------------------------===//
1619 /// ExpandIntegerOperand - This method is called when the specified operand of
1620 /// the specified node is found to need expansion. At this point, all of the
1621 /// result types of the node are known to be legal, but other operands of the
1622 /// node may need promotion or expansion as well as the specified one.
1623 bool DAGTypeLegalizer::ExpandIntegerOperand(SDNode *N, unsigned OpNo) {
1624 DEBUG(cerr << "Expand integer operand: "; N->dump(&DAG); cerr << "\n");
1625 SDOperand Res(0, 0);
1627 if (TLI.getOperationAction(N->getOpcode(), N->getOperand(OpNo).getValueType())
1628 == TargetLowering::Custom)
1629 Res = TLI.LowerOperation(SDOperand(N, 0), DAG);
1632 switch (N->getOpcode()) {
1635 cerr << "ExpandIntegerOperand Op #" << OpNo << ": ";
1636 N->dump(&DAG); cerr << "\n";
1638 assert(0 && "Do not know how to expand this operator's operand!");
1641 case ISD::BUILD_VECTOR: Res = ExpandOp_BUILD_VECTOR(N); break;
1642 case ISD::BIT_CONVERT: Res = ExpandOp_BIT_CONVERT(N); break;
1643 case ISD::EXTRACT_ELEMENT: Res = ExpandOp_EXTRACT_ELEMENT(N); break;
1645 case ISD::TRUNCATE: Res = ExpandIntOp_TRUNCATE(N); break;
1647 case ISD::SINT_TO_FP:
1648 Res = ExpandIntOp_SINT_TO_FP(N->getOperand(0), N->getValueType(0));
1650 case ISD::UINT_TO_FP:
1651 Res = ExpandIntOp_UINT_TO_FP(N->getOperand(0), N->getValueType(0));
1654 case ISD::BR_CC: Res = ExpandIntOp_BR_CC(N); break;
1655 case ISD::SELECT_CC: Res = ExpandIntOp_SELECT_CC(N); break;
1656 case ISD::SETCC: Res = ExpandIntOp_SETCC(N); break;
1659 Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo);
1664 // If the result is null, the sub-method took care of registering results etc.
1665 if (!Res.Val) return false;
1666 // If the result is N, the sub-method updated N in place. Check to see if any
1667 // operands are new, and if so, mark them.
1669 // Mark N as new and remark N and its operands. This allows us to correctly
1670 // revisit N if it needs another step of expansion and allows us to visit
1671 // any new operands to N.
1676 assert(Res.getValueType() == N->getValueType(0) && N->getNumValues() == 1 &&
1677 "Invalid operand expansion");
1679 ReplaceValueWith(SDOperand(N, 0), Res);
1683 SDOperand DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) {
1685 GetExpandedInteger(N->getOperand(0), InL, InH);
1686 // Just truncate the low part of the source.
1687 return DAG.getNode(ISD::TRUNCATE, N->getValueType(0), InL);
1690 SDOperand DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDOperand Source,
1692 // We know the destination is legal, but that the input needs to be expanded.
1693 MVT SourceVT = Source.getValueType();
1695 // Check to see if the target has a custom way to lower this. If so, use it.
1696 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
1697 default: assert(0 && "This action not implemented for this operation!");
1698 case TargetLowering::Legal:
1699 case TargetLowering::Expand:
1700 break; // This case is handled below.
1701 case TargetLowering::Custom:
1702 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
1704 if (NV.Val) return NV;
1705 break; // The target lowered this.
1708 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1709 if (SourceVT == MVT::i64) {
1710 if (DestTy == MVT::f32)
1711 LC = RTLIB::SINTTOFP_I64_F32;
1713 assert(DestTy == MVT::f64 && "Unknown fp value type!");
1714 LC = RTLIB::SINTTOFP_I64_F64;
1716 } else if (SourceVT == MVT::i128) {
1717 if (DestTy == MVT::f32)
1718 LC = RTLIB::SINTTOFP_I128_F32;
1719 else if (DestTy == MVT::f64)
1720 LC = RTLIB::SINTTOFP_I128_F64;
1721 else if (DestTy == MVT::f80)
1722 LC = RTLIB::SINTTOFP_I128_F80;
1724 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
1725 LC = RTLIB::SINTTOFP_I128_PPCF128;
1728 assert(0 && "Unknown int value type!");
1731 assert(LC != RTLIB::UNKNOWN_LIBCALL &&
1732 "Don't know how to expand this SINT_TO_FP!");
1733 return MakeLibCall(LC, DestTy, &Source, 1, true);
1736 SDOperand DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDOperand Source,
1738 // We know the destination is legal, but that the input needs to be expanded.
1739 assert(getTypeAction(Source.getValueType()) == ExpandInteger &&
1740 "This is not an expansion!");
1742 // If this is unsigned, and not supported, first perform the conversion to
1743 // signed, then adjust the result if the sign bit is set.
1744 SDOperand SignedConv = ExpandIntOp_SINT_TO_FP(Source, DestTy);
1746 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
1747 // incoming integer is set. To handle this, we dynamically test to see if
1748 // it is set, and, if so, add a fudge factor.
1750 GetExpandedInteger(Source, Lo, Hi);
1752 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
1753 DAG.getConstant(0, Hi.getValueType()),
1755 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
1756 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
1757 SignSet, Four, Zero);
1758 uint64_t FF = 0x5f800000ULL;
1759 if (TLI.isLittleEndian()) FF <<= 32;
1760 Constant *FudgeFactor = ConstantInt::get((Type*)Type::Int64Ty, FF);
1762 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
1763 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
1764 SDOperand FudgeInReg;
1765 if (DestTy == MVT::f32)
1766 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
1767 else if (DestTy.bitsGT(MVT::f32))
1768 // FIXME: Avoid the extend by construction the right constantpool?
1769 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
1770 CPIdx, NULL, 0, MVT::f32);
1772 assert(0 && "Unexpected conversion");
1774 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
1777 SDOperand DAGTypeLegalizer::ExpandIntOp_BR_CC(SDNode *N) {
1778 SDOperand NewLHS = N->getOperand(2), NewRHS = N->getOperand(3);
1779 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get();
1780 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1782 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1783 // against zero to select between true and false values.
1784 if (NewRHS.Val == 0) {
1785 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1786 CCCode = ISD::SETNE;
1789 // Update N to have the operands specified.
1790 return DAG.UpdateNodeOperands(SDOperand(N, 0), N->getOperand(0),
1791 DAG.getCondCode(CCCode), NewLHS, NewRHS,
1795 SDOperand DAGTypeLegalizer::ExpandIntOp_SELECT_CC(SDNode *N) {
1796 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1797 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get();
1798 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1800 // If ExpandSetCCOperands returned a scalar, we need to compare the result
1801 // against zero to select between true and false values.
1802 if (NewRHS.Val == 0) {
1803 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1804 CCCode = ISD::SETNE;
1807 // Update N to have the operands specified.
1808 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1809 N->getOperand(2), N->getOperand(3),
1810 DAG.getCondCode(CCCode));
1813 SDOperand DAGTypeLegalizer::ExpandIntOp_SETCC(SDNode *N) {
1814 SDOperand NewLHS = N->getOperand(0), NewRHS = N->getOperand(1);
1815 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();
1816 IntegerExpandSetCCOperands(NewLHS, NewRHS, CCCode);
1818 // If ExpandSetCCOperands returned a scalar, use it.
1819 if (NewRHS.Val == 0) {
1820 assert(NewLHS.getValueType() == N->getValueType(0) &&
1821 "Unexpected setcc expansion!");
1825 // Otherwise, update N to have the operands specified.
1826 return DAG.UpdateNodeOperands(SDOperand(N, 0), NewLHS, NewRHS,
1827 DAG.getCondCode(CCCode));
1830 /// IntegerExpandSetCCOperands - Expand the operands of a comparison. This code
1831 /// is shared among BR_CC, SELECT_CC, and SETCC handlers.
1832 void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDOperand &NewLHS,
1834 ISD::CondCode &CCCode) {
1835 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1836 GetExpandedInteger(NewLHS, LHSLo, LHSHi);
1837 GetExpandedInteger(NewRHS, RHSLo, RHSHi);
1839 MVT VT = NewLHS.getValueType();
1841 if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
1842 if (RHSLo == RHSHi) {
1843 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
1844 if (RHSCST->isAllOnesValue()) {
1845 // Equality comparison to -1.
1846 NewLHS = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1853 NewLHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1854 NewRHS = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1855 NewLHS = DAG.getNode(ISD::OR, NewLHS.getValueType(), NewLHS, NewRHS);
1856 NewRHS = DAG.getConstant(0, NewLHS.getValueType());
1860 // If this is a comparison of the sign bit, just look at the top part.
1862 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
1863 if ((CCCode == ISD::SETLT && CST->isNullValue()) || // X < 0
1864 (CCCode == ISD::SETGT && CST->isAllOnesValue())) { // X > -1
1870 // FIXME: This generated code sucks.
1871 ISD::CondCode LowCC;
1873 default: assert(0 && "Unknown integer setcc!");
1875 case ISD::SETULT: LowCC = ISD::SETULT; break;
1877 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1879 case ISD::SETULE: LowCC = ISD::SETULE; break;
1881 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1884 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1885 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1886 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1888 // NOTE: on targets without efficient SELECT of bools, we can always use
1889 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1890 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
1891 SDOperand Tmp1, Tmp2;
1892 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC,
1893 false, DagCombineInfo);
1895 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
1896 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1897 CCCode, false, DagCombineInfo);
1899 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1900 DAG.getCondCode(CCCode));
1902 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
1903 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
1904 if ((Tmp1C && Tmp1C->isNullValue()) ||
1905 (Tmp2C && Tmp2C->isNullValue() &&
1906 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
1907 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
1908 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
1909 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
1910 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
1911 // low part is known false, returns high part.
1912 // For LE / GE, if high part is known false, ignore the low part.
1913 // For LT / GT, if high part is known true, ignore the low part.
1915 NewRHS = SDOperand();
1919 NewLHS = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1920 ISD::SETEQ, false, DagCombineInfo);
1922 NewLHS = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
1924 NewLHS = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1925 NewLHS, Tmp1, Tmp2);
1926 NewRHS = SDOperand();
1929 SDOperand DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) {
1930 if (ISD::isNormalStore(N))
1931 return ExpandOp_NormalStore(N, OpNo);
1933 assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
1934 assert(OpNo == 1 && "Can only expand the stored value so far");
1936 MVT VT = N->getOperand(1).getValueType();
1937 MVT NVT = TLI.getTypeToTransformTo(VT);
1938 SDOperand Ch = N->getChain();
1939 SDOperand Ptr = N->getBasePtr();
1940 int SVOffset = N->getSrcValueOffset();
1941 unsigned Alignment = N->getAlignment();
1942 bool isVolatile = N->isVolatile();
1945 assert(NVT.isByteSized() && "Expanded type not byte sized!");
1947 if (N->getMemoryVT().bitsLE(NVT)) {
1948 GetExpandedInteger(N->getValue(), Lo, Hi);
1949 return DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1950 N->getMemoryVT(), isVolatile, Alignment);
1951 } else if (TLI.isLittleEndian()) {
1952 // Little-endian - low bits are at low addresses.
1953 GetExpandedInteger(N->getValue(), Lo, Hi);
1955 Lo = DAG.getStore(Ch, Lo, Ptr, N->getSrcValue(), SVOffset,
1956 isVolatile, Alignment);
1958 unsigned ExcessBits =
1959 N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
1960 MVT NEVT = MVT::getIntegerVT(ExcessBits);
1962 // Increment the pointer to the other half.
1963 unsigned IncrementSize = NVT.getSizeInBits()/8;
1964 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1965 DAG.getIntPtrConstant(IncrementSize));
1966 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1967 SVOffset+IncrementSize, NEVT,
1968 isVolatile, MinAlign(Alignment, IncrementSize));
1969 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1971 // Big-endian - high bits are at low addresses. Favor aligned stores at
1972 // the cost of some bit-fiddling.
1973 GetExpandedInteger(N->getValue(), Lo, Hi);
1975 MVT EVT = N->getMemoryVT();
1976 unsigned EBytes = EVT.getStoreSizeInBits()/8;
1977 unsigned IncrementSize = NVT.getSizeInBits()/8;
1978 unsigned ExcessBits = (EBytes - IncrementSize)*8;
1979 MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
1981 if (ExcessBits < NVT.getSizeInBits()) {
1982 // Transfer high bits from the top of Lo to the bottom of Hi.
1983 Hi = DAG.getNode(ISD::SHL, NVT, Hi,
1984 DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
1985 TLI.getShiftAmountTy()));
1986 Hi = DAG.getNode(ISD::OR, NVT, Hi,
1987 DAG.getNode(ISD::SRL, NVT, Lo,
1988 DAG.getConstant(ExcessBits,
1989 TLI.getShiftAmountTy())));
1992 // Store both the high bits and maybe some of the low bits.
1993 Hi = DAG.getTruncStore(Ch, Hi, Ptr, N->getSrcValue(),
1994 SVOffset, HiVT, isVolatile, Alignment);
1996 // Increment the pointer to the other half.
1997 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
1998 DAG.getIntPtrConstant(IncrementSize));
1999 // Store the lowest ExcessBits bits in the second half.
2000 Lo = DAG.getTruncStore(Ch, Lo, Ptr, N->getSrcValue(),
2001 SVOffset+IncrementSize,
2002 MVT::getIntegerVT(ExcessBits),
2003 isVolatile, MinAlign(Alignment, IncrementSize));
2004 return DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);