1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// PromoteOp - Given an operation that produces a value in an invalid type,
151 /// promote it to compute the value into a larger type. The produced value
152 /// will have the correct bits for the low portion of the register, but no
153 /// guarantee is made about the top bits: it may be zero, sign-extended, or
155 SDOperand PromoteOp(SDOperand O);
157 /// ExpandOp - Expand the specified SDOperand into its two component pieces
158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
159 /// the LegalizeNodes map is filled in for any results that are not expanded,
160 /// the ExpandedNodes map is filled in for any results that are expanded, and
161 /// the Lo/Hi values are returned. This applies to integer types and Vector
163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// SplitVectorOp - Given an operand of vector type, break it down into
166 /// two smaller values.
167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
169 /// ScalarizeVectorOp - Given an operand of single-element vector type
170 /// (e.g. v1f32), convert it into the equivalent operation that returns a
171 /// scalar (e.g. f32) value.
172 SDOperand ScalarizeVectorOp(SDOperand O);
174 /// isShuffleLegal - Return true if a vector shuffle is legal with the
175 /// specified mask and type. Targets can specify exactly which masks they
176 /// support and the code generator is tasked with not creating illegal masks.
178 /// Note that this will also return true for shuffles that are promoted to a
181 /// If this is a legal shuffle, this method returns the (possibly promoted)
182 /// build_vector Mask. If it's not a legal shuffle, it returns null.
183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
190 SDOperand CreateStackTemporary(MVT::ValueType VT);
192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
198 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
200 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
202 MVT::ValueType DestVT);
203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
208 SDOperand ExpandBSWAP(SDOperand Op);
209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
211 SDOperand &Lo, SDOperand &Hi);
212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
213 SDOperand &Lo, SDOperand &Hi);
215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
218 SDOperand getIntPtrConstant(uint64_t Val) {
219 return DAG.getConstant(Val, TLI.getPointerTy());
224 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
225 /// specified mask and type. Targets can specify exactly which masks they
226 /// support and the code generator is tasked with not creating illegal masks.
228 /// Note that this will also return true for shuffles that are promoted to a
230 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
231 SDOperand Mask) const {
232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
234 case TargetLowering::Legal:
235 case TargetLowering::Custom:
237 case TargetLowering::Promote: {
238 // If this is promoted to a different type, convert the shuffle mask and
239 // ask if it is legal in the promoted type!
240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
242 // If we changed # elements, change the shuffle mask.
243 unsigned NumEltsGrowth =
244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
246 if (NumEltsGrowth > 1) {
247 // Renumber the elements.
248 SmallVector<SDOperand, 8> Ops;
249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
250 SDOperand InOp = Mask.getOperand(i);
251 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
252 if (InOp.getOpcode() == ISD::UNDEF)
253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
269 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
270 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
271 ValueTypeActions(TLI.getValueTypeActions()) {
272 assert(MVT::LAST_VALUETYPE <= 32 &&
273 "Too many value types for ValueTypeActions to hold!");
276 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
277 /// contains all of a nodes operands before it contains the node.
278 static void ComputeTopDownOrdering(SelectionDAG &DAG,
279 SmallVector<SDNode*, 64> &Order) {
281 DenseMap<SDNode*, unsigned> Visited;
282 std::vector<SDNode*> Worklist;
283 Worklist.reserve(128);
285 // Compute ordering from all of the leaves in the graphs, those (like the
286 // entry node) that have no operands.
287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
288 E = DAG.allnodes_end(); I != E; ++I) {
289 if (I->getNumOperands() == 0) {
291 Worklist.push_back(I);
295 while (!Worklist.empty()) {
296 SDNode *N = Worklist.back();
299 if (++Visited[N] != N->getNumOperands())
300 continue; // Haven't visited all operands yet
304 // Now that we have N in, add anything that uses it if all of their operands
306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
308 Worklist.push_back(*UI);
311 assert(Order.size() == Visited.size() &&
313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
314 "Error: DAG is cyclic!");
318 void SelectionDAGLegalize::LegalizeDAG() {
319 LastCALLSEQ_END = DAG.getEntryNode();
320 IsLegalizingCall = false;
322 // The legalize process is inherently a bottom-up recursive process (users
323 // legalize their uses before themselves). Given infinite stack space, we
324 // could just start legalizing on the root and traverse the whole graph. In
325 // practice however, this causes us to run out of stack space on large basic
326 // blocks. To avoid this problem, compute an ordering of the nodes where each
327 // node is only legalized after all of its operands are legalized.
328 SmallVector<SDNode*, 64> Order;
329 ComputeTopDownOrdering(DAG, Order);
331 for (unsigned i = 0, e = Order.size(); i != e; ++i)
332 HandleOp(SDOperand(Order[i], 0));
334 // Finally, it's possible the root changed. Get the new root.
335 SDOperand OldRoot = DAG.getRoot();
336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
337 DAG.setRoot(LegalizedNodes[OldRoot]);
339 ExpandedNodes.clear();
340 LegalizedNodes.clear();
341 PromotedNodes.clear();
343 ScalarizedNodes.clear();
345 // Remove dead nodes now.
346 DAG.RemoveDeadNodes();
350 /// FindCallEndFromCallStart - Given a chained node that is part of a call
351 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
352 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
353 if (Node->getOpcode() == ISD::CALLSEQ_END)
355 if (Node->use_empty())
356 return 0; // No CallSeqEnd
358 // The chain is usually at the end.
359 SDOperand TheChain(Node, Node->getNumValues()-1);
360 if (TheChain.getValueType() != MVT::Other) {
361 // Sometimes it's at the beginning.
362 TheChain = SDOperand(Node, 0);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Otherwise, hunt for it.
365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
366 if (Node->getValueType(i) == MVT::Other) {
367 TheChain = SDOperand(Node, i);
371 // Otherwise, we walked into a node without a chain.
372 if (TheChain.getValueType() != MVT::Other)
377 for (SDNode::use_iterator UI = Node->use_begin(),
378 E = Node->use_end(); UI != E; ++UI) {
380 // Make sure to only follow users of our token chain.
382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
383 if (User->getOperand(i) == TheChain)
384 if (SDNode *Result = FindCallEndFromCallStart(User))
390 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
391 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
392 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
393 assert(Node && "Didn't find callseq_start for a call??");
394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
396 assert(Node->getOperand(0).getValueType() == MVT::Other &&
397 "Node doesn't have a token chain argument!");
398 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
401 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
402 /// see if any uses can reach Dest. If no dest operands can get to dest,
403 /// legalize them, legalize ourself, and return false, otherwise, return true.
405 /// Keep track of the nodes we fine that actually do lead to Dest in
406 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If we've already processed this node and it does lead to Dest, there is no
413 // need to reprocess it.
414 if (NodesLeadingTo.count(N)) return true;
416 // If the first result of this node has been already legalized, then it cannot
418 switch (getTypeAction(N->getValueType(0))) {
420 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
423 if (PromotedNodes.count(SDOperand(N, 0))) return false;
426 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
430 // Okay, this node has not already been legalized. Check and legalize all
431 // operands. If none lead to Dest, then we can legalize this node.
432 bool OperandsLeadToDest = false;
433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
434 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
437 if (OperandsLeadToDest) {
438 NodesLeadingTo.insert(N);
442 // Okay, this node looks safe, legalize it and return false.
443 HandleOp(SDOperand(N, 0));
447 /// HandleOp - Legalize, Promote, or Expand the specified operand as
448 /// appropriate for its type.
449 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
450 MVT::ValueType VT = Op.getValueType();
451 switch (getTypeAction(VT)) {
452 default: assert(0 && "Bad type action!");
453 case Legal: (void)LegalizeOp(Op); break;
454 case Promote: (void)PromoteOp(Op); break;
456 if (!MVT::isVector(VT)) {
457 // If this is an illegal scalar, expand it into its two component
460 if (Op.getOpcode() == ISD::TargetConstant)
461 break; // Allow illegal target nodes.
463 } else if (MVT::getVectorNumElements(VT) == 1) {
464 // If this is an illegal single element vector, convert it to a
466 (void)ScalarizeVectorOp(Op);
468 // Otherwise, this is an illegal multiple element vector.
469 // Split it in half and legalize both parts.
471 SplitVectorOp(Op, X, Y);
477 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
478 /// a load from the constant pool.
479 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
480 SelectionDAG &DAG, TargetLowering &TLI) {
483 // If a FP immediate is precise when represented as a float and if the
484 // target can do an extending load from float to double, we put it into
485 // the constant pool as a float, even if it's is statically typed as a
487 MVT::ValueType VT = CFP->getValueType(0);
488 bool isDouble = VT == MVT::f64;
489 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
492 if (VT!=MVT::f64 && VT!=MVT::f32)
493 assert(0 && "Invalid type expansion");
494 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
495 isDouble ? MVT::i64 : MVT::i32);
498 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
499 // Only do this if the target has a native EXTLOAD instruction from f32.
500 // Do not try to be clever about long doubles (so far)
501 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
502 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
507 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
509 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
510 CPIdx, NULL, 0, MVT::f32);
512 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
517 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
520 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
521 SelectionDAG &DAG, TargetLowering &TLI) {
522 MVT::ValueType VT = Node->getValueType(0);
523 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
524 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
525 "fcopysign expansion only supported for f32 and f64");
526 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
528 // First get the sign bit of second operand.
529 SDOperand Mask1 = (SrcVT == MVT::f64)
530 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
531 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
532 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
533 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
534 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
535 // Shift right or sign-extend it if the two operands have different types.
536 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
538 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
539 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
540 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
541 } else if (SizeDiff < 0)
542 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
544 // Clear the sign bit of first operand.
545 SDOperand Mask2 = (VT == MVT::f64)
546 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
547 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
548 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
549 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
550 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
552 // Or the value with the sign bit.
553 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
557 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
559 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
560 TargetLowering &TLI) {
561 SDOperand Chain = ST->getChain();
562 SDOperand Ptr = ST->getBasePtr();
563 SDOperand Val = ST->getValue();
564 MVT::ValueType VT = Val.getValueType();
565 int Alignment = ST->getAlignment();
566 int SVOffset = ST->getSrcValueOffset();
567 if (MVT::isFloatingPoint(ST->getStoredVT())) {
568 // Expand to a bitconvert of the value to the integer type of the
569 // same size, then a (misaligned) int store.
570 MVT::ValueType intVT;
573 else if (VT==MVT::f32)
576 assert(0 && "Unaligned load of unsupported floating point type");
578 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
579 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
580 SVOffset, ST->isVolatile(), Alignment);
582 assert(MVT::isInteger(ST->getStoredVT()) &&
583 "Unaligned store of unknown type.");
584 // Get the half-size VT
585 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
586 int NumBits = MVT::getSizeInBits(NewStoredVT);
587 int IncrementSize = NumBits / 8;
589 // Divide the stored value in two parts.
590 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
592 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
594 // Store the two parts
595 SDOperand Store1, Store2;
596 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
597 ST->getSrcValue(), SVOffset, NewStoredVT,
598 ST->isVolatile(), Alignment);
599 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
600 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
601 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
602 ST->getSrcValue(), SVOffset + IncrementSize,
603 NewStoredVT, ST->isVolatile(), Alignment);
605 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
608 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
610 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
611 TargetLowering &TLI) {
612 int SVOffset = LD->getSrcValueOffset();
613 SDOperand Chain = LD->getChain();
614 SDOperand Ptr = LD->getBasePtr();
615 MVT::ValueType VT = LD->getValueType(0);
616 MVT::ValueType LoadedVT = LD->getLoadedVT();
617 if (MVT::isFloatingPoint(VT)) {
618 // Expand to a (misaligned) integer load of the same size,
619 // then bitconvert to floating point.
620 MVT::ValueType intVT;
621 if (LoadedVT==MVT::f64)
623 else if (LoadedVT==MVT::f32)
626 assert(0 && "Unaligned load of unsupported floating point type");
628 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
629 SVOffset, LD->isVolatile(),
631 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
633 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
635 SDOperand Ops[] = { Result, Chain };
636 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
639 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type.");
640 MVT::ValueType NewLoadedVT = LoadedVT - 1;
641 int NumBits = MVT::getSizeInBits(NewLoadedVT);
642 int Alignment = LD->getAlignment();
643 int IncrementSize = NumBits / 8;
644 ISD::LoadExtType HiExtType = LD->getExtensionType();
646 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
647 if (HiExtType == ISD::NON_EXTLOAD)
648 HiExtType = ISD::ZEXTLOAD;
650 // Load the value in two parts
652 if (TLI.isLittleEndian()) {
653 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
654 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
655 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
656 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
657 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
658 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
661 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
662 NewLoadedVT,LD->isVolatile(), Alignment);
663 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
664 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
665 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
666 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
670 // aggregate the two parts
671 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
672 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
673 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
675 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
678 SDOperand Ops[] = { Result, TF };
679 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
682 /// LegalizeOp - We know that the specified value has a legal type, and
683 /// that its operands are legal. Now ensure that the operation itself
684 /// is legal, recursively ensuring that the operands' operations remain
686 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
687 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
690 assert(isTypeLegal(Op.getValueType()) &&
691 "Caller should expand or promote operands that are not legal!");
692 SDNode *Node = Op.Val;
694 // If this operation defines any values that cannot be represented in a
695 // register on this target, make sure to expand or promote them.
696 if (Node->getNumValues() > 1) {
697 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
698 if (getTypeAction(Node->getValueType(i)) != Legal) {
699 HandleOp(Op.getValue(i));
700 assert(LegalizedNodes.count(Op) &&
701 "Handling didn't add legal operands!");
702 return LegalizedNodes[Op];
706 // Note that LegalizeOp may be reentered even from single-use nodes, which
707 // means that we always must cache transformed nodes.
708 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
709 if (I != LegalizedNodes.end()) return I->second;
711 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
712 SDOperand Result = Op;
713 bool isCustom = false;
715 switch (Node->getOpcode()) {
716 case ISD::FrameIndex:
717 case ISD::EntryToken:
719 case ISD::BasicBlock:
720 case ISD::TargetFrameIndex:
721 case ISD::TargetJumpTable:
722 case ISD::TargetConstant:
723 case ISD::TargetConstantFP:
724 case ISD::TargetConstantPool:
725 case ISD::TargetGlobalAddress:
726 case ISD::TargetGlobalTLSAddress:
727 case ISD::TargetExternalSymbol:
732 // Primitives must all be legal.
733 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
734 "This must be legal!");
737 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
738 // If this is a target node, legalize it by legalizing the operands then
739 // passing it through.
740 SmallVector<SDOperand, 8> Ops;
741 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
742 Ops.push_back(LegalizeOp(Node->getOperand(i)));
744 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
746 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
747 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
748 return Result.getValue(Op.ResNo);
750 // Otherwise this is an unhandled builtin node. splat.
752 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
754 assert(0 && "Do not know how to legalize this operator!");
756 case ISD::GLOBAL_OFFSET_TABLE:
757 case ISD::GlobalAddress:
758 case ISD::GlobalTLSAddress:
759 case ISD::ExternalSymbol:
760 case ISD::ConstantPool:
761 case ISD::JumpTable: // Nothing to do.
762 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
763 default: assert(0 && "This action is not supported yet!");
764 case TargetLowering::Custom:
765 Tmp1 = TLI.LowerOperation(Op, DAG);
766 if (Tmp1.Val) Result = Tmp1;
767 // FALLTHROUGH if the target doesn't want to lower this op after all.
768 case TargetLowering::Legal:
773 case ISD::RETURNADDR:
774 // The only option for these nodes is to custom lower them. If the target
775 // does not custom lower them, then return zero.
776 Tmp1 = TLI.LowerOperation(Op, DAG);
780 Result = DAG.getConstant(0, TLI.getPointerTy());
782 case ISD::FRAME_TO_ARGS_OFFSET: {
783 MVT::ValueType VT = Node->getValueType(0);
784 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
785 default: assert(0 && "This action is not supported yet!");
786 case TargetLowering::Custom:
787 Result = TLI.LowerOperation(Op, DAG);
788 if (Result.Val) break;
790 case TargetLowering::Legal:
791 Result = DAG.getConstant(0, VT);
796 case ISD::EXCEPTIONADDR: {
797 Tmp1 = LegalizeOp(Node->getOperand(0));
798 MVT::ValueType VT = Node->getValueType(0);
799 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
800 default: assert(0 && "This action is not supported yet!");
801 case TargetLowering::Expand: {
802 unsigned Reg = TLI.getExceptionAddressRegister();
803 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
806 case TargetLowering::Custom:
807 Result = TLI.LowerOperation(Op, DAG);
808 if (Result.Val) break;
810 case TargetLowering::Legal: {
811 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
812 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
813 Ops, 2).getValue(Op.ResNo);
819 case ISD::EHSELECTION: {
820 Tmp1 = LegalizeOp(Node->getOperand(0));
821 Tmp2 = LegalizeOp(Node->getOperand(1));
822 MVT::ValueType VT = Node->getValueType(0);
823 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
824 default: assert(0 && "This action is not supported yet!");
825 case TargetLowering::Expand: {
826 unsigned Reg = TLI.getExceptionSelectorRegister();
827 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
830 case TargetLowering::Custom:
831 Result = TLI.LowerOperation(Op, DAG);
832 if (Result.Val) break;
834 case TargetLowering::Legal: {
835 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
836 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
837 Ops, 2).getValue(Op.ResNo);
843 case ISD::EH_RETURN: {
844 MVT::ValueType VT = Node->getValueType(0);
845 // The only "good" option for this node is to custom lower it.
846 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
847 default: assert(0 && "This action is not supported at all!");
848 case TargetLowering::Custom:
849 Result = TLI.LowerOperation(Op, DAG);
850 if (Result.Val) break;
852 case TargetLowering::Legal:
853 // Target does not know, how to lower this, lower to noop
854 Result = LegalizeOp(Node->getOperand(0));
859 case ISD::AssertSext:
860 case ISD::AssertZext:
861 Tmp1 = LegalizeOp(Node->getOperand(0));
862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
864 case ISD::MERGE_VALUES:
865 // Legalize eliminates MERGE_VALUES nodes.
866 Result = Node->getOperand(Op.ResNo);
868 case ISD::CopyFromReg:
869 Tmp1 = LegalizeOp(Node->getOperand(0));
870 Result = Op.getValue(0);
871 if (Node->getNumValues() == 2) {
872 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
874 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
875 if (Node->getNumOperands() == 3) {
876 Tmp2 = LegalizeOp(Node->getOperand(2));
877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
881 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
883 // Since CopyFromReg produces two values, make sure to remember that we
884 // legalized both of them.
885 AddLegalizedOperand(Op.getValue(0), Result);
886 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
887 return Result.getValue(Op.ResNo);
889 MVT::ValueType VT = Op.getValueType();
890 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
891 default: assert(0 && "This action is not supported yet!");
892 case TargetLowering::Expand:
893 if (MVT::isInteger(VT))
894 Result = DAG.getConstant(0, VT);
895 else if (MVT::isFloatingPoint(VT))
896 Result = DAG.getConstantFP(0, VT);
898 assert(0 && "Unknown value type!");
900 case TargetLowering::Legal:
906 case ISD::INTRINSIC_W_CHAIN:
907 case ISD::INTRINSIC_WO_CHAIN:
908 case ISD::INTRINSIC_VOID: {
909 SmallVector<SDOperand, 8> Ops;
910 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
911 Ops.push_back(LegalizeOp(Node->getOperand(i)));
912 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
914 // Allow the target to custom lower its intrinsics if it wants to.
915 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
916 TargetLowering::Custom) {
917 Tmp3 = TLI.LowerOperation(Result, DAG);
918 if (Tmp3.Val) Result = Tmp3;
921 if (Result.Val->getNumValues() == 1) break;
923 // Must have return value and chain result.
924 assert(Result.Val->getNumValues() == 2 &&
925 "Cannot return more than two values!");
927 // Since loads produce two values, make sure to remember that we
928 // legalized both of them.
929 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
930 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
931 return Result.getValue(Op.ResNo);
935 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
936 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
938 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
939 case TargetLowering::Promote:
940 default: assert(0 && "This action is not supported yet!");
941 case TargetLowering::Expand: {
942 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
943 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
944 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
946 if (MMI && (useDEBUG_LOC || useLABEL)) {
947 const std::string &FName =
948 cast<StringSDNode>(Node->getOperand(3))->getValue();
949 const std::string &DirName =
950 cast<StringSDNode>(Node->getOperand(4))->getValue();
951 unsigned SrcFile = MMI->RecordSource(DirName, FName);
953 SmallVector<SDOperand, 8> Ops;
954 Ops.push_back(Tmp1); // chain
955 SDOperand LineOp = Node->getOperand(1);
956 SDOperand ColOp = Node->getOperand(2);
959 Ops.push_back(LineOp); // line #
960 Ops.push_back(ColOp); // col #
961 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
962 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
964 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
965 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
966 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
967 Ops.push_back(DAG.getConstant(ID, MVT::i32));
968 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
971 Result = Tmp1; // chain
975 case TargetLowering::Legal:
976 if (Tmp1 != Node->getOperand(0) ||
977 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
978 SmallVector<SDOperand, 8> Ops;
980 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
981 Ops.push_back(Node->getOperand(1)); // line # must be legal.
982 Ops.push_back(Node->getOperand(2)); // col # must be legal.
984 // Otherwise promote them.
985 Ops.push_back(PromoteOp(Node->getOperand(1)));
986 Ops.push_back(PromoteOp(Node->getOperand(2)));
988 Ops.push_back(Node->getOperand(3)); // filename must be legal.
989 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
990 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
997 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
998 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
999 default: assert(0 && "This action is not supported yet!");
1000 case TargetLowering::Legal:
1001 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1002 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1003 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1004 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1005 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1011 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1012 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1013 default: assert(0 && "This action is not supported yet!");
1014 case TargetLowering::Legal:
1015 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1016 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1017 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1019 case TargetLowering::Expand:
1020 Result = LegalizeOp(Node->getOperand(0));
1025 case ISD::Constant: {
1026 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1028 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1030 // We know we don't need to expand constants here, constants only have one
1031 // value and we check that it is fine above.
1033 if (opAction == TargetLowering::Custom) {
1034 Tmp1 = TLI.LowerOperation(Result, DAG);
1040 case ISD::ConstantFP: {
1041 // Spill FP immediates to the constant pool if the target cannot directly
1042 // codegen them. Targets often have some immediate values that can be
1043 // efficiently generated into an FP register without a load. We explicitly
1044 // leave these constants as ConstantFP nodes for the target to deal with.
1045 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1047 // Check to see if this FP immediate is already legal.
1048 bool isLegal = false;
1049 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1050 E = TLI.legal_fpimm_end(); I != E; ++I)
1051 if (CFP->isExactlyValue(*I)) {
1056 // If this is a legal constant, turn it into a TargetConstantFP node.
1058 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1059 CFP->getValueType(0));
1063 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1064 default: assert(0 && "This action is not supported yet!");
1065 case TargetLowering::Custom:
1066 Tmp3 = TLI.LowerOperation(Result, DAG);
1072 case TargetLowering::Expand:
1073 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1077 case ISD::TokenFactor:
1078 if (Node->getNumOperands() == 2) {
1079 Tmp1 = LegalizeOp(Node->getOperand(0));
1080 Tmp2 = LegalizeOp(Node->getOperand(1));
1081 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1082 } else if (Node->getNumOperands() == 3) {
1083 Tmp1 = LegalizeOp(Node->getOperand(0));
1084 Tmp2 = LegalizeOp(Node->getOperand(1));
1085 Tmp3 = LegalizeOp(Node->getOperand(2));
1086 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1088 SmallVector<SDOperand, 8> Ops;
1089 // Legalize the operands.
1090 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1091 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1092 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1096 case ISD::FORMAL_ARGUMENTS:
1098 // The only option for this is to custom lower it.
1099 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1100 assert(Tmp3.Val && "Target didn't custom lower this node!");
1101 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1102 "Lowering call/formal_arguments produced unexpected # results!");
1104 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1105 // remember that we legalized all of them, so it doesn't get relegalized.
1106 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1107 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1110 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1113 case ISD::EXTRACT_SUBREG: {
1114 Tmp1 = LegalizeOp(Node->getOperand(0));
1115 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1116 assert(idx && "Operand must be a constant");
1117 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1118 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1121 case ISD::INSERT_SUBREG: {
1122 Tmp1 = LegalizeOp(Node->getOperand(0));
1123 Tmp2 = LegalizeOp(Node->getOperand(1));
1124 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1125 assert(idx && "Operand must be a constant");
1126 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1127 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1130 case ISD::BUILD_VECTOR:
1131 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Custom:
1134 Tmp3 = TLI.LowerOperation(Result, DAG);
1140 case TargetLowering::Expand:
1141 Result = ExpandBUILD_VECTOR(Result.Val);
1145 case ISD::INSERT_VECTOR_ELT:
1146 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1147 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1148 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1151 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1152 Node->getValueType(0))) {
1153 default: assert(0 && "This action is not supported yet!");
1154 case TargetLowering::Legal:
1156 case TargetLowering::Custom:
1157 Tmp3 = TLI.LowerOperation(Result, DAG);
1163 case TargetLowering::Expand: {
1164 // If the insert index is a constant, codegen this as a scalar_to_vector,
1165 // then a shuffle that inserts it into the right position in the vector.
1166 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1167 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1168 Tmp1.getValueType(), Tmp2);
1170 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1171 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1172 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1174 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1175 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1177 SmallVector<SDOperand, 8> ShufOps;
1178 for (unsigned i = 0; i != NumElts; ++i) {
1179 if (i != InsertPos->getValue())
1180 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1182 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1184 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1185 &ShufOps[0], ShufOps.size());
1187 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1188 Tmp1, ScVec, ShufMask);
1189 Result = LegalizeOp(Result);
1193 // If the target doesn't support this, we have to spill the input vector
1194 // to a temporary stack slot, update the element, then reload it. This is
1195 // badness. We could also load the value into a vector register (either
1196 // with a "move to register" or "extload into register" instruction, then
1197 // permute it into place, if the idx is a constant and if the idx is
1198 // supported by the target.
1199 MVT::ValueType VT = Tmp1.getValueType();
1200 MVT::ValueType EltVT = Tmp2.getValueType();
1201 MVT::ValueType IdxVT = Tmp3.getValueType();
1202 MVT::ValueType PtrVT = TLI.getPointerTy();
1203 SDOperand StackPtr = CreateStackTemporary(VT);
1204 // Store the vector.
1205 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1207 // Truncate or zero extend offset to target pointer type.
1208 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1209 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1210 // Add the offset to the index.
1211 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1212 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1213 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1214 // Store the scalar value.
1215 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1216 // Load the updated vector.
1217 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1222 case ISD::SCALAR_TO_VECTOR:
1223 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1224 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1228 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1229 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1230 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1231 Node->getValueType(0))) {
1232 default: assert(0 && "This action is not supported yet!");
1233 case TargetLowering::Legal:
1235 case TargetLowering::Custom:
1236 Tmp3 = TLI.LowerOperation(Result, DAG);
1242 case TargetLowering::Expand:
1243 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1247 case ISD::VECTOR_SHUFFLE:
1248 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1249 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1250 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1252 // Allow targets to custom lower the SHUFFLEs they support.
1253 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1254 default: assert(0 && "Unknown operation action!");
1255 case TargetLowering::Legal:
1256 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1257 "vector shuffle should not be created if not legal!");
1259 case TargetLowering::Custom:
1260 Tmp3 = TLI.LowerOperation(Result, DAG);
1266 case TargetLowering::Expand: {
1267 MVT::ValueType VT = Node->getValueType(0);
1268 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1269 MVT::ValueType PtrVT = TLI.getPointerTy();
1270 SDOperand Mask = Node->getOperand(2);
1271 unsigned NumElems = Mask.getNumOperands();
1272 SmallVector<SDOperand,8> Ops;
1273 for (unsigned i = 0; i != NumElems; ++i) {
1274 SDOperand Arg = Mask.getOperand(i);
1275 if (Arg.getOpcode() == ISD::UNDEF) {
1276 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1278 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1279 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1281 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1282 DAG.getConstant(Idx, PtrVT)));
1284 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1285 DAG.getConstant(Idx - NumElems, PtrVT)));
1288 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1291 case TargetLowering::Promote: {
1292 // Change base type to a different vector type.
1293 MVT::ValueType OVT = Node->getValueType(0);
1294 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1296 // Cast the two input vectors.
1297 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1298 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1300 // Convert the shuffle mask to the right # elements.
1301 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1302 assert(Tmp3.Val && "Shuffle not legal?");
1303 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1304 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1310 case ISD::EXTRACT_VECTOR_ELT:
1311 Tmp1 = Node->getOperand(0);
1312 Tmp2 = LegalizeOp(Node->getOperand(1));
1313 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1314 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1317 case ISD::EXTRACT_SUBVECTOR:
1318 Tmp1 = Node->getOperand(0);
1319 Tmp2 = LegalizeOp(Node->getOperand(1));
1320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1321 Result = ExpandEXTRACT_SUBVECTOR(Result);
1324 case ISD::CALLSEQ_START: {
1325 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1327 // Recursively Legalize all of the inputs of the call end that do not lead
1328 // to this call start. This ensures that any libcalls that need be inserted
1329 // are inserted *before* the CALLSEQ_START.
1330 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1331 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1332 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1336 // Now that we legalized all of the inputs (which may have inserted
1337 // libcalls) create the new CALLSEQ_START node.
1338 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1340 // Merge in the last call, to ensure that this call start after the last
1342 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1343 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1344 Tmp1 = LegalizeOp(Tmp1);
1347 // Do not try to legalize the target-specific arguments (#1+).
1348 if (Tmp1 != Node->getOperand(0)) {
1349 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1351 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1354 // Remember that the CALLSEQ_START is legalized.
1355 AddLegalizedOperand(Op.getValue(0), Result);
1356 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1357 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1359 // Now that the callseq_start and all of the non-call nodes above this call
1360 // sequence have been legalized, legalize the call itself. During this
1361 // process, no libcalls can/will be inserted, guaranteeing that no calls
1363 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1364 SDOperand InCallSEQ = LastCALLSEQ_END;
1365 // Note that we are selecting this call!
1366 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1367 IsLegalizingCall = true;
1369 // Legalize the call, starting from the CALLSEQ_END.
1370 LegalizeOp(LastCALLSEQ_END);
1371 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1374 case ISD::CALLSEQ_END:
1375 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1376 // will cause this node to be legalized as well as handling libcalls right.
1377 if (LastCALLSEQ_END.Val != Node) {
1378 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1379 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1380 assert(I != LegalizedNodes.end() &&
1381 "Legalizing the call start should have legalized this node!");
1385 // Otherwise, the call start has been legalized and everything is going
1386 // according to plan. Just legalize ourselves normally here.
1387 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1388 // Do not try to legalize the target-specific arguments (#1+), except for
1389 // an optional flag input.
1390 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1391 if (Tmp1 != Node->getOperand(0)) {
1392 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1394 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1397 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1398 if (Tmp1 != Node->getOperand(0) ||
1399 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1400 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1403 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1406 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1407 // This finishes up call legalization.
1408 IsLegalizingCall = false;
1410 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1411 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1412 if (Node->getNumValues() == 2)
1413 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1414 return Result.getValue(Op.ResNo);
1415 case ISD::DYNAMIC_STACKALLOC: {
1416 MVT::ValueType VT = Node->getValueType(0);
1417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1418 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1419 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1422 Tmp1 = Result.getValue(0);
1423 Tmp2 = Result.getValue(1);
1424 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1425 default: assert(0 && "This action is not supported yet!");
1426 case TargetLowering::Expand: {
1427 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1428 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1429 " not tell us which reg is the stack pointer!");
1430 SDOperand Chain = Tmp1.getOperand(0);
1431 SDOperand Size = Tmp2.getOperand(1);
1432 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1433 Chain = SP.getValue(1);
1434 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1435 unsigned StackAlign =
1436 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1437 if (Align > StackAlign)
1438 SP = DAG.getNode(ISD::AND, VT, SP,
1439 DAG.getConstant(-(uint64_t)Align, VT));
1440 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1441 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1442 Tmp1 = LegalizeOp(Tmp1);
1443 Tmp2 = LegalizeOp(Tmp2);
1446 case TargetLowering::Custom:
1447 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1449 Tmp1 = LegalizeOp(Tmp3);
1450 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1453 case TargetLowering::Legal:
1456 // Since this op produce two values, make sure to remember that we
1457 // legalized both of them.
1458 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1459 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1460 return Op.ResNo ? Tmp2 : Tmp1;
1462 case ISD::INLINEASM: {
1463 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1464 bool Changed = false;
1465 // Legalize all of the operands of the inline asm, in case they are nodes
1466 // that need to be expanded or something. Note we skip the asm string and
1467 // all of the TargetConstant flags.
1468 SDOperand Op = LegalizeOp(Ops[0]);
1469 Changed = Op != Ops[0];
1472 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1473 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1474 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1475 for (++i; NumVals; ++i, --NumVals) {
1476 SDOperand Op = LegalizeOp(Ops[i]);
1485 Op = LegalizeOp(Ops.back());
1486 Changed |= Op != Ops.back();
1491 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1493 // INLINE asm returns a chain and flag, make sure to add both to the map.
1494 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1495 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1496 return Result.getValue(Op.ResNo);
1499 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1500 // Ensure that libcalls are emitted before a branch.
1501 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1502 Tmp1 = LegalizeOp(Tmp1);
1503 LastCALLSEQ_END = DAG.getEntryNode();
1505 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1508 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1509 // Ensure that libcalls are emitted before a branch.
1510 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1511 Tmp1 = LegalizeOp(Tmp1);
1512 LastCALLSEQ_END = DAG.getEntryNode();
1514 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1515 default: assert(0 && "Indirect target must be legal type (pointer)!");
1517 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1520 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1523 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1524 // Ensure that libcalls are emitted before a branch.
1525 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1526 Tmp1 = LegalizeOp(Tmp1);
1527 LastCALLSEQ_END = DAG.getEntryNode();
1529 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1530 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1532 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1533 default: assert(0 && "This action is not supported yet!");
1534 case TargetLowering::Legal: break;
1535 case TargetLowering::Custom:
1536 Tmp1 = TLI.LowerOperation(Result, DAG);
1537 if (Tmp1.Val) Result = Tmp1;
1539 case TargetLowering::Expand: {
1540 SDOperand Chain = Result.getOperand(0);
1541 SDOperand Table = Result.getOperand(1);
1542 SDOperand Index = Result.getOperand(2);
1544 MVT::ValueType PTy = TLI.getPointerTy();
1545 MachineFunction &MF = DAG.getMachineFunction();
1546 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1547 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1548 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1551 switch (EntrySize) {
1552 default: assert(0 && "Size of jump table not supported yet."); break;
1553 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1554 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1557 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1558 // For PIC, the sequence is:
1559 // BRIND(load(Jumptable + index) + RelocBase)
1560 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1562 if (TLI.usesGlobalOffsetTable())
1563 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1566 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1567 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1568 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1570 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1576 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1577 // Ensure that libcalls are emitted before a return.
1578 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1579 Tmp1 = LegalizeOp(Tmp1);
1580 LastCALLSEQ_END = DAG.getEntryNode();
1582 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1583 case Expand: assert(0 && "It's impossible to expand bools");
1585 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1588 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1590 // The top bits of the promoted condition are not necessarily zero, ensure
1591 // that the value is properly zero extended.
1592 if (!DAG.MaskedValueIsZero(Tmp2,
1593 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1594 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1598 // Basic block destination (Op#2) is always legal.
1599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1601 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1602 default: assert(0 && "This action is not supported yet!");
1603 case TargetLowering::Legal: break;
1604 case TargetLowering::Custom:
1605 Tmp1 = TLI.LowerOperation(Result, DAG);
1606 if (Tmp1.Val) Result = Tmp1;
1608 case TargetLowering::Expand:
1609 // Expand brcond's setcc into its constituent parts and create a BR_CC
1611 if (Tmp2.getOpcode() == ISD::SETCC) {
1612 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1613 Tmp2.getOperand(0), Tmp2.getOperand(1),
1614 Node->getOperand(2));
1616 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1617 DAG.getCondCode(ISD::SETNE), Tmp2,
1618 DAG.getConstant(0, Tmp2.getValueType()),
1619 Node->getOperand(2));
1625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1626 // Ensure that libcalls are emitted before a branch.
1627 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1628 Tmp1 = LegalizeOp(Tmp1);
1629 Tmp2 = Node->getOperand(2); // LHS
1630 Tmp3 = Node->getOperand(3); // RHS
1631 Tmp4 = Node->getOperand(1); // CC
1633 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1634 LastCALLSEQ_END = DAG.getEntryNode();
1636 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1637 // the LHS is a legal SETCC itself. In this case, we need to compare
1638 // the result against zero to select between true and false values.
1639 if (Tmp3.Val == 0) {
1640 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1641 Tmp4 = DAG.getCondCode(ISD::SETNE);
1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1645 Node->getOperand(4));
1647 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1648 default: assert(0 && "Unexpected action for BR_CC!");
1649 case TargetLowering::Legal: break;
1650 case TargetLowering::Custom:
1651 Tmp4 = TLI.LowerOperation(Result, DAG);
1652 if (Tmp4.Val) Result = Tmp4;
1657 LoadSDNode *LD = cast<LoadSDNode>(Node);
1658 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1659 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1661 ISD::LoadExtType ExtType = LD->getExtensionType();
1662 if (ExtType == ISD::NON_EXTLOAD) {
1663 MVT::ValueType VT = Node->getValueType(0);
1664 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1665 Tmp3 = Result.getValue(0);
1666 Tmp4 = Result.getValue(1);
1668 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1669 default: assert(0 && "This action is not supported yet!");
1670 case TargetLowering::Legal:
1671 // If this is an unaligned load and the target doesn't support it,
1673 if (!TLI.allowsUnalignedMemoryAccesses()) {
1674 unsigned ABIAlignment = TLI.getTargetData()->
1675 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1676 if (LD->getAlignment() < ABIAlignment){
1677 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1679 Tmp3 = Result.getOperand(0);
1680 Tmp4 = Result.getOperand(1);
1681 Tmp3 = LegalizeOp(Tmp3);
1682 Tmp4 = LegalizeOp(Tmp4);
1686 case TargetLowering::Custom:
1687 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1689 Tmp3 = LegalizeOp(Tmp1);
1690 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1693 case TargetLowering::Promote: {
1694 // Only promote a load of vector type to another.
1695 assert(MVT::isVector(VT) && "Cannot promote this load!");
1696 // Change base type to a different vector type.
1697 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1699 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1700 LD->getSrcValueOffset(),
1701 LD->isVolatile(), LD->getAlignment());
1702 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1703 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1707 // Since loads produce two values, make sure to remember that we
1708 // legalized both of them.
1709 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1710 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1711 return Op.ResNo ? Tmp4 : Tmp3;
1713 MVT::ValueType SrcVT = LD->getLoadedVT();
1714 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1715 default: assert(0 && "This action is not supported yet!");
1716 case TargetLowering::Promote:
1717 assert(SrcVT == MVT::i1 &&
1718 "Can only promote extending LOAD from i1 -> i8!");
1719 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1720 LD->getSrcValue(), LD->getSrcValueOffset(),
1721 MVT::i8, LD->isVolatile(), LD->getAlignment());
1722 Tmp1 = Result.getValue(0);
1723 Tmp2 = Result.getValue(1);
1725 case TargetLowering::Custom:
1728 case TargetLowering::Legal:
1729 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1730 Tmp1 = Result.getValue(0);
1731 Tmp2 = Result.getValue(1);
1734 Tmp3 = TLI.LowerOperation(Result, DAG);
1736 Tmp1 = LegalizeOp(Tmp3);
1737 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1740 // If this is an unaligned load and the target doesn't support it,
1742 if (!TLI.allowsUnalignedMemoryAccesses()) {
1743 unsigned ABIAlignment = TLI.getTargetData()->
1744 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1745 if (LD->getAlignment() < ABIAlignment){
1746 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1748 Tmp1 = Result.getOperand(0);
1749 Tmp2 = Result.getOperand(1);
1750 Tmp1 = LegalizeOp(Tmp1);
1751 Tmp2 = LegalizeOp(Tmp2);
1756 case TargetLowering::Expand:
1757 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1758 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1759 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1760 LD->getSrcValueOffset(),
1761 LD->isVolatile(), LD->getAlignment());
1762 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1763 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1764 Tmp2 = LegalizeOp(Load.getValue(1));
1767 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1768 // Turn the unsupported load into an EXTLOAD followed by an explicit
1769 // zero/sign extend inreg.
1770 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1771 Tmp1, Tmp2, LD->getSrcValue(),
1772 LD->getSrcValueOffset(), SrcVT,
1773 LD->isVolatile(), LD->getAlignment());
1775 if (ExtType == ISD::SEXTLOAD)
1776 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1777 Result, DAG.getValueType(SrcVT));
1779 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1780 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1781 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1784 // Since loads produce two values, make sure to remember that we legalized
1786 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1787 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1788 return Op.ResNo ? Tmp2 : Tmp1;
1791 case ISD::EXTRACT_ELEMENT: {
1792 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1793 switch (getTypeAction(OpTy)) {
1794 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1796 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1798 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1799 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1800 TLI.getShiftAmountTy()));
1801 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1804 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1805 Node->getOperand(0));
1809 // Get both the low and high parts.
1810 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1811 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1812 Result = Tmp2; // 1 -> Hi
1814 Result = Tmp1; // 0 -> Lo
1820 case ISD::CopyToReg:
1821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1823 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1824 "Register type must be legal!");
1825 // Legalize the incoming value (must be a legal type).
1826 Tmp2 = LegalizeOp(Node->getOperand(2));
1827 if (Node->getNumValues() == 1) {
1828 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1830 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1831 if (Node->getNumOperands() == 4) {
1832 Tmp3 = LegalizeOp(Node->getOperand(3));
1833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1839 // Since this produces two values, make sure to remember that we legalized
1841 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1842 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1850 // Ensure that libcalls are emitted before a return.
1851 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1852 Tmp1 = LegalizeOp(Tmp1);
1853 LastCALLSEQ_END = DAG.getEntryNode();
1855 switch (Node->getNumOperands()) {
1857 Tmp2 = Node->getOperand(1);
1858 Tmp3 = Node->getOperand(2); // Signness
1859 switch (getTypeAction(Tmp2.getValueType())) {
1861 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1864 if (!MVT::isVector(Tmp2.getValueType())) {
1866 ExpandOp(Tmp2, Lo, Hi);
1868 // Big endian systems want the hi reg first.
1869 if (!TLI.isLittleEndian())
1873 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1875 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1876 Result = LegalizeOp(Result);
1878 SDNode *InVal = Tmp2.Val;
1879 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1880 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1882 // Figure out if there is a simple type corresponding to this Vector
1883 // type. If so, convert to the vector type.
1884 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1885 if (TLI.isTypeLegal(TVT)) {
1886 // Turn this into a return of the vector type.
1887 Tmp2 = LegalizeOp(Tmp2);
1888 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1889 } else if (NumElems == 1) {
1890 // Turn this into a return of the scalar type.
1891 Tmp2 = ScalarizeVectorOp(Tmp2);
1892 Tmp2 = LegalizeOp(Tmp2);
1893 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1895 // FIXME: Returns of gcc generic vectors smaller than a legal type
1896 // should be returned in integer registers!
1898 // The scalarized value type may not be legal, e.g. it might require
1899 // promotion or expansion. Relegalize the return.
1900 Result = LegalizeOp(Result);
1902 // FIXME: Returns of gcc generic vectors larger than a legal vector
1903 // type should be returned by reference!
1905 SplitVectorOp(Tmp2, Lo, Hi);
1906 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1907 Result = LegalizeOp(Result);
1912 Tmp2 = PromoteOp(Node->getOperand(1));
1913 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1914 Result = LegalizeOp(Result);
1919 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1921 default: { // ret <values>
1922 SmallVector<SDOperand, 8> NewValues;
1923 NewValues.push_back(Tmp1);
1924 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1925 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1927 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1928 NewValues.push_back(Node->getOperand(i+1));
1932 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1933 "FIXME: TODO: implement returning non-legal vector types!");
1934 ExpandOp(Node->getOperand(i), Lo, Hi);
1935 NewValues.push_back(Lo);
1936 NewValues.push_back(Node->getOperand(i+1));
1938 NewValues.push_back(Hi);
1939 NewValues.push_back(Node->getOperand(i+1));
1944 assert(0 && "Can't promote multiple return value yet!");
1947 if (NewValues.size() == Node->getNumOperands())
1948 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1950 Result = DAG.getNode(ISD::RET, MVT::Other,
1951 &NewValues[0], NewValues.size());
1956 if (Result.getOpcode() == ISD::RET) {
1957 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1958 default: assert(0 && "This action is not supported yet!");
1959 case TargetLowering::Legal: break;
1960 case TargetLowering::Custom:
1961 Tmp1 = TLI.LowerOperation(Result, DAG);
1962 if (Tmp1.Val) Result = Tmp1;
1968 StoreSDNode *ST = cast<StoreSDNode>(Node);
1969 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1970 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1971 int SVOffset = ST->getSrcValueOffset();
1972 unsigned Alignment = ST->getAlignment();
1973 bool isVolatile = ST->isVolatile();
1975 if (!ST->isTruncatingStore()) {
1976 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1977 // FIXME: We shouldn't do this for TargetConstantFP's.
1978 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1979 // to phase ordering between legalized code and the dag combiner. This
1980 // probably means that we need to integrate dag combiner and legalizer
1982 // We generally can't do this one for long doubles.
1983 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1984 if (CFP->getValueType(0) == MVT::f32) {
1985 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
1986 convertToAPInt().getZExtValue(),
1988 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1989 SVOffset, isVolatile, Alignment);
1991 } else if (CFP->getValueType(0) == MVT::f64) {
1992 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
1993 getZExtValue(), MVT::i64);
1994 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1995 SVOffset, isVolatile, Alignment);
2000 switch (getTypeAction(ST->getStoredVT())) {
2002 Tmp3 = LegalizeOp(ST->getValue());
2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2006 MVT::ValueType VT = Tmp3.getValueType();
2007 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2008 default: assert(0 && "This action is not supported yet!");
2009 case TargetLowering::Legal:
2010 // If this is an unaligned store and the target doesn't support it,
2012 if (!TLI.allowsUnalignedMemoryAccesses()) {
2013 unsigned ABIAlignment = TLI.getTargetData()->
2014 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2015 if (ST->getAlignment() < ABIAlignment)
2016 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2020 case TargetLowering::Custom:
2021 Tmp1 = TLI.LowerOperation(Result, DAG);
2022 if (Tmp1.Val) Result = Tmp1;
2024 case TargetLowering::Promote:
2025 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2026 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2027 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2028 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2029 ST->getSrcValue(), SVOffset, isVolatile,
2036 // Truncate the value and store the result.
2037 Tmp3 = PromoteOp(ST->getValue());
2038 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2039 SVOffset, ST->getStoredVT(),
2040 isVolatile, Alignment);
2044 unsigned IncrementSize = 0;
2047 // If this is a vector type, then we have to calculate the increment as
2048 // the product of the element size in bytes, and the number of elements
2049 // in the high half of the vector.
2050 if (MVT::isVector(ST->getValue().getValueType())) {
2051 SDNode *InVal = ST->getValue().Val;
2052 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2053 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2055 // Figure out if there is a simple type corresponding to this Vector
2056 // type. If so, convert to the vector type.
2057 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2058 if (TLI.isTypeLegal(TVT)) {
2059 // Turn this into a normal store of the vector type.
2060 Tmp3 = LegalizeOp(Node->getOperand(1));
2061 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2062 SVOffset, isVolatile, Alignment);
2063 Result = LegalizeOp(Result);
2065 } else if (NumElems == 1) {
2066 // Turn this into a normal store of the scalar type.
2067 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2068 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2069 SVOffset, isVolatile, Alignment);
2070 // The scalarized value type may not be legal, e.g. it might require
2071 // promotion or expansion. Relegalize the scalar store.
2072 Result = LegalizeOp(Result);
2075 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2076 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2079 ExpandOp(Node->getOperand(1), Lo, Hi);
2080 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2082 if (!TLI.isLittleEndian())
2086 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2087 SVOffset, isVolatile, Alignment);
2089 if (Hi.Val == NULL) {
2090 // Must be int <-> float one-to-one expansion.
2095 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2096 getIntPtrConstant(IncrementSize));
2097 assert(isTypeLegal(Tmp2.getValueType()) &&
2098 "Pointers must be legal!");
2099 SVOffset += IncrementSize;
2100 if (Alignment > IncrementSize)
2101 Alignment = IncrementSize;
2102 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2103 SVOffset, isVolatile, Alignment);
2104 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2109 assert(isTypeLegal(ST->getValue().getValueType()) &&
2110 "Cannot handle illegal TRUNCSTORE yet!");
2111 Tmp3 = LegalizeOp(ST->getValue());
2113 // The only promote case we handle is TRUNCSTORE:i1 X into
2114 // -> TRUNCSTORE:i8 (and X, 1)
2115 if (ST->getStoredVT() == MVT::i1 &&
2116 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2117 // Promote the bool to a mask then store.
2118 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2119 DAG.getConstant(1, Tmp3.getValueType()));
2120 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2122 isVolatile, Alignment);
2123 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2124 Tmp2 != ST->getBasePtr()) {
2125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2129 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2130 switch (TLI.getStoreXAction(StVT)) {
2131 default: assert(0 && "This action is not supported yet!");
2132 case TargetLowering::Legal:
2133 // If this is an unaligned store and the target doesn't support it,
2135 if (!TLI.allowsUnalignedMemoryAccesses()) {
2136 unsigned ABIAlignment = TLI.getTargetData()->
2137 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2138 if (ST->getAlignment() < ABIAlignment)
2139 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2143 case TargetLowering::Custom:
2144 Tmp1 = TLI.LowerOperation(Result, DAG);
2145 if (Tmp1.Val) Result = Tmp1;
2152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2153 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2155 case ISD::STACKSAVE:
2156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2157 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2158 Tmp1 = Result.getValue(0);
2159 Tmp2 = Result.getValue(1);
2161 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2162 default: assert(0 && "This action is not supported yet!");
2163 case TargetLowering::Legal: break;
2164 case TargetLowering::Custom:
2165 Tmp3 = TLI.LowerOperation(Result, DAG);
2167 Tmp1 = LegalizeOp(Tmp3);
2168 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2171 case TargetLowering::Expand:
2172 // Expand to CopyFromReg if the target set
2173 // StackPointerRegisterToSaveRestore.
2174 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2175 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2176 Node->getValueType(0));
2177 Tmp2 = Tmp1.getValue(1);
2179 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2180 Tmp2 = Node->getOperand(0);
2185 // Since stacksave produce two values, make sure to remember that we
2186 // legalized both of them.
2187 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2188 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2189 return Op.ResNo ? Tmp2 : Tmp1;
2191 case ISD::STACKRESTORE:
2192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2193 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2196 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2197 default: assert(0 && "This action is not supported yet!");
2198 case TargetLowering::Legal: break;
2199 case TargetLowering::Custom:
2200 Tmp1 = TLI.LowerOperation(Result, DAG);
2201 if (Tmp1.Val) Result = Tmp1;
2203 case TargetLowering::Expand:
2204 // Expand to CopyToReg if the target set
2205 // StackPointerRegisterToSaveRestore.
2206 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2207 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2215 case ISD::READCYCLECOUNTER:
2216 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2217 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2218 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2219 Node->getValueType(0))) {
2220 default: assert(0 && "This action is not supported yet!");
2221 case TargetLowering::Legal:
2222 Tmp1 = Result.getValue(0);
2223 Tmp2 = Result.getValue(1);
2225 case TargetLowering::Custom:
2226 Result = TLI.LowerOperation(Result, DAG);
2227 Tmp1 = LegalizeOp(Result.getValue(0));
2228 Tmp2 = LegalizeOp(Result.getValue(1));
2232 // Since rdcc produce two values, make sure to remember that we legalized
2234 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2235 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2239 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2240 case Expand: assert(0 && "It's impossible to expand bools");
2242 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2245 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2246 // Make sure the condition is either zero or one.
2247 if (!DAG.MaskedValueIsZero(Tmp1,
2248 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2249 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2252 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2253 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2255 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2257 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2258 default: assert(0 && "This action is not supported yet!");
2259 case TargetLowering::Legal: break;
2260 case TargetLowering::Custom: {
2261 Tmp1 = TLI.LowerOperation(Result, DAG);
2262 if (Tmp1.Val) Result = Tmp1;
2265 case TargetLowering::Expand:
2266 if (Tmp1.getOpcode() == ISD::SETCC) {
2267 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2269 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2271 Result = DAG.getSelectCC(Tmp1,
2272 DAG.getConstant(0, Tmp1.getValueType()),
2273 Tmp2, Tmp3, ISD::SETNE);
2276 case TargetLowering::Promote: {
2277 MVT::ValueType NVT =
2278 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2279 unsigned ExtOp, TruncOp;
2280 if (MVT::isVector(Tmp2.getValueType())) {
2281 ExtOp = ISD::BIT_CONVERT;
2282 TruncOp = ISD::BIT_CONVERT;
2283 } else if (MVT::isInteger(Tmp2.getValueType())) {
2284 ExtOp = ISD::ANY_EXTEND;
2285 TruncOp = ISD::TRUNCATE;
2287 ExtOp = ISD::FP_EXTEND;
2288 TruncOp = ISD::FP_ROUND;
2290 // Promote each of the values to the new type.
2291 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2292 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2293 // Perform the larger operation, then round down.
2294 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2295 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2300 case ISD::SELECT_CC: {
2301 Tmp1 = Node->getOperand(0); // LHS
2302 Tmp2 = Node->getOperand(1); // RHS
2303 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2304 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2305 SDOperand CC = Node->getOperand(4);
2307 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2309 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2310 // the LHS is a legal SETCC itself. In this case, we need to compare
2311 // the result against zero to select between true and false values.
2312 if (Tmp2.Val == 0) {
2313 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2314 CC = DAG.getCondCode(ISD::SETNE);
2316 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2318 // Everything is legal, see if we should expand this op or something.
2319 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2320 default: assert(0 && "This action is not supported yet!");
2321 case TargetLowering::Legal: break;
2322 case TargetLowering::Custom:
2323 Tmp1 = TLI.LowerOperation(Result, DAG);
2324 if (Tmp1.Val) Result = Tmp1;
2330 Tmp1 = Node->getOperand(0);
2331 Tmp2 = Node->getOperand(1);
2332 Tmp3 = Node->getOperand(2);
2333 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2335 // If we had to Expand the SetCC operands into a SELECT node, then it may
2336 // not always be possible to return a true LHS & RHS. In this case, just
2337 // return the value we legalized, returned in the LHS
2338 if (Tmp2.Val == 0) {
2343 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2344 default: assert(0 && "Cannot handle this action for SETCC yet!");
2345 case TargetLowering::Custom:
2348 case TargetLowering::Legal:
2349 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2351 Tmp4 = TLI.LowerOperation(Result, DAG);
2352 if (Tmp4.Val) Result = Tmp4;
2355 case TargetLowering::Promote: {
2356 // First step, figure out the appropriate operation to use.
2357 // Allow SETCC to not be supported for all legal data types
2358 // Mostly this targets FP
2359 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2360 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2362 // Scan for the appropriate larger type to use.
2364 NewInTy = (MVT::ValueType)(NewInTy+1);
2366 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2367 "Fell off of the edge of the integer world");
2368 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2369 "Fell off of the edge of the floating point world");
2371 // If the target supports SETCC of this type, use it.
2372 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2375 if (MVT::isInteger(NewInTy))
2376 assert(0 && "Cannot promote Legal Integer SETCC yet");
2378 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2379 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2381 Tmp1 = LegalizeOp(Tmp1);
2382 Tmp2 = LegalizeOp(Tmp2);
2383 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2384 Result = LegalizeOp(Result);
2387 case TargetLowering::Expand:
2388 // Expand a setcc node into a select_cc of the same condition, lhs, and
2389 // rhs that selects between const 1 (true) and const 0 (false).
2390 MVT::ValueType VT = Node->getValueType(0);
2391 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2392 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2399 case ISD::MEMMOVE: {
2400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2401 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2403 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2404 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2405 case Expand: assert(0 && "Cannot expand a byte!");
2407 Tmp3 = LegalizeOp(Node->getOperand(2));
2410 Tmp3 = PromoteOp(Node->getOperand(2));
2414 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2418 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2420 // Length is too big, just take the lo-part of the length.
2422 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2426 Tmp4 = LegalizeOp(Node->getOperand(3));
2429 Tmp4 = PromoteOp(Node->getOperand(3));
2434 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2435 case Expand: assert(0 && "Cannot expand this yet!");
2437 Tmp5 = LegalizeOp(Node->getOperand(4));
2440 Tmp5 = PromoteOp(Node->getOperand(4));
2444 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2445 default: assert(0 && "This action not implemented for this operation!");
2446 case TargetLowering::Custom:
2449 case TargetLowering::Legal:
2450 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2452 Tmp1 = TLI.LowerOperation(Result, DAG);
2453 if (Tmp1.Val) Result = Tmp1;
2456 case TargetLowering::Expand: {
2457 // Otherwise, the target does not support this operation. Lower the
2458 // operation to an explicit libcall as appropriate.
2459 MVT::ValueType IntPtr = TLI.getPointerTy();
2460 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2461 TargetLowering::ArgListTy Args;
2462 TargetLowering::ArgListEntry Entry;
2464 const char *FnName = 0;
2465 if (Node->getOpcode() == ISD::MEMSET) {
2466 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2467 Args.push_back(Entry);
2468 // Extend the (previously legalized) ubyte argument to be an int value
2470 if (Tmp3.getValueType() > MVT::i32)
2471 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2473 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2474 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2475 Args.push_back(Entry);
2476 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2477 Args.push_back(Entry);
2480 } else if (Node->getOpcode() == ISD::MEMCPY ||
2481 Node->getOpcode() == ISD::MEMMOVE) {
2482 Entry.Ty = IntPtrTy;
2483 Entry.Node = Tmp2; Args.push_back(Entry);
2484 Entry.Node = Tmp3; Args.push_back(Entry);
2485 Entry.Node = Tmp4; Args.push_back(Entry);
2486 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2488 assert(0 && "Unknown op!");
2491 std::pair<SDOperand,SDOperand> CallResult =
2492 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2493 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2494 Result = CallResult.second;
2501 case ISD::SHL_PARTS:
2502 case ISD::SRA_PARTS:
2503 case ISD::SRL_PARTS: {
2504 SmallVector<SDOperand, 8> Ops;
2505 bool Changed = false;
2506 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2507 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2508 Changed |= Ops.back() != Node->getOperand(i);
2511 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2513 switch (TLI.getOperationAction(Node->getOpcode(),
2514 Node->getValueType(0))) {
2515 default: assert(0 && "This action is not supported yet!");
2516 case TargetLowering::Legal: break;
2517 case TargetLowering::Custom:
2518 Tmp1 = TLI.LowerOperation(Result, DAG);
2520 SDOperand Tmp2, RetVal(0, 0);
2521 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2522 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2523 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2527 assert(RetVal.Val && "Illegal result number");
2533 // Since these produce multiple values, make sure to remember that we
2534 // legalized all of them.
2535 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2536 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2537 return Result.getValue(Op.ResNo);
2558 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2559 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2560 case Expand: assert(0 && "Not possible");
2562 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2565 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2569 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2571 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2572 default: assert(0 && "BinOp legalize operation not supported");
2573 case TargetLowering::Legal: break;
2574 case TargetLowering::Custom:
2575 Tmp1 = TLI.LowerOperation(Result, DAG);
2576 if (Tmp1.Val) Result = Tmp1;
2578 case TargetLowering::Expand: {
2579 if (Node->getValueType(0) == MVT::i32) {
2580 switch (Node->getOpcode()) {
2581 default: assert(0 && "Do not know how to expand this integer BinOp!");
2584 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2585 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2587 bool isSigned = Node->getOpcode() == ISD::SDIV;
2588 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2593 assert(MVT::isVector(Node->getValueType(0)) &&
2594 "Cannot expand this binary operator!");
2595 // Expand the operation into a bunch of nasty scalar code.
2596 SmallVector<SDOperand, 8> Ops;
2597 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2598 MVT::ValueType PtrVT = TLI.getPointerTy();
2599 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2601 SDOperand Idx = DAG.getConstant(i, PtrVT);
2602 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2603 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2604 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2606 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2607 &Ops[0], Ops.size());
2610 case TargetLowering::Promote: {
2611 switch (Node->getOpcode()) {
2612 default: assert(0 && "Do not know how to promote this BinOp!");
2616 MVT::ValueType OVT = Node->getValueType(0);
2617 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2618 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2619 // Bit convert each of the values to the new type.
2620 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2621 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2622 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2623 // Bit convert the result back the original type.
2624 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2632 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2633 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2634 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2635 case Expand: assert(0 && "Not possible");
2637 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2640 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2646 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2647 default: assert(0 && "Operation not supported");
2648 case TargetLowering::Custom:
2649 Tmp1 = TLI.LowerOperation(Result, DAG);
2650 if (Tmp1.Val) Result = Tmp1;
2652 case TargetLowering::Legal: break;
2653 case TargetLowering::Expand: {
2654 // If this target supports fabs/fneg natively and select is cheap,
2655 // do this efficiently.
2656 if (!TLI.isSelectExpensive() &&
2657 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2658 TargetLowering::Legal &&
2659 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2660 TargetLowering::Legal) {
2661 // Get the sign bit of the RHS.
2662 MVT::ValueType IVT =
2663 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2664 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2665 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2666 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2667 // Get the absolute value of the result.
2668 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2669 // Select between the nabs and abs value based on the sign bit of
2671 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2672 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2675 Result = LegalizeOp(Result);
2679 // Otherwise, do bitwise ops!
2680 MVT::ValueType NVT =
2681 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2682 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2683 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2684 Result = LegalizeOp(Result);
2692 Tmp1 = LegalizeOp(Node->getOperand(0));
2693 Tmp2 = LegalizeOp(Node->getOperand(1));
2694 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2695 // Since this produces two values, make sure to remember that we legalized
2697 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2698 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2703 Tmp1 = LegalizeOp(Node->getOperand(0));
2704 Tmp2 = LegalizeOp(Node->getOperand(1));
2705 Tmp3 = LegalizeOp(Node->getOperand(2));
2706 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2707 // Since this produces two values, make sure to remember that we legalized
2709 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2710 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2713 case ISD::BUILD_PAIR: {
2714 MVT::ValueType PairTy = Node->getValueType(0);
2715 // TODO: handle the case where the Lo and Hi operands are not of legal type
2716 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2717 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2718 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2719 case TargetLowering::Promote:
2720 case TargetLowering::Custom:
2721 assert(0 && "Cannot promote/custom this yet!");
2722 case TargetLowering::Legal:
2723 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2724 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2726 case TargetLowering::Expand:
2727 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2728 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2729 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2730 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2731 TLI.getShiftAmountTy()));
2732 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2741 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2742 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2744 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2745 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2746 case TargetLowering::Custom:
2749 case TargetLowering::Legal:
2750 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2752 Tmp1 = TLI.LowerOperation(Result, DAG);
2753 if (Tmp1.Val) Result = Tmp1;
2756 case TargetLowering::Expand:
2757 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2758 bool isSigned = DivOpc == ISD::SDIV;
2759 if (MVT::isInteger(Node->getValueType(0))) {
2760 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2761 TargetLowering::Legal) {
2763 MVT::ValueType VT = Node->getValueType(0);
2764 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2765 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2766 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2768 assert(Node->getValueType(0) == MVT::i32 &&
2769 "Cannot expand this binary operator!");
2770 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2771 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2773 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2776 // Floating point mod -> fmod libcall.
2777 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2778 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2780 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2781 false/*sign irrelevant*/, Dummy);
2787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2788 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2790 MVT::ValueType VT = Node->getValueType(0);
2791 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2792 default: assert(0 && "This action is not supported yet!");
2793 case TargetLowering::Custom:
2796 case TargetLowering::Legal:
2797 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2798 Result = Result.getValue(0);
2799 Tmp1 = Result.getValue(1);
2802 Tmp2 = TLI.LowerOperation(Result, DAG);
2804 Result = LegalizeOp(Tmp2);
2805 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2809 case TargetLowering::Expand: {
2810 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2811 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2812 SV->getValue(), SV->getOffset());
2813 // Increment the pointer, VAList, to the next vaarg
2814 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2815 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2816 TLI.getPointerTy()));
2817 // Store the incremented VAList to the legalized pointer
2818 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2820 // Load the actual argument out of the pointer VAList
2821 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2822 Tmp1 = LegalizeOp(Result.getValue(1));
2823 Result = LegalizeOp(Result);
2827 // Since VAARG produces two values, make sure to remember that we
2828 // legalized both of them.
2829 AddLegalizedOperand(SDOperand(Node, 0), Result);
2830 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2831 return Op.ResNo ? Tmp1 : Result;
2835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2836 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2837 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2839 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2840 default: assert(0 && "This action is not supported yet!");
2841 case TargetLowering::Custom:
2844 case TargetLowering::Legal:
2845 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2846 Node->getOperand(3), Node->getOperand(4));
2848 Tmp1 = TLI.LowerOperation(Result, DAG);
2849 if (Tmp1.Val) Result = Tmp1;
2852 case TargetLowering::Expand:
2853 // This defaults to loading a pointer from the input and storing it to the
2854 // output, returning the chain.
2855 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2856 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2857 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2859 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2866 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2867 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2869 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2870 default: assert(0 && "This action is not supported yet!");
2871 case TargetLowering::Custom:
2874 case TargetLowering::Legal:
2875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2877 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2878 if (Tmp1.Val) Result = Tmp1;
2881 case TargetLowering::Expand:
2882 Result = Tmp1; // Default to a no-op, return the chain
2888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2889 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2891 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2893 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2894 default: assert(0 && "This action is not supported yet!");
2895 case TargetLowering::Legal: break;
2896 case TargetLowering::Custom:
2897 Tmp1 = TLI.LowerOperation(Result, DAG);
2898 if (Tmp1.Val) Result = Tmp1;
2905 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2906 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2907 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2908 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2910 assert(0 && "ROTL/ROTR legalize operation not supported");
2912 case TargetLowering::Legal:
2914 case TargetLowering::Custom:
2915 Tmp1 = TLI.LowerOperation(Result, DAG);
2916 if (Tmp1.Val) Result = Tmp1;
2918 case TargetLowering::Promote:
2919 assert(0 && "Do not know how to promote ROTL/ROTR");
2921 case TargetLowering::Expand:
2922 assert(0 && "Do not know how to expand ROTL/ROTR");
2928 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2929 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2930 case TargetLowering::Custom:
2931 assert(0 && "Cannot custom legalize this yet!");
2932 case TargetLowering::Legal:
2933 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2935 case TargetLowering::Promote: {
2936 MVT::ValueType OVT = Tmp1.getValueType();
2937 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2938 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2940 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2941 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2942 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2943 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2946 case TargetLowering::Expand:
2947 Result = ExpandBSWAP(Tmp1);
2955 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2956 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2957 case TargetLowering::Custom:
2958 case TargetLowering::Legal:
2959 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2960 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
2961 TargetLowering::Custom) {
2962 Tmp1 = TLI.LowerOperation(Result, DAG);
2968 case TargetLowering::Promote: {
2969 MVT::ValueType OVT = Tmp1.getValueType();
2970 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2972 // Zero extend the argument.
2973 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2974 // Perform the larger operation, then subtract if needed.
2975 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2976 switch (Node->getOpcode()) {
2981 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2982 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2983 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2985 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2986 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2989 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2990 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2991 DAG.getConstant(MVT::getSizeInBits(NVT) -
2992 MVT::getSizeInBits(OVT), NVT));
2997 case TargetLowering::Expand:
2998 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3009 Tmp1 = LegalizeOp(Node->getOperand(0));
3010 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3011 case TargetLowering::Promote:
3012 case TargetLowering::Custom:
3015 case TargetLowering::Legal:
3016 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3018 Tmp1 = TLI.LowerOperation(Result, DAG);
3019 if (Tmp1.Val) Result = Tmp1;
3022 case TargetLowering::Expand:
3023 switch (Node->getOpcode()) {
3024 default: assert(0 && "Unreachable!");
3026 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3027 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3028 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3031 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3032 MVT::ValueType VT = Node->getValueType(0);
3033 Tmp2 = DAG.getConstantFP(0.0, VT);
3034 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3035 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3036 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3042 MVT::ValueType VT = Node->getValueType(0);
3043 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3044 switch(Node->getOpcode()) {
3046 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
3049 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
3052 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
3054 default: assert(0 && "Unreachable!");
3057 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3058 false/*sign irrelevant*/, Dummy);
3066 // We always lower FPOWI into a libcall. No target support it yet.
3067 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
3068 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
3070 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3071 false/*sign irrelevant*/, Dummy);
3074 case ISD::BIT_CONVERT:
3075 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3076 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3077 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3078 // The input has to be a vector type, we have to either scalarize it, pack
3079 // it, or convert it based on whether the input vector type is legal.
3080 SDNode *InVal = Node->getOperand(0).Val;
3081 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3082 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3084 // Figure out if there is a simple type corresponding to this Vector
3085 // type. If so, convert to the vector type.
3086 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3087 if (TLI.isTypeLegal(TVT)) {
3088 // Turn this into a bit convert of the vector input.
3089 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3090 LegalizeOp(Node->getOperand(0)));
3092 } else if (NumElems == 1) {
3093 // Turn this into a bit convert of the scalar input.
3094 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3095 ScalarizeVectorOp(Node->getOperand(0)));
3098 // FIXME: UNIMP! Store then reload
3099 assert(0 && "Cast from unsupported vector type not implemented yet!");
3102 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3103 Node->getOperand(0).getValueType())) {
3104 default: assert(0 && "Unknown operation action!");
3105 case TargetLowering::Expand:
3106 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3108 case TargetLowering::Legal:
3109 Tmp1 = LegalizeOp(Node->getOperand(0));
3110 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3116 // Conversion operators. The source and destination have different types.
3117 case ISD::SINT_TO_FP:
3118 case ISD::UINT_TO_FP: {
3119 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3120 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3122 switch (TLI.getOperationAction(Node->getOpcode(),
3123 Node->getOperand(0).getValueType())) {
3124 default: assert(0 && "Unknown operation action!");
3125 case TargetLowering::Custom:
3128 case TargetLowering::Legal:
3129 Tmp1 = LegalizeOp(Node->getOperand(0));
3130 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3132 Tmp1 = TLI.LowerOperation(Result, DAG);
3133 if (Tmp1.Val) Result = Tmp1;
3136 case TargetLowering::Expand:
3137 Result = ExpandLegalINT_TO_FP(isSigned,
3138 LegalizeOp(Node->getOperand(0)),
3139 Node->getValueType(0));
3141 case TargetLowering::Promote:
3142 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3143 Node->getValueType(0),
3149 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3150 Node->getValueType(0), Node->getOperand(0));
3153 Tmp1 = PromoteOp(Node->getOperand(0));
3155 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3156 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3158 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3159 Node->getOperand(0).getValueType());
3161 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3162 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3168 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3170 Tmp1 = LegalizeOp(Node->getOperand(0));
3171 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3174 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3176 // Since the result is legal, we should just be able to truncate the low
3177 // part of the source.
3178 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3181 Result = PromoteOp(Node->getOperand(0));
3182 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3187 case ISD::FP_TO_SINT:
3188 case ISD::FP_TO_UINT:
3189 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3191 Tmp1 = LegalizeOp(Node->getOperand(0));
3193 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3194 default: assert(0 && "Unknown operation action!");
3195 case TargetLowering::Custom:
3198 case TargetLowering::Legal:
3199 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3201 Tmp1 = TLI.LowerOperation(Result, DAG);
3202 if (Tmp1.Val) Result = Tmp1;
3205 case TargetLowering::Promote:
3206 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3207 Node->getOpcode() == ISD::FP_TO_SINT);
3209 case TargetLowering::Expand:
3210 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3211 SDOperand True, False;
3212 MVT::ValueType VT = Node->getOperand(0).getValueType();
3213 MVT::ValueType NVT = Node->getValueType(0);
3214 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3215 Tmp2 = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT),
3216 1ULL << ShiftAmt)), VT);
3217 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3218 Node->getOperand(0), Tmp2, ISD::SETLT);
3219 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3220 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3221 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3223 False = DAG.getNode(ISD::XOR, NVT, False,
3224 DAG.getConstant(1ULL << ShiftAmt, NVT));
3225 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3228 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3234 // Convert f32 / f64 to i32 / i64.
3235 MVT::ValueType VT = Op.getValueType();
3236 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3237 switch (Node->getOpcode()) {
3238 case ISD::FP_TO_SINT:
3239 if (Node->getOperand(0).getValueType() == MVT::f32)
3240 LC = (VT == MVT::i32)
3241 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3243 LC = (VT == MVT::i32)
3244 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3246 case ISD::FP_TO_UINT:
3247 if (Node->getOperand(0).getValueType() == MVT::f32)
3248 LC = (VT == MVT::i32)
3249 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3251 LC = (VT == MVT::i32)
3252 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3254 default: assert(0 && "Unreachable!");
3257 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3258 false/*sign irrelevant*/, Dummy);
3262 Tmp1 = PromoteOp(Node->getOperand(0));
3263 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3264 Result = LegalizeOp(Result);
3269 case ISD::FP_EXTEND:
3270 case ISD::FP_ROUND: {
3271 MVT::ValueType newVT = Op.getValueType();
3272 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3273 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3274 // The only way we can lower this is to turn it into a STORE,
3275 // LOAD pair, targetting a temporary location (a stack slot).
3277 // NOTE: there is a choice here between constantly creating new stack
3278 // slots and always reusing the same one. We currently always create
3279 // new ones, as reuse may inhibit scheduling.
3280 MVT::ValueType slotVT =
3281 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3282 const Type *Ty = MVT::getTypeForValueType(slotVT);
3283 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3284 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3285 MachineFunction &MF = DAG.getMachineFunction();
3287 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3288 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3289 if (Node->getOpcode() == ISD::FP_EXTEND) {
3290 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3291 StackSlot, NULL, 0);
3292 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3293 Result, StackSlot, NULL, 0, oldVT);
3295 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3296 StackSlot, NULL, 0, newVT);
3297 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
3303 case ISD::ANY_EXTEND:
3304 case ISD::ZERO_EXTEND:
3305 case ISD::SIGN_EXTEND:
3306 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3307 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3309 Tmp1 = LegalizeOp(Node->getOperand(0));
3310 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3313 switch (Node->getOpcode()) {
3314 case ISD::ANY_EXTEND:
3315 Tmp1 = PromoteOp(Node->getOperand(0));
3316 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3318 case ISD::ZERO_EXTEND:
3319 Result = PromoteOp(Node->getOperand(0));
3320 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3321 Result = DAG.getZeroExtendInReg(Result,
3322 Node->getOperand(0).getValueType());
3324 case ISD::SIGN_EXTEND:
3325 Result = PromoteOp(Node->getOperand(0));
3326 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3327 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3329 DAG.getValueType(Node->getOperand(0).getValueType()));
3331 case ISD::FP_EXTEND:
3332 Result = PromoteOp(Node->getOperand(0));
3333 if (Result.getValueType() != Op.getValueType())
3334 // Dynamically dead while we have only 2 FP types.
3335 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3338 Result = PromoteOp(Node->getOperand(0));
3339 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3344 case ISD::FP_ROUND_INREG:
3345 case ISD::SIGN_EXTEND_INREG: {
3346 Tmp1 = LegalizeOp(Node->getOperand(0));
3347 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3349 // If this operation is not supported, convert it to a shl/shr or load/store
3351 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3352 default: assert(0 && "This action not supported for this op yet!");
3353 case TargetLowering::Legal:
3354 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3356 case TargetLowering::Expand:
3357 // If this is an integer extend and shifts are supported, do that.
3358 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3359 // NOTE: we could fall back on load/store here too for targets without
3360 // SAR. However, it is doubtful that any exist.
3361 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3362 MVT::getSizeInBits(ExtraVT);
3363 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3364 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3365 Node->getOperand(0), ShiftCst);
3366 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3368 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3369 // The only way we can lower this is to turn it into a TRUNCSTORE,
3370 // EXTLOAD pair, targetting a temporary location (a stack slot).
3372 // NOTE: there is a choice here between constantly creating new stack
3373 // slots and always reusing the same one. We currently always create
3374 // new ones, as reuse may inhibit scheduling.
3375 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3376 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3377 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3378 MachineFunction &MF = DAG.getMachineFunction();
3380 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3381 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3382 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3383 StackSlot, NULL, 0, ExtraVT);
3384 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3385 Result, StackSlot, NULL, 0, ExtraVT);
3387 assert(0 && "Unknown op");
3393 case ISD::TRAMPOLINE: {
3395 for (unsigned i = 0; i != 6; ++i)
3396 Ops[i] = LegalizeOp(Node->getOperand(i));
3397 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3398 // The only option for this node is to custom lower it.
3399 Result = TLI.LowerOperation(Result, DAG);
3400 assert(Result.Val && "Should always custom lower!");
3402 // Since trampoline produces two values, make sure to remember that we
3403 // legalized both of them.
3404 Tmp1 = LegalizeOp(Result.getValue(1));
3405 Result = LegalizeOp(Result);
3406 AddLegalizedOperand(SDOperand(Node, 0), Result);
3407 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3408 return Op.ResNo ? Tmp1 : Result;
3412 assert(Result.getValueType() == Op.getValueType() &&
3413 "Bad legalization!");
3415 // Make sure that the generated code is itself legal.
3417 Result = LegalizeOp(Result);
3419 // Note that LegalizeOp may be reentered even from single-use nodes, which
3420 // means that we always must cache transformed nodes.
3421 AddLegalizedOperand(Op, Result);
3425 /// PromoteOp - Given an operation that produces a value in an invalid type,
3426 /// promote it to compute the value into a larger type. The produced value will
3427 /// have the correct bits for the low portion of the register, but no guarantee
3428 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3429 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3430 MVT::ValueType VT = Op.getValueType();
3431 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3432 assert(getTypeAction(VT) == Promote &&
3433 "Caller should expand or legalize operands that are not promotable!");
3434 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3435 "Cannot promote to smaller type!");
3437 SDOperand Tmp1, Tmp2, Tmp3;
3439 SDNode *Node = Op.Val;
3441 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3442 if (I != PromotedNodes.end()) return I->second;
3444 switch (Node->getOpcode()) {
3445 case ISD::CopyFromReg:
3446 assert(0 && "CopyFromReg must be legal!");
3449 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3451 assert(0 && "Do not know how to promote this operator!");
3454 Result = DAG.getNode(ISD::UNDEF, NVT);
3458 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3460 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3461 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3463 case ISD::ConstantFP:
3464 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3465 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3469 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3470 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3471 Node->getOperand(1), Node->getOperand(2));
3475 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3477 Result = LegalizeOp(Node->getOperand(0));
3478 assert(Result.getValueType() >= NVT &&
3479 "This truncation doesn't make sense!");
3480 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3481 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3484 // The truncation is not required, because we don't guarantee anything
3485 // about high bits anyway.
3486 Result = PromoteOp(Node->getOperand(0));
3489 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3490 // Truncate the low part of the expanded value to the result type
3491 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3494 case ISD::SIGN_EXTEND:
3495 case ISD::ZERO_EXTEND:
3496 case ISD::ANY_EXTEND:
3497 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3498 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3500 // Input is legal? Just do extend all the way to the larger type.
3501 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3504 // Promote the reg if it's smaller.
3505 Result = PromoteOp(Node->getOperand(0));
3506 // The high bits are not guaranteed to be anything. Insert an extend.
3507 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3508 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3509 DAG.getValueType(Node->getOperand(0).getValueType()));
3510 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3511 Result = DAG.getZeroExtendInReg(Result,
3512 Node->getOperand(0).getValueType());
3516 case ISD::BIT_CONVERT:
3517 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3518 Result = PromoteOp(Result);
3521 case ISD::FP_EXTEND:
3522 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3524 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3525 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3526 case Promote: assert(0 && "Unreachable with 2 FP types!");
3528 // Input is legal? Do an FP_ROUND_INREG.
3529 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3530 DAG.getValueType(VT));
3535 case ISD::SINT_TO_FP:
3536 case ISD::UINT_TO_FP:
3537 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3539 // No extra round required here.
3540 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3544 Result = PromoteOp(Node->getOperand(0));
3545 if (Node->getOpcode() == ISD::SINT_TO_FP)
3546 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3548 DAG.getValueType(Node->getOperand(0).getValueType()));
3550 Result = DAG.getZeroExtendInReg(Result,
3551 Node->getOperand(0).getValueType());
3552 // No extra round required here.
3553 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3556 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3557 Node->getOperand(0));
3558 // Round if we cannot tolerate excess precision.
3559 if (NoExcessFPPrecision)
3560 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3561 DAG.getValueType(VT));
3566 case ISD::SIGN_EXTEND_INREG:
3567 Result = PromoteOp(Node->getOperand(0));
3568 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3569 Node->getOperand(1));
3571 case ISD::FP_TO_SINT:
3572 case ISD::FP_TO_UINT:
3573 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3576 Tmp1 = Node->getOperand(0);
3579 // The input result is prerounded, so we don't have to do anything
3581 Tmp1 = PromoteOp(Node->getOperand(0));
3584 // If we're promoting a UINT to a larger size, check to see if the new node
3585 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3586 // we can use that instead. This allows us to generate better code for
3587 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3588 // legal, such as PowerPC.
3589 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3590 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3591 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3592 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3593 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3595 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3601 Tmp1 = PromoteOp(Node->getOperand(0));
3602 assert(Tmp1.getValueType() == NVT);
3603 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3604 // NOTE: we do not have to do any extra rounding here for
3605 // NoExcessFPPrecision, because we know the input will have the appropriate
3606 // precision, and these operations don't modify precision at all.
3612 Tmp1 = PromoteOp(Node->getOperand(0));
3613 assert(Tmp1.getValueType() == NVT);
3614 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3615 if (NoExcessFPPrecision)
3616 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3617 DAG.getValueType(VT));
3621 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3622 // directly as well, which may be better.
3623 Tmp1 = PromoteOp(Node->getOperand(0));
3624 assert(Tmp1.getValueType() == NVT);
3625 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3626 if (NoExcessFPPrecision)
3627 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3628 DAG.getValueType(VT));
3638 // The input may have strange things in the top bits of the registers, but
3639 // these operations don't care. They may have weird bits going out, but
3640 // that too is okay if they are integer operations.
3641 Tmp1 = PromoteOp(Node->getOperand(0));
3642 Tmp2 = PromoteOp(Node->getOperand(1));
3643 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3644 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3649 Tmp1 = PromoteOp(Node->getOperand(0));
3650 Tmp2 = PromoteOp(Node->getOperand(1));
3651 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3652 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3654 // Floating point operations will give excess precision that we may not be
3655 // able to tolerate. If we DO allow excess precision, just leave it,
3656 // otherwise excise it.
3657 // FIXME: Why would we need to round FP ops more than integer ones?
3658 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3659 if (NoExcessFPPrecision)
3660 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3661 DAG.getValueType(VT));
3666 // These operators require that their input be sign extended.
3667 Tmp1 = PromoteOp(Node->getOperand(0));
3668 Tmp2 = PromoteOp(Node->getOperand(1));
3669 if (MVT::isInteger(NVT)) {
3670 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3671 DAG.getValueType(VT));
3672 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3673 DAG.getValueType(VT));
3675 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3677 // Perform FP_ROUND: this is probably overly pessimistic.
3678 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3679 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3680 DAG.getValueType(VT));
3684 case ISD::FCOPYSIGN:
3685 // These operators require that their input be fp extended.
3686 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3688 Tmp1 = LegalizeOp(Node->getOperand(0));
3691 Tmp1 = PromoteOp(Node->getOperand(0));
3694 assert(0 && "not implemented");
3696 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3698 Tmp2 = LegalizeOp(Node->getOperand(1));
3701 Tmp2 = PromoteOp(Node->getOperand(1));
3704 assert(0 && "not implemented");
3706 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3708 // Perform FP_ROUND: this is probably overly pessimistic.
3709 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3710 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3711 DAG.getValueType(VT));
3716 // These operators require that their input be zero extended.
3717 Tmp1 = PromoteOp(Node->getOperand(0));
3718 Tmp2 = PromoteOp(Node->getOperand(1));
3719 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3720 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3721 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3722 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3726 Tmp1 = PromoteOp(Node->getOperand(0));
3727 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3730 // The input value must be properly sign extended.
3731 Tmp1 = PromoteOp(Node->getOperand(0));
3732 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3733 DAG.getValueType(VT));
3734 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3737 // The input value must be properly zero extended.
3738 Tmp1 = PromoteOp(Node->getOperand(0));
3739 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3740 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3744 Tmp1 = Node->getOperand(0); // Get the chain.
3745 Tmp2 = Node->getOperand(1); // Get the pointer.
3746 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3747 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3748 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3750 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3751 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3752 SV->getValue(), SV->getOffset());
3753 // Increment the pointer, VAList, to the next vaarg
3754 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3755 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3756 TLI.getPointerTy()));
3757 // Store the incremented VAList to the legalized pointer
3758 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3760 // Load the actual argument out of the pointer VAList
3761 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3763 // Remember that we legalized the chain.
3764 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3768 LoadSDNode *LD = cast<LoadSDNode>(Node);
3769 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3770 ? ISD::EXTLOAD : LD->getExtensionType();
3771 Result = DAG.getExtLoad(ExtType, NVT,
3772 LD->getChain(), LD->getBasePtr(),
3773 LD->getSrcValue(), LD->getSrcValueOffset(),
3776 LD->getAlignment());
3777 // Remember that we legalized the chain.
3778 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3782 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3783 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3784 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3786 case ISD::SELECT_CC:
3787 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3788 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3789 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3790 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3793 Tmp1 = Node->getOperand(0);
3794 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3795 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3796 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3797 DAG.getConstant(MVT::getSizeInBits(NVT) -
3798 MVT::getSizeInBits(VT),
3799 TLI.getShiftAmountTy()));
3804 // Zero extend the argument
3805 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3806 // Perform the larger operation, then subtract if needed.
3807 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3808 switch(Node->getOpcode()) {
3813 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3814 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3815 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3817 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3818 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3821 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3822 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3823 DAG.getConstant(MVT::getSizeInBits(NVT) -
3824 MVT::getSizeInBits(VT), NVT));
3828 case ISD::EXTRACT_SUBVECTOR:
3829 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3831 case ISD::EXTRACT_VECTOR_ELT:
3832 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3836 assert(Result.Val && "Didn't set a result!");
3838 // Make sure the result is itself legal.
3839 Result = LegalizeOp(Result);
3841 // Remember that we promoted this!
3842 AddPromotedOperand(Op, Result);
3846 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3847 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3848 /// based on the vector type. The return type of this matches the element type
3849 /// of the vector, which may not be legal for the target.
3850 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3851 // We know that operand #0 is the Vec vector. If the index is a constant
3852 // or if the invec is a supported hardware type, we can use it. Otherwise,
3853 // lower to a store then an indexed load.
3854 SDOperand Vec = Op.getOperand(0);
3855 SDOperand Idx = Op.getOperand(1);
3857 SDNode *InVal = Vec.Val;
3858 MVT::ValueType TVT = InVal->getValueType(0);
3859 unsigned NumElems = MVT::getVectorNumElements(TVT);
3861 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3862 default: assert(0 && "This action is not supported yet!");
3863 case TargetLowering::Custom: {
3864 Vec = LegalizeOp(Vec);
3865 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3866 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3871 case TargetLowering::Legal:
3872 if (isTypeLegal(TVT)) {
3873 Vec = LegalizeOp(Vec);
3874 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3878 case TargetLowering::Expand:
3882 if (NumElems == 1) {
3883 // This must be an access of the only element. Return it.
3884 Op = ScalarizeVectorOp(Vec);
3885 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3886 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3888 SplitVectorOp(Vec, Lo, Hi);
3889 if (CIdx->getValue() < NumElems/2) {
3893 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3894 Idx.getValueType());
3897 // It's now an extract from the appropriate high or low part. Recurse.
3898 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3899 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3901 // Store the value to a temporary stack slot, then LOAD the scalar
3902 // element back out.
3903 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3904 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3906 // Add the offset to the index.
3907 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3908 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3909 DAG.getConstant(EltSize, Idx.getValueType()));
3910 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3912 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3917 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3918 /// we assume the operation can be split if it is not already legal.
3919 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3920 // We know that operand #0 is the Vec vector. For now we assume the index
3921 // is a constant and that the extracted result is a supported hardware type.
3922 SDOperand Vec = Op.getOperand(0);
3923 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3925 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3927 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3928 // This must be an access of the desired vector length. Return it.
3932 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3934 SplitVectorOp(Vec, Lo, Hi);
3935 if (CIdx->getValue() < NumElems/2) {
3939 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3942 // It's now an extract from the appropriate high or low part. Recurse.
3943 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3944 return ExpandEXTRACT_SUBVECTOR(Op);
3947 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3948 /// with condition CC on the current target. This usually involves legalizing
3949 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3950 /// there may be no choice but to create a new SetCC node to represent the
3951 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3952 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3953 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3956 SDOperand Tmp1, Tmp2, Result;
3958 switch (getTypeAction(LHS.getValueType())) {
3960 Tmp1 = LegalizeOp(LHS); // LHS
3961 Tmp2 = LegalizeOp(RHS); // RHS
3964 Tmp1 = PromoteOp(LHS); // LHS
3965 Tmp2 = PromoteOp(RHS); // RHS
3967 // If this is an FP compare, the operands have already been extended.
3968 if (MVT::isInteger(LHS.getValueType())) {
3969 MVT::ValueType VT = LHS.getValueType();
3970 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3972 // Otherwise, we have to insert explicit sign or zero extends. Note
3973 // that we could insert sign extends for ALL conditions, but zero extend
3974 // is cheaper on many machines (an AND instead of two shifts), so prefer
3976 switch (cast<CondCodeSDNode>(CC)->get()) {
3977 default: assert(0 && "Unknown integer comparison!");
3984 // ALL of these operations will work if we either sign or zero extend
3985 // the operands (including the unsigned comparisons!). Zero extend is
3986 // usually a simpler/cheaper operation, so prefer it.
3987 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3988 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3994 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3995 DAG.getValueType(VT));
3996 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3997 DAG.getValueType(VT));
4003 MVT::ValueType VT = LHS.getValueType();
4004 if (VT == MVT::f32 || VT == MVT::f64) {
4005 // Expand into one or more soft-fp libcall(s).
4006 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4007 switch (cast<CondCodeSDNode>(CC)->get()) {
4010 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4014 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4018 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4022 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4026 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4030 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4033 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4036 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4039 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4040 switch (cast<CondCodeSDNode>(CC)->get()) {
4042 // SETONE = SETOLT | SETOGT
4043 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4046 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4049 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4052 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4055 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4058 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4060 default: assert(0 && "Unsupported FP setcc!");
4065 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4066 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4067 false /*sign irrelevant*/, Dummy);
4068 Tmp2 = DAG.getConstant(0, MVT::i32);
4069 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4070 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4071 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4072 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4073 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4074 false /*sign irrelevant*/, Dummy);
4075 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4076 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4077 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4085 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4086 ExpandOp(LHS, LHSLo, LHSHi);
4087 ExpandOp(RHS, RHSLo, RHSHi);
4088 switch (cast<CondCodeSDNode>(CC)->get()) {
4092 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4093 if (RHSCST->isAllOnesValue()) {
4094 // Comparison to -1.
4095 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4100 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4101 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4102 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4103 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4106 // If this is a comparison of the sign bit, just look at the top part.
4108 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4109 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4110 CST->getValue() == 0) || // X < 0
4111 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4112 CST->isAllOnesValue())) { // X > -1
4118 // FIXME: This generated code sucks.
4119 ISD::CondCode LowCC;
4120 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4122 default: assert(0 && "Unknown integer setcc!");
4124 case ISD::SETULT: LowCC = ISD::SETULT; break;
4126 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4128 case ISD::SETULE: LowCC = ISD::SETULE; break;
4130 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4133 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4134 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4135 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4137 // NOTE: on targets without efficient SELECT of bools, we can always use
4138 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4139 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4140 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4141 false, DagCombineInfo);
4143 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4144 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4145 CCCode, false, DagCombineInfo);
4147 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
4149 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4150 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4151 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4152 (Tmp2C && Tmp2C->getValue() == 0 &&
4153 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4154 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4155 (Tmp2C && Tmp2C->getValue() == 1 &&
4156 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4157 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4158 // low part is known false, returns high part.
4159 // For LE / GE, if high part is known false, ignore the low part.
4160 // For LT / GT, if high part is known true, ignore the low part.
4164 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4165 ISD::SETEQ, false, DagCombineInfo);
4167 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4168 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4169 Result, Tmp1, Tmp2));
4180 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4181 /// The resultant code need not be legal. Note that SrcOp is the input operand
4182 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4183 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4185 // Create the stack frame object.
4186 SDOperand FIPtr = CreateStackTemporary(DestVT);
4188 // Emit a store to the stack slot.
4189 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4190 // Result is a load from the stack slot.
4191 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4194 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4195 // Create a vector sized/aligned stack slot, store the value to element #0,
4196 // then load the whole vector back out.
4197 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
4198 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4200 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4204 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4205 /// support the operation, but do support the resultant vector type.
4206 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4208 // If the only non-undef value is the low element, turn this into a
4209 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4210 unsigned NumElems = Node->getNumOperands();
4211 bool isOnlyLowElement = true;
4212 SDOperand SplatValue = Node->getOperand(0);
4213 std::map<SDOperand, std::vector<unsigned> > Values;
4214 Values[SplatValue].push_back(0);
4215 bool isConstant = true;
4216 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4217 SplatValue.getOpcode() != ISD::UNDEF)
4220 for (unsigned i = 1; i < NumElems; ++i) {
4221 SDOperand V = Node->getOperand(i);
4222 Values[V].push_back(i);
4223 if (V.getOpcode() != ISD::UNDEF)
4224 isOnlyLowElement = false;
4225 if (SplatValue != V)
4226 SplatValue = SDOperand(0,0);
4228 // If this isn't a constant element or an undef, we can't use a constant
4230 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4231 V.getOpcode() != ISD::UNDEF)
4235 if (isOnlyLowElement) {
4236 // If the low element is an undef too, then this whole things is an undef.
4237 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4238 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4239 // Otherwise, turn this into a scalar_to_vector node.
4240 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4241 Node->getOperand(0));
4244 // If all elements are constants, create a load from the constant pool.
4246 MVT::ValueType VT = Node->getValueType(0);
4248 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4249 std::vector<Constant*> CV;
4250 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4251 if (ConstantFPSDNode *V =
4252 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4253 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4254 } else if (ConstantSDNode *V =
4255 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4256 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4258 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4259 CV.push_back(UndefValue::get(OpNTy));
4262 Constant *CP = ConstantVector::get(CV);
4263 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4264 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4267 if (SplatValue.Val) { // Splat of one value?
4268 // Build the shuffle constant vector: <0, 0, 0, 0>
4269 MVT::ValueType MaskVT =
4270 MVT::getIntVectorWithNumElements(NumElems);
4271 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4272 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4273 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4274 &ZeroVec[0], ZeroVec.size());
4276 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4277 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4278 // Get the splatted value into the low element of a vector register.
4279 SDOperand LowValVec =
4280 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4282 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4283 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4284 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4289 // If there are only two unique elements, we may be able to turn this into a
4291 if (Values.size() == 2) {
4292 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4293 MVT::ValueType MaskVT =
4294 MVT::getIntVectorWithNumElements(NumElems);
4295 std::vector<SDOperand> MaskVec(NumElems);
4297 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4298 E = Values.end(); I != E; ++I) {
4299 for (std::vector<unsigned>::iterator II = I->second.begin(),
4300 EE = I->second.end(); II != EE; ++II)
4301 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4304 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4305 &MaskVec[0], MaskVec.size());
4307 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4308 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4309 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4310 SmallVector<SDOperand, 8> Ops;
4311 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4312 E = Values.end(); I != E; ++I) {
4313 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4317 Ops.push_back(ShuffleMask);
4319 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4320 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4321 &Ops[0], Ops.size());
4325 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4326 // aligned object on the stack, store each element into it, then load
4327 // the result as a vector.
4328 MVT::ValueType VT = Node->getValueType(0);
4329 // Create the stack frame object.
4330 SDOperand FIPtr = CreateStackTemporary(VT);
4332 // Emit a store of each element to the stack slot.
4333 SmallVector<SDOperand, 8> Stores;
4334 unsigned TypeByteSize =
4335 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4336 // Store (in the right endianness) the elements to memory.
4337 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4338 // Ignore undef elements.
4339 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4341 unsigned Offset = TypeByteSize*i;
4343 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4344 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4346 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4350 SDOperand StoreChain;
4351 if (!Stores.empty()) // Not all undef elements?
4352 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4353 &Stores[0], Stores.size());
4355 StoreChain = DAG.getEntryNode();
4357 // Result is a load from the stack slot.
4358 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4361 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4362 /// specified value type.
4363 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4364 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4365 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4366 const Type *Ty = MVT::getTypeForValueType(VT);
4367 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4368 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4369 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4372 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4373 SDOperand Op, SDOperand Amt,
4374 SDOperand &Lo, SDOperand &Hi) {
4375 // Expand the subcomponents.
4376 SDOperand LHSL, LHSH;
4377 ExpandOp(Op, LHSL, LHSH);
4379 SDOperand Ops[] = { LHSL, LHSH, Amt };
4380 MVT::ValueType VT = LHSL.getValueType();
4381 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4382 Hi = Lo.getValue(1);
4386 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4387 /// smaller elements. If we can't find a way that is more efficient than a
4388 /// libcall on this target, return false. Otherwise, return true with the
4389 /// low-parts expanded into Lo and Hi.
4390 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4391 SDOperand &Lo, SDOperand &Hi) {
4392 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4393 "This is not a shift!");
4395 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4396 SDOperand ShAmt = LegalizeOp(Amt);
4397 MVT::ValueType ShTy = ShAmt.getValueType();
4398 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4399 unsigned NVTBits = MVT::getSizeInBits(NVT);
4401 // Handle the case when Amt is an immediate. Other cases are currently broken
4402 // and are disabled.
4403 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4404 unsigned Cst = CN->getValue();
4405 // Expand the incoming operand to be shifted, so that we have its parts
4407 ExpandOp(Op, InL, InH);
4411 Lo = DAG.getConstant(0, NVT);
4412 Hi = DAG.getConstant(0, NVT);
4413 } else if (Cst > NVTBits) {
4414 Lo = DAG.getConstant(0, NVT);
4415 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4416 } else if (Cst == NVTBits) {
4417 Lo = DAG.getConstant(0, NVT);
4420 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4421 Hi = DAG.getNode(ISD::OR, NVT,
4422 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4423 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4428 Lo = DAG.getConstant(0, NVT);
4429 Hi = DAG.getConstant(0, NVT);
4430 } else if (Cst > NVTBits) {
4431 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4432 Hi = DAG.getConstant(0, NVT);
4433 } else if (Cst == NVTBits) {
4435 Hi = DAG.getConstant(0, NVT);
4437 Lo = DAG.getNode(ISD::OR, NVT,
4438 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4439 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4440 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4445 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4446 DAG.getConstant(NVTBits-1, ShTy));
4447 } else if (Cst > NVTBits) {
4448 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4449 DAG.getConstant(Cst-NVTBits, ShTy));
4450 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4451 DAG.getConstant(NVTBits-1, ShTy));
4452 } else if (Cst == NVTBits) {
4454 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4455 DAG.getConstant(NVTBits-1, ShTy));
4457 Lo = DAG.getNode(ISD::OR, NVT,
4458 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4459 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4460 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4466 // Okay, the shift amount isn't constant. However, if we can tell that it is
4467 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4468 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4469 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4471 // If we know that the high bit of the shift amount is one, then we can do
4472 // this as a couple of simple shifts.
4473 if (KnownOne & Mask) {
4474 // Mask out the high bit, which we know is set.
4475 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4476 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4478 // Expand the incoming operand to be shifted, so that we have its parts
4480 ExpandOp(Op, InL, InH);
4483 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4484 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4487 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4488 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4491 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4492 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4493 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4498 // If we know that the high bit of the shift amount is zero, then we can do
4499 // this as a couple of simple shifts.
4500 if (KnownZero & Mask) {
4502 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4503 DAG.getConstant(NVTBits, Amt.getValueType()),
4506 // Expand the incoming operand to be shifted, so that we have its parts
4508 ExpandOp(Op, InL, InH);
4511 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4512 Hi = DAG.getNode(ISD::OR, NVT,
4513 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4514 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4517 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4518 Lo = DAG.getNode(ISD::OR, NVT,
4519 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4520 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4523 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4524 Lo = DAG.getNode(ISD::OR, NVT,
4525 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4526 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4535 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4536 // does not fit into a register, return the lo part and set the hi part to the
4537 // by-reg argument. If it does fit into a single register, return the result
4538 // and leave the Hi part unset.
4539 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4540 bool isSigned, SDOperand &Hi) {
4541 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4542 // The input chain to this libcall is the entry node of the function.
4543 // Legalizing the call will automatically add the previous call to the
4545 SDOperand InChain = DAG.getEntryNode();
4547 TargetLowering::ArgListTy Args;
4548 TargetLowering::ArgListEntry Entry;
4549 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4550 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4551 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4552 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4553 Entry.isSExt = isSigned;
4554 Args.push_back(Entry);
4556 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4558 // Splice the libcall in wherever FindInputOutputChains tells us to.
4559 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4560 std::pair<SDOperand,SDOperand> CallInfo =
4561 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4564 // Legalize the call sequence, starting with the chain. This will advance
4565 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4566 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4567 LegalizeOp(CallInfo.second);
4569 switch (getTypeAction(CallInfo.first.getValueType())) {
4570 default: assert(0 && "Unknown thing");
4572 Result = CallInfo.first;
4575 ExpandOp(CallInfo.first, Result, Hi);
4582 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4584 SDOperand SelectionDAGLegalize::
4585 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4586 assert(getTypeAction(Source.getValueType()) == Expand &&
4587 "This is not an expansion!");
4588 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4591 assert(Source.getValueType() == MVT::i64 &&
4592 "This only works for 64-bit -> FP");
4593 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4594 // incoming integer is set. To handle this, we dynamically test to see if
4595 // it is set, and, if so, add a fudge factor.
4597 ExpandOp(Source, Lo, Hi);
4599 // If this is unsigned, and not supported, first perform the conversion to
4600 // signed, then adjust the result if the sign bit is set.
4601 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4602 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4604 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4605 DAG.getConstant(0, Hi.getValueType()),
4607 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4608 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4609 SignSet, Four, Zero);
4610 uint64_t FF = 0x5f800000ULL;
4611 if (TLI.isLittleEndian()) FF <<= 32;
4612 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4614 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4615 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4616 SDOperand FudgeInReg;
4617 if (DestTy == MVT::f32)
4618 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4619 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4620 // FIXME: Avoid the extend by construction the right constantpool?
4621 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
4622 CPIdx, NULL, 0, MVT::f32);
4624 assert(0 && "Unexpected conversion");
4626 MVT::ValueType SCVT = SignedConv.getValueType();
4627 if (SCVT != DestTy) {
4628 // Destination type needs to be expanded as well. The FADD now we are
4629 // constructing will be expanded into a libcall.
4630 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4631 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4632 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4633 SignedConv, SignedConv.getValue(1));
4635 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4637 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4640 // Check to see if the target has a custom way to lower this. If so, use it.
4641 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4642 default: assert(0 && "This action not implemented for this operation!");
4643 case TargetLowering::Legal:
4644 case TargetLowering::Expand:
4645 break; // This case is handled below.
4646 case TargetLowering::Custom: {
4647 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4650 return LegalizeOp(NV);
4651 break; // The target decided this was legal after all
4655 // Expand the source, then glue it back together for the call. We must expand
4656 // the source in case it is shared (this pass of legalize must traverse it).
4657 SDOperand SrcLo, SrcHi;
4658 ExpandOp(Source, SrcLo, SrcHi);
4659 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4662 if (DestTy == MVT::f32)
4663 LC = RTLIB::SINTTOFP_I64_F32;
4665 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4666 LC = RTLIB::SINTTOFP_I64_F64;
4669 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4670 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4671 SDOperand UnusedHiPart;
4672 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4676 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4677 /// INT_TO_FP operation of the specified operand when the target requests that
4678 /// we expand it. At this point, we know that the result and operand types are
4679 /// legal for the target.
4680 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4682 MVT::ValueType DestVT) {
4683 if (Op0.getValueType() == MVT::i32) {
4684 // simple 32-bit [signed|unsigned] integer to float/double expansion
4686 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4687 MachineFunction &MF = DAG.getMachineFunction();
4688 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4689 unsigned StackAlign =
4690 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4691 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4692 // get address of 8 byte buffer
4693 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4694 // word offset constant for Hi/Lo address computation
4695 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4696 // set up Hi and Lo (into buffer) address based on endian
4697 SDOperand Hi = StackSlot;
4698 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4699 if (TLI.isLittleEndian())
4702 // if signed map to unsigned space
4703 SDOperand Op0Mapped;
4705 // constant used to invert sign bit (signed to unsigned mapping)
4706 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4707 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4711 // store the lo of the constructed double - based on integer input
4712 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4713 Op0Mapped, Lo, NULL, 0);
4714 // initial hi portion of constructed double
4715 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4716 // store the hi of the constructed double - biased exponent
4717 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4718 // load the constructed double
4719 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4720 // FP constant to bias correct the final result
4721 SDOperand Bias = DAG.getConstantFP(isSigned ?
4722 BitsToDouble(0x4330000080000000ULL)
4723 : BitsToDouble(0x4330000000000000ULL),
4725 // subtract the bias
4726 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4729 // handle final rounding
4730 if (DestVT == MVT::f64) {
4733 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
4734 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
4735 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
4736 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
4740 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4741 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4743 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4744 DAG.getConstant(0, Op0.getValueType()),
4746 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4747 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4748 SignSet, Four, Zero);
4750 // If the sign bit of the integer is set, the large number will be treated
4751 // as a negative number. To counteract this, the dynamic code adds an
4752 // offset depending on the data type.
4754 switch (Op0.getValueType()) {
4755 default: assert(0 && "Unsupported integer type!");
4756 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4757 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4758 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4759 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4761 if (TLI.isLittleEndian()) FF <<= 32;
4762 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4764 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4765 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4766 SDOperand FudgeInReg;
4767 if (DestVT == MVT::f32)
4768 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4770 assert(DestVT == MVT::f64 && "Unexpected conversion");
4771 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4772 DAG.getEntryNode(), CPIdx,
4773 NULL, 0, MVT::f32));
4776 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4779 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4780 /// *INT_TO_FP operation of the specified operand when the target requests that
4781 /// we promote it. At this point, we know that the result and operand types are
4782 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4783 /// operation that takes a larger input.
4784 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4785 MVT::ValueType DestVT,
4787 // First step, figure out the appropriate *INT_TO_FP operation to use.
4788 MVT::ValueType NewInTy = LegalOp.getValueType();
4790 unsigned OpToUse = 0;
4792 // Scan for the appropriate larger type to use.
4794 NewInTy = (MVT::ValueType)(NewInTy+1);
4795 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4797 // If the target supports SINT_TO_FP of this type, use it.
4798 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4800 case TargetLowering::Legal:
4801 if (!TLI.isTypeLegal(NewInTy))
4802 break; // Can't use this datatype.
4804 case TargetLowering::Custom:
4805 OpToUse = ISD::SINT_TO_FP;
4809 if (isSigned) continue;
4811 // If the target supports UINT_TO_FP of this type, use it.
4812 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4814 case TargetLowering::Legal:
4815 if (!TLI.isTypeLegal(NewInTy))
4816 break; // Can't use this datatype.
4818 case TargetLowering::Custom:
4819 OpToUse = ISD::UINT_TO_FP;
4824 // Otherwise, try a larger type.
4827 // Okay, we found the operation and type to use. Zero extend our input to the
4828 // desired type then run the operation on it.
4829 return DAG.getNode(OpToUse, DestVT,
4830 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4834 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4835 /// FP_TO_*INT operation of the specified operand when the target requests that
4836 /// we promote it. At this point, we know that the result and operand types are
4837 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4838 /// operation that returns a larger result.
4839 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4840 MVT::ValueType DestVT,
4842 // First step, figure out the appropriate FP_TO*INT operation to use.
4843 MVT::ValueType NewOutTy = DestVT;
4845 unsigned OpToUse = 0;
4847 // Scan for the appropriate larger type to use.
4849 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4850 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4852 // If the target supports FP_TO_SINT returning this type, use it.
4853 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4855 case TargetLowering::Legal:
4856 if (!TLI.isTypeLegal(NewOutTy))
4857 break; // Can't use this datatype.
4859 case TargetLowering::Custom:
4860 OpToUse = ISD::FP_TO_SINT;
4865 // If the target supports FP_TO_UINT of this type, use it.
4866 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4868 case TargetLowering::Legal:
4869 if (!TLI.isTypeLegal(NewOutTy))
4870 break; // Can't use this datatype.
4872 case TargetLowering::Custom:
4873 OpToUse = ISD::FP_TO_UINT;
4878 // Otherwise, try a larger type.
4881 // Okay, we found the operation and type to use. Truncate the result of the
4882 // extended FP_TO_*INT operation to the desired size.
4883 return DAG.getNode(ISD::TRUNCATE, DestVT,
4884 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4887 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4889 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4890 MVT::ValueType VT = Op.getValueType();
4891 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4892 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4894 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4896 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4897 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4898 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4900 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4901 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4902 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4903 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4904 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4905 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4906 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4907 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4908 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4910 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4911 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4912 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4913 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4914 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4915 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4916 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4917 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4918 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4919 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4920 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4921 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4922 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4923 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4924 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4925 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4926 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4927 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4928 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4929 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4930 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4934 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4936 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4938 default: assert(0 && "Cannot expand this yet!");
4940 static const uint64_t mask[6] = {
4941 0x5555555555555555ULL, 0x3333333333333333ULL,
4942 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4943 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4945 MVT::ValueType VT = Op.getValueType();
4946 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4947 unsigned len = MVT::getSizeInBits(VT);
4948 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4949 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4950 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4951 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4952 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4953 DAG.getNode(ISD::AND, VT,
4954 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4959 // for now, we do this:
4960 // x = x | (x >> 1);
4961 // x = x | (x >> 2);
4963 // x = x | (x >>16);
4964 // x = x | (x >>32); // for 64-bit input
4965 // return popcount(~x);
4967 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4968 MVT::ValueType VT = Op.getValueType();
4969 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4970 unsigned len = MVT::getSizeInBits(VT);
4971 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4972 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4973 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4975 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4976 return DAG.getNode(ISD::CTPOP, VT, Op);
4979 // for now, we use: { return popcount(~x & (x - 1)); }
4980 // unless the target has ctlz but not ctpop, in which case we use:
4981 // { return 32 - nlz(~x & (x-1)); }
4982 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4983 MVT::ValueType VT = Op.getValueType();
4984 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4985 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4986 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4987 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4988 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4989 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4990 TLI.isOperationLegal(ISD::CTLZ, VT))
4991 return DAG.getNode(ISD::SUB, VT,
4992 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4993 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4994 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4999 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5000 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5001 /// LegalizeNodes map is filled in for any results that are not expanded, the
5002 /// ExpandedNodes map is filled in for any results that are expanded, and the
5003 /// Lo/Hi values are returned.
5004 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5005 MVT::ValueType VT = Op.getValueType();
5006 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5007 SDNode *Node = Op.Val;
5008 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5009 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5010 MVT::isVector(VT)) &&
5011 "Cannot expand to FP value or to larger int value!");
5013 // See if we already expanded it.
5014 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5015 = ExpandedNodes.find(Op);
5016 if (I != ExpandedNodes.end()) {
5017 Lo = I->second.first;
5018 Hi = I->second.second;
5022 switch (Node->getOpcode()) {
5023 case ISD::CopyFromReg:
5024 assert(0 && "CopyFromReg must be legal!");
5027 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5029 assert(0 && "Do not know how to expand this operator!");
5032 NVT = TLI.getTypeToExpandTo(VT);
5033 Lo = DAG.getNode(ISD::UNDEF, NVT);
5034 Hi = DAG.getNode(ISD::UNDEF, NVT);
5036 case ISD::Constant: {
5037 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5038 Lo = DAG.getConstant(Cst, NVT);
5039 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5042 case ISD::ConstantFP: {
5043 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5044 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5045 if (getTypeAction(Lo.getValueType()) == Expand)
5046 ExpandOp(Lo, Lo, Hi);
5049 case ISD::BUILD_PAIR:
5050 // Return the operands.
5051 Lo = Node->getOperand(0);
5052 Hi = Node->getOperand(1);
5055 case ISD::SIGN_EXTEND_INREG:
5056 ExpandOp(Node->getOperand(0), Lo, Hi);
5057 // sext_inreg the low part if needed.
5058 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5060 // The high part gets the sign extension from the lo-part. This handles
5061 // things like sextinreg V:i64 from i8.
5062 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5063 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5064 TLI.getShiftAmountTy()));
5068 ExpandOp(Node->getOperand(0), Lo, Hi);
5069 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5070 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5076 ExpandOp(Node->getOperand(0), Lo, Hi);
5077 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5078 DAG.getNode(ISD::CTPOP, NVT, Lo),
5079 DAG.getNode(ISD::CTPOP, NVT, Hi));
5080 Hi = DAG.getConstant(0, NVT);
5084 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5085 ExpandOp(Node->getOperand(0), Lo, Hi);
5086 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5087 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5088 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5090 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5091 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5093 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5094 Hi = DAG.getConstant(0, NVT);
5099 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5100 ExpandOp(Node->getOperand(0), Lo, Hi);
5101 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5102 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5103 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5105 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5106 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5108 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5109 Hi = DAG.getConstant(0, NVT);
5114 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5115 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5116 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5117 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5119 // Remember that we legalized the chain.
5120 Hi = LegalizeOp(Hi);
5121 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5122 if (!TLI.isLittleEndian())
5128 LoadSDNode *LD = cast<LoadSDNode>(Node);
5129 SDOperand Ch = LD->getChain(); // Legalize the chain.
5130 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5131 ISD::LoadExtType ExtType = LD->getExtensionType();
5132 int SVOffset = LD->getSrcValueOffset();
5133 unsigned Alignment = LD->getAlignment();
5134 bool isVolatile = LD->isVolatile();
5136 if (ExtType == ISD::NON_EXTLOAD) {
5137 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5138 isVolatile, Alignment);
5139 if (VT == MVT::f32 || VT == MVT::f64) {
5140 // f32->i32 or f64->i64 one to one expansion.
5141 // Remember that we legalized the chain.
5142 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5143 // Recursively expand the new load.
5144 if (getTypeAction(NVT) == Expand)
5145 ExpandOp(Lo, Lo, Hi);
5149 // Increment the pointer to the other half.
5150 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5151 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5152 getIntPtrConstant(IncrementSize));
5153 SVOffset += IncrementSize;
5154 if (Alignment > IncrementSize)
5155 Alignment = IncrementSize;
5156 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5157 isVolatile, Alignment);
5159 // Build a factor node to remember that this load is independent of the
5161 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5164 // Remember that we legalized the chain.
5165 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5166 if (!TLI.isLittleEndian())
5169 MVT::ValueType EVT = LD->getLoadedVT();
5171 if (VT == MVT::f64 && EVT == MVT::f32) {
5172 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5173 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5174 SVOffset, isVolatile, Alignment);
5175 // Remember that we legalized the chain.
5176 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5177 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5182 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5183 SVOffset, isVolatile, Alignment);
5185 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5186 SVOffset, EVT, isVolatile,
5189 // Remember that we legalized the chain.
5190 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5192 if (ExtType == ISD::SEXTLOAD) {
5193 // The high part is obtained by SRA'ing all but one of the bits of the
5195 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5196 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5197 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5198 } else if (ExtType == ISD::ZEXTLOAD) {
5199 // The high part is just a zero.
5200 Hi = DAG.getConstant(0, NVT);
5201 } else /* if (ExtType == ISD::EXTLOAD) */ {
5202 // The high part is undefined.
5203 Hi = DAG.getNode(ISD::UNDEF, NVT);
5210 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5211 SDOperand LL, LH, RL, RH;
5212 ExpandOp(Node->getOperand(0), LL, LH);
5213 ExpandOp(Node->getOperand(1), RL, RH);
5214 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5215 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5219 SDOperand LL, LH, RL, RH;
5220 ExpandOp(Node->getOperand(1), LL, LH);
5221 ExpandOp(Node->getOperand(2), RL, RH);
5222 if (getTypeAction(NVT) == Expand)
5223 NVT = TLI.getTypeToExpandTo(NVT);
5224 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5226 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5229 case ISD::SELECT_CC: {
5230 SDOperand TL, TH, FL, FH;
5231 ExpandOp(Node->getOperand(2), TL, TH);
5232 ExpandOp(Node->getOperand(3), FL, FH);
5233 if (getTypeAction(NVT) == Expand)
5234 NVT = TLI.getTypeToExpandTo(NVT);
5235 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5236 Node->getOperand(1), TL, FL, Node->getOperand(4));
5238 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5239 Node->getOperand(1), TH, FH, Node->getOperand(4));
5242 case ISD::ANY_EXTEND:
5243 // The low part is any extension of the input (which degenerates to a copy).
5244 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5245 // The high part is undefined.
5246 Hi = DAG.getNode(ISD::UNDEF, NVT);
5248 case ISD::SIGN_EXTEND: {
5249 // The low part is just a sign extension of the input (which degenerates to
5251 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5253 // The high part is obtained by SRA'ing all but one of the bits of the lo
5255 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5256 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5257 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5260 case ISD::ZERO_EXTEND:
5261 // The low part is just a zero extension of the input (which degenerates to
5263 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5265 // The high part is just a zero.
5266 Hi = DAG.getConstant(0, NVT);
5269 case ISD::TRUNCATE: {
5270 // The input value must be larger than this value. Expand *it*.
5272 ExpandOp(Node->getOperand(0), NewLo, Hi);
5274 // The low part is now either the right size, or it is closer. If not the
5275 // right size, make an illegal truncate so we recursively expand it.
5276 if (NewLo.getValueType() != Node->getValueType(0))
5277 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5278 ExpandOp(NewLo, Lo, Hi);
5282 case ISD::BIT_CONVERT: {
5284 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5285 // If the target wants to, allow it to lower this itself.
5286 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5287 case Expand: assert(0 && "cannot expand FP!");
5288 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5289 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5291 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5294 // f32 / f64 must be expanded to i32 / i64.
5295 if (VT == MVT::f32 || VT == MVT::f64) {
5296 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5297 if (getTypeAction(NVT) == Expand)
5298 ExpandOp(Lo, Lo, Hi);
5302 // If source operand will be expanded to the same type as VT, i.e.
5303 // i64 <- f64, i32 <- f32, expand the source operand instead.
5304 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5305 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5306 ExpandOp(Node->getOperand(0), Lo, Hi);
5310 // Turn this into a load/store pair by default.
5312 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5314 ExpandOp(Tmp, Lo, Hi);
5318 case ISD::READCYCLECOUNTER:
5319 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5320 TargetLowering::Custom &&
5321 "Must custom expand ReadCycleCounter");
5322 Lo = TLI.LowerOperation(Op, DAG);
5323 assert(Lo.Val && "Node must be custom expanded!");
5324 Hi = Lo.getValue(1);
5325 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5326 LegalizeOp(Lo.getValue(2)));
5329 // These operators cannot be expanded directly, emit them as calls to
5330 // library functions.
5331 case ISD::FP_TO_SINT: {
5332 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5334 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5335 case Expand: assert(0 && "cannot expand FP!");
5336 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5337 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5340 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5342 // Now that the custom expander is done, expand the result, which is still
5345 ExpandOp(Op, Lo, Hi);
5351 if (Node->getOperand(0).getValueType() == MVT::f32)
5352 LC = RTLIB::FPTOSINT_F32_I64;
5354 LC = RTLIB::FPTOSINT_F64_I64;
5355 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5356 false/*sign irrelevant*/, Hi);
5360 case ISD::FP_TO_UINT: {
5361 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5363 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5364 case Expand: assert(0 && "cannot expand FP!");
5365 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5366 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5369 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5371 // Now that the custom expander is done, expand the result.
5373 ExpandOp(Op, Lo, Hi);
5379 if (Node->getOperand(0).getValueType() == MVT::f32)
5380 LC = RTLIB::FPTOUINT_F32_I64;
5382 LC = RTLIB::FPTOUINT_F64_I64;
5383 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5384 false/*sign irrelevant*/, Hi);
5389 // If the target wants custom lowering, do so.
5390 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5391 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5392 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5393 Op = TLI.LowerOperation(Op, DAG);
5395 // Now that the custom expander is done, expand the result, which is
5397 ExpandOp(Op, Lo, Hi);
5402 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5403 // this X << 1 as X+X.
5404 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5405 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5406 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5407 SDOperand LoOps[2], HiOps[3];
5408 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5409 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5410 LoOps[1] = LoOps[0];
5411 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5413 HiOps[1] = HiOps[0];
5414 HiOps[2] = Lo.getValue(1);
5415 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5420 // If we can emit an efficient shift operation, do so now.
5421 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5424 // If this target supports SHL_PARTS, use it.
5425 TargetLowering::LegalizeAction Action =
5426 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5427 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5428 Action == TargetLowering::Custom) {
5429 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5433 // Otherwise, emit a libcall.
5434 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5435 false/*left shift=unsigned*/, Hi);
5440 // If the target wants custom lowering, do so.
5441 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5442 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5443 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5444 Op = TLI.LowerOperation(Op, DAG);
5446 // Now that the custom expander is done, expand the result, which is
5448 ExpandOp(Op, Lo, Hi);
5453 // If we can emit an efficient shift operation, do so now.
5454 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5457 // If this target supports SRA_PARTS, use it.
5458 TargetLowering::LegalizeAction Action =
5459 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5460 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5461 Action == TargetLowering::Custom) {
5462 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5466 // Otherwise, emit a libcall.
5467 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5468 true/*ashr is signed*/, Hi);
5473 // If the target wants custom lowering, do so.
5474 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5475 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5476 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5477 Op = TLI.LowerOperation(Op, DAG);
5479 // Now that the custom expander is done, expand the result, which is
5481 ExpandOp(Op, Lo, Hi);
5486 // If we can emit an efficient shift operation, do so now.
5487 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5490 // If this target supports SRL_PARTS, use it.
5491 TargetLowering::LegalizeAction Action =
5492 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5493 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5494 Action == TargetLowering::Custom) {
5495 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5499 // Otherwise, emit a libcall.
5500 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5501 false/*lshr is unsigned*/, Hi);
5507 // If the target wants to custom expand this, let them.
5508 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5509 TargetLowering::Custom) {
5510 Op = TLI.LowerOperation(Op, DAG);
5512 ExpandOp(Op, Lo, Hi);
5517 // Expand the subcomponents.
5518 SDOperand LHSL, LHSH, RHSL, RHSH;
5519 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5520 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5521 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5522 SDOperand LoOps[2], HiOps[3];
5527 if (Node->getOpcode() == ISD::ADD) {
5528 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5529 HiOps[2] = Lo.getValue(1);
5530 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5532 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5533 HiOps[2] = Lo.getValue(1);
5534 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5541 // Expand the subcomponents.
5542 SDOperand LHSL, LHSH, RHSL, RHSH;
5543 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5544 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5545 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5546 SDOperand LoOps[2] = { LHSL, RHSL };
5547 SDOperand HiOps[3] = { LHSH, RHSH };
5549 if (Node->getOpcode() == ISD::ADDC) {
5550 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5551 HiOps[2] = Lo.getValue(1);
5552 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5554 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5555 HiOps[2] = Lo.getValue(1);
5556 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5558 // Remember that we legalized the flag.
5559 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5564 // Expand the subcomponents.
5565 SDOperand LHSL, LHSH, RHSL, RHSH;
5566 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5567 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5568 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5569 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5570 SDOperand HiOps[3] = { LHSH, RHSH };
5572 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5573 HiOps[2] = Lo.getValue(1);
5574 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5576 // Remember that we legalized the flag.
5577 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5581 // If the target wants to custom expand this, let them.
5582 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5583 SDOperand New = TLI.LowerOperation(Op, DAG);
5585 ExpandOp(New, Lo, Hi);
5590 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5591 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5592 if (HasMULHS || HasMULHU) {
5593 SDOperand LL, LH, RL, RH;
5594 ExpandOp(Node->getOperand(0), LL, LH);
5595 ExpandOp(Node->getOperand(1), RL, RH);
5596 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5597 // FIXME: Move this to the dag combiner.
5598 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5599 // extended the sign bit of the low half through the upper half, and if so
5600 // emit a MULHS instead of the alternate sequence that is valid for any
5601 // i64 x i64 multiply.
5603 // is RH an extension of the sign bit of RL?
5604 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5605 RH.getOperand(1).getOpcode() == ISD::Constant &&
5606 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5607 // is LH an extension of the sign bit of LL?
5608 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5609 LH.getOperand(1).getOpcode() == ISD::Constant &&
5610 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5612 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5614 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5616 } else if (HasMULHU) {
5618 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5621 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5622 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5623 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5624 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5625 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5630 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5631 false/*sign irrelevant*/, Hi);
5635 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5638 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5641 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5644 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5648 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5649 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5653 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5654 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5658 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5659 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5663 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5664 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5667 case ISD::FP_EXTEND:
5668 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5671 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5674 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5675 ? RTLIB::POWI_F32 : RTLIB::POWI_F64),
5681 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5682 switch(Node->getOpcode()) {
5684 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5687 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5690 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5692 default: assert(0 && "Unreachable!");
5694 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5698 SDOperand Mask = (VT == MVT::f64)
5699 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5700 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5701 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5702 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5703 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5704 if (getTypeAction(NVT) == Expand)
5705 ExpandOp(Lo, Lo, Hi);
5709 SDOperand Mask = (VT == MVT::f64)
5710 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5711 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5712 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5713 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5714 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5715 if (getTypeAction(NVT) == Expand)
5716 ExpandOp(Lo, Lo, Hi);
5719 case ISD::FCOPYSIGN: {
5720 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5721 if (getTypeAction(NVT) == Expand)
5722 ExpandOp(Lo, Lo, Hi);
5725 case ISD::SINT_TO_FP:
5726 case ISD::UINT_TO_FP: {
5727 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5728 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5730 if (Node->getOperand(0).getValueType() == MVT::i64) {
5732 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5734 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5737 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5739 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5742 // Promote the operand if needed.
5743 if (getTypeAction(SrcVT) == Promote) {
5744 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5746 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5747 DAG.getValueType(SrcVT))
5748 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5749 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5752 const char *LibCall = TLI.getLibcallName(LC);
5754 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5756 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5757 Node->getOperand(0));
5758 if (getTypeAction(Lo.getValueType()) == Expand)
5759 ExpandOp(Lo, Lo, Hi);
5765 // Make sure the resultant values have been legalized themselves, unless this
5766 // is a type that requires multi-step expansion.
5767 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5768 Lo = LegalizeOp(Lo);
5770 // Don't legalize the high part if it is expanded to a single node.
5771 Hi = LegalizeOp(Hi);
5774 // Remember in a map if the values will be reused later.
5775 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5776 assert(isNew && "Value already expanded?!?");
5779 /// SplitVectorOp - Given an operand of vector type, break it down into
5780 /// two smaller values, still of vector type.
5781 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5783 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5784 SDNode *Node = Op.Val;
5785 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5786 assert(NumElements > 1 && "Cannot split a single element vector!");
5787 unsigned NewNumElts = NumElements/2;
5788 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5789 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5791 // See if we already split it.
5792 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5793 = SplitNodes.find(Op);
5794 if (I != SplitNodes.end()) {
5795 Lo = I->second.first;
5796 Hi = I->second.second;
5800 switch (Node->getOpcode()) {
5805 assert(0 && "Unhandled operation in SplitVectorOp!");
5806 case ISD::BUILD_PAIR:
5807 Lo = Node->getOperand(0);
5808 Hi = Node->getOperand(1);
5810 case ISD::BUILD_VECTOR: {
5811 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5812 Node->op_begin()+NewNumElts);
5813 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5815 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5817 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5820 case ISD::CONCAT_VECTORS: {
5821 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5822 if (NewNumSubvectors == 1) {
5823 Lo = Node->getOperand(0);
5824 Hi = Node->getOperand(1);
5826 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5827 Node->op_begin()+NewNumSubvectors);
5828 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5830 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5832 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5848 SDOperand LL, LH, RL, RH;
5849 SplitVectorOp(Node->getOperand(0), LL, LH);
5850 SplitVectorOp(Node->getOperand(1), RL, RH);
5852 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5853 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5857 LoadSDNode *LD = cast<LoadSDNode>(Node);
5858 SDOperand Ch = LD->getChain();
5859 SDOperand Ptr = LD->getBasePtr();
5860 const Value *SV = LD->getSrcValue();
5861 int SVOffset = LD->getSrcValueOffset();
5862 unsigned Alignment = LD->getAlignment();
5863 bool isVolatile = LD->isVolatile();
5865 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5866 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5867 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5868 getIntPtrConstant(IncrementSize));
5869 SVOffset += IncrementSize;
5870 if (Alignment > IncrementSize)
5871 Alignment = IncrementSize;
5872 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5874 // Build a factor node to remember that this load is independent of the
5876 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5879 // Remember that we legalized the chain.
5880 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5883 case ISD::BIT_CONVERT: {
5884 // We know the result is a vector. The input may be either a vector or a
5886 SDOperand InOp = Node->getOperand(0);
5887 if (!MVT::isVector(InOp.getValueType()) ||
5888 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5889 // The input is a scalar or single-element vector.
5890 // Lower to a store/load so that it can be split.
5891 // FIXME: this could be improved probably.
5892 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5894 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5895 InOp, Ptr, NULL, 0);
5896 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5898 // Split the vector and convert each of the pieces now.
5899 SplitVectorOp(InOp, Lo, Hi);
5900 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5901 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5906 // Remember in a map if the values will be reused later.
5908 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5909 assert(isNew && "Value already split?!?");
5913 /// ScalarizeVectorOp - Given an operand of single-element vector type
5914 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5915 /// scalar (e.g. f32) value.
5916 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5917 assert(MVT::isVector(Op.getValueType()) &&
5918 "Bad ScalarizeVectorOp invocation!");
5919 SDNode *Node = Op.Val;
5920 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5921 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5923 // See if we already scalarized it.
5924 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5925 if (I != ScalarizedNodes.end()) return I->second;
5928 switch (Node->getOpcode()) {
5931 Node->dump(&DAG); cerr << "\n";
5933 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5949 Result = DAG.getNode(Node->getOpcode(),
5951 ScalarizeVectorOp(Node->getOperand(0)),
5952 ScalarizeVectorOp(Node->getOperand(1)));
5959 Result = DAG.getNode(Node->getOpcode(),
5961 ScalarizeVectorOp(Node->getOperand(0)));
5964 LoadSDNode *LD = cast<LoadSDNode>(Node);
5965 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5966 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5968 const Value *SV = LD->getSrcValue();
5969 int SVOffset = LD->getSrcValueOffset();
5970 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5971 LD->isVolatile(), LD->getAlignment());
5973 // Remember that we legalized the chain.
5974 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5977 case ISD::BUILD_VECTOR:
5978 Result = Node->getOperand(0);
5980 case ISD::INSERT_VECTOR_ELT:
5981 // Returning the inserted scalar element.
5982 Result = Node->getOperand(1);
5984 case ISD::CONCAT_VECTORS:
5985 assert(Node->getOperand(0).getValueType() == NewVT &&
5986 "Concat of non-legal vectors not yet supported!");
5987 Result = Node->getOperand(0);
5989 case ISD::VECTOR_SHUFFLE: {
5990 // Figure out if the scalar is the LHS or RHS and return it.
5991 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5992 if (cast<ConstantSDNode>(EltNum)->getValue())
5993 Result = ScalarizeVectorOp(Node->getOperand(1));
5995 Result = ScalarizeVectorOp(Node->getOperand(0));
5998 case ISD::EXTRACT_SUBVECTOR:
5999 Result = Node->getOperand(0);
6000 assert(Result.getValueType() == NewVT);
6002 case ISD::BIT_CONVERT:
6003 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6006 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6007 ScalarizeVectorOp(Op.getOperand(1)),
6008 ScalarizeVectorOp(Op.getOperand(2)));
6012 if (TLI.isTypeLegal(NewVT))
6013 Result = LegalizeOp(Result);
6014 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6015 assert(isNew && "Value already scalarized?");
6020 // SelectionDAG::Legalize - This is the entry point for the file.
6022 void SelectionDAG::Legalize() {
6023 if (ViewLegalizeDAGs) viewGraph();
6025 /// run - This is the main entry point to this class.
6027 SelectionDAGLegalize(*this).LegalizeDAG();