1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/SmallPtrSet.h"
36 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
37 cl::desc("Pop up a window to show dags before legalize"));
39 static const bool ViewLegalizeDAGs = 0;
44 struct DenseMapKeyInfo<SDOperand> {
45 static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); }
46 static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1, 0);}
47 static unsigned getHashValue(const SDOperand &Val) {
48 return DenseMapKeyInfo<void*>::getHashValue(Val.Val) + Val.ResNo;
50 static bool isPod() { return true; }
54 //===----------------------------------------------------------------------===//
55 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
56 /// hacks on it until the target machine can handle it. This involves
57 /// eliminating value sizes the machine cannot handle (promoting small sizes to
58 /// large sizes or splitting up large values into small values) as well as
59 /// eliminating operations the machine cannot handle.
61 /// This code also does a small amount of optimization and recognition of idioms
62 /// as part of its processing. For example, if a target does not support a
63 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
64 /// will attempt merge setcc and brc instructions into brcc's.
67 class VISIBILITY_HIDDEN SelectionDAGLegalize {
71 // Libcall insertion helpers.
73 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
74 /// legalized. We use this to ensure that calls are properly serialized
75 /// against each other, including inserted libcalls.
76 SDOperand LastCALLSEQ_END;
78 /// IsLegalizingCall - This member is used *only* for purposes of providing
79 /// helpful assertions that a libcall isn't created while another call is
80 /// being legalized (which could lead to non-serialized call sequences).
81 bool IsLegalizingCall;
84 Legal, // The target natively supports this operation.
85 Promote, // This operation should be executed in a larger type.
86 Expand // Try to expand this to other ops, otherwise use a libcall.
89 /// ValueTypeActions - This is a bitvector that contains two bits for each
90 /// value type, where the two bits correspond to the LegalizeAction enum.
91 /// This can be queried with "getTypeAction(VT)".
92 TargetLowering::ValueTypeActionImpl ValueTypeActions;
94 /// LegalizedNodes - For nodes that are of legal width, and that have more
95 /// than one use, this map indicates what regularized operand to use. This
96 /// allows us to avoid legalizing the same thing more than once.
97 DenseMap<SDOperand, SDOperand> LegalizedNodes;
99 /// PromotedNodes - For nodes that are below legal width, and that have more
100 /// than one use, this map indicates what promoted value to use. This allows
101 /// us to avoid promoting the same thing more than once.
102 DenseMap<SDOperand, SDOperand> PromotedNodes;
104 /// ExpandedNodes - For nodes that need to be expanded this map indicates
105 /// which which operands are the expanded version of the input. This allows
106 /// us to avoid expanding the same node more than once.
107 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
109 /// SplitNodes - For vector nodes that need to be split, this map indicates
110 /// which which operands are the split version of the input. This allows us
111 /// to avoid splitting the same node more than once.
112 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
114 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
115 /// concrete vector types, this contains the mapping of ones we have already
116 /// processed to the result.
117 std::map<SDOperand, SDOperand> PackedNodes;
119 void AddLegalizedOperand(SDOperand From, SDOperand To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDOperand From, SDOperand To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
127 assert(isNew && "Got into the map somehow?");
128 // If someone requests legalization of the new node, return itself.
129 LegalizedNodes.insert(std::make_pair(To, To));
134 SelectionDAGLegalize(SelectionDAG &DAG);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT::ValueType VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT::ValueType VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDOperand Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDOperand LegalizeOp(SDOperand O);
161 /// PromoteOp - Given an operation that produces a value in an invalid type,
162 /// promote it to compute the value into a larger type. The produced value
163 /// will have the correct bits for the low portion of the register, but no
164 /// guarantee is made about the top bits: it may be zero, sign-extended, or
166 SDOperand PromoteOp(SDOperand O);
168 /// ExpandOp - Expand the specified SDOperand into its two component pieces
169 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
170 /// the LegalizeNodes map is filled in for any results that are not expanded,
171 /// the ExpandedNodes map is filled in for any results that are expanded, and
172 /// the Lo/Hi values are returned. This applies to integer types and Vector
174 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
177 /// two smaller values of MVT::Vector type.
178 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
180 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
181 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
182 /// this is called, we know that PackedVT is the right type for the result and
183 /// we know that this type is legal for the target.
184 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
186 /// isShuffleLegal - Return true if a vector shuffle is legal with the
187 /// specified mask and type. Targets can specify exactly which masks they
188 /// support and the code generator is tasked with not creating illegal masks.
190 /// Note that this will also return true for shuffles that are promoted to a
193 /// If this is a legal shuffle, this method returns the (possibly promoted)
194 /// build_vector Mask. If it's not a legal shuffle, it returns null.
195 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
197 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
198 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
200 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
202 SDOperand CreateStackTemporary(MVT::ValueType VT);
204 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
206 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
209 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
210 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
212 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
214 MVT::ValueType DestVT);
215 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
217 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
220 SDOperand ExpandBSWAP(SDOperand Op);
221 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
222 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
223 SDOperand &Lo, SDOperand &Hi);
224 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
225 SDOperand &Lo, SDOperand &Hi);
227 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
228 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
230 SDOperand getIntPtrConstant(uint64_t Val) {
231 return DAG.getConstant(Val, TLI.getPointerTy());
236 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
237 /// specified mask and type. Targets can specify exactly which masks they
238 /// support and the code generator is tasked with not creating illegal masks.
240 /// Note that this will also return true for shuffles that are promoted to a
242 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
243 SDOperand Mask) const {
244 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
246 case TargetLowering::Legal:
247 case TargetLowering::Custom:
249 case TargetLowering::Promote: {
250 // If this is promoted to a different type, convert the shuffle mask and
251 // ask if it is legal in the promoted type!
252 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
254 // If we changed # elements, change the shuffle mask.
255 unsigned NumEltsGrowth =
256 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
257 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
258 if (NumEltsGrowth > 1) {
259 // Renumber the elements.
260 SmallVector<SDOperand, 8> Ops;
261 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
262 SDOperand InOp = Mask.getOperand(i);
263 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
264 if (InOp.getOpcode() == ISD::UNDEF)
265 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
267 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
268 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
272 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
278 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
281 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
282 /// specified vector opcode.
283 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
285 default: assert(0 && "Don't know how to scalarize this opcode!");
286 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
287 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
288 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
289 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
290 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
291 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
292 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
293 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
297 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
298 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
299 ValueTypeActions(TLI.getValueTypeActions()) {
300 assert(MVT::LAST_VALUETYPE <= 32 &&
301 "Too many value types for ValueTypeActions to hold!");
304 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
305 /// not been visited yet and if all of its operands have already been visited.
306 static void ComputeTopDownOrdering(SDNode *N, SmallVector<SDNode*, 64> &Order,
307 DenseMap<SDNode*, unsigned> &Visited) {
308 if (++Visited[N] != N->getNumOperands())
309 return; // Haven't visited all operands yet
313 if (N->hasOneUse()) { // Tail recurse in common case.
314 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
318 // Now that we have N in, add anything that uses it if all of their operands
320 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
321 ComputeTopDownOrdering(*UI, Order, Visited);
325 void SelectionDAGLegalize::LegalizeDAG() {
326 LastCALLSEQ_END = DAG.getEntryNode();
327 IsLegalizingCall = false;
329 // The legalize process is inherently a bottom-up recursive process (users
330 // legalize their uses before themselves). Given infinite stack space, we
331 // could just start legalizing on the root and traverse the whole graph. In
332 // practice however, this causes us to run out of stack space on large basic
333 // blocks. To avoid this problem, compute an ordering of the nodes where each
334 // node is only legalized after all of its operands are legalized.
335 DenseMap<SDNode*, unsigned> Visited;
336 SmallVector<SDNode*, 64> Order;
338 // Compute ordering from all of the leaves in the graphs, those (like the
339 // entry node) that have no operands.
340 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
341 E = DAG.allnodes_end(); I != E; ++I) {
342 if (I->getNumOperands() == 0) {
344 ComputeTopDownOrdering(I, Order, Visited);
348 assert(Order.size() == Visited.size() &&
350 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
351 "Error: DAG is cyclic!");
354 for (unsigned i = 0, e = Order.size(); i != e; ++i)
355 HandleOp(SDOperand(Order[i], 0));
357 // Finally, it's possible the root changed. Get the new root.
358 SDOperand OldRoot = DAG.getRoot();
359 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
360 DAG.setRoot(LegalizedNodes[OldRoot]);
362 ExpandedNodes.clear();
363 LegalizedNodes.clear();
364 PromotedNodes.clear();
368 // Remove dead nodes now.
369 DAG.RemoveDeadNodes();
373 /// FindCallEndFromCallStart - Given a chained node that is part of a call
374 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
375 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
376 if (Node->getOpcode() == ISD::CALLSEQ_END)
378 if (Node->use_empty())
379 return 0; // No CallSeqEnd
381 // The chain is usually at the end.
382 SDOperand TheChain(Node, Node->getNumValues()-1);
383 if (TheChain.getValueType() != MVT::Other) {
384 // Sometimes it's at the beginning.
385 TheChain = SDOperand(Node, 0);
386 if (TheChain.getValueType() != MVT::Other) {
387 // Otherwise, hunt for it.
388 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
389 if (Node->getValueType(i) == MVT::Other) {
390 TheChain = SDOperand(Node, i);
394 // Otherwise, we walked into a node without a chain.
395 if (TheChain.getValueType() != MVT::Other)
400 for (SDNode::use_iterator UI = Node->use_begin(),
401 E = Node->use_end(); UI != E; ++UI) {
403 // Make sure to only follow users of our token chain.
405 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
406 if (User->getOperand(i) == TheChain)
407 if (SDNode *Result = FindCallEndFromCallStart(User))
413 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
414 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
415 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
416 assert(Node && "Didn't find callseq_start for a call??");
417 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
419 assert(Node->getOperand(0).getValueType() == MVT::Other &&
420 "Node doesn't have a token chain argument!");
421 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
424 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
425 /// see if any uses can reach Dest. If no dest operands can get to dest,
426 /// legalize them, legalize ourself, and return false, otherwise, return true.
428 /// Keep track of the nodes we fine that actually do lead to Dest in
429 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
431 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
432 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
433 if (N == Dest) return true; // N certainly leads to Dest :)
435 // If we've already processed this node and it does lead to Dest, there is no
436 // need to reprocess it.
437 if (NodesLeadingTo.count(N)) return true;
439 // If the first result of this node has been already legalized, then it cannot
441 switch (getTypeAction(N->getValueType(0))) {
443 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
446 if (PromotedNodes.count(SDOperand(N, 0))) return false;
449 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
453 // Okay, this node has not already been legalized. Check and legalize all
454 // operands. If none lead to Dest, then we can legalize this node.
455 bool OperandsLeadToDest = false;
456 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
457 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
458 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
460 if (OperandsLeadToDest) {
461 NodesLeadingTo.insert(N);
465 // Okay, this node looks safe, legalize it and return false.
466 HandleOp(SDOperand(N, 0));
470 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
471 /// appropriate for its type.
472 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
473 switch (getTypeAction(Op.getValueType())) {
474 default: assert(0 && "Bad type action!");
475 case Legal: LegalizeOp(Op); break;
476 case Promote: PromoteOp(Op); break;
478 if (Op.getValueType() != MVT::Vector) {
483 unsigned NumOps = N->getNumOperands();
484 unsigned NumElements =
485 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
486 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
487 MVT::ValueType PackedVT = MVT::getVectorType(EVT, NumElements);
488 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
489 // In the common case, this is a legal vector type, convert it to the
490 // packed operation and type now.
491 PackVectorOp(Op, PackedVT);
492 } else if (NumElements == 1) {
493 // Otherwise, if this is a single element vector, convert it to a
495 PackVectorOp(Op, EVT);
497 // Otherwise, this is a multiple element vector that isn't supported.
498 // Split it in half and legalize both parts.
500 SplitVectorOp(Op, X, Y);
507 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
508 /// a load from the constant pool.
509 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
510 SelectionDAG &DAG, TargetLowering &TLI) {
513 // If a FP immediate is precise when represented as a float and if the
514 // target can do an extending load from float to double, we put it into
515 // the constant pool as a float, even if it's is statically typed as a
517 MVT::ValueType VT = CFP->getValueType(0);
518 bool isDouble = VT == MVT::f64;
519 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
520 Type::FloatTy, CFP->getValue());
522 double Val = LLVMC->getValue();
524 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
525 : DAG.getConstant(FloatToBits(Val), MVT::i32);
528 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
529 // Only do this if the target has a native EXTLOAD instruction from f32.
530 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
531 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
536 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
538 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
539 CPIdx, NULL, 0, MVT::f32);
541 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
546 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
549 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
550 SelectionDAG &DAG, TargetLowering &TLI) {
551 MVT::ValueType VT = Node->getValueType(0);
552 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
553 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
555 // First get the sign bit of second operand.
556 SDOperand Mask1 = (SrcVT == MVT::f64)
557 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
558 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
559 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
560 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
561 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
562 // Shift right or sign-extend it if the two operands have different types.
563 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
565 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
566 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
567 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
568 } else if (SizeDiff < 0)
569 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
571 // Clear the sign bit of first operand.
572 SDOperand Mask2 = (VT == MVT::f64)
573 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
574 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
575 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
576 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
577 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
579 // Or the value with the sign bit.
580 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
585 /// LegalizeOp - We know that the specified value has a legal type.
586 /// Recursively ensure that the operands have legal types, then return the
588 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
589 assert(isTypeLegal(Op.getValueType()) &&
590 "Caller should expand or promote operands that are not legal!");
591 SDNode *Node = Op.Val;
593 // If this operation defines any values that cannot be represented in a
594 // register on this target, make sure to expand or promote them.
595 if (Node->getNumValues() > 1) {
596 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
597 if (getTypeAction(Node->getValueType(i)) != Legal) {
598 HandleOp(Op.getValue(i));
599 assert(LegalizedNodes.count(Op) &&
600 "Handling didn't add legal operands!");
601 return LegalizedNodes[Op];
605 // Note that LegalizeOp may be reentered even from single-use nodes, which
606 // means that we always must cache transformed nodes.
607 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
608 if (I != LegalizedNodes.end()) return I->second;
610 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
611 SDOperand Result = Op;
612 bool isCustom = false;
614 switch (Node->getOpcode()) {
615 case ISD::FrameIndex:
616 case ISD::EntryToken:
618 case ISD::BasicBlock:
619 case ISD::TargetFrameIndex:
620 case ISD::TargetJumpTable:
621 case ISD::TargetConstant:
622 case ISD::TargetConstantFP:
623 case ISD::TargetConstantPool:
624 case ISD::TargetGlobalAddress:
625 case ISD::TargetGlobalTLSAddress:
626 case ISD::TargetExternalSymbol:
631 // Primitives must all be legal.
632 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
633 "This must be legal!");
636 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
637 // If this is a target node, legalize it by legalizing the operands then
638 // passing it through.
639 SmallVector<SDOperand, 8> Ops;
640 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
641 Ops.push_back(LegalizeOp(Node->getOperand(i)));
643 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
645 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
646 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
647 return Result.getValue(Op.ResNo);
649 // Otherwise this is an unhandled builtin node. splat.
651 cerr << "NODE: "; Node->dump(); cerr << "\n";
653 assert(0 && "Do not know how to legalize this operator!");
655 case ISD::GLOBAL_OFFSET_TABLE:
656 case ISD::GlobalAddress:
657 case ISD::GlobalTLSAddress:
658 case ISD::ExternalSymbol:
659 case ISD::ConstantPool:
660 case ISD::JumpTable: // Nothing to do.
661 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
662 default: assert(0 && "This action is not supported yet!");
663 case TargetLowering::Custom:
664 Tmp1 = TLI.LowerOperation(Op, DAG);
665 if (Tmp1.Val) Result = Tmp1;
666 // FALLTHROUGH if the target doesn't want to lower this op after all.
667 case TargetLowering::Legal:
672 case ISD::RETURNADDR:
673 // The only option for these nodes is to custom lower them. If the target
674 // does not custom lower them, then return zero.
675 Tmp1 = TLI.LowerOperation(Op, DAG);
679 Result = DAG.getConstant(0, TLI.getPointerTy());
681 case ISD::EXCEPTIONADDR: {
682 Tmp1 = LegalizeOp(Node->getOperand(0));
683 MVT::ValueType VT = Node->getValueType(0);
684 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
685 default: assert(0 && "This action is not supported yet!");
686 case TargetLowering::Expand: {
687 unsigned Reg = TLI.getExceptionAddressRegister();
688 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
691 case TargetLowering::Custom:
692 Result = TLI.LowerOperation(Op, DAG);
693 if (Result.Val) break;
695 case TargetLowering::Legal: {
696 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
697 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
698 Ops, 2).getValue(Op.ResNo);
704 case ISD::EHSELECTION: {
705 Tmp1 = LegalizeOp(Node->getOperand(0));
706 Tmp2 = LegalizeOp(Node->getOperand(1));
707 MVT::ValueType VT = Node->getValueType(0);
708 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
709 default: assert(0 && "This action is not supported yet!");
710 case TargetLowering::Expand: {
711 unsigned Reg = TLI.getExceptionSelectorRegister();
712 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
715 case TargetLowering::Custom:
716 Result = TLI.LowerOperation(Op, DAG);
717 if (Result.Val) break;
719 case TargetLowering::Legal: {
720 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
721 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
722 Ops, 2).getValue(Op.ResNo);
728 case ISD::AssertSext:
729 case ISD::AssertZext:
730 Tmp1 = LegalizeOp(Node->getOperand(0));
731 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
733 case ISD::MERGE_VALUES:
734 // Legalize eliminates MERGE_VALUES nodes.
735 Result = Node->getOperand(Op.ResNo);
737 case ISD::CopyFromReg:
738 Tmp1 = LegalizeOp(Node->getOperand(0));
739 Result = Op.getValue(0);
740 if (Node->getNumValues() == 2) {
741 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
743 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
744 if (Node->getNumOperands() == 3) {
745 Tmp2 = LegalizeOp(Node->getOperand(2));
746 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
748 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
750 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
752 // Since CopyFromReg produces two values, make sure to remember that we
753 // legalized both of them.
754 AddLegalizedOperand(Op.getValue(0), Result);
755 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
756 return Result.getValue(Op.ResNo);
758 MVT::ValueType VT = Op.getValueType();
759 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
760 default: assert(0 && "This action is not supported yet!");
761 case TargetLowering::Expand:
762 if (MVT::isInteger(VT))
763 Result = DAG.getConstant(0, VT);
764 else if (MVT::isFloatingPoint(VT))
765 Result = DAG.getConstantFP(0, VT);
767 assert(0 && "Unknown value type!");
769 case TargetLowering::Legal:
775 case ISD::INTRINSIC_W_CHAIN:
776 case ISD::INTRINSIC_WO_CHAIN:
777 case ISD::INTRINSIC_VOID: {
778 SmallVector<SDOperand, 8> Ops;
779 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
780 Ops.push_back(LegalizeOp(Node->getOperand(i)));
781 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
783 // Allow the target to custom lower its intrinsics if it wants to.
784 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
785 TargetLowering::Custom) {
786 Tmp3 = TLI.LowerOperation(Result, DAG);
787 if (Tmp3.Val) Result = Tmp3;
790 if (Result.Val->getNumValues() == 1) break;
792 // Must have return value and chain result.
793 assert(Result.Val->getNumValues() == 2 &&
794 "Cannot return more than two values!");
796 // Since loads produce two values, make sure to remember that we
797 // legalized both of them.
798 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
799 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
800 return Result.getValue(Op.ResNo);
804 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
805 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
807 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
808 case TargetLowering::Promote:
809 default: assert(0 && "This action is not supported yet!");
810 case TargetLowering::Expand: {
811 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
812 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
813 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
815 if (MMI && (useDEBUG_LOC || useLABEL)) {
816 const std::string &FName =
817 cast<StringSDNode>(Node->getOperand(3))->getValue();
818 const std::string &DirName =
819 cast<StringSDNode>(Node->getOperand(4))->getValue();
820 unsigned SrcFile = MMI->RecordSource(DirName, FName);
822 SmallVector<SDOperand, 8> Ops;
823 Ops.push_back(Tmp1); // chain
824 SDOperand LineOp = Node->getOperand(1);
825 SDOperand ColOp = Node->getOperand(2);
828 Ops.push_back(LineOp); // line #
829 Ops.push_back(ColOp); // col #
830 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
831 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
833 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
834 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
835 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
836 Ops.push_back(DAG.getConstant(ID, MVT::i32));
837 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
840 Result = Tmp1; // chain
844 case TargetLowering::Legal:
845 if (Tmp1 != Node->getOperand(0) ||
846 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
847 SmallVector<SDOperand, 8> Ops;
849 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
850 Ops.push_back(Node->getOperand(1)); // line # must be legal.
851 Ops.push_back(Node->getOperand(2)); // col # must be legal.
853 // Otherwise promote them.
854 Ops.push_back(PromoteOp(Node->getOperand(1)));
855 Ops.push_back(PromoteOp(Node->getOperand(2)));
857 Ops.push_back(Node->getOperand(3)); // filename must be legal.
858 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
859 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
866 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
867 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
868 default: assert(0 && "This action is not supported yet!");
869 case TargetLowering::Legal:
870 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
871 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
872 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
873 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
880 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
881 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
882 default: assert(0 && "This action is not supported yet!");
883 case TargetLowering::Legal:
884 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
885 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
886 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
888 case TargetLowering::Expand:
889 Result = LegalizeOp(Node->getOperand(0));
895 // We know we don't need to expand constants here, constants only have one
896 // value and we check that it is fine above.
898 // FIXME: Maybe we should handle things like targets that don't support full
899 // 32-bit immediates?
901 case ISD::ConstantFP: {
902 // Spill FP immediates to the constant pool if the target cannot directly
903 // codegen them. Targets often have some immediate values that can be
904 // efficiently generated into an FP register without a load. We explicitly
905 // leave these constants as ConstantFP nodes for the target to deal with.
906 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
908 // Check to see if this FP immediate is already legal.
909 bool isLegal = false;
910 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
911 E = TLI.legal_fpimm_end(); I != E; ++I)
912 if (CFP->isExactlyValue(*I)) {
917 // If this is a legal constant, turn it into a TargetConstantFP node.
919 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
923 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
924 default: assert(0 && "This action is not supported yet!");
925 case TargetLowering::Custom:
926 Tmp3 = TLI.LowerOperation(Result, DAG);
932 case TargetLowering::Expand:
933 Result = ExpandConstantFP(CFP, true, DAG, TLI);
937 case ISD::TokenFactor:
938 if (Node->getNumOperands() == 2) {
939 Tmp1 = LegalizeOp(Node->getOperand(0));
940 Tmp2 = LegalizeOp(Node->getOperand(1));
941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
942 } else if (Node->getNumOperands() == 3) {
943 Tmp1 = LegalizeOp(Node->getOperand(0));
944 Tmp2 = LegalizeOp(Node->getOperand(1));
945 Tmp3 = LegalizeOp(Node->getOperand(2));
946 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
948 SmallVector<SDOperand, 8> Ops;
949 // Legalize the operands.
950 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
951 Ops.push_back(LegalizeOp(Node->getOperand(i)));
952 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
956 case ISD::FORMAL_ARGUMENTS:
958 // The only option for this is to custom lower it.
959 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
960 assert(Tmp3.Val && "Target didn't custom lower this node!");
961 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
962 "Lowering call/formal_arguments produced unexpected # results!");
964 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
965 // remember that we legalized all of them, so it doesn't get relegalized.
966 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
967 Tmp1 = LegalizeOp(Tmp3.getValue(i));
970 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
974 case ISD::BUILD_VECTOR:
975 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
976 default: assert(0 && "This action is not supported yet!");
977 case TargetLowering::Custom:
978 Tmp3 = TLI.LowerOperation(Result, DAG);
984 case TargetLowering::Expand:
985 Result = ExpandBUILD_VECTOR(Result.Val);
989 case ISD::INSERT_VECTOR_ELT:
990 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
991 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
992 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
993 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
995 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
996 Node->getValueType(0))) {
997 default: assert(0 && "This action is not supported yet!");
998 case TargetLowering::Legal:
1000 case TargetLowering::Custom:
1001 Tmp3 = TLI.LowerOperation(Result, DAG);
1007 case TargetLowering::Expand: {
1008 // If the insert index is a constant, codegen this as a scalar_to_vector,
1009 // then a shuffle that inserts it into the right position in the vector.
1010 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1011 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1012 Tmp1.getValueType(), Tmp2);
1014 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1015 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1016 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
1018 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1019 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1021 SmallVector<SDOperand, 8> ShufOps;
1022 for (unsigned i = 0; i != NumElts; ++i) {
1023 if (i != InsertPos->getValue())
1024 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1026 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1028 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1029 &ShufOps[0], ShufOps.size());
1031 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1032 Tmp1, ScVec, ShufMask);
1033 Result = LegalizeOp(Result);
1037 // If the target doesn't support this, we have to spill the input vector
1038 // to a temporary stack slot, update the element, then reload it. This is
1039 // badness. We could also load the value into a vector register (either
1040 // with a "move to register" or "extload into register" instruction, then
1041 // permute it into place, if the idx is a constant and if the idx is
1042 // supported by the target.
1043 MVT::ValueType VT = Tmp1.getValueType();
1044 MVT::ValueType EltVT = Tmp2.getValueType();
1045 MVT::ValueType IdxVT = Tmp3.getValueType();
1046 MVT::ValueType PtrVT = TLI.getPointerTy();
1047 SDOperand StackPtr = CreateStackTemporary(VT);
1048 // Store the vector.
1049 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1051 // Truncate or zero extend offset to target pointer type.
1052 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1053 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1054 // Add the offset to the index.
1055 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1056 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1057 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1058 // Store the scalar value.
1059 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1060 // Load the updated vector.
1061 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1066 case ISD::SCALAR_TO_VECTOR:
1067 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1068 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1072 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1073 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1074 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1075 Node->getValueType(0))) {
1076 default: assert(0 && "This action is not supported yet!");
1077 case TargetLowering::Legal:
1079 case TargetLowering::Custom:
1080 Tmp3 = TLI.LowerOperation(Result, DAG);
1086 case TargetLowering::Expand:
1087 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1091 case ISD::VECTOR_SHUFFLE:
1092 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1093 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1094 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1096 // Allow targets to custom lower the SHUFFLEs they support.
1097 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1098 default: assert(0 && "Unknown operation action!");
1099 case TargetLowering::Legal:
1100 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1101 "vector shuffle should not be created if not legal!");
1103 case TargetLowering::Custom:
1104 Tmp3 = TLI.LowerOperation(Result, DAG);
1110 case TargetLowering::Expand: {
1111 MVT::ValueType VT = Node->getValueType(0);
1112 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
1113 MVT::ValueType PtrVT = TLI.getPointerTy();
1114 SDOperand Mask = Node->getOperand(2);
1115 unsigned NumElems = Mask.getNumOperands();
1116 SmallVector<SDOperand,8> Ops;
1117 for (unsigned i = 0; i != NumElems; ++i) {
1118 SDOperand Arg = Mask.getOperand(i);
1119 if (Arg.getOpcode() == ISD::UNDEF) {
1120 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1122 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1123 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1125 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1126 DAG.getConstant(Idx, PtrVT)));
1128 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1129 DAG.getConstant(Idx - NumElems, PtrVT)));
1132 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1135 case TargetLowering::Promote: {
1136 // Change base type to a different vector type.
1137 MVT::ValueType OVT = Node->getValueType(0);
1138 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1140 // Cast the two input vectors.
1141 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1142 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1144 // Convert the shuffle mask to the right # elements.
1145 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1146 assert(Tmp3.Val && "Shuffle not legal?");
1147 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1148 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1154 case ISD::EXTRACT_VECTOR_ELT:
1155 Tmp1 = LegalizeOp(Node->getOperand(0));
1156 Tmp2 = LegalizeOp(Node->getOperand(1));
1157 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1159 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1160 Tmp1.getValueType())) {
1161 default: assert(0 && "This action is not supported yet!");
1162 case TargetLowering::Legal:
1164 case TargetLowering::Custom:
1165 Tmp3 = TLI.LowerOperation(Result, DAG);
1171 case TargetLowering::Expand:
1172 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1177 case ISD::VEXTRACT_VECTOR_ELT:
1178 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1181 case ISD::CALLSEQ_START: {
1182 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1184 // Recursively Legalize all of the inputs of the call end that do not lead
1185 // to this call start. This ensures that any libcalls that need be inserted
1186 // are inserted *before* the CALLSEQ_START.
1187 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1188 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1189 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1193 // Now that we legalized all of the inputs (which may have inserted
1194 // libcalls) create the new CALLSEQ_START node.
1195 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1197 // Merge in the last call, to ensure that this call start after the last
1199 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1200 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1201 Tmp1 = LegalizeOp(Tmp1);
1204 // Do not try to legalize the target-specific arguments (#1+).
1205 if (Tmp1 != Node->getOperand(0)) {
1206 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1208 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1211 // Remember that the CALLSEQ_START is legalized.
1212 AddLegalizedOperand(Op.getValue(0), Result);
1213 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1214 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1216 // Now that the callseq_start and all of the non-call nodes above this call
1217 // sequence have been legalized, legalize the call itself. During this
1218 // process, no libcalls can/will be inserted, guaranteeing that no calls
1220 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1221 SDOperand InCallSEQ = LastCALLSEQ_END;
1222 // Note that we are selecting this call!
1223 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1224 IsLegalizingCall = true;
1226 // Legalize the call, starting from the CALLSEQ_END.
1227 LegalizeOp(LastCALLSEQ_END);
1228 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1231 case ISD::CALLSEQ_END:
1232 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1233 // will cause this node to be legalized as well as handling libcalls right.
1234 if (LastCALLSEQ_END.Val != Node) {
1235 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1236 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1237 assert(I != LegalizedNodes.end() &&
1238 "Legalizing the call start should have legalized this node!");
1242 // Otherwise, the call start has been legalized and everything is going
1243 // according to plan. Just legalize ourselves normally here.
1244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1245 // Do not try to legalize the target-specific arguments (#1+), except for
1246 // an optional flag input.
1247 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1248 if (Tmp1 != Node->getOperand(0)) {
1249 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1251 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1254 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1255 if (Tmp1 != Node->getOperand(0) ||
1256 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1257 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1260 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1263 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1264 // This finishes up call legalization.
1265 IsLegalizingCall = false;
1267 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1268 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1269 if (Node->getNumValues() == 2)
1270 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1271 return Result.getValue(Op.ResNo);
1272 case ISD::DYNAMIC_STACKALLOC: {
1273 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1274 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1275 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1276 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1278 Tmp1 = Result.getValue(0);
1279 Tmp2 = Result.getValue(1);
1280 switch (TLI.getOperationAction(Node->getOpcode(),
1281 Node->getValueType(0))) {
1282 default: assert(0 && "This action is not supported yet!");
1283 case TargetLowering::Expand: {
1284 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1285 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1286 " not tell us which reg is the stack pointer!");
1287 SDOperand Chain = Tmp1.getOperand(0);
1288 SDOperand Size = Tmp2.getOperand(1);
1289 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1290 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1291 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1292 Tmp1 = LegalizeOp(Tmp1);
1293 Tmp2 = LegalizeOp(Tmp2);
1296 case TargetLowering::Custom:
1297 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1299 Tmp1 = LegalizeOp(Tmp3);
1300 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1303 case TargetLowering::Legal:
1306 // Since this op produce two values, make sure to remember that we
1307 // legalized both of them.
1308 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1309 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1310 return Op.ResNo ? Tmp2 : Tmp1;
1312 case ISD::INLINEASM: {
1313 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1314 bool Changed = false;
1315 // Legalize all of the operands of the inline asm, in case they are nodes
1316 // that need to be expanded or something. Note we skip the asm string and
1317 // all of the TargetConstant flags.
1318 SDOperand Op = LegalizeOp(Ops[0]);
1319 Changed = Op != Ops[0];
1322 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1323 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1324 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1325 for (++i; NumVals; ++i, --NumVals) {
1326 SDOperand Op = LegalizeOp(Ops[i]);
1335 Op = LegalizeOp(Ops.back());
1336 Changed |= Op != Ops.back();
1341 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1343 // INLINE asm returns a chain and flag, make sure to add both to the map.
1344 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1345 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1346 return Result.getValue(Op.ResNo);
1349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1350 // Ensure that libcalls are emitted before a branch.
1351 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1352 Tmp1 = LegalizeOp(Tmp1);
1353 LastCALLSEQ_END = DAG.getEntryNode();
1355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1359 // Ensure that libcalls are emitted before a branch.
1360 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1361 Tmp1 = LegalizeOp(Tmp1);
1362 LastCALLSEQ_END = DAG.getEntryNode();
1364 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1365 default: assert(0 && "Indirect target must be legal type (pointer)!");
1367 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1370 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1373 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1374 // Ensure that libcalls are emitted before a branch.
1375 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1376 Tmp1 = LegalizeOp(Tmp1);
1377 LastCALLSEQ_END = DAG.getEntryNode();
1379 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1382 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1383 default: assert(0 && "This action is not supported yet!");
1384 case TargetLowering::Legal: break;
1385 case TargetLowering::Custom:
1386 Tmp1 = TLI.LowerOperation(Result, DAG);
1387 if (Tmp1.Val) Result = Tmp1;
1389 case TargetLowering::Expand: {
1390 SDOperand Chain = Result.getOperand(0);
1391 SDOperand Table = Result.getOperand(1);
1392 SDOperand Index = Result.getOperand(2);
1394 MVT::ValueType PTy = TLI.getPointerTy();
1395 MachineFunction &MF = DAG.getMachineFunction();
1396 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1397 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1398 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1401 switch (EntrySize) {
1402 default: assert(0 && "Size of jump table not supported yet."); break;
1403 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1404 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1407 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1408 // For PIC, the sequence is:
1409 // BRIND(load(Jumptable + index) + RelocBase)
1410 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1412 if (TLI.usesGlobalOffsetTable())
1413 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1416 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1417 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1418 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1420 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1426 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1427 // Ensure that libcalls are emitted before a return.
1428 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1429 Tmp1 = LegalizeOp(Tmp1);
1430 LastCALLSEQ_END = DAG.getEntryNode();
1432 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1433 case Expand: assert(0 && "It's impossible to expand bools");
1435 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1438 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1440 // The top bits of the promoted condition are not necessarily zero, ensure
1441 // that the value is properly zero extended.
1442 if (!TLI.MaskedValueIsZero(Tmp2,
1443 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1444 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1448 // Basic block destination (Op#2) is always legal.
1449 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1451 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1452 default: assert(0 && "This action is not supported yet!");
1453 case TargetLowering::Legal: break;
1454 case TargetLowering::Custom:
1455 Tmp1 = TLI.LowerOperation(Result, DAG);
1456 if (Tmp1.Val) Result = Tmp1;
1458 case TargetLowering::Expand:
1459 // Expand brcond's setcc into its constituent parts and create a BR_CC
1461 if (Tmp2.getOpcode() == ISD::SETCC) {
1462 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1463 Tmp2.getOperand(0), Tmp2.getOperand(1),
1464 Node->getOperand(2));
1466 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1467 DAG.getCondCode(ISD::SETNE), Tmp2,
1468 DAG.getConstant(0, Tmp2.getValueType()),
1469 Node->getOperand(2));
1475 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1476 // Ensure that libcalls are emitted before a branch.
1477 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1478 Tmp1 = LegalizeOp(Tmp1);
1479 Tmp2 = Node->getOperand(2); // LHS
1480 Tmp3 = Node->getOperand(3); // RHS
1481 Tmp4 = Node->getOperand(1); // CC
1483 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1484 LastCALLSEQ_END = DAG.getEntryNode();
1486 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1487 // the LHS is a legal SETCC itself. In this case, we need to compare
1488 // the result against zero to select between true and false values.
1489 if (Tmp3.Val == 0) {
1490 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1491 Tmp4 = DAG.getCondCode(ISD::SETNE);
1494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1495 Node->getOperand(4));
1497 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1498 default: assert(0 && "Unexpected action for BR_CC!");
1499 case TargetLowering::Legal: break;
1500 case TargetLowering::Custom:
1501 Tmp4 = TLI.LowerOperation(Result, DAG);
1502 if (Tmp4.Val) Result = Tmp4;
1507 LoadSDNode *LD = cast<LoadSDNode>(Node);
1508 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1509 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1511 ISD::LoadExtType ExtType = LD->getExtensionType();
1512 if (ExtType == ISD::NON_EXTLOAD) {
1513 MVT::ValueType VT = Node->getValueType(0);
1514 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1515 Tmp3 = Result.getValue(0);
1516 Tmp4 = Result.getValue(1);
1518 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1519 default: assert(0 && "This action is not supported yet!");
1520 case TargetLowering::Legal: break;
1521 case TargetLowering::Custom:
1522 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1524 Tmp3 = LegalizeOp(Tmp1);
1525 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1528 case TargetLowering::Promote: {
1529 // Only promote a load of vector type to another.
1530 assert(MVT::isVector(VT) && "Cannot promote this load!");
1531 // Change base type to a different vector type.
1532 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1534 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1535 LD->getSrcValueOffset());
1536 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1537 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1541 // Since loads produce two values, make sure to remember that we
1542 // legalized both of them.
1543 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1544 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1545 return Op.ResNo ? Tmp4 : Tmp3;
1547 MVT::ValueType SrcVT = LD->getLoadedVT();
1548 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1549 default: assert(0 && "This action is not supported yet!");
1550 case TargetLowering::Promote:
1551 assert(SrcVT == MVT::i1 &&
1552 "Can only promote extending LOAD from i1 -> i8!");
1553 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1554 LD->getSrcValue(), LD->getSrcValueOffset(),
1556 Tmp1 = Result.getValue(0);
1557 Tmp2 = Result.getValue(1);
1559 case TargetLowering::Custom:
1562 case TargetLowering::Legal:
1563 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1564 Tmp1 = Result.getValue(0);
1565 Tmp2 = Result.getValue(1);
1568 Tmp3 = TLI.LowerOperation(Result, DAG);
1570 Tmp1 = LegalizeOp(Tmp3);
1571 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1575 case TargetLowering::Expand:
1576 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1577 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1578 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1579 LD->getSrcValueOffset());
1580 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1581 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1582 Tmp2 = LegalizeOp(Load.getValue(1));
1585 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1586 // Turn the unsupported load into an EXTLOAD followed by an explicit
1587 // zero/sign extend inreg.
1588 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1589 Tmp1, Tmp2, LD->getSrcValue(),
1590 LD->getSrcValueOffset(), SrcVT);
1592 if (ExtType == ISD::SEXTLOAD)
1593 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1594 Result, DAG.getValueType(SrcVT));
1596 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1597 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1598 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1601 // Since loads produce two values, make sure to remember that we legalized
1603 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1604 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1605 return Op.ResNo ? Tmp2 : Tmp1;
1608 case ISD::EXTRACT_ELEMENT: {
1609 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1610 switch (getTypeAction(OpTy)) {
1611 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1613 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1615 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1616 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1617 TLI.getShiftAmountTy()));
1618 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1621 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1622 Node->getOperand(0));
1626 // Get both the low and high parts.
1627 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1628 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1629 Result = Tmp2; // 1 -> Hi
1631 Result = Tmp1; // 0 -> Lo
1637 case ISD::CopyToReg:
1638 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1640 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1641 "Register type must be legal!");
1642 // Legalize the incoming value (must be a legal type).
1643 Tmp2 = LegalizeOp(Node->getOperand(2));
1644 if (Node->getNumValues() == 1) {
1645 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1647 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1648 if (Node->getNumOperands() == 4) {
1649 Tmp3 = LegalizeOp(Node->getOperand(3));
1650 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1653 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1656 // Since this produces two values, make sure to remember that we legalized
1658 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1659 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1665 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1667 // Ensure that libcalls are emitted before a return.
1668 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1669 Tmp1 = LegalizeOp(Tmp1);
1670 LastCALLSEQ_END = DAG.getEntryNode();
1672 switch (Node->getNumOperands()) {
1674 Tmp2 = Node->getOperand(1);
1675 Tmp3 = Node->getOperand(2); // Signness
1676 switch (getTypeAction(Tmp2.getValueType())) {
1678 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1681 if (Tmp2.getValueType() != MVT::Vector) {
1683 ExpandOp(Tmp2, Lo, Hi);
1685 // Big endian systems want the hi reg first.
1686 if (!TLI.isLittleEndian())
1690 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1692 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1693 Result = LegalizeOp(Result);
1695 SDNode *InVal = Tmp2.Val;
1697 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1698 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1700 // Figure out if there is a Packed type corresponding to this Vector
1701 // type. If so, convert to the vector type.
1702 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1703 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1704 // Turn this into a return of the vector type.
1705 Tmp2 = PackVectorOp(Tmp2, TVT);
1706 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1707 } else if (NumElems == 1) {
1708 // Turn this into a return of the scalar type.
1709 Tmp2 = PackVectorOp(Tmp2, EVT);
1710 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1712 // FIXME: Returns of gcc generic vectors smaller than a legal type
1713 // should be returned in integer registers!
1715 // The scalarized value type may not be legal, e.g. it might require
1716 // promotion or expansion. Relegalize the return.
1717 Result = LegalizeOp(Result);
1719 // FIXME: Returns of gcc generic vectors larger than a legal vector
1720 // type should be returned by reference!
1722 SplitVectorOp(Tmp2, Lo, Hi);
1723 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1724 Result = LegalizeOp(Result);
1729 Tmp2 = PromoteOp(Node->getOperand(1));
1730 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1731 Result = LegalizeOp(Result);
1736 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1738 default: { // ret <values>
1739 SmallVector<SDOperand, 8> NewValues;
1740 NewValues.push_back(Tmp1);
1741 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1742 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1744 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1745 NewValues.push_back(Node->getOperand(i+1));
1749 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1750 "FIXME: TODO: implement returning non-legal vector types!");
1751 ExpandOp(Node->getOperand(i), Lo, Hi);
1752 NewValues.push_back(Lo);
1753 NewValues.push_back(Node->getOperand(i+1));
1755 NewValues.push_back(Hi);
1756 NewValues.push_back(Node->getOperand(i+1));
1761 assert(0 && "Can't promote multiple return value yet!");
1764 if (NewValues.size() == Node->getNumOperands())
1765 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1767 Result = DAG.getNode(ISD::RET, MVT::Other,
1768 &NewValues[0], NewValues.size());
1773 if (Result.getOpcode() == ISD::RET) {
1774 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1775 default: assert(0 && "This action is not supported yet!");
1776 case TargetLowering::Legal: break;
1777 case TargetLowering::Custom:
1778 Tmp1 = TLI.LowerOperation(Result, DAG);
1779 if (Tmp1.Val) Result = Tmp1;
1785 StoreSDNode *ST = cast<StoreSDNode>(Node);
1786 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1787 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1789 if (!ST->isTruncatingStore()) {
1790 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1791 // FIXME: We shouldn't do this for TargetConstantFP's.
1792 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1793 // to phase ordering between legalized code and the dag combiner. This
1794 // probably means that we need to integrate dag combiner and legalizer
1796 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1797 if (CFP->getValueType(0) == MVT::f32) {
1798 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1800 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1801 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1803 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1804 ST->getSrcValueOffset());
1808 switch (getTypeAction(ST->getStoredVT())) {
1810 Tmp3 = LegalizeOp(ST->getValue());
1811 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1814 MVT::ValueType VT = Tmp3.getValueType();
1815 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1816 default: assert(0 && "This action is not supported yet!");
1817 case TargetLowering::Legal: break;
1818 case TargetLowering::Custom:
1819 Tmp1 = TLI.LowerOperation(Result, DAG);
1820 if (Tmp1.Val) Result = Tmp1;
1822 case TargetLowering::Promote:
1823 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1824 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1825 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1826 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1827 ST->getSrcValue(), ST->getSrcValueOffset());
1833 // Truncate the value and store the result.
1834 Tmp3 = PromoteOp(ST->getValue());
1835 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1836 ST->getSrcValueOffset(), ST->getStoredVT());
1840 unsigned IncrementSize = 0;
1843 // If this is a vector type, then we have to calculate the increment as
1844 // the product of the element size in bytes, and the number of elements
1845 // in the high half of the vector.
1846 if (ST->getValue().getValueType() == MVT::Vector) {
1847 SDNode *InVal = ST->getValue().Val;
1849 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1850 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1852 // Figure out if there is a Packed type corresponding to this Vector
1853 // type. If so, convert to the vector type.
1854 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1855 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1856 // Turn this into a normal store of the vector type.
1857 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1858 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1859 ST->getSrcValueOffset());
1860 Result = LegalizeOp(Result);
1862 } else if (NumElems == 1) {
1863 // Turn this into a normal store of the scalar type.
1864 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1865 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1866 ST->getSrcValueOffset());
1867 // The scalarized value type may not be legal, e.g. it might require
1868 // promotion or expansion. Relegalize the scalar store.
1869 Result = LegalizeOp(Result);
1872 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1873 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1876 ExpandOp(Node->getOperand(1), Lo, Hi);
1877 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1879 if (!TLI.isLittleEndian())
1883 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1884 ST->getSrcValueOffset());
1886 if (Hi.Val == NULL) {
1887 // Must be int <-> float one-to-one expansion.
1892 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1893 getIntPtrConstant(IncrementSize));
1894 assert(isTypeLegal(Tmp2.getValueType()) &&
1895 "Pointers must be legal!");
1896 // FIXME: This sets the srcvalue of both halves to be the same, which is
1898 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1899 ST->getSrcValueOffset());
1900 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1905 assert(isTypeLegal(ST->getValue().getValueType()) &&
1906 "Cannot handle illegal TRUNCSTORE yet!");
1907 Tmp3 = LegalizeOp(ST->getValue());
1909 // The only promote case we handle is TRUNCSTORE:i1 X into
1910 // -> TRUNCSTORE:i8 (and X, 1)
1911 if (ST->getStoredVT() == MVT::i1 &&
1912 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1913 // Promote the bool to a mask then store.
1914 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1915 DAG.getConstant(1, Tmp3.getValueType()));
1916 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1917 ST->getSrcValueOffset(), MVT::i8);
1918 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1919 Tmp2 != ST->getBasePtr()) {
1920 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1924 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1925 switch (TLI.getStoreXAction(StVT)) {
1926 default: assert(0 && "This action is not supported yet!");
1927 case TargetLowering::Legal: break;
1928 case TargetLowering::Custom:
1929 Tmp1 = TLI.LowerOperation(Result, DAG);
1930 if (Tmp1.Val) Result = Tmp1;
1937 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1940 case ISD::STACKSAVE:
1941 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1942 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1943 Tmp1 = Result.getValue(0);
1944 Tmp2 = Result.getValue(1);
1946 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1947 default: assert(0 && "This action is not supported yet!");
1948 case TargetLowering::Legal: break;
1949 case TargetLowering::Custom:
1950 Tmp3 = TLI.LowerOperation(Result, DAG);
1952 Tmp1 = LegalizeOp(Tmp3);
1953 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1956 case TargetLowering::Expand:
1957 // Expand to CopyFromReg if the target set
1958 // StackPointerRegisterToSaveRestore.
1959 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1960 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1961 Node->getValueType(0));
1962 Tmp2 = Tmp1.getValue(1);
1964 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1965 Tmp2 = Node->getOperand(0);
1970 // Since stacksave produce two values, make sure to remember that we
1971 // legalized both of them.
1972 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1973 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1974 return Op.ResNo ? Tmp2 : Tmp1;
1976 case ISD::STACKRESTORE:
1977 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1978 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1979 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1981 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1982 default: assert(0 && "This action is not supported yet!");
1983 case TargetLowering::Legal: break;
1984 case TargetLowering::Custom:
1985 Tmp1 = TLI.LowerOperation(Result, DAG);
1986 if (Tmp1.Val) Result = Tmp1;
1988 case TargetLowering::Expand:
1989 // Expand to CopyToReg if the target set
1990 // StackPointerRegisterToSaveRestore.
1991 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1992 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2000 case ISD::READCYCLECOUNTER:
2001 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2002 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2003 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2004 Node->getValueType(0))) {
2005 default: assert(0 && "This action is not supported yet!");
2006 case TargetLowering::Legal:
2007 Tmp1 = Result.getValue(0);
2008 Tmp2 = Result.getValue(1);
2010 case TargetLowering::Custom:
2011 Result = TLI.LowerOperation(Result, DAG);
2012 Tmp1 = LegalizeOp(Result.getValue(0));
2013 Tmp2 = LegalizeOp(Result.getValue(1));
2017 // Since rdcc produce two values, make sure to remember that we legalized
2019 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2020 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2024 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2025 case Expand: assert(0 && "It's impossible to expand bools");
2027 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2030 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2031 // Make sure the condition is either zero or one.
2032 if (!TLI.MaskedValueIsZero(Tmp1,
2033 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2034 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2037 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2038 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2040 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2042 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2043 default: assert(0 && "This action is not supported yet!");
2044 case TargetLowering::Legal: break;
2045 case TargetLowering::Custom: {
2046 Tmp1 = TLI.LowerOperation(Result, DAG);
2047 if (Tmp1.Val) Result = Tmp1;
2050 case TargetLowering::Expand:
2051 if (Tmp1.getOpcode() == ISD::SETCC) {
2052 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2054 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2056 Result = DAG.getSelectCC(Tmp1,
2057 DAG.getConstant(0, Tmp1.getValueType()),
2058 Tmp2, Tmp3, ISD::SETNE);
2061 case TargetLowering::Promote: {
2062 MVT::ValueType NVT =
2063 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2064 unsigned ExtOp, TruncOp;
2065 if (MVT::isVector(Tmp2.getValueType())) {
2066 ExtOp = ISD::BIT_CONVERT;
2067 TruncOp = ISD::BIT_CONVERT;
2068 } else if (MVT::isInteger(Tmp2.getValueType())) {
2069 ExtOp = ISD::ANY_EXTEND;
2070 TruncOp = ISD::TRUNCATE;
2072 ExtOp = ISD::FP_EXTEND;
2073 TruncOp = ISD::FP_ROUND;
2075 // Promote each of the values to the new type.
2076 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2077 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2078 // Perform the larger operation, then round down.
2079 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2080 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2085 case ISD::SELECT_CC: {
2086 Tmp1 = Node->getOperand(0); // LHS
2087 Tmp2 = Node->getOperand(1); // RHS
2088 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2089 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2090 SDOperand CC = Node->getOperand(4);
2092 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2094 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2095 // the LHS is a legal SETCC itself. In this case, we need to compare
2096 // the result against zero to select between true and false values.
2097 if (Tmp2.Val == 0) {
2098 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2099 CC = DAG.getCondCode(ISD::SETNE);
2101 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2103 // Everything is legal, see if we should expand this op or something.
2104 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2105 default: assert(0 && "This action is not supported yet!");
2106 case TargetLowering::Legal: break;
2107 case TargetLowering::Custom:
2108 Tmp1 = TLI.LowerOperation(Result, DAG);
2109 if (Tmp1.Val) Result = Tmp1;
2115 Tmp1 = Node->getOperand(0);
2116 Tmp2 = Node->getOperand(1);
2117 Tmp3 = Node->getOperand(2);
2118 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2120 // If we had to Expand the SetCC operands into a SELECT node, then it may
2121 // not always be possible to return a true LHS & RHS. In this case, just
2122 // return the value we legalized, returned in the LHS
2123 if (Tmp2.Val == 0) {
2128 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2129 default: assert(0 && "Cannot handle this action for SETCC yet!");
2130 case TargetLowering::Custom:
2133 case TargetLowering::Legal:
2134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2136 Tmp4 = TLI.LowerOperation(Result, DAG);
2137 if (Tmp4.Val) Result = Tmp4;
2140 case TargetLowering::Promote: {
2141 // First step, figure out the appropriate operation to use.
2142 // Allow SETCC to not be supported for all legal data types
2143 // Mostly this targets FP
2144 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2145 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2147 // Scan for the appropriate larger type to use.
2149 NewInTy = (MVT::ValueType)(NewInTy+1);
2151 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2152 "Fell off of the edge of the integer world");
2153 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2154 "Fell off of the edge of the floating point world");
2156 // If the target supports SETCC of this type, use it.
2157 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2160 if (MVT::isInteger(NewInTy))
2161 assert(0 && "Cannot promote Legal Integer SETCC yet");
2163 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2164 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2166 Tmp1 = LegalizeOp(Tmp1);
2167 Tmp2 = LegalizeOp(Tmp2);
2168 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2169 Result = LegalizeOp(Result);
2172 case TargetLowering::Expand:
2173 // Expand a setcc node into a select_cc of the same condition, lhs, and
2174 // rhs that selects between const 1 (true) and const 0 (false).
2175 MVT::ValueType VT = Node->getValueType(0);
2176 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2177 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2184 case ISD::MEMMOVE: {
2185 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2186 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2188 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2189 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2190 case Expand: assert(0 && "Cannot expand a byte!");
2192 Tmp3 = LegalizeOp(Node->getOperand(2));
2195 Tmp3 = PromoteOp(Node->getOperand(2));
2199 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2203 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2205 // Length is too big, just take the lo-part of the length.
2207 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2211 Tmp4 = LegalizeOp(Node->getOperand(3));
2214 Tmp4 = PromoteOp(Node->getOperand(3));
2219 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2220 case Expand: assert(0 && "Cannot expand this yet!");
2222 Tmp5 = LegalizeOp(Node->getOperand(4));
2225 Tmp5 = PromoteOp(Node->getOperand(4));
2229 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2230 default: assert(0 && "This action not implemented for this operation!");
2231 case TargetLowering::Custom:
2234 case TargetLowering::Legal:
2235 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2237 Tmp1 = TLI.LowerOperation(Result, DAG);
2238 if (Tmp1.Val) Result = Tmp1;
2241 case TargetLowering::Expand: {
2242 // Otherwise, the target does not support this operation. Lower the
2243 // operation to an explicit libcall as appropriate.
2244 MVT::ValueType IntPtr = TLI.getPointerTy();
2245 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2246 TargetLowering::ArgListTy Args;
2247 TargetLowering::ArgListEntry Entry;
2249 const char *FnName = 0;
2250 if (Node->getOpcode() == ISD::MEMSET) {
2251 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2252 Args.push_back(Entry);
2253 // Extend the (previously legalized) ubyte argument to be an int value
2255 if (Tmp3.getValueType() > MVT::i32)
2256 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2258 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2259 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2260 Args.push_back(Entry);
2261 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2262 Args.push_back(Entry);
2265 } else if (Node->getOpcode() == ISD::MEMCPY ||
2266 Node->getOpcode() == ISD::MEMMOVE) {
2267 Entry.Ty = IntPtrTy;
2268 Entry.Node = Tmp2; Args.push_back(Entry);
2269 Entry.Node = Tmp3; Args.push_back(Entry);
2270 Entry.Node = Tmp4; Args.push_back(Entry);
2271 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2273 assert(0 && "Unknown op!");
2276 std::pair<SDOperand,SDOperand> CallResult =
2277 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2278 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2279 Result = CallResult.second;
2286 case ISD::SHL_PARTS:
2287 case ISD::SRA_PARTS:
2288 case ISD::SRL_PARTS: {
2289 SmallVector<SDOperand, 8> Ops;
2290 bool Changed = false;
2291 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2292 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2293 Changed |= Ops.back() != Node->getOperand(i);
2296 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2298 switch (TLI.getOperationAction(Node->getOpcode(),
2299 Node->getValueType(0))) {
2300 default: assert(0 && "This action is not supported yet!");
2301 case TargetLowering::Legal: break;
2302 case TargetLowering::Custom:
2303 Tmp1 = TLI.LowerOperation(Result, DAG);
2305 SDOperand Tmp2, RetVal(0, 0);
2306 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2307 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2308 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2312 assert(RetVal.Val && "Illegal result number");
2318 // Since these produce multiple values, make sure to remember that we
2319 // legalized all of them.
2320 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2321 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2322 return Result.getValue(Op.ResNo);
2343 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2344 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2345 case Expand: assert(0 && "Not possible");
2347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2350 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2354 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2356 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2357 default: assert(0 && "BinOp legalize operation not supported");
2358 case TargetLowering::Legal: break;
2359 case TargetLowering::Custom:
2360 Tmp1 = TLI.LowerOperation(Result, DAG);
2361 if (Tmp1.Val) Result = Tmp1;
2363 case TargetLowering::Expand: {
2364 if (Node->getValueType(0) == MVT::i32) {
2365 switch (Node->getOpcode()) {
2366 default: assert(0 && "Do not know how to expand this integer BinOp!");
2369 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2370 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2372 bool isSigned = Node->getOpcode() == ISD::SDIV;
2373 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2378 assert(MVT::isVector(Node->getValueType(0)) &&
2379 "Cannot expand this binary operator!");
2380 // Expand the operation into a bunch of nasty scalar code.
2381 SmallVector<SDOperand, 8> Ops;
2382 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2383 MVT::ValueType PtrVT = TLI.getPointerTy();
2384 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2386 SDOperand Idx = DAG.getConstant(i, PtrVT);
2387 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2388 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2389 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2391 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2392 &Ops[0], Ops.size());
2395 case TargetLowering::Promote: {
2396 switch (Node->getOpcode()) {
2397 default: assert(0 && "Do not know how to promote this BinOp!");
2401 MVT::ValueType OVT = Node->getValueType(0);
2402 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2403 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2404 // Bit convert each of the values to the new type.
2405 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2406 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2407 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2408 // Bit convert the result back the original type.
2409 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2417 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2418 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2419 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2420 case Expand: assert(0 && "Not possible");
2422 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2425 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2429 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2431 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2432 default: assert(0 && "Operation not supported");
2433 case TargetLowering::Custom:
2434 Tmp1 = TLI.LowerOperation(Result, DAG);
2435 if (Tmp1.Val) Result = Tmp1;
2437 case TargetLowering::Legal: break;
2438 case TargetLowering::Expand: {
2439 // If this target supports fabs/fneg natively and select is cheap,
2440 // do this efficiently.
2441 if (!TLI.isSelectExpensive() &&
2442 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2443 TargetLowering::Legal &&
2444 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2445 TargetLowering::Legal) {
2446 // Get the sign bit of the RHS.
2447 MVT::ValueType IVT =
2448 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2449 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2450 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2451 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2452 // Get the absolute value of the result.
2453 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2454 // Select between the nabs and abs value based on the sign bit of
2456 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2457 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2460 Result = LegalizeOp(Result);
2464 // Otherwise, do bitwise ops!
2465 MVT::ValueType NVT =
2466 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2467 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2468 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2469 Result = LegalizeOp(Result);
2477 Tmp1 = LegalizeOp(Node->getOperand(0));
2478 Tmp2 = LegalizeOp(Node->getOperand(1));
2479 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2480 // Since this produces two values, make sure to remember that we legalized
2482 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2483 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2488 Tmp1 = LegalizeOp(Node->getOperand(0));
2489 Tmp2 = LegalizeOp(Node->getOperand(1));
2490 Tmp3 = LegalizeOp(Node->getOperand(2));
2491 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2492 // Since this produces two values, make sure to remember that we legalized
2494 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2495 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2498 case ISD::BUILD_PAIR: {
2499 MVT::ValueType PairTy = Node->getValueType(0);
2500 // TODO: handle the case where the Lo and Hi operands are not of legal type
2501 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2502 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2503 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2504 case TargetLowering::Promote:
2505 case TargetLowering::Custom:
2506 assert(0 && "Cannot promote/custom this yet!");
2507 case TargetLowering::Legal:
2508 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2509 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2511 case TargetLowering::Expand:
2512 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2513 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2514 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2515 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2516 TLI.getShiftAmountTy()));
2517 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2526 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2527 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2529 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2530 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2531 case TargetLowering::Custom:
2534 case TargetLowering::Legal:
2535 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2537 Tmp1 = TLI.LowerOperation(Result, DAG);
2538 if (Tmp1.Val) Result = Tmp1;
2541 case TargetLowering::Expand:
2542 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2543 bool isSigned = DivOpc == ISD::SDIV;
2544 if (MVT::isInteger(Node->getValueType(0))) {
2545 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2546 TargetLowering::Legal) {
2548 MVT::ValueType VT = Node->getValueType(0);
2549 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2550 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2551 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2553 assert(Node->getValueType(0) == MVT::i32 &&
2554 "Cannot expand this binary operator!");
2555 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2556 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2558 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2561 // Floating point mod -> fmod libcall.
2562 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2563 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2565 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2566 false/*sign irrelevant*/, Dummy);
2572 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2573 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2575 MVT::ValueType VT = Node->getValueType(0);
2576 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2577 default: assert(0 && "This action is not supported yet!");
2578 case TargetLowering::Custom:
2581 case TargetLowering::Legal:
2582 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2583 Result = Result.getValue(0);
2584 Tmp1 = Result.getValue(1);
2587 Tmp2 = TLI.LowerOperation(Result, DAG);
2589 Result = LegalizeOp(Tmp2);
2590 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2594 case TargetLowering::Expand: {
2595 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2596 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2597 SV->getValue(), SV->getOffset());
2598 // Increment the pointer, VAList, to the next vaarg
2599 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2600 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2601 TLI.getPointerTy()));
2602 // Store the incremented VAList to the legalized pointer
2603 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2605 // Load the actual argument out of the pointer VAList
2606 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2607 Tmp1 = LegalizeOp(Result.getValue(1));
2608 Result = LegalizeOp(Result);
2612 // Since VAARG produces two values, make sure to remember that we
2613 // legalized both of them.
2614 AddLegalizedOperand(SDOperand(Node, 0), Result);
2615 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2616 return Op.ResNo ? Tmp1 : Result;
2620 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2621 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2622 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2624 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2625 default: assert(0 && "This action is not supported yet!");
2626 case TargetLowering::Custom:
2629 case TargetLowering::Legal:
2630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2631 Node->getOperand(3), Node->getOperand(4));
2633 Tmp1 = TLI.LowerOperation(Result, DAG);
2634 if (Tmp1.Val) Result = Tmp1;
2637 case TargetLowering::Expand:
2638 // This defaults to loading a pointer from the input and storing it to the
2639 // output, returning the chain.
2640 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2641 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2642 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2644 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2651 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2652 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2654 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2655 default: assert(0 && "This action is not supported yet!");
2656 case TargetLowering::Custom:
2659 case TargetLowering::Legal:
2660 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2662 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2663 if (Tmp1.Val) Result = Tmp1;
2666 case TargetLowering::Expand:
2667 Result = Tmp1; // Default to a no-op, return the chain
2673 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2674 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2676 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2678 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2679 default: assert(0 && "This action is not supported yet!");
2680 case TargetLowering::Legal: break;
2681 case TargetLowering::Custom:
2682 Tmp1 = TLI.LowerOperation(Result, DAG);
2683 if (Tmp1.Val) Result = Tmp1;
2690 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2691 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2693 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2695 assert(0 && "ROTL/ROTR legalize operation not supported");
2697 case TargetLowering::Legal:
2699 case TargetLowering::Custom:
2700 Tmp1 = TLI.LowerOperation(Result, DAG);
2701 if (Tmp1.Val) Result = Tmp1;
2703 case TargetLowering::Promote:
2704 assert(0 && "Do not know how to promote ROTL/ROTR");
2706 case TargetLowering::Expand:
2707 assert(0 && "Do not know how to expand ROTL/ROTR");
2713 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2714 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2715 case TargetLowering::Custom:
2716 assert(0 && "Cannot custom legalize this yet!");
2717 case TargetLowering::Legal:
2718 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2720 case TargetLowering::Promote: {
2721 MVT::ValueType OVT = Tmp1.getValueType();
2722 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2723 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2725 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2726 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2727 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2728 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2731 case TargetLowering::Expand:
2732 Result = ExpandBSWAP(Tmp1);
2740 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2741 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2742 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2743 case TargetLowering::Legal:
2744 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2746 case TargetLowering::Promote: {
2747 MVT::ValueType OVT = Tmp1.getValueType();
2748 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2750 // Zero extend the argument.
2751 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2752 // Perform the larger operation, then subtract if needed.
2753 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2754 switch (Node->getOpcode()) {
2759 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2760 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2761 DAG.getConstant(getSizeInBits(NVT), NVT),
2763 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2764 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2767 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2768 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2769 DAG.getConstant(getSizeInBits(NVT) -
2770 getSizeInBits(OVT), NVT));
2775 case TargetLowering::Expand:
2776 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2787 Tmp1 = LegalizeOp(Node->getOperand(0));
2788 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2789 case TargetLowering::Promote:
2790 case TargetLowering::Custom:
2793 case TargetLowering::Legal:
2794 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2796 Tmp1 = TLI.LowerOperation(Result, DAG);
2797 if (Tmp1.Val) Result = Tmp1;
2800 case TargetLowering::Expand:
2801 switch (Node->getOpcode()) {
2802 default: assert(0 && "Unreachable!");
2804 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2805 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2806 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2809 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2810 MVT::ValueType VT = Node->getValueType(0);
2811 Tmp2 = DAG.getConstantFP(0.0, VT);
2812 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2813 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2814 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2820 MVT::ValueType VT = Node->getValueType(0);
2821 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2822 switch(Node->getOpcode()) {
2824 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2827 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2830 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2832 default: assert(0 && "Unreachable!");
2835 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2836 false/*sign irrelevant*/, Dummy);
2844 // We always lower FPOWI into a libcall. No target support it yet.
2845 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2846 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2848 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2849 false/*sign irrelevant*/, Dummy);
2852 case ISD::BIT_CONVERT:
2853 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2854 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2856 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2857 Node->getOperand(0).getValueType())) {
2858 default: assert(0 && "Unknown operation action!");
2859 case TargetLowering::Expand:
2860 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2862 case TargetLowering::Legal:
2863 Tmp1 = LegalizeOp(Node->getOperand(0));
2864 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2869 case ISD::VBIT_CONVERT: {
2870 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2871 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2873 // The input has to be a vector type, we have to either scalarize it, pack
2874 // it, or convert it based on whether the input vector type is legal.
2875 SDNode *InVal = Node->getOperand(0).Val;
2877 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2878 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2880 // Figure out if there is a Packed type corresponding to this Vector
2881 // type. If so, convert to the vector type.
2882 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2883 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2884 // Turn this into a bit convert of the packed input.
2885 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2886 PackVectorOp(Node->getOperand(0), TVT));
2888 } else if (NumElems == 1) {
2889 // Turn this into a bit convert of the scalar input.
2890 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2891 PackVectorOp(Node->getOperand(0), EVT));
2894 // FIXME: UNIMP! Store then reload
2895 assert(0 && "Cast from unsupported vector type not implemented yet!");
2899 // Conversion operators. The source and destination have different types.
2900 case ISD::SINT_TO_FP:
2901 case ISD::UINT_TO_FP: {
2902 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2903 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2905 switch (TLI.getOperationAction(Node->getOpcode(),
2906 Node->getOperand(0).getValueType())) {
2907 default: assert(0 && "Unknown operation action!");
2908 case TargetLowering::Custom:
2911 case TargetLowering::Legal:
2912 Tmp1 = LegalizeOp(Node->getOperand(0));
2913 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2915 Tmp1 = TLI.LowerOperation(Result, DAG);
2916 if (Tmp1.Val) Result = Tmp1;
2919 case TargetLowering::Expand:
2920 Result = ExpandLegalINT_TO_FP(isSigned,
2921 LegalizeOp(Node->getOperand(0)),
2922 Node->getValueType(0));
2924 case TargetLowering::Promote:
2925 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2926 Node->getValueType(0),
2932 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2933 Node->getValueType(0), Node->getOperand(0));
2936 Tmp1 = PromoteOp(Node->getOperand(0));
2938 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2939 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2941 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2942 Node->getOperand(0).getValueType());
2944 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2945 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2951 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2953 Tmp1 = LegalizeOp(Node->getOperand(0));
2954 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2957 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2959 // Since the result is legal, we should just be able to truncate the low
2960 // part of the source.
2961 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2964 Result = PromoteOp(Node->getOperand(0));
2965 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2970 case ISD::FP_TO_SINT:
2971 case ISD::FP_TO_UINT:
2972 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2974 Tmp1 = LegalizeOp(Node->getOperand(0));
2976 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2977 default: assert(0 && "Unknown operation action!");
2978 case TargetLowering::Custom:
2981 case TargetLowering::Legal:
2982 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2984 Tmp1 = TLI.LowerOperation(Result, DAG);
2985 if (Tmp1.Val) Result = Tmp1;
2988 case TargetLowering::Promote:
2989 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2990 Node->getOpcode() == ISD::FP_TO_SINT);
2992 case TargetLowering::Expand:
2993 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2994 SDOperand True, False;
2995 MVT::ValueType VT = Node->getOperand(0).getValueType();
2996 MVT::ValueType NVT = Node->getValueType(0);
2997 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2998 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2999 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3000 Node->getOperand(0), Tmp2, ISD::SETLT);
3001 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3002 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3003 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3005 False = DAG.getNode(ISD::XOR, NVT, False,
3006 DAG.getConstant(1ULL << ShiftAmt, NVT));
3007 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3010 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3016 // Convert f32 / f64 to i32 / i64.
3017 MVT::ValueType VT = Op.getValueType();
3018 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3019 switch (Node->getOpcode()) {
3020 case ISD::FP_TO_SINT:
3021 if (Node->getOperand(0).getValueType() == MVT::f32)
3022 LC = (VT == MVT::i32)
3023 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3025 LC = (VT == MVT::i32)
3026 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3028 case ISD::FP_TO_UINT:
3029 if (Node->getOperand(0).getValueType() == MVT::f32)
3030 LC = (VT == MVT::i32)
3031 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3033 LC = (VT == MVT::i32)
3034 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3036 default: assert(0 && "Unreachable!");
3039 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3040 false/*sign irrelevant*/, Dummy);
3044 Tmp1 = PromoteOp(Node->getOperand(0));
3045 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3046 Result = LegalizeOp(Result);
3051 case ISD::ANY_EXTEND:
3052 case ISD::ZERO_EXTEND:
3053 case ISD::SIGN_EXTEND:
3054 case ISD::FP_EXTEND:
3056 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3057 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3059 Tmp1 = LegalizeOp(Node->getOperand(0));
3060 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3063 switch (Node->getOpcode()) {
3064 case ISD::ANY_EXTEND:
3065 Tmp1 = PromoteOp(Node->getOperand(0));
3066 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3068 case ISD::ZERO_EXTEND:
3069 Result = PromoteOp(Node->getOperand(0));
3070 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3071 Result = DAG.getZeroExtendInReg(Result,
3072 Node->getOperand(0).getValueType());
3074 case ISD::SIGN_EXTEND:
3075 Result = PromoteOp(Node->getOperand(0));
3076 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3077 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3079 DAG.getValueType(Node->getOperand(0).getValueType()));
3081 case ISD::FP_EXTEND:
3082 Result = PromoteOp(Node->getOperand(0));
3083 if (Result.getValueType() != Op.getValueType())
3084 // Dynamically dead while we have only 2 FP types.
3085 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3088 Result = PromoteOp(Node->getOperand(0));
3089 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3094 case ISD::FP_ROUND_INREG:
3095 case ISD::SIGN_EXTEND_INREG: {
3096 Tmp1 = LegalizeOp(Node->getOperand(0));
3097 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3099 // If this operation is not supported, convert it to a shl/shr or load/store
3101 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3102 default: assert(0 && "This action not supported for this op yet!");
3103 case TargetLowering::Legal:
3104 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3106 case TargetLowering::Expand:
3107 // If this is an integer extend and shifts are supported, do that.
3108 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3109 // NOTE: we could fall back on load/store here too for targets without
3110 // SAR. However, it is doubtful that any exist.
3111 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3112 MVT::getSizeInBits(ExtraVT);
3113 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3114 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3115 Node->getOperand(0), ShiftCst);
3116 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3118 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3119 // The only way we can lower this is to turn it into a TRUNCSTORE,
3120 // EXTLOAD pair, targetting a temporary location (a stack slot).
3122 // NOTE: there is a choice here between constantly creating new stack
3123 // slots and always reusing the same one. We currently always create
3124 // new ones, as reuse may inhibit scheduling.
3125 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3126 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
3127 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3128 MachineFunction &MF = DAG.getMachineFunction();
3130 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
3131 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3132 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3133 StackSlot, NULL, 0, ExtraVT);
3134 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3135 Result, StackSlot, NULL, 0, ExtraVT);
3137 assert(0 && "Unknown op");
3145 assert(Result.getValueType() == Op.getValueType() &&
3146 "Bad legalization!");
3148 // Make sure that the generated code is itself legal.
3150 Result = LegalizeOp(Result);
3152 // Note that LegalizeOp may be reentered even from single-use nodes, which
3153 // means that we always must cache transformed nodes.
3154 AddLegalizedOperand(Op, Result);
3158 /// PromoteOp - Given an operation that produces a value in an invalid type,
3159 /// promote it to compute the value into a larger type. The produced value will
3160 /// have the correct bits for the low portion of the register, but no guarantee
3161 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3162 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3163 MVT::ValueType VT = Op.getValueType();
3164 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3165 assert(getTypeAction(VT) == Promote &&
3166 "Caller should expand or legalize operands that are not promotable!");
3167 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3168 "Cannot promote to smaller type!");
3170 SDOperand Tmp1, Tmp2, Tmp3;
3172 SDNode *Node = Op.Val;
3174 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3175 if (I != PromotedNodes.end()) return I->second;
3177 switch (Node->getOpcode()) {
3178 case ISD::CopyFromReg:
3179 assert(0 && "CopyFromReg must be legal!");
3182 cerr << "NODE: "; Node->dump(); cerr << "\n";
3184 assert(0 && "Do not know how to promote this operator!");
3187 Result = DAG.getNode(ISD::UNDEF, NVT);
3191 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3193 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3194 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3196 case ISD::ConstantFP:
3197 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3198 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3202 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3203 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3204 Node->getOperand(1), Node->getOperand(2));
3208 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3210 Result = LegalizeOp(Node->getOperand(0));
3211 assert(Result.getValueType() >= NVT &&
3212 "This truncation doesn't make sense!");
3213 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3214 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3217 // The truncation is not required, because we don't guarantee anything
3218 // about high bits anyway.
3219 Result = PromoteOp(Node->getOperand(0));
3222 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3223 // Truncate the low part of the expanded value to the result type
3224 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3227 case ISD::SIGN_EXTEND:
3228 case ISD::ZERO_EXTEND:
3229 case ISD::ANY_EXTEND:
3230 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3231 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3233 // Input is legal? Just do extend all the way to the larger type.
3234 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3237 // Promote the reg if it's smaller.
3238 Result = PromoteOp(Node->getOperand(0));
3239 // The high bits are not guaranteed to be anything. Insert an extend.
3240 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3241 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3242 DAG.getValueType(Node->getOperand(0).getValueType()));
3243 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3244 Result = DAG.getZeroExtendInReg(Result,
3245 Node->getOperand(0).getValueType());
3249 case ISD::BIT_CONVERT:
3250 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3251 Result = PromoteOp(Result);
3254 case ISD::FP_EXTEND:
3255 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3257 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3258 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3259 case Promote: assert(0 && "Unreachable with 2 FP types!");
3261 // Input is legal? Do an FP_ROUND_INREG.
3262 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3263 DAG.getValueType(VT));
3268 case ISD::SINT_TO_FP:
3269 case ISD::UINT_TO_FP:
3270 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3272 // No extra round required here.
3273 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3277 Result = PromoteOp(Node->getOperand(0));
3278 if (Node->getOpcode() == ISD::SINT_TO_FP)
3279 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3281 DAG.getValueType(Node->getOperand(0).getValueType()));
3283 Result = DAG.getZeroExtendInReg(Result,
3284 Node->getOperand(0).getValueType());
3285 // No extra round required here.
3286 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3289 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3290 Node->getOperand(0));
3291 // Round if we cannot tolerate excess precision.
3292 if (NoExcessFPPrecision)
3293 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3294 DAG.getValueType(VT));
3299 case ISD::SIGN_EXTEND_INREG:
3300 Result = PromoteOp(Node->getOperand(0));
3301 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3302 Node->getOperand(1));
3304 case ISD::FP_TO_SINT:
3305 case ISD::FP_TO_UINT:
3306 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3309 Tmp1 = Node->getOperand(0);
3312 // The input result is prerounded, so we don't have to do anything
3314 Tmp1 = PromoteOp(Node->getOperand(0));
3317 // If we're promoting a UINT to a larger size, check to see if the new node
3318 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3319 // we can use that instead. This allows us to generate better code for
3320 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3321 // legal, such as PowerPC.
3322 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3323 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3324 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3325 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3326 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3328 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3334 Tmp1 = PromoteOp(Node->getOperand(0));
3335 assert(Tmp1.getValueType() == NVT);
3336 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3337 // NOTE: we do not have to do any extra rounding here for
3338 // NoExcessFPPrecision, because we know the input will have the appropriate
3339 // precision, and these operations don't modify precision at all.
3345 Tmp1 = PromoteOp(Node->getOperand(0));
3346 assert(Tmp1.getValueType() == NVT);
3347 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3348 if (NoExcessFPPrecision)
3349 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3350 DAG.getValueType(VT));
3354 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3355 // directly as well, which may be better.
3356 Tmp1 = PromoteOp(Node->getOperand(0));
3357 assert(Tmp1.getValueType() == NVT);
3358 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3359 if (NoExcessFPPrecision)
3360 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3361 DAG.getValueType(VT));
3371 // The input may have strange things in the top bits of the registers, but
3372 // these operations don't care. They may have weird bits going out, but
3373 // that too is okay if they are integer operations.
3374 Tmp1 = PromoteOp(Node->getOperand(0));
3375 Tmp2 = PromoteOp(Node->getOperand(1));
3376 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3377 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3382 Tmp1 = PromoteOp(Node->getOperand(0));
3383 Tmp2 = PromoteOp(Node->getOperand(1));
3384 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3385 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3387 // Floating point operations will give excess precision that we may not be
3388 // able to tolerate. If we DO allow excess precision, just leave it,
3389 // otherwise excise it.
3390 // FIXME: Why would we need to round FP ops more than integer ones?
3391 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3392 if (NoExcessFPPrecision)
3393 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3394 DAG.getValueType(VT));
3399 // These operators require that their input be sign extended.
3400 Tmp1 = PromoteOp(Node->getOperand(0));
3401 Tmp2 = PromoteOp(Node->getOperand(1));
3402 if (MVT::isInteger(NVT)) {
3403 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3404 DAG.getValueType(VT));
3405 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3406 DAG.getValueType(VT));
3408 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3410 // Perform FP_ROUND: this is probably overly pessimistic.
3411 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3412 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3413 DAG.getValueType(VT));
3417 case ISD::FCOPYSIGN:
3418 // These operators require that their input be fp extended.
3419 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3421 Tmp1 = LegalizeOp(Node->getOperand(0));
3424 Tmp1 = PromoteOp(Node->getOperand(0));
3427 assert(0 && "not implemented");
3429 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3431 Tmp2 = LegalizeOp(Node->getOperand(1));
3434 Tmp2 = PromoteOp(Node->getOperand(1));
3437 assert(0 && "not implemented");
3439 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3441 // Perform FP_ROUND: this is probably overly pessimistic.
3442 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3443 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3444 DAG.getValueType(VT));
3449 // These operators require that their input be zero extended.
3450 Tmp1 = PromoteOp(Node->getOperand(0));
3451 Tmp2 = PromoteOp(Node->getOperand(1));
3452 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3453 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3454 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3455 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3459 Tmp1 = PromoteOp(Node->getOperand(0));
3460 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3463 // The input value must be properly sign extended.
3464 Tmp1 = PromoteOp(Node->getOperand(0));
3465 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3466 DAG.getValueType(VT));
3467 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3470 // The input value must be properly zero extended.
3471 Tmp1 = PromoteOp(Node->getOperand(0));
3472 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3473 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3477 Tmp1 = Node->getOperand(0); // Get the chain.
3478 Tmp2 = Node->getOperand(1); // Get the pointer.
3479 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3480 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3481 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3483 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3484 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3485 SV->getValue(), SV->getOffset());
3486 // Increment the pointer, VAList, to the next vaarg
3487 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3488 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3489 TLI.getPointerTy()));
3490 // Store the incremented VAList to the legalized pointer
3491 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3493 // Load the actual argument out of the pointer VAList
3494 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3496 // Remember that we legalized the chain.
3497 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3501 LoadSDNode *LD = cast<LoadSDNode>(Node);
3502 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3503 ? ISD::EXTLOAD : LD->getExtensionType();
3504 Result = DAG.getExtLoad(ExtType, NVT,
3505 LD->getChain(), LD->getBasePtr(),
3506 LD->getSrcValue(), LD->getSrcValueOffset(),
3508 // Remember that we legalized the chain.
3509 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3513 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3514 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3515 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3517 case ISD::SELECT_CC:
3518 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3519 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3520 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3521 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3524 Tmp1 = Node->getOperand(0);
3525 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3526 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3527 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3528 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3529 TLI.getShiftAmountTy()));
3534 // Zero extend the argument
3535 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3536 // Perform the larger operation, then subtract if needed.
3537 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3538 switch(Node->getOpcode()) {
3543 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3544 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3545 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3546 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3547 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3550 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3551 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3552 DAG.getConstant(getSizeInBits(NVT) -
3553 getSizeInBits(VT), NVT));
3557 case ISD::VEXTRACT_VECTOR_ELT:
3558 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3560 case ISD::EXTRACT_VECTOR_ELT:
3561 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3565 assert(Result.Val && "Didn't set a result!");
3567 // Make sure the result is itself legal.
3568 Result = LegalizeOp(Result);
3570 // Remember that we promoted this!
3571 AddPromotedOperand(Op, Result);
3575 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3576 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3577 /// on the vector type. The return type of this matches the element type of the
3578 /// vector, which may not be legal for the target.
3579 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3580 // We know that operand #0 is the Vec vector. If the index is a constant
3581 // or if the invec is a supported hardware type, we can use it. Otherwise,
3582 // lower to a store then an indexed load.
3583 SDOperand Vec = Op.getOperand(0);
3584 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3586 SDNode *InVal = Vec.Val;
3587 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3588 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3590 // Figure out if there is a Packed type corresponding to this Vector
3591 // type. If so, convert to the vector type.
3592 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3593 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3594 // Turn this into a packed extract_vector_elt operation.
3595 Vec = PackVectorOp(Vec, TVT);
3596 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3597 } else if (NumElems == 1) {
3598 // This must be an access of the only element. Return it.
3599 return PackVectorOp(Vec, EVT);
3600 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3602 SplitVectorOp(Vec, Lo, Hi);
3603 if (CIdx->getValue() < NumElems/2) {
3607 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3610 // It's now an extract from the appropriate high or low part. Recurse.
3611 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3612 return LowerVEXTRACT_VECTOR_ELT(Op);
3614 // Variable index case for extract element.
3615 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3616 assert(0 && "unimp!");
3621 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3623 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3624 SDOperand Vector = Op.getOperand(0);
3625 SDOperand Idx = Op.getOperand(1);
3627 // If the target doesn't support this, store the value to a temporary
3628 // stack slot, then LOAD the scalar element back out.
3629 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3630 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3632 // Add the offset to the index.
3633 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3634 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3635 DAG.getConstant(EltSize, Idx.getValueType()));
3636 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3638 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3642 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3643 /// with condition CC on the current target. This usually involves legalizing
3644 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3645 /// there may be no choice but to create a new SetCC node to represent the
3646 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3647 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3648 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3651 SDOperand Tmp1, Tmp2, Result;
3653 switch (getTypeAction(LHS.getValueType())) {
3655 Tmp1 = LegalizeOp(LHS); // LHS
3656 Tmp2 = LegalizeOp(RHS); // RHS
3659 Tmp1 = PromoteOp(LHS); // LHS
3660 Tmp2 = PromoteOp(RHS); // RHS
3662 // If this is an FP compare, the operands have already been extended.
3663 if (MVT::isInteger(LHS.getValueType())) {
3664 MVT::ValueType VT = LHS.getValueType();
3665 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3667 // Otherwise, we have to insert explicit sign or zero extends. Note
3668 // that we could insert sign extends for ALL conditions, but zero extend
3669 // is cheaper on many machines (an AND instead of two shifts), so prefer
3671 switch (cast<CondCodeSDNode>(CC)->get()) {
3672 default: assert(0 && "Unknown integer comparison!");
3679 // ALL of these operations will work if we either sign or zero extend
3680 // the operands (including the unsigned comparisons!). Zero extend is
3681 // usually a simpler/cheaper operation, so prefer it.
3682 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3683 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3689 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3690 DAG.getValueType(VT));
3691 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3692 DAG.getValueType(VT));
3698 MVT::ValueType VT = LHS.getValueType();
3699 if (VT == MVT::f32 || VT == MVT::f64) {
3700 // Expand into one or more soft-fp libcall(s).
3701 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3702 switch (cast<CondCodeSDNode>(CC)->get()) {
3705 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3709 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3713 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3717 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3721 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3725 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3728 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3731 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3734 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3735 switch (cast<CondCodeSDNode>(CC)->get()) {
3737 // SETONE = SETOLT | SETOGT
3738 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3741 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3744 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3747 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3750 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3753 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3755 default: assert(0 && "Unsupported FP setcc!");
3760 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3761 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3762 false /*sign irrelevant*/, Dummy);
3763 Tmp2 = DAG.getConstant(0, MVT::i32);
3764 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
3765 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3766 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3767 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3768 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3769 false /*sign irrelevant*/, Dummy);
3770 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3771 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
3772 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3780 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3781 ExpandOp(LHS, LHSLo, LHSHi);
3782 ExpandOp(RHS, RHSLo, RHSHi);
3783 switch (cast<CondCodeSDNode>(CC)->get()) {
3787 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3788 if (RHSCST->isAllOnesValue()) {
3789 // Comparison to -1.
3790 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3795 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3796 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3797 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3798 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3801 // If this is a comparison of the sign bit, just look at the top part.
3803 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3804 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3805 CST->getValue() == 0) || // X < 0
3806 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3807 CST->isAllOnesValue())) { // X > -1
3813 // FIXME: This generated code sucks.
3814 ISD::CondCode LowCC;
3815 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
3817 default: assert(0 && "Unknown integer setcc!");
3819 case ISD::SETULT: LowCC = ISD::SETULT; break;
3821 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3823 case ISD::SETULE: LowCC = ISD::SETULE; break;
3825 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3828 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3829 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3830 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3832 // NOTE: on targets without efficient SELECT of bools, we can always use
3833 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3834 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
3835 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
3836 false, DagCombineInfo);
3838 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3839 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3840 CCCode, false, DagCombineInfo);
3842 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3844 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
3845 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
3846 if ((Tmp1C && Tmp1C->getValue() == 0) ||
3847 (Tmp2C && Tmp2C->getValue() == 0 &&
3848 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3849 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
3850 (Tmp2C && Tmp2C->getValue() == 1 &&
3851 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
3852 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
3853 // low part is known false, returns high part.
3854 // For LE / GE, if high part is known false, ignore the low part.
3855 // For LT / GT, if high part is known true, ignore the low part.
3859 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3860 ISD::SETEQ, false, DagCombineInfo);
3862 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3863 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3864 Result, Tmp1, Tmp2));
3875 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3876 /// The resultant code need not be legal. Note that SrcOp is the input operand
3877 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3878 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3880 // Create the stack frame object.
3881 SDOperand FIPtr = CreateStackTemporary(DestVT);
3883 // Emit a store to the stack slot.
3884 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3885 // Result is a load from the stack slot.
3886 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3889 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3890 // Create a vector sized/aligned stack slot, store the value to element #0,
3891 // then load the whole vector back out.
3892 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3893 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3895 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3899 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3900 /// support the operation, but do support the resultant packed vector type.
3901 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3903 // If the only non-undef value is the low element, turn this into a
3904 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3905 unsigned NumElems = Node->getNumOperands();
3906 bool isOnlyLowElement = true;
3907 SDOperand SplatValue = Node->getOperand(0);
3908 std::map<SDOperand, std::vector<unsigned> > Values;
3909 Values[SplatValue].push_back(0);
3910 bool isConstant = true;
3911 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3912 SplatValue.getOpcode() != ISD::UNDEF)
3915 for (unsigned i = 1; i < NumElems; ++i) {
3916 SDOperand V = Node->getOperand(i);
3917 Values[V].push_back(i);
3918 if (V.getOpcode() != ISD::UNDEF)
3919 isOnlyLowElement = false;
3920 if (SplatValue != V)
3921 SplatValue = SDOperand(0,0);
3923 // If this isn't a constant element or an undef, we can't use a constant
3925 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3926 V.getOpcode() != ISD::UNDEF)
3930 if (isOnlyLowElement) {
3931 // If the low element is an undef too, then this whole things is an undef.
3932 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3933 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3934 // Otherwise, turn this into a scalar_to_vector node.
3935 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3936 Node->getOperand(0));
3939 // If all elements are constants, create a load from the constant pool.
3941 MVT::ValueType VT = Node->getValueType(0);
3943 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3944 std::vector<Constant*> CV;
3945 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3946 if (ConstantFPSDNode *V =
3947 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3948 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3949 } else if (ConstantSDNode *V =
3950 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3951 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3953 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3954 CV.push_back(UndefValue::get(OpNTy));
3957 Constant *CP = ConstantVector::get(CV);
3958 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3959 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3962 if (SplatValue.Val) { // Splat of one value?
3963 // Build the shuffle constant vector: <0, 0, 0, 0>
3964 MVT::ValueType MaskVT =
3965 MVT::getIntVectorWithNumElements(NumElems);
3966 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3967 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3968 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3969 &ZeroVec[0], ZeroVec.size());
3971 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3972 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3973 // Get the splatted value into the low element of a vector register.
3974 SDOperand LowValVec =
3975 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3977 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3978 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3979 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3984 // If there are only two unique elements, we may be able to turn this into a
3986 if (Values.size() == 2) {
3987 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3988 MVT::ValueType MaskVT =
3989 MVT::getIntVectorWithNumElements(NumElems);
3990 std::vector<SDOperand> MaskVec(NumElems);
3992 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3993 E = Values.end(); I != E; ++I) {
3994 for (std::vector<unsigned>::iterator II = I->second.begin(),
3995 EE = I->second.end(); II != EE; ++II)
3996 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3999 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4000 &MaskVec[0], MaskVec.size());
4002 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4003 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4004 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4005 SmallVector<SDOperand, 8> Ops;
4006 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4007 E = Values.end(); I != E; ++I) {
4008 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4012 Ops.push_back(ShuffleMask);
4014 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4015 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4016 &Ops[0], Ops.size());
4020 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4021 // aligned object on the stack, store each element into it, then load
4022 // the result as a vector.
4023 MVT::ValueType VT = Node->getValueType(0);
4024 // Create the stack frame object.
4025 SDOperand FIPtr = CreateStackTemporary(VT);
4027 // Emit a store of each element to the stack slot.
4028 SmallVector<SDOperand, 8> Stores;
4029 unsigned TypeByteSize =
4030 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4031 // Store (in the right endianness) the elements to memory.
4032 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4033 // Ignore undef elements.
4034 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4036 unsigned Offset = TypeByteSize*i;
4038 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4039 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4041 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4045 SDOperand StoreChain;
4046 if (!Stores.empty()) // Not all undef elements?
4047 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4048 &Stores[0], Stores.size());
4050 StoreChain = DAG.getEntryNode();
4052 // Result is a load from the stack slot.
4053 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4056 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4057 /// specified value type.
4058 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4059 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4060 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4061 const Type *Ty = MVT::getTypeForValueType(VT);
4062 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4063 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4064 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4067 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4068 SDOperand Op, SDOperand Amt,
4069 SDOperand &Lo, SDOperand &Hi) {
4070 // Expand the subcomponents.
4071 SDOperand LHSL, LHSH;
4072 ExpandOp(Op, LHSL, LHSH);
4074 SDOperand Ops[] = { LHSL, LHSH, Amt };
4075 MVT::ValueType VT = LHSL.getValueType();
4076 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4077 Hi = Lo.getValue(1);
4081 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4082 /// smaller elements. If we can't find a way that is more efficient than a
4083 /// libcall on this target, return false. Otherwise, return true with the
4084 /// low-parts expanded into Lo and Hi.
4085 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4086 SDOperand &Lo, SDOperand &Hi) {
4087 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4088 "This is not a shift!");
4090 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4091 SDOperand ShAmt = LegalizeOp(Amt);
4092 MVT::ValueType ShTy = ShAmt.getValueType();
4093 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4094 unsigned NVTBits = MVT::getSizeInBits(NVT);
4096 // Handle the case when Amt is an immediate. Other cases are currently broken
4097 // and are disabled.
4098 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4099 unsigned Cst = CN->getValue();
4100 // Expand the incoming operand to be shifted, so that we have its parts
4102 ExpandOp(Op, InL, InH);
4106 Lo = DAG.getConstant(0, NVT);
4107 Hi = DAG.getConstant(0, NVT);
4108 } else if (Cst > NVTBits) {
4109 Lo = DAG.getConstant(0, NVT);
4110 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4111 } else if (Cst == NVTBits) {
4112 Lo = DAG.getConstant(0, NVT);
4115 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4116 Hi = DAG.getNode(ISD::OR, NVT,
4117 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4118 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4123 Lo = DAG.getConstant(0, NVT);
4124 Hi = DAG.getConstant(0, NVT);
4125 } else if (Cst > NVTBits) {
4126 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4127 Hi = DAG.getConstant(0, NVT);
4128 } else if (Cst == NVTBits) {
4130 Hi = DAG.getConstant(0, NVT);
4132 Lo = DAG.getNode(ISD::OR, NVT,
4133 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4134 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4135 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4140 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4141 DAG.getConstant(NVTBits-1, ShTy));
4142 } else if (Cst > NVTBits) {
4143 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4144 DAG.getConstant(Cst-NVTBits, ShTy));
4145 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4146 DAG.getConstant(NVTBits-1, ShTy));
4147 } else if (Cst == NVTBits) {
4149 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4150 DAG.getConstant(NVTBits-1, ShTy));
4152 Lo = DAG.getNode(ISD::OR, NVT,
4153 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4154 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4155 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4161 // Okay, the shift amount isn't constant. However, if we can tell that it is
4162 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4163 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4164 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4166 // If we know that the high bit of the shift amount is one, then we can do
4167 // this as a couple of simple shifts.
4168 if (KnownOne & Mask) {
4169 // Mask out the high bit, which we know is set.
4170 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4171 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4173 // Expand the incoming operand to be shifted, so that we have its parts
4175 ExpandOp(Op, InL, InH);
4178 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4179 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4182 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4183 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4186 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4187 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4188 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4193 // If we know that the high bit of the shift amount is zero, then we can do
4194 // this as a couple of simple shifts.
4195 if (KnownZero & Mask) {
4197 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4198 DAG.getConstant(NVTBits, Amt.getValueType()),
4201 // Expand the incoming operand to be shifted, so that we have its parts
4203 ExpandOp(Op, InL, InH);
4206 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4207 Hi = DAG.getNode(ISD::OR, NVT,
4208 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4209 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4212 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4213 Lo = DAG.getNode(ISD::OR, NVT,
4214 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4215 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4218 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4219 Lo = DAG.getNode(ISD::OR, NVT,
4220 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4221 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4230 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4231 // does not fit into a register, return the lo part and set the hi part to the
4232 // by-reg argument. If it does fit into a single register, return the result
4233 // and leave the Hi part unset.
4234 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4235 bool isSigned, SDOperand &Hi) {
4236 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4237 // The input chain to this libcall is the entry node of the function.
4238 // Legalizing the call will automatically add the previous call to the
4240 SDOperand InChain = DAG.getEntryNode();
4242 TargetLowering::ArgListTy Args;
4243 TargetLowering::ArgListEntry Entry;
4244 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4245 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4246 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4247 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4248 Entry.isSExt = isSigned;
4249 Args.push_back(Entry);
4251 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4253 // Splice the libcall in wherever FindInputOutputChains tells us to.
4254 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4255 std::pair<SDOperand,SDOperand> CallInfo =
4256 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4259 // Legalize the call sequence, starting with the chain. This will advance
4260 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4261 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4262 LegalizeOp(CallInfo.second);
4264 switch (getTypeAction(CallInfo.first.getValueType())) {
4265 default: assert(0 && "Unknown thing");
4267 Result = CallInfo.first;
4270 ExpandOp(CallInfo.first, Result, Hi);
4277 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4279 SDOperand SelectionDAGLegalize::
4280 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4281 assert(getTypeAction(Source.getValueType()) == Expand &&
4282 "This is not an expansion!");
4283 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4286 assert(Source.getValueType() == MVT::i64 &&
4287 "This only works for 64-bit -> FP");
4288 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4289 // incoming integer is set. To handle this, we dynamically test to see if
4290 // it is set, and, if so, add a fudge factor.
4292 ExpandOp(Source, Lo, Hi);
4294 // If this is unsigned, and not supported, first perform the conversion to
4295 // signed, then adjust the result if the sign bit is set.
4296 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4297 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4299 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4300 DAG.getConstant(0, Hi.getValueType()),
4302 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4303 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4304 SignSet, Four, Zero);
4305 uint64_t FF = 0x5f800000ULL;
4306 if (TLI.isLittleEndian()) FF <<= 32;
4307 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4309 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4310 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4311 SDOperand FudgeInReg;
4312 if (DestTy == MVT::f32)
4313 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4315 assert(DestTy == MVT::f64 && "Unexpected conversion");
4316 // FIXME: Avoid the extend by construction the right constantpool?
4317 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4318 CPIdx, NULL, 0, MVT::f32);
4320 MVT::ValueType SCVT = SignedConv.getValueType();
4321 if (SCVT != DestTy) {
4322 // Destination type needs to be expanded as well. The FADD now we are
4323 // constructing will be expanded into a libcall.
4324 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4325 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4326 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4327 SignedConv, SignedConv.getValue(1));
4329 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4331 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4334 // Check to see if the target has a custom way to lower this. If so, use it.
4335 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4336 default: assert(0 && "This action not implemented for this operation!");
4337 case TargetLowering::Legal:
4338 case TargetLowering::Expand:
4339 break; // This case is handled below.
4340 case TargetLowering::Custom: {
4341 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4344 return LegalizeOp(NV);
4345 break; // The target decided this was legal after all
4349 // Expand the source, then glue it back together for the call. We must expand
4350 // the source in case it is shared (this pass of legalize must traverse it).
4351 SDOperand SrcLo, SrcHi;
4352 ExpandOp(Source, SrcLo, SrcHi);
4353 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4356 if (DestTy == MVT::f32)
4357 LC = RTLIB::SINTTOFP_I64_F32;
4359 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4360 LC = RTLIB::SINTTOFP_I64_F64;
4363 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4364 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4365 SDOperand UnusedHiPart;
4366 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4370 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4371 /// INT_TO_FP operation of the specified operand when the target requests that
4372 /// we expand it. At this point, we know that the result and operand types are
4373 /// legal for the target.
4374 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4376 MVT::ValueType DestVT) {
4377 if (Op0.getValueType() == MVT::i32) {
4378 // simple 32-bit [signed|unsigned] integer to float/double expansion
4380 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4381 MachineFunction &MF = DAG.getMachineFunction();
4382 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4383 unsigned StackAlign =
4384 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4385 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4386 // get address of 8 byte buffer
4387 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4388 // word offset constant for Hi/Lo address computation
4389 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4390 // set up Hi and Lo (into buffer) address based on endian
4391 SDOperand Hi = StackSlot;
4392 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4393 if (TLI.isLittleEndian())
4396 // if signed map to unsigned space
4397 SDOperand Op0Mapped;
4399 // constant used to invert sign bit (signed to unsigned mapping)
4400 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4401 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4405 // store the lo of the constructed double - based on integer input
4406 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4407 Op0Mapped, Lo, NULL, 0);
4408 // initial hi portion of constructed double
4409 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4410 // store the hi of the constructed double - biased exponent
4411 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4412 // load the constructed double
4413 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4414 // FP constant to bias correct the final result
4415 SDOperand Bias = DAG.getConstantFP(isSigned ?
4416 BitsToDouble(0x4330000080000000ULL)
4417 : BitsToDouble(0x4330000000000000ULL),
4419 // subtract the bias
4420 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4423 // handle final rounding
4424 if (DestVT == MVT::f64) {
4428 // if f32 then cast to f32
4429 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4433 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4434 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4436 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4437 DAG.getConstant(0, Op0.getValueType()),
4439 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4440 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4441 SignSet, Four, Zero);
4443 // If the sign bit of the integer is set, the large number will be treated
4444 // as a negative number. To counteract this, the dynamic code adds an
4445 // offset depending on the data type.
4447 switch (Op0.getValueType()) {
4448 default: assert(0 && "Unsupported integer type!");
4449 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4450 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4451 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4452 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4454 if (TLI.isLittleEndian()) FF <<= 32;
4455 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4457 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4458 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4459 SDOperand FudgeInReg;
4460 if (DestVT == MVT::f32)
4461 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4463 assert(DestVT == MVT::f64 && "Unexpected conversion");
4464 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4465 DAG.getEntryNode(), CPIdx,
4466 NULL, 0, MVT::f32));
4469 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4472 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4473 /// *INT_TO_FP operation of the specified operand when the target requests that
4474 /// we promote it. At this point, we know that the result and operand types are
4475 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4476 /// operation that takes a larger input.
4477 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4478 MVT::ValueType DestVT,
4480 // First step, figure out the appropriate *INT_TO_FP operation to use.
4481 MVT::ValueType NewInTy = LegalOp.getValueType();
4483 unsigned OpToUse = 0;
4485 // Scan for the appropriate larger type to use.
4487 NewInTy = (MVT::ValueType)(NewInTy+1);
4488 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4490 // If the target supports SINT_TO_FP of this type, use it.
4491 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4493 case TargetLowering::Legal:
4494 if (!TLI.isTypeLegal(NewInTy))
4495 break; // Can't use this datatype.
4497 case TargetLowering::Custom:
4498 OpToUse = ISD::SINT_TO_FP;
4502 if (isSigned) continue;
4504 // If the target supports UINT_TO_FP of this type, use it.
4505 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4507 case TargetLowering::Legal:
4508 if (!TLI.isTypeLegal(NewInTy))
4509 break; // Can't use this datatype.
4511 case TargetLowering::Custom:
4512 OpToUse = ISD::UINT_TO_FP;
4517 // Otherwise, try a larger type.
4520 // Okay, we found the operation and type to use. Zero extend our input to the
4521 // desired type then run the operation on it.
4522 return DAG.getNode(OpToUse, DestVT,
4523 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4527 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4528 /// FP_TO_*INT operation of the specified operand when the target requests that
4529 /// we promote it. At this point, we know that the result and operand types are
4530 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4531 /// operation that returns a larger result.
4532 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4533 MVT::ValueType DestVT,
4535 // First step, figure out the appropriate FP_TO*INT operation to use.
4536 MVT::ValueType NewOutTy = DestVT;
4538 unsigned OpToUse = 0;
4540 // Scan for the appropriate larger type to use.
4542 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4543 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4545 // If the target supports FP_TO_SINT returning this type, use it.
4546 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4548 case TargetLowering::Legal:
4549 if (!TLI.isTypeLegal(NewOutTy))
4550 break; // Can't use this datatype.
4552 case TargetLowering::Custom:
4553 OpToUse = ISD::FP_TO_SINT;
4558 // If the target supports FP_TO_UINT of this type, use it.
4559 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4561 case TargetLowering::Legal:
4562 if (!TLI.isTypeLegal(NewOutTy))
4563 break; // Can't use this datatype.
4565 case TargetLowering::Custom:
4566 OpToUse = ISD::FP_TO_UINT;
4571 // Otherwise, try a larger type.
4574 // Okay, we found the operation and type to use. Truncate the result of the
4575 // extended FP_TO_*INT operation to the desired size.
4576 return DAG.getNode(ISD::TRUNCATE, DestVT,
4577 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4580 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4582 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4583 MVT::ValueType VT = Op.getValueType();
4584 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4585 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4587 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4589 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4590 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4591 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4593 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4594 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4595 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4596 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4597 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4598 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4599 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4600 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4601 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4603 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4604 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4605 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4606 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4607 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4608 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4609 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4610 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4611 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4612 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4613 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4614 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4615 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4616 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4617 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4618 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4619 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4620 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4621 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4622 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4623 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4627 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4629 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4631 default: assert(0 && "Cannot expand this yet!");
4633 static const uint64_t mask[6] = {
4634 0x5555555555555555ULL, 0x3333333333333333ULL,
4635 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4636 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4638 MVT::ValueType VT = Op.getValueType();
4639 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4640 unsigned len = getSizeInBits(VT);
4641 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4642 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4643 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4644 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4645 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4646 DAG.getNode(ISD::AND, VT,
4647 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4652 // for now, we do this:
4653 // x = x | (x >> 1);
4654 // x = x | (x >> 2);
4656 // x = x | (x >>16);
4657 // x = x | (x >>32); // for 64-bit input
4658 // return popcount(~x);
4660 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4661 MVT::ValueType VT = Op.getValueType();
4662 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4663 unsigned len = getSizeInBits(VT);
4664 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4665 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4666 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4668 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4669 return DAG.getNode(ISD::CTPOP, VT, Op);
4672 // for now, we use: { return popcount(~x & (x - 1)); }
4673 // unless the target has ctlz but not ctpop, in which case we use:
4674 // { return 32 - nlz(~x & (x-1)); }
4675 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4676 MVT::ValueType VT = Op.getValueType();
4677 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4678 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4679 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4680 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4681 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4682 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4683 TLI.isOperationLegal(ISD::CTLZ, VT))
4684 return DAG.getNode(ISD::SUB, VT,
4685 DAG.getConstant(getSizeInBits(VT), VT),
4686 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4687 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4692 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4693 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4694 /// LegalizeNodes map is filled in for any results that are not expanded, the
4695 /// ExpandedNodes map is filled in for any results that are expanded, and the
4696 /// Lo/Hi values are returned.
4697 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4698 MVT::ValueType VT = Op.getValueType();
4699 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4700 SDNode *Node = Op.Val;
4701 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4702 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4703 VT == MVT::Vector) &&
4704 "Cannot expand to FP value or to larger int value!");
4706 // See if we already expanded it.
4707 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4708 = ExpandedNodes.find(Op);
4709 if (I != ExpandedNodes.end()) {
4710 Lo = I->second.first;
4711 Hi = I->second.second;
4715 switch (Node->getOpcode()) {
4716 case ISD::CopyFromReg:
4717 assert(0 && "CopyFromReg must be legal!");
4720 cerr << "NODE: "; Node->dump(); cerr << "\n";
4722 assert(0 && "Do not know how to expand this operator!");
4725 NVT = TLI.getTypeToExpandTo(VT);
4726 Lo = DAG.getNode(ISD::UNDEF, NVT);
4727 Hi = DAG.getNode(ISD::UNDEF, NVT);
4729 case ISD::Constant: {
4730 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4731 Lo = DAG.getConstant(Cst, NVT);
4732 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4735 case ISD::ConstantFP: {
4736 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4737 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4738 if (getTypeAction(Lo.getValueType()) == Expand)
4739 ExpandOp(Lo, Lo, Hi);
4742 case ISD::BUILD_PAIR:
4743 // Return the operands.
4744 Lo = Node->getOperand(0);
4745 Hi = Node->getOperand(1);
4748 case ISD::SIGN_EXTEND_INREG:
4749 ExpandOp(Node->getOperand(0), Lo, Hi);
4750 // sext_inreg the low part if needed.
4751 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4753 // The high part gets the sign extension from the lo-part. This handles
4754 // things like sextinreg V:i64 from i8.
4755 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4756 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4757 TLI.getShiftAmountTy()));
4761 ExpandOp(Node->getOperand(0), Lo, Hi);
4762 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4763 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4769 ExpandOp(Node->getOperand(0), Lo, Hi);
4770 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4771 DAG.getNode(ISD::CTPOP, NVT, Lo),
4772 DAG.getNode(ISD::CTPOP, NVT, Hi));
4773 Hi = DAG.getConstant(0, NVT);
4777 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4778 ExpandOp(Node->getOperand(0), Lo, Hi);
4779 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4780 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4781 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4783 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4784 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4786 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4787 Hi = DAG.getConstant(0, NVT);
4792 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4793 ExpandOp(Node->getOperand(0), Lo, Hi);
4794 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4795 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4796 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4798 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4799 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4801 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4802 Hi = DAG.getConstant(0, NVT);
4807 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4808 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4809 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4810 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4812 // Remember that we legalized the chain.
4813 Hi = LegalizeOp(Hi);
4814 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4815 if (!TLI.isLittleEndian())
4821 LoadSDNode *LD = cast<LoadSDNode>(Node);
4822 SDOperand Ch = LD->getChain(); // Legalize the chain.
4823 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4824 ISD::LoadExtType ExtType = LD->getExtensionType();
4826 if (ExtType == ISD::NON_EXTLOAD) {
4827 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset());
4828 if (VT == MVT::f32 || VT == MVT::f64) {
4829 // f32->i32 or f64->i64 one to one expansion.
4830 // Remember that we legalized the chain.
4831 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4832 // Recursively expand the new load.
4833 if (getTypeAction(NVT) == Expand)
4834 ExpandOp(Lo, Lo, Hi);
4838 // Increment the pointer to the other half.
4839 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4840 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4841 getIntPtrConstant(IncrementSize));
4842 // FIXME: This creates a bogus srcvalue!
4843 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset());
4845 // Build a factor node to remember that this load is independent of the
4847 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4850 // Remember that we legalized the chain.
4851 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4852 if (!TLI.isLittleEndian())
4855 MVT::ValueType EVT = LD->getLoadedVT();
4857 if (VT == MVT::f64 && EVT == MVT::f32) {
4858 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4859 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4860 LD->getSrcValueOffset());
4861 // Remember that we legalized the chain.
4862 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4863 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4868 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4869 LD->getSrcValueOffset());
4871 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4872 LD->getSrcValueOffset(), EVT);
4874 // Remember that we legalized the chain.
4875 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4877 if (ExtType == ISD::SEXTLOAD) {
4878 // The high part is obtained by SRA'ing all but one of the bits of the
4880 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4881 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4882 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4883 } else if (ExtType == ISD::ZEXTLOAD) {
4884 // The high part is just a zero.
4885 Hi = DAG.getConstant(0, NVT);
4886 } else /* if (ExtType == ISD::EXTLOAD) */ {
4887 // The high part is undefined.
4888 Hi = DAG.getNode(ISD::UNDEF, NVT);
4895 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4896 SDOperand LL, LH, RL, RH;
4897 ExpandOp(Node->getOperand(0), LL, LH);
4898 ExpandOp(Node->getOperand(1), RL, RH);
4899 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4900 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4904 SDOperand LL, LH, RL, RH;
4905 ExpandOp(Node->getOperand(1), LL, LH);
4906 ExpandOp(Node->getOperand(2), RL, RH);
4907 if (getTypeAction(NVT) == Expand)
4908 NVT = TLI.getTypeToExpandTo(NVT);
4909 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4911 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4914 case ISD::SELECT_CC: {
4915 SDOperand TL, TH, FL, FH;
4916 ExpandOp(Node->getOperand(2), TL, TH);
4917 ExpandOp(Node->getOperand(3), FL, FH);
4918 if (getTypeAction(NVT) == Expand)
4919 NVT = TLI.getTypeToExpandTo(NVT);
4920 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4921 Node->getOperand(1), TL, FL, Node->getOperand(4));
4923 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4924 Node->getOperand(1), TH, FH, Node->getOperand(4));
4927 case ISD::ANY_EXTEND:
4928 // The low part is any extension of the input (which degenerates to a copy).
4929 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4930 // The high part is undefined.
4931 Hi = DAG.getNode(ISD::UNDEF, NVT);
4933 case ISD::SIGN_EXTEND: {
4934 // The low part is just a sign extension of the input (which degenerates to
4936 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4938 // The high part is obtained by SRA'ing all but one of the bits of the lo
4940 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4941 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4942 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4945 case ISD::ZERO_EXTEND:
4946 // The low part is just a zero extension of the input (which degenerates to
4948 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4950 // The high part is just a zero.
4951 Hi = DAG.getConstant(0, NVT);
4954 case ISD::TRUNCATE: {
4955 // The input value must be larger than this value. Expand *it*.
4957 ExpandOp(Node->getOperand(0), NewLo, Hi);
4959 // The low part is now either the right size, or it is closer. If not the
4960 // right size, make an illegal truncate so we recursively expand it.
4961 if (NewLo.getValueType() != Node->getValueType(0))
4962 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
4963 ExpandOp(NewLo, Lo, Hi);
4967 case ISD::BIT_CONVERT: {
4969 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4970 // If the target wants to, allow it to lower this itself.
4971 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4972 case Expand: assert(0 && "cannot expand FP!");
4973 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4974 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4976 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4979 // f32 / f64 must be expanded to i32 / i64.
4980 if (VT == MVT::f32 || VT == MVT::f64) {
4981 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4982 if (getTypeAction(NVT) == Expand)
4983 ExpandOp(Lo, Lo, Hi);
4987 // If source operand will be expanded to the same type as VT, i.e.
4988 // i64 <- f64, i32 <- f32, expand the source operand instead.
4989 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
4990 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
4991 ExpandOp(Node->getOperand(0), Lo, Hi);
4995 // Turn this into a load/store pair by default.
4997 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
4999 ExpandOp(Tmp, Lo, Hi);
5003 case ISD::READCYCLECOUNTER:
5004 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5005 TargetLowering::Custom &&
5006 "Must custom expand ReadCycleCounter");
5007 Lo = TLI.LowerOperation(Op, DAG);
5008 assert(Lo.Val && "Node must be custom expanded!");
5009 Hi = Lo.getValue(1);
5010 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5011 LegalizeOp(Lo.getValue(2)));
5014 // These operators cannot be expanded directly, emit them as calls to
5015 // library functions.
5016 case ISD::FP_TO_SINT: {
5017 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5019 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5020 case Expand: assert(0 && "cannot expand FP!");
5021 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5022 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5025 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5027 // Now that the custom expander is done, expand the result, which is still
5030 ExpandOp(Op, Lo, Hi);
5036 if (Node->getOperand(0).getValueType() == MVT::f32)
5037 LC = RTLIB::FPTOSINT_F32_I64;
5039 LC = RTLIB::FPTOSINT_F64_I64;
5040 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5041 false/*sign irrelevant*/, Hi);
5045 case ISD::FP_TO_UINT: {
5046 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5048 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5049 case Expand: assert(0 && "cannot expand FP!");
5050 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5051 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5054 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5056 // Now that the custom expander is done, expand the result.
5058 ExpandOp(Op, Lo, Hi);
5064 if (Node->getOperand(0).getValueType() == MVT::f32)
5065 LC = RTLIB::FPTOUINT_F32_I64;
5067 LC = RTLIB::FPTOUINT_F64_I64;
5068 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5069 false/*sign irrelevant*/, Hi);
5074 // If the target wants custom lowering, do so.
5075 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5076 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5077 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5078 Op = TLI.LowerOperation(Op, DAG);
5080 // Now that the custom expander is done, expand the result, which is
5082 ExpandOp(Op, Lo, Hi);
5087 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5088 // this X << 1 as X+X.
5089 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5090 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5091 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5092 SDOperand LoOps[2], HiOps[3];
5093 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5094 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5095 LoOps[1] = LoOps[0];
5096 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5098 HiOps[1] = HiOps[0];
5099 HiOps[2] = Lo.getValue(1);
5100 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5105 // If we can emit an efficient shift operation, do so now.
5106 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5109 // If this target supports SHL_PARTS, use it.
5110 TargetLowering::LegalizeAction Action =
5111 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5112 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5113 Action == TargetLowering::Custom) {
5114 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5118 // Otherwise, emit a libcall.
5119 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5120 false/*left shift=unsigned*/, Hi);
5125 // If the target wants custom lowering, do so.
5126 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5127 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5128 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5129 Op = TLI.LowerOperation(Op, DAG);
5131 // Now that the custom expander is done, expand the result, which is
5133 ExpandOp(Op, Lo, Hi);
5138 // If we can emit an efficient shift operation, do so now.
5139 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5142 // If this target supports SRA_PARTS, use it.
5143 TargetLowering::LegalizeAction Action =
5144 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5145 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5146 Action == TargetLowering::Custom) {
5147 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5151 // Otherwise, emit a libcall.
5152 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5153 true/*ashr is signed*/, Hi);
5158 // If the target wants custom lowering, do so.
5159 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5160 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5161 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5162 Op = TLI.LowerOperation(Op, DAG);
5164 // Now that the custom expander is done, expand the result, which is
5166 ExpandOp(Op, Lo, Hi);
5171 // If we can emit an efficient shift operation, do so now.
5172 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5175 // If this target supports SRL_PARTS, use it.
5176 TargetLowering::LegalizeAction Action =
5177 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5178 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5179 Action == TargetLowering::Custom) {
5180 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5184 // Otherwise, emit a libcall.
5185 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5186 false/*lshr is unsigned*/, Hi);
5192 // If the target wants to custom expand this, let them.
5193 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5194 TargetLowering::Custom) {
5195 Op = TLI.LowerOperation(Op, DAG);
5197 ExpandOp(Op, Lo, Hi);
5202 // Expand the subcomponents.
5203 SDOperand LHSL, LHSH, RHSL, RHSH;
5204 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5205 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5206 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5207 SDOperand LoOps[2], HiOps[3];
5212 if (Node->getOpcode() == ISD::ADD) {
5213 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5214 HiOps[2] = Lo.getValue(1);
5215 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5217 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5218 HiOps[2] = Lo.getValue(1);
5219 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5224 // If the target wants to custom expand this, let them.
5225 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5226 SDOperand New = TLI.LowerOperation(Op, DAG);
5228 ExpandOp(New, Lo, Hi);
5233 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5234 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5235 if (HasMULHS || HasMULHU) {
5236 SDOperand LL, LH, RL, RH;
5237 ExpandOp(Node->getOperand(0), LL, LH);
5238 ExpandOp(Node->getOperand(1), RL, RH);
5239 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5240 // FIXME: Move this to the dag combiner.
5241 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5242 // extended the sign bit of the low half through the upper half, and if so
5243 // emit a MULHS instead of the alternate sequence that is valid for any
5244 // i64 x i64 multiply.
5246 // is RH an extension of the sign bit of RL?
5247 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5248 RH.getOperand(1).getOpcode() == ISD::Constant &&
5249 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5250 // is LH an extension of the sign bit of LL?
5251 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5252 LH.getOperand(1).getOpcode() == ISD::Constant &&
5253 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5255 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5257 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5259 } else if (HasMULHU) {
5261 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5264 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5265 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5266 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5267 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5268 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5273 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5274 false/*sign irrelevant*/, Hi);
5278 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5281 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5284 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5287 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5291 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5292 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5296 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5297 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5301 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5302 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5306 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5307 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5310 case ISD::FP_EXTEND:
5311 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5314 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5319 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5320 switch(Node->getOpcode()) {
5322 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5325 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5328 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5330 default: assert(0 && "Unreachable!");
5332 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5336 SDOperand Mask = (VT == MVT::f64)
5337 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5338 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5339 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5340 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5341 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5342 if (getTypeAction(NVT) == Expand)
5343 ExpandOp(Lo, Lo, Hi);
5347 SDOperand Mask = (VT == MVT::f64)
5348 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5349 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5350 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5351 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5352 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5353 if (getTypeAction(NVT) == Expand)
5354 ExpandOp(Lo, Lo, Hi);
5357 case ISD::FCOPYSIGN: {
5358 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5359 if (getTypeAction(NVT) == Expand)
5360 ExpandOp(Lo, Lo, Hi);
5363 case ISD::SINT_TO_FP:
5364 case ISD::UINT_TO_FP: {
5365 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5366 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5368 if (Node->getOperand(0).getValueType() == MVT::i64) {
5370 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5372 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5375 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5377 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5380 // Promote the operand if needed.
5381 if (getTypeAction(SrcVT) == Promote) {
5382 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5384 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5385 DAG.getValueType(SrcVT))
5386 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5387 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5390 const char *LibCall = TLI.getLibcallName(LC);
5392 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5394 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5395 Node->getOperand(0));
5396 if (getTypeAction(Lo.getValueType()) == Expand)
5397 ExpandOp(Lo, Lo, Hi);
5403 // Make sure the resultant values have been legalized themselves, unless this
5404 // is a type that requires multi-step expansion.
5405 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5406 Lo = LegalizeOp(Lo);
5408 // Don't legalize the high part if it is expanded to a single node.
5409 Hi = LegalizeOp(Hi);
5412 // Remember in a map if the values will be reused later.
5413 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5414 assert(isNew && "Value already expanded?!?");
5417 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
5418 /// two smaller values of MVT::Vector type.
5419 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5421 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
5422 SDNode *Node = Op.Val;
5423 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
5424 assert(NumElements > 1 && "Cannot split a single element vector!");
5425 unsigned NewNumElts = NumElements/2;
5426 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
5427 SDOperand TypeNode = *(Node->op_end()-1);
5429 // See if we already split it.
5430 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5431 = SplitNodes.find(Op);
5432 if (I != SplitNodes.end()) {
5433 Lo = I->second.first;
5434 Hi = I->second.second;
5438 switch (Node->getOpcode()) {
5443 assert(0 && "Unhandled operation in SplitVectorOp!");
5444 case ISD::VBUILD_VECTOR: {
5445 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5446 Node->op_begin()+NewNumElts);
5447 LoOps.push_back(NewNumEltsNode);
5448 LoOps.push_back(TypeNode);
5449 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
5451 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5453 HiOps.push_back(NewNumEltsNode);
5454 HiOps.push_back(TypeNode);
5455 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
5466 SDOperand LL, LH, RL, RH;
5467 SplitVectorOp(Node->getOperand(0), LL, LH);
5468 SplitVectorOp(Node->getOperand(1), RL, RH);
5470 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
5471 NewNumEltsNode, TypeNode);
5472 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
5473 NewNumEltsNode, TypeNode);
5477 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5478 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5479 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5481 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5482 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
5483 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5484 getIntPtrConstant(IncrementSize));
5485 // FIXME: This creates a bogus srcvalue!
5486 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5488 // Build a factor node to remember that this load is independent of the
5490 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5493 // Remember that we legalized the chain.
5494 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5497 case ISD::VBIT_CONVERT: {
5498 // We know the result is a vector. The input may be either a vector or a
5500 if (Op.getOperand(0).getValueType() != MVT::Vector) {
5501 // Lower to a store/load. FIXME: this could be improved probably.
5502 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
5504 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5505 Op.getOperand(0), Ptr, NULL, 0);
5506 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5507 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
5508 SplitVectorOp(St, Lo, Hi);
5510 // If the input is a vector type, we have to either scalarize it, pack it
5511 // or convert it based on whether the input vector type is legal.
5512 SDNode *InVal = Node->getOperand(0).Val;
5514 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5515 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5517 // If the input is from a single element vector, scalarize the vector,
5518 // then treat like a scalar.
5519 if (NumElems == 1) {
5520 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
5521 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
5522 Op.getOperand(1), Op.getOperand(2));
5523 SplitVectorOp(Scalar, Lo, Hi);
5525 // Split the input vector.
5526 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5528 // Convert each of the pieces now.
5529 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
5530 NewNumEltsNode, TypeNode);
5531 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
5532 NewNumEltsNode, TypeNode);
5539 // Remember in a map if the values will be reused later.
5541 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5542 assert(isNew && "Value already expanded?!?");
5546 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
5547 /// equivalent operation that returns a scalar (e.g. F32) or packed value
5548 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
5549 /// type for the result.
5550 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
5551 MVT::ValueType NewVT) {
5552 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5553 SDNode *Node = Op.Val;
5555 // See if we already packed it.
5556 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5557 if (I != PackedNodes.end()) return I->second;
5560 switch (Node->getOpcode()) {
5563 Node->dump(); cerr << "\n";
5565 assert(0 && "Unknown vector operation in PackVectorOp!");
5574 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5576 PackVectorOp(Node->getOperand(0), NewVT),
5577 PackVectorOp(Node->getOperand(1), NewVT));
5580 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5581 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5583 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5584 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5586 // Remember that we legalized the chain.
5587 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5590 case ISD::VBUILD_VECTOR:
5591 if (Node->getOperand(0).getValueType() == NewVT) {
5592 // Returning a scalar?
5593 Result = Node->getOperand(0);
5595 // Returning a BUILD_VECTOR?
5597 // If all elements of the build_vector are undefs, return an undef.
5598 bool AllUndef = true;
5599 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5600 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5605 Result = DAG.getNode(ISD::UNDEF, NewVT);
5607 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5608 Node->getNumOperands()-2);
5612 case ISD::VINSERT_VECTOR_ELT:
5613 if (!MVT::isVector(NewVT)) {
5614 // Returning a scalar? Must be the inserted element.
5615 Result = Node->getOperand(1);
5617 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5618 PackVectorOp(Node->getOperand(0), NewVT),
5619 Node->getOperand(1), Node->getOperand(2));
5622 case ISD::VVECTOR_SHUFFLE:
5623 if (!MVT::isVector(NewVT)) {
5624 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5625 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5626 if (cast<ConstantSDNode>(EltNum)->getValue())
5627 Result = PackVectorOp(Node->getOperand(1), NewVT);
5629 Result = PackVectorOp(Node->getOperand(0), NewVT);
5631 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5632 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5633 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5634 Node->getOperand(2).Val->op_end()-2);
5635 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5636 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5637 Node->getOperand(2).Val->op_begin(),
5638 Node->getOperand(2).Val->getNumOperands()-2);
5640 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5641 PackVectorOp(Node->getOperand(0), NewVT),
5642 PackVectorOp(Node->getOperand(1), NewVT), BV);
5645 case ISD::VBIT_CONVERT:
5646 if (Op.getOperand(0).getValueType() != MVT::Vector)
5647 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5649 // If the input is a vector type, we have to either scalarize it, pack it
5650 // or convert it based on whether the input vector type is legal.
5651 SDNode *InVal = Node->getOperand(0).Val;
5653 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5654 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5656 // Figure out if there is a Packed type corresponding to this Vector
5657 // type. If so, convert to the vector type.
5658 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5659 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5660 // Turn this into a bit convert of the packed input.
5661 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5662 PackVectorOp(Node->getOperand(0), TVT));
5664 } else if (NumElems == 1) {
5665 // Turn this into a bit convert of the scalar input.
5666 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5667 PackVectorOp(Node->getOperand(0), EVT));
5671 assert(0 && "Cast from unsupported vector type not implemented yet!");
5676 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5677 PackVectorOp(Op.getOperand(1), NewVT),
5678 PackVectorOp(Op.getOperand(2), NewVT));
5682 if (TLI.isTypeLegal(NewVT))
5683 Result = LegalizeOp(Result);
5684 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5685 assert(isNew && "Value already packed?");
5690 // SelectionDAG::Legalize - This is the entry point for the file.
5692 void SelectionDAG::Legalize() {
5693 if (ViewLegalizeDAGs) viewGraph();
5695 /// run - This is the main entry point to this class.
5697 SelectionDAGLegalize(*this).LegalizeDAG();