1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 // Libcall insertion helpers.
46 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
47 /// legalized. We use this to ensure that calls are properly serialized
48 /// against each other, including inserted libcalls.
49 SDOperand LastCALLSEQ_END;
51 /// IsLegalizingCall - This member is used *only* for purposes of providing
52 /// helpful assertions that a libcall isn't created while another call is
53 /// being legalized (which could lead to non-serialized call sequences).
54 bool IsLegalizingCall;
57 Legal, // The target natively supports this operation.
58 Promote, // This operation should be executed in a larger type.
59 Expand, // Try to expand this to other ops, otherwise use a libcall.
62 /// ValueTypeActions - This is a bitvector that contains two bits for each
63 /// value type, where the two bits correspond to the LegalizeAction enum.
64 /// This can be queried with "getTypeAction(VT)".
65 TargetLowering::ValueTypeActionImpl ValueTypeActions;
67 /// LegalizedNodes - For nodes that are of legal width, and that have more
68 /// than one use, this map indicates what regularized operand to use. This
69 /// allows us to avoid legalizing the same thing more than once.
70 std::map<SDOperand, SDOperand> LegalizedNodes;
72 /// PromotedNodes - For nodes that are below legal width, and that have more
73 /// than one use, this map indicates what promoted value to use. This allows
74 /// us to avoid promoting the same thing more than once.
75 std::map<SDOperand, SDOperand> PromotedNodes;
77 /// ExpandedNodes - For nodes that need to be expanded this map indicates
78 /// which which operands are the expanded version of the input. This allows
79 /// us to avoid expanding the same node more than once.
80 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
82 /// SplitNodes - For vector nodes that need to be split, this map indicates
83 /// which which operands are the split version of the input. This allows us
84 /// to avoid splitting the same node more than once.
85 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
87 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
88 /// concrete packed types, this contains the mapping of ones we have already
89 /// processed to the result.
90 std::map<SDOperand, SDOperand> PackedNodes;
92 void AddLegalizedOperand(SDOperand From, SDOperand To) {
93 LegalizedNodes.insert(std::make_pair(From, To));
94 // If someone requests legalization of the new node, return itself.
96 LegalizedNodes.insert(std::make_pair(To, To));
98 void AddPromotedOperand(SDOperand From, SDOperand To) {
99 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
100 assert(isNew && "Got into the map somehow?");
101 // If someone requests legalization of the new node, return itself.
102 LegalizedNodes.insert(std::make_pair(To, To));
107 SelectionDAGLegalize(SelectionDAG &DAG);
109 /// getTypeAction - Return how we should legalize values of this type, either
110 /// it is already legal or we need to expand it into multiple registers of
111 /// smaller integer type, or we need to promote it to a larger type.
112 LegalizeAction getTypeAction(MVT::ValueType VT) const {
113 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
116 /// isTypeLegal - Return true if this type is legal on this target.
118 bool isTypeLegal(MVT::ValueType VT) const {
119 return getTypeAction(VT) == Legal;
125 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
126 /// appropriate for its type.
127 void HandleOp(SDOperand Op);
129 /// LegalizeOp - We know that the specified value has a legal type.
130 /// Recursively ensure that the operands have legal types, then return the
132 SDOperand LegalizeOp(SDOperand O);
134 /// PromoteOp - Given an operation that produces a value in an invalid type,
135 /// promote it to compute the value into a larger type. The produced value
136 /// will have the correct bits for the low portion of the register, but no
137 /// guarantee is made about the top bits: it may be zero, sign-extended, or
139 SDOperand PromoteOp(SDOperand O);
141 /// ExpandOp - Expand the specified SDOperand into its two component pieces
142 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
143 /// the LegalizeNodes map is filled in for any results that are not expanded,
144 /// the ExpandedNodes map is filled in for any results that are expanded, and
145 /// the Lo/Hi values are returned. This applies to integer types and Vector
147 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
149 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
150 /// two smaller values of MVT::Vector type.
151 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
153 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
154 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
155 /// this is called, we know that PackedVT is the right type for the result and
156 /// we know that this type is legal for the target.
157 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
159 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
161 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
163 SDOperand CreateStackTemporary(MVT::ValueType VT);
165 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
167 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
170 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
171 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
172 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
174 MVT::ValueType DestVT);
175 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
177 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
180 SDOperand ExpandBSWAP(SDOperand Op);
181 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
182 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
183 SDOperand &Lo, SDOperand &Hi);
184 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
185 SDOperand &Lo, SDOperand &Hi);
187 SDOperand getIntPtrConstant(uint64_t Val) {
188 return DAG.getConstant(Val, TLI.getPointerTy());
193 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
194 /// specified vector opcode.
195 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
197 default: assert(0 && "Don't know how to scalarize this opcode!");
198 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
199 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
200 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
201 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
202 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
203 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
204 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
205 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
209 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
210 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
211 ValueTypeActions(TLI.getValueTypeActions()) {
212 assert(MVT::LAST_VALUETYPE <= 32 &&
213 "Too many value types for ValueTypeActions to hold!");
216 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
217 /// not been visited yet and if all of its operands have already been visited.
218 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
219 std::map<SDNode*, unsigned> &Visited) {
220 if (++Visited[N] != N->getNumOperands())
221 return; // Haven't visited all operands yet
225 if (N->hasOneUse()) { // Tail recurse in common case.
226 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
230 // Now that we have N in, add anything that uses it if all of their operands
232 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
233 ComputeTopDownOrdering(*UI, Order, Visited);
237 void SelectionDAGLegalize::LegalizeDAG() {
238 LastCALLSEQ_END = DAG.getEntryNode();
239 IsLegalizingCall = false;
241 // The legalize process is inherently a bottom-up recursive process (users
242 // legalize their uses before themselves). Given infinite stack space, we
243 // could just start legalizing on the root and traverse the whole graph. In
244 // practice however, this causes us to run out of stack space on large basic
245 // blocks. To avoid this problem, compute an ordering of the nodes where each
246 // node is only legalized after all of its operands are legalized.
247 std::map<SDNode*, unsigned> Visited;
248 std::vector<SDNode*> Order;
250 // Compute ordering from all of the leaves in the graphs, those (like the
251 // entry node) that have no operands.
252 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
253 E = DAG.allnodes_end(); I != E; ++I) {
254 if (I->getNumOperands() == 0) {
256 ComputeTopDownOrdering(I, Order, Visited);
260 assert(Order.size() == Visited.size() &&
262 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
263 "Error: DAG is cyclic!");
266 for (unsigned i = 0, e = Order.size(); i != e; ++i)
267 HandleOp(SDOperand(Order[i], 0));
269 // Finally, it's possible the root changed. Get the new root.
270 SDOperand OldRoot = DAG.getRoot();
271 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
272 DAG.setRoot(LegalizedNodes[OldRoot]);
274 ExpandedNodes.clear();
275 LegalizedNodes.clear();
276 PromotedNodes.clear();
280 // Remove dead nodes now.
281 DAG.RemoveDeadNodes(OldRoot.Val);
285 /// FindCallEndFromCallStart - Given a chained node that is part of a call
286 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
287 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
288 if (Node->getOpcode() == ISD::CALLSEQ_END)
290 if (Node->use_empty())
291 return 0; // No CallSeqEnd
293 // The chain is usually at the end.
294 SDOperand TheChain(Node, Node->getNumValues()-1);
295 if (TheChain.getValueType() != MVT::Other) {
296 // Sometimes it's at the beginning.
297 TheChain = SDOperand(Node, 0);
298 if (TheChain.getValueType() != MVT::Other) {
299 // Otherwise, hunt for it.
300 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
301 if (Node->getValueType(i) == MVT::Other) {
302 TheChain = SDOperand(Node, i);
306 // Otherwise, we walked into a node without a chain.
307 if (TheChain.getValueType() != MVT::Other)
312 for (SDNode::use_iterator UI = Node->use_begin(),
313 E = Node->use_end(); UI != E; ++UI) {
315 // Make sure to only follow users of our token chain.
317 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
318 if (User->getOperand(i) == TheChain)
319 if (SDNode *Result = FindCallEndFromCallStart(User))
325 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
326 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
327 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
328 assert(Node && "Didn't find callseq_start for a call??");
329 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
331 assert(Node->getOperand(0).getValueType() == MVT::Other &&
332 "Node doesn't have a token chain argument!");
333 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
336 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
337 /// see if any uses can reach Dest. If no dest operands can get to dest,
338 /// legalize them, legalize ourself, and return false, otherwise, return true.
339 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
341 if (N == Dest) return true; // N certainly leads to Dest :)
343 // If the first result of this node has been already legalized, then it cannot
345 switch (getTypeAction(N->getValueType(0))) {
347 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
350 if (PromotedNodes.count(SDOperand(N, 0))) return false;
353 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
357 // Okay, this node has not already been legalized. Check and legalize all
358 // operands. If none lead to Dest, then we can legalize this node.
359 bool OperandsLeadToDest = false;
360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
361 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
362 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
364 if (OperandsLeadToDest) return true;
366 // Okay, this node looks safe, legalize it and return false.
367 switch (getTypeAction(N->getValueType(0))) {
369 LegalizeOp(SDOperand(N, 0));
372 PromoteOp(SDOperand(N, 0));
376 ExpandOp(SDOperand(N, 0), X, Y);
383 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
384 /// appropriate for its type.
385 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
386 switch (getTypeAction(Op.getValueType())) {
387 default: assert(0 && "Bad type action!");
388 case Legal: LegalizeOp(Op); break;
389 case Promote: PromoteOp(Op); break;
391 if (Op.getValueType() != MVT::Vector) {
396 unsigned NumOps = N->getNumOperands();
397 unsigned NumElements =
398 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
399 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
400 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
401 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
402 // In the common case, this is a legal vector type, convert it to the
403 // packed operation and type now.
404 PackVectorOp(Op, PackedVT);
405 } else if (NumElements == 1) {
406 // Otherwise, if this is a single element vector, convert it to a
408 PackVectorOp(Op, EVT);
410 // Otherwise, this is a multiple element vector that isn't supported.
411 // Split it in half and legalize both parts.
413 SplitVectorOp(Op, X, Y);
421 /// LegalizeOp - We know that the specified value has a legal type.
422 /// Recursively ensure that the operands have legal types, then return the
424 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
425 assert(isTypeLegal(Op.getValueType()) &&
426 "Caller should expand or promote operands that are not legal!");
427 SDNode *Node = Op.Val;
429 // If this operation defines any values that cannot be represented in a
430 // register on this target, make sure to expand or promote them.
431 if (Node->getNumValues() > 1) {
432 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
433 if (getTypeAction(Node->getValueType(i)) != Legal) {
434 HandleOp(Op.getValue(i));
435 assert(LegalizedNodes.count(Op) &&
436 "Handling didn't add legal operands!");
437 return LegalizedNodes[Op];
441 // Note that LegalizeOp may be reentered even from single-use nodes, which
442 // means that we always must cache transformed nodes.
443 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
444 if (I != LegalizedNodes.end()) return I->second;
446 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
447 SDOperand Result = Op;
448 bool isCustom = false;
450 switch (Node->getOpcode()) {
451 case ISD::FrameIndex:
452 case ISD::EntryToken:
454 case ISD::BasicBlock:
455 case ISD::TargetFrameIndex:
456 case ISD::TargetConstant:
457 case ISD::TargetConstantFP:
458 case ISD::TargetConstantPool:
459 case ISD::TargetGlobalAddress:
460 case ISD::TargetExternalSymbol:
465 // Primitives must all be legal.
466 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
467 "This must be legal!");
470 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
471 // If this is a target node, legalize it by legalizing the operands then
472 // passing it through.
473 std::vector<SDOperand> Ops;
474 bool Changed = false;
475 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
476 Ops.push_back(LegalizeOp(Node->getOperand(i)));
477 Changed = Changed || Node->getOperand(i) != Ops.back();
480 if (Node->getNumValues() == 1)
481 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
483 std::vector<MVT::ValueType> VTs(Node->value_begin(),
485 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
488 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
489 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
490 return Result.getValue(Op.ResNo);
492 // Otherwise this is an unhandled builtin node. splat.
493 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
494 assert(0 && "Do not know how to legalize this operator!");
496 case ISD::GlobalAddress:
497 case ISD::ExternalSymbol:
498 case ISD::ConstantPool: // Nothing to do.
499 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
500 default: assert(0 && "This action is not supported yet!");
501 case TargetLowering::Custom:
502 Tmp1 = TLI.LowerOperation(Op, DAG);
503 if (Tmp1.Val) Result = Tmp1;
504 // FALLTHROUGH if the target doesn't want to lower this op after all.
505 case TargetLowering::Legal:
509 case ISD::AssertSext:
510 case ISD::AssertZext:
511 Tmp1 = LegalizeOp(Node->getOperand(0));
512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
514 case ISD::MERGE_VALUES:
515 // Legalize eliminates MERGE_VALUES nodes.
516 Result = Node->getOperand(Op.ResNo);
518 case ISD::CopyFromReg:
519 Tmp1 = LegalizeOp(Node->getOperand(0));
520 Result = Op.getValue(0);
521 if (Node->getNumValues() == 2) {
522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
524 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
525 if (Node->getNumOperands() == 3) {
526 Tmp2 = LegalizeOp(Node->getOperand(2));
527 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
531 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
533 // Since CopyFromReg produces two values, make sure to remember that we
534 // legalized both of them.
535 AddLegalizedOperand(Op.getValue(0), Result);
536 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
537 return Result.getValue(Op.ResNo);
539 MVT::ValueType VT = Op.getValueType();
540 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
541 default: assert(0 && "This action is not supported yet!");
542 case TargetLowering::Expand:
543 if (MVT::isInteger(VT))
544 Result = DAG.getConstant(0, VT);
545 else if (MVT::isFloatingPoint(VT))
546 Result = DAG.getConstantFP(0, VT);
548 assert(0 && "Unknown value type!");
550 case TargetLowering::Legal:
557 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
558 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
560 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
561 case TargetLowering::Promote:
562 default: assert(0 && "This action is not supported yet!");
563 case TargetLowering::Expand: {
564 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
565 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
566 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
568 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
569 const std::string &FName =
570 cast<StringSDNode>(Node->getOperand(3))->getValue();
571 const std::string &DirName =
572 cast<StringSDNode>(Node->getOperand(4))->getValue();
573 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
575 std::vector<SDOperand> Ops;
576 Ops.push_back(Tmp1); // chain
577 SDOperand LineOp = Node->getOperand(1);
578 SDOperand ColOp = Node->getOperand(2);
581 Ops.push_back(LineOp); // line #
582 Ops.push_back(ColOp); // col #
583 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
584 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
586 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
587 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
588 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
589 Ops.push_back(DAG.getConstant(ID, MVT::i32));
590 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
593 Result = Tmp1; // chain
597 case TargetLowering::Legal:
598 if (Tmp1 != Node->getOperand(0) ||
599 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
600 std::vector<SDOperand> Ops;
602 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
603 Ops.push_back(Node->getOperand(1)); // line # must be legal.
604 Ops.push_back(Node->getOperand(2)); // col # must be legal.
606 // Otherwise promote them.
607 Ops.push_back(PromoteOp(Node->getOperand(1)));
608 Ops.push_back(PromoteOp(Node->getOperand(2)));
610 Ops.push_back(Node->getOperand(3)); // filename must be legal.
611 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
612 Result = DAG.UpdateNodeOperands(Result, Ops);
619 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
620 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
621 default: assert(0 && "This action is not supported yet!");
622 case TargetLowering::Legal:
623 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
624 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
625 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
626 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
632 case ISD::DEBUG_LABEL:
633 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
634 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
635 default: assert(0 && "This action is not supported yet!");
636 case TargetLowering::Legal:
637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
638 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
645 // We know we don't need to expand constants here, constants only have one
646 // value and we check that it is fine above.
648 // FIXME: Maybe we should handle things like targets that don't support full
649 // 32-bit immediates?
651 case ISD::ConstantFP: {
652 // Spill FP immediates to the constant pool if the target cannot directly
653 // codegen them. Targets often have some immediate values that can be
654 // efficiently generated into an FP register without a load. We explicitly
655 // leave these constants as ConstantFP nodes for the target to deal with.
656 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
658 // Check to see if this FP immediate is already legal.
659 bool isLegal = false;
660 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
661 E = TLI.legal_fpimm_end(); I != E; ++I)
662 if (CFP->isExactlyValue(*I)) {
667 // If this is a legal constant, turn it into a TargetConstantFP node.
669 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
673 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
674 default: assert(0 && "This action is not supported yet!");
675 case TargetLowering::Custom:
676 Tmp3 = TLI.LowerOperation(Result, DAG);
682 case TargetLowering::Expand:
683 // Otherwise we need to spill the constant to memory.
686 // If a FP immediate is precise when represented as a float and if the
687 // target can do an extending load from float to double, we put it into
688 // the constant pool as a float, even if it's is statically typed as a
690 MVT::ValueType VT = CFP->getValueType(0);
691 bool isDouble = VT == MVT::f64;
692 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
693 Type::FloatTy, CFP->getValue());
694 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
695 // Only do this if the target has a native EXTLOAD instruction from
697 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
698 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
703 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
705 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
706 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
708 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
709 DAG.getSrcValue(NULL));
714 case ISD::TokenFactor:
715 if (Node->getNumOperands() == 2) {
716 Tmp1 = LegalizeOp(Node->getOperand(0));
717 Tmp2 = LegalizeOp(Node->getOperand(1));
718 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
719 } else if (Node->getNumOperands() == 3) {
720 Tmp1 = LegalizeOp(Node->getOperand(0));
721 Tmp2 = LegalizeOp(Node->getOperand(1));
722 Tmp3 = LegalizeOp(Node->getOperand(2));
723 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
725 std::vector<SDOperand> Ops;
726 // Legalize the operands.
727 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
728 Ops.push_back(LegalizeOp(Node->getOperand(i)));
729 Result = DAG.UpdateNodeOperands(Result, Ops);
733 case ISD::BUILD_VECTOR:
734 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
735 default: assert(0 && "This action is not supported yet!");
736 case TargetLowering::Custom:
737 Tmp3 = TLI.LowerOperation(Result, DAG);
743 case TargetLowering::Expand:
744 Result = ExpandBUILD_VECTOR(Result.Val);
748 case ISD::INSERT_VECTOR_ELT:
749 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
750 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
751 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
752 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
754 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
755 Node->getValueType(0))) {
756 default: assert(0 && "This action is not supported yet!");
757 case TargetLowering::Legal:
759 case TargetLowering::Custom:
760 Tmp3 = TLI.LowerOperation(Result, DAG);
766 case TargetLowering::Expand: {
767 // If the target doesn't support this, we have to spill the input vector
768 // to a temporary stack slot, update the element, then reload it. This is
769 // badness. We could also load the value into a vector register (either
770 // with a "move to register" or "extload into register" instruction, then
771 // permute it into place, if the idx is a constant and if the idx is
772 // supported by the target.
773 assert(0 && "INSERT_VECTOR_ELT expand not supported yet!");
778 case ISD::SCALAR_TO_VECTOR:
779 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
780 Result = DAG.UpdateNodeOperands(Result, Tmp1);
781 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
782 Node->getValueType(0))) {
783 default: assert(0 && "This action is not supported yet!");
784 case TargetLowering::Legal:
786 case TargetLowering::Custom:
787 Tmp3 = TLI.LowerOperation(Result, DAG);
793 case TargetLowering::Expand: {
794 // If the target doesn't support this, store the value to a temporary
795 // stack slot, then EXTLOAD the vector back out.
796 // TODO: If a target doesn't support this, create a stack slot for the
797 // whole vector, then store into it, then load the whole vector.
799 CreateStackTemporary(Node->getOperand(0).getValueType());
800 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
801 Node->getOperand(0), StackPtr,
802 DAG.getSrcValue(NULL));
803 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), Ch, StackPtr,
804 DAG.getSrcValue(NULL),
805 Node->getOperand(0).getValueType());
810 case ISD::VECTOR_SHUFFLE:
811 assert(TLI.isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
812 "vector shuffle should not be created if not legal!");
813 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
814 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
817 // Allow targets to custom lower the SHUFFLEs they support.
818 if (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, Result.getValueType())
819 == TargetLowering::Custom) {
820 Tmp1 = TLI.LowerOperation(Result, DAG);
821 if (Tmp1.Val) Result = Tmp1;
825 case ISD::EXTRACT_VECTOR_ELT:
826 Tmp1 = LegalizeOp(Node->getOperand(0));
827 Tmp2 = LegalizeOp(Node->getOperand(1));
828 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
830 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
831 Tmp1.getValueType())) {
832 default: assert(0 && "This action is not supported yet!");
833 case TargetLowering::Legal:
835 case TargetLowering::Custom:
836 Tmp3 = TLI.LowerOperation(Result, DAG);
842 case TargetLowering::Expand: {
843 // If the target doesn't support this, store the value to a temporary
844 // stack slot, then LOAD the scalar element back out.
845 SDOperand StackPtr = CreateStackTemporary(Tmp1.getValueType());
846 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
847 Tmp1, StackPtr, DAG.getSrcValue(NULL));
849 // Add the offset to the index.
850 unsigned EltSize = MVT::getSizeInBits(Result.getValueType())/8;
851 Tmp2 = DAG.getNode(ISD::MUL, Tmp2.getValueType(), Tmp2,
852 DAG.getConstant(EltSize, Tmp2.getValueType()));
853 StackPtr = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2, StackPtr);
855 Result = DAG.getLoad(Result.getValueType(), Ch, StackPtr,
856 DAG.getSrcValue(NULL));
862 case ISD::VEXTRACT_VECTOR_ELT:
863 // We know that operand #0 is the Vec vector. If the index is a constant
864 // or if the invec is a supported hardware type, we can use it. Otherwise,
865 // lower to a store then an indexed load.
866 Tmp1 = Node->getOperand(0);
867 Tmp2 = LegalizeOp(Node->getOperand(1));
869 SDNode *InVal = Tmp1.Val;
870 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
871 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
873 // Figure out if there is a Packed type corresponding to this Vector
874 // type. If so, convert to the packed type.
875 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
876 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
877 // Turn this into a packed extract_vector_elt operation.
878 Tmp1 = PackVectorOp(Tmp1, TVT);
879 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Node->getValueType(0),
882 } else if (NumElems == 1) {
883 // This must be an access of the only element.
884 Result = PackVectorOp(Tmp1, EVT);
886 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Tmp2)) {
888 SplitVectorOp(Tmp1, Lo, Hi);
889 if (CIdx->getValue() < NumElems/2) {
893 Tmp2 = DAG.getConstant(CIdx->getValue() - NumElems/2,
894 Tmp2.getValueType());
897 // It's now an extract from the appropriate high or low part.
898 Result = LegalizeOp(DAG.UpdateNodeOperands(Result, Tmp1, Tmp2));
900 // FIXME: IMPLEMENT STORE/LOAD lowering.
901 assert(0 && "unimp!");
905 case ISD::CALLSEQ_START: {
906 SDNode *CallEnd = FindCallEndFromCallStart(Node);
908 // Recursively Legalize all of the inputs of the call end that do not lead
909 // to this call start. This ensures that any libcalls that need be inserted
910 // are inserted *before* the CALLSEQ_START.
911 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
912 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
914 // Now that we legalized all of the inputs (which may have inserted
915 // libcalls) create the new CALLSEQ_START node.
916 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
918 // Merge in the last call, to ensure that this call start after the last
920 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
921 Tmp1 = LegalizeOp(Tmp1);
923 // Do not try to legalize the target-specific arguments (#1+).
924 if (Tmp1 != Node->getOperand(0)) {
925 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
927 Result = DAG.UpdateNodeOperands(Result, Ops);
930 // Remember that the CALLSEQ_START is legalized.
931 AddLegalizedOperand(Op.getValue(0), Result);
932 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
933 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
935 // Now that the callseq_start and all of the non-call nodes above this call
936 // sequence have been legalized, legalize the call itself. During this
937 // process, no libcalls can/will be inserted, guaranteeing that no calls
939 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
940 SDOperand InCallSEQ = LastCALLSEQ_END;
941 // Note that we are selecting this call!
942 LastCALLSEQ_END = SDOperand(CallEnd, 0);
943 IsLegalizingCall = true;
945 // Legalize the call, starting from the CALLSEQ_END.
946 LegalizeOp(LastCALLSEQ_END);
947 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
950 case ISD::CALLSEQ_END:
951 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
952 // will cause this node to be legalized as well as handling libcalls right.
953 if (LastCALLSEQ_END.Val != Node) {
954 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
955 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
956 assert(I != LegalizedNodes.end() &&
957 "Legalizing the call start should have legalized this node!");
961 // Otherwise, the call start has been legalized and everything is going
962 // according to plan. Just legalize ourselves normally here.
963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
964 // Do not try to legalize the target-specific arguments (#1+), except for
965 // an optional flag input.
966 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
967 if (Tmp1 != Node->getOperand(0)) {
968 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
970 Result = DAG.UpdateNodeOperands(Result, Ops);
973 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
974 if (Tmp1 != Node->getOperand(0) ||
975 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
976 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
979 Result = DAG.UpdateNodeOperands(Result, Ops);
982 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
983 // This finishes up call legalization.
984 IsLegalizingCall = false;
986 // If the CALLSEQ_END node has a flag, remember that we legalized it.
987 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
988 if (Node->getNumValues() == 2)
989 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
990 return Result.getValue(Op.ResNo);
991 case ISD::DYNAMIC_STACKALLOC: {
992 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
993 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
994 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
995 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
997 Tmp1 = Result.getValue(0);
998 Tmp2 = Result.getValue(1);
999 switch (TLI.getOperationAction(Node->getOpcode(),
1000 Node->getValueType(0))) {
1001 default: assert(0 && "This action is not supported yet!");
1002 case TargetLowering::Expand: {
1003 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1004 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1005 " not tell us which reg is the stack pointer!");
1006 SDOperand Chain = Tmp1.getOperand(0);
1007 SDOperand Size = Tmp2.getOperand(1);
1008 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1009 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1010 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1011 Tmp1 = LegalizeOp(Tmp1);
1012 Tmp2 = LegalizeOp(Tmp2);
1015 case TargetLowering::Custom:
1016 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1018 Tmp1 = LegalizeOp(Tmp3);
1019 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1022 case TargetLowering::Legal:
1025 // Since this op produce two values, make sure to remember that we
1026 // legalized both of them.
1027 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1028 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1029 return Op.ResNo ? Tmp2 : Tmp1;
1031 case ISD::INLINEASM:
1032 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain.
1033 Tmp2 = Node->getOperand(Node->getNumOperands()-1);
1034 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists.
1035 Tmp2 = Tmp3 = SDOperand(0, 0);
1037 Tmp3 = LegalizeOp(Tmp2);
1039 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
1040 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1042 if (Tmp3.Val) Ops.back() = Tmp3;
1043 Result = DAG.UpdateNodeOperands(Result, Ops);
1046 // INLINE asm returns a chain and flag, make sure to add both to the map.
1047 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1048 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1049 return Result.getValue(Op.ResNo);
1051 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1052 // Ensure that libcalls are emitted before a branch.
1053 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1054 Tmp1 = LegalizeOp(Tmp1);
1055 LastCALLSEQ_END = DAG.getEntryNode();
1057 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1061 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1062 // Ensure that libcalls are emitted before a return.
1063 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1064 Tmp1 = LegalizeOp(Tmp1);
1065 LastCALLSEQ_END = DAG.getEntryNode();
1067 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1068 case Expand: assert(0 && "It's impossible to expand bools");
1070 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1073 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1077 // Basic block destination (Op#2) is always legal.
1078 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1080 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1081 default: assert(0 && "This action is not supported yet!");
1082 case TargetLowering::Legal: break;
1083 case TargetLowering::Custom:
1084 Tmp1 = TLI.LowerOperation(Result, DAG);
1085 if (Tmp1.Val) Result = Tmp1;
1087 case TargetLowering::Expand:
1088 // Expand brcond's setcc into its constituent parts and create a BR_CC
1090 if (Tmp2.getOpcode() == ISD::SETCC) {
1091 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1092 Tmp2.getOperand(0), Tmp2.getOperand(1),
1093 Node->getOperand(2));
1095 // Make sure the condition is either zero or one. It may have been
1096 // promoted from something else.
1097 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1098 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1099 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1101 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1102 DAG.getCondCode(ISD::SETNE), Tmp2,
1103 DAG.getConstant(0, Tmp2.getValueType()),
1104 Node->getOperand(2));
1110 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1111 // Ensure that libcalls are emitted before a branch.
1112 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1113 Tmp1 = LegalizeOp(Tmp1);
1114 LastCALLSEQ_END = DAG.getEntryNode();
1116 Tmp2 = Node->getOperand(2); // LHS
1117 Tmp3 = Node->getOperand(3); // RHS
1118 Tmp4 = Node->getOperand(1); // CC
1120 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1122 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1123 // the LHS is a legal SETCC itself. In this case, we need to compare
1124 // the result against zero to select between true and false values.
1125 if (Tmp3.Val == 0) {
1126 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1127 Tmp4 = DAG.getCondCode(ISD::SETNE);
1130 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1131 Node->getOperand(4));
1133 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1134 default: assert(0 && "Unexpected action for BR_CC!");
1135 case TargetLowering::Legal: break;
1136 case TargetLowering::Custom:
1137 Tmp4 = TLI.LowerOperation(Result, DAG);
1138 if (Tmp4.Val) Result = Tmp4;
1143 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1144 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1146 MVT::ValueType VT = Node->getValueType(0);
1147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1148 Tmp2 = Result.getValue(0);
1149 Tmp3 = Result.getValue(1);
1151 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1152 default: assert(0 && "This action is not supported yet!");
1153 case TargetLowering::Legal: break;
1154 case TargetLowering::Custom:
1155 Tmp1 = TLI.LowerOperation(Tmp2, DAG);
1157 Tmp2 = LegalizeOp(Tmp1);
1158 Tmp3 = LegalizeOp(Tmp1.getValue(1));
1162 // Since loads produce two values, make sure to remember that we
1163 // legalized both of them.
1164 AddLegalizedOperand(SDOperand(Node, 0), Tmp2);
1165 AddLegalizedOperand(SDOperand(Node, 1), Tmp3);
1166 return Op.ResNo ? Tmp3 : Tmp2;
1170 case ISD::ZEXTLOAD: {
1171 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1172 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1174 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1175 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1176 default: assert(0 && "This action is not supported yet!");
1177 case TargetLowering::Promote:
1178 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1179 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1180 DAG.getValueType(MVT::i8));
1181 Tmp1 = Result.getValue(0);
1182 Tmp2 = Result.getValue(1);
1184 case TargetLowering::Custom:
1187 case TargetLowering::Legal:
1188 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1189 Node->getOperand(3));
1190 Tmp1 = Result.getValue(0);
1191 Tmp2 = Result.getValue(1);
1194 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1196 Tmp1 = LegalizeOp(Tmp3);
1197 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1201 case TargetLowering::Expand:
1202 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1203 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1204 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1205 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1206 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1207 Tmp2 = LegalizeOp(Load.getValue(1));
1210 assert(Node->getOpcode() != ISD::EXTLOAD &&
1211 "EXTLOAD should always be supported!");
1212 // Turn the unsupported load into an EXTLOAD followed by an explicit
1213 // zero/sign extend inreg.
1214 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1215 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1217 if (Node->getOpcode() == ISD::SEXTLOAD)
1218 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1219 Result, DAG.getValueType(SrcVT));
1221 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1222 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1223 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1226 // Since loads produce two values, make sure to remember that we legalized
1228 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1229 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1230 return Op.ResNo ? Tmp2 : Tmp1;
1232 case ISD::EXTRACT_ELEMENT: {
1233 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1234 switch (getTypeAction(OpTy)) {
1235 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1237 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1239 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1240 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1241 TLI.getShiftAmountTy()));
1242 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1245 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1246 Node->getOperand(0));
1250 // Get both the low and high parts.
1251 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1252 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1253 Result = Tmp2; // 1 -> Hi
1255 Result = Tmp1; // 0 -> Lo
1261 case ISD::CopyToReg:
1262 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1264 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1265 "Register type must be legal!");
1266 // Legalize the incoming value (must be a legal type).
1267 Tmp2 = LegalizeOp(Node->getOperand(2));
1268 if (Node->getNumValues() == 1) {
1269 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1271 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1272 if (Node->getNumOperands() == 4) {
1273 Tmp3 = LegalizeOp(Node->getOperand(3));
1274 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1277 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1280 // Since this produces two values, make sure to remember that we legalized
1282 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1283 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1289 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1291 // Ensure that libcalls are emitted before a return.
1292 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1293 Tmp1 = LegalizeOp(Tmp1);
1294 LastCALLSEQ_END = DAG.getEntryNode();
1296 switch (Node->getNumOperands()) {
1298 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1300 Tmp2 = LegalizeOp(Node->getOperand(1));
1301 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1305 ExpandOp(Node->getOperand(1), Lo, Hi);
1306 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1310 Tmp2 = PromoteOp(Node->getOperand(1));
1311 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1312 Result = LegalizeOp(Result);
1317 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1319 default: { // ret <values>
1320 std::vector<SDOperand> NewValues;
1321 NewValues.push_back(Tmp1);
1322 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1323 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1325 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1329 ExpandOp(Node->getOperand(i), Lo, Hi);
1330 NewValues.push_back(Lo);
1331 NewValues.push_back(Hi);
1335 assert(0 && "Can't promote multiple return value yet!");
1338 if (NewValues.size() == Node->getNumOperands())
1339 Result = DAG.UpdateNodeOperands(Result, NewValues);
1341 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1346 if (Result.getOpcode() == ISD::RET) {
1347 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1348 default: assert(0 && "This action is not supported yet!");
1349 case TargetLowering::Legal: break;
1350 case TargetLowering::Custom:
1351 Tmp1 = TLI.LowerOperation(Result, DAG);
1352 if (Tmp1.Val) Result = Tmp1;
1358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1359 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1361 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1362 // FIXME: We shouldn't do this for TargetConstantFP's.
1363 // FIXME: move this to the DAG Combiner!
1364 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1365 if (CFP->getValueType(0) == MVT::f32) {
1366 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1368 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1369 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1371 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1372 Node->getOperand(3));
1376 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1378 Tmp3 = LegalizeOp(Node->getOperand(1));
1379 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1380 Node->getOperand(3));
1382 MVT::ValueType VT = Tmp3.getValueType();
1383 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1384 default: assert(0 && "This action is not supported yet!");
1385 case TargetLowering::Legal: break;
1386 case TargetLowering::Custom:
1387 Tmp1 = TLI.LowerOperation(Result, DAG);
1388 if (Tmp1.Val) Result = Tmp1;
1394 // Truncate the value and store the result.
1395 Tmp3 = PromoteOp(Node->getOperand(1));
1396 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1397 Node->getOperand(3),
1398 DAG.getValueType(Node->getOperand(1).getValueType()));
1402 unsigned IncrementSize = 0;
1405 // If this is a vector type, then we have to calculate the increment as
1406 // the product of the element size in bytes, and the number of elements
1407 // in the high half of the vector.
1408 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1409 SDNode *InVal = Node->getOperand(1).Val;
1411 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1412 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1414 // Figure out if there is a Packed type corresponding to this Vector
1415 // type. If so, convert to the packed type.
1416 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1417 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1418 // Turn this into a normal store of the packed type.
1419 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1421 Node->getOperand(3));
1423 } else if (NumElems == 1) {
1424 // Turn this into a normal store of the scalar type.
1425 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1426 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1427 Node->getOperand(3));
1430 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1431 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1434 ExpandOp(Node->getOperand(1), Lo, Hi);
1435 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1438 if (!TLI.isLittleEndian())
1441 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1442 Node->getOperand(3));
1443 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1444 getIntPtrConstant(IncrementSize));
1445 assert(isTypeLegal(Tmp2.getValueType()) &&
1446 "Pointers must be legal!");
1447 // FIXME: This sets the srcvalue of both halves to be the same, which is
1449 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1450 Node->getOperand(3));
1451 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1457 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1458 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1460 case ISD::STACKSAVE:
1461 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1462 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1463 Tmp1 = Result.getValue(0);
1464 Tmp2 = Result.getValue(1);
1466 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1467 default: assert(0 && "This action is not supported yet!");
1468 case TargetLowering::Legal: break;
1469 case TargetLowering::Custom:
1470 Tmp3 = TLI.LowerOperation(Result, DAG);
1472 Tmp1 = LegalizeOp(Tmp3);
1473 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1476 case TargetLowering::Expand:
1477 // Expand to CopyFromReg if the target set
1478 // StackPointerRegisterToSaveRestore.
1479 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1480 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1481 Node->getValueType(0));
1482 Tmp2 = Tmp1.getValue(1);
1484 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1485 Tmp2 = Node->getOperand(0);
1490 // Since stacksave produce two values, make sure to remember that we
1491 // legalized both of them.
1492 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1493 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1494 return Op.ResNo ? Tmp2 : Tmp1;
1496 case ISD::STACKRESTORE:
1497 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1498 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1499 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1501 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1502 default: assert(0 && "This action is not supported yet!");
1503 case TargetLowering::Legal: break;
1504 case TargetLowering::Custom:
1505 Tmp1 = TLI.LowerOperation(Result, DAG);
1506 if (Tmp1.Val) Result = Tmp1;
1508 case TargetLowering::Expand:
1509 // Expand to CopyToReg if the target set
1510 // StackPointerRegisterToSaveRestore.
1511 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1512 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1520 case ISD::READCYCLECOUNTER:
1521 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1522 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1524 // Since rdcc produce two values, make sure to remember that we legalized
1526 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1527 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1530 case ISD::TRUNCSTORE: {
1531 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1532 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1534 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1535 "Cannot handle illegal TRUNCSTORE yet!");
1536 Tmp2 = LegalizeOp(Node->getOperand(1));
1538 // The only promote case we handle is TRUNCSTORE:i1 X into
1539 // -> TRUNCSTORE:i8 (and X, 1)
1540 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1541 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1542 TargetLowering::Promote) {
1543 // Promote the bool to a mask then store.
1544 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1545 DAG.getConstant(1, Tmp2.getValueType()));
1546 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1547 Node->getOperand(3), DAG.getValueType(MVT::i8));
1549 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1550 Tmp3 != Node->getOperand(2)) {
1551 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1552 Node->getOperand(3), Node->getOperand(4));
1555 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1556 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1557 default: assert(0 && "This action is not supported yet!");
1558 case TargetLowering::Legal: break;
1559 case TargetLowering::Custom:
1560 Tmp1 = TLI.LowerOperation(Result, DAG);
1561 if (Tmp1.Val) Result = Tmp1;
1567 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1568 case Expand: assert(0 && "It's impossible to expand bools");
1570 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1573 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1576 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1577 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1581 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1582 default: assert(0 && "This action is not supported yet!");
1583 case TargetLowering::Legal: break;
1584 case TargetLowering::Custom: {
1585 Tmp1 = TLI.LowerOperation(Result, DAG);
1586 if (Tmp1.Val) Result = Tmp1;
1589 case TargetLowering::Expand:
1590 if (Tmp1.getOpcode() == ISD::SETCC) {
1591 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1593 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1595 // Make sure the condition is either zero or one. It may have been
1596 // promoted from something else.
1597 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1598 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1599 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1600 Result = DAG.getSelectCC(Tmp1,
1601 DAG.getConstant(0, Tmp1.getValueType()),
1602 Tmp2, Tmp3, ISD::SETNE);
1605 case TargetLowering::Promote: {
1606 MVT::ValueType NVT =
1607 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1608 unsigned ExtOp, TruncOp;
1609 if (MVT::isInteger(Tmp2.getValueType())) {
1610 ExtOp = ISD::ANY_EXTEND;
1611 TruncOp = ISD::TRUNCATE;
1613 ExtOp = ISD::FP_EXTEND;
1614 TruncOp = ISD::FP_ROUND;
1616 // Promote each of the values to the new type.
1617 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1618 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1619 // Perform the larger operation, then round down.
1620 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1621 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1626 case ISD::SELECT_CC: {
1627 Tmp1 = Node->getOperand(0); // LHS
1628 Tmp2 = Node->getOperand(1); // RHS
1629 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1630 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1631 SDOperand CC = Node->getOperand(4);
1633 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1635 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1636 // the LHS is a legal SETCC itself. In this case, we need to compare
1637 // the result against zero to select between true and false values.
1638 if (Tmp2.Val == 0) {
1639 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1640 CC = DAG.getCondCode(ISD::SETNE);
1642 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1644 // Everything is legal, see if we should expand this op or something.
1645 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1646 default: assert(0 && "This action is not supported yet!");
1647 case TargetLowering::Legal: break;
1648 case TargetLowering::Custom:
1649 Tmp1 = TLI.LowerOperation(Result, DAG);
1650 if (Tmp1.Val) Result = Tmp1;
1656 Tmp1 = Node->getOperand(0);
1657 Tmp2 = Node->getOperand(1);
1658 Tmp3 = Node->getOperand(2);
1659 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1661 // If we had to Expand the SetCC operands into a SELECT node, then it may
1662 // not always be possible to return a true LHS & RHS. In this case, just
1663 // return the value we legalized, returned in the LHS
1664 if (Tmp2.Val == 0) {
1669 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1670 default: assert(0 && "Cannot handle this action for SETCC yet!");
1671 case TargetLowering::Custom:
1674 case TargetLowering::Legal:
1675 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1677 Tmp3 = TLI.LowerOperation(Result, DAG);
1678 if (Tmp3.Val) Result = Tmp3;
1681 case TargetLowering::Promote: {
1682 // First step, figure out the appropriate operation to use.
1683 // Allow SETCC to not be supported for all legal data types
1684 // Mostly this targets FP
1685 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1686 MVT::ValueType OldVT = NewInTy;
1688 // Scan for the appropriate larger type to use.
1690 NewInTy = (MVT::ValueType)(NewInTy+1);
1692 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1693 "Fell off of the edge of the integer world");
1694 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1695 "Fell off of the edge of the floating point world");
1697 // If the target supports SETCC of this type, use it.
1698 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1701 if (MVT::isInteger(NewInTy))
1702 assert(0 && "Cannot promote Legal Integer SETCC yet");
1704 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1705 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1707 Tmp1 = LegalizeOp(Tmp1);
1708 Tmp2 = LegalizeOp(Tmp2);
1709 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1710 Result = LegalizeOp(Result);
1713 case TargetLowering::Expand:
1714 // Expand a setcc node into a select_cc of the same condition, lhs, and
1715 // rhs that selects between const 1 (true) and const 0 (false).
1716 MVT::ValueType VT = Node->getValueType(0);
1717 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1718 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1719 Node->getOperand(2));
1725 case ISD::MEMMOVE: {
1726 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1727 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1729 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1730 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1731 case Expand: assert(0 && "Cannot expand a byte!");
1733 Tmp3 = LegalizeOp(Node->getOperand(2));
1736 Tmp3 = PromoteOp(Node->getOperand(2));
1740 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1744 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1746 // Length is too big, just take the lo-part of the length.
1748 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1752 Tmp4 = LegalizeOp(Node->getOperand(3));
1755 Tmp4 = PromoteOp(Node->getOperand(3));
1760 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1761 case Expand: assert(0 && "Cannot expand this yet!");
1763 Tmp5 = LegalizeOp(Node->getOperand(4));
1766 Tmp5 = PromoteOp(Node->getOperand(4));
1770 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1771 default: assert(0 && "This action not implemented for this operation!");
1772 case TargetLowering::Custom:
1775 case TargetLowering::Legal:
1776 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
1778 Tmp1 = TLI.LowerOperation(Result, DAG);
1779 if (Tmp1.Val) Result = Tmp1;
1782 case TargetLowering::Expand: {
1783 // Otherwise, the target does not support this operation. Lower the
1784 // operation to an explicit libcall as appropriate.
1785 MVT::ValueType IntPtr = TLI.getPointerTy();
1786 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1787 std::vector<std::pair<SDOperand, const Type*> > Args;
1789 const char *FnName = 0;
1790 if (Node->getOpcode() == ISD::MEMSET) {
1791 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1792 // Extend the (previously legalized) ubyte argument to be an int value
1794 if (Tmp3.getValueType() > MVT::i32)
1795 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
1797 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1798 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1799 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1802 } else if (Node->getOpcode() == ISD::MEMCPY ||
1803 Node->getOpcode() == ISD::MEMMOVE) {
1804 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1805 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1806 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1807 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1809 assert(0 && "Unknown op!");
1812 std::pair<SDOperand,SDOperand> CallResult =
1813 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1814 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1815 Result = CallResult.second;
1822 case ISD::SHL_PARTS:
1823 case ISD::SRA_PARTS:
1824 case ISD::SRL_PARTS: {
1825 std::vector<SDOperand> Ops;
1826 bool Changed = false;
1827 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1828 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1829 Changed |= Ops.back() != Node->getOperand(i);
1832 Result = DAG.UpdateNodeOperands(Result, Ops);
1834 switch (TLI.getOperationAction(Node->getOpcode(),
1835 Node->getValueType(0))) {
1836 default: assert(0 && "This action is not supported yet!");
1837 case TargetLowering::Legal: break;
1838 case TargetLowering::Custom:
1839 Tmp1 = TLI.LowerOperation(Result, DAG);
1841 SDOperand Tmp2, RetVal(0, 0);
1842 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1843 Tmp2 = LegalizeOp(Tmp1.getValue(i));
1844 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
1848 assert(RetVal.Val && "Illegal result number");
1854 // Since these produce multiple values, make sure to remember that we
1855 // legalized all of them.
1856 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1857 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1858 return Result.getValue(Op.ResNo);
1879 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1880 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1881 case Expand: assert(0 && "Not possible");
1883 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1886 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1890 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1892 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1893 default: assert(0 && "Operation not supported");
1894 case TargetLowering::Legal: break;
1895 case TargetLowering::Custom:
1896 Tmp1 = TLI.LowerOperation(Result, DAG);
1897 if (Tmp1.Val) Result = Tmp1;
1902 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
1903 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1904 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1905 case Expand: assert(0 && "Not possible");
1907 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1910 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1916 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1917 default: assert(0 && "Operation not supported");
1918 case TargetLowering::Custom:
1919 Tmp1 = TLI.LowerOperation(Result, DAG);
1920 if (Tmp1.Val) Result = Tmp1;
1922 case TargetLowering::Legal: break;
1923 case TargetLowering::Expand:
1924 // If this target supports fabs/fneg natively, do this efficiently.
1925 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
1926 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
1927 // Get the sign bit of the RHS.
1928 MVT::ValueType IVT =
1929 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
1930 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
1931 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
1932 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
1933 // Get the absolute value of the result.
1934 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
1935 // Select between the nabs and abs value based on the sign bit of
1937 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
1938 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
1941 Result = LegalizeOp(Result);
1945 // Otherwise, do bitwise ops!
1947 // copysign -> copysignf/copysign libcall.
1949 if (Node->getValueType(0) == MVT::f32) {
1950 FnName = "copysignf";
1951 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
1952 Result = DAG.UpdateNodeOperands(Result, Tmp1,
1953 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
1955 FnName = "copysign";
1956 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
1957 Result = DAG.UpdateNodeOperands(Result, Tmp1,
1958 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
1961 Result = ExpandLibCall(FnName, Node, Dummy);
1968 Tmp1 = LegalizeOp(Node->getOperand(0));
1969 Tmp2 = LegalizeOp(Node->getOperand(1));
1970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1971 // Since this produces two values, make sure to remember that we legalized
1973 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1974 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1979 Tmp1 = LegalizeOp(Node->getOperand(0));
1980 Tmp2 = LegalizeOp(Node->getOperand(1));
1981 Tmp3 = LegalizeOp(Node->getOperand(2));
1982 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1983 // Since this produces two values, make sure to remember that we legalized
1985 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1986 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1989 case ISD::BUILD_PAIR: {
1990 MVT::ValueType PairTy = Node->getValueType(0);
1991 // TODO: handle the case where the Lo and Hi operands are not of legal type
1992 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1993 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1994 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1995 case TargetLowering::Promote:
1996 case TargetLowering::Custom:
1997 assert(0 && "Cannot promote/custom this yet!");
1998 case TargetLowering::Legal:
1999 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2000 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2002 case TargetLowering::Expand:
2003 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2004 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2005 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2006 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2007 TLI.getShiftAmountTy()));
2008 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2017 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2018 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2020 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2021 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2022 case TargetLowering::Custom:
2025 case TargetLowering::Legal:
2026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2028 Tmp1 = TLI.LowerOperation(Result, DAG);
2029 if (Tmp1.Val) Result = Tmp1;
2032 case TargetLowering::Expand:
2033 if (MVT::isInteger(Node->getValueType(0))) {
2035 MVT::ValueType VT = Node->getValueType(0);
2036 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2037 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2038 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2039 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2041 // Floating point mod -> fmod libcall.
2042 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2044 Result = ExpandLibCall(FnName, Node, Dummy);
2050 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2051 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2053 MVT::ValueType VT = Node->getValueType(0);
2054 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2055 default: assert(0 && "This action is not supported yet!");
2056 case TargetLowering::Custom:
2059 case TargetLowering::Legal:
2060 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2061 Result = Result.getValue(0);
2062 Tmp1 = Result.getValue(1);
2065 Tmp2 = TLI.LowerOperation(Result, DAG);
2067 Result = LegalizeOp(Tmp2);
2068 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2072 case TargetLowering::Expand: {
2073 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2074 Node->getOperand(2));
2075 // Increment the pointer, VAList, to the next vaarg
2076 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2077 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2078 TLI.getPointerTy()));
2079 // Store the incremented VAList to the legalized pointer
2080 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2081 Node->getOperand(2));
2082 // Load the actual argument out of the pointer VAList
2083 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2084 Tmp1 = LegalizeOp(Result.getValue(1));
2085 Result = LegalizeOp(Result);
2089 // Since VAARG produces two values, make sure to remember that we
2090 // legalized both of them.
2091 AddLegalizedOperand(SDOperand(Node, 0), Result);
2092 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2093 return Op.ResNo ? Tmp1 : Result;
2097 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2098 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2099 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2101 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2102 default: assert(0 && "This action is not supported yet!");
2103 case TargetLowering::Custom:
2106 case TargetLowering::Legal:
2107 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2108 Node->getOperand(3), Node->getOperand(4));
2110 Tmp1 = TLI.LowerOperation(Result, DAG);
2111 if (Tmp1.Val) Result = Tmp1;
2114 case TargetLowering::Expand:
2115 // This defaults to loading a pointer from the input and storing it to the
2116 // output, returning the chain.
2117 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2118 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2119 Node->getOperand(4));
2125 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2126 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2128 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2129 default: assert(0 && "This action is not supported yet!");
2130 case TargetLowering::Custom:
2133 case TargetLowering::Legal:
2134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2136 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2137 if (Tmp1.Val) Result = Tmp1;
2140 case TargetLowering::Expand:
2141 Result = Tmp1; // Default to a no-op, return the chain
2147 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2148 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2150 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2152 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2153 default: assert(0 && "This action is not supported yet!");
2154 case TargetLowering::Legal: break;
2155 case TargetLowering::Custom:
2156 Tmp1 = TLI.LowerOperation(Result, DAG);
2157 if (Tmp1.Val) Result = Tmp1;
2164 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2165 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2167 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2168 "Cannot handle this yet!");
2169 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2173 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2174 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2175 case TargetLowering::Custom:
2176 assert(0 && "Cannot custom legalize this yet!");
2177 case TargetLowering::Legal:
2178 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2180 case TargetLowering::Promote: {
2181 MVT::ValueType OVT = Tmp1.getValueType();
2182 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2183 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2185 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2186 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2187 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2188 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2191 case TargetLowering::Expand:
2192 Result = ExpandBSWAP(Tmp1);
2200 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2201 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2202 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2203 case TargetLowering::Legal:
2204 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2206 case TargetLowering::Promote: {
2207 MVT::ValueType OVT = Tmp1.getValueType();
2208 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2210 // Zero extend the argument.
2211 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2212 // Perform the larger operation, then subtract if needed.
2213 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2214 switch (Node->getOpcode()) {
2219 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2220 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2221 DAG.getConstant(getSizeInBits(NVT), NVT),
2223 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2224 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2227 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2228 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2229 DAG.getConstant(getSizeInBits(NVT) -
2230 getSizeInBits(OVT), NVT));
2235 case TargetLowering::Expand:
2236 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2247 Tmp1 = LegalizeOp(Node->getOperand(0));
2248 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2249 case TargetLowering::Promote:
2250 case TargetLowering::Custom:
2253 case TargetLowering::Legal:
2254 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2256 Tmp1 = TLI.LowerOperation(Result, DAG);
2257 if (Tmp1.Val) Result = Tmp1;
2260 case TargetLowering::Expand:
2261 switch (Node->getOpcode()) {
2262 default: assert(0 && "Unreachable!");
2264 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2265 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2266 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2269 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2270 MVT::ValueType VT = Node->getValueType(0);
2271 Tmp2 = DAG.getConstantFP(0.0, VT);
2272 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2273 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2274 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2280 MVT::ValueType VT = Node->getValueType(0);
2281 const char *FnName = 0;
2282 switch(Node->getOpcode()) {
2283 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2284 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2285 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2286 default: assert(0 && "Unreachable!");
2289 Result = ExpandLibCall(FnName, Node, Dummy);
2297 case ISD::BIT_CONVERT:
2298 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2299 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2301 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2302 Node->getOperand(0).getValueType())) {
2303 default: assert(0 && "Unknown operation action!");
2304 case TargetLowering::Expand:
2305 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2307 case TargetLowering::Legal:
2308 Tmp1 = LegalizeOp(Node->getOperand(0));
2309 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2314 // Conversion operators. The source and destination have different types.
2315 case ISD::SINT_TO_FP:
2316 case ISD::UINT_TO_FP: {
2317 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2318 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2320 switch (TLI.getOperationAction(Node->getOpcode(),
2321 Node->getOperand(0).getValueType())) {
2322 default: assert(0 && "Unknown operation action!");
2323 case TargetLowering::Custom:
2326 case TargetLowering::Legal:
2327 Tmp1 = LegalizeOp(Node->getOperand(0));
2328 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2330 Tmp1 = TLI.LowerOperation(Result, DAG);
2331 if (Tmp1.Val) Result = Tmp1;
2334 case TargetLowering::Expand:
2335 Result = ExpandLegalINT_TO_FP(isSigned,
2336 LegalizeOp(Node->getOperand(0)),
2337 Node->getValueType(0));
2339 case TargetLowering::Promote:
2340 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2341 Node->getValueType(0),
2347 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2348 Node->getValueType(0), Node->getOperand(0));
2351 Tmp1 = PromoteOp(Node->getOperand(0));
2353 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2354 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2356 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2357 Node->getOperand(0).getValueType());
2359 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2360 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2366 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2368 Tmp1 = LegalizeOp(Node->getOperand(0));
2369 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2372 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2374 // Since the result is legal, we should just be able to truncate the low
2375 // part of the source.
2376 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2379 Result = PromoteOp(Node->getOperand(0));
2380 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2385 case ISD::FP_TO_SINT:
2386 case ISD::FP_TO_UINT:
2387 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2389 Tmp1 = LegalizeOp(Node->getOperand(0));
2391 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2392 default: assert(0 && "Unknown operation action!");
2393 case TargetLowering::Custom:
2396 case TargetLowering::Legal:
2397 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2399 Tmp1 = TLI.LowerOperation(Result, DAG);
2400 if (Tmp1.Val) Result = Tmp1;
2403 case TargetLowering::Promote:
2404 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2405 Node->getOpcode() == ISD::FP_TO_SINT);
2407 case TargetLowering::Expand:
2408 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2409 SDOperand True, False;
2410 MVT::ValueType VT = Node->getOperand(0).getValueType();
2411 MVT::ValueType NVT = Node->getValueType(0);
2412 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2413 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2414 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2415 Node->getOperand(0), Tmp2, ISD::SETLT);
2416 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2417 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2418 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2420 False = DAG.getNode(ISD::XOR, NVT, False,
2421 DAG.getConstant(1ULL << ShiftAmt, NVT));
2422 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2425 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2431 assert(0 && "Shouldn't need to expand other operators here!");
2433 Tmp1 = PromoteOp(Node->getOperand(0));
2434 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2435 Result = LegalizeOp(Result);
2440 case ISD::ANY_EXTEND:
2441 case ISD::ZERO_EXTEND:
2442 case ISD::SIGN_EXTEND:
2443 case ISD::FP_EXTEND:
2445 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2446 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2448 Tmp1 = LegalizeOp(Node->getOperand(0));
2449 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2452 switch (Node->getOpcode()) {
2453 case ISD::ANY_EXTEND:
2454 Tmp1 = PromoteOp(Node->getOperand(0));
2455 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2457 case ISD::ZERO_EXTEND:
2458 Result = PromoteOp(Node->getOperand(0));
2459 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2460 Result = DAG.getZeroExtendInReg(Result,
2461 Node->getOperand(0).getValueType());
2463 case ISD::SIGN_EXTEND:
2464 Result = PromoteOp(Node->getOperand(0));
2465 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2466 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2468 DAG.getValueType(Node->getOperand(0).getValueType()));
2470 case ISD::FP_EXTEND:
2471 Result = PromoteOp(Node->getOperand(0));
2472 if (Result.getValueType() != Op.getValueType())
2473 // Dynamically dead while we have only 2 FP types.
2474 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2477 Result = PromoteOp(Node->getOperand(0));
2478 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2483 case ISD::FP_ROUND_INREG:
2484 case ISD::SIGN_EXTEND_INREG: {
2485 Tmp1 = LegalizeOp(Node->getOperand(0));
2486 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2488 // If this operation is not supported, convert it to a shl/shr or load/store
2490 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2491 default: assert(0 && "This action not supported for this op yet!");
2492 case TargetLowering::Legal:
2493 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2495 case TargetLowering::Expand:
2496 // If this is an integer extend and shifts are supported, do that.
2497 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2498 // NOTE: we could fall back on load/store here too for targets without
2499 // SAR. However, it is doubtful that any exist.
2500 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2501 MVT::getSizeInBits(ExtraVT);
2502 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2503 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2504 Node->getOperand(0), ShiftCst);
2505 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2507 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2508 // The only way we can lower this is to turn it into a STORETRUNC,
2509 // EXTLOAD pair, targetting a temporary location (a stack slot).
2511 // NOTE: there is a choice here between constantly creating new stack
2512 // slots and always reusing the same one. We currently always create
2513 // new ones, as reuse may inhibit scheduling.
2514 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2515 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2516 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2517 MachineFunction &MF = DAG.getMachineFunction();
2519 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2520 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2521 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2522 Node->getOperand(0), StackSlot,
2523 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2524 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2525 Result, StackSlot, DAG.getSrcValue(NULL),
2528 assert(0 && "Unknown op");
2536 // Make sure that the generated code is itself legal.
2538 Result = LegalizeOp(Result);
2540 // Note that LegalizeOp may be reentered even from single-use nodes, which
2541 // means that we always must cache transformed nodes.
2542 AddLegalizedOperand(Op, Result);
2546 /// PromoteOp - Given an operation that produces a value in an invalid type,
2547 /// promote it to compute the value into a larger type. The produced value will
2548 /// have the correct bits for the low portion of the register, but no guarantee
2549 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2550 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2551 MVT::ValueType VT = Op.getValueType();
2552 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2553 assert(getTypeAction(VT) == Promote &&
2554 "Caller should expand or legalize operands that are not promotable!");
2555 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2556 "Cannot promote to smaller type!");
2558 SDOperand Tmp1, Tmp2, Tmp3;
2560 SDNode *Node = Op.Val;
2562 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2563 if (I != PromotedNodes.end()) return I->second;
2565 switch (Node->getOpcode()) {
2566 case ISD::CopyFromReg:
2567 assert(0 && "CopyFromReg must be legal!");
2569 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2570 assert(0 && "Do not know how to promote this operator!");
2573 Result = DAG.getNode(ISD::UNDEF, NVT);
2577 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2579 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2580 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2582 case ISD::ConstantFP:
2583 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2584 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2588 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2589 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2590 Node->getOperand(1), Node->getOperand(2));
2594 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2596 Result = LegalizeOp(Node->getOperand(0));
2597 assert(Result.getValueType() >= NVT &&
2598 "This truncation doesn't make sense!");
2599 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2600 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2603 // The truncation is not required, because we don't guarantee anything
2604 // about high bits anyway.
2605 Result = PromoteOp(Node->getOperand(0));
2608 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2609 // Truncate the low part of the expanded value to the result type
2610 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2613 case ISD::SIGN_EXTEND:
2614 case ISD::ZERO_EXTEND:
2615 case ISD::ANY_EXTEND:
2616 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2617 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2619 // Input is legal? Just do extend all the way to the larger type.
2620 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2623 // Promote the reg if it's smaller.
2624 Result = PromoteOp(Node->getOperand(0));
2625 // The high bits are not guaranteed to be anything. Insert an extend.
2626 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2627 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2628 DAG.getValueType(Node->getOperand(0).getValueType()));
2629 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2630 Result = DAG.getZeroExtendInReg(Result,
2631 Node->getOperand(0).getValueType());
2635 case ISD::BIT_CONVERT:
2636 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2637 Result = PromoteOp(Result);
2640 case ISD::FP_EXTEND:
2641 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2643 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2644 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2645 case Promote: assert(0 && "Unreachable with 2 FP types!");
2647 // Input is legal? Do an FP_ROUND_INREG.
2648 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2649 DAG.getValueType(VT));
2654 case ISD::SINT_TO_FP:
2655 case ISD::UINT_TO_FP:
2656 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2658 // No extra round required here.
2659 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2663 Result = PromoteOp(Node->getOperand(0));
2664 if (Node->getOpcode() == ISD::SINT_TO_FP)
2665 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2667 DAG.getValueType(Node->getOperand(0).getValueType()));
2669 Result = DAG.getZeroExtendInReg(Result,
2670 Node->getOperand(0).getValueType());
2671 // No extra round required here.
2672 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2675 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2676 Node->getOperand(0));
2677 // Round if we cannot tolerate excess precision.
2678 if (NoExcessFPPrecision)
2679 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2680 DAG.getValueType(VT));
2685 case ISD::SIGN_EXTEND_INREG:
2686 Result = PromoteOp(Node->getOperand(0));
2687 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2688 Node->getOperand(1));
2690 case ISD::FP_TO_SINT:
2691 case ISD::FP_TO_UINT:
2692 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2694 Tmp1 = Node->getOperand(0);
2697 // The input result is prerounded, so we don't have to do anything
2699 Tmp1 = PromoteOp(Node->getOperand(0));
2702 assert(0 && "not implemented");
2704 // If we're promoting a UINT to a larger size, check to see if the new node
2705 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2706 // we can use that instead. This allows us to generate better code for
2707 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2708 // legal, such as PowerPC.
2709 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2710 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2711 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2712 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2713 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2715 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2721 Tmp1 = PromoteOp(Node->getOperand(0));
2722 assert(Tmp1.getValueType() == NVT);
2723 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2724 // NOTE: we do not have to do any extra rounding here for
2725 // NoExcessFPPrecision, because we know the input will have the appropriate
2726 // precision, and these operations don't modify precision at all.
2732 Tmp1 = PromoteOp(Node->getOperand(0));
2733 assert(Tmp1.getValueType() == NVT);
2734 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2735 if (NoExcessFPPrecision)
2736 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2737 DAG.getValueType(VT));
2746 // The input may have strange things in the top bits of the registers, but
2747 // these operations don't care. They may have weird bits going out, but
2748 // that too is okay if they are integer operations.
2749 Tmp1 = PromoteOp(Node->getOperand(0));
2750 Tmp2 = PromoteOp(Node->getOperand(1));
2751 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2752 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2757 Tmp1 = PromoteOp(Node->getOperand(0));
2758 Tmp2 = PromoteOp(Node->getOperand(1));
2759 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2760 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2762 // Floating point operations will give excess precision that we may not be
2763 // able to tolerate. If we DO allow excess precision, just leave it,
2764 // otherwise excise it.
2765 // FIXME: Why would we need to round FP ops more than integer ones?
2766 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2767 if (NoExcessFPPrecision)
2768 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2769 DAG.getValueType(VT));
2774 // These operators require that their input be sign extended.
2775 Tmp1 = PromoteOp(Node->getOperand(0));
2776 Tmp2 = PromoteOp(Node->getOperand(1));
2777 if (MVT::isInteger(NVT)) {
2778 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2779 DAG.getValueType(VT));
2780 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2781 DAG.getValueType(VT));
2783 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2785 // Perform FP_ROUND: this is probably overly pessimistic.
2786 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2787 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2788 DAG.getValueType(VT));
2792 case ISD::FCOPYSIGN:
2793 // These operators require that their input be fp extended.
2794 Tmp1 = PromoteOp(Node->getOperand(0));
2795 Tmp2 = PromoteOp(Node->getOperand(1));
2796 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2798 // Perform FP_ROUND: this is probably overly pessimistic.
2799 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
2800 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2801 DAG.getValueType(VT));
2806 // These operators require that their input be zero extended.
2807 Tmp1 = PromoteOp(Node->getOperand(0));
2808 Tmp2 = PromoteOp(Node->getOperand(1));
2809 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2810 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2811 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2812 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2816 Tmp1 = PromoteOp(Node->getOperand(0));
2817 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
2820 // The input value must be properly sign extended.
2821 Tmp1 = PromoteOp(Node->getOperand(0));
2822 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2823 DAG.getValueType(VT));
2824 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
2827 // The input value must be properly zero extended.
2828 Tmp1 = PromoteOp(Node->getOperand(0));
2829 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2830 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
2834 Tmp1 = Node->getOperand(0); // Get the chain.
2835 Tmp2 = Node->getOperand(1); // Get the pointer.
2836 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
2837 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
2838 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
2840 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2841 Node->getOperand(2));
2842 // Increment the pointer, VAList, to the next vaarg
2843 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2844 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2845 TLI.getPointerTy()));
2846 // Store the incremented VAList to the legalized pointer
2847 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2848 Node->getOperand(2));
2849 // Load the actual argument out of the pointer VAList
2850 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
2851 DAG.getSrcValue(0), VT);
2853 // Remember that we legalized the chain.
2854 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2858 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
2859 Node->getOperand(1), Node->getOperand(2), VT);
2860 // Remember that we legalized the chain.
2861 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2866 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
2867 Node->getOperand(1), Node->getOperand(2),
2868 cast<VTSDNode>(Node->getOperand(3))->getVT());
2869 // Remember that we legalized the chain.
2870 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2873 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2874 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2875 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
2877 case ISD::SELECT_CC:
2878 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2879 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2880 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2881 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
2884 Tmp1 = Node->getOperand(0);
2885 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2886 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2887 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2888 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
2889 TLI.getShiftAmountTy()));
2894 // Zero extend the argument
2895 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
2896 // Perform the larger operation, then subtract if needed.
2897 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2898 switch(Node->getOpcode()) {
2903 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2904 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2905 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2906 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2907 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
2910 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2911 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2912 DAG.getConstant(getSizeInBits(NVT) -
2913 getSizeInBits(VT), NVT));
2919 assert(Result.Val && "Didn't set a result!");
2921 // Make sure the result is itself legal.
2922 Result = LegalizeOp(Result);
2924 // Remember that we promoted this!
2925 AddPromotedOperand(Op, Result);
2929 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
2930 /// with condition CC on the current target. This usually involves legalizing
2931 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
2932 /// there may be no choice but to create a new SetCC node to represent the
2933 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
2934 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
2935 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
2938 SDOperand Tmp1, Tmp2, Result;
2940 switch (getTypeAction(LHS.getValueType())) {
2942 Tmp1 = LegalizeOp(LHS); // LHS
2943 Tmp2 = LegalizeOp(RHS); // RHS
2946 Tmp1 = PromoteOp(LHS); // LHS
2947 Tmp2 = PromoteOp(RHS); // RHS
2949 // If this is an FP compare, the operands have already been extended.
2950 if (MVT::isInteger(LHS.getValueType())) {
2951 MVT::ValueType VT = LHS.getValueType();
2952 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2954 // Otherwise, we have to insert explicit sign or zero extends. Note
2955 // that we could insert sign extends for ALL conditions, but zero extend
2956 // is cheaper on many machines (an AND instead of two shifts), so prefer
2958 switch (cast<CondCodeSDNode>(CC)->get()) {
2959 default: assert(0 && "Unknown integer comparison!");
2966 // ALL of these operations will work if we either sign or zero extend
2967 // the operands (including the unsigned comparisons!). Zero extend is
2968 // usually a simpler/cheaper operation, so prefer it.
2969 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2970 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2976 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2977 DAG.getValueType(VT));
2978 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2979 DAG.getValueType(VT));
2985 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
2986 ExpandOp(LHS, LHSLo, LHSHi);
2987 ExpandOp(RHS, RHSLo, RHSHi);
2988 switch (cast<CondCodeSDNode>(CC)->get()) {
2992 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
2993 if (RHSCST->isAllOnesValue()) {
2994 // Comparison to -1.
2995 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3000 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3001 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3002 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3003 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3006 // If this is a comparison of the sign bit, just look at the top part.
3008 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3009 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3010 CST->getValue() == 0) || // X < 0
3011 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3012 CST->isAllOnesValue())) { // X > -1
3018 // FIXME: This generated code sucks.
3019 ISD::CondCode LowCC;
3020 switch (cast<CondCodeSDNode>(CC)->get()) {
3021 default: assert(0 && "Unknown integer setcc!");
3023 case ISD::SETULT: LowCC = ISD::SETULT; break;
3025 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3027 case ISD::SETULE: LowCC = ISD::SETULE; break;
3029 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3032 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3033 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3034 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3036 // NOTE: on targets without efficient SELECT of bools, we can always use
3037 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3038 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3039 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3040 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3041 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3042 Result, Tmp1, Tmp2));
3051 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3052 /// The resultant code need not be legal. Note that SrcOp is the input operand
3053 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3054 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3056 // Create the stack frame object.
3057 SDOperand FIPtr = CreateStackTemporary(DestVT);
3059 // Emit a store to the stack slot.
3060 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3061 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3062 // Result is a load from the stack slot.
3063 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3066 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3067 /// support the operation, but do support the resultant packed vector type.
3068 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3070 // If the only non-undef value is the low element, turn this into a
3071 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3072 bool isOnlyLowElement = true;
3073 SDOperand SplatValue = Node->getOperand(0);
3074 for (SDNode::op_iterator I = Node->op_begin()+1, E = Node->op_end();
3076 if (I->getOpcode() != ISD::UNDEF)
3077 isOnlyLowElement = false;
3078 if (SplatValue != *I)
3079 SplatValue = SDOperand(0,0);
3082 if (isOnlyLowElement) {
3083 // If the low element is an undef too, then this whole things is an undef.
3084 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3085 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3086 // Otherwise, turn this into a scalar_to_vector node.
3087 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3088 Node->getOperand(0));
3091 if (SplatValue.Val) { // Splat of one value?
3092 // Build the shuffle constant vector: <0, 0, 0, 0>
3093 MVT::ValueType MaskVT =
3094 MVT::getIntVectorWithNumElements(Node->getNumOperands());
3095 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3096 std::vector<SDOperand> ZeroVec(Node->getNumOperands(), Zero);
3097 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
3099 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3100 if (TLI.isShuffleLegal(Node->getValueType(0), SplatMask)) {
3101 // Get the splatted value into the low element of a vector register.
3102 SDOperand LowValVec =
3103 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3105 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3106 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3107 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3112 // If the elements are all constants, turn this into a load from the constant
3114 bool isConstant = true;
3115 for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
3117 if (!isa<ConstantFPSDNode>(I) && !isa<ConstantSDNode>(I) &&
3118 I->getOpcode() != ISD::UNDEF) {
3124 // Create a ConstantPacked, and put it in the constant pool.
3126 MVT::ValueType VT = Node->getValueType(0);
3128 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3129 std::vector<Constant*> CV;
3130 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3131 if (ConstantFPSDNode *V =
3132 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3133 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3134 } else if (ConstantSDNode *V =
3135 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3136 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3138 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3139 CV.push_back(UndefValue::get(OpNTy));
3142 Constant *CP = ConstantPacked::get(CV);
3143 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3144 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3145 DAG.getSrcValue(NULL));
3148 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3149 // aligned object on the stack, store each element into it, then load
3150 // the result as a vector.
3151 MVT::ValueType VT = Node->getValueType(0);
3152 // Create the stack frame object.
3153 SDOperand FIPtr = CreateStackTemporary(VT);
3155 // Emit a store of each element to the stack slot.
3156 std::vector<SDOperand> Stores;
3157 bool isLittleEndian = TLI.isLittleEndian();
3158 unsigned TypeByteSize =
3159 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3160 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3161 // Store (in the right endianness) the elements to memory.
3162 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3163 // Ignore undef elements.
3164 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3168 Offset = TypeByteSize*i;
3170 Offset = TypeByteSize*(e-i-1);
3172 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3173 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3175 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3176 Node->getOperand(i), Idx,
3177 DAG.getSrcValue(NULL)));
3180 SDOperand StoreChain;
3181 if (!Stores.empty()) // Not all undef elements?
3182 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
3184 StoreChain = DAG.getEntryNode();
3186 // Result is a load from the stack slot.
3187 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3190 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3191 /// specified value type.
3192 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3193 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3194 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3195 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3196 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3199 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3200 SDOperand Op, SDOperand Amt,
3201 SDOperand &Lo, SDOperand &Hi) {
3202 // Expand the subcomponents.
3203 SDOperand LHSL, LHSH;
3204 ExpandOp(Op, LHSL, LHSH);
3206 std::vector<SDOperand> Ops;
3207 Ops.push_back(LHSL);
3208 Ops.push_back(LHSH);
3210 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3211 Lo = DAG.getNode(NodeOp, VTs, Ops);
3212 Hi = Lo.getValue(1);
3216 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3217 /// smaller elements. If we can't find a way that is more efficient than a
3218 /// libcall on this target, return false. Otherwise, return true with the
3219 /// low-parts expanded into Lo and Hi.
3220 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3221 SDOperand &Lo, SDOperand &Hi) {
3222 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3223 "This is not a shift!");
3225 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3226 SDOperand ShAmt = LegalizeOp(Amt);
3227 MVT::ValueType ShTy = ShAmt.getValueType();
3228 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3229 unsigned NVTBits = MVT::getSizeInBits(NVT);
3231 // Handle the case when Amt is an immediate. Other cases are currently broken
3232 // and are disabled.
3233 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3234 unsigned Cst = CN->getValue();
3235 // Expand the incoming operand to be shifted, so that we have its parts
3237 ExpandOp(Op, InL, InH);
3241 Lo = DAG.getConstant(0, NVT);
3242 Hi = DAG.getConstant(0, NVT);
3243 } else if (Cst > NVTBits) {
3244 Lo = DAG.getConstant(0, NVT);
3245 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3246 } else if (Cst == NVTBits) {
3247 Lo = DAG.getConstant(0, NVT);
3250 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3251 Hi = DAG.getNode(ISD::OR, NVT,
3252 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3253 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3258 Lo = DAG.getConstant(0, NVT);
3259 Hi = DAG.getConstant(0, NVT);
3260 } else if (Cst > NVTBits) {
3261 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3262 Hi = DAG.getConstant(0, NVT);
3263 } else if (Cst == NVTBits) {
3265 Hi = DAG.getConstant(0, NVT);
3267 Lo = DAG.getNode(ISD::OR, NVT,
3268 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3269 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3270 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3275 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3276 DAG.getConstant(NVTBits-1, ShTy));
3277 } else if (Cst > NVTBits) {
3278 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3279 DAG.getConstant(Cst-NVTBits, ShTy));
3280 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3281 DAG.getConstant(NVTBits-1, ShTy));
3282 } else if (Cst == NVTBits) {
3284 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3285 DAG.getConstant(NVTBits-1, ShTy));
3287 Lo = DAG.getNode(ISD::OR, NVT,
3288 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3289 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3290 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3299 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3300 // does not fit into a register, return the lo part and set the hi part to the
3301 // by-reg argument. If it does fit into a single register, return the result
3302 // and leave the Hi part unset.
3303 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3305 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3306 // The input chain to this libcall is the entry node of the function.
3307 // Legalizing the call will automatically add the previous call to the
3309 SDOperand InChain = DAG.getEntryNode();
3311 TargetLowering::ArgListTy Args;
3312 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3313 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3314 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3315 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3317 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3319 // Splice the libcall in wherever FindInputOutputChains tells us to.
3320 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3321 std::pair<SDOperand,SDOperand> CallInfo =
3322 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3325 // Legalize the call sequence, starting with the chain. This will advance
3326 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3327 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3328 LegalizeOp(CallInfo.second);
3330 switch (getTypeAction(CallInfo.first.getValueType())) {
3331 default: assert(0 && "Unknown thing");
3333 Result = CallInfo.first;
3336 ExpandOp(CallInfo.first, Result, Hi);
3343 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3344 /// destination type is legal.
3345 SDOperand SelectionDAGLegalize::
3346 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3347 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3348 assert(getTypeAction(Source.getValueType()) == Expand &&
3349 "This is not an expansion!");
3350 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3353 assert(Source.getValueType() == MVT::i64 &&
3354 "This only works for 64-bit -> FP");
3355 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3356 // incoming integer is set. To handle this, we dynamically test to see if
3357 // it is set, and, if so, add a fudge factor.
3359 ExpandOp(Source, Lo, Hi);
3361 // If this is unsigned, and not supported, first perform the conversion to
3362 // signed, then adjust the result if the sign bit is set.
3363 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3364 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3366 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3367 DAG.getConstant(0, Hi.getValueType()),
3369 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3370 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3371 SignSet, Four, Zero);
3372 uint64_t FF = 0x5f800000ULL;
3373 if (TLI.isLittleEndian()) FF <<= 32;
3374 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3376 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3377 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3378 SDOperand FudgeInReg;
3379 if (DestTy == MVT::f32)
3380 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3381 DAG.getSrcValue(NULL));
3383 assert(DestTy == MVT::f64 && "Unexpected conversion");
3384 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3385 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3387 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3390 // Check to see if the target has a custom way to lower this. If so, use it.
3391 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3392 default: assert(0 && "This action not implemented for this operation!");
3393 case TargetLowering::Legal:
3394 case TargetLowering::Expand:
3395 break; // This case is handled below.
3396 case TargetLowering::Custom: {
3397 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3400 return LegalizeOp(NV);
3401 break; // The target decided this was legal after all
3405 // Expand the source, then glue it back together for the call. We must expand
3406 // the source in case it is shared (this pass of legalize must traverse it).
3407 SDOperand SrcLo, SrcHi;
3408 ExpandOp(Source, SrcLo, SrcHi);
3409 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3411 const char *FnName = 0;
3412 if (DestTy == MVT::f32)
3413 FnName = "__floatdisf";
3415 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3416 FnName = "__floatdidf";
3419 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3420 SDOperand UnusedHiPart;
3421 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3424 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3425 /// INT_TO_FP operation of the specified operand when the target requests that
3426 /// we expand it. At this point, we know that the result and operand types are
3427 /// legal for the target.
3428 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3430 MVT::ValueType DestVT) {
3431 if (Op0.getValueType() == MVT::i32) {
3432 // simple 32-bit [signed|unsigned] integer to float/double expansion
3434 // get the stack frame index of a 8 byte buffer
3435 MachineFunction &MF = DAG.getMachineFunction();
3436 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3437 // get address of 8 byte buffer
3438 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3439 // word offset constant for Hi/Lo address computation
3440 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3441 // set up Hi and Lo (into buffer) address based on endian
3443 if (TLI.isLittleEndian()) {
3444 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
3448 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
3450 // if signed map to unsigned space
3451 SDOperand Op0Mapped;
3453 // constant used to invert sign bit (signed to unsigned mapping)
3454 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3455 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3459 // store the lo of the constructed double - based on integer input
3460 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3461 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3462 // initial hi portion of constructed double
3463 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3464 // store the hi of the constructed double - biased exponent
3465 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3466 InitialHi, Hi, DAG.getSrcValue(NULL));
3467 // load the constructed double
3468 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3469 DAG.getSrcValue(NULL));
3470 // FP constant to bias correct the final result
3471 SDOperand Bias = DAG.getConstantFP(isSigned ?
3472 BitsToDouble(0x4330000080000000ULL)
3473 : BitsToDouble(0x4330000000000000ULL),
3475 // subtract the bias
3476 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3479 // handle final rounding
3480 if (DestVT == MVT::f64) {
3484 // if f32 then cast to f32
3485 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3489 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3490 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3492 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3493 DAG.getConstant(0, Op0.getValueType()),
3495 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3496 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3497 SignSet, Four, Zero);
3499 // If the sign bit of the integer is set, the large number will be treated
3500 // as a negative number. To counteract this, the dynamic code adds an
3501 // offset depending on the data type.
3503 switch (Op0.getValueType()) {
3504 default: assert(0 && "Unsupported integer type!");
3505 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3506 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3507 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3508 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3510 if (TLI.isLittleEndian()) FF <<= 32;
3511 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3513 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3514 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3515 SDOperand FudgeInReg;
3516 if (DestVT == MVT::f32)
3517 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3518 DAG.getSrcValue(NULL));
3520 assert(DestVT == MVT::f64 && "Unexpected conversion");
3521 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3522 DAG.getEntryNode(), CPIdx,
3523 DAG.getSrcValue(NULL), MVT::f32));
3526 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3529 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3530 /// *INT_TO_FP operation of the specified operand when the target requests that
3531 /// we promote it. At this point, we know that the result and operand types are
3532 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3533 /// operation that takes a larger input.
3534 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3535 MVT::ValueType DestVT,
3537 // First step, figure out the appropriate *INT_TO_FP operation to use.
3538 MVT::ValueType NewInTy = LegalOp.getValueType();
3540 unsigned OpToUse = 0;
3542 // Scan for the appropriate larger type to use.
3544 NewInTy = (MVT::ValueType)(NewInTy+1);
3545 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
3547 // If the target supports SINT_TO_FP of this type, use it.
3548 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
3550 case TargetLowering::Legal:
3551 if (!TLI.isTypeLegal(NewInTy))
3552 break; // Can't use this datatype.
3554 case TargetLowering::Custom:
3555 OpToUse = ISD::SINT_TO_FP;
3559 if (isSigned) continue;
3561 // If the target supports UINT_TO_FP of this type, use it.
3562 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
3564 case TargetLowering::Legal:
3565 if (!TLI.isTypeLegal(NewInTy))
3566 break; // Can't use this datatype.
3568 case TargetLowering::Custom:
3569 OpToUse = ISD::UINT_TO_FP;
3574 // Otherwise, try a larger type.
3577 // Okay, we found the operation and type to use. Zero extend our input to the
3578 // desired type then run the operation on it.
3579 return DAG.getNode(OpToUse, DestVT,
3580 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3584 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
3585 /// FP_TO_*INT operation of the specified operand when the target requests that
3586 /// we promote it. At this point, we know that the result and operand types are
3587 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
3588 /// operation that returns a larger result.
3589 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
3590 MVT::ValueType DestVT,
3592 // First step, figure out the appropriate FP_TO*INT operation to use.
3593 MVT::ValueType NewOutTy = DestVT;
3595 unsigned OpToUse = 0;
3597 // Scan for the appropriate larger type to use.
3599 NewOutTy = (MVT::ValueType)(NewOutTy+1);
3600 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
3602 // If the target supports FP_TO_SINT returning this type, use it.
3603 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
3605 case TargetLowering::Legal:
3606 if (!TLI.isTypeLegal(NewOutTy))
3607 break; // Can't use this datatype.
3609 case TargetLowering::Custom:
3610 OpToUse = ISD::FP_TO_SINT;
3615 // If the target supports FP_TO_UINT of this type, use it.
3616 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
3618 case TargetLowering::Legal:
3619 if (!TLI.isTypeLegal(NewOutTy))
3620 break; // Can't use this datatype.
3622 case TargetLowering::Custom:
3623 OpToUse = ISD::FP_TO_UINT;
3628 // Otherwise, try a larger type.
3631 // Okay, we found the operation and type to use. Truncate the result of the
3632 // extended FP_TO_*INT operation to the desired size.
3633 return DAG.getNode(ISD::TRUNCATE, DestVT,
3634 DAG.getNode(OpToUse, NewOutTy, LegalOp));
3637 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
3639 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
3640 MVT::ValueType VT = Op.getValueType();
3641 MVT::ValueType SHVT = TLI.getShiftAmountTy();
3642 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
3644 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
3646 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3647 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3648 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
3650 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
3651 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3652 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3653 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
3654 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
3655 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
3656 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
3657 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
3658 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
3660 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
3661 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
3662 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
3663 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3664 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3665 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
3666 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
3667 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
3668 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
3669 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
3670 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
3671 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
3672 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
3673 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
3674 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
3675 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
3676 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
3677 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
3678 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
3679 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
3680 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
3684 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
3686 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
3688 default: assert(0 && "Cannot expand this yet!");
3690 static const uint64_t mask[6] = {
3691 0x5555555555555555ULL, 0x3333333333333333ULL,
3692 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
3693 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
3695 MVT::ValueType VT = Op.getValueType();
3696 MVT::ValueType ShVT = TLI.getShiftAmountTy();
3697 unsigned len = getSizeInBits(VT);
3698 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
3699 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
3700 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
3701 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
3702 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
3703 DAG.getNode(ISD::AND, VT,
3704 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
3709 // for now, we do this:
3710 // x = x | (x >> 1);
3711 // x = x | (x >> 2);
3713 // x = x | (x >>16);
3714 // x = x | (x >>32); // for 64-bit input
3715 // return popcount(~x);
3717 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
3718 MVT::ValueType VT = Op.getValueType();
3719 MVT::ValueType ShVT = TLI.getShiftAmountTy();
3720 unsigned len = getSizeInBits(VT);
3721 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
3722 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
3723 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
3725 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
3726 return DAG.getNode(ISD::CTPOP, VT, Op);
3729 // for now, we use: { return popcount(~x & (x - 1)); }
3730 // unless the target has ctlz but not ctpop, in which case we use:
3731 // { return 32 - nlz(~x & (x-1)); }
3732 // see also http://www.hackersdelight.org/HDcode/ntz.cc
3733 MVT::ValueType VT = Op.getValueType();
3734 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
3735 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
3736 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
3737 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
3738 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
3739 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
3740 TLI.isOperationLegal(ISD::CTLZ, VT))
3741 return DAG.getNode(ISD::SUB, VT,
3742 DAG.getConstant(getSizeInBits(VT), VT),
3743 DAG.getNode(ISD::CTLZ, VT, Tmp3));
3744 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
3750 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3751 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3752 /// LegalizeNodes map is filled in for any results that are not expanded, the
3753 /// ExpandedNodes map is filled in for any results that are expanded, and the
3754 /// Lo/Hi values are returned.
3755 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3756 MVT::ValueType VT = Op.getValueType();
3757 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3758 SDNode *Node = Op.Val;
3759 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3760 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3761 "Cannot expand FP values!");
3762 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3763 "Cannot expand to FP value or to larger int value!");
3765 // See if we already expanded it.
3766 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3767 = ExpandedNodes.find(Op);
3768 if (I != ExpandedNodes.end()) {
3769 Lo = I->second.first;
3770 Hi = I->second.second;
3774 switch (Node->getOpcode()) {
3775 case ISD::CopyFromReg:
3776 assert(0 && "CopyFromReg must be legal!");
3778 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3779 assert(0 && "Do not know how to expand this operator!");
3782 Lo = DAG.getNode(ISD::UNDEF, NVT);
3783 Hi = DAG.getNode(ISD::UNDEF, NVT);
3785 case ISD::Constant: {
3786 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3787 Lo = DAG.getConstant(Cst, NVT);
3788 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3791 case ISD::BUILD_PAIR:
3792 // Return the operands.
3793 Lo = Node->getOperand(0);
3794 Hi = Node->getOperand(1);
3797 case ISD::SIGN_EXTEND_INREG:
3798 ExpandOp(Node->getOperand(0), Lo, Hi);
3799 // Sign extend the lo-part.
3800 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3801 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3802 TLI.getShiftAmountTy()));
3803 // sext_inreg the low part if needed.
3804 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3808 ExpandOp(Node->getOperand(0), Lo, Hi);
3809 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
3810 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
3816 ExpandOp(Node->getOperand(0), Lo, Hi);
3817 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3818 DAG.getNode(ISD::CTPOP, NVT, Lo),
3819 DAG.getNode(ISD::CTPOP, NVT, Hi));
3820 Hi = DAG.getConstant(0, NVT);
3824 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3825 ExpandOp(Node->getOperand(0), Lo, Hi);
3826 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3827 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3828 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3830 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3831 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3833 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3834 Hi = DAG.getConstant(0, NVT);
3839 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3840 ExpandOp(Node->getOperand(0), Lo, Hi);
3841 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3842 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3843 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3845 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3846 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3848 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3849 Hi = DAG.getConstant(0, NVT);
3854 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
3855 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
3856 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
3857 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
3859 // Remember that we legalized the chain.
3860 Hi = LegalizeOp(Hi);
3861 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
3862 if (!TLI.isLittleEndian())
3868 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
3869 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
3870 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3872 // Increment the pointer to the other half.
3873 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3874 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3875 getIntPtrConstant(IncrementSize));
3876 // FIXME: This creates a bogus srcvalue!
3877 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3879 // Build a factor node to remember that this load is independent of the
3881 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3884 // Remember that we legalized the chain.
3885 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
3886 if (!TLI.isLittleEndian())
3892 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3893 SDOperand LL, LH, RL, RH;
3894 ExpandOp(Node->getOperand(0), LL, LH);
3895 ExpandOp(Node->getOperand(1), RL, RH);
3896 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3897 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3901 SDOperand LL, LH, RL, RH;
3902 ExpandOp(Node->getOperand(1), LL, LH);
3903 ExpandOp(Node->getOperand(2), RL, RH);
3904 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
3905 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
3908 case ISD::SELECT_CC: {
3909 SDOperand TL, TH, FL, FH;
3910 ExpandOp(Node->getOperand(2), TL, TH);
3911 ExpandOp(Node->getOperand(3), FL, FH);
3912 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3913 Node->getOperand(1), TL, FL, Node->getOperand(4));
3914 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3915 Node->getOperand(1), TH, FH, Node->getOperand(4));
3918 case ISD::SEXTLOAD: {
3919 SDOperand Chain = Node->getOperand(0);
3920 SDOperand Ptr = Node->getOperand(1);
3921 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3924 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3926 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3929 // Remember that we legalized the chain.
3930 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3932 // The high part is obtained by SRA'ing all but one of the bits of the lo
3934 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3935 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3936 TLI.getShiftAmountTy()));
3939 case ISD::ZEXTLOAD: {
3940 SDOperand Chain = Node->getOperand(0);
3941 SDOperand Ptr = Node->getOperand(1);
3942 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3945 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3947 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3950 // Remember that we legalized the chain.
3951 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3953 // The high part is just a zero.
3954 Hi = DAG.getConstant(0, NVT);
3957 case ISD::EXTLOAD: {
3958 SDOperand Chain = Node->getOperand(0);
3959 SDOperand Ptr = Node->getOperand(1);
3960 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3963 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3965 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3968 // Remember that we legalized the chain.
3969 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3971 // The high part is undefined.
3972 Hi = DAG.getNode(ISD::UNDEF, NVT);
3975 case ISD::ANY_EXTEND:
3976 // The low part is any extension of the input (which degenerates to a copy).
3977 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
3978 // The high part is undefined.
3979 Hi = DAG.getNode(ISD::UNDEF, NVT);
3981 case ISD::SIGN_EXTEND: {
3982 // The low part is just a sign extension of the input (which degenerates to
3984 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
3986 // The high part is obtained by SRA'ing all but one of the bits of the lo
3988 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3989 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3990 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
3993 case ISD::ZERO_EXTEND:
3994 // The low part is just a zero extension of the input (which degenerates to
3996 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3998 // The high part is just a zero.
3999 Hi = DAG.getConstant(0, NVT);
4002 case ISD::BIT_CONVERT: {
4003 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4004 Node->getOperand(0));
4005 ExpandOp(Tmp, Lo, Hi);
4009 case ISD::READCYCLECOUNTER:
4010 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4011 TargetLowering::Custom &&
4012 "Must custom expand ReadCycleCounter");
4013 Lo = TLI.LowerOperation(Op, DAG);
4014 assert(Lo.Val && "Node must be custom expanded!");
4015 Hi = Lo.getValue(1);
4016 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4017 LegalizeOp(Lo.getValue(2)));
4020 // These operators cannot be expanded directly, emit them as calls to
4021 // library functions.
4022 case ISD::FP_TO_SINT:
4023 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4025 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4026 case Expand: assert(0 && "cannot expand FP!");
4027 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4028 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4031 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4033 // Now that the custom expander is done, expand the result, which is still
4036 ExpandOp(Op, Lo, Hi);
4041 if (Node->getOperand(0).getValueType() == MVT::f32)
4042 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4044 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4047 case ISD::FP_TO_UINT:
4048 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4050 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4051 case Expand: assert(0 && "cannot expand FP!");
4052 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4053 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4056 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4058 // Now that the custom expander is done, expand the result.
4060 ExpandOp(Op, Lo, Hi);
4065 if (Node->getOperand(0).getValueType() == MVT::f32)
4066 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4068 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4072 // If the target wants custom lowering, do so.
4073 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4074 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4075 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4076 Op = TLI.LowerOperation(Op, DAG);
4078 // Now that the custom expander is done, expand the result, which is
4080 ExpandOp(Op, Lo, Hi);
4085 // If we can emit an efficient shift operation, do so now.
4086 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4089 // If this target supports SHL_PARTS, use it.
4090 TargetLowering::LegalizeAction Action =
4091 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4092 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4093 Action == TargetLowering::Custom) {
4094 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4098 // Otherwise, emit a libcall.
4099 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4104 // If the target wants custom lowering, do so.
4105 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4106 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4107 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4108 Op = TLI.LowerOperation(Op, DAG);
4110 // Now that the custom expander is done, expand the result, which is
4112 ExpandOp(Op, Lo, Hi);
4117 // If we can emit an efficient shift operation, do so now.
4118 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4121 // If this target supports SRA_PARTS, use it.
4122 TargetLowering::LegalizeAction Action =
4123 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4124 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4125 Action == TargetLowering::Custom) {
4126 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4130 // Otherwise, emit a libcall.
4131 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4136 // If the target wants custom lowering, do so.
4137 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4138 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4139 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4140 Op = TLI.LowerOperation(Op, DAG);
4142 // Now that the custom expander is done, expand the result, which is
4144 ExpandOp(Op, Lo, Hi);
4149 // If we can emit an efficient shift operation, do so now.
4150 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4153 // If this target supports SRL_PARTS, use it.
4154 TargetLowering::LegalizeAction Action =
4155 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4156 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4157 Action == TargetLowering::Custom) {
4158 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4162 // Otherwise, emit a libcall.
4163 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4169 // If the target wants to custom expand this, let them.
4170 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4171 TargetLowering::Custom) {
4172 Op = TLI.LowerOperation(Op, DAG);
4174 ExpandOp(Op, Lo, Hi);
4179 // Expand the subcomponents.
4180 SDOperand LHSL, LHSH, RHSL, RHSH;
4181 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4182 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4183 std::vector<MVT::ValueType> VTs;
4184 std::vector<SDOperand> LoOps, HiOps;
4185 VTs.push_back(LHSL.getValueType());
4186 VTs.push_back(MVT::Flag);
4187 LoOps.push_back(LHSL);
4188 LoOps.push_back(RHSL);
4189 HiOps.push_back(LHSH);
4190 HiOps.push_back(RHSH);
4191 if (Node->getOpcode() == ISD::ADD) {
4192 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
4193 HiOps.push_back(Lo.getValue(1));
4194 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
4196 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
4197 HiOps.push_back(Lo.getValue(1));
4198 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
4203 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4204 SDOperand LL, LH, RL, RH;
4205 ExpandOp(Node->getOperand(0), LL, LH);
4206 ExpandOp(Node->getOperand(1), RL, RH);
4207 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4208 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4209 // extended the sign bit of the low half through the upper half, and if so
4210 // emit a MULHS instead of the alternate sequence that is valid for any
4211 // i64 x i64 multiply.
4212 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4213 // is RH an extension of the sign bit of RL?
4214 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4215 RH.getOperand(1).getOpcode() == ISD::Constant &&
4216 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4217 // is LH an extension of the sign bit of LL?
4218 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4219 LH.getOperand(1).getOpcode() == ISD::Constant &&
4220 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4221 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4223 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4224 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4225 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4226 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4227 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4229 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4231 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4235 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4236 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4237 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4238 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4241 // Make sure the resultant values have been legalized themselves, unless this
4242 // is a type that requires multi-step expansion.
4243 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4244 Lo = LegalizeOp(Lo);
4245 Hi = LegalizeOp(Hi);
4248 // Remember in a map if the values will be reused later.
4250 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4251 assert(isNew && "Value already expanded?!?");
4254 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4255 /// two smaller values of MVT::Vector type.
4256 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4258 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4259 SDNode *Node = Op.Val;
4260 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4261 assert(NumElements > 1 && "Cannot split a single element vector!");
4262 unsigned NewNumElts = NumElements/2;
4263 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4264 SDOperand TypeNode = *(Node->op_end()-1);
4266 // See if we already split it.
4267 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4268 = SplitNodes.find(Op);
4269 if (I != SplitNodes.end()) {
4270 Lo = I->second.first;
4271 Hi = I->second.second;
4275 switch (Node->getOpcode()) {
4276 default: assert(0 && "Unknown vector operation!");
4277 case ISD::VBUILD_VECTOR: {
4278 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
4279 LoOps.push_back(NewNumEltsNode);
4280 LoOps.push_back(TypeNode);
4281 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
4283 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
4284 HiOps.push_back(NewNumEltsNode);
4285 HiOps.push_back(TypeNode);
4286 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
4297 SDOperand LL, LH, RL, RH;
4298 SplitVectorOp(Node->getOperand(0), LL, LH);
4299 SplitVectorOp(Node->getOperand(1), RL, RH);
4301 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4302 NewNumEltsNode, TypeNode);
4303 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4304 NewNumEltsNode, TypeNode);
4308 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4309 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4310 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4312 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4313 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4314 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4315 getIntPtrConstant(IncrementSize));
4316 // FIXME: This creates a bogus srcvalue!
4317 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4319 // Build a factor node to remember that this load is independent of the
4321 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4324 // Remember that we legalized the chain.
4325 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4326 if (!TLI.isLittleEndian())
4332 // Remember in a map if the values will be reused later.
4334 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4335 assert(isNew && "Value already expanded?!?");
4339 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4340 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4341 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4342 /// type for the result.
4343 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4344 MVT::ValueType NewVT) {
4345 // FIXME: THIS IS A TEMPORARY HACK
4346 if (Op.getValueType() == NewVT) return Op;
4348 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4349 SDNode *Node = Op.Val;
4351 // See if we already packed it.
4352 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4353 if (I != PackedNodes.end()) return I->second;
4356 switch (Node->getOpcode()) {
4358 Node->dump(); std::cerr << "\n";
4359 assert(0 && "Unknown vector operation in PackVectorOp!");
4368 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4370 PackVectorOp(Node->getOperand(0), NewVT),
4371 PackVectorOp(Node->getOperand(1), NewVT));
4374 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4375 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4377 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4379 // Remember that we legalized the chain.
4380 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4383 case ISD::VBUILD_VECTOR:
4384 if (!MVT::isVector(NewVT)) {
4385 // Returning a scalar?
4386 Result = Node->getOperand(0);
4388 // Returning a BUILD_VECTOR?
4389 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
4390 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
4393 case ISD::VINSERT_VECTOR_ELT:
4394 if (!MVT::isVector(NewVT)) {
4395 // Returning a scalar? Must be the inserted element.
4396 Result = Node->getOperand(1);
4398 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4399 PackVectorOp(Node->getOperand(0), NewVT),
4400 Node->getOperand(1), Node->getOperand(2));
4405 if (TLI.isTypeLegal(NewVT))
4406 Result = LegalizeOp(Result);
4407 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4408 assert(isNew && "Value already packed?");
4413 // SelectionDAG::Legalize - This is the entry point for the file.
4415 void SelectionDAG::Legalize() {
4416 /// run - This is the main entry point to this class.
4418 SelectionDAGLegalize(*this).LegalizeDAG();