1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineJumpTableInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetFrameLowering.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/Function.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class SelectionDAGLegalize {
57 const TargetMachine &TM;
58 const TargetLowering &TLI;
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDValue LastCALLSEQ_END;
70 Legal, // The target natively supports this operation.
71 Promote, // This operation should be executed in a larger type.
72 Expand // Try to expand this to other ops, otherwise use a libcall.
75 /// ValueTypeActions - This is a bitvector that contains two bits for each
76 /// value type, where the two bits correspond to the LegalizeAction enum.
77 /// This can be queried with "getTypeAction(VT)".
78 TargetLowering::ValueTypeActionImpl ValueTypeActions;
80 /// LegalizedNodes - For nodes that are of legal width, and that have more
81 /// than one use, this map indicates what regularized operand to use. This
82 /// allows us to avoid legalizing the same thing more than once.
83 DenseMap<SDValue, SDValue> LegalizedNodes;
85 void AddLegalizedOperand(SDValue From, SDValue To) {
86 LegalizedNodes.insert(std::make_pair(From, To));
87 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
91 // Transfer SDDbgValues.
92 DAG.TransferDbgValues(From, To);
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(EVT VT) const {
102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
105 /// isTypeLegal - Return true if this type is legal on this target.
107 bool isTypeLegal(EVT VT) const {
108 return getTypeAction(VT) == Legal;
114 /// LegalizeOp - We know that the specified value has a legal type.
115 /// Recursively ensure that the operands have legal types, then return the
117 SDValue LegalizeOp(SDValue O);
119 SDValue OptimizeFloatStore(StoreSDNode *ST);
121 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
122 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
123 /// is necessary to spill the vector being inserted into to memory, perform
124 /// the insert there, and then read the result back.
125 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
126 SDValue Idx, DebugLoc dl);
127 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
130 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
131 /// performs the same shuffe in terms of order or result bytes, but on a type
132 /// whose vector element type is narrower than the original shuffle type.
133 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
134 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
135 SDValue N1, SDValue N2,
136 SmallVectorImpl<int> &Mask) const;
138 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
139 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
141 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
144 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
145 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
146 SDNode *Node, bool isSigned);
147 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
148 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
149 RTLIB::Libcall Call_PPCF128);
150 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
151 RTLIB::Libcall Call_I8,
152 RTLIB::Libcall Call_I16,
153 RTLIB::Libcall Call_I32,
154 RTLIB::Libcall Call_I64,
155 RTLIB::Libcall Call_I128);
157 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
158 SDValue ExpandBUILD_VECTOR(SDNode *Node);
159 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
160 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
161 SmallVectorImpl<SDValue> &Results);
162 SDValue ExpandFCOPYSIGN(SDNode *Node);
163 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
165 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
167 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
170 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
171 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
173 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
174 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
175 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
177 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
179 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
180 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
184 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
185 /// performs the same shuffe in terms of order or result bytes, but on a type
186 /// whose vector element type is narrower than the original shuffle type.
187 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
189 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
190 SDValue N1, SDValue N2,
191 SmallVectorImpl<int> &Mask) const {
192 unsigned NumMaskElts = VT.getVectorNumElements();
193 unsigned NumDestElts = NVT.getVectorNumElements();
194 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
196 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
198 if (NumEltsGrowth == 1)
199 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
201 SmallVector<int, 8> NewMask;
202 for (unsigned i = 0; i != NumMaskElts; ++i) {
204 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
206 NewMask.push_back(-1);
208 NewMask.push_back(Idx * NumEltsGrowth + j);
211 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
212 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
213 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
216 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
217 CodeGenOpt::Level ol)
218 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
219 DAG(dag), OptLevel(ol),
220 ValueTypeActions(TLI.getValueTypeActions()) {
221 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
222 "Too many value types for ValueTypeActions to hold!");
225 void SelectionDAGLegalize::LegalizeDAG() {
226 LastCALLSEQ_END = DAG.getEntryNode();
228 // The legalize process is inherently a bottom-up recursive process (users
229 // legalize their uses before themselves). Given infinite stack space, we
230 // could just start legalizing on the root and traverse the whole graph. In
231 // practice however, this causes us to run out of stack space on large basic
232 // blocks. To avoid this problem, compute an ordering of the nodes where each
233 // node is only legalized after all of its operands are legalized.
234 DAG.AssignTopologicalOrder();
235 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
236 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
237 LegalizeOp(SDValue(I, 0));
239 // Finally, it's possible the root changed. Get the new root.
240 SDValue OldRoot = DAG.getRoot();
241 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
242 DAG.setRoot(LegalizedNodes[OldRoot]);
244 LegalizedNodes.clear();
246 // Remove dead nodes now.
247 DAG.RemoveDeadNodes();
251 /// FindCallEndFromCallStart - Given a chained node that is part of a call
252 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
253 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
254 // Nested CALLSEQ_START/END constructs aren't yet legal,
255 // but we can DTRT and handle them correctly here.
256 if (Node->getOpcode() == ISD::CALLSEQ_START)
258 else if (Node->getOpcode() == ISD::CALLSEQ_END) {
263 if (Node->use_empty())
264 return 0; // No CallSeqEnd
266 // The chain is usually at the end.
267 SDValue TheChain(Node, Node->getNumValues()-1);
268 if (TheChain.getValueType() != MVT::Other) {
269 // Sometimes it's at the beginning.
270 TheChain = SDValue(Node, 0);
271 if (TheChain.getValueType() != MVT::Other) {
272 // Otherwise, hunt for it.
273 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
274 if (Node->getValueType(i) == MVT::Other) {
275 TheChain = SDValue(Node, i);
279 // Otherwise, we walked into a node without a chain.
280 if (TheChain.getValueType() != MVT::Other)
285 for (SDNode::use_iterator UI = Node->use_begin(),
286 E = Node->use_end(); UI != E; ++UI) {
288 // Make sure to only follow users of our token chain.
290 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
291 if (User->getOperand(i) == TheChain)
292 if (SDNode *Result = FindCallEndFromCallStart(User, depth))
298 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
299 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
300 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
302 assert(Node && "Didn't find callseq_start for a call??");
303 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
304 Node = Node->getOperand(0).getNode();
305 assert(Node->getOperand(0).getValueType() == MVT::Other &&
306 "Node doesn't have a token chain argument!");
307 switch (Node->getOpcode()) {
310 case ISD::CALLSEQ_START:
315 case ISD::CALLSEQ_END:
323 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
324 /// see if any uses can reach Dest. If no dest operands can get to dest,
325 /// legalize them, legalize ourself, and return false, otherwise, return true.
327 /// Keep track of the nodes we fine that actually do lead to Dest in
328 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
330 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
331 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
332 if (N == Dest) return true; // N certainly leads to Dest :)
334 // If we've already processed this node and it does lead to Dest, there is no
335 // need to reprocess it.
336 if (NodesLeadingTo.count(N)) return true;
338 // If the first result of this node has been already legalized, then it cannot
340 if (LegalizedNodes.count(SDValue(N, 0))) return false;
342 // Okay, this node has not already been legalized. Check and legalize all
343 // operands. If none lead to Dest, then we can legalize this node.
344 bool OperandsLeadToDest = false;
345 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
346 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
347 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
350 if (OperandsLeadToDest) {
351 NodesLeadingTo.insert(N);
355 // Okay, this node looks safe, legalize it and return false.
356 LegalizeOp(SDValue(N, 0));
360 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
361 /// a load from the constant pool.
362 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
363 SelectionDAG &DAG, const TargetLowering &TLI) {
365 DebugLoc dl = CFP->getDebugLoc();
367 // If a FP immediate is precise when represented as a float and if the
368 // target can do an extending load from float to double, we put it into
369 // the constant pool as a float, even if it's is statically typed as a
370 // double. This shrinks FP constants and canonicalizes them for targets where
371 // an FP extending load is the same cost as a normal load (such as on the x87
372 // fp stack or PPC FP unit).
373 EVT VT = CFP->getValueType(0);
374 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
376 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
377 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
378 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
383 while (SVT != MVT::f32) {
384 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
385 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
386 // Only do this if the target has a native EXTLOAD instruction from
388 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
389 TLI.ShouldShrinkFPConstant(OrigVT)) {
390 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
391 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
397 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
398 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
400 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
402 CPIdx, MachinePointerInfo::getConstantPool(),
403 VT, false, false, Alignment);
404 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
405 MachinePointerInfo::getConstantPool(), false, false,
409 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
411 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
412 const TargetLowering &TLI) {
413 SDValue Chain = ST->getChain();
414 SDValue Ptr = ST->getBasePtr();
415 SDValue Val = ST->getValue();
416 EVT VT = Val.getValueType();
417 int Alignment = ST->getAlignment();
418 DebugLoc dl = ST->getDebugLoc();
419 if (ST->getMemoryVT().isFloatingPoint() ||
420 ST->getMemoryVT().isVector()) {
421 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
422 if (TLI.isTypeLegal(intVT)) {
423 // Expand to a bitconvert of the value to the integer type of the
424 // same size, then a (misaligned) int store.
425 // FIXME: Does not handle truncating floating point stores!
426 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
427 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
428 ST->isVolatile(), ST->isNonTemporal(), Alignment);
430 // Do a (aligned) store to a stack slot, then copy from the stack slot
431 // to the final destination using (unaligned) integer loads and stores.
432 EVT StoredVT = ST->getMemoryVT();
434 TLI.getRegisterType(*DAG.getContext(),
435 EVT::getIntegerVT(*DAG.getContext(),
436 StoredVT.getSizeInBits()));
437 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
438 unsigned RegBytes = RegVT.getSizeInBits() / 8;
439 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
441 // Make sure the stack slot is also aligned for the register type.
442 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
444 // Perform the original store, only redirected to the stack slot.
445 SDValue Store = DAG.getTruncStore(Chain, dl,
446 Val, StackPtr, MachinePointerInfo(),
447 StoredVT, false, false, 0);
448 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
449 SmallVector<SDValue, 8> Stores;
452 // Do all but one copies using the full register width.
453 for (unsigned i = 1; i < NumRegs; i++) {
454 // Load one integer register's worth from the stack slot.
455 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
456 MachinePointerInfo(),
458 // Store it to the final location. Remember the store.
459 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
460 ST->getPointerInfo().getWithOffset(Offset),
461 ST->isVolatile(), ST->isNonTemporal(),
462 MinAlign(ST->getAlignment(), Offset)));
463 // Increment the pointers.
465 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
467 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
470 // The last store may be partial. Do a truncating store. On big-endian
471 // machines this requires an extending load from the stack slot to ensure
472 // that the bits are in the right place.
473 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
474 8 * (StoredBytes - Offset));
476 // Load from the stack slot.
477 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
478 MachinePointerInfo(),
479 MemVT, false, false, 0);
481 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
483 .getWithOffset(Offset),
484 MemVT, ST->isVolatile(),
486 MinAlign(ST->getAlignment(), Offset)));
487 // The order of the stores doesn't matter - say it with a TokenFactor.
488 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
492 assert(ST->getMemoryVT().isInteger() &&
493 !ST->getMemoryVT().isVector() &&
494 "Unaligned store of unknown type.");
495 // Get the half-size VT
496 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
497 int NumBits = NewStoredVT.getSizeInBits();
498 int IncrementSize = NumBits / 8;
500 // Divide the stored value in two parts.
501 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
503 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
505 // Store the two parts
506 SDValue Store1, Store2;
507 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
508 ST->getPointerInfo(), NewStoredVT,
509 ST->isVolatile(), ST->isNonTemporal(), Alignment);
510 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
511 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
512 Alignment = MinAlign(Alignment, IncrementSize);
513 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
514 ST->getPointerInfo().getWithOffset(IncrementSize),
515 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
518 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
521 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
523 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
524 const TargetLowering &TLI) {
525 SDValue Chain = LD->getChain();
526 SDValue Ptr = LD->getBasePtr();
527 EVT VT = LD->getValueType(0);
528 EVT LoadedVT = LD->getMemoryVT();
529 DebugLoc dl = LD->getDebugLoc();
530 if (VT.isFloatingPoint() || VT.isVector()) {
531 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
532 if (TLI.isTypeLegal(intVT)) {
533 // Expand to a (misaligned) integer load of the same size,
534 // then bitconvert to floating point or vector.
535 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
537 LD->isNonTemporal(), LD->getAlignment());
538 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
539 if (VT.isFloatingPoint() && LoadedVT != VT)
540 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
542 SDValue Ops[] = { Result, Chain };
543 return DAG.getMergeValues(Ops, 2, dl);
546 // Copy the value to a (aligned) stack slot using (unaligned) integer
547 // loads and stores, then do a (aligned) load from the stack slot.
548 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
549 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
550 unsigned RegBytes = RegVT.getSizeInBits() / 8;
551 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
553 // Make sure the stack slot is also aligned for the register type.
554 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
556 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
557 SmallVector<SDValue, 8> Stores;
558 SDValue StackPtr = StackBase;
561 // Do all but one copies using the full register width.
562 for (unsigned i = 1; i < NumRegs; i++) {
563 // Load one integer register's worth from the original location.
564 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
565 LD->getPointerInfo().getWithOffset(Offset),
566 LD->isVolatile(), LD->isNonTemporal(),
567 MinAlign(LD->getAlignment(), Offset));
568 // Follow the load with a store to the stack slot. Remember the store.
569 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
570 MachinePointerInfo(), false, false, 0));
571 // Increment the pointers.
573 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
574 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
578 // The last copy may be partial. Do an extending load.
579 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
580 8 * (LoadedBytes - Offset));
581 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
582 LD->getPointerInfo().getWithOffset(Offset),
583 MemVT, LD->isVolatile(),
585 MinAlign(LD->getAlignment(), Offset));
586 // Follow the load with a store to the stack slot. Remember the store.
587 // On big-endian machines this requires a truncating store to ensure
588 // that the bits end up in the right place.
589 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
590 MachinePointerInfo(), MemVT,
593 // The order of the stores doesn't matter - say it with a TokenFactor.
594 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
597 // Finally, perform the original load only redirected to the stack slot.
598 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
599 MachinePointerInfo(), LoadedVT, false, false, 0);
601 // Callers expect a MERGE_VALUES node.
602 SDValue Ops[] = { Load, TF };
603 return DAG.getMergeValues(Ops, 2, dl);
605 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
606 "Unaligned load of unsupported type.");
608 // Compute the new VT that is half the size of the old one. This is an
610 unsigned NumBits = LoadedVT.getSizeInBits();
612 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
615 unsigned Alignment = LD->getAlignment();
616 unsigned IncrementSize = NumBits / 8;
617 ISD::LoadExtType HiExtType = LD->getExtensionType();
619 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
620 if (HiExtType == ISD::NON_EXTLOAD)
621 HiExtType = ISD::ZEXTLOAD;
623 // Load the value in two parts
625 if (TLI.isLittleEndian()) {
626 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getPointerInfo(),
627 NewLoadedVT, LD->isVolatile(),
628 LD->isNonTemporal(), Alignment);
629 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
630 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
631 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr,
632 LD->getPointerInfo().getWithOffset(IncrementSize),
633 NewLoadedVT, LD->isVolatile(),
634 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
636 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getPointerInfo(),
637 NewLoadedVT, LD->isVolatile(),
638 LD->isNonTemporal(), Alignment);
639 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
640 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
641 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr,
642 LD->getPointerInfo().getWithOffset(IncrementSize),
643 NewLoadedVT, LD->isVolatile(),
644 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
647 // aggregate the two parts
648 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
649 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
650 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
652 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
655 SDValue Ops[] = { Result, TF };
656 return DAG.getMergeValues(Ops, 2, dl);
659 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
660 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
661 /// is necessary to spill the vector being inserted into to memory, perform
662 /// the insert there, and then read the result back.
663 SDValue SelectionDAGLegalize::
664 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
670 // If the target doesn't support this, we have to spill the input vector
671 // to a temporary stack slot, update the element, then reload it. This is
672 // badness. We could also load the value into a vector register (either
673 // with a "move to register" or "extload into register" instruction, then
674 // permute it into place, if the idx is a constant and if the idx is
675 // supported by the target.
676 EVT VT = Tmp1.getValueType();
677 EVT EltVT = VT.getVectorElementType();
678 EVT IdxVT = Tmp3.getValueType();
679 EVT PtrVT = TLI.getPointerTy();
680 SDValue StackPtr = DAG.CreateStackTemporary(VT);
682 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
685 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
686 MachinePointerInfo::getFixedStack(SPFI),
689 // Truncate or zero extend offset to target pointer type.
690 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
691 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
692 // Add the offset to the index.
693 unsigned EltSize = EltVT.getSizeInBits()/8;
694 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
695 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
696 // Store the scalar value.
697 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
699 // Load the updated vector.
700 return DAG.getLoad(VT, dl, Ch, StackPtr,
701 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
705 SDValue SelectionDAGLegalize::
706 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
707 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
708 // SCALAR_TO_VECTOR requires that the type of the value being inserted
709 // match the element type of the vector being created, except for
710 // integers in which case the inserted value can be over width.
711 EVT EltVT = Vec.getValueType().getVectorElementType();
712 if (Val.getValueType() == EltVT ||
713 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
714 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
715 Vec.getValueType(), Val);
717 unsigned NumElts = Vec.getValueType().getVectorNumElements();
718 // We generate a shuffle of InVec and ScVec, so the shuffle mask
719 // should be 0,1,2,3,4,5... with the appropriate element replaced with
721 SmallVector<int, 8> ShufOps;
722 for (unsigned i = 0; i != NumElts; ++i)
723 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
725 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
729 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
732 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
733 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
734 // FIXME: We shouldn't do this for TargetConstantFP's.
735 // FIXME: move this to the DAG Combiner! Note that we can't regress due
736 // to phase ordering between legalized code and the dag combiner. This
737 // probably means that we need to integrate dag combiner and legalizer
739 // We generally can't do this one for long doubles.
740 SDValue Tmp1 = ST->getChain();
741 SDValue Tmp2 = ST->getBasePtr();
743 unsigned Alignment = ST->getAlignment();
744 bool isVolatile = ST->isVolatile();
745 bool isNonTemporal = ST->isNonTemporal();
746 DebugLoc dl = ST->getDebugLoc();
747 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
748 if (CFP->getValueType(0) == MVT::f32 &&
749 getTypeAction(MVT::i32) == Legal) {
750 Tmp3 = DAG.getConstant(CFP->getValueAPF().
751 bitcastToAPInt().zextOrTrunc(32),
753 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
754 isVolatile, isNonTemporal, Alignment);
757 if (CFP->getValueType(0) == MVT::f64) {
758 // If this target supports 64-bit registers, do a single 64-bit store.
759 if (getTypeAction(MVT::i64) == Legal) {
760 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
761 zextOrTrunc(64), MVT::i64);
762 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
763 isVolatile, isNonTemporal, Alignment);
766 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
767 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
768 // stores. If the target supports neither 32- nor 64-bits, this
769 // xform is certainly not worth it.
770 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
771 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
772 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
773 if (TLI.isBigEndian()) std::swap(Lo, Hi);
775 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
776 isNonTemporal, Alignment);
777 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
778 DAG.getIntPtrConstant(4));
779 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
780 ST->getPointerInfo().getWithOffset(4),
781 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
783 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
790 /// LegalizeOp - We know that the specified value has a legal type, and
791 /// that its operands are legal. Now ensure that the operation itself
792 /// is legal, recursively ensuring that the operands' operations remain
794 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
795 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
798 SDNode *Node = Op.getNode();
799 DebugLoc dl = Node->getDebugLoc();
801 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
802 assert(getTypeAction(Node->getValueType(i)) == Legal &&
803 "Unexpected illegal type!");
805 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
806 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
807 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
808 "Unexpected illegal type!");
810 // Note that LegalizeOp may be reentered even from single-use nodes, which
811 // means that we always must cache transformed nodes.
812 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
813 if (I != LegalizedNodes.end()) return I->second;
815 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
817 bool isCustom = false;
819 // Figure out the correct action; the way to query this varies by opcode
820 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
821 bool SimpleFinishLegalizing = true;
822 switch (Node->getOpcode()) {
823 case ISD::INTRINSIC_W_CHAIN:
824 case ISD::INTRINSIC_WO_CHAIN:
825 case ISD::INTRINSIC_VOID:
828 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
830 case ISD::SINT_TO_FP:
831 case ISD::UINT_TO_FP:
832 case ISD::EXTRACT_VECTOR_ELT:
833 Action = TLI.getOperationAction(Node->getOpcode(),
834 Node->getOperand(0).getValueType());
836 case ISD::FP_ROUND_INREG:
837 case ISD::SIGN_EXTEND_INREG: {
838 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
839 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
845 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
846 Node->getOpcode() == ISD::SETCC ? 2 : 1;
847 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
848 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
849 ISD::CondCode CCCode =
850 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
851 Action = TLI.getCondCodeAction(CCCode, OpVT);
852 if (Action == TargetLowering::Legal) {
853 if (Node->getOpcode() == ISD::SELECT_CC)
854 Action = TLI.getOperationAction(Node->getOpcode(),
855 Node->getValueType(0));
857 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
863 // FIXME: Model these properly. LOAD and STORE are complicated, and
864 // STORE expects the unlegalized operand in some cases.
865 SimpleFinishLegalizing = false;
867 case ISD::CALLSEQ_START:
868 case ISD::CALLSEQ_END:
869 // FIXME: This shouldn't be necessary. These nodes have special properties
870 // dealing with the recursive nature of legalization. Removing this
871 // special case should be done as part of making LegalizeDAG non-recursive.
872 SimpleFinishLegalizing = false;
874 case ISD::EXTRACT_ELEMENT:
875 case ISD::FLT_ROUNDS_:
883 case ISD::MERGE_VALUES:
885 case ISD::FRAME_TO_ARGS_OFFSET:
886 case ISD::EH_SJLJ_SETJMP:
887 case ISD::EH_SJLJ_LONGJMP:
888 case ISD::EH_SJLJ_DISPATCHSETUP:
889 // These operations lie about being legal: when they claim to be legal,
890 // they should actually be expanded.
891 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
892 if (Action == TargetLowering::Legal)
893 Action = TargetLowering::Expand;
895 case ISD::TRAMPOLINE:
897 case ISD::RETURNADDR:
898 // These operations lie about being legal: when they claim to be legal,
899 // they should actually be custom-lowered.
900 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
901 if (Action == TargetLowering::Legal)
902 Action = TargetLowering::Custom;
904 case ISD::BUILD_VECTOR:
905 // A weird case: legalization for BUILD_VECTOR never legalizes the
907 // FIXME: This really sucks... changing it isn't semantically incorrect,
908 // but it massively pessimizes the code for floating-point BUILD_VECTORs
909 // because ConstantFP operands get legalized into constant pool loads
910 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
911 // though, because BUILD_VECTORS usually get lowered into other nodes
912 // which get legalized properly.
913 SimpleFinishLegalizing = false;
916 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
917 Action = TargetLowering::Legal;
919 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
924 if (SimpleFinishLegalizing) {
925 SmallVector<SDValue, 8> Ops, ResultVals;
926 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
927 Ops.push_back(LegalizeOp(Node->getOperand(i)));
928 switch (Node->getOpcode()) {
935 // Branches tweak the chain to include LastCALLSEQ_END
936 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
938 Ops[0] = LegalizeOp(Ops[0]);
939 LastCALLSEQ_END = DAG.getEntryNode();
946 // Legalizing shifts/rotates requires adjusting the shift amount
947 // to the appropriate width.
948 if (!Ops[1].getValueType().isVector())
949 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
954 // Legalizing shifts/rotates requires adjusting the shift amount
955 // to the appropriate width.
956 if (!Ops[2].getValueType().isVector())
957 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
961 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
964 case TargetLowering::Legal:
965 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
966 ResultVals.push_back(Result.getValue(i));
968 case TargetLowering::Custom:
969 // FIXME: The handling for custom lowering with multiple results is
971 Tmp1 = TLI.LowerOperation(Result, DAG);
972 if (Tmp1.getNode()) {
973 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
975 ResultVals.push_back(Tmp1);
977 ResultVals.push_back(Tmp1.getValue(i));
983 case TargetLowering::Expand:
984 ExpandNode(Result.getNode(), ResultVals);
986 case TargetLowering::Promote:
987 PromoteNode(Result.getNode(), ResultVals);
990 if (!ResultVals.empty()) {
991 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
992 if (ResultVals[i] != SDValue(Node, i))
993 ResultVals[i] = LegalizeOp(ResultVals[i]);
994 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
996 return ResultVals[Op.getResNo()];
1000 switch (Node->getOpcode()) {
1007 assert(0 && "Do not know how to legalize this operator!");
1009 case ISD::BUILD_VECTOR:
1010 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1011 default: assert(0 && "This action is not supported yet!");
1012 case TargetLowering::Custom:
1013 Tmp3 = TLI.LowerOperation(Result, DAG);
1014 if (Tmp3.getNode()) {
1019 case TargetLowering::Expand:
1020 Result = ExpandBUILD_VECTOR(Result.getNode());
1024 case ISD::CALLSEQ_START: {
1025 static int depth = 0;
1026 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1028 // Recursively Legalize all of the inputs of the call end that do not lead
1029 // to this call start. This ensures that any libcalls that need be inserted
1030 // are inserted *before* the CALLSEQ_START.
1031 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1032 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1033 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1037 // Now that we have legalized all of the inputs (which may have inserted
1038 // libcalls), create the new CALLSEQ_START node.
1039 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1041 // Merge in the last call to ensure that this call starts after the last
1043 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken && depth == 0) {
1044 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1045 Tmp1, LastCALLSEQ_END);
1046 Tmp1 = LegalizeOp(Tmp1);
1049 // Do not try to legalize the target-specific arguments (#1+).
1050 if (Tmp1 != Node->getOperand(0)) {
1051 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1053 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1054 Ops.size()), Result.getResNo());
1057 // Remember that the CALLSEQ_START is legalized.
1058 AddLegalizedOperand(Op.getValue(0), Result);
1059 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1060 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1062 // Now that the callseq_start and all of the non-call nodes above this call
1063 // sequence have been legalized, legalize the call itself. During this
1064 // process, no libcalls can/will be inserted, guaranteeing that no calls
1067 SDValue Saved_LastCALLSEQ_END = LastCALLSEQ_END ;
1068 // Note that we are selecting this call!
1069 LastCALLSEQ_END = SDValue(CallEnd, 0);
1072 // Legalize the call, starting from the CALLSEQ_END.
1073 LegalizeOp(LastCALLSEQ_END);
1075 assert(depth >= 0 && "Un-matched CALLSEQ_START?");
1077 LastCALLSEQ_END = Saved_LastCALLSEQ_END;
1080 case ISD::CALLSEQ_END:
1081 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1082 // will cause this node to be legalized as well as handling libcalls right.
1083 if (LastCALLSEQ_END.getNode() != Node) {
1084 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1085 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1086 assert(I != LegalizedNodes.end() &&
1087 "Legalizing the call start should have legalized this node!");
1091 // Otherwise, the call start has been legalized and everything is going
1092 // according to plan. Just legalize ourselves normally here.
1093 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1094 // Do not try to legalize the target-specific arguments (#1+), except for
1095 // an optional flag input.
1096 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1097 if (Tmp1 != Node->getOperand(0)) {
1098 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1100 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1101 &Ops[0], Ops.size()),
1105 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1106 if (Tmp1 != Node->getOperand(0) ||
1107 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1108 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1111 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1112 &Ops[0], Ops.size()),
1116 // This finishes up call legalization.
1117 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1118 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1119 if (Node->getNumValues() == 2)
1120 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1121 return Result.getValue(Op.getResNo());
1123 LoadSDNode *LD = cast<LoadSDNode>(Node);
1124 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1125 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1127 ISD::LoadExtType ExtType = LD->getExtensionType();
1128 if (ExtType == ISD::NON_EXTLOAD) {
1129 EVT VT = Node->getValueType(0);
1130 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1131 Tmp1, Tmp2, LD->getOffset()),
1133 Tmp3 = Result.getValue(0);
1134 Tmp4 = Result.getValue(1);
1136 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1137 default: assert(0 && "This action is not supported yet!");
1138 case TargetLowering::Legal:
1139 // If this is an unaligned load and the target doesn't support it,
1141 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1142 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1143 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1144 if (LD->getAlignment() < ABIAlignment){
1145 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1147 Tmp3 = Result.getOperand(0);
1148 Tmp4 = Result.getOperand(1);
1149 Tmp3 = LegalizeOp(Tmp3);
1150 Tmp4 = LegalizeOp(Tmp4);
1154 case TargetLowering::Custom:
1155 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1156 if (Tmp1.getNode()) {
1157 Tmp3 = LegalizeOp(Tmp1);
1158 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1161 case TargetLowering::Promote: {
1162 // Only promote a load of vector type to another.
1163 assert(VT.isVector() && "Cannot promote this load!");
1164 // Change base type to a different vector type.
1165 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1167 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1168 LD->isVolatile(), LD->isNonTemporal(),
1169 LD->getAlignment());
1170 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1171 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1175 // Since loads produce two values, make sure to remember that we
1176 // legalized both of them.
1177 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1178 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1179 return Op.getResNo() ? Tmp4 : Tmp3;
1182 EVT SrcVT = LD->getMemoryVT();
1183 unsigned SrcWidth = SrcVT.getSizeInBits();
1184 unsigned Alignment = LD->getAlignment();
1185 bool isVolatile = LD->isVolatile();
1186 bool isNonTemporal = LD->isNonTemporal();
1188 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1189 // Some targets pretend to have an i1 loading operation, and actually
1190 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1191 // bits are guaranteed to be zero; it helps the optimizers understand
1192 // that these bits are zero. It is also useful for EXTLOAD, since it
1193 // tells the optimizers that those bits are undefined. It would be
1194 // nice to have an effective generic way of getting these benefits...
1195 // Until such a way is found, don't insist on promoting i1 here.
1196 (SrcVT != MVT::i1 ||
1197 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1198 // Promote to a byte-sized load if not loading an integral number of
1199 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1200 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1201 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1204 // The extra bits are guaranteed to be zero, since we stored them that
1205 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1207 ISD::LoadExtType NewExtType =
1208 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1210 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
1211 Tmp1, Tmp2, LD->getPointerInfo(),
1212 NVT, isVolatile, isNonTemporal, Alignment);
1214 Ch = Result.getValue(1); // The chain.
1216 if (ExtType == ISD::SEXTLOAD)
1217 // Having the top bits zero doesn't help when sign extending.
1218 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1219 Result.getValueType(),
1220 Result, DAG.getValueType(SrcVT));
1221 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1222 // All the top bits are guaranteed to be zero - inform the optimizers.
1223 Result = DAG.getNode(ISD::AssertZext, dl,
1224 Result.getValueType(), Result,
1225 DAG.getValueType(SrcVT));
1227 Tmp1 = LegalizeOp(Result);
1228 Tmp2 = LegalizeOp(Ch);
1229 } else if (SrcWidth & (SrcWidth - 1)) {
1230 // If not loading a power-of-2 number of bits, expand as two loads.
1231 assert(!SrcVT.isVector() && "Unsupported extload!");
1232 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1233 assert(RoundWidth < SrcWidth);
1234 unsigned ExtraWidth = SrcWidth - RoundWidth;
1235 assert(ExtraWidth < RoundWidth);
1236 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1237 "Load size not an integral number of bytes!");
1238 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1239 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1241 unsigned IncrementSize;
1243 if (TLI.isLittleEndian()) {
1244 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1245 // Load the bottom RoundWidth bits.
1246 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
1248 LD->getPointerInfo(), RoundVT, isVolatile,
1249 isNonTemporal, Alignment);
1251 // Load the remaining ExtraWidth bits.
1252 IncrementSize = RoundWidth / 8;
1253 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1254 DAG.getIntPtrConstant(IncrementSize));
1255 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1256 LD->getPointerInfo().getWithOffset(IncrementSize),
1257 ExtraVT, isVolatile, isNonTemporal,
1258 MinAlign(Alignment, IncrementSize));
1260 // Build a factor node to remember that this load is independent of
1262 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1265 // Move the top bits to the right place.
1266 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1267 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1269 // Join the hi and lo parts.
1270 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1272 // Big endian - avoid unaligned loads.
1273 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1274 // Load the top RoundWidth bits.
1275 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1276 LD->getPointerInfo(), RoundVT, isVolatile,
1277 isNonTemporal, Alignment);
1279 // Load the remaining ExtraWidth bits.
1280 IncrementSize = RoundWidth / 8;
1281 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1282 DAG.getIntPtrConstant(IncrementSize));
1283 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1284 Node->getValueType(0), dl, Tmp1, Tmp2,
1285 LD->getPointerInfo().getWithOffset(IncrementSize),
1286 ExtraVT, isVolatile, isNonTemporal,
1287 MinAlign(Alignment, IncrementSize));
1289 // Build a factor node to remember that this load is independent of
1291 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1294 // Move the top bits to the right place.
1295 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1296 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1298 // Join the hi and lo parts.
1299 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1302 Tmp1 = LegalizeOp(Result);
1303 Tmp2 = LegalizeOp(Ch);
1305 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1306 default: assert(0 && "This action is not supported yet!");
1307 case TargetLowering::Custom:
1310 case TargetLowering::Legal:
1311 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1312 Tmp1, Tmp2, LD->getOffset()),
1314 Tmp1 = Result.getValue(0);
1315 Tmp2 = Result.getValue(1);
1318 Tmp3 = TLI.LowerOperation(Result, DAG);
1319 if (Tmp3.getNode()) {
1320 Tmp1 = LegalizeOp(Tmp3);
1321 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1324 // If this is an unaligned load and the target doesn't support it,
1326 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1328 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1329 unsigned ABIAlignment =
1330 TLI.getTargetData()->getABITypeAlignment(Ty);
1331 if (LD->getAlignment() < ABIAlignment){
1332 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1334 Tmp1 = Result.getOperand(0);
1335 Tmp2 = Result.getOperand(1);
1336 Tmp1 = LegalizeOp(Tmp1);
1337 Tmp2 = LegalizeOp(Tmp2);
1342 case TargetLowering::Expand:
1343 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1344 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1345 LD->getPointerInfo(),
1346 LD->isVolatile(), LD->isNonTemporal(),
1347 LD->getAlignment());
1351 ExtendOp = (SrcVT.isFloatingPoint() ?
1352 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1354 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1355 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1356 default: llvm_unreachable("Unexpected extend load type!");
1358 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1359 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1360 Tmp2 = LegalizeOp(Load.getValue(1));
1363 // FIXME: This does not work for vectors on most targets. Sign- and
1364 // zero-extend operations are currently folded into extending loads,
1365 // whether they are legal or not, and then we end up here without any
1366 // support for legalizing them.
1367 assert(ExtType != ISD::EXTLOAD &&
1368 "EXTLOAD should always be supported!");
1369 // Turn the unsupported load into an EXTLOAD followed by an explicit
1370 // zero/sign extend inreg.
1371 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
1372 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1373 LD->isVolatile(), LD->isNonTemporal(),
1374 LD->getAlignment());
1376 if (ExtType == ISD::SEXTLOAD)
1377 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1378 Result.getValueType(),
1379 Result, DAG.getValueType(SrcVT));
1381 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1382 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1383 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1388 // Since loads produce two values, make sure to remember that we legalized
1390 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1391 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1392 return Op.getResNo() ? Tmp2 : Tmp1;
1395 StoreSDNode *ST = cast<StoreSDNode>(Node);
1396 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1397 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1398 unsigned Alignment = ST->getAlignment();
1399 bool isVolatile = ST->isVolatile();
1400 bool isNonTemporal = ST->isNonTemporal();
1402 if (!ST->isTruncatingStore()) {
1403 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1404 Result = SDValue(OptStore, 0);
1409 Tmp3 = LegalizeOp(ST->getValue());
1410 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1415 EVT VT = Tmp3.getValueType();
1416 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1417 default: assert(0 && "This action is not supported yet!");
1418 case TargetLowering::Legal:
1419 // If this is an unaligned store and the target doesn't support it,
1421 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1422 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1423 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1424 if (ST->getAlignment() < ABIAlignment)
1425 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1429 case TargetLowering::Custom:
1430 Tmp1 = TLI.LowerOperation(Result, DAG);
1431 if (Tmp1.getNode()) Result = Tmp1;
1433 case TargetLowering::Promote:
1434 assert(VT.isVector() && "Unknown legal promote case!");
1435 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1436 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1437 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1438 ST->getPointerInfo(), isVolatile,
1439 isNonTemporal, Alignment);
1445 Tmp3 = LegalizeOp(ST->getValue());
1447 EVT StVT = ST->getMemoryVT();
1448 unsigned StWidth = StVT.getSizeInBits();
1450 if (StWidth != StVT.getStoreSizeInBits()) {
1451 // Promote to a byte-sized store with upper bits zero if not
1452 // storing an integral number of bytes. For example, promote
1453 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1454 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1455 StVT.getStoreSizeInBits());
1456 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1457 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1458 NVT, isVolatile, isNonTemporal, Alignment);
1459 } else if (StWidth & (StWidth - 1)) {
1460 // If not storing a power-of-2 number of bits, expand as two stores.
1461 assert(!StVT.isVector() && "Unsupported truncstore!");
1462 unsigned RoundWidth = 1 << Log2_32(StWidth);
1463 assert(RoundWidth < StWidth);
1464 unsigned ExtraWidth = StWidth - RoundWidth;
1465 assert(ExtraWidth < RoundWidth);
1466 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1467 "Store size not an integral number of bytes!");
1468 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1469 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1471 unsigned IncrementSize;
1473 if (TLI.isLittleEndian()) {
1474 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1475 // Store the bottom RoundWidth bits.
1476 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1478 isVolatile, isNonTemporal, Alignment);
1480 // Store the remaining ExtraWidth bits.
1481 IncrementSize = RoundWidth / 8;
1482 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1483 DAG.getIntPtrConstant(IncrementSize));
1484 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1485 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1486 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1487 ST->getPointerInfo().getWithOffset(IncrementSize),
1488 ExtraVT, isVolatile, isNonTemporal,
1489 MinAlign(Alignment, IncrementSize));
1491 // Big endian - avoid unaligned stores.
1492 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1493 // Store the top RoundWidth bits.
1494 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1495 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1496 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1497 RoundVT, isVolatile, isNonTemporal, Alignment);
1499 // Store the remaining ExtraWidth bits.
1500 IncrementSize = RoundWidth / 8;
1501 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1502 DAG.getIntPtrConstant(IncrementSize));
1503 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1504 ST->getPointerInfo().getWithOffset(IncrementSize),
1505 ExtraVT, isVolatile, isNonTemporal,
1506 MinAlign(Alignment, IncrementSize));
1509 // The order of the stores doesn't matter.
1510 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1512 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1513 Tmp2 != ST->getBasePtr())
1514 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1519 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1520 default: assert(0 && "This action is not supported yet!");
1521 case TargetLowering::Legal:
1522 // If this is an unaligned store and the target doesn't support it,
1524 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1525 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1526 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1527 if (ST->getAlignment() < ABIAlignment)
1528 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1532 case TargetLowering::Custom:
1533 Result = TLI.LowerOperation(Result, DAG);
1536 // TRUNCSTORE:i16 i32 -> STORE i16
1537 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1538 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1539 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1540 isVolatile, isNonTemporal, Alignment);
1548 assert(Result.getValueType() == Op.getValueType() &&
1549 "Bad legalization!");
1551 // Make sure that the generated code is itself legal.
1553 Result = LegalizeOp(Result);
1555 // Note that LegalizeOp may be reentered even from single-use nodes, which
1556 // means that we always must cache transformed nodes.
1557 AddLegalizedOperand(Op, Result);
1561 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1562 SDValue Vec = Op.getOperand(0);
1563 SDValue Idx = Op.getOperand(1);
1564 DebugLoc dl = Op.getDebugLoc();
1565 // Store the value to a temporary stack slot, then LOAD the returned part.
1566 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1567 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1568 MachinePointerInfo(), false, false, 0);
1570 // Add the offset to the index.
1572 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1573 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1574 DAG.getConstant(EltSize, Idx.getValueType()));
1576 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1577 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1579 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1581 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1583 if (Op.getValueType().isVector())
1584 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1586 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
1587 MachinePointerInfo(),
1588 Vec.getValueType().getVectorElementType(),
1592 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1593 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1595 SDValue Vec = Op.getOperand(0);
1596 SDValue Part = Op.getOperand(1);
1597 SDValue Idx = Op.getOperand(2);
1598 DebugLoc dl = Op.getDebugLoc();
1600 // Store the value to a temporary stack slot, then LOAD the returned part.
1602 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1603 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1604 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1606 // First store the whole vector.
1607 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1610 // Then store the inserted part.
1612 // Add the offset to the index.
1614 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1616 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1617 DAG.getConstant(EltSize, Idx.getValueType()));
1619 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1620 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1622 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1624 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1627 // Store the subvector.
1628 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1629 MachinePointerInfo(), false, false, 0);
1631 // Finally, load the updated vector.
1632 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1636 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1637 // We can't handle this case efficiently. Allocate a sufficiently
1638 // aligned object on the stack, store each element into it, then load
1639 // the result as a vector.
1640 // Create the stack frame object.
1641 EVT VT = Node->getValueType(0);
1642 EVT EltVT = VT.getVectorElementType();
1643 DebugLoc dl = Node->getDebugLoc();
1644 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1645 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1646 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1648 // Emit a store of each element to the stack slot.
1649 SmallVector<SDValue, 8> Stores;
1650 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1651 // Store (in the right endianness) the elements to memory.
1652 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1653 // Ignore undef elements.
1654 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1656 unsigned Offset = TypeByteSize*i;
1658 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1659 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1661 // If the destination vector element type is narrower than the source
1662 // element type, only store the bits necessary.
1663 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1664 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1665 Node->getOperand(i), Idx,
1666 PtrInfo.getWithOffset(Offset),
1667 EltVT, false, false, 0));
1669 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1670 Node->getOperand(i), Idx,
1671 PtrInfo.getWithOffset(Offset),
1676 if (!Stores.empty()) // Not all undef elements?
1677 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1678 &Stores[0], Stores.size());
1680 StoreChain = DAG.getEntryNode();
1682 // Result is a load from the stack slot.
1683 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1686 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1687 DebugLoc dl = Node->getDebugLoc();
1688 SDValue Tmp1 = Node->getOperand(0);
1689 SDValue Tmp2 = Node->getOperand(1);
1691 // Get the sign bit of the RHS. First obtain a value that has the same
1692 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1694 EVT FloatVT = Tmp2.getValueType();
1695 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1696 if (isTypeLegal(IVT)) {
1697 // Convert to an integer with the same sign bit.
1698 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1700 // Store the float to memory, then load the sign part out as an integer.
1701 MVT LoadTy = TLI.getPointerTy();
1702 // First create a temporary that is aligned for both the load and store.
1703 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1704 // Then store the float to it.
1706 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1708 if (TLI.isBigEndian()) {
1709 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1710 // Load out a legal integer with the same sign bit as the float.
1711 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1713 } else { // Little endian
1714 SDValue LoadPtr = StackPtr;
1715 // The float may be wider than the integer we are going to load. Advance
1716 // the pointer so that the loaded integer will contain the sign bit.
1717 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1718 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1719 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1720 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1721 // Load a legal integer containing the sign bit.
1722 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1724 // Move the sign bit to the top bit of the loaded integer.
1725 unsigned BitShift = LoadTy.getSizeInBits() -
1726 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1727 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1729 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1730 DAG.getConstant(BitShift,TLI.getShiftAmountTy()));
1733 // Now get the sign bit proper, by seeing whether the value is negative.
1734 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1735 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1737 // Get the absolute value of the result.
1738 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1739 // Select between the nabs and abs value based on the sign bit of
1741 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1742 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1746 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1747 SmallVectorImpl<SDValue> &Results) {
1748 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1749 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1750 " not tell us which reg is the stack pointer!");
1751 DebugLoc dl = Node->getDebugLoc();
1752 EVT VT = Node->getValueType(0);
1753 SDValue Tmp1 = SDValue(Node, 0);
1754 SDValue Tmp2 = SDValue(Node, 1);
1755 SDValue Tmp3 = Node->getOperand(2);
1756 SDValue Chain = Tmp1.getOperand(0);
1758 // Chain the dynamic stack allocation so that it doesn't modify the stack
1759 // pointer when other instructions are using the stack.
1760 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1762 SDValue Size = Tmp2.getOperand(1);
1763 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1764 Chain = SP.getValue(1);
1765 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1766 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1767 if (Align > StackAlign)
1768 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1769 DAG.getConstant(-(uint64_t)Align, VT));
1770 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1771 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1773 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1774 DAG.getIntPtrConstant(0, true), SDValue());
1776 Results.push_back(Tmp1);
1777 Results.push_back(Tmp2);
1780 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1781 /// condition code CC on the current target. This routine expands SETCC with
1782 /// illegal condition code into AND / OR of multiple SETCC values.
1783 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1784 SDValue &LHS, SDValue &RHS,
1787 EVT OpVT = LHS.getValueType();
1788 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1789 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1790 default: assert(0 && "Unknown condition code action!");
1791 case TargetLowering::Legal:
1794 case TargetLowering::Expand: {
1795 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1798 default: assert(0 && "Don't know how to expand this condition!");
1799 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1800 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1801 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1802 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1803 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1804 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1805 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1806 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1807 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1808 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1809 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1810 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1811 // FIXME: Implement more expansions.
1814 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1815 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1816 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1824 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1825 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1826 /// a load from the stack slot to DestVT, extending it if needed.
1827 /// The resultant code need not be legal.
1828 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1832 // Create the stack frame object.
1834 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1835 getTypeForEVT(*DAG.getContext()));
1836 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1838 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1839 int SPFI = StackPtrFI->getIndex();
1840 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1842 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1843 unsigned SlotSize = SlotVT.getSizeInBits();
1844 unsigned DestSize = DestVT.getSizeInBits();
1845 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1846 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1848 // Emit a store to the stack slot. Use a truncstore if the input value is
1849 // later than DestVT.
1852 if (SrcSize > SlotSize)
1853 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1854 PtrInfo, SlotVT, false, false, SrcAlign);
1856 assert(SrcSize == SlotSize && "Invalid store");
1857 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1858 PtrInfo, false, false, SrcAlign);
1861 // Result is a load from the stack slot.
1862 if (SlotSize == DestSize)
1863 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1864 false, false, DestAlign);
1866 assert(SlotSize < DestSize && "Unknown extension!");
1867 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr,
1868 PtrInfo, SlotVT, false, false, DestAlign);
1871 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1872 DebugLoc dl = Node->getDebugLoc();
1873 // Create a vector sized/aligned stack slot, store the value to element #0,
1874 // then load the whole vector back out.
1875 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1877 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1878 int SPFI = StackPtrFI->getIndex();
1880 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1882 MachinePointerInfo::getFixedStack(SPFI),
1883 Node->getValueType(0).getVectorElementType(),
1885 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1886 MachinePointerInfo::getFixedStack(SPFI),
1891 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1892 /// support the operation, but do support the resultant vector type.
1893 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1894 unsigned NumElems = Node->getNumOperands();
1895 SDValue Value1, Value2;
1896 DebugLoc dl = Node->getDebugLoc();
1897 EVT VT = Node->getValueType(0);
1898 EVT OpVT = Node->getOperand(0).getValueType();
1899 EVT EltVT = VT.getVectorElementType();
1901 // If the only non-undef value is the low element, turn this into a
1902 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1903 bool isOnlyLowElement = true;
1904 bool MoreThanTwoValues = false;
1905 bool isConstant = true;
1906 for (unsigned i = 0; i < NumElems; ++i) {
1907 SDValue V = Node->getOperand(i);
1908 if (V.getOpcode() == ISD::UNDEF)
1911 isOnlyLowElement = false;
1912 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1915 if (!Value1.getNode()) {
1917 } else if (!Value2.getNode()) {
1920 } else if (V != Value1 && V != Value2) {
1921 MoreThanTwoValues = true;
1925 if (!Value1.getNode())
1926 return DAG.getUNDEF(VT);
1928 if (isOnlyLowElement)
1929 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1931 // If all elements are constants, create a load from the constant pool.
1933 std::vector<Constant*> CV;
1934 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1935 if (ConstantFPSDNode *V =
1936 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1937 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1938 } else if (ConstantSDNode *V =
1939 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1941 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1943 // If OpVT and EltVT don't match, EltVT is not legal and the
1944 // element values have been promoted/truncated earlier. Undo this;
1945 // we don't want a v16i8 to become a v16i32 for example.
1946 const ConstantInt *CI = V->getConstantIntValue();
1947 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1948 CI->getZExtValue()));
1951 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1952 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1953 CV.push_back(UndefValue::get(OpNTy));
1956 Constant *CP = ConstantVector::get(CV);
1957 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1958 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1959 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1960 MachinePointerInfo::getConstantPool(),
1961 false, false, Alignment);
1964 if (!MoreThanTwoValues) {
1965 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1966 for (unsigned i = 0; i < NumElems; ++i) {
1967 SDValue V = Node->getOperand(i);
1968 if (V.getOpcode() == ISD::UNDEF)
1970 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1972 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1973 // Get the splatted value into the low element of a vector register.
1974 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1976 if (Value2.getNode())
1977 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1979 Vec2 = DAG.getUNDEF(VT);
1981 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1982 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1986 // Otherwise, we can't handle this case efficiently.
1987 return ExpandVectorBuildThroughStack(Node);
1990 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1991 // does not fit into a register, return the lo part and set the hi part to the
1992 // by-reg argument. If it does fit into a single register, return the result
1993 // and leave the Hi part unset.
1994 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1996 // The input chain to this libcall is the entry node of the function.
1997 // Legalizing the call will automatically add the previous call to the
1999 SDValue InChain = DAG.getEntryNode();
2001 TargetLowering::ArgListTy Args;
2002 TargetLowering::ArgListEntry Entry;
2003 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2004 EVT ArgVT = Node->getOperand(i).getValueType();
2005 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2006 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2007 Entry.isSExt = isSigned;
2008 Entry.isZExt = !isSigned;
2009 Args.push_back(Entry);
2011 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2012 TLI.getPointerTy());
2014 // Splice the libcall in wherever FindInputOutputChains tells us to.
2015 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2017 // isTailCall may be true since the callee does not reference caller stack
2018 // frame. Check if it's in the right position.
2019 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2020 std::pair<SDValue, SDValue> CallInfo =
2021 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2022 0, TLI.getLibcallCallingConv(LC), isTailCall,
2023 /*isReturnValueUsed=*/true,
2024 Callee, Args, DAG, Node->getDebugLoc());
2026 if (!CallInfo.second.getNode())
2027 // It's a tailcall, return the chain (which is the DAG root).
2028 return DAG.getRoot();
2030 // Legalize the call sequence, starting with the chain. This will advance
2031 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2032 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2033 LegalizeOp(CallInfo.second);
2034 return CallInfo.first;
2037 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2038 // ExpandLibCall except that the first operand is the in-chain.
2039 std::pair<SDValue, SDValue>
2040 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2043 SDValue InChain = Node->getOperand(0);
2045 TargetLowering::ArgListTy Args;
2046 TargetLowering::ArgListEntry Entry;
2047 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2048 EVT ArgVT = Node->getOperand(i).getValueType();
2049 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2050 Entry.Node = Node->getOperand(i);
2052 Entry.isSExt = isSigned;
2053 Entry.isZExt = !isSigned;
2054 Args.push_back(Entry);
2056 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2057 TLI.getPointerTy());
2059 // Splice the libcall in wherever FindInputOutputChains tells us to.
2060 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2061 std::pair<SDValue, SDValue> CallInfo =
2062 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2063 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2064 /*isReturnValueUsed=*/true,
2065 Callee, Args, DAG, Node->getDebugLoc());
2067 // Legalize the call sequence, starting with the chain. This will advance
2068 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2069 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2070 LegalizeOp(CallInfo.second);
2074 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2075 RTLIB::Libcall Call_F32,
2076 RTLIB::Libcall Call_F64,
2077 RTLIB::Libcall Call_F80,
2078 RTLIB::Libcall Call_PPCF128) {
2080 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2081 default: assert(0 && "Unexpected request for libcall!");
2082 case MVT::f32: LC = Call_F32; break;
2083 case MVT::f64: LC = Call_F64; break;
2084 case MVT::f80: LC = Call_F80; break;
2085 case MVT::ppcf128: LC = Call_PPCF128; break;
2087 return ExpandLibCall(LC, Node, false);
2090 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2091 RTLIB::Libcall Call_I8,
2092 RTLIB::Libcall Call_I16,
2093 RTLIB::Libcall Call_I32,
2094 RTLIB::Libcall Call_I64,
2095 RTLIB::Libcall Call_I128) {
2097 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2098 default: assert(0 && "Unexpected request for libcall!");
2099 case MVT::i8: LC = Call_I8; break;
2100 case MVT::i16: LC = Call_I16; break;
2101 case MVT::i32: LC = Call_I32; break;
2102 case MVT::i64: LC = Call_I64; break;
2103 case MVT::i128: LC = Call_I128; break;
2105 return ExpandLibCall(LC, Node, isSigned);
2108 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2109 /// INT_TO_FP operation of the specified operand when the target requests that
2110 /// we expand it. At this point, we know that the result and operand types are
2111 /// legal for the target.
2112 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2116 if (Op0.getValueType() == MVT::i32) {
2117 // simple 32-bit [signed|unsigned] integer to float/double expansion
2119 // Get the stack frame index of a 8 byte buffer.
2120 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2122 // word offset constant for Hi/Lo address computation
2123 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2124 // set up Hi and Lo (into buffer) address based on endian
2125 SDValue Hi = StackSlot;
2126 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2127 TLI.getPointerTy(), StackSlot, WordOff);
2128 if (TLI.isLittleEndian())
2131 // if signed map to unsigned space
2134 // constant used to invert sign bit (signed to unsigned mapping)
2135 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2136 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2140 // store the lo of the constructed double - based on integer input
2141 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2142 Op0Mapped, Lo, MachinePointerInfo(),
2144 // initial hi portion of constructed double
2145 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2146 // store the hi of the constructed double - biased exponent
2147 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2148 MachinePointerInfo(),
2150 // load the constructed double
2151 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2152 MachinePointerInfo(), false, false, 0);
2153 // FP constant to bias correct the final result
2154 SDValue Bias = DAG.getConstantFP(isSigned ?
2155 BitsToDouble(0x4330000080000000ULL) :
2156 BitsToDouble(0x4330000000000000ULL),
2158 // subtract the bias
2159 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2162 // handle final rounding
2163 if (DestVT == MVT::f64) {
2166 } else if (DestVT.bitsLT(MVT::f64)) {
2167 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2168 DAG.getIntPtrConstant(0));
2169 } else if (DestVT.bitsGT(MVT::f64)) {
2170 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2174 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2175 // Code below here assumes !isSigned without checking again.
2177 // Implementation of unsigned i64 to f64 following the algorithm in
2178 // __floatundidf in compiler_rt. This implementation has the advantage
2179 // of performing rounding correctly, both in the default rounding mode
2180 // and in all alternate rounding modes.
2181 // TODO: Generalize this for use with other types.
2182 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2184 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2185 SDValue TwoP84PlusTwoP52 =
2186 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2188 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2190 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2191 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2192 DAG.getConstant(32, MVT::i64));
2193 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2194 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2195 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2196 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2197 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2199 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2202 // Implementation of unsigned i64 to f32.
2203 // TODO: Generalize this for use with other types.
2204 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2205 // For unsigned conversions, convert them to signed conversions using the
2206 // algorithm from the x86_64 __floatundidf in compiler_rt.
2208 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2210 SDValue ShiftConst = DAG.getConstant(1, TLI.getShiftAmountTy());
2211 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2212 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2213 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2214 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2216 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2217 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2219 // TODO: This really should be implemented using a branch rather than a
2220 // select. We happen to get lucky and machinesink does the right
2221 // thing most of the time. This would be a good candidate for a
2222 //pseudo-op, or, even better, for whole-function isel.
2223 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2224 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2225 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2228 // Otherwise, implement the fully general conversion.
2229 EVT SHVT = TLI.getShiftAmountTy();
2231 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2232 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2233 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2234 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2235 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2236 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2237 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2238 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2239 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2240 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2241 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2243 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2245 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2246 DAG.getConstant(32, SHVT));
2247 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2248 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2250 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2251 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2252 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2253 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2254 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2255 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2256 DAG.getIntPtrConstant(0));
2259 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2261 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2262 Op0, DAG.getConstant(0, Op0.getValueType()),
2264 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2265 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2266 SignSet, Four, Zero);
2268 // If the sign bit of the integer is set, the large number will be treated
2269 // as a negative number. To counteract this, the dynamic code adds an
2270 // offset depending on the data type.
2272 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2273 default: assert(0 && "Unsupported integer type!");
2274 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2275 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2276 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2277 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2279 if (TLI.isLittleEndian()) FF <<= 32;
2280 Constant *FudgeFactor = ConstantInt::get(
2281 Type::getInt64Ty(*DAG.getContext()), FF);
2283 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2284 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2285 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2286 Alignment = std::min(Alignment, 4u);
2288 if (DestVT == MVT::f32)
2289 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2290 MachinePointerInfo::getConstantPool(),
2291 false, false, Alignment);
2294 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
2295 DAG.getEntryNode(), CPIdx,
2296 MachinePointerInfo::getConstantPool(),
2297 MVT::f32, false, false, Alignment));
2300 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2303 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2304 /// *INT_TO_FP operation of the specified operand when the target requests that
2305 /// we promote it. At this point, we know that the result and operand types are
2306 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2307 /// operation that takes a larger input.
2308 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2312 // First step, figure out the appropriate *INT_TO_FP operation to use.
2313 EVT NewInTy = LegalOp.getValueType();
2315 unsigned OpToUse = 0;
2317 // Scan for the appropriate larger type to use.
2319 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2320 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2322 // If the target supports SINT_TO_FP of this type, use it.
2323 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2324 OpToUse = ISD::SINT_TO_FP;
2327 if (isSigned) continue;
2329 // If the target supports UINT_TO_FP of this type, use it.
2330 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2331 OpToUse = ISD::UINT_TO_FP;
2335 // Otherwise, try a larger type.
2338 // Okay, we found the operation and type to use. Zero extend our input to the
2339 // desired type then run the operation on it.
2340 return DAG.getNode(OpToUse, dl, DestVT,
2341 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2342 dl, NewInTy, LegalOp));
2345 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2346 /// FP_TO_*INT operation of the specified operand when the target requests that
2347 /// we promote it. At this point, we know that the result and operand types are
2348 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2349 /// operation that returns a larger result.
2350 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2354 // First step, figure out the appropriate FP_TO*INT operation to use.
2355 EVT NewOutTy = DestVT;
2357 unsigned OpToUse = 0;
2359 // Scan for the appropriate larger type to use.
2361 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2362 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2364 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2365 OpToUse = ISD::FP_TO_SINT;
2369 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2370 OpToUse = ISD::FP_TO_UINT;
2374 // Otherwise, try a larger type.
2378 // Okay, we found the operation and type to use.
2379 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2381 // Truncate the result of the extended FP_TO_*INT operation to the desired
2383 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2386 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2388 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2389 EVT VT = Op.getValueType();
2390 EVT SHVT = TLI.getShiftAmountTy();
2391 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2392 switch (VT.getSimpleVT().SimpleTy) {
2393 default: assert(0 && "Unhandled Expand type in BSWAP!");
2395 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2396 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2397 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2399 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2400 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2401 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2402 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2403 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2404 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2405 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2406 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2407 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2409 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2410 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2411 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2412 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2413 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2414 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2415 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2416 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2417 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2418 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2419 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2420 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2421 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2422 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2423 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2424 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2425 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2426 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2427 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2428 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2429 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2433 /// SplatByte - Distribute ByteVal over NumBits bits.
2434 // FIXME: Move this helper to a common place.
2435 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2436 APInt Val = APInt(NumBits, ByteVal);
2438 for (unsigned i = NumBits; i > 8; i >>= 1) {
2439 Val = (Val << Shift) | Val;
2445 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2447 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2450 default: assert(0 && "Cannot expand this yet!");
2452 EVT VT = Op.getValueType();
2453 EVT ShVT = TLI.getShiftAmountTy();
2454 unsigned Len = VT.getSizeInBits();
2456 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2457 "CTPOP not implemented for this type.");
2459 // This is the "best" algorithm from
2460 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2462 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2463 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2464 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2465 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2467 // v = v - ((v >> 1) & 0x55555555...)
2468 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2469 DAG.getNode(ISD::AND, dl, VT,
2470 DAG.getNode(ISD::SRL, dl, VT, Op,
2471 DAG.getConstant(1, ShVT)),
2473 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2474 Op = DAG.getNode(ISD::ADD, dl, VT,
2475 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2476 DAG.getNode(ISD::AND, dl, VT,
2477 DAG.getNode(ISD::SRL, dl, VT, Op,
2478 DAG.getConstant(2, ShVT)),
2480 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2481 Op = DAG.getNode(ISD::AND, dl, VT,
2482 DAG.getNode(ISD::ADD, dl, VT, Op,
2483 DAG.getNode(ISD::SRL, dl, VT, Op,
2484 DAG.getConstant(4, ShVT))),
2486 // v = (v * 0x01010101...) >> (Len - 8)
2487 Op = DAG.getNode(ISD::SRL, dl, VT,
2488 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2489 DAG.getConstant(Len - 8, ShVT));
2494 // for now, we do this:
2495 // x = x | (x >> 1);
2496 // x = x | (x >> 2);
2498 // x = x | (x >>16);
2499 // x = x | (x >>32); // for 64-bit input
2500 // return popcount(~x);
2502 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2503 EVT VT = Op.getValueType();
2504 EVT ShVT = TLI.getShiftAmountTy();
2505 unsigned len = VT.getSizeInBits();
2506 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2507 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2508 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2509 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2511 Op = DAG.getNOT(dl, Op, VT);
2512 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2515 // for now, we use: { return popcount(~x & (x - 1)); }
2516 // unless the target has ctlz but not ctpop, in which case we use:
2517 // { return 32 - nlz(~x & (x-1)); }
2518 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2519 EVT VT = Op.getValueType();
2520 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2521 DAG.getNOT(dl, Op, VT),
2522 DAG.getNode(ISD::SUB, dl, VT, Op,
2523 DAG.getConstant(1, VT)));
2524 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2525 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2526 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2527 return DAG.getNode(ISD::SUB, dl, VT,
2528 DAG.getConstant(VT.getSizeInBits(), VT),
2529 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2530 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2535 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2536 unsigned Opc = Node->getOpcode();
2537 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2542 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2544 case ISD::ATOMIC_SWAP:
2545 switch (VT.SimpleTy) {
2546 default: llvm_unreachable("Unexpected value type for atomic!");
2547 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2548 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2549 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2550 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2553 case ISD::ATOMIC_CMP_SWAP:
2554 switch (VT.SimpleTy) {
2555 default: llvm_unreachable("Unexpected value type for atomic!");
2556 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2557 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2558 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2559 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2562 case ISD::ATOMIC_LOAD_ADD:
2563 switch (VT.SimpleTy) {
2564 default: llvm_unreachable("Unexpected value type for atomic!");
2565 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2566 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2567 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2568 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2571 case ISD::ATOMIC_LOAD_SUB:
2572 switch (VT.SimpleTy) {
2573 default: llvm_unreachable("Unexpected value type for atomic!");
2574 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2575 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2576 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2577 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2580 case ISD::ATOMIC_LOAD_AND:
2581 switch (VT.SimpleTy) {
2582 default: llvm_unreachable("Unexpected value type for atomic!");
2583 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2584 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2585 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2586 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2589 case ISD::ATOMIC_LOAD_OR:
2590 switch (VT.SimpleTy) {
2591 default: llvm_unreachable("Unexpected value type for atomic!");
2592 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2593 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2594 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2595 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2598 case ISD::ATOMIC_LOAD_XOR:
2599 switch (VT.SimpleTy) {
2600 default: llvm_unreachable("Unexpected value type for atomic!");
2601 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2602 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2603 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2604 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2607 case ISD::ATOMIC_LOAD_NAND:
2608 switch (VT.SimpleTy) {
2609 default: llvm_unreachable("Unexpected value type for atomic!");
2610 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2611 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2612 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2613 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2618 return ExpandChainLibCall(LC, Node, false);
2621 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2622 SmallVectorImpl<SDValue> &Results) {
2623 DebugLoc dl = Node->getDebugLoc();
2624 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2625 switch (Node->getOpcode()) {
2629 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2630 Results.push_back(Tmp1);
2633 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2635 case ISD::FRAMEADDR:
2636 case ISD::RETURNADDR:
2637 case ISD::FRAME_TO_ARGS_OFFSET:
2638 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2640 case ISD::FLT_ROUNDS_:
2641 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2643 case ISD::EH_RETURN:
2647 case ISD::EH_SJLJ_LONGJMP:
2648 case ISD::EH_SJLJ_DISPATCHSETUP:
2649 // If the target didn't expand these, there's nothing to do, so just
2650 // preserve the chain and be done.
2651 Results.push_back(Node->getOperand(0));
2653 case ISD::EH_SJLJ_SETJMP:
2654 // If the target didn't expand this, just return 'zero' and preserve the
2656 Results.push_back(DAG.getConstant(0, MVT::i32));
2657 Results.push_back(Node->getOperand(0));
2659 case ISD::MEMBARRIER: {
2660 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2661 TargetLowering::ArgListTy Args;
2662 std::pair<SDValue, SDValue> CallResult =
2663 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2664 false, false, false, false, 0, CallingConv::C,
2665 /*isTailCall=*/false,
2666 /*isReturnValueUsed=*/true,
2667 DAG.getExternalSymbol("__sync_synchronize",
2668 TLI.getPointerTy()),
2670 Results.push_back(CallResult.second);
2673 // By default, atomic intrinsics are marked Legal and lowered. Targets
2674 // which don't support them directly, however, may want libcalls, in which
2675 // case they mark them Expand, and we get here.
2676 case ISD::ATOMIC_SWAP:
2677 case ISD::ATOMIC_LOAD_ADD:
2678 case ISD::ATOMIC_LOAD_SUB:
2679 case ISD::ATOMIC_LOAD_AND:
2680 case ISD::ATOMIC_LOAD_OR:
2681 case ISD::ATOMIC_LOAD_XOR:
2682 case ISD::ATOMIC_LOAD_NAND:
2683 case ISD::ATOMIC_LOAD_MIN:
2684 case ISD::ATOMIC_LOAD_MAX:
2685 case ISD::ATOMIC_LOAD_UMIN:
2686 case ISD::ATOMIC_LOAD_UMAX:
2687 case ISD::ATOMIC_CMP_SWAP: {
2688 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2689 Results.push_back(Tmp.first);
2690 Results.push_back(Tmp.second);
2693 case ISD::DYNAMIC_STACKALLOC:
2694 ExpandDYNAMIC_STACKALLOC(Node, Results);
2696 case ISD::MERGE_VALUES:
2697 for (unsigned i = 0; i < Node->getNumValues(); i++)
2698 Results.push_back(Node->getOperand(i));
2701 EVT VT = Node->getValueType(0);
2703 Results.push_back(DAG.getConstant(0, VT));
2705 assert(VT.isFloatingPoint() && "Unknown value type!");
2706 Results.push_back(DAG.getConstantFP(0, VT));
2711 // If this operation is not supported, lower it to 'abort()' call
2712 TargetLowering::ArgListTy Args;
2713 std::pair<SDValue, SDValue> CallResult =
2714 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2715 false, false, false, false, 0, CallingConv::C,
2716 /*isTailCall=*/false,
2717 /*isReturnValueUsed=*/true,
2718 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2720 Results.push_back(CallResult.second);
2725 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2726 Node->getValueType(0), dl);
2727 Results.push_back(Tmp1);
2729 case ISD::FP_EXTEND:
2730 Tmp1 = EmitStackConvert(Node->getOperand(0),
2731 Node->getOperand(0).getValueType(),
2732 Node->getValueType(0), dl);
2733 Results.push_back(Tmp1);
2735 case ISD::SIGN_EXTEND_INREG: {
2736 // NOTE: we could fall back on load/store here too for targets without
2737 // SAR. However, it is doubtful that any exist.
2738 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2739 EVT VT = Node->getValueType(0);
2740 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2743 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2744 ExtraVT.getScalarType().getSizeInBits();
2745 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2746 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2747 Node->getOperand(0), ShiftCst);
2748 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2749 Results.push_back(Tmp1);
2752 case ISD::FP_ROUND_INREG: {
2753 // The only way we can lower this is to turn it into a TRUNCSTORE,
2754 // EXTLOAD pair, targetting a temporary location (a stack slot).
2756 // NOTE: there is a choice here between constantly creating new stack
2757 // slots and always reusing the same one. We currently always create
2758 // new ones, as reuse may inhibit scheduling.
2759 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2760 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2761 Node->getValueType(0), dl);
2762 Results.push_back(Tmp1);
2765 case ISD::SINT_TO_FP:
2766 case ISD::UINT_TO_FP:
2767 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2768 Node->getOperand(0), Node->getValueType(0), dl);
2769 Results.push_back(Tmp1);
2771 case ISD::FP_TO_UINT: {
2772 SDValue True, False;
2773 EVT VT = Node->getOperand(0).getValueType();
2774 EVT NVT = Node->getValueType(0);
2775 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2776 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2777 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2778 Tmp1 = DAG.getConstantFP(apf, VT);
2779 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2780 Node->getOperand(0),
2782 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2783 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2784 DAG.getNode(ISD::FSUB, dl, VT,
2785 Node->getOperand(0), Tmp1));
2786 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2787 DAG.getConstant(x, NVT));
2788 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2789 Results.push_back(Tmp1);
2793 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2794 EVT VT = Node->getValueType(0);
2795 Tmp1 = Node->getOperand(0);
2796 Tmp2 = Node->getOperand(1);
2797 unsigned Align = Node->getConstantOperandVal(3);
2799 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2800 MachinePointerInfo(V), false, false, 0);
2801 SDValue VAList = VAListLoad;
2803 if (Align > TLI.getMinStackArgumentAlignment()) {
2804 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2806 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2807 DAG.getConstant(Align - 1,
2808 TLI.getPointerTy()));
2810 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2811 DAG.getConstant(-(int64_t)Align,
2812 TLI.getPointerTy()));
2815 // Increment the pointer, VAList, to the next vaarg
2816 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2817 DAG.getConstant(TLI.getTargetData()->
2818 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2819 TLI.getPointerTy()));
2820 // Store the incremented VAList to the legalized pointer
2821 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2822 MachinePointerInfo(V), false, false, 0);
2823 // Load the actual argument out of the pointer VAList
2824 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2826 Results.push_back(Results[0].getValue(1));
2830 // This defaults to loading a pointer from the input and storing it to the
2831 // output, returning the chain.
2832 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2833 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2834 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2835 Node->getOperand(2), MachinePointerInfo(VS),
2837 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2838 MachinePointerInfo(VD), false, false, 0);
2839 Results.push_back(Tmp1);
2842 case ISD::EXTRACT_VECTOR_ELT:
2843 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2844 // This must be an access of the only element. Return it.
2845 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2846 Node->getOperand(0));
2848 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2849 Results.push_back(Tmp1);
2851 case ISD::EXTRACT_SUBVECTOR:
2852 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2854 case ISD::INSERT_SUBVECTOR:
2855 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
2857 case ISD::CONCAT_VECTORS: {
2858 Results.push_back(ExpandVectorBuildThroughStack(Node));
2861 case ISD::SCALAR_TO_VECTOR:
2862 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2864 case ISD::INSERT_VECTOR_ELT:
2865 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2866 Node->getOperand(1),
2867 Node->getOperand(2), dl));
2869 case ISD::VECTOR_SHUFFLE: {
2870 SmallVector<int, 8> Mask;
2871 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2873 EVT VT = Node->getValueType(0);
2874 EVT EltVT = VT.getVectorElementType();
2875 if (getTypeAction(EltVT) == Promote)
2876 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2877 unsigned NumElems = VT.getVectorNumElements();
2878 SmallVector<SDValue, 8> Ops;
2879 for (unsigned i = 0; i != NumElems; ++i) {
2881 Ops.push_back(DAG.getUNDEF(EltVT));
2884 unsigned Idx = Mask[i];
2886 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2887 Node->getOperand(0),
2888 DAG.getIntPtrConstant(Idx)));
2890 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2891 Node->getOperand(1),
2892 DAG.getIntPtrConstant(Idx - NumElems)));
2894 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2895 Results.push_back(Tmp1);
2898 case ISD::EXTRACT_ELEMENT: {
2899 EVT OpTy = Node->getOperand(0).getValueType();
2900 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2902 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2903 DAG.getConstant(OpTy.getSizeInBits()/2,
2904 TLI.getShiftAmountTy()));
2905 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2908 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2909 Node->getOperand(0));
2911 Results.push_back(Tmp1);
2914 case ISD::STACKSAVE:
2915 // Expand to CopyFromReg if the target set
2916 // StackPointerRegisterToSaveRestore.
2917 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2918 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2919 Node->getValueType(0)));
2920 Results.push_back(Results[0].getValue(1));
2922 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2923 Results.push_back(Node->getOperand(0));
2926 case ISD::STACKRESTORE:
2927 // Expand to CopyToReg if the target set
2928 // StackPointerRegisterToSaveRestore.
2929 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2930 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2931 Node->getOperand(1)));
2933 Results.push_back(Node->getOperand(0));
2936 case ISD::FCOPYSIGN:
2937 Results.push_back(ExpandFCOPYSIGN(Node));
2940 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2941 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2942 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2943 Node->getOperand(0));
2944 Results.push_back(Tmp1);
2947 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2948 EVT VT = Node->getValueType(0);
2949 Tmp1 = Node->getOperand(0);
2950 Tmp2 = DAG.getConstantFP(0.0, VT);
2951 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2952 Tmp1, Tmp2, ISD::SETUGT);
2953 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2954 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2955 Results.push_back(Tmp1);
2959 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2960 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2963 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2964 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2967 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2968 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2971 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2972 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2975 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2976 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2979 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2980 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2983 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2984 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2987 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2988 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2991 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2992 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2995 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2996 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2999 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3000 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3003 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3004 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3006 case ISD::FNEARBYINT:
3007 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3008 RTLIB::NEARBYINT_F64,
3009 RTLIB::NEARBYINT_F80,
3010 RTLIB::NEARBYINT_PPCF128));
3013 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3014 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3017 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3018 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3021 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3022 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3025 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3026 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3028 case ISD::FP16_TO_FP32:
3029 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3031 case ISD::FP32_TO_FP16:
3032 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3034 case ISD::ConstantFP: {
3035 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3036 // Check to see if this FP immediate is already legal.
3037 // If this is a legal constant, turn it into a TargetConstantFP node.
3038 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3039 Results.push_back(SDValue(Node, 0));
3041 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3044 case ISD::EHSELECTION: {
3045 unsigned Reg = TLI.getExceptionSelectorRegister();
3046 assert(Reg && "Can't expand to unknown register!");
3047 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3048 Node->getValueType(0)));
3049 Results.push_back(Results[0].getValue(1));
3052 case ISD::EXCEPTIONADDR: {
3053 unsigned Reg = TLI.getExceptionAddressRegister();
3054 assert(Reg && "Can't expand to unknown register!");
3055 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3056 Node->getValueType(0)));
3057 Results.push_back(Results[0].getValue(1));
3061 EVT VT = Node->getValueType(0);
3062 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3063 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3064 "Don't know how to expand this subtraction!");
3065 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3066 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3067 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3068 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3073 EVT VT = Node->getValueType(0);
3074 SDVTList VTs = DAG.getVTList(VT, VT);
3075 bool isSigned = Node->getOpcode() == ISD::SREM;
3076 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3077 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3078 Tmp2 = Node->getOperand(0);
3079 Tmp3 = Node->getOperand(1);
3080 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3081 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3082 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3084 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3085 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3086 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3087 } else if (isSigned) {
3088 Tmp1 = ExpandIntLibCall(Node, true,
3090 RTLIB::SREM_I16, RTLIB::SREM_I32,
3091 RTLIB::SREM_I64, RTLIB::SREM_I128);
3093 Tmp1 = ExpandIntLibCall(Node, false,
3095 RTLIB::UREM_I16, RTLIB::UREM_I32,
3096 RTLIB::UREM_I64, RTLIB::UREM_I128);
3098 Results.push_back(Tmp1);
3103 bool isSigned = Node->getOpcode() == ISD::SDIV;
3104 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3105 EVT VT = Node->getValueType(0);
3106 SDVTList VTs = DAG.getVTList(VT, VT);
3107 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
3108 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3109 Node->getOperand(1));
3111 Tmp1 = ExpandIntLibCall(Node, true,
3113 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3114 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3116 Tmp1 = ExpandIntLibCall(Node, false,
3118 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3119 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3120 Results.push_back(Tmp1);
3125 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3127 EVT VT = Node->getValueType(0);
3128 SDVTList VTs = DAG.getVTList(VT, VT);
3129 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3130 "If this wasn't legal, it shouldn't have been created!");
3131 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3132 Node->getOperand(1));
3133 Results.push_back(Tmp1.getValue(1));
3137 EVT VT = Node->getValueType(0);
3138 SDVTList VTs = DAG.getVTList(VT, VT);
3139 // See if multiply or divide can be lowered using two-result operations.
3140 // We just need the low half of the multiply; try both the signed
3141 // and unsigned forms. If the target supports both SMUL_LOHI and
3142 // UMUL_LOHI, form a preference by checking which forms of plain
3143 // MULH it supports.
3144 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3145 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3146 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3147 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3148 unsigned OpToUse = 0;
3149 if (HasSMUL_LOHI && !HasMULHS) {
3150 OpToUse = ISD::SMUL_LOHI;
3151 } else if (HasUMUL_LOHI && !HasMULHU) {
3152 OpToUse = ISD::UMUL_LOHI;
3153 } else if (HasSMUL_LOHI) {
3154 OpToUse = ISD::SMUL_LOHI;
3155 } else if (HasUMUL_LOHI) {
3156 OpToUse = ISD::UMUL_LOHI;
3159 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3160 Node->getOperand(1)));
3163 Tmp1 = ExpandIntLibCall(Node, false,
3165 RTLIB::MUL_I16, RTLIB::MUL_I32,
3166 RTLIB::MUL_I64, RTLIB::MUL_I128);
3167 Results.push_back(Tmp1);
3172 SDValue LHS = Node->getOperand(0);
3173 SDValue RHS = Node->getOperand(1);
3174 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3175 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3177 Results.push_back(Sum);
3178 EVT OType = Node->getValueType(1);
3180 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3182 // LHSSign -> LHS >= 0
3183 // RHSSign -> RHS >= 0
3184 // SumSign -> Sum >= 0
3187 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3189 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3191 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3192 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3193 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3194 Node->getOpcode() == ISD::SADDO ?
3195 ISD::SETEQ : ISD::SETNE);
3197 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3198 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3200 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3201 Results.push_back(Cmp);
3206 SDValue LHS = Node->getOperand(0);
3207 SDValue RHS = Node->getOperand(1);
3208 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3209 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3211 Results.push_back(Sum);
3212 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3213 Node->getOpcode () == ISD::UADDO ?
3214 ISD::SETULT : ISD::SETUGT));
3219 EVT VT = Node->getValueType(0);
3220 SDValue LHS = Node->getOperand(0);
3221 SDValue RHS = Node->getOperand(1);
3224 static const unsigned Ops[2][3] =
3225 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3226 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3227 bool isSigned = Node->getOpcode() == ISD::SMULO;
3228 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3229 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3230 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3231 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3232 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3234 TopHalf = BottomHalf.getValue(1);
3235 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3236 VT.getSizeInBits() * 2))) {
3237 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3238 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3239 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3240 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3241 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3242 DAG.getIntPtrConstant(0));
3243 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3244 DAG.getIntPtrConstant(1));
3246 // We can fall back to a libcall with an illegal type for the MUL if we
3247 // have a libcall big enough.
3248 // Also, we can fall back to a division in some cases, but that's a big
3249 // performance hit in the general case.
3250 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3251 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3252 if (WideVT == MVT::i16)
3253 LC = RTLIB::MUL_I16;
3254 else if (WideVT == MVT::i32)
3255 LC = RTLIB::MUL_I32;
3256 else if (WideVT == MVT::i64)
3257 LC = RTLIB::MUL_I64;
3258 else if (WideVT == MVT::i128)
3259 LC = RTLIB::MUL_I128;
3260 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3261 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3262 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3264 SDValue Ret = ExpandLibCall(LC, Node, isSigned);
3265 BottomHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, Ret);
3266 TopHalf = DAG.getNode(ISD::SRL, dl, Ret.getValueType(), Ret,
3267 DAG.getConstant(VT.getSizeInBits(), TLI.getPointerTy()));
3268 TopHalf = DAG.getNode(ISD::TRUNCATE, dl, VT, TopHalf);
3271 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
3272 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3273 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3276 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3277 DAG.getConstant(0, VT), ISD::SETNE);
3279 Results.push_back(BottomHalf);
3280 Results.push_back(TopHalf);
3283 case ISD::BUILD_PAIR: {
3284 EVT PairTy = Node->getValueType(0);
3285 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3286 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3287 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3288 DAG.getConstant(PairTy.getSizeInBits()/2,
3289 TLI.getShiftAmountTy()));
3290 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3294 Tmp1 = Node->getOperand(0);
3295 Tmp2 = Node->getOperand(1);
3296 Tmp3 = Node->getOperand(2);
3297 if (Tmp1.getOpcode() == ISD::SETCC) {
3298 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3300 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3302 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3303 DAG.getConstant(0, Tmp1.getValueType()),
3304 Tmp2, Tmp3, ISD::SETNE);
3306 Results.push_back(Tmp1);
3309 SDValue Chain = Node->getOperand(0);
3310 SDValue Table = Node->getOperand(1);
3311 SDValue Index = Node->getOperand(2);
3313 EVT PTy = TLI.getPointerTy();
3315 const TargetData &TD = *TLI.getTargetData();
3316 unsigned EntrySize =
3317 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3319 Index = DAG.getNode(ISD::MUL, dl, PTy,
3320 Index, DAG.getConstant(EntrySize, PTy));
3321 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3323 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3324 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
3325 MachinePointerInfo::getJumpTable(), MemVT,
3328 if (TM.getRelocationModel() == Reloc::PIC_) {
3329 // For PIC, the sequence is:
3330 // BRIND(load(Jumptable + index) + RelocBase)
3331 // RelocBase can be JumpTable, GOT or some sort of global base.
3332 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3333 TLI.getPICJumpTableRelocBase(Table, DAG));
3335 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3336 Results.push_back(Tmp1);
3340 // Expand brcond's setcc into its constituent parts and create a BR_CC
3342 Tmp1 = Node->getOperand(0);
3343 Tmp2 = Node->getOperand(1);
3344 if (Tmp2.getOpcode() == ISD::SETCC) {
3345 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3346 Tmp1, Tmp2.getOperand(2),
3347 Tmp2.getOperand(0), Tmp2.getOperand(1),
3348 Node->getOperand(2));
3350 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3351 DAG.getCondCode(ISD::SETNE), Tmp2,
3352 DAG.getConstant(0, Tmp2.getValueType()),
3353 Node->getOperand(2));
3355 Results.push_back(Tmp1);
3358 Tmp1 = Node->getOperand(0);
3359 Tmp2 = Node->getOperand(1);
3360 Tmp3 = Node->getOperand(2);
3361 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3363 // If we expanded the SETCC into an AND/OR, return the new node
3364 if (Tmp2.getNode() == 0) {
3365 Results.push_back(Tmp1);
3369 // Otherwise, SETCC for the given comparison type must be completely
3370 // illegal; expand it into a SELECT_CC.
3371 EVT VT = Node->getValueType(0);
3372 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3373 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3374 Results.push_back(Tmp1);
3377 case ISD::SELECT_CC: {
3378 Tmp1 = Node->getOperand(0); // LHS
3379 Tmp2 = Node->getOperand(1); // RHS
3380 Tmp3 = Node->getOperand(2); // True
3381 Tmp4 = Node->getOperand(3); // False
3382 SDValue CC = Node->getOperand(4);
3384 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3385 Tmp1, Tmp2, CC, dl);
3387 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3388 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3389 CC = DAG.getCondCode(ISD::SETNE);
3390 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3392 Results.push_back(Tmp1);
3396 Tmp1 = Node->getOperand(0); // Chain
3397 Tmp2 = Node->getOperand(2); // LHS
3398 Tmp3 = Node->getOperand(3); // RHS
3399 Tmp4 = Node->getOperand(1); // CC
3401 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3402 Tmp2, Tmp3, Tmp4, dl);
3403 LastCALLSEQ_END = DAG.getEntryNode();
3405 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3406 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3407 Tmp4 = DAG.getCondCode(ISD::SETNE);
3408 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3409 Tmp3, Node->getOperand(4));
3410 Results.push_back(Tmp1);
3413 case ISD::GLOBAL_OFFSET_TABLE:
3414 case ISD::GlobalAddress:
3415 case ISD::GlobalTLSAddress:
3416 case ISD::ExternalSymbol:
3417 case ISD::ConstantPool:
3418 case ISD::JumpTable:
3419 case ISD::INTRINSIC_W_CHAIN:
3420 case ISD::INTRINSIC_WO_CHAIN:
3421 case ISD::INTRINSIC_VOID:
3422 // FIXME: Custom lowering for these operations shouldn't return null!
3423 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3424 Results.push_back(SDValue(Node, i));
3428 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3429 SmallVectorImpl<SDValue> &Results) {
3430 EVT OVT = Node->getValueType(0);
3431 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3432 Node->getOpcode() == ISD::SINT_TO_FP ||
3433 Node->getOpcode() == ISD::SETCC) {
3434 OVT = Node->getOperand(0).getValueType();
3436 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3437 DebugLoc dl = Node->getDebugLoc();
3438 SDValue Tmp1, Tmp2, Tmp3;
3439 switch (Node->getOpcode()) {
3443 // Zero extend the argument.
3444 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3445 // Perform the larger operation.
3446 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3447 if (Node->getOpcode() == ISD::CTTZ) {
3448 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3449 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3450 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3452 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3453 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3454 } else if (Node->getOpcode() == ISD::CTLZ) {
3455 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3456 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3457 DAG.getConstant(NVT.getSizeInBits() -
3458 OVT.getSizeInBits(), NVT));
3460 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3463 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3464 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3465 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3466 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3467 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3468 Results.push_back(Tmp1);
3471 case ISD::FP_TO_UINT:
3472 case ISD::FP_TO_SINT:
3473 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3474 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3475 Results.push_back(Tmp1);
3477 case ISD::UINT_TO_FP:
3478 case ISD::SINT_TO_FP:
3479 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3480 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3481 Results.push_back(Tmp1);
3486 unsigned ExtOp, TruncOp;
3487 if (OVT.isVector()) {
3488 ExtOp = ISD::BITCAST;
3489 TruncOp = ISD::BITCAST;
3491 assert(OVT.isInteger() && "Cannot promote logic operation");
3492 ExtOp = ISD::ANY_EXTEND;
3493 TruncOp = ISD::TRUNCATE;
3495 // Promote each of the values to the new type.
3496 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3497 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3498 // Perform the larger operation, then convert back
3499 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3500 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3504 unsigned ExtOp, TruncOp;
3505 if (Node->getValueType(0).isVector()) {
3506 ExtOp = ISD::BITCAST;
3507 TruncOp = ISD::BITCAST;
3508 } else if (Node->getValueType(0).isInteger()) {
3509 ExtOp = ISD::ANY_EXTEND;
3510 TruncOp = ISD::TRUNCATE;
3512 ExtOp = ISD::FP_EXTEND;
3513 TruncOp = ISD::FP_ROUND;
3515 Tmp1 = Node->getOperand(0);
3516 // Promote each of the values to the new type.
3517 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3518 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3519 // Perform the larger operation, then round down.
3520 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3521 if (TruncOp != ISD::FP_ROUND)
3522 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3524 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3525 DAG.getIntPtrConstant(0));
3526 Results.push_back(Tmp1);
3529 case ISD::VECTOR_SHUFFLE: {
3530 SmallVector<int, 8> Mask;
3531 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3533 // Cast the two input vectors.
3534 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3535 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3537 // Convert the shuffle mask to the right # elements.
3538 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3539 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3540 Results.push_back(Tmp1);
3544 unsigned ExtOp = ISD::FP_EXTEND;
3545 if (NVT.isInteger()) {
3546 ISD::CondCode CCCode =
3547 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3548 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3550 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3551 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3552 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3553 Tmp1, Tmp2, Node->getOperand(2)));
3559 // SelectionDAG::Legalize - This is the entry point for the file.
3561 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3562 /// run - This is the main entry point to this class.
3564 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();