1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineJumpTableInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetFrameLowering.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/Function.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class SelectionDAGLegalize {
57 const TargetMachine &TM;
58 const TargetLowering &TLI;
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SmallVector<SDValue, 8> LastCALLSEQ;
70 Legal, // The target natively supports this operation.
71 Promote, // This operation should be executed in a larger type.
72 Expand // Try to expand this to other ops, otherwise use a libcall.
75 /// ValueTypeActions - This is a bitvector that contains two bits for each
76 /// value type, where the two bits correspond to the LegalizeAction enum.
77 /// This can be queried with "getTypeAction(VT)".
78 TargetLowering::ValueTypeActionImpl ValueTypeActions;
80 /// LegalizedNodes - For nodes that are of legal width, and that have more
81 /// than one use, this map indicates what regularized operand to use. This
82 /// allows us to avoid legalizing the same thing more than once.
83 DenseMap<SDValue, SDValue> LegalizedNodes;
85 void AddLegalizedOperand(SDValue From, SDValue To) {
86 LegalizedNodes.insert(std::make_pair(From, To));
87 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
91 // Transfer SDDbgValues.
92 DAG.TransferDbgValues(From, To);
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(EVT VT) const {
102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
105 /// isTypeLegal - Return true if this type is legal on this target.
107 bool isTypeLegal(EVT VT) const {
108 return getTypeAction(VT) == Legal;
114 /// LegalizeOp - We know that the specified value has a legal type.
115 /// Recursively ensure that the operands have legal types, then return the
117 SDValue LegalizeOp(SDValue O);
119 SDValue OptimizeFloatStore(StoreSDNode *ST);
121 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
122 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
123 /// is necessary to spill the vector being inserted into to memory, perform
124 /// the insert there, and then read the result back.
125 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
126 SDValue Idx, DebugLoc dl);
127 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
130 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
131 /// performs the same shuffe in terms of order or result bytes, but on a type
132 /// whose vector element type is narrower than the original shuffle type.
133 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
134 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
135 SDValue N1, SDValue N2,
136 SmallVectorImpl<int> &Mask) const;
138 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
139 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
141 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
144 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
145 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
146 unsigned NumOps, bool isSigned, DebugLoc dl);
148 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
149 SDNode *Node, bool isSigned);
150 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
151 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
152 RTLIB::Libcall Call_PPCF128);
153 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
154 RTLIB::Libcall Call_I8,
155 RTLIB::Libcall Call_I16,
156 RTLIB::Libcall Call_I32,
157 RTLIB::Libcall Call_I64,
158 RTLIB::Libcall Call_I128);
159 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
161 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
162 SDValue ExpandBUILD_VECTOR(SDNode *Node);
163 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
164 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
165 SmallVectorImpl<SDValue> &Results);
166 SDValue ExpandFCOPYSIGN(SDNode *Node);
167 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
169 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
171 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
174 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
175 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
177 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
178 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
179 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
181 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
183 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
184 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
186 SDValue getLastCALLSEQ() { return LastCALLSEQ.back(); }
187 void setLastCALLSEQ(const SDValue s) { LastCALLSEQ.back() = s; }
188 void pushLastCALLSEQ(SDValue s) {
189 LastCALLSEQ.push_back(s);
191 void popLastCALLSEQ() {
192 LastCALLSEQ.pop_back();
197 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
198 /// performs the same shuffe in terms of order or result bytes, but on a type
199 /// whose vector element type is narrower than the original shuffle type.
200 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
202 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
203 SDValue N1, SDValue N2,
204 SmallVectorImpl<int> &Mask) const {
205 unsigned NumMaskElts = VT.getVectorNumElements();
206 unsigned NumDestElts = NVT.getVectorNumElements();
207 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
209 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
211 if (NumEltsGrowth == 1)
212 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
214 SmallVector<int, 8> NewMask;
215 for (unsigned i = 0; i != NumMaskElts; ++i) {
217 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
219 NewMask.push_back(-1);
221 NewMask.push_back(Idx * NumEltsGrowth + j);
224 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
225 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
226 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
229 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
230 CodeGenOpt::Level ol)
231 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
232 DAG(dag), OptLevel(ol),
233 ValueTypeActions(TLI.getValueTypeActions()) {
234 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
235 "Too many value types for ValueTypeActions to hold!");
238 void SelectionDAGLegalize::LegalizeDAG() {
239 pushLastCALLSEQ(DAG.getEntryNode());
241 // The legalize process is inherently a bottom-up recursive process (users
242 // legalize their uses before themselves). Given infinite stack space, we
243 // could just start legalizing on the root and traverse the whole graph. In
244 // practice however, this causes us to run out of stack space on large basic
245 // blocks. To avoid this problem, compute an ordering of the nodes where each
246 // node is only legalized after all of its operands are legalized.
247 DAG.AssignTopologicalOrder();
248 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
249 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
250 LegalizeOp(SDValue(I, 0));
252 // Finally, it's possible the root changed. Get the new root.
253 SDValue OldRoot = DAG.getRoot();
254 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
255 DAG.setRoot(LegalizedNodes[OldRoot]);
257 LegalizedNodes.clear();
259 // Remove dead nodes now.
260 DAG.RemoveDeadNodes();
264 /// FindCallEndFromCallStart - Given a chained node that is part of a call
265 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
266 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
267 int next_depth = depth;
268 if (Node->getOpcode() == ISD::CALLSEQ_START)
269 next_depth = depth + 1;
270 if (Node->getOpcode() == ISD::CALLSEQ_END) {
271 assert(depth > 0 && "negative depth!");
275 next_depth = depth - 1;
277 if (Node->use_empty())
278 return 0; // No CallSeqEnd
280 // The chain is usually at the end.
281 SDValue TheChain(Node, Node->getNumValues()-1);
282 if (TheChain.getValueType() != MVT::Other) {
283 // Sometimes it's at the beginning.
284 TheChain = SDValue(Node, 0);
285 if (TheChain.getValueType() != MVT::Other) {
286 // Otherwise, hunt for it.
287 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
288 if (Node->getValueType(i) == MVT::Other) {
289 TheChain = SDValue(Node, i);
293 // Otherwise, we walked into a node without a chain.
294 if (TheChain.getValueType() != MVT::Other)
299 for (SDNode::use_iterator UI = Node->use_begin(),
300 E = Node->use_end(); UI != E; ++UI) {
302 // Make sure to only follow users of our token chain.
304 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
305 if (User->getOperand(i) == TheChain)
306 if (SDNode *Result = FindCallEndFromCallStart(User, next_depth))
312 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
313 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
314 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
316 assert(Node && "Didn't find callseq_start for a call??");
317 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
318 Node = Node->getOperand(0).getNode();
319 assert(Node->getOperand(0).getValueType() == MVT::Other &&
320 "Node doesn't have a token chain argument!");
321 switch (Node->getOpcode()) {
324 case ISD::CALLSEQ_START:
329 case ISD::CALLSEQ_END:
337 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
338 /// see if any uses can reach Dest. If no dest operands can get to dest,
339 /// legalize them, legalize ourself, and return false, otherwise, return true.
341 /// Keep track of the nodes we fine that actually do lead to Dest in
342 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
344 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
345 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
346 if (N == Dest) return true; // N certainly leads to Dest :)
348 // If we've already processed this node and it does lead to Dest, there is no
349 // need to reprocess it.
350 if (NodesLeadingTo.count(N)) return true;
352 // If the first result of this node has been already legalized, then it cannot
354 if (LegalizedNodes.count(SDValue(N, 0))) return false;
356 // Okay, this node has not already been legalized. Check and legalize all
357 // operands. If none lead to Dest, then we can legalize this node.
358 bool OperandsLeadToDest = false;
359 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
360 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
361 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
364 if (OperandsLeadToDest) {
365 NodesLeadingTo.insert(N);
369 // Okay, this node looks safe, legalize it and return false.
370 LegalizeOp(SDValue(N, 0));
374 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
375 /// a load from the constant pool.
376 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
377 SelectionDAG &DAG, const TargetLowering &TLI) {
379 DebugLoc dl = CFP->getDebugLoc();
381 // If a FP immediate is precise when represented as a float and if the
382 // target can do an extending load from float to double, we put it into
383 // the constant pool as a float, even if it's is statically typed as a
384 // double. This shrinks FP constants and canonicalizes them for targets where
385 // an FP extending load is the same cost as a normal load (such as on the x87
386 // fp stack or PPC FP unit).
387 EVT VT = CFP->getValueType(0);
388 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
390 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
391 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
392 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
397 while (SVT != MVT::f32) {
398 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
399 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
400 // Only do this if the target has a native EXTLOAD instruction from
402 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
403 TLI.ShouldShrinkFPConstant(OrigVT)) {
404 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
405 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
411 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
412 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
414 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
416 CPIdx, MachinePointerInfo::getConstantPool(),
417 VT, false, false, Alignment);
418 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
419 MachinePointerInfo::getConstantPool(), false, false,
423 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
425 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
426 const TargetLowering &TLI) {
427 SDValue Chain = ST->getChain();
428 SDValue Ptr = ST->getBasePtr();
429 SDValue Val = ST->getValue();
430 EVT VT = Val.getValueType();
431 int Alignment = ST->getAlignment();
432 DebugLoc dl = ST->getDebugLoc();
433 if (ST->getMemoryVT().isFloatingPoint() ||
434 ST->getMemoryVT().isVector()) {
435 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
436 if (TLI.isTypeLegal(intVT)) {
437 // Expand to a bitconvert of the value to the integer type of the
438 // same size, then a (misaligned) int store.
439 // FIXME: Does not handle truncating floating point stores!
440 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
441 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
442 ST->isVolatile(), ST->isNonTemporal(), Alignment);
444 // Do a (aligned) store to a stack slot, then copy from the stack slot
445 // to the final destination using (unaligned) integer loads and stores.
446 EVT StoredVT = ST->getMemoryVT();
448 TLI.getRegisterType(*DAG.getContext(),
449 EVT::getIntegerVT(*DAG.getContext(),
450 StoredVT.getSizeInBits()));
451 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
452 unsigned RegBytes = RegVT.getSizeInBits() / 8;
453 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
455 // Make sure the stack slot is also aligned for the register type.
456 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
458 // Perform the original store, only redirected to the stack slot.
459 SDValue Store = DAG.getTruncStore(Chain, dl,
460 Val, StackPtr, MachinePointerInfo(),
461 StoredVT, false, false, 0);
462 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
463 SmallVector<SDValue, 8> Stores;
466 // Do all but one copies using the full register width.
467 for (unsigned i = 1; i < NumRegs; i++) {
468 // Load one integer register's worth from the stack slot.
469 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
470 MachinePointerInfo(),
472 // Store it to the final location. Remember the store.
473 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
474 ST->getPointerInfo().getWithOffset(Offset),
475 ST->isVolatile(), ST->isNonTemporal(),
476 MinAlign(ST->getAlignment(), Offset)));
477 // Increment the pointers.
479 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
481 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
484 // The last store may be partial. Do a truncating store. On big-endian
485 // machines this requires an extending load from the stack slot to ensure
486 // that the bits are in the right place.
487 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
488 8 * (StoredBytes - Offset));
490 // Load from the stack slot.
491 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
492 MachinePointerInfo(),
493 MemVT, false, false, 0);
495 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
497 .getWithOffset(Offset),
498 MemVT, ST->isVolatile(),
500 MinAlign(ST->getAlignment(), Offset)));
501 // The order of the stores doesn't matter - say it with a TokenFactor.
502 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
506 assert(ST->getMemoryVT().isInteger() &&
507 !ST->getMemoryVT().isVector() &&
508 "Unaligned store of unknown type.");
509 // Get the half-size VT
510 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
511 int NumBits = NewStoredVT.getSizeInBits();
512 int IncrementSize = NumBits / 8;
514 // Divide the stored value in two parts.
515 SDValue ShiftAmount = DAG.getConstant(NumBits,
516 TLI.getShiftAmountTy(Val.getValueType()));
518 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
520 // Store the two parts
521 SDValue Store1, Store2;
522 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
523 ST->getPointerInfo(), NewStoredVT,
524 ST->isVolatile(), ST->isNonTemporal(), Alignment);
525 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
526 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
527 Alignment = MinAlign(Alignment, IncrementSize);
528 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
529 ST->getPointerInfo().getWithOffset(IncrementSize),
530 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
533 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
536 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
538 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
539 const TargetLowering &TLI) {
540 SDValue Chain = LD->getChain();
541 SDValue Ptr = LD->getBasePtr();
542 EVT VT = LD->getValueType(0);
543 EVT LoadedVT = LD->getMemoryVT();
544 DebugLoc dl = LD->getDebugLoc();
545 if (VT.isFloatingPoint() || VT.isVector()) {
546 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
547 if (TLI.isTypeLegal(intVT)) {
548 // Expand to a (misaligned) integer load of the same size,
549 // then bitconvert to floating point or vector.
550 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
552 LD->isNonTemporal(), LD->getAlignment());
553 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
554 if (VT.isFloatingPoint() && LoadedVT != VT)
555 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
557 SDValue Ops[] = { Result, Chain };
558 return DAG.getMergeValues(Ops, 2, dl);
561 // Copy the value to a (aligned) stack slot using (unaligned) integer
562 // loads and stores, then do a (aligned) load from the stack slot.
563 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
564 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
565 unsigned RegBytes = RegVT.getSizeInBits() / 8;
566 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
568 // Make sure the stack slot is also aligned for the register type.
569 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
571 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
572 SmallVector<SDValue, 8> Stores;
573 SDValue StackPtr = StackBase;
576 // Do all but one copies using the full register width.
577 for (unsigned i = 1; i < NumRegs; i++) {
578 // Load one integer register's worth from the original location.
579 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
580 LD->getPointerInfo().getWithOffset(Offset),
581 LD->isVolatile(), LD->isNonTemporal(),
582 MinAlign(LD->getAlignment(), Offset));
583 // Follow the load with a store to the stack slot. Remember the store.
584 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
585 MachinePointerInfo(), false, false, 0));
586 // Increment the pointers.
588 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
589 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
593 // The last copy may be partial. Do an extending load.
594 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
595 8 * (LoadedBytes - Offset));
596 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
597 LD->getPointerInfo().getWithOffset(Offset),
598 MemVT, LD->isVolatile(),
600 MinAlign(LD->getAlignment(), Offset));
601 // Follow the load with a store to the stack slot. Remember the store.
602 // On big-endian machines this requires a truncating store to ensure
603 // that the bits end up in the right place.
604 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
605 MachinePointerInfo(), MemVT,
608 // The order of the stores doesn't matter - say it with a TokenFactor.
609 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
612 // Finally, perform the original load only redirected to the stack slot.
613 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
614 MachinePointerInfo(), LoadedVT, false, false, 0);
616 // Callers expect a MERGE_VALUES node.
617 SDValue Ops[] = { Load, TF };
618 return DAG.getMergeValues(Ops, 2, dl);
620 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
621 "Unaligned load of unsupported type.");
623 // Compute the new VT that is half the size of the old one. This is an
625 unsigned NumBits = LoadedVT.getSizeInBits();
627 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
630 unsigned Alignment = LD->getAlignment();
631 unsigned IncrementSize = NumBits / 8;
632 ISD::LoadExtType HiExtType = LD->getExtensionType();
634 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
635 if (HiExtType == ISD::NON_EXTLOAD)
636 HiExtType = ISD::ZEXTLOAD;
638 // Load the value in two parts
640 if (TLI.isLittleEndian()) {
641 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
642 NewLoadedVT, LD->isVolatile(),
643 LD->isNonTemporal(), Alignment);
644 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
645 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
646 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
647 LD->getPointerInfo().getWithOffset(IncrementSize),
648 NewLoadedVT, LD->isVolatile(),
649 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
651 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
652 NewLoadedVT, LD->isVolatile(),
653 LD->isNonTemporal(), Alignment);
654 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
655 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
656 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
657 LD->getPointerInfo().getWithOffset(IncrementSize),
658 NewLoadedVT, LD->isVolatile(),
659 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
662 // aggregate the two parts
663 SDValue ShiftAmount = DAG.getConstant(NumBits,
664 TLI.getShiftAmountTy(Hi.getValueType()));
665 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
666 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
668 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
671 SDValue Ops[] = { Result, TF };
672 return DAG.getMergeValues(Ops, 2, dl);
675 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
676 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
677 /// is necessary to spill the vector being inserted into to memory, perform
678 /// the insert there, and then read the result back.
679 SDValue SelectionDAGLegalize::
680 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
686 // If the target doesn't support this, we have to spill the input vector
687 // to a temporary stack slot, update the element, then reload it. This is
688 // badness. We could also load the value into a vector register (either
689 // with a "move to register" or "extload into register" instruction, then
690 // permute it into place, if the idx is a constant and if the idx is
691 // supported by the target.
692 EVT VT = Tmp1.getValueType();
693 EVT EltVT = VT.getVectorElementType();
694 EVT IdxVT = Tmp3.getValueType();
695 EVT PtrVT = TLI.getPointerTy();
696 SDValue StackPtr = DAG.CreateStackTemporary(VT);
698 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
701 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
702 MachinePointerInfo::getFixedStack(SPFI),
705 // Truncate or zero extend offset to target pointer type.
706 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
707 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
708 // Add the offset to the index.
709 unsigned EltSize = EltVT.getSizeInBits()/8;
710 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
711 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
712 // Store the scalar value.
713 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
715 // Load the updated vector.
716 return DAG.getLoad(VT, dl, Ch, StackPtr,
717 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
721 SDValue SelectionDAGLegalize::
722 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
723 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
724 // SCALAR_TO_VECTOR requires that the type of the value being inserted
725 // match the element type of the vector being created, except for
726 // integers in which case the inserted value can be over width.
727 EVT EltVT = Vec.getValueType().getVectorElementType();
728 if (Val.getValueType() == EltVT ||
729 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
730 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
731 Vec.getValueType(), Val);
733 unsigned NumElts = Vec.getValueType().getVectorNumElements();
734 // We generate a shuffle of InVec and ScVec, so the shuffle mask
735 // should be 0,1,2,3,4,5... with the appropriate element replaced with
737 SmallVector<int, 8> ShufOps;
738 for (unsigned i = 0; i != NumElts; ++i)
739 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
741 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
745 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
748 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
749 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
750 // FIXME: We shouldn't do this for TargetConstantFP's.
751 // FIXME: move this to the DAG Combiner! Note that we can't regress due
752 // to phase ordering between legalized code and the dag combiner. This
753 // probably means that we need to integrate dag combiner and legalizer
755 // We generally can't do this one for long doubles.
756 SDValue Tmp1 = ST->getChain();
757 SDValue Tmp2 = ST->getBasePtr();
759 unsigned Alignment = ST->getAlignment();
760 bool isVolatile = ST->isVolatile();
761 bool isNonTemporal = ST->isNonTemporal();
762 DebugLoc dl = ST->getDebugLoc();
763 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
764 if (CFP->getValueType(0) == MVT::f32 &&
765 getTypeAction(MVT::i32) == Legal) {
766 Tmp3 = DAG.getConstant(CFP->getValueAPF().
767 bitcastToAPInt().zextOrTrunc(32),
769 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
770 isVolatile, isNonTemporal, Alignment);
773 if (CFP->getValueType(0) == MVT::f64) {
774 // If this target supports 64-bit registers, do a single 64-bit store.
775 if (getTypeAction(MVT::i64) == Legal) {
776 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
777 zextOrTrunc(64), MVT::i64);
778 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
779 isVolatile, isNonTemporal, Alignment);
782 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
783 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
784 // stores. If the target supports neither 32- nor 64-bits, this
785 // xform is certainly not worth it.
786 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
787 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
788 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
789 if (TLI.isBigEndian()) std::swap(Lo, Hi);
791 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
792 isNonTemporal, Alignment);
793 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
794 DAG.getIntPtrConstant(4));
795 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
796 ST->getPointerInfo().getWithOffset(4),
797 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
799 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
803 return SDValue(0, 0);
806 /// LegalizeOp - We know that the specified value has a legal type, and
807 /// that its operands are legal. Now ensure that the operation itself
808 /// is legal, recursively ensuring that the operands' operations remain
810 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
811 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
814 SDNode *Node = Op.getNode();
815 DebugLoc dl = Node->getDebugLoc();
817 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
818 assert(getTypeAction(Node->getValueType(i)) == Legal &&
819 "Unexpected illegal type!");
821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
822 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
823 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
824 "Unexpected illegal type!");
826 // Note that LegalizeOp may be reentered even from single-use nodes, which
827 // means that we always must cache transformed nodes.
828 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
829 if (I != LegalizedNodes.end()) return I->second;
831 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
833 bool isCustom = false;
835 // Figure out the correct action; the way to query this varies by opcode
836 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
837 bool SimpleFinishLegalizing = true;
838 switch (Node->getOpcode()) {
839 case ISD::INTRINSIC_W_CHAIN:
840 case ISD::INTRINSIC_WO_CHAIN:
841 case ISD::INTRINSIC_VOID:
844 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
846 case ISD::SINT_TO_FP:
847 case ISD::UINT_TO_FP:
848 case ISD::EXTRACT_VECTOR_ELT:
849 Action = TLI.getOperationAction(Node->getOpcode(),
850 Node->getOperand(0).getValueType());
852 case ISD::FP_ROUND_INREG:
853 case ISD::SIGN_EXTEND_INREG: {
854 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
855 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
861 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
862 Node->getOpcode() == ISD::SETCC ? 2 : 1;
863 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
864 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
865 ISD::CondCode CCCode =
866 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
867 Action = TLI.getCondCodeAction(CCCode, OpVT);
868 if (Action == TargetLowering::Legal) {
869 if (Node->getOpcode() == ISD::SELECT_CC)
870 Action = TLI.getOperationAction(Node->getOpcode(),
871 Node->getValueType(0));
873 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
879 // FIXME: Model these properly. LOAD and STORE are complicated, and
880 // STORE expects the unlegalized operand in some cases.
881 SimpleFinishLegalizing = false;
883 case ISD::CALLSEQ_START:
884 case ISD::CALLSEQ_END:
885 // FIXME: This shouldn't be necessary. These nodes have special properties
886 // dealing with the recursive nature of legalization. Removing this
887 // special case should be done as part of making LegalizeDAG non-recursive.
888 SimpleFinishLegalizing = false;
890 case ISD::EXTRACT_ELEMENT:
891 case ISD::FLT_ROUNDS_:
899 case ISD::MERGE_VALUES:
901 case ISD::FRAME_TO_ARGS_OFFSET:
902 case ISD::EH_SJLJ_SETJMP:
903 case ISD::EH_SJLJ_LONGJMP:
904 case ISD::EH_SJLJ_DISPATCHSETUP:
905 // These operations lie about being legal: when they claim to be legal,
906 // they should actually be expanded.
907 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
908 if (Action == TargetLowering::Legal)
909 Action = TargetLowering::Expand;
911 case ISD::TRAMPOLINE:
913 case ISD::RETURNADDR:
914 // These operations lie about being legal: when they claim to be legal,
915 // they should actually be custom-lowered.
916 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
917 if (Action == TargetLowering::Legal)
918 Action = TargetLowering::Custom;
920 case ISD::BUILD_VECTOR:
921 // A weird case: legalization for BUILD_VECTOR never legalizes the
923 // FIXME: This really sucks... changing it isn't semantically incorrect,
924 // but it massively pessimizes the code for floating-point BUILD_VECTORs
925 // because ConstantFP operands get legalized into constant pool loads
926 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
927 // though, because BUILD_VECTORS usually get lowered into other nodes
928 // which get legalized properly.
929 SimpleFinishLegalizing = false;
932 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
933 Action = TargetLowering::Legal;
935 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
940 if (SimpleFinishLegalizing) {
941 SmallVector<SDValue, 8> Ops, ResultVals;
942 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
943 Ops.push_back(LegalizeOp(Node->getOperand(i)));
944 switch (Node->getOpcode()) {
951 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
952 // Branches tweak the chain to include LastCALLSEQ
953 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
955 Ops[0] = LegalizeOp(Ops[0]);
956 setLastCALLSEQ(DAG.getEntryNode());
963 // Legalizing shifts/rotates requires adjusting the shift amount
964 // to the appropriate width.
965 if (!Ops[1].getValueType().isVector())
966 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
972 // Legalizing shifts/rotates requires adjusting the shift amount
973 // to the appropriate width.
974 if (!Ops[2].getValueType().isVector())
975 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
980 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
983 case TargetLowering::Legal:
984 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
985 ResultVals.push_back(Result.getValue(i));
987 case TargetLowering::Custom:
988 // FIXME: The handling for custom lowering with multiple results is
990 Tmp1 = TLI.LowerOperation(Result, DAG);
991 if (Tmp1.getNode()) {
992 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
994 ResultVals.push_back(Tmp1);
996 ResultVals.push_back(Tmp1.getValue(i));
1002 case TargetLowering::Expand:
1003 ExpandNode(Result.getNode(), ResultVals);
1005 case TargetLowering::Promote:
1006 PromoteNode(Result.getNode(), ResultVals);
1009 if (!ResultVals.empty()) {
1010 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
1011 if (ResultVals[i] != SDValue(Node, i))
1012 ResultVals[i] = LegalizeOp(ResultVals[i]);
1013 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
1015 return ResultVals[Op.getResNo()];
1019 switch (Node->getOpcode()) {
1026 assert(0 && "Do not know how to legalize this operator!");
1028 case ISD::BUILD_VECTOR:
1029 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1030 default: assert(0 && "This action is not supported yet!");
1031 case TargetLowering::Custom:
1032 Tmp3 = TLI.LowerOperation(Result, DAG);
1033 if (Tmp3.getNode()) {
1038 case TargetLowering::Expand:
1039 Result = ExpandBUILD_VECTOR(Result.getNode());
1043 case ISD::CALLSEQ_START: {
1044 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1045 assert(CallEnd && "didn't find CALLSEQ_END!");
1047 // Recursively Legalize all of the inputs of the call end that do not lead
1048 // to this call start. This ensures that any libcalls that need be inserted
1049 // are inserted *before* the CALLSEQ_START.
1050 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1051 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1052 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1056 // Now that we have legalized all of the inputs (which may have inserted
1057 // libcalls), create the new CALLSEQ_START node.
1058 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1060 // Merge in the last call to ensure that this call starts after the last
1062 if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) {
1063 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1064 Tmp1, getLastCALLSEQ());
1065 Tmp1 = LegalizeOp(Tmp1);
1068 // Do not try to legalize the target-specific arguments (#1+).
1069 if (Tmp1 != Node->getOperand(0)) {
1070 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1072 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1073 Ops.size()), Result.getResNo());
1076 // Remember that the CALLSEQ_START is legalized.
1077 AddLegalizedOperand(Op.getValue(0), Result);
1078 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1079 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1081 // Now that the callseq_start and all of the non-call nodes above this call
1082 // sequence have been legalized, legalize the call itself. During this
1083 // process, no libcalls can/will be inserted, guaranteeing that no calls
1085 // Note that we are selecting this call!
1086 setLastCALLSEQ(SDValue(CallEnd, 0));
1088 // Legalize the call, starting from the CALLSEQ_END.
1089 LegalizeOp(getLastCALLSEQ());
1092 case ISD::CALLSEQ_END:
1094 SDNode *myCALLSEQ_BEGIN = FindCallStartFromCallEnd(Node);
1096 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1097 // will cause this node to be legalized as well as handling libcalls right.
1098 if (getLastCALLSEQ().getNode() != Node) {
1099 LegalizeOp(SDValue(myCALLSEQ_BEGIN, 0));
1100 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1101 assert(I != LegalizedNodes.end() &&
1102 "Legalizing the call start should have legalized this node!");
1106 pushLastCALLSEQ(SDValue(myCALLSEQ_BEGIN, 0));
1109 // Otherwise, the call start has been legalized and everything is going
1110 // according to plan. Just legalize ourselves normally here.
1111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1112 // Do not try to legalize the target-specific arguments (#1+), except for
1113 // an optional flag input.
1114 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1115 if (Tmp1 != Node->getOperand(0)) {
1116 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1118 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1119 &Ops[0], Ops.size()),
1123 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1124 if (Tmp1 != Node->getOperand(0) ||
1125 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1126 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1129 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1130 &Ops[0], Ops.size()),
1134 // This finishes up call legalization.
1137 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1138 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1139 if (Node->getNumValues() == 2)
1140 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1141 return Result.getValue(Op.getResNo());
1143 LoadSDNode *LD = cast<LoadSDNode>(Node);
1144 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1145 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1147 ISD::LoadExtType ExtType = LD->getExtensionType();
1148 if (ExtType == ISD::NON_EXTLOAD) {
1149 EVT VT = Node->getValueType(0);
1150 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1151 Tmp1, Tmp2, LD->getOffset()),
1153 Tmp3 = Result.getValue(0);
1154 Tmp4 = Result.getValue(1);
1156 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1157 default: assert(0 && "This action is not supported yet!");
1158 case TargetLowering::Legal:
1159 // If this is an unaligned load and the target doesn't support it,
1161 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1162 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1163 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1164 if (LD->getAlignment() < ABIAlignment){
1165 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1167 Tmp3 = Result.getOperand(0);
1168 Tmp4 = Result.getOperand(1);
1169 Tmp3 = LegalizeOp(Tmp3);
1170 Tmp4 = LegalizeOp(Tmp4);
1174 case TargetLowering::Custom:
1175 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1176 if (Tmp1.getNode()) {
1177 Tmp3 = LegalizeOp(Tmp1);
1178 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1181 case TargetLowering::Promote: {
1182 // Only promote a load of vector type to another.
1183 assert(VT.isVector() && "Cannot promote this load!");
1184 // Change base type to a different vector type.
1185 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1187 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1188 LD->isVolatile(), LD->isNonTemporal(),
1189 LD->getAlignment());
1190 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1191 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1195 // Since loads produce two values, make sure to remember that we
1196 // legalized both of them.
1197 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1198 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1199 return Op.getResNo() ? Tmp4 : Tmp3;
1202 EVT SrcVT = LD->getMemoryVT();
1203 unsigned SrcWidth = SrcVT.getSizeInBits();
1204 unsigned Alignment = LD->getAlignment();
1205 bool isVolatile = LD->isVolatile();
1206 bool isNonTemporal = LD->isNonTemporal();
1208 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1209 // Some targets pretend to have an i1 loading operation, and actually
1210 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1211 // bits are guaranteed to be zero; it helps the optimizers understand
1212 // that these bits are zero. It is also useful for EXTLOAD, since it
1213 // tells the optimizers that those bits are undefined. It would be
1214 // nice to have an effective generic way of getting these benefits...
1215 // Until such a way is found, don't insist on promoting i1 here.
1216 (SrcVT != MVT::i1 ||
1217 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1218 // Promote to a byte-sized load if not loading an integral number of
1219 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1220 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1221 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1224 // The extra bits are guaranteed to be zero, since we stored them that
1225 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1227 ISD::LoadExtType NewExtType =
1228 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1230 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1231 Tmp1, Tmp2, LD->getPointerInfo(),
1232 NVT, isVolatile, isNonTemporal, Alignment);
1234 Ch = Result.getValue(1); // The chain.
1236 if (ExtType == ISD::SEXTLOAD)
1237 // Having the top bits zero doesn't help when sign extending.
1238 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1239 Result.getValueType(),
1240 Result, DAG.getValueType(SrcVT));
1241 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1242 // All the top bits are guaranteed to be zero - inform the optimizers.
1243 Result = DAG.getNode(ISD::AssertZext, dl,
1244 Result.getValueType(), Result,
1245 DAG.getValueType(SrcVT));
1247 Tmp1 = LegalizeOp(Result);
1248 Tmp2 = LegalizeOp(Ch);
1249 } else if (SrcWidth & (SrcWidth - 1)) {
1250 // If not loading a power-of-2 number of bits, expand as two loads.
1251 assert(!SrcVT.isVector() && "Unsupported extload!");
1252 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1253 assert(RoundWidth < SrcWidth);
1254 unsigned ExtraWidth = SrcWidth - RoundWidth;
1255 assert(ExtraWidth < RoundWidth);
1256 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1257 "Load size not an integral number of bytes!");
1258 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1259 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1261 unsigned IncrementSize;
1263 if (TLI.isLittleEndian()) {
1264 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1265 // Load the bottom RoundWidth bits.
1266 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1268 LD->getPointerInfo(), RoundVT, isVolatile,
1269 isNonTemporal, Alignment);
1271 // Load the remaining ExtraWidth bits.
1272 IncrementSize = RoundWidth / 8;
1273 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1274 DAG.getIntPtrConstant(IncrementSize));
1275 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1276 LD->getPointerInfo().getWithOffset(IncrementSize),
1277 ExtraVT, isVolatile, isNonTemporal,
1278 MinAlign(Alignment, IncrementSize));
1280 // Build a factor node to remember that this load is independent of
1282 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1285 // Move the top bits to the right place.
1286 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1287 DAG.getConstant(RoundWidth,
1288 TLI.getShiftAmountTy(Hi.getValueType())));
1290 // Join the hi and lo parts.
1291 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1293 // Big endian - avoid unaligned loads.
1294 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1295 // Load the top RoundWidth bits.
1296 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1297 LD->getPointerInfo(), RoundVT, isVolatile,
1298 isNonTemporal, Alignment);
1300 // Load the remaining ExtraWidth bits.
1301 IncrementSize = RoundWidth / 8;
1302 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1303 DAG.getIntPtrConstant(IncrementSize));
1304 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1305 dl, Node->getValueType(0), Tmp1, Tmp2,
1306 LD->getPointerInfo().getWithOffset(IncrementSize),
1307 ExtraVT, isVolatile, isNonTemporal,
1308 MinAlign(Alignment, IncrementSize));
1310 // Build a factor node to remember that this load is independent of
1312 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1315 // Move the top bits to the right place.
1316 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1317 DAG.getConstant(ExtraWidth,
1318 TLI.getShiftAmountTy(Hi.getValueType())));
1320 // Join the hi and lo parts.
1321 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1324 Tmp1 = LegalizeOp(Result);
1325 Tmp2 = LegalizeOp(Ch);
1327 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1328 default: assert(0 && "This action is not supported yet!");
1329 case TargetLowering::Custom:
1332 case TargetLowering::Legal:
1333 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1334 Tmp1, Tmp2, LD->getOffset()),
1336 Tmp1 = Result.getValue(0);
1337 Tmp2 = Result.getValue(1);
1340 Tmp3 = TLI.LowerOperation(Result, DAG);
1341 if (Tmp3.getNode()) {
1342 Tmp1 = LegalizeOp(Tmp3);
1343 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1346 // If this is an unaligned load and the target doesn't support it,
1348 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1350 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1351 unsigned ABIAlignment =
1352 TLI.getTargetData()->getABITypeAlignment(Ty);
1353 if (LD->getAlignment() < ABIAlignment){
1354 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1356 Tmp1 = Result.getOperand(0);
1357 Tmp2 = Result.getOperand(1);
1358 Tmp1 = LegalizeOp(Tmp1);
1359 Tmp2 = LegalizeOp(Tmp2);
1364 case TargetLowering::Expand:
1365 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1366 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1367 LD->getPointerInfo(),
1368 LD->isVolatile(), LD->isNonTemporal(),
1369 LD->getAlignment());
1373 ExtendOp = (SrcVT.isFloatingPoint() ?
1374 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1376 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1377 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1378 default: llvm_unreachable("Unexpected extend load type!");
1380 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1381 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1382 Tmp2 = LegalizeOp(Load.getValue(1));
1385 // FIXME: This does not work for vectors on most targets. Sign- and
1386 // zero-extend operations are currently folded into extending loads,
1387 // whether they are legal or not, and then we end up here without any
1388 // support for legalizing them.
1389 assert(ExtType != ISD::EXTLOAD &&
1390 "EXTLOAD should always be supported!");
1391 // Turn the unsupported load into an EXTLOAD followed by an explicit
1392 // zero/sign extend inreg.
1393 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1394 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1395 LD->isVolatile(), LD->isNonTemporal(),
1396 LD->getAlignment());
1398 if (ExtType == ISD::SEXTLOAD)
1399 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1400 Result.getValueType(),
1401 Result, DAG.getValueType(SrcVT));
1403 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1404 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1405 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1410 // Since loads produce two values, make sure to remember that we legalized
1412 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1413 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1414 return Op.getResNo() ? Tmp2 : Tmp1;
1417 StoreSDNode *ST = cast<StoreSDNode>(Node);
1418 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1419 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1420 unsigned Alignment = ST->getAlignment();
1421 bool isVolatile = ST->isVolatile();
1422 bool isNonTemporal = ST->isNonTemporal();
1424 if (!ST->isTruncatingStore()) {
1425 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1426 Result = SDValue(OptStore, 0);
1431 Tmp3 = LegalizeOp(ST->getValue());
1432 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1437 EVT VT = Tmp3.getValueType();
1438 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1439 default: assert(0 && "This action is not supported yet!");
1440 case TargetLowering::Legal:
1441 // If this is an unaligned store and the target doesn't support it,
1443 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1444 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1445 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1446 if (ST->getAlignment() < ABIAlignment)
1447 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1451 case TargetLowering::Custom:
1452 Tmp1 = TLI.LowerOperation(Result, DAG);
1453 if (Tmp1.getNode()) Result = Tmp1;
1455 case TargetLowering::Promote:
1456 assert(VT.isVector() && "Unknown legal promote case!");
1457 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1458 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1459 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1460 ST->getPointerInfo(), isVolatile,
1461 isNonTemporal, Alignment);
1467 Tmp3 = LegalizeOp(ST->getValue());
1469 EVT StVT = ST->getMemoryVT();
1470 unsigned StWidth = StVT.getSizeInBits();
1472 if (StWidth != StVT.getStoreSizeInBits()) {
1473 // Promote to a byte-sized store with upper bits zero if not
1474 // storing an integral number of bytes. For example, promote
1475 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1476 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1477 StVT.getStoreSizeInBits());
1478 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1479 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1480 NVT, isVolatile, isNonTemporal, Alignment);
1481 } else if (StWidth & (StWidth - 1)) {
1482 // If not storing a power-of-2 number of bits, expand as two stores.
1483 assert(!StVT.isVector() && "Unsupported truncstore!");
1484 unsigned RoundWidth = 1 << Log2_32(StWidth);
1485 assert(RoundWidth < StWidth);
1486 unsigned ExtraWidth = StWidth - RoundWidth;
1487 assert(ExtraWidth < RoundWidth);
1488 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1489 "Store size not an integral number of bytes!");
1490 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1491 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1493 unsigned IncrementSize;
1495 if (TLI.isLittleEndian()) {
1496 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1497 // Store the bottom RoundWidth bits.
1498 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1500 isVolatile, isNonTemporal, Alignment);
1502 // Store the remaining ExtraWidth bits.
1503 IncrementSize = RoundWidth / 8;
1504 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1505 DAG.getIntPtrConstant(IncrementSize));
1506 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1507 DAG.getConstant(RoundWidth,
1508 TLI.getShiftAmountTy(Tmp3.getValueType())));
1509 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1510 ST->getPointerInfo().getWithOffset(IncrementSize),
1511 ExtraVT, isVolatile, isNonTemporal,
1512 MinAlign(Alignment, IncrementSize));
1514 // Big endian - avoid unaligned stores.
1515 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1516 // Store the top RoundWidth bits.
1517 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1518 DAG.getConstant(ExtraWidth,
1519 TLI.getShiftAmountTy(Tmp3.getValueType())));
1520 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1521 RoundVT, isVolatile, isNonTemporal, Alignment);
1523 // Store the remaining ExtraWidth bits.
1524 IncrementSize = RoundWidth / 8;
1525 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1526 DAG.getIntPtrConstant(IncrementSize));
1527 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1528 ST->getPointerInfo().getWithOffset(IncrementSize),
1529 ExtraVT, isVolatile, isNonTemporal,
1530 MinAlign(Alignment, IncrementSize));
1533 // The order of the stores doesn't matter.
1534 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1536 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1537 Tmp2 != ST->getBasePtr())
1538 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1543 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1544 default: assert(0 && "This action is not supported yet!");
1545 case TargetLowering::Legal:
1546 // If this is an unaligned store and the target doesn't support it,
1548 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1549 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1550 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1551 if (ST->getAlignment() < ABIAlignment)
1552 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1556 case TargetLowering::Custom:
1557 Result = TLI.LowerOperation(Result, DAG);
1560 // TRUNCSTORE:i16 i32 -> STORE i16
1561 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1562 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1563 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1564 isVolatile, isNonTemporal, Alignment);
1572 assert(Result.getValueType() == Op.getValueType() &&
1573 "Bad legalization!");
1575 // Make sure that the generated code is itself legal.
1577 Result = LegalizeOp(Result);
1579 // Note that LegalizeOp may be reentered even from single-use nodes, which
1580 // means that we always must cache transformed nodes.
1581 AddLegalizedOperand(Op, Result);
1585 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1586 SDValue Vec = Op.getOperand(0);
1587 SDValue Idx = Op.getOperand(1);
1588 DebugLoc dl = Op.getDebugLoc();
1589 // Store the value to a temporary stack slot, then LOAD the returned part.
1590 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1591 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1592 MachinePointerInfo(), false, false, 0);
1594 // Add the offset to the index.
1596 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1597 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1598 DAG.getConstant(EltSize, Idx.getValueType()));
1600 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1601 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1603 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1605 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1607 if (Op.getValueType().isVector())
1608 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1610 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1611 MachinePointerInfo(),
1612 Vec.getValueType().getVectorElementType(),
1616 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1617 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1619 SDValue Vec = Op.getOperand(0);
1620 SDValue Part = Op.getOperand(1);
1621 SDValue Idx = Op.getOperand(2);
1622 DebugLoc dl = Op.getDebugLoc();
1624 // Store the value to a temporary stack slot, then LOAD the returned part.
1626 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1627 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1628 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1630 // First store the whole vector.
1631 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1634 // Then store the inserted part.
1636 // Add the offset to the index.
1638 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1640 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1641 DAG.getConstant(EltSize, Idx.getValueType()));
1643 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1644 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1646 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1648 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1651 // Store the subvector.
1652 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1653 MachinePointerInfo(), false, false, 0);
1655 // Finally, load the updated vector.
1656 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1660 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1661 // We can't handle this case efficiently. Allocate a sufficiently
1662 // aligned object on the stack, store each element into it, then load
1663 // the result as a vector.
1664 // Create the stack frame object.
1665 EVT VT = Node->getValueType(0);
1666 EVT EltVT = VT.getVectorElementType();
1667 DebugLoc dl = Node->getDebugLoc();
1668 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1669 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1670 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1672 // Emit a store of each element to the stack slot.
1673 SmallVector<SDValue, 8> Stores;
1674 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1675 // Store (in the right endianness) the elements to memory.
1676 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1677 // Ignore undef elements.
1678 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1680 unsigned Offset = TypeByteSize*i;
1682 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1683 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1685 // If the destination vector element type is narrower than the source
1686 // element type, only store the bits necessary.
1687 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1688 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1689 Node->getOperand(i), Idx,
1690 PtrInfo.getWithOffset(Offset),
1691 EltVT, false, false, 0));
1693 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1694 Node->getOperand(i), Idx,
1695 PtrInfo.getWithOffset(Offset),
1700 if (!Stores.empty()) // Not all undef elements?
1701 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1702 &Stores[0], Stores.size());
1704 StoreChain = DAG.getEntryNode();
1706 // Result is a load from the stack slot.
1707 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1710 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1711 DebugLoc dl = Node->getDebugLoc();
1712 SDValue Tmp1 = Node->getOperand(0);
1713 SDValue Tmp2 = Node->getOperand(1);
1715 // Get the sign bit of the RHS. First obtain a value that has the same
1716 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1718 EVT FloatVT = Tmp2.getValueType();
1719 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1720 if (isTypeLegal(IVT)) {
1721 // Convert to an integer with the same sign bit.
1722 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1724 // Store the float to memory, then load the sign part out as an integer.
1725 MVT LoadTy = TLI.getPointerTy();
1726 // First create a temporary that is aligned for both the load and store.
1727 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1728 // Then store the float to it.
1730 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1732 if (TLI.isBigEndian()) {
1733 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1734 // Load out a legal integer with the same sign bit as the float.
1735 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1737 } else { // Little endian
1738 SDValue LoadPtr = StackPtr;
1739 // The float may be wider than the integer we are going to load. Advance
1740 // the pointer so that the loaded integer will contain the sign bit.
1741 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1742 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1743 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1744 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1745 // Load a legal integer containing the sign bit.
1746 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1748 // Move the sign bit to the top bit of the loaded integer.
1749 unsigned BitShift = LoadTy.getSizeInBits() -
1750 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1751 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1753 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1754 DAG.getConstant(BitShift,
1755 TLI.getShiftAmountTy(SignBit.getValueType())));
1758 // Now get the sign bit proper, by seeing whether the value is negative.
1759 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1760 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1762 // Get the absolute value of the result.
1763 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1764 // Select between the nabs and abs value based on the sign bit of
1766 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1767 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1771 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1772 SmallVectorImpl<SDValue> &Results) {
1773 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1774 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1775 " not tell us which reg is the stack pointer!");
1776 DebugLoc dl = Node->getDebugLoc();
1777 EVT VT = Node->getValueType(0);
1778 SDValue Tmp1 = SDValue(Node, 0);
1779 SDValue Tmp2 = SDValue(Node, 1);
1780 SDValue Tmp3 = Node->getOperand(2);
1781 SDValue Chain = Tmp1.getOperand(0);
1783 // Chain the dynamic stack allocation so that it doesn't modify the stack
1784 // pointer when other instructions are using the stack.
1785 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1787 SDValue Size = Tmp2.getOperand(1);
1788 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1789 Chain = SP.getValue(1);
1790 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1791 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1792 if (Align > StackAlign)
1793 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1794 DAG.getConstant(-(uint64_t)Align, VT));
1795 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1796 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1798 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1799 DAG.getIntPtrConstant(0, true), SDValue());
1801 Results.push_back(Tmp1);
1802 Results.push_back(Tmp2);
1805 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1806 /// condition code CC on the current target. This routine expands SETCC with
1807 /// illegal condition code into AND / OR of multiple SETCC values.
1808 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1809 SDValue &LHS, SDValue &RHS,
1812 EVT OpVT = LHS.getValueType();
1813 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1814 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1815 default: assert(0 && "Unknown condition code action!");
1816 case TargetLowering::Legal:
1819 case TargetLowering::Expand: {
1820 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1823 default: assert(0 && "Don't know how to expand this condition!");
1824 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1825 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1826 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1827 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1828 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1829 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1830 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1831 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1832 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1833 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1834 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1835 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1836 // FIXME: Implement more expansions.
1839 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1840 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1841 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1849 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1850 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1851 /// a load from the stack slot to DestVT, extending it if needed.
1852 /// The resultant code need not be legal.
1853 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1857 // Create the stack frame object.
1859 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1860 getTypeForEVT(*DAG.getContext()));
1861 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1863 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1864 int SPFI = StackPtrFI->getIndex();
1865 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1867 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1868 unsigned SlotSize = SlotVT.getSizeInBits();
1869 unsigned DestSize = DestVT.getSizeInBits();
1870 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1871 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1873 // Emit a store to the stack slot. Use a truncstore if the input value is
1874 // later than DestVT.
1877 if (SrcSize > SlotSize)
1878 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1879 PtrInfo, SlotVT, false, false, SrcAlign);
1881 assert(SrcSize == SlotSize && "Invalid store");
1882 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1883 PtrInfo, false, false, SrcAlign);
1886 // Result is a load from the stack slot.
1887 if (SlotSize == DestSize)
1888 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1889 false, false, DestAlign);
1891 assert(SlotSize < DestSize && "Unknown extension!");
1892 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1893 PtrInfo, SlotVT, false, false, DestAlign);
1896 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1897 DebugLoc dl = Node->getDebugLoc();
1898 // Create a vector sized/aligned stack slot, store the value to element #0,
1899 // then load the whole vector back out.
1900 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1902 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1903 int SPFI = StackPtrFI->getIndex();
1905 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1907 MachinePointerInfo::getFixedStack(SPFI),
1908 Node->getValueType(0).getVectorElementType(),
1910 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1911 MachinePointerInfo::getFixedStack(SPFI),
1916 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1917 /// support the operation, but do support the resultant vector type.
1918 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1919 unsigned NumElems = Node->getNumOperands();
1920 SDValue Value1, Value2;
1921 DebugLoc dl = Node->getDebugLoc();
1922 EVT VT = Node->getValueType(0);
1923 EVT OpVT = Node->getOperand(0).getValueType();
1924 EVT EltVT = VT.getVectorElementType();
1926 // If the only non-undef value is the low element, turn this into a
1927 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1928 bool isOnlyLowElement = true;
1929 bool MoreThanTwoValues = false;
1930 bool isConstant = true;
1931 for (unsigned i = 0; i < NumElems; ++i) {
1932 SDValue V = Node->getOperand(i);
1933 if (V.getOpcode() == ISD::UNDEF)
1936 isOnlyLowElement = false;
1937 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1940 if (!Value1.getNode()) {
1942 } else if (!Value2.getNode()) {
1945 } else if (V != Value1 && V != Value2) {
1946 MoreThanTwoValues = true;
1950 if (!Value1.getNode())
1951 return DAG.getUNDEF(VT);
1953 if (isOnlyLowElement)
1954 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1956 // If all elements are constants, create a load from the constant pool.
1958 std::vector<Constant*> CV;
1959 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1960 if (ConstantFPSDNode *V =
1961 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1962 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1963 } else if (ConstantSDNode *V =
1964 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1966 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1968 // If OpVT and EltVT don't match, EltVT is not legal and the
1969 // element values have been promoted/truncated earlier. Undo this;
1970 // we don't want a v16i8 to become a v16i32 for example.
1971 const ConstantInt *CI = V->getConstantIntValue();
1972 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1973 CI->getZExtValue()));
1976 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1977 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1978 CV.push_back(UndefValue::get(OpNTy));
1981 Constant *CP = ConstantVector::get(CV);
1982 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1983 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1984 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1985 MachinePointerInfo::getConstantPool(),
1986 false, false, Alignment);
1989 if (!MoreThanTwoValues) {
1990 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1991 for (unsigned i = 0; i < NumElems; ++i) {
1992 SDValue V = Node->getOperand(i);
1993 if (V.getOpcode() == ISD::UNDEF)
1995 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1997 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1998 // Get the splatted value into the low element of a vector register.
1999 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2001 if (Value2.getNode())
2002 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2004 Vec2 = DAG.getUNDEF(VT);
2006 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2007 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2011 // Otherwise, we can't handle this case efficiently.
2012 return ExpandVectorBuildThroughStack(Node);
2015 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2016 // does not fit into a register, return the lo part and set the hi part to the
2017 // by-reg argument. If it does fit into a single register, return the result
2018 // and leave the Hi part unset.
2019 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2021 // The input chain to this libcall is the entry node of the function.
2022 // Legalizing the call will automatically add the previous call to the
2024 SDValue InChain = DAG.getEntryNode();
2026 TargetLowering::ArgListTy Args;
2027 TargetLowering::ArgListEntry Entry;
2028 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2029 EVT ArgVT = Node->getOperand(i).getValueType();
2030 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2031 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2032 Entry.isSExt = isSigned;
2033 Entry.isZExt = !isSigned;
2034 Args.push_back(Entry);
2036 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2037 TLI.getPointerTy());
2039 // Splice the libcall in wherever FindInputOutputChains tells us to.
2040 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2042 // isTailCall may be true since the callee does not reference caller stack
2043 // frame. Check if it's in the right position.
2044 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2045 std::pair<SDValue, SDValue> CallInfo =
2046 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2047 0, TLI.getLibcallCallingConv(LC), isTailCall,
2048 /*isReturnValueUsed=*/true,
2049 Callee, Args, DAG, Node->getDebugLoc());
2051 if (!CallInfo.second.getNode())
2052 // It's a tailcall, return the chain (which is the DAG root).
2053 return DAG.getRoot();
2055 // Legalize the call sequence, starting with the chain. This will advance
2056 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2057 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2058 LegalizeOp(CallInfo.second);
2059 return CallInfo.first;
2062 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2063 /// and returning a result of type RetVT.
2064 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2065 const SDValue *Ops, unsigned NumOps,
2066 bool isSigned, DebugLoc dl) {
2067 TargetLowering::ArgListTy Args;
2068 Args.reserve(NumOps);
2070 TargetLowering::ArgListEntry Entry;
2071 for (unsigned i = 0; i != NumOps; ++i) {
2072 Entry.Node = Ops[i];
2073 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2074 Entry.isSExt = isSigned;
2075 Entry.isZExt = !isSigned;
2076 Args.push_back(Entry);
2078 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2079 TLI.getPointerTy());
2081 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2082 std::pair<SDValue,SDValue> CallInfo =
2083 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2084 false, 0, TLI.getLibcallCallingConv(LC), false,
2085 /*isReturnValueUsed=*/true,
2086 Callee, Args, DAG, dl);
2088 // Legalize the call sequence, starting with the chain. This will advance
2089 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2090 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2091 LegalizeOp(CallInfo.second);
2093 return CallInfo.first;
2096 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2097 // ExpandLibCall except that the first operand is the in-chain.
2098 std::pair<SDValue, SDValue>
2099 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2102 SDValue InChain = Node->getOperand(0);
2104 TargetLowering::ArgListTy Args;
2105 TargetLowering::ArgListEntry Entry;
2106 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2107 EVT ArgVT = Node->getOperand(i).getValueType();
2108 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2109 Entry.Node = Node->getOperand(i);
2111 Entry.isSExt = isSigned;
2112 Entry.isZExt = !isSigned;
2113 Args.push_back(Entry);
2115 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2116 TLI.getPointerTy());
2118 // Splice the libcall in wherever FindInputOutputChains tells us to.
2119 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2120 std::pair<SDValue, SDValue> CallInfo =
2121 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2122 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2123 /*isReturnValueUsed=*/true,
2124 Callee, Args, DAG, Node->getDebugLoc());
2126 // Legalize the call sequence, starting with the chain. This will advance
2127 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2128 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2129 LegalizeOp(CallInfo.second);
2133 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2134 RTLIB::Libcall Call_F32,
2135 RTLIB::Libcall Call_F64,
2136 RTLIB::Libcall Call_F80,
2137 RTLIB::Libcall Call_PPCF128) {
2139 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2140 default: assert(0 && "Unexpected request for libcall!");
2141 case MVT::f32: LC = Call_F32; break;
2142 case MVT::f64: LC = Call_F64; break;
2143 case MVT::f80: LC = Call_F80; break;
2144 case MVT::ppcf128: LC = Call_PPCF128; break;
2146 return ExpandLibCall(LC, Node, false);
2149 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2150 RTLIB::Libcall Call_I8,
2151 RTLIB::Libcall Call_I16,
2152 RTLIB::Libcall Call_I32,
2153 RTLIB::Libcall Call_I64,
2154 RTLIB::Libcall Call_I128) {
2156 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2157 default: assert(0 && "Unexpected request for libcall!");
2158 case MVT::i8: LC = Call_I8; break;
2159 case MVT::i16: LC = Call_I16; break;
2160 case MVT::i32: LC = Call_I32; break;
2161 case MVT::i64: LC = Call_I64; break;
2162 case MVT::i128: LC = Call_I128; break;
2164 return ExpandLibCall(LC, Node, isSigned);
2167 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2168 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2169 const TargetLowering &TLI) {
2171 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2172 default: assert(0 && "Unexpected request for libcall!");
2173 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2174 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2175 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2176 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2177 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2180 return TLI.getLibcallName(LC) != 0;
2183 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are
2185 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2186 unsigned OtherOpcode = 0;
2188 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2190 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2192 SDValue Op0 = Node->getOperand(0);
2193 SDValue Op1 = Node->getOperand(1);
2194 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2195 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2199 if (User->getOpcode() == OtherOpcode &&
2200 User->getOperand(0) == Op0 &&
2201 User->getOperand(1) == Op1)
2207 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2210 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2211 SmallVectorImpl<SDValue> &Results) {
2212 unsigned Opcode = Node->getOpcode();
2213 bool isSigned = Opcode == ISD::SDIVREM;
2216 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2217 default: assert(0 && "Unexpected request for libcall!");
2218 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2219 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2220 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2221 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2222 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2225 // The input chain to this libcall is the entry node of the function.
2226 // Legalizing the call will automatically add the previous call to the
2228 SDValue InChain = DAG.getEntryNode();
2230 EVT RetVT = Node->getValueType(0);
2231 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2233 TargetLowering::ArgListTy Args;
2234 TargetLowering::ArgListEntry Entry;
2235 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2236 EVT ArgVT = Node->getOperand(i).getValueType();
2237 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2238 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2239 Entry.isSExt = isSigned;
2240 Entry.isZExt = !isSigned;
2241 Args.push_back(Entry);
2244 // Also pass the return address of the remainder.
2245 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2247 Entry.Ty = RetTy->getPointerTo();
2248 Entry.isSExt = isSigned;
2249 Entry.isZExt = !isSigned;
2250 Args.push_back(Entry);
2252 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2253 TLI.getPointerTy());
2255 // Splice the libcall in wherever FindInputOutputChains tells us to.
2256 DebugLoc dl = Node->getDebugLoc();
2257 std::pair<SDValue, SDValue> CallInfo =
2258 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2259 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2260 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
2262 // Legalize the call sequence, starting with the chain. This will advance
2263 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2264 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2265 LegalizeOp(CallInfo.second);
2267 // Remainder is loaded back from the stack frame.
2268 SDValue Rem = DAG.getLoad(RetVT, dl, getLastCALLSEQ(), FIPtr,
2269 MachinePointerInfo(), false, false, 0);
2270 Results.push_back(CallInfo.first);
2271 Results.push_back(Rem);
2274 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2275 /// INT_TO_FP operation of the specified operand when the target requests that
2276 /// we expand it. At this point, we know that the result and operand types are
2277 /// legal for the target.
2278 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2282 if (Op0.getValueType() == MVT::i32) {
2283 // simple 32-bit [signed|unsigned] integer to float/double expansion
2285 // Get the stack frame index of a 8 byte buffer.
2286 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2288 // word offset constant for Hi/Lo address computation
2289 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2290 // set up Hi and Lo (into buffer) address based on endian
2291 SDValue Hi = StackSlot;
2292 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2293 TLI.getPointerTy(), StackSlot, WordOff);
2294 if (TLI.isLittleEndian())
2297 // if signed map to unsigned space
2300 // constant used to invert sign bit (signed to unsigned mapping)
2301 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2302 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2306 // store the lo of the constructed double - based on integer input
2307 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2308 Op0Mapped, Lo, MachinePointerInfo(),
2310 // initial hi portion of constructed double
2311 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2312 // store the hi of the constructed double - biased exponent
2313 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2314 MachinePointerInfo(),
2316 // load the constructed double
2317 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2318 MachinePointerInfo(), false, false, 0);
2319 // FP constant to bias correct the final result
2320 SDValue Bias = DAG.getConstantFP(isSigned ?
2321 BitsToDouble(0x4330000080000000ULL) :
2322 BitsToDouble(0x4330000000000000ULL),
2324 // subtract the bias
2325 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2328 // handle final rounding
2329 if (DestVT == MVT::f64) {
2332 } else if (DestVT.bitsLT(MVT::f64)) {
2333 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2334 DAG.getIntPtrConstant(0));
2335 } else if (DestVT.bitsGT(MVT::f64)) {
2336 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2340 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2341 // Code below here assumes !isSigned without checking again.
2343 // Implementation of unsigned i64 to f64 following the algorithm in
2344 // __floatundidf in compiler_rt. This implementation has the advantage
2345 // of performing rounding correctly, both in the default rounding mode
2346 // and in all alternate rounding modes.
2347 // TODO: Generalize this for use with other types.
2348 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2350 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2351 SDValue TwoP84PlusTwoP52 =
2352 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2354 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2356 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2357 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2358 DAG.getConstant(32, MVT::i64));
2359 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2360 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2361 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2362 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2363 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2365 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2368 // Implementation of unsigned i64 to f32.
2369 // TODO: Generalize this for use with other types.
2370 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2371 // For unsigned conversions, convert them to signed conversions using the
2372 // algorithm from the x86_64 __floatundidf in compiler_rt.
2374 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2376 SDValue ShiftConst =
2377 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2378 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2379 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2380 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2381 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2383 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2384 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2386 // TODO: This really should be implemented using a branch rather than a
2387 // select. We happen to get lucky and machinesink does the right
2388 // thing most of the time. This would be a good candidate for a
2389 //pseudo-op, or, even better, for whole-function isel.
2390 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2391 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2392 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2395 // Otherwise, implement the fully general conversion.
2397 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2398 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2399 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2400 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2401 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2402 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2403 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2404 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2405 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2406 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2407 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2409 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2410 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2412 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2413 DAG.getConstant(32, SHVT));
2414 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2415 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2417 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2418 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2419 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2420 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2421 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2422 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2423 DAG.getIntPtrConstant(0));
2426 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2428 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2429 Op0, DAG.getConstant(0, Op0.getValueType()),
2431 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2432 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2433 SignSet, Four, Zero);
2435 // If the sign bit of the integer is set, the large number will be treated
2436 // as a negative number. To counteract this, the dynamic code adds an
2437 // offset depending on the data type.
2439 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2440 default: assert(0 && "Unsupported integer type!");
2441 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2442 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2443 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2444 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2446 if (TLI.isLittleEndian()) FF <<= 32;
2447 Constant *FudgeFactor = ConstantInt::get(
2448 Type::getInt64Ty(*DAG.getContext()), FF);
2450 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2451 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2452 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2453 Alignment = std::min(Alignment, 4u);
2455 if (DestVT == MVT::f32)
2456 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2457 MachinePointerInfo::getConstantPool(),
2458 false, false, Alignment);
2461 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2462 DAG.getEntryNode(), CPIdx,
2463 MachinePointerInfo::getConstantPool(),
2464 MVT::f32, false, false, Alignment));
2467 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2470 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2471 /// *INT_TO_FP operation of the specified operand when the target requests that
2472 /// we promote it. At this point, we know that the result and operand types are
2473 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2474 /// operation that takes a larger input.
2475 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2479 // First step, figure out the appropriate *INT_TO_FP operation to use.
2480 EVT NewInTy = LegalOp.getValueType();
2482 unsigned OpToUse = 0;
2484 // Scan for the appropriate larger type to use.
2486 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2487 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2489 // If the target supports SINT_TO_FP of this type, use it.
2490 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2491 OpToUse = ISD::SINT_TO_FP;
2494 if (isSigned) continue;
2496 // If the target supports UINT_TO_FP of this type, use it.
2497 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2498 OpToUse = ISD::UINT_TO_FP;
2502 // Otherwise, try a larger type.
2505 // Okay, we found the operation and type to use. Zero extend our input to the
2506 // desired type then run the operation on it.
2507 return DAG.getNode(OpToUse, dl, DestVT,
2508 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2509 dl, NewInTy, LegalOp));
2512 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2513 /// FP_TO_*INT operation of the specified operand when the target requests that
2514 /// we promote it. At this point, we know that the result and operand types are
2515 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2516 /// operation that returns a larger result.
2517 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2521 // First step, figure out the appropriate FP_TO*INT operation to use.
2522 EVT NewOutTy = DestVT;
2524 unsigned OpToUse = 0;
2526 // Scan for the appropriate larger type to use.
2528 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2529 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2531 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2532 OpToUse = ISD::FP_TO_SINT;
2536 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2537 OpToUse = ISD::FP_TO_UINT;
2541 // Otherwise, try a larger type.
2545 // Okay, we found the operation and type to use.
2546 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2548 // Truncate the result of the extended FP_TO_*INT operation to the desired
2550 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2553 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2555 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2556 EVT VT = Op.getValueType();
2557 EVT SHVT = TLI.getShiftAmountTy(VT);
2558 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2559 switch (VT.getSimpleVT().SimpleTy) {
2560 default: assert(0 && "Unhandled Expand type in BSWAP!");
2562 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2563 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2564 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2566 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2567 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2568 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2569 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2570 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2571 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2572 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2573 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2574 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2576 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2577 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2578 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2579 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2580 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2581 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2582 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2583 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2584 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2585 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2586 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2587 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2588 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2589 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2590 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2591 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2592 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2593 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2594 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2595 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2596 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2600 /// SplatByte - Distribute ByteVal over NumBits bits.
2601 // FIXME: Move this helper to a common place.
2602 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2603 APInt Val = APInt(NumBits, ByteVal);
2605 for (unsigned i = NumBits; i > 8; i >>= 1) {
2606 Val = (Val << Shift) | Val;
2612 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2614 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2617 default: assert(0 && "Cannot expand this yet!");
2619 EVT VT = Op.getValueType();
2620 EVT ShVT = TLI.getShiftAmountTy(VT);
2621 unsigned Len = VT.getSizeInBits();
2623 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2624 "CTPOP not implemented for this type.");
2626 // This is the "best" algorithm from
2627 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2629 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2630 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2631 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2632 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2634 // v = v - ((v >> 1) & 0x55555555...)
2635 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2636 DAG.getNode(ISD::AND, dl, VT,
2637 DAG.getNode(ISD::SRL, dl, VT, Op,
2638 DAG.getConstant(1, ShVT)),
2640 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2641 Op = DAG.getNode(ISD::ADD, dl, VT,
2642 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2643 DAG.getNode(ISD::AND, dl, VT,
2644 DAG.getNode(ISD::SRL, dl, VT, Op,
2645 DAG.getConstant(2, ShVT)),
2647 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2648 Op = DAG.getNode(ISD::AND, dl, VT,
2649 DAG.getNode(ISD::ADD, dl, VT, Op,
2650 DAG.getNode(ISD::SRL, dl, VT, Op,
2651 DAG.getConstant(4, ShVT))),
2653 // v = (v * 0x01010101...) >> (Len - 8)
2654 Op = DAG.getNode(ISD::SRL, dl, VT,
2655 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2656 DAG.getConstant(Len - 8, ShVT));
2661 // for now, we do this:
2662 // x = x | (x >> 1);
2663 // x = x | (x >> 2);
2665 // x = x | (x >>16);
2666 // x = x | (x >>32); // for 64-bit input
2667 // return popcount(~x);
2669 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2670 EVT VT = Op.getValueType();
2671 EVT ShVT = TLI.getShiftAmountTy(VT);
2672 unsigned len = VT.getSizeInBits();
2673 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2674 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2675 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2676 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2678 Op = DAG.getNOT(dl, Op, VT);
2679 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2682 // for now, we use: { return popcount(~x & (x - 1)); }
2683 // unless the target has ctlz but not ctpop, in which case we use:
2684 // { return 32 - nlz(~x & (x-1)); }
2685 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2686 EVT VT = Op.getValueType();
2687 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2688 DAG.getNOT(dl, Op, VT),
2689 DAG.getNode(ISD::SUB, dl, VT, Op,
2690 DAG.getConstant(1, VT)));
2691 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2692 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2693 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2694 return DAG.getNode(ISD::SUB, dl, VT,
2695 DAG.getConstant(VT.getSizeInBits(), VT),
2696 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2697 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2702 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2703 unsigned Opc = Node->getOpcode();
2704 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2709 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2711 case ISD::ATOMIC_SWAP:
2712 switch (VT.SimpleTy) {
2713 default: llvm_unreachable("Unexpected value type for atomic!");
2714 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2715 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2716 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2717 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2720 case ISD::ATOMIC_CMP_SWAP:
2721 switch (VT.SimpleTy) {
2722 default: llvm_unreachable("Unexpected value type for atomic!");
2723 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2724 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2725 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2726 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2729 case ISD::ATOMIC_LOAD_ADD:
2730 switch (VT.SimpleTy) {
2731 default: llvm_unreachable("Unexpected value type for atomic!");
2732 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2733 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2734 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2735 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2738 case ISD::ATOMIC_LOAD_SUB:
2739 switch (VT.SimpleTy) {
2740 default: llvm_unreachable("Unexpected value type for atomic!");
2741 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2742 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2743 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2744 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2747 case ISD::ATOMIC_LOAD_AND:
2748 switch (VT.SimpleTy) {
2749 default: llvm_unreachable("Unexpected value type for atomic!");
2750 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2751 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2752 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2753 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2756 case ISD::ATOMIC_LOAD_OR:
2757 switch (VT.SimpleTy) {
2758 default: llvm_unreachable("Unexpected value type for atomic!");
2759 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2760 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2761 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2762 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2765 case ISD::ATOMIC_LOAD_XOR:
2766 switch (VT.SimpleTy) {
2767 default: llvm_unreachable("Unexpected value type for atomic!");
2768 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2769 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2770 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2771 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2774 case ISD::ATOMIC_LOAD_NAND:
2775 switch (VT.SimpleTy) {
2776 default: llvm_unreachable("Unexpected value type for atomic!");
2777 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2778 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2779 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2780 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2785 return ExpandChainLibCall(LC, Node, false);
2788 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2789 SmallVectorImpl<SDValue> &Results) {
2790 DebugLoc dl = Node->getDebugLoc();
2791 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2792 switch (Node->getOpcode()) {
2796 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2797 Results.push_back(Tmp1);
2800 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2802 case ISD::FRAMEADDR:
2803 case ISD::RETURNADDR:
2804 case ISD::FRAME_TO_ARGS_OFFSET:
2805 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2807 case ISD::FLT_ROUNDS_:
2808 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2810 case ISD::EH_RETURN:
2814 case ISD::EH_SJLJ_LONGJMP:
2815 case ISD::EH_SJLJ_DISPATCHSETUP:
2816 // If the target didn't expand these, there's nothing to do, so just
2817 // preserve the chain and be done.
2818 Results.push_back(Node->getOperand(0));
2820 case ISD::EH_SJLJ_SETJMP:
2821 // If the target didn't expand this, just return 'zero' and preserve the
2823 Results.push_back(DAG.getConstant(0, MVT::i32));
2824 Results.push_back(Node->getOperand(0));
2826 case ISD::MEMBARRIER: {
2827 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2828 TargetLowering::ArgListTy Args;
2829 std::pair<SDValue, SDValue> CallResult =
2830 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2831 false, false, false, false, 0, CallingConv::C,
2832 /*isTailCall=*/false,
2833 /*isReturnValueUsed=*/true,
2834 DAG.getExternalSymbol("__sync_synchronize",
2835 TLI.getPointerTy()),
2837 Results.push_back(CallResult.second);
2840 // By default, atomic intrinsics are marked Legal and lowered. Targets
2841 // which don't support them directly, however, may want libcalls, in which
2842 // case they mark them Expand, and we get here.
2843 case ISD::ATOMIC_SWAP:
2844 case ISD::ATOMIC_LOAD_ADD:
2845 case ISD::ATOMIC_LOAD_SUB:
2846 case ISD::ATOMIC_LOAD_AND:
2847 case ISD::ATOMIC_LOAD_OR:
2848 case ISD::ATOMIC_LOAD_XOR:
2849 case ISD::ATOMIC_LOAD_NAND:
2850 case ISD::ATOMIC_LOAD_MIN:
2851 case ISD::ATOMIC_LOAD_MAX:
2852 case ISD::ATOMIC_LOAD_UMIN:
2853 case ISD::ATOMIC_LOAD_UMAX:
2854 case ISD::ATOMIC_CMP_SWAP: {
2855 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2856 Results.push_back(Tmp.first);
2857 Results.push_back(Tmp.second);
2860 case ISD::DYNAMIC_STACKALLOC:
2861 ExpandDYNAMIC_STACKALLOC(Node, Results);
2863 case ISD::MERGE_VALUES:
2864 for (unsigned i = 0; i < Node->getNumValues(); i++)
2865 Results.push_back(Node->getOperand(i));
2868 EVT VT = Node->getValueType(0);
2870 Results.push_back(DAG.getConstant(0, VT));
2872 assert(VT.isFloatingPoint() && "Unknown value type!");
2873 Results.push_back(DAG.getConstantFP(0, VT));
2878 // If this operation is not supported, lower it to 'abort()' call
2879 TargetLowering::ArgListTy Args;
2880 std::pair<SDValue, SDValue> CallResult =
2881 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2882 false, false, false, false, 0, CallingConv::C,
2883 /*isTailCall=*/false,
2884 /*isReturnValueUsed=*/true,
2885 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2887 Results.push_back(CallResult.second);
2892 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2893 Node->getValueType(0), dl);
2894 Results.push_back(Tmp1);
2896 case ISD::FP_EXTEND:
2897 Tmp1 = EmitStackConvert(Node->getOperand(0),
2898 Node->getOperand(0).getValueType(),
2899 Node->getValueType(0), dl);
2900 Results.push_back(Tmp1);
2902 case ISD::SIGN_EXTEND_INREG: {
2903 // NOTE: we could fall back on load/store here too for targets without
2904 // SAR. However, it is doubtful that any exist.
2905 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2906 EVT VT = Node->getValueType(0);
2907 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2910 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2911 ExtraVT.getScalarType().getSizeInBits();
2912 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2913 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2914 Node->getOperand(0), ShiftCst);
2915 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2916 Results.push_back(Tmp1);
2919 case ISD::FP_ROUND_INREG: {
2920 // The only way we can lower this is to turn it into a TRUNCSTORE,
2921 // EXTLOAD pair, targeting a temporary location (a stack slot).
2923 // NOTE: there is a choice here between constantly creating new stack
2924 // slots and always reusing the same one. We currently always create
2925 // new ones, as reuse may inhibit scheduling.
2926 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2927 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2928 Node->getValueType(0), dl);
2929 Results.push_back(Tmp1);
2932 case ISD::SINT_TO_FP:
2933 case ISD::UINT_TO_FP:
2934 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2935 Node->getOperand(0), Node->getValueType(0), dl);
2936 Results.push_back(Tmp1);
2938 case ISD::FP_TO_UINT: {
2939 SDValue True, False;
2940 EVT VT = Node->getOperand(0).getValueType();
2941 EVT NVT = Node->getValueType(0);
2942 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2943 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2944 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2945 Tmp1 = DAG.getConstantFP(apf, VT);
2946 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2947 Node->getOperand(0),
2949 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2950 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2951 DAG.getNode(ISD::FSUB, dl, VT,
2952 Node->getOperand(0), Tmp1));
2953 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2954 DAG.getConstant(x, NVT));
2955 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2956 Results.push_back(Tmp1);
2960 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2961 EVT VT = Node->getValueType(0);
2962 Tmp1 = Node->getOperand(0);
2963 Tmp2 = Node->getOperand(1);
2964 unsigned Align = Node->getConstantOperandVal(3);
2966 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2967 MachinePointerInfo(V), false, false, 0);
2968 SDValue VAList = VAListLoad;
2970 if (Align > TLI.getMinStackArgumentAlignment()) {
2971 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2973 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2974 DAG.getConstant(Align - 1,
2975 TLI.getPointerTy()));
2977 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2978 DAG.getConstant(-(int64_t)Align,
2979 TLI.getPointerTy()));
2982 // Increment the pointer, VAList, to the next vaarg
2983 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2984 DAG.getConstant(TLI.getTargetData()->
2985 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2986 TLI.getPointerTy()));
2987 // Store the incremented VAList to the legalized pointer
2988 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2989 MachinePointerInfo(V), false, false, 0);
2990 // Load the actual argument out of the pointer VAList
2991 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2993 Results.push_back(Results[0].getValue(1));
2997 // This defaults to loading a pointer from the input and storing it to the
2998 // output, returning the chain.
2999 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3000 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3001 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3002 Node->getOperand(2), MachinePointerInfo(VS),
3004 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3005 MachinePointerInfo(VD), false, false, 0);
3006 Results.push_back(Tmp1);
3009 case ISD::EXTRACT_VECTOR_ELT:
3010 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3011 // This must be an access of the only element. Return it.
3012 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3013 Node->getOperand(0));
3015 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3016 Results.push_back(Tmp1);
3018 case ISD::EXTRACT_SUBVECTOR:
3019 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3021 case ISD::INSERT_SUBVECTOR:
3022 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3024 case ISD::CONCAT_VECTORS: {
3025 Results.push_back(ExpandVectorBuildThroughStack(Node));
3028 case ISD::SCALAR_TO_VECTOR:
3029 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3031 case ISD::INSERT_VECTOR_ELT:
3032 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3033 Node->getOperand(1),
3034 Node->getOperand(2), dl));
3036 case ISD::VECTOR_SHUFFLE: {
3037 SmallVector<int, 8> Mask;
3038 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3040 EVT VT = Node->getValueType(0);
3041 EVT EltVT = VT.getVectorElementType();
3042 if (getTypeAction(EltVT) == Promote)
3043 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3044 unsigned NumElems = VT.getVectorNumElements();
3045 SmallVector<SDValue, 8> Ops;
3046 for (unsigned i = 0; i != NumElems; ++i) {
3048 Ops.push_back(DAG.getUNDEF(EltVT));
3051 unsigned Idx = Mask[i];
3053 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3054 Node->getOperand(0),
3055 DAG.getIntPtrConstant(Idx)));
3057 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3058 Node->getOperand(1),
3059 DAG.getIntPtrConstant(Idx - NumElems)));
3061 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3062 Results.push_back(Tmp1);
3065 case ISD::EXTRACT_ELEMENT: {
3066 EVT OpTy = Node->getOperand(0).getValueType();
3067 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3069 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3070 DAG.getConstant(OpTy.getSizeInBits()/2,
3071 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3072 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3075 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3076 Node->getOperand(0));
3078 Results.push_back(Tmp1);
3081 case ISD::STACKSAVE:
3082 // Expand to CopyFromReg if the target set
3083 // StackPointerRegisterToSaveRestore.
3084 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3085 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3086 Node->getValueType(0)));
3087 Results.push_back(Results[0].getValue(1));
3089 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3090 Results.push_back(Node->getOperand(0));
3093 case ISD::STACKRESTORE:
3094 // Expand to CopyToReg if the target set
3095 // StackPointerRegisterToSaveRestore.
3096 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3097 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3098 Node->getOperand(1)));
3100 Results.push_back(Node->getOperand(0));
3103 case ISD::FCOPYSIGN:
3104 Results.push_back(ExpandFCOPYSIGN(Node));
3107 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3108 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3109 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3110 Node->getOperand(0));
3111 Results.push_back(Tmp1);
3114 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3115 EVT VT = Node->getValueType(0);
3116 Tmp1 = Node->getOperand(0);
3117 Tmp2 = DAG.getConstantFP(0.0, VT);
3118 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3119 Tmp1, Tmp2, ISD::SETUGT);
3120 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3121 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3122 Results.push_back(Tmp1);
3126 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3127 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3130 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3131 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3134 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3135 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3138 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3139 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3142 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3143 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3146 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3147 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3150 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3151 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3154 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3155 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3158 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3159 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3162 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3163 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3166 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3167 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3170 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3171 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3173 case ISD::FNEARBYINT:
3174 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3175 RTLIB::NEARBYINT_F64,
3176 RTLIB::NEARBYINT_F80,
3177 RTLIB::NEARBYINT_PPCF128));
3180 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3181 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3184 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3185 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3188 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3189 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3192 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3193 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3195 case ISD::FP16_TO_FP32:
3196 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3198 case ISD::FP32_TO_FP16:
3199 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3201 case ISD::ConstantFP: {
3202 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3203 // Check to see if this FP immediate is already legal.
3204 // If this is a legal constant, turn it into a TargetConstantFP node.
3205 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3206 Results.push_back(SDValue(Node, 0));
3208 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3211 case ISD::EHSELECTION: {
3212 unsigned Reg = TLI.getExceptionSelectorRegister();
3213 assert(Reg && "Can't expand to unknown register!");
3214 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3215 Node->getValueType(0)));
3216 Results.push_back(Results[0].getValue(1));
3219 case ISD::EXCEPTIONADDR: {
3220 unsigned Reg = TLI.getExceptionAddressRegister();
3221 assert(Reg && "Can't expand to unknown register!");
3222 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3223 Node->getValueType(0)));
3224 Results.push_back(Results[0].getValue(1));
3228 EVT VT = Node->getValueType(0);
3229 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3230 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3231 "Don't know how to expand this subtraction!");
3232 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3233 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3234 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3235 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3240 EVT VT = Node->getValueType(0);
3241 SDVTList VTs = DAG.getVTList(VT, VT);
3242 bool isSigned = Node->getOpcode() == ISD::SREM;
3243 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3244 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3245 Tmp2 = Node->getOperand(0);
3246 Tmp3 = Node->getOperand(1);
3247 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3248 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3249 UseDivRem(Node, isSigned, false))) {
3250 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3251 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3253 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3254 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3255 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3256 } else if (isSigned)
3257 Tmp1 = ExpandIntLibCall(Node, true,
3259 RTLIB::SREM_I16, RTLIB::SREM_I32,
3260 RTLIB::SREM_I64, RTLIB::SREM_I128);
3262 Tmp1 = ExpandIntLibCall(Node, false,
3264 RTLIB::UREM_I16, RTLIB::UREM_I32,
3265 RTLIB::UREM_I64, RTLIB::UREM_I128);
3266 Results.push_back(Tmp1);
3271 bool isSigned = Node->getOpcode() == ISD::SDIV;
3272 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3273 EVT VT = Node->getValueType(0);
3274 SDVTList VTs = DAG.getVTList(VT, VT);
3275 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3276 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3277 UseDivRem(Node, isSigned, true)))
3278 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3279 Node->getOperand(1));
3281 Tmp1 = ExpandIntLibCall(Node, true,
3283 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3284 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3286 Tmp1 = ExpandIntLibCall(Node, false,
3288 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3289 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3290 Results.push_back(Tmp1);
3295 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3297 EVT VT = Node->getValueType(0);
3298 SDVTList VTs = DAG.getVTList(VT, VT);
3299 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3300 "If this wasn't legal, it shouldn't have been created!");
3301 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3302 Node->getOperand(1));
3303 Results.push_back(Tmp1.getValue(1));
3308 // Expand into divrem libcall
3309 ExpandDivRemLibCall(Node, Results);
3312 EVT VT = Node->getValueType(0);
3313 SDVTList VTs = DAG.getVTList(VT, VT);
3314 // See if multiply or divide can be lowered using two-result operations.
3315 // We just need the low half of the multiply; try both the signed
3316 // and unsigned forms. If the target supports both SMUL_LOHI and
3317 // UMUL_LOHI, form a preference by checking which forms of plain
3318 // MULH it supports.
3319 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3320 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3321 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3322 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3323 unsigned OpToUse = 0;
3324 if (HasSMUL_LOHI && !HasMULHS) {
3325 OpToUse = ISD::SMUL_LOHI;
3326 } else if (HasUMUL_LOHI && !HasMULHU) {
3327 OpToUse = ISD::UMUL_LOHI;
3328 } else if (HasSMUL_LOHI) {
3329 OpToUse = ISD::SMUL_LOHI;
3330 } else if (HasUMUL_LOHI) {
3331 OpToUse = ISD::UMUL_LOHI;
3334 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3335 Node->getOperand(1)));
3338 Tmp1 = ExpandIntLibCall(Node, false,
3340 RTLIB::MUL_I16, RTLIB::MUL_I32,
3341 RTLIB::MUL_I64, RTLIB::MUL_I128);
3342 Results.push_back(Tmp1);
3347 SDValue LHS = Node->getOperand(0);
3348 SDValue RHS = Node->getOperand(1);
3349 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3350 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3352 Results.push_back(Sum);
3353 EVT OType = Node->getValueType(1);
3355 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3357 // LHSSign -> LHS >= 0
3358 // RHSSign -> RHS >= 0
3359 // SumSign -> Sum >= 0
3362 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3364 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3366 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3367 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3368 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3369 Node->getOpcode() == ISD::SADDO ?
3370 ISD::SETEQ : ISD::SETNE);
3372 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3373 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3375 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3376 Results.push_back(Cmp);
3381 SDValue LHS = Node->getOperand(0);
3382 SDValue RHS = Node->getOperand(1);
3383 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3384 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3386 Results.push_back(Sum);
3387 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3388 Node->getOpcode () == ISD::UADDO ?
3389 ISD::SETULT : ISD::SETUGT));
3394 EVT VT = Node->getValueType(0);
3395 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3396 SDValue LHS = Node->getOperand(0);
3397 SDValue RHS = Node->getOperand(1);
3400 static const unsigned Ops[2][3] =
3401 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3402 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3403 bool isSigned = Node->getOpcode() == ISD::SMULO;
3404 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3405 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3406 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3407 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3408 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3410 TopHalf = BottomHalf.getValue(1);
3411 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3412 VT.getSizeInBits() * 2))) {
3413 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3414 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3415 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3416 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3417 DAG.getIntPtrConstant(0));
3418 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3419 DAG.getIntPtrConstant(1));
3421 // We can fall back to a libcall with an illegal type for the MUL if we
3422 // have a libcall big enough.
3423 // Also, we can fall back to a division in some cases, but that's a big
3424 // performance hit in the general case.
3425 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3426 if (WideVT == MVT::i16)
3427 LC = RTLIB::MUL_I16;
3428 else if (WideVT == MVT::i32)
3429 LC = RTLIB::MUL_I32;
3430 else if (WideVT == MVT::i64)
3431 LC = RTLIB::MUL_I64;
3432 else if (WideVT == MVT::i128)
3433 LC = RTLIB::MUL_I128;
3434 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3436 // The high part is obtained by SRA'ing all but one of the bits of low
3438 unsigned LoSize = VT.getSizeInBits();
3439 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3440 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3441 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3442 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3444 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3445 // pre-lowered to the correct types. This all depends upon WideVT not
3446 // being a legal type for the architecture and thus has to be split to
3448 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3449 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3450 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3451 DAG.getIntPtrConstant(0));
3452 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3453 DAG.getIntPtrConstant(1));
3457 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3458 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3459 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3460 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3463 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3464 DAG.getConstant(0, VT), ISD::SETNE);
3466 Results.push_back(BottomHalf);
3467 Results.push_back(TopHalf);
3470 case ISD::BUILD_PAIR: {
3471 EVT PairTy = Node->getValueType(0);
3472 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3473 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3474 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3475 DAG.getConstant(PairTy.getSizeInBits()/2,
3476 TLI.getShiftAmountTy(PairTy)));
3477 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3481 Tmp1 = Node->getOperand(0);
3482 Tmp2 = Node->getOperand(1);
3483 Tmp3 = Node->getOperand(2);
3484 if (Tmp1.getOpcode() == ISD::SETCC) {
3485 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3487 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3489 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3490 DAG.getConstant(0, Tmp1.getValueType()),
3491 Tmp2, Tmp3, ISD::SETNE);
3493 Results.push_back(Tmp1);
3496 SDValue Chain = Node->getOperand(0);
3497 SDValue Table = Node->getOperand(1);
3498 SDValue Index = Node->getOperand(2);
3500 EVT PTy = TLI.getPointerTy();
3502 const TargetData &TD = *TLI.getTargetData();
3503 unsigned EntrySize =
3504 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3506 Index = DAG.getNode(ISD::MUL, dl, PTy,
3507 Index, DAG.getConstant(EntrySize, PTy));
3508 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3510 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3511 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3512 MachinePointerInfo::getJumpTable(), MemVT,
3515 if (TM.getRelocationModel() == Reloc::PIC_) {
3516 // For PIC, the sequence is:
3517 // BRIND(load(Jumptable + index) + RelocBase)
3518 // RelocBase can be JumpTable, GOT or some sort of global base.
3519 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3520 TLI.getPICJumpTableRelocBase(Table, DAG));
3522 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3523 Results.push_back(Tmp1);
3527 // Expand brcond's setcc into its constituent parts and create a BR_CC
3529 Tmp1 = Node->getOperand(0);
3530 Tmp2 = Node->getOperand(1);
3531 if (Tmp2.getOpcode() == ISD::SETCC) {
3532 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3533 Tmp1, Tmp2.getOperand(2),
3534 Tmp2.getOperand(0), Tmp2.getOperand(1),
3535 Node->getOperand(2));
3537 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3538 DAG.getCondCode(ISD::SETNE), Tmp2,
3539 DAG.getConstant(0, Tmp2.getValueType()),
3540 Node->getOperand(2));
3542 Results.push_back(Tmp1);
3545 Tmp1 = Node->getOperand(0);
3546 Tmp2 = Node->getOperand(1);
3547 Tmp3 = Node->getOperand(2);
3548 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3550 // If we expanded the SETCC into an AND/OR, return the new node
3551 if (Tmp2.getNode() == 0) {
3552 Results.push_back(Tmp1);
3556 // Otherwise, SETCC for the given comparison type must be completely
3557 // illegal; expand it into a SELECT_CC.
3558 EVT VT = Node->getValueType(0);
3559 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3560 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3561 Results.push_back(Tmp1);
3564 case ISD::SELECT_CC: {
3565 Tmp1 = Node->getOperand(0); // LHS
3566 Tmp2 = Node->getOperand(1); // RHS
3567 Tmp3 = Node->getOperand(2); // True
3568 Tmp4 = Node->getOperand(3); // False
3569 SDValue CC = Node->getOperand(4);
3571 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3572 Tmp1, Tmp2, CC, dl);
3574 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3575 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3576 CC = DAG.getCondCode(ISD::SETNE);
3577 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3579 Results.push_back(Tmp1);
3583 Tmp1 = Node->getOperand(0); // Chain
3584 Tmp2 = Node->getOperand(2); // LHS
3585 Tmp3 = Node->getOperand(3); // RHS
3586 Tmp4 = Node->getOperand(1); // CC
3588 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3589 Tmp2, Tmp3, Tmp4, dl);
3590 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
3591 setLastCALLSEQ(DAG.getEntryNode());
3593 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3594 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3595 Tmp4 = DAG.getCondCode(ISD::SETNE);
3596 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3597 Tmp3, Node->getOperand(4));
3598 Results.push_back(Tmp1);
3601 case ISD::GLOBAL_OFFSET_TABLE:
3602 case ISD::GlobalAddress:
3603 case ISD::GlobalTLSAddress:
3604 case ISD::ExternalSymbol:
3605 case ISD::ConstantPool:
3606 case ISD::JumpTable:
3607 case ISD::INTRINSIC_W_CHAIN:
3608 case ISD::INTRINSIC_WO_CHAIN:
3609 case ISD::INTRINSIC_VOID:
3610 // FIXME: Custom lowering for these operations shouldn't return null!
3611 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3612 Results.push_back(SDValue(Node, i));
3616 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3617 SmallVectorImpl<SDValue> &Results) {
3618 EVT OVT = Node->getValueType(0);
3619 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3620 Node->getOpcode() == ISD::SINT_TO_FP ||
3621 Node->getOpcode() == ISD::SETCC) {
3622 OVT = Node->getOperand(0).getValueType();
3624 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3625 DebugLoc dl = Node->getDebugLoc();
3626 SDValue Tmp1, Tmp2, Tmp3;
3627 switch (Node->getOpcode()) {
3631 // Zero extend the argument.
3632 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3633 // Perform the larger operation.
3634 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3635 if (Node->getOpcode() == ISD::CTTZ) {
3636 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3637 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3638 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3640 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3641 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3642 } else if (Node->getOpcode() == ISD::CTLZ) {
3643 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3644 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3645 DAG.getConstant(NVT.getSizeInBits() -
3646 OVT.getSizeInBits(), NVT));
3648 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3651 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3652 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3653 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3654 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3655 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3656 Results.push_back(Tmp1);
3659 case ISD::FP_TO_UINT:
3660 case ISD::FP_TO_SINT:
3661 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3662 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3663 Results.push_back(Tmp1);
3665 case ISD::UINT_TO_FP:
3666 case ISD::SINT_TO_FP:
3667 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3668 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3669 Results.push_back(Tmp1);
3674 unsigned ExtOp, TruncOp;
3675 if (OVT.isVector()) {
3676 ExtOp = ISD::BITCAST;
3677 TruncOp = ISD::BITCAST;
3679 assert(OVT.isInteger() && "Cannot promote logic operation");
3680 ExtOp = ISD::ANY_EXTEND;
3681 TruncOp = ISD::TRUNCATE;
3683 // Promote each of the values to the new type.
3684 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3685 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3686 // Perform the larger operation, then convert back
3687 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3688 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3692 unsigned ExtOp, TruncOp;
3693 if (Node->getValueType(0).isVector()) {
3694 ExtOp = ISD::BITCAST;
3695 TruncOp = ISD::BITCAST;
3696 } else if (Node->getValueType(0).isInteger()) {
3697 ExtOp = ISD::ANY_EXTEND;
3698 TruncOp = ISD::TRUNCATE;
3700 ExtOp = ISD::FP_EXTEND;
3701 TruncOp = ISD::FP_ROUND;
3703 Tmp1 = Node->getOperand(0);
3704 // Promote each of the values to the new type.
3705 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3706 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3707 // Perform the larger operation, then round down.
3708 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3709 if (TruncOp != ISD::FP_ROUND)
3710 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3712 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3713 DAG.getIntPtrConstant(0));
3714 Results.push_back(Tmp1);
3717 case ISD::VECTOR_SHUFFLE: {
3718 SmallVector<int, 8> Mask;
3719 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3721 // Cast the two input vectors.
3722 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3723 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3725 // Convert the shuffle mask to the right # elements.
3726 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3727 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3728 Results.push_back(Tmp1);
3732 unsigned ExtOp = ISD::FP_EXTEND;
3733 if (NVT.isInteger()) {
3734 ISD::CondCode CCCode =
3735 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3736 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3738 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3739 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3740 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3741 Tmp1, Tmp2, Node->getOperand(2)));
3747 // SelectionDAG::Legalize - This is the entry point for the file.
3749 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3750 /// run - This is the main entry point to this class.
3752 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();