1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/SmallPtrSet.h"
36 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
37 cl::desc("Pop up a window to show dags before legalize"));
39 static const bool ViewLegalizeDAGs = 0;
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
59 // Libcall insertion helpers.
61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
62 /// legalized. We use this to ensure that calls are properly serialized
63 /// against each other, including inserted libcalls.
64 SDOperand LastCALLSEQ_END;
66 /// IsLegalizingCall - This member is used *only* for purposes of providing
67 /// helpful assertions that a libcall isn't created while another call is
68 /// being legalized (which could lead to non-serialized call sequences).
69 bool IsLegalizingCall;
72 Legal, // The target natively supports this operation.
73 Promote, // This operation should be executed in a larger type.
74 Expand // Try to expand this to other ops, otherwise use a libcall.
77 /// ValueTypeActions - This is a bitvector that contains two bits for each
78 /// value type, where the two bits correspond to the LegalizeAction enum.
79 /// This can be queried with "getTypeAction(VT)".
80 TargetLowering::ValueTypeActionImpl ValueTypeActions;
82 /// LegalizedNodes - For nodes that are of legal width, and that have more
83 /// than one use, this map indicates what regularized operand to use. This
84 /// allows us to avoid legalizing the same thing more than once.
85 DenseMap<SDOperand, SDOperand> LegalizedNodes;
87 /// PromotedNodes - For nodes that are below legal width, and that have more
88 /// than one use, this map indicates what promoted value to use. This allows
89 /// us to avoid promoting the same thing more than once.
90 DenseMap<SDOperand, SDOperand> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which which operands are the expanded version of the input. This allows
94 /// us to avoid expanding the same node more than once.
95 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
97 /// SplitNodes - For vector nodes that need to be split, this map indicates
98 /// which which operands are the split version of the input. This allows us
99 /// to avoid splitting the same node more than once.
100 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
102 /// ScalarizedNodes - For nodes that need to be converted from vector types to
103 /// scalar types, this contains the mapping of ones we have already
104 /// processed to the result.
105 std::map<SDOperand, SDOperand> ScalarizedNodes;
107 void AddLegalizedOperand(SDOperand From, SDOperand To) {
108 LegalizedNodes.insert(std::make_pair(From, To));
109 // If someone requests legalization of the new node, return itself.
111 LegalizedNodes.insert(std::make_pair(To, To));
113 void AddPromotedOperand(SDOperand From, SDOperand To) {
114 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
115 assert(isNew && "Got into the map somehow?");
116 // If someone requests legalization of the new node, return itself.
117 LegalizedNodes.insert(std::make_pair(To, To));
122 SelectionDAGLegalize(SelectionDAG &DAG);
124 /// getTypeAction - Return how we should legalize values of this type, either
125 /// it is already legal or we need to expand it into multiple registers of
126 /// smaller integer type, or we need to promote it to a larger type.
127 LegalizeAction getTypeAction(MVT::ValueType VT) const {
128 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
131 /// isTypeLegal - Return true if this type is legal on this target.
133 bool isTypeLegal(MVT::ValueType VT) const {
134 return getTypeAction(VT) == Legal;
140 /// HandleOp - Legalize, Promote, or Expand the specified operand as
141 /// appropriate for its type.
142 void HandleOp(SDOperand Op);
144 /// LegalizeOp - We know that the specified value has a legal type.
145 /// Recursively ensure that the operands have legal types, then return the
147 SDOperand LegalizeOp(SDOperand O);
149 /// PromoteOp - Given an operation that produces a value in an invalid type,
150 /// promote it to compute the value into a larger type. The produced value
151 /// will have the correct bits for the low portion of the register, but no
152 /// guarantee is made about the top bits: it may be zero, sign-extended, or
154 SDOperand PromoteOp(SDOperand O);
156 /// ExpandOp - Expand the specified SDOperand into its two component pieces
157 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
158 /// the LegalizeNodes map is filled in for any results that are not expanded,
159 /// the ExpandedNodes map is filled in for any results that are expanded, and
160 /// the Lo/Hi values are returned. This applies to integer types and Vector
162 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// SplitVectorOp - Given an operand of vector type, break it down into
165 /// two smaller values.
166 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
168 /// ScalarizeVectorOp - Given an operand of single-element vector type
169 /// (e.g. v1f32), convert it into the equivalent operation that returns a
170 /// scalar (e.g. f32) value.
171 SDOperand ScalarizeVectorOp(SDOperand O);
173 /// isShuffleLegal - Return true if a vector shuffle is legal with the
174 /// specified mask and type. Targets can specify exactly which masks they
175 /// support and the code generator is tasked with not creating illegal masks.
177 /// Note that this will also return true for shuffles that are promoted to a
180 /// If this is a legal shuffle, this method returns the (possibly promoted)
181 /// build_vector Mask. If it's not a legal shuffle, it returns null.
182 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
184 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
185 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
187 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
189 SDOperand CreateStackTemporary(MVT::ValueType VT);
191 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
193 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
196 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
197 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
198 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
199 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
201 MVT::ValueType DestVT);
202 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
207 SDOperand ExpandBSWAP(SDOperand Op);
208 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
209 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
210 SDOperand &Lo, SDOperand &Hi);
211 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
212 SDOperand &Lo, SDOperand &Hi);
214 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
215 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
217 SDOperand getIntPtrConstant(uint64_t Val) {
218 return DAG.getConstant(Val, TLI.getPointerTy());
223 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
224 /// specified mask and type. Targets can specify exactly which masks they
225 /// support and the code generator is tasked with not creating illegal masks.
227 /// Note that this will also return true for shuffles that are promoted to a
229 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
230 SDOperand Mask) const {
231 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
233 case TargetLowering::Legal:
234 case TargetLowering::Custom:
236 case TargetLowering::Promote: {
237 // If this is promoted to a different type, convert the shuffle mask and
238 // ask if it is legal in the promoted type!
239 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
241 // If we changed # elements, change the shuffle mask.
242 unsigned NumEltsGrowth =
243 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
244 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
245 if (NumEltsGrowth > 1) {
246 // Renumber the elements.
247 SmallVector<SDOperand, 8> Ops;
248 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
249 SDOperand InOp = Mask.getOperand(i);
250 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
251 if (InOp.getOpcode() == ISD::UNDEF)
252 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
254 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
255 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
259 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
265 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
268 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
269 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
270 ValueTypeActions(TLI.getValueTypeActions()) {
271 assert(MVT::LAST_VALUETYPE <= 32 &&
272 "Too many value types for ValueTypeActions to hold!");
275 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
276 /// contains all of a nodes operands before it contains the node.
277 static void ComputeTopDownOrdering(SelectionDAG &DAG,
278 SmallVector<SDNode*, 64> &Order) {
280 DenseMap<SDNode*, unsigned> Visited;
281 std::vector<SDNode*> Worklist;
282 Worklist.reserve(128);
284 // Compute ordering from all of the leaves in the graphs, those (like the
285 // entry node) that have no operands.
286 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
287 E = DAG.allnodes_end(); I != E; ++I) {
288 if (I->getNumOperands() == 0) {
290 Worklist.push_back(I);
294 while (!Worklist.empty()) {
295 SDNode *N = Worklist.back();
298 if (++Visited[N] != N->getNumOperands())
299 continue; // Haven't visited all operands yet
303 // Now that we have N in, add anything that uses it if all of their operands
305 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
307 Worklist.push_back(*UI);
310 assert(Order.size() == Visited.size() &&
312 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
313 "Error: DAG is cyclic!");
317 void SelectionDAGLegalize::LegalizeDAG() {
318 LastCALLSEQ_END = DAG.getEntryNode();
319 IsLegalizingCall = false;
321 // The legalize process is inherently a bottom-up recursive process (users
322 // legalize their uses before themselves). Given infinite stack space, we
323 // could just start legalizing on the root and traverse the whole graph. In
324 // practice however, this causes us to run out of stack space on large basic
325 // blocks. To avoid this problem, compute an ordering of the nodes where each
326 // node is only legalized after all of its operands are legalized.
327 SmallVector<SDNode*, 64> Order;
328 ComputeTopDownOrdering(DAG, Order);
330 for (unsigned i = 0, e = Order.size(); i != e; ++i)
331 HandleOp(SDOperand(Order[i], 0));
333 // Finally, it's possible the root changed. Get the new root.
334 SDOperand OldRoot = DAG.getRoot();
335 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
336 DAG.setRoot(LegalizedNodes[OldRoot]);
338 ExpandedNodes.clear();
339 LegalizedNodes.clear();
340 PromotedNodes.clear();
342 ScalarizedNodes.clear();
344 // Remove dead nodes now.
345 DAG.RemoveDeadNodes();
349 /// FindCallEndFromCallStart - Given a chained node that is part of a call
350 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
351 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
352 if (Node->getOpcode() == ISD::CALLSEQ_END)
354 if (Node->use_empty())
355 return 0; // No CallSeqEnd
357 // The chain is usually at the end.
358 SDOperand TheChain(Node, Node->getNumValues()-1);
359 if (TheChain.getValueType() != MVT::Other) {
360 // Sometimes it's at the beginning.
361 TheChain = SDOperand(Node, 0);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Otherwise, hunt for it.
364 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
365 if (Node->getValueType(i) == MVT::Other) {
366 TheChain = SDOperand(Node, i);
370 // Otherwise, we walked into a node without a chain.
371 if (TheChain.getValueType() != MVT::Other)
376 for (SDNode::use_iterator UI = Node->use_begin(),
377 E = Node->use_end(); UI != E; ++UI) {
379 // Make sure to only follow users of our token chain.
381 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
382 if (User->getOperand(i) == TheChain)
383 if (SDNode *Result = FindCallEndFromCallStart(User))
389 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
390 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
391 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
392 assert(Node && "Didn't find callseq_start for a call??");
393 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
395 assert(Node->getOperand(0).getValueType() == MVT::Other &&
396 "Node doesn't have a token chain argument!");
397 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
400 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
401 /// see if any uses can reach Dest. If no dest operands can get to dest,
402 /// legalize them, legalize ourself, and return false, otherwise, return true.
404 /// Keep track of the nodes we fine that actually do lead to Dest in
405 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
407 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
408 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
409 if (N == Dest) return true; // N certainly leads to Dest :)
411 // If we've already processed this node and it does lead to Dest, there is no
412 // need to reprocess it.
413 if (NodesLeadingTo.count(N)) return true;
415 // If the first result of this node has been already legalized, then it cannot
417 switch (getTypeAction(N->getValueType(0))) {
419 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
422 if (PromotedNodes.count(SDOperand(N, 0))) return false;
425 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
429 // Okay, this node has not already been legalized. Check and legalize all
430 // operands. If none lead to Dest, then we can legalize this node.
431 bool OperandsLeadToDest = false;
432 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
433 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
434 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
436 if (OperandsLeadToDest) {
437 NodesLeadingTo.insert(N);
441 // Okay, this node looks safe, legalize it and return false.
442 HandleOp(SDOperand(N, 0));
446 /// HandleOp - Legalize, Promote, or Expand the specified operand as
447 /// appropriate for its type.
448 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
449 MVT::ValueType VT = Op.getValueType();
450 switch (getTypeAction(VT)) {
451 default: assert(0 && "Bad type action!");
452 case Legal: (void)LegalizeOp(Op); break;
453 case Promote: (void)PromoteOp(Op); break;
455 if (!MVT::isVector(VT)) {
456 // If this is an illegal scalar, expand it into its two component
460 } else if (MVT::getVectorNumElements(VT) == 1) {
461 // If this is an illegal single element vector, convert it to a
463 (void)ScalarizeVectorOp(Op);
465 // Otherwise, this is an illegal multiple element vector.
466 // Split it in half and legalize both parts.
468 SplitVectorOp(Op, X, Y);
474 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
475 /// a load from the constant pool.
476 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
477 SelectionDAG &DAG, TargetLowering &TLI) {
480 // If a FP immediate is precise when represented as a float and if the
481 // target can do an extending load from float to double, we put it into
482 // the constant pool as a float, even if it's is statically typed as a
484 MVT::ValueType VT = CFP->getValueType(0);
485 bool isDouble = VT == MVT::f64;
486 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
487 Type::FloatTy, CFP->getValue());
489 double Val = LLVMC->getValue();
491 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
492 : DAG.getConstant(FloatToBits(Val), MVT::i32);
495 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
496 // Only do this if the target has a native EXTLOAD instruction from f32.
497 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
498 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
503 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
505 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
506 CPIdx, NULL, 0, MVT::f32);
508 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
513 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
516 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
517 SelectionDAG &DAG, TargetLowering &TLI) {
518 MVT::ValueType VT = Node->getValueType(0);
519 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
520 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
521 "fcopysign expansion only supported for f32 and f64");
522 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
524 // First get the sign bit of second operand.
525 SDOperand Mask1 = (SrcVT == MVT::f64)
526 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
527 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
528 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
529 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
530 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
531 // Shift right or sign-extend it if the two operands have different types.
532 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
534 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
535 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
536 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
537 } else if (SizeDiff < 0)
538 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
540 // Clear the sign bit of first operand.
541 SDOperand Mask2 = (VT == MVT::f64)
542 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
543 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
544 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
545 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
546 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
548 // Or the value with the sign bit.
549 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
554 /// LegalizeOp - We know that the specified value has a legal type, and
555 /// that its operands are legal. Now ensure that the operation itself
556 /// is legal, recursively ensuring that the operands' operations remain
558 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
559 assert(isTypeLegal(Op.getValueType()) &&
560 "Caller should expand or promote operands that are not legal!");
561 SDNode *Node = Op.Val;
563 // If this operation defines any values that cannot be represented in a
564 // register on this target, make sure to expand or promote them.
565 if (Node->getNumValues() > 1) {
566 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
567 if (getTypeAction(Node->getValueType(i)) != Legal) {
568 HandleOp(Op.getValue(i));
569 assert(LegalizedNodes.count(Op) &&
570 "Handling didn't add legal operands!");
571 return LegalizedNodes[Op];
575 // Note that LegalizeOp may be reentered even from single-use nodes, which
576 // means that we always must cache transformed nodes.
577 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
578 if (I != LegalizedNodes.end()) return I->second;
580 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
581 SDOperand Result = Op;
582 bool isCustom = false;
584 switch (Node->getOpcode()) {
585 case ISD::FrameIndex:
586 case ISD::EntryToken:
588 case ISD::BasicBlock:
589 case ISD::TargetFrameIndex:
590 case ISD::TargetJumpTable:
591 case ISD::TargetConstant:
592 case ISD::TargetConstantFP:
593 case ISD::TargetConstantPool:
594 case ISD::TargetGlobalAddress:
595 case ISD::TargetGlobalTLSAddress:
596 case ISD::TargetExternalSymbol:
601 // Primitives must all be legal.
602 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
603 "This must be legal!");
606 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
607 // If this is a target node, legalize it by legalizing the operands then
608 // passing it through.
609 SmallVector<SDOperand, 8> Ops;
610 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
611 Ops.push_back(LegalizeOp(Node->getOperand(i)));
613 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
615 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
616 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
617 return Result.getValue(Op.ResNo);
619 // Otherwise this is an unhandled builtin node. splat.
621 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
623 assert(0 && "Do not know how to legalize this operator!");
625 case ISD::GLOBAL_OFFSET_TABLE:
626 case ISD::GlobalAddress:
627 case ISD::GlobalTLSAddress:
628 case ISD::ExternalSymbol:
629 case ISD::ConstantPool:
630 case ISD::JumpTable: // Nothing to do.
631 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
632 default: assert(0 && "This action is not supported yet!");
633 case TargetLowering::Custom:
634 Tmp1 = TLI.LowerOperation(Op, DAG);
635 if (Tmp1.Val) Result = Tmp1;
636 // FALLTHROUGH if the target doesn't want to lower this op after all.
637 case TargetLowering::Legal:
642 case ISD::RETURNADDR:
643 // The only option for these nodes is to custom lower them. If the target
644 // does not custom lower them, then return zero.
645 Tmp1 = TLI.LowerOperation(Op, DAG);
649 Result = DAG.getConstant(0, TLI.getPointerTy());
651 case ISD::EXCEPTIONADDR: {
652 Tmp1 = LegalizeOp(Node->getOperand(0));
653 MVT::ValueType VT = Node->getValueType(0);
654 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
655 default: assert(0 && "This action is not supported yet!");
656 case TargetLowering::Expand: {
657 unsigned Reg = TLI.getExceptionAddressRegister();
658 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
661 case TargetLowering::Custom:
662 Result = TLI.LowerOperation(Op, DAG);
663 if (Result.Val) break;
665 case TargetLowering::Legal: {
666 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
667 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
668 Ops, 2).getValue(Op.ResNo);
674 case ISD::EHSELECTION: {
675 Tmp1 = LegalizeOp(Node->getOperand(0));
676 Tmp2 = LegalizeOp(Node->getOperand(1));
677 MVT::ValueType VT = Node->getValueType(0);
678 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
679 default: assert(0 && "This action is not supported yet!");
680 case TargetLowering::Expand: {
681 unsigned Reg = TLI.getExceptionSelectorRegister();
682 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
685 case TargetLowering::Custom:
686 Result = TLI.LowerOperation(Op, DAG);
687 if (Result.Val) break;
689 case TargetLowering::Legal: {
690 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
691 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
692 Ops, 2).getValue(Op.ResNo);
698 case ISD::AssertSext:
699 case ISD::AssertZext:
700 Tmp1 = LegalizeOp(Node->getOperand(0));
701 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
703 case ISD::MERGE_VALUES:
704 // Legalize eliminates MERGE_VALUES nodes.
705 Result = Node->getOperand(Op.ResNo);
707 case ISD::CopyFromReg:
708 Tmp1 = LegalizeOp(Node->getOperand(0));
709 Result = Op.getValue(0);
710 if (Node->getNumValues() == 2) {
711 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
713 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
714 if (Node->getNumOperands() == 3) {
715 Tmp2 = LegalizeOp(Node->getOperand(2));
716 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
718 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
720 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
722 // Since CopyFromReg produces two values, make sure to remember that we
723 // legalized both of them.
724 AddLegalizedOperand(Op.getValue(0), Result);
725 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
726 return Result.getValue(Op.ResNo);
728 MVT::ValueType VT = Op.getValueType();
729 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
730 default: assert(0 && "This action is not supported yet!");
731 case TargetLowering::Expand:
732 if (MVT::isInteger(VT))
733 Result = DAG.getConstant(0, VT);
734 else if (MVT::isFloatingPoint(VT))
735 Result = DAG.getConstantFP(0, VT);
737 assert(0 && "Unknown value type!");
739 case TargetLowering::Legal:
745 case ISD::INTRINSIC_W_CHAIN:
746 case ISD::INTRINSIC_WO_CHAIN:
747 case ISD::INTRINSIC_VOID: {
748 SmallVector<SDOperand, 8> Ops;
749 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
750 Ops.push_back(LegalizeOp(Node->getOperand(i)));
751 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
753 // Allow the target to custom lower its intrinsics if it wants to.
754 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
755 TargetLowering::Custom) {
756 Tmp3 = TLI.LowerOperation(Result, DAG);
757 if (Tmp3.Val) Result = Tmp3;
760 if (Result.Val->getNumValues() == 1) break;
762 // Must have return value and chain result.
763 assert(Result.Val->getNumValues() == 2 &&
764 "Cannot return more than two values!");
766 // Since loads produce two values, make sure to remember that we
767 // legalized both of them.
768 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
769 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
770 return Result.getValue(Op.ResNo);
774 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
777 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
778 case TargetLowering::Promote:
779 default: assert(0 && "This action is not supported yet!");
780 case TargetLowering::Expand: {
781 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
782 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
783 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
785 if (MMI && (useDEBUG_LOC || useLABEL)) {
786 const std::string &FName =
787 cast<StringSDNode>(Node->getOperand(3))->getValue();
788 const std::string &DirName =
789 cast<StringSDNode>(Node->getOperand(4))->getValue();
790 unsigned SrcFile = MMI->RecordSource(DirName, FName);
792 SmallVector<SDOperand, 8> Ops;
793 Ops.push_back(Tmp1); // chain
794 SDOperand LineOp = Node->getOperand(1);
795 SDOperand ColOp = Node->getOperand(2);
798 Ops.push_back(LineOp); // line #
799 Ops.push_back(ColOp); // col #
800 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
801 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
803 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
804 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
805 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
806 Ops.push_back(DAG.getConstant(ID, MVT::i32));
807 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
810 Result = Tmp1; // chain
814 case TargetLowering::Legal:
815 if (Tmp1 != Node->getOperand(0) ||
816 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
817 SmallVector<SDOperand, 8> Ops;
819 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
820 Ops.push_back(Node->getOperand(1)); // line # must be legal.
821 Ops.push_back(Node->getOperand(2)); // col # must be legal.
823 // Otherwise promote them.
824 Ops.push_back(PromoteOp(Node->getOperand(1)));
825 Ops.push_back(PromoteOp(Node->getOperand(2)));
827 Ops.push_back(Node->getOperand(3)); // filename must be legal.
828 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
829 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
836 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
837 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
838 default: assert(0 && "This action is not supported yet!");
839 case TargetLowering::Legal:
840 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
841 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
842 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
843 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
844 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
850 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
851 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
852 default: assert(0 && "This action is not supported yet!");
853 case TargetLowering::Legal:
854 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
855 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
856 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
858 case TargetLowering::Expand:
859 Result = LegalizeOp(Node->getOperand(0));
865 // We know we don't need to expand constants here, constants only have one
866 // value and we check that it is fine above.
868 // FIXME: Maybe we should handle things like targets that don't support full
869 // 32-bit immediates?
871 case ISD::ConstantFP: {
872 // Spill FP immediates to the constant pool if the target cannot directly
873 // codegen them. Targets often have some immediate values that can be
874 // efficiently generated into an FP register without a load. We explicitly
875 // leave these constants as ConstantFP nodes for the target to deal with.
876 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
878 // Check to see if this FP immediate is already legal.
879 bool isLegal = false;
880 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
881 E = TLI.legal_fpimm_end(); I != E; ++I)
882 if (CFP->isExactlyValue(*I)) {
887 // If this is a legal constant, turn it into a TargetConstantFP node.
889 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
893 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
894 default: assert(0 && "This action is not supported yet!");
895 case TargetLowering::Custom:
896 Tmp3 = TLI.LowerOperation(Result, DAG);
902 case TargetLowering::Expand:
903 Result = ExpandConstantFP(CFP, true, DAG, TLI);
907 case ISD::TokenFactor:
908 if (Node->getNumOperands() == 2) {
909 Tmp1 = LegalizeOp(Node->getOperand(0));
910 Tmp2 = LegalizeOp(Node->getOperand(1));
911 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
912 } else if (Node->getNumOperands() == 3) {
913 Tmp1 = LegalizeOp(Node->getOperand(0));
914 Tmp2 = LegalizeOp(Node->getOperand(1));
915 Tmp3 = LegalizeOp(Node->getOperand(2));
916 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
918 SmallVector<SDOperand, 8> Ops;
919 // Legalize the operands.
920 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
921 Ops.push_back(LegalizeOp(Node->getOperand(i)));
922 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
926 case ISD::FORMAL_ARGUMENTS:
928 // The only option for this is to custom lower it.
929 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
930 assert(Tmp3.Val && "Target didn't custom lower this node!");
931 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
932 "Lowering call/formal_arguments produced unexpected # results!");
934 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
935 // remember that we legalized all of them, so it doesn't get relegalized.
936 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
937 Tmp1 = LegalizeOp(Tmp3.getValue(i));
940 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
944 case ISD::BUILD_VECTOR:
945 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
946 default: assert(0 && "This action is not supported yet!");
947 case TargetLowering::Custom:
948 Tmp3 = TLI.LowerOperation(Result, DAG);
954 case TargetLowering::Expand:
955 Result = ExpandBUILD_VECTOR(Result.Val);
959 case ISD::INSERT_VECTOR_ELT:
960 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
961 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
962 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
963 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
965 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
966 Node->getValueType(0))) {
967 default: assert(0 && "This action is not supported yet!");
968 case TargetLowering::Legal:
970 case TargetLowering::Custom:
971 Tmp3 = TLI.LowerOperation(Result, DAG);
977 case TargetLowering::Expand: {
978 // If the insert index is a constant, codegen this as a scalar_to_vector,
979 // then a shuffle that inserts it into the right position in the vector.
980 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
981 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
982 Tmp1.getValueType(), Tmp2);
984 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
985 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
986 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
988 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
989 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
991 SmallVector<SDOperand, 8> ShufOps;
992 for (unsigned i = 0; i != NumElts; ++i) {
993 if (i != InsertPos->getValue())
994 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
996 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
998 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
999 &ShufOps[0], ShufOps.size());
1001 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1002 Tmp1, ScVec, ShufMask);
1003 Result = LegalizeOp(Result);
1007 // If the target doesn't support this, we have to spill the input vector
1008 // to a temporary stack slot, update the element, then reload it. This is
1009 // badness. We could also load the value into a vector register (either
1010 // with a "move to register" or "extload into register" instruction, then
1011 // permute it into place, if the idx is a constant and if the idx is
1012 // supported by the target.
1013 MVT::ValueType VT = Tmp1.getValueType();
1014 MVT::ValueType EltVT = Tmp2.getValueType();
1015 MVT::ValueType IdxVT = Tmp3.getValueType();
1016 MVT::ValueType PtrVT = TLI.getPointerTy();
1017 SDOperand StackPtr = CreateStackTemporary(VT);
1018 // Store the vector.
1019 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1021 // Truncate or zero extend offset to target pointer type.
1022 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1023 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1024 // Add the offset to the index.
1025 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1026 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1027 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1028 // Store the scalar value.
1029 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1030 // Load the updated vector.
1031 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1036 case ISD::SCALAR_TO_VECTOR:
1037 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1038 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1042 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1043 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1044 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1045 Node->getValueType(0))) {
1046 default: assert(0 && "This action is not supported yet!");
1047 case TargetLowering::Legal:
1049 case TargetLowering::Custom:
1050 Tmp3 = TLI.LowerOperation(Result, DAG);
1056 case TargetLowering::Expand:
1057 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1061 case ISD::VECTOR_SHUFFLE:
1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1063 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1064 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1066 // Allow targets to custom lower the SHUFFLEs they support.
1067 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1068 default: assert(0 && "Unknown operation action!");
1069 case TargetLowering::Legal:
1070 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1071 "vector shuffle should not be created if not legal!");
1073 case TargetLowering::Custom:
1074 Tmp3 = TLI.LowerOperation(Result, DAG);
1080 case TargetLowering::Expand: {
1081 MVT::ValueType VT = Node->getValueType(0);
1082 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1083 MVT::ValueType PtrVT = TLI.getPointerTy();
1084 SDOperand Mask = Node->getOperand(2);
1085 unsigned NumElems = Mask.getNumOperands();
1086 SmallVector<SDOperand,8> Ops;
1087 for (unsigned i = 0; i != NumElems; ++i) {
1088 SDOperand Arg = Mask.getOperand(i);
1089 if (Arg.getOpcode() == ISD::UNDEF) {
1090 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1092 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1093 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1095 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1096 DAG.getConstant(Idx, PtrVT)));
1098 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1099 DAG.getConstant(Idx - NumElems, PtrVT)));
1102 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1105 case TargetLowering::Promote: {
1106 // Change base type to a different vector type.
1107 MVT::ValueType OVT = Node->getValueType(0);
1108 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1110 // Cast the two input vectors.
1111 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1112 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1114 // Convert the shuffle mask to the right # elements.
1115 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1116 assert(Tmp3.Val && "Shuffle not legal?");
1117 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1118 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1124 case ISD::EXTRACT_VECTOR_ELT:
1125 Tmp1 = Node->getOperand(0);
1126 Tmp2 = LegalizeOp(Node->getOperand(1));
1127 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1128 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1131 case ISD::EXTRACT_SUBVECTOR:
1132 Tmp1 = Node->getOperand(0);
1133 Tmp2 = LegalizeOp(Node->getOperand(1));
1134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1135 Result = ExpandEXTRACT_SUBVECTOR(Result);
1138 case ISD::CALLSEQ_START: {
1139 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1141 // Recursively Legalize all of the inputs of the call end that do not lead
1142 // to this call start. This ensures that any libcalls that need be inserted
1143 // are inserted *before* the CALLSEQ_START.
1144 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1145 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1146 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1150 // Now that we legalized all of the inputs (which may have inserted
1151 // libcalls) create the new CALLSEQ_START node.
1152 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1154 // Merge in the last call, to ensure that this call start after the last
1156 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1157 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1158 Tmp1 = LegalizeOp(Tmp1);
1161 // Do not try to legalize the target-specific arguments (#1+).
1162 if (Tmp1 != Node->getOperand(0)) {
1163 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1165 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1168 // Remember that the CALLSEQ_START is legalized.
1169 AddLegalizedOperand(Op.getValue(0), Result);
1170 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1171 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1173 // Now that the callseq_start and all of the non-call nodes above this call
1174 // sequence have been legalized, legalize the call itself. During this
1175 // process, no libcalls can/will be inserted, guaranteeing that no calls
1177 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1178 SDOperand InCallSEQ = LastCALLSEQ_END;
1179 // Note that we are selecting this call!
1180 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1181 IsLegalizingCall = true;
1183 // Legalize the call, starting from the CALLSEQ_END.
1184 LegalizeOp(LastCALLSEQ_END);
1185 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1188 case ISD::CALLSEQ_END:
1189 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1190 // will cause this node to be legalized as well as handling libcalls right.
1191 if (LastCALLSEQ_END.Val != Node) {
1192 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1193 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1194 assert(I != LegalizedNodes.end() &&
1195 "Legalizing the call start should have legalized this node!");
1199 // Otherwise, the call start has been legalized and everything is going
1200 // according to plan. Just legalize ourselves normally here.
1201 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1202 // Do not try to legalize the target-specific arguments (#1+), except for
1203 // an optional flag input.
1204 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1205 if (Tmp1 != Node->getOperand(0)) {
1206 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1208 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1211 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1212 if (Tmp1 != Node->getOperand(0) ||
1213 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1214 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1217 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1220 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1221 // This finishes up call legalization.
1222 IsLegalizingCall = false;
1224 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1225 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1226 if (Node->getNumValues() == 2)
1227 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1228 return Result.getValue(Op.ResNo);
1229 case ISD::DYNAMIC_STACKALLOC: {
1230 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1231 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1232 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1233 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1235 Tmp1 = Result.getValue(0);
1236 Tmp2 = Result.getValue(1);
1237 switch (TLI.getOperationAction(Node->getOpcode(),
1238 Node->getValueType(0))) {
1239 default: assert(0 && "This action is not supported yet!");
1240 case TargetLowering::Expand: {
1241 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1242 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1243 " not tell us which reg is the stack pointer!");
1244 SDOperand Chain = Tmp1.getOperand(0);
1245 SDOperand Size = Tmp2.getOperand(1);
1246 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1247 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1248 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1249 Tmp1 = LegalizeOp(Tmp1);
1250 Tmp2 = LegalizeOp(Tmp2);
1253 case TargetLowering::Custom:
1254 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1256 Tmp1 = LegalizeOp(Tmp3);
1257 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1260 case TargetLowering::Legal:
1263 // Since this op produce two values, make sure to remember that we
1264 // legalized both of them.
1265 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1266 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1267 return Op.ResNo ? Tmp2 : Tmp1;
1269 case ISD::INLINEASM: {
1270 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1271 bool Changed = false;
1272 // Legalize all of the operands of the inline asm, in case they are nodes
1273 // that need to be expanded or something. Note we skip the asm string and
1274 // all of the TargetConstant flags.
1275 SDOperand Op = LegalizeOp(Ops[0]);
1276 Changed = Op != Ops[0];
1279 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1280 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1281 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1282 for (++i; NumVals; ++i, --NumVals) {
1283 SDOperand Op = LegalizeOp(Ops[i]);
1292 Op = LegalizeOp(Ops.back());
1293 Changed |= Op != Ops.back();
1298 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1300 // INLINE asm returns a chain and flag, make sure to add both to the map.
1301 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1302 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1303 return Result.getValue(Op.ResNo);
1306 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1307 // Ensure that libcalls are emitted before a branch.
1308 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1309 Tmp1 = LegalizeOp(Tmp1);
1310 LastCALLSEQ_END = DAG.getEntryNode();
1312 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1315 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1316 // Ensure that libcalls are emitted before a branch.
1317 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1318 Tmp1 = LegalizeOp(Tmp1);
1319 LastCALLSEQ_END = DAG.getEntryNode();
1321 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1322 default: assert(0 && "Indirect target must be legal type (pointer)!");
1324 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1327 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1330 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1331 // Ensure that libcalls are emitted before a branch.
1332 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1333 Tmp1 = LegalizeOp(Tmp1);
1334 LastCALLSEQ_END = DAG.getEntryNode();
1336 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1339 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1340 default: assert(0 && "This action is not supported yet!");
1341 case TargetLowering::Legal: break;
1342 case TargetLowering::Custom:
1343 Tmp1 = TLI.LowerOperation(Result, DAG);
1344 if (Tmp1.Val) Result = Tmp1;
1346 case TargetLowering::Expand: {
1347 SDOperand Chain = Result.getOperand(0);
1348 SDOperand Table = Result.getOperand(1);
1349 SDOperand Index = Result.getOperand(2);
1351 MVT::ValueType PTy = TLI.getPointerTy();
1352 MachineFunction &MF = DAG.getMachineFunction();
1353 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1354 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1355 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1358 switch (EntrySize) {
1359 default: assert(0 && "Size of jump table not supported yet."); break;
1360 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1361 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1364 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1365 // For PIC, the sequence is:
1366 // BRIND(load(Jumptable + index) + RelocBase)
1367 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1369 if (TLI.usesGlobalOffsetTable())
1370 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1373 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1374 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1375 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1377 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1384 // Ensure that libcalls are emitted before a return.
1385 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1386 Tmp1 = LegalizeOp(Tmp1);
1387 LastCALLSEQ_END = DAG.getEntryNode();
1389 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1390 case Expand: assert(0 && "It's impossible to expand bools");
1392 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1395 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1397 // The top bits of the promoted condition are not necessarily zero, ensure
1398 // that the value is properly zero extended.
1399 if (!DAG.MaskedValueIsZero(Tmp2,
1400 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1401 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1405 // Basic block destination (Op#2) is always legal.
1406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1408 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1409 default: assert(0 && "This action is not supported yet!");
1410 case TargetLowering::Legal: break;
1411 case TargetLowering::Custom:
1412 Tmp1 = TLI.LowerOperation(Result, DAG);
1413 if (Tmp1.Val) Result = Tmp1;
1415 case TargetLowering::Expand:
1416 // Expand brcond's setcc into its constituent parts and create a BR_CC
1418 if (Tmp2.getOpcode() == ISD::SETCC) {
1419 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1420 Tmp2.getOperand(0), Tmp2.getOperand(1),
1421 Node->getOperand(2));
1423 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1424 DAG.getCondCode(ISD::SETNE), Tmp2,
1425 DAG.getConstant(0, Tmp2.getValueType()),
1426 Node->getOperand(2));
1432 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1433 // Ensure that libcalls are emitted before a branch.
1434 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1435 Tmp1 = LegalizeOp(Tmp1);
1436 Tmp2 = Node->getOperand(2); // LHS
1437 Tmp3 = Node->getOperand(3); // RHS
1438 Tmp4 = Node->getOperand(1); // CC
1440 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1441 LastCALLSEQ_END = DAG.getEntryNode();
1443 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1444 // the LHS is a legal SETCC itself. In this case, we need to compare
1445 // the result against zero to select between true and false values.
1446 if (Tmp3.Val == 0) {
1447 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1448 Tmp4 = DAG.getCondCode(ISD::SETNE);
1451 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1452 Node->getOperand(4));
1454 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1455 default: assert(0 && "Unexpected action for BR_CC!");
1456 case TargetLowering::Legal: break;
1457 case TargetLowering::Custom:
1458 Tmp4 = TLI.LowerOperation(Result, DAG);
1459 if (Tmp4.Val) Result = Tmp4;
1464 LoadSDNode *LD = cast<LoadSDNode>(Node);
1465 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1466 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1468 ISD::LoadExtType ExtType = LD->getExtensionType();
1469 if (ExtType == ISD::NON_EXTLOAD) {
1470 MVT::ValueType VT = Node->getValueType(0);
1471 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1472 Tmp3 = Result.getValue(0);
1473 Tmp4 = Result.getValue(1);
1475 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1476 default: assert(0 && "This action is not supported yet!");
1477 case TargetLowering::Legal: break;
1478 case TargetLowering::Custom:
1479 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1481 Tmp3 = LegalizeOp(Tmp1);
1482 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1485 case TargetLowering::Promote: {
1486 // Only promote a load of vector type to another.
1487 assert(MVT::isVector(VT) && "Cannot promote this load!");
1488 // Change base type to a different vector type.
1489 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1491 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1492 LD->getSrcValueOffset(),
1493 LD->isVolatile(), LD->getAlignment());
1494 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1495 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1499 // Since loads produce two values, make sure to remember that we
1500 // legalized both of them.
1501 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1502 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1503 return Op.ResNo ? Tmp4 : Tmp3;
1505 MVT::ValueType SrcVT = LD->getLoadedVT();
1506 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1507 default: assert(0 && "This action is not supported yet!");
1508 case TargetLowering::Promote:
1509 assert(SrcVT == MVT::i1 &&
1510 "Can only promote extending LOAD from i1 -> i8!");
1511 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1512 LD->getSrcValue(), LD->getSrcValueOffset(),
1513 MVT::i8, LD->isVolatile(), LD->getAlignment());
1514 Tmp1 = Result.getValue(0);
1515 Tmp2 = Result.getValue(1);
1517 case TargetLowering::Custom:
1520 case TargetLowering::Legal:
1521 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1522 Tmp1 = Result.getValue(0);
1523 Tmp2 = Result.getValue(1);
1526 Tmp3 = TLI.LowerOperation(Result, DAG);
1528 Tmp1 = LegalizeOp(Tmp3);
1529 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1533 case TargetLowering::Expand:
1534 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1535 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1536 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1537 LD->getSrcValueOffset(),
1538 LD->isVolatile(), LD->getAlignment());
1539 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1540 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1541 Tmp2 = LegalizeOp(Load.getValue(1));
1544 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1545 // Turn the unsupported load into an EXTLOAD followed by an explicit
1546 // zero/sign extend inreg.
1547 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1548 Tmp1, Tmp2, LD->getSrcValue(),
1549 LD->getSrcValueOffset(), SrcVT,
1550 LD->isVolatile(), LD->getAlignment());
1552 if (ExtType == ISD::SEXTLOAD)
1553 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1554 Result, DAG.getValueType(SrcVT));
1556 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1557 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1558 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1561 // Since loads produce two values, make sure to remember that we legalized
1563 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1564 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1565 return Op.ResNo ? Tmp2 : Tmp1;
1568 case ISD::EXTRACT_ELEMENT: {
1569 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1570 switch (getTypeAction(OpTy)) {
1571 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1573 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1575 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1576 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1577 TLI.getShiftAmountTy()));
1578 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1581 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1582 Node->getOperand(0));
1586 // Get both the low and high parts.
1587 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1588 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1589 Result = Tmp2; // 1 -> Hi
1591 Result = Tmp1; // 0 -> Lo
1597 case ISD::CopyToReg:
1598 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1600 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1601 "Register type must be legal!");
1602 // Legalize the incoming value (must be a legal type).
1603 Tmp2 = LegalizeOp(Node->getOperand(2));
1604 if (Node->getNumValues() == 1) {
1605 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1607 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1608 if (Node->getNumOperands() == 4) {
1609 Tmp3 = LegalizeOp(Node->getOperand(3));
1610 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1613 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1616 // Since this produces two values, make sure to remember that we legalized
1618 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1619 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1625 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1627 // Ensure that libcalls are emitted before a return.
1628 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1629 Tmp1 = LegalizeOp(Tmp1);
1630 LastCALLSEQ_END = DAG.getEntryNode();
1632 switch (Node->getNumOperands()) {
1634 Tmp2 = Node->getOperand(1);
1635 Tmp3 = Node->getOperand(2); // Signness
1636 switch (getTypeAction(Tmp2.getValueType())) {
1638 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1641 if (!MVT::isVector(Tmp2.getValueType())) {
1643 ExpandOp(Tmp2, Lo, Hi);
1645 // Big endian systems want the hi reg first.
1646 if (!TLI.isLittleEndian())
1650 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1652 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1653 Result = LegalizeOp(Result);
1655 SDNode *InVal = Tmp2.Val;
1656 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1657 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1659 // Figure out if there is a simple type corresponding to this Vector
1660 // type. If so, convert to the vector type.
1661 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1662 if (TLI.isTypeLegal(TVT)) {
1663 // Turn this into a return of the vector type.
1664 Tmp2 = LegalizeOp(Tmp2);
1665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1666 } else if (NumElems == 1) {
1667 // Turn this into a return of the scalar type.
1668 Tmp2 = ScalarizeVectorOp(Tmp2);
1669 Tmp2 = LegalizeOp(Tmp2);
1670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1672 // FIXME: Returns of gcc generic vectors smaller than a legal type
1673 // should be returned in integer registers!
1675 // The scalarized value type may not be legal, e.g. it might require
1676 // promotion or expansion. Relegalize the return.
1677 Result = LegalizeOp(Result);
1679 // FIXME: Returns of gcc generic vectors larger than a legal vector
1680 // type should be returned by reference!
1682 SplitVectorOp(Tmp2, Lo, Hi);
1683 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1684 Result = LegalizeOp(Result);
1689 Tmp2 = PromoteOp(Node->getOperand(1));
1690 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1691 Result = LegalizeOp(Result);
1696 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1698 default: { // ret <values>
1699 SmallVector<SDOperand, 8> NewValues;
1700 NewValues.push_back(Tmp1);
1701 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1702 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1704 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1705 NewValues.push_back(Node->getOperand(i+1));
1709 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1710 "FIXME: TODO: implement returning non-legal vector types!");
1711 ExpandOp(Node->getOperand(i), Lo, Hi);
1712 NewValues.push_back(Lo);
1713 NewValues.push_back(Node->getOperand(i+1));
1715 NewValues.push_back(Hi);
1716 NewValues.push_back(Node->getOperand(i+1));
1721 assert(0 && "Can't promote multiple return value yet!");
1724 if (NewValues.size() == Node->getNumOperands())
1725 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1727 Result = DAG.getNode(ISD::RET, MVT::Other,
1728 &NewValues[0], NewValues.size());
1733 if (Result.getOpcode() == ISD::RET) {
1734 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1735 default: assert(0 && "This action is not supported yet!");
1736 case TargetLowering::Legal: break;
1737 case TargetLowering::Custom:
1738 Tmp1 = TLI.LowerOperation(Result, DAG);
1739 if (Tmp1.Val) Result = Tmp1;
1745 StoreSDNode *ST = cast<StoreSDNode>(Node);
1746 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1747 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1748 int SVOffset = ST->getSrcValueOffset();
1749 unsigned Alignment = ST->getAlignment();
1750 bool isVolatile = ST->isVolatile();
1752 if (!ST->isTruncatingStore()) {
1753 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1754 // FIXME: We shouldn't do this for TargetConstantFP's.
1755 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1756 // to phase ordering between legalized code and the dag combiner. This
1757 // probably means that we need to integrate dag combiner and legalizer
1759 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1760 if (CFP->getValueType(0) == MVT::f32) {
1761 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1763 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1764 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1766 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1767 SVOffset, isVolatile, Alignment);
1771 switch (getTypeAction(ST->getStoredVT())) {
1773 Tmp3 = LegalizeOp(ST->getValue());
1774 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1777 MVT::ValueType VT = Tmp3.getValueType();
1778 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1779 default: assert(0 && "This action is not supported yet!");
1780 case TargetLowering::Legal: break;
1781 case TargetLowering::Custom:
1782 Tmp1 = TLI.LowerOperation(Result, DAG);
1783 if (Tmp1.Val) Result = Tmp1;
1785 case TargetLowering::Promote:
1786 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1787 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1788 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1789 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1790 ST->getSrcValue(), SVOffset, isVolatile,
1797 // Truncate the value and store the result.
1798 Tmp3 = PromoteOp(ST->getValue());
1799 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1800 SVOffset, ST->getStoredVT(),
1801 isVolatile, Alignment);
1805 unsigned IncrementSize = 0;
1808 // If this is a vector type, then we have to calculate the increment as
1809 // the product of the element size in bytes, and the number of elements
1810 // in the high half of the vector.
1811 if (MVT::isVector(ST->getValue().getValueType())) {
1812 SDNode *InVal = ST->getValue().Val;
1813 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1814 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1816 // Figure out if there is a simple type corresponding to this Vector
1817 // type. If so, convert to the vector type.
1818 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1819 if (TLI.isTypeLegal(TVT)) {
1820 // Turn this into a normal store of the vector type.
1821 Tmp3 = LegalizeOp(Node->getOperand(1));
1822 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1823 SVOffset, isVolatile, Alignment);
1824 Result = LegalizeOp(Result);
1826 } else if (NumElems == 1) {
1827 // Turn this into a normal store of the scalar type.
1828 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
1829 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1830 SVOffset, isVolatile, Alignment);
1831 // The scalarized value type may not be legal, e.g. it might require
1832 // promotion or expansion. Relegalize the scalar store.
1833 Result = LegalizeOp(Result);
1836 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1837 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1840 ExpandOp(Node->getOperand(1), Lo, Hi);
1841 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1843 if (!TLI.isLittleEndian())
1847 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1848 SVOffset, isVolatile, Alignment);
1850 if (Hi.Val == NULL) {
1851 // Must be int <-> float one-to-one expansion.
1856 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1857 getIntPtrConstant(IncrementSize));
1858 assert(isTypeLegal(Tmp2.getValueType()) &&
1859 "Pointers must be legal!");
1860 SVOffset += IncrementSize;
1861 if (Alignment > IncrementSize)
1862 Alignment = IncrementSize;
1863 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1864 SVOffset, isVolatile, Alignment);
1865 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1870 assert(isTypeLegal(ST->getValue().getValueType()) &&
1871 "Cannot handle illegal TRUNCSTORE yet!");
1872 Tmp3 = LegalizeOp(ST->getValue());
1874 // The only promote case we handle is TRUNCSTORE:i1 X into
1875 // -> TRUNCSTORE:i8 (and X, 1)
1876 if (ST->getStoredVT() == MVT::i1 &&
1877 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1878 // Promote the bool to a mask then store.
1879 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1880 DAG.getConstant(1, Tmp3.getValueType()));
1881 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1883 isVolatile, Alignment);
1884 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1885 Tmp2 != ST->getBasePtr()) {
1886 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1890 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1891 switch (TLI.getStoreXAction(StVT)) {
1892 default: assert(0 && "This action is not supported yet!");
1893 case TargetLowering::Legal: break;
1894 case TargetLowering::Custom:
1895 Tmp1 = TLI.LowerOperation(Result, DAG);
1896 if (Tmp1.Val) Result = Tmp1;
1903 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1904 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1906 case ISD::STACKSAVE:
1907 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1908 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1909 Tmp1 = Result.getValue(0);
1910 Tmp2 = Result.getValue(1);
1912 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1913 default: assert(0 && "This action is not supported yet!");
1914 case TargetLowering::Legal: break;
1915 case TargetLowering::Custom:
1916 Tmp3 = TLI.LowerOperation(Result, DAG);
1918 Tmp1 = LegalizeOp(Tmp3);
1919 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1922 case TargetLowering::Expand:
1923 // Expand to CopyFromReg if the target set
1924 // StackPointerRegisterToSaveRestore.
1925 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1926 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1927 Node->getValueType(0));
1928 Tmp2 = Tmp1.getValue(1);
1930 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1931 Tmp2 = Node->getOperand(0);
1936 // Since stacksave produce two values, make sure to remember that we
1937 // legalized both of them.
1938 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1939 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1940 return Op.ResNo ? Tmp2 : Tmp1;
1942 case ISD::STACKRESTORE:
1943 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1944 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1947 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1948 default: assert(0 && "This action is not supported yet!");
1949 case TargetLowering::Legal: break;
1950 case TargetLowering::Custom:
1951 Tmp1 = TLI.LowerOperation(Result, DAG);
1952 if (Tmp1.Val) Result = Tmp1;
1954 case TargetLowering::Expand:
1955 // Expand to CopyToReg if the target set
1956 // StackPointerRegisterToSaveRestore.
1957 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1958 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1966 case ISD::READCYCLECOUNTER:
1967 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1968 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1969 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1970 Node->getValueType(0))) {
1971 default: assert(0 && "This action is not supported yet!");
1972 case TargetLowering::Legal:
1973 Tmp1 = Result.getValue(0);
1974 Tmp2 = Result.getValue(1);
1976 case TargetLowering::Custom:
1977 Result = TLI.LowerOperation(Result, DAG);
1978 Tmp1 = LegalizeOp(Result.getValue(0));
1979 Tmp2 = LegalizeOp(Result.getValue(1));
1983 // Since rdcc produce two values, make sure to remember that we legalized
1985 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1986 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1990 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1991 case Expand: assert(0 && "It's impossible to expand bools");
1993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1996 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1997 // Make sure the condition is either zero or one.
1998 if (!DAG.MaskedValueIsZero(Tmp1,
1999 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2000 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2003 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2004 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2008 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2009 default: assert(0 && "This action is not supported yet!");
2010 case TargetLowering::Legal: break;
2011 case TargetLowering::Custom: {
2012 Tmp1 = TLI.LowerOperation(Result, DAG);
2013 if (Tmp1.Val) Result = Tmp1;
2016 case TargetLowering::Expand:
2017 if (Tmp1.getOpcode() == ISD::SETCC) {
2018 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2020 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2022 Result = DAG.getSelectCC(Tmp1,
2023 DAG.getConstant(0, Tmp1.getValueType()),
2024 Tmp2, Tmp3, ISD::SETNE);
2027 case TargetLowering::Promote: {
2028 MVT::ValueType NVT =
2029 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2030 unsigned ExtOp, TruncOp;
2031 if (MVT::isVector(Tmp2.getValueType())) {
2032 ExtOp = ISD::BIT_CONVERT;
2033 TruncOp = ISD::BIT_CONVERT;
2034 } else if (MVT::isInteger(Tmp2.getValueType())) {
2035 ExtOp = ISD::ANY_EXTEND;
2036 TruncOp = ISD::TRUNCATE;
2038 ExtOp = ISD::FP_EXTEND;
2039 TruncOp = ISD::FP_ROUND;
2041 // Promote each of the values to the new type.
2042 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2043 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2044 // Perform the larger operation, then round down.
2045 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2046 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2051 case ISD::SELECT_CC: {
2052 Tmp1 = Node->getOperand(0); // LHS
2053 Tmp2 = Node->getOperand(1); // RHS
2054 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2055 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2056 SDOperand CC = Node->getOperand(4);
2058 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2060 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2061 // the LHS is a legal SETCC itself. In this case, we need to compare
2062 // the result against zero to select between true and false values.
2063 if (Tmp2.Val == 0) {
2064 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2065 CC = DAG.getCondCode(ISD::SETNE);
2067 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2069 // Everything is legal, see if we should expand this op or something.
2070 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2071 default: assert(0 && "This action is not supported yet!");
2072 case TargetLowering::Legal: break;
2073 case TargetLowering::Custom:
2074 Tmp1 = TLI.LowerOperation(Result, DAG);
2075 if (Tmp1.Val) Result = Tmp1;
2081 Tmp1 = Node->getOperand(0);
2082 Tmp2 = Node->getOperand(1);
2083 Tmp3 = Node->getOperand(2);
2084 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2086 // If we had to Expand the SetCC operands into a SELECT node, then it may
2087 // not always be possible to return a true LHS & RHS. In this case, just
2088 // return the value we legalized, returned in the LHS
2089 if (Tmp2.Val == 0) {
2094 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2095 default: assert(0 && "Cannot handle this action for SETCC yet!");
2096 case TargetLowering::Custom:
2099 case TargetLowering::Legal:
2100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2102 Tmp4 = TLI.LowerOperation(Result, DAG);
2103 if (Tmp4.Val) Result = Tmp4;
2106 case TargetLowering::Promote: {
2107 // First step, figure out the appropriate operation to use.
2108 // Allow SETCC to not be supported for all legal data types
2109 // Mostly this targets FP
2110 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2111 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2113 // Scan for the appropriate larger type to use.
2115 NewInTy = (MVT::ValueType)(NewInTy+1);
2117 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2118 "Fell off of the edge of the integer world");
2119 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2120 "Fell off of the edge of the floating point world");
2122 // If the target supports SETCC of this type, use it.
2123 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2126 if (MVT::isInteger(NewInTy))
2127 assert(0 && "Cannot promote Legal Integer SETCC yet");
2129 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2130 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2132 Tmp1 = LegalizeOp(Tmp1);
2133 Tmp2 = LegalizeOp(Tmp2);
2134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2135 Result = LegalizeOp(Result);
2138 case TargetLowering::Expand:
2139 // Expand a setcc node into a select_cc of the same condition, lhs, and
2140 // rhs that selects between const 1 (true) and const 0 (false).
2141 MVT::ValueType VT = Node->getValueType(0);
2142 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2143 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2150 case ISD::MEMMOVE: {
2151 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2152 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2154 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2155 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2156 case Expand: assert(0 && "Cannot expand a byte!");
2158 Tmp3 = LegalizeOp(Node->getOperand(2));
2161 Tmp3 = PromoteOp(Node->getOperand(2));
2165 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2169 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2171 // Length is too big, just take the lo-part of the length.
2173 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2177 Tmp4 = LegalizeOp(Node->getOperand(3));
2180 Tmp4 = PromoteOp(Node->getOperand(3));
2185 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2186 case Expand: assert(0 && "Cannot expand this yet!");
2188 Tmp5 = LegalizeOp(Node->getOperand(4));
2191 Tmp5 = PromoteOp(Node->getOperand(4));
2195 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2196 default: assert(0 && "This action not implemented for this operation!");
2197 case TargetLowering::Custom:
2200 case TargetLowering::Legal:
2201 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2203 Tmp1 = TLI.LowerOperation(Result, DAG);
2204 if (Tmp1.Val) Result = Tmp1;
2207 case TargetLowering::Expand: {
2208 // Otherwise, the target does not support this operation. Lower the
2209 // operation to an explicit libcall as appropriate.
2210 MVT::ValueType IntPtr = TLI.getPointerTy();
2211 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2212 TargetLowering::ArgListTy Args;
2213 TargetLowering::ArgListEntry Entry;
2215 const char *FnName = 0;
2216 if (Node->getOpcode() == ISD::MEMSET) {
2217 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2218 Args.push_back(Entry);
2219 // Extend the (previously legalized) ubyte argument to be an int value
2221 if (Tmp3.getValueType() > MVT::i32)
2222 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2224 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2225 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2226 Args.push_back(Entry);
2227 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2228 Args.push_back(Entry);
2231 } else if (Node->getOpcode() == ISD::MEMCPY ||
2232 Node->getOpcode() == ISD::MEMMOVE) {
2233 Entry.Ty = IntPtrTy;
2234 Entry.Node = Tmp2; Args.push_back(Entry);
2235 Entry.Node = Tmp3; Args.push_back(Entry);
2236 Entry.Node = Tmp4; Args.push_back(Entry);
2237 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2239 assert(0 && "Unknown op!");
2242 std::pair<SDOperand,SDOperand> CallResult =
2243 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2244 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2245 Result = CallResult.second;
2252 case ISD::SHL_PARTS:
2253 case ISD::SRA_PARTS:
2254 case ISD::SRL_PARTS: {
2255 SmallVector<SDOperand, 8> Ops;
2256 bool Changed = false;
2257 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2258 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2259 Changed |= Ops.back() != Node->getOperand(i);
2262 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2264 switch (TLI.getOperationAction(Node->getOpcode(),
2265 Node->getValueType(0))) {
2266 default: assert(0 && "This action is not supported yet!");
2267 case TargetLowering::Legal: break;
2268 case TargetLowering::Custom:
2269 Tmp1 = TLI.LowerOperation(Result, DAG);
2271 SDOperand Tmp2, RetVal(0, 0);
2272 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2273 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2274 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2278 assert(RetVal.Val && "Illegal result number");
2284 // Since these produce multiple values, make sure to remember that we
2285 // legalized all of them.
2286 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2287 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2288 return Result.getValue(Op.ResNo);
2309 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2310 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2311 case Expand: assert(0 && "Not possible");
2313 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2316 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2322 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2323 default: assert(0 && "BinOp legalize operation not supported");
2324 case TargetLowering::Legal: break;
2325 case TargetLowering::Custom:
2326 Tmp1 = TLI.LowerOperation(Result, DAG);
2327 if (Tmp1.Val) Result = Tmp1;
2329 case TargetLowering::Expand: {
2330 if (Node->getValueType(0) == MVT::i32) {
2331 switch (Node->getOpcode()) {
2332 default: assert(0 && "Do not know how to expand this integer BinOp!");
2335 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2336 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2338 bool isSigned = Node->getOpcode() == ISD::SDIV;
2339 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2344 assert(MVT::isVector(Node->getValueType(0)) &&
2345 "Cannot expand this binary operator!");
2346 // Expand the operation into a bunch of nasty scalar code.
2347 SmallVector<SDOperand, 8> Ops;
2348 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2349 MVT::ValueType PtrVT = TLI.getPointerTy();
2350 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2352 SDOperand Idx = DAG.getConstant(i, PtrVT);
2353 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2354 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2355 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2357 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2358 &Ops[0], Ops.size());
2361 case TargetLowering::Promote: {
2362 switch (Node->getOpcode()) {
2363 default: assert(0 && "Do not know how to promote this BinOp!");
2367 MVT::ValueType OVT = Node->getValueType(0);
2368 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2369 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2370 // Bit convert each of the values to the new type.
2371 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2372 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2373 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2374 // Bit convert the result back the original type.
2375 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2383 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2384 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2385 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2386 case Expand: assert(0 && "Not possible");
2388 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2391 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2395 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2397 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2398 default: assert(0 && "Operation not supported");
2399 case TargetLowering::Custom:
2400 Tmp1 = TLI.LowerOperation(Result, DAG);
2401 if (Tmp1.Val) Result = Tmp1;
2403 case TargetLowering::Legal: break;
2404 case TargetLowering::Expand: {
2405 // If this target supports fabs/fneg natively and select is cheap,
2406 // do this efficiently.
2407 if (!TLI.isSelectExpensive() &&
2408 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2409 TargetLowering::Legal &&
2410 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2411 TargetLowering::Legal) {
2412 // Get the sign bit of the RHS.
2413 MVT::ValueType IVT =
2414 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2415 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2416 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2417 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2418 // Get the absolute value of the result.
2419 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2420 // Select between the nabs and abs value based on the sign bit of
2422 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2423 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2426 Result = LegalizeOp(Result);
2430 // Otherwise, do bitwise ops!
2431 MVT::ValueType NVT =
2432 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2433 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2434 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2435 Result = LegalizeOp(Result);
2443 Tmp1 = LegalizeOp(Node->getOperand(0));
2444 Tmp2 = LegalizeOp(Node->getOperand(1));
2445 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2446 // Since this produces two values, make sure to remember that we legalized
2448 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2449 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2454 Tmp1 = LegalizeOp(Node->getOperand(0));
2455 Tmp2 = LegalizeOp(Node->getOperand(1));
2456 Tmp3 = LegalizeOp(Node->getOperand(2));
2457 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2458 // Since this produces two values, make sure to remember that we legalized
2460 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2461 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2464 case ISD::BUILD_PAIR: {
2465 MVT::ValueType PairTy = Node->getValueType(0);
2466 // TODO: handle the case where the Lo and Hi operands are not of legal type
2467 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2468 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2469 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2470 case TargetLowering::Promote:
2471 case TargetLowering::Custom:
2472 assert(0 && "Cannot promote/custom this yet!");
2473 case TargetLowering::Legal:
2474 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2475 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2477 case TargetLowering::Expand:
2478 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2479 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2480 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2481 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2482 TLI.getShiftAmountTy()));
2483 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2492 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2493 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2495 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2496 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2497 case TargetLowering::Custom:
2500 case TargetLowering::Legal:
2501 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2503 Tmp1 = TLI.LowerOperation(Result, DAG);
2504 if (Tmp1.Val) Result = Tmp1;
2507 case TargetLowering::Expand:
2508 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2509 bool isSigned = DivOpc == ISD::SDIV;
2510 if (MVT::isInteger(Node->getValueType(0))) {
2511 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2512 TargetLowering::Legal) {
2514 MVT::ValueType VT = Node->getValueType(0);
2515 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2516 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2517 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2519 assert(Node->getValueType(0) == MVT::i32 &&
2520 "Cannot expand this binary operator!");
2521 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2522 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2524 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2527 // Floating point mod -> fmod libcall.
2528 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2529 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2531 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2532 false/*sign irrelevant*/, Dummy);
2538 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2539 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2541 MVT::ValueType VT = Node->getValueType(0);
2542 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2543 default: assert(0 && "This action is not supported yet!");
2544 case TargetLowering::Custom:
2547 case TargetLowering::Legal:
2548 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2549 Result = Result.getValue(0);
2550 Tmp1 = Result.getValue(1);
2553 Tmp2 = TLI.LowerOperation(Result, DAG);
2555 Result = LegalizeOp(Tmp2);
2556 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2560 case TargetLowering::Expand: {
2561 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2562 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2563 SV->getValue(), SV->getOffset());
2564 // Increment the pointer, VAList, to the next vaarg
2565 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2566 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2567 TLI.getPointerTy()));
2568 // Store the incremented VAList to the legalized pointer
2569 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2571 // Load the actual argument out of the pointer VAList
2572 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2573 Tmp1 = LegalizeOp(Result.getValue(1));
2574 Result = LegalizeOp(Result);
2578 // Since VAARG produces two values, make sure to remember that we
2579 // legalized both of them.
2580 AddLegalizedOperand(SDOperand(Node, 0), Result);
2581 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2582 return Op.ResNo ? Tmp1 : Result;
2586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2587 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2588 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2590 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2591 default: assert(0 && "This action is not supported yet!");
2592 case TargetLowering::Custom:
2595 case TargetLowering::Legal:
2596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2597 Node->getOperand(3), Node->getOperand(4));
2599 Tmp1 = TLI.LowerOperation(Result, DAG);
2600 if (Tmp1.Val) Result = Tmp1;
2603 case TargetLowering::Expand:
2604 // This defaults to loading a pointer from the input and storing it to the
2605 // output, returning the chain.
2606 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2607 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2608 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2610 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2617 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2618 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2620 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2621 default: assert(0 && "This action is not supported yet!");
2622 case TargetLowering::Custom:
2625 case TargetLowering::Legal:
2626 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2628 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2629 if (Tmp1.Val) Result = Tmp1;
2632 case TargetLowering::Expand:
2633 Result = Tmp1; // Default to a no-op, return the chain
2639 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2640 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2642 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2644 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2645 default: assert(0 && "This action is not supported yet!");
2646 case TargetLowering::Legal: break;
2647 case TargetLowering::Custom:
2648 Tmp1 = TLI.LowerOperation(Result, DAG);
2649 if (Tmp1.Val) Result = Tmp1;
2656 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2657 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2658 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2659 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2661 assert(0 && "ROTL/ROTR legalize operation not supported");
2663 case TargetLowering::Legal:
2665 case TargetLowering::Custom:
2666 Tmp1 = TLI.LowerOperation(Result, DAG);
2667 if (Tmp1.Val) Result = Tmp1;
2669 case TargetLowering::Promote:
2670 assert(0 && "Do not know how to promote ROTL/ROTR");
2672 case TargetLowering::Expand:
2673 assert(0 && "Do not know how to expand ROTL/ROTR");
2679 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2680 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2681 case TargetLowering::Custom:
2682 assert(0 && "Cannot custom legalize this yet!");
2683 case TargetLowering::Legal:
2684 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2686 case TargetLowering::Promote: {
2687 MVT::ValueType OVT = Tmp1.getValueType();
2688 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2689 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2691 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2692 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2693 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2694 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2697 case TargetLowering::Expand:
2698 Result = ExpandBSWAP(Tmp1);
2706 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2707 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2708 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2709 case TargetLowering::Legal:
2710 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2712 case TargetLowering::Promote: {
2713 MVT::ValueType OVT = Tmp1.getValueType();
2714 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2716 // Zero extend the argument.
2717 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2718 // Perform the larger operation, then subtract if needed.
2719 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2720 switch (Node->getOpcode()) {
2725 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2726 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2727 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2729 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2730 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2733 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2734 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2735 DAG.getConstant(MVT::getSizeInBits(NVT) -
2736 MVT::getSizeInBits(OVT), NVT));
2741 case TargetLowering::Expand:
2742 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2753 Tmp1 = LegalizeOp(Node->getOperand(0));
2754 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2755 case TargetLowering::Promote:
2756 case TargetLowering::Custom:
2759 case TargetLowering::Legal:
2760 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2762 Tmp1 = TLI.LowerOperation(Result, DAG);
2763 if (Tmp1.Val) Result = Tmp1;
2766 case TargetLowering::Expand:
2767 switch (Node->getOpcode()) {
2768 default: assert(0 && "Unreachable!");
2770 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2771 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2772 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2775 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2776 MVT::ValueType VT = Node->getValueType(0);
2777 Tmp2 = DAG.getConstantFP(0.0, VT);
2778 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2779 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2780 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2786 MVT::ValueType VT = Node->getValueType(0);
2787 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2788 switch(Node->getOpcode()) {
2790 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2793 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2796 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2798 default: assert(0 && "Unreachable!");
2801 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2802 false/*sign irrelevant*/, Dummy);
2810 // We always lower FPOWI into a libcall. No target support it yet.
2811 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2812 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2814 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2815 false/*sign irrelevant*/, Dummy);
2818 case ISD::BIT_CONVERT:
2819 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2820 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2821 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
2822 // The input has to be a vector type, we have to either scalarize it, pack
2823 // it, or convert it based on whether the input vector type is legal.
2824 SDNode *InVal = Node->getOperand(0).Val;
2825 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2826 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2828 // Figure out if there is a simple type corresponding to this Vector
2829 // type. If so, convert to the vector type.
2830 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2831 if (TLI.isTypeLegal(TVT)) {
2832 // Turn this into a bit convert of the packed input.
2833 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2834 LegalizeOp(Node->getOperand(0)));
2836 } else if (NumElems == 1) {
2837 // Turn this into a bit convert of the scalar input.
2838 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2839 ScalarizeVectorOp(Node->getOperand(0)));
2842 // FIXME: UNIMP! Store then reload
2843 assert(0 && "Cast from unsupported vector type not implemented yet!");
2846 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2847 Node->getOperand(0).getValueType())) {
2848 default: assert(0 && "Unknown operation action!");
2849 case TargetLowering::Expand:
2850 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2852 case TargetLowering::Legal:
2853 Tmp1 = LegalizeOp(Node->getOperand(0));
2854 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2860 // Conversion operators. The source and destination have different types.
2861 case ISD::SINT_TO_FP:
2862 case ISD::UINT_TO_FP: {
2863 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2864 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2866 switch (TLI.getOperationAction(Node->getOpcode(),
2867 Node->getOperand(0).getValueType())) {
2868 default: assert(0 && "Unknown operation action!");
2869 case TargetLowering::Custom:
2872 case TargetLowering::Legal:
2873 Tmp1 = LegalizeOp(Node->getOperand(0));
2874 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2876 Tmp1 = TLI.LowerOperation(Result, DAG);
2877 if (Tmp1.Val) Result = Tmp1;
2880 case TargetLowering::Expand:
2881 Result = ExpandLegalINT_TO_FP(isSigned,
2882 LegalizeOp(Node->getOperand(0)),
2883 Node->getValueType(0));
2885 case TargetLowering::Promote:
2886 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2887 Node->getValueType(0),
2893 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2894 Node->getValueType(0), Node->getOperand(0));
2897 Tmp1 = PromoteOp(Node->getOperand(0));
2899 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2900 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2902 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2903 Node->getOperand(0).getValueType());
2905 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2906 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2912 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2914 Tmp1 = LegalizeOp(Node->getOperand(0));
2915 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2918 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2920 // Since the result is legal, we should just be able to truncate the low
2921 // part of the source.
2922 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2925 Result = PromoteOp(Node->getOperand(0));
2926 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2931 case ISD::FP_TO_SINT:
2932 case ISD::FP_TO_UINT:
2933 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2935 Tmp1 = LegalizeOp(Node->getOperand(0));
2937 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2938 default: assert(0 && "Unknown operation action!");
2939 case TargetLowering::Custom:
2942 case TargetLowering::Legal:
2943 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2945 Tmp1 = TLI.LowerOperation(Result, DAG);
2946 if (Tmp1.Val) Result = Tmp1;
2949 case TargetLowering::Promote:
2950 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2951 Node->getOpcode() == ISD::FP_TO_SINT);
2953 case TargetLowering::Expand:
2954 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2955 SDOperand True, False;
2956 MVT::ValueType VT = Node->getOperand(0).getValueType();
2957 MVT::ValueType NVT = Node->getValueType(0);
2958 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2959 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2960 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2961 Node->getOperand(0), Tmp2, ISD::SETLT);
2962 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2963 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2964 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2966 False = DAG.getNode(ISD::XOR, NVT, False,
2967 DAG.getConstant(1ULL << ShiftAmt, NVT));
2968 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2971 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2977 // Convert f32 / f64 to i32 / i64.
2978 MVT::ValueType VT = Op.getValueType();
2979 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2980 switch (Node->getOpcode()) {
2981 case ISD::FP_TO_SINT:
2982 if (Node->getOperand(0).getValueType() == MVT::f32)
2983 LC = (VT == MVT::i32)
2984 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
2986 LC = (VT == MVT::i32)
2987 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
2989 case ISD::FP_TO_UINT:
2990 if (Node->getOperand(0).getValueType() == MVT::f32)
2991 LC = (VT == MVT::i32)
2992 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
2994 LC = (VT == MVT::i32)
2995 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
2997 default: assert(0 && "Unreachable!");
3000 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3001 false/*sign irrelevant*/, Dummy);
3005 Tmp1 = PromoteOp(Node->getOperand(0));
3006 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3007 Result = LegalizeOp(Result);
3013 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3014 TargetLowering::Expand) {
3015 // The only way we can lower this is to turn it into a TRUNCSTORE,
3016 // EXTLOAD pair, targetting a temporary location (a stack slot).
3018 // NOTE: there is a choice here between constantly creating new stack
3019 // slots and always reusing the same one. We currently always create
3020 // new ones, as reuse may inhibit scheduling.
3021 MVT::ValueType VT = Op.getValueType(); // 32
3022 const Type *Ty = MVT::getTypeForValueType(VT);
3023 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3024 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3025 MachineFunction &MF = DAG.getMachineFunction();
3027 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3028 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3029 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3030 StackSlot, NULL, 0, VT);
3031 Result = DAG.getLoad(VT, Result, StackSlot, NULL, 0, VT);
3035 case ISD::ANY_EXTEND:
3036 case ISD::ZERO_EXTEND:
3037 case ISD::SIGN_EXTEND:
3038 case ISD::FP_EXTEND:
3039 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3040 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3042 Tmp1 = LegalizeOp(Node->getOperand(0));
3043 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3046 switch (Node->getOpcode()) {
3047 case ISD::ANY_EXTEND:
3048 Tmp1 = PromoteOp(Node->getOperand(0));
3049 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3051 case ISD::ZERO_EXTEND:
3052 Result = PromoteOp(Node->getOperand(0));
3053 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3054 Result = DAG.getZeroExtendInReg(Result,
3055 Node->getOperand(0).getValueType());
3057 case ISD::SIGN_EXTEND:
3058 Result = PromoteOp(Node->getOperand(0));
3059 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3060 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3062 DAG.getValueType(Node->getOperand(0).getValueType()));
3064 case ISD::FP_EXTEND:
3065 Result = PromoteOp(Node->getOperand(0));
3066 if (Result.getValueType() != Op.getValueType())
3067 // Dynamically dead while we have only 2 FP types.
3068 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3071 Result = PromoteOp(Node->getOperand(0));
3072 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3077 case ISD::FP_ROUND_INREG:
3078 case ISD::SIGN_EXTEND_INREG: {
3079 Tmp1 = LegalizeOp(Node->getOperand(0));
3080 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3082 // If this operation is not supported, convert it to a shl/shr or load/store
3084 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3085 default: assert(0 && "This action not supported for this op yet!");
3086 case TargetLowering::Legal:
3087 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3089 case TargetLowering::Expand:
3090 // If this is an integer extend and shifts are supported, do that.
3091 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3092 // NOTE: we could fall back on load/store here too for targets without
3093 // SAR. However, it is doubtful that any exist.
3094 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3095 MVT::getSizeInBits(ExtraVT);
3096 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3097 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3098 Node->getOperand(0), ShiftCst);
3099 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3101 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3102 // The only way we can lower this is to turn it into a TRUNCSTORE,
3103 // EXTLOAD pair, targetting a temporary location (a stack slot).
3105 // NOTE: there is a choice here between constantly creating new stack
3106 // slots and always reusing the same one. We currently always create
3107 // new ones, as reuse may inhibit scheduling.
3108 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3109 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3110 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3111 MachineFunction &MF = DAG.getMachineFunction();
3113 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3114 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3115 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3116 StackSlot, NULL, 0, ExtraVT);
3117 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3118 Result, StackSlot, NULL, 0, ExtraVT);
3120 assert(0 && "Unknown op");
3128 assert(Result.getValueType() == Op.getValueType() &&
3129 "Bad legalization!");
3131 // Make sure that the generated code is itself legal.
3133 Result = LegalizeOp(Result);
3135 // Note that LegalizeOp may be reentered even from single-use nodes, which
3136 // means that we always must cache transformed nodes.
3137 AddLegalizedOperand(Op, Result);
3141 /// PromoteOp - Given an operation that produces a value in an invalid type,
3142 /// promote it to compute the value into a larger type. The produced value will
3143 /// have the correct bits for the low portion of the register, but no guarantee
3144 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3145 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3146 MVT::ValueType VT = Op.getValueType();
3147 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3148 assert(getTypeAction(VT) == Promote &&
3149 "Caller should expand or legalize operands that are not promotable!");
3150 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3151 "Cannot promote to smaller type!");
3153 SDOperand Tmp1, Tmp2, Tmp3;
3155 SDNode *Node = Op.Val;
3157 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3158 if (I != PromotedNodes.end()) return I->second;
3160 switch (Node->getOpcode()) {
3161 case ISD::CopyFromReg:
3162 assert(0 && "CopyFromReg must be legal!");
3165 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3167 assert(0 && "Do not know how to promote this operator!");
3170 Result = DAG.getNode(ISD::UNDEF, NVT);
3174 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3176 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3177 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3179 case ISD::ConstantFP:
3180 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3181 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3185 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3186 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3187 Node->getOperand(1), Node->getOperand(2));
3191 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3193 Result = LegalizeOp(Node->getOperand(0));
3194 assert(Result.getValueType() >= NVT &&
3195 "This truncation doesn't make sense!");
3196 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3197 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3200 // The truncation is not required, because we don't guarantee anything
3201 // about high bits anyway.
3202 Result = PromoteOp(Node->getOperand(0));
3205 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3206 // Truncate the low part of the expanded value to the result type
3207 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3210 case ISD::SIGN_EXTEND:
3211 case ISD::ZERO_EXTEND:
3212 case ISD::ANY_EXTEND:
3213 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3214 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3216 // Input is legal? Just do extend all the way to the larger type.
3217 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3220 // Promote the reg if it's smaller.
3221 Result = PromoteOp(Node->getOperand(0));
3222 // The high bits are not guaranteed to be anything. Insert an extend.
3223 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3224 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3225 DAG.getValueType(Node->getOperand(0).getValueType()));
3226 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3227 Result = DAG.getZeroExtendInReg(Result,
3228 Node->getOperand(0).getValueType());
3232 case ISD::BIT_CONVERT:
3233 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3234 Result = PromoteOp(Result);
3237 case ISD::FP_EXTEND:
3238 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3240 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3241 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3242 case Promote: assert(0 && "Unreachable with 2 FP types!");
3244 // Input is legal? Do an FP_ROUND_INREG.
3245 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3246 DAG.getValueType(VT));
3251 case ISD::SINT_TO_FP:
3252 case ISD::UINT_TO_FP:
3253 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3255 // No extra round required here.
3256 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3260 Result = PromoteOp(Node->getOperand(0));
3261 if (Node->getOpcode() == ISD::SINT_TO_FP)
3262 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3264 DAG.getValueType(Node->getOperand(0).getValueType()));
3266 Result = DAG.getZeroExtendInReg(Result,
3267 Node->getOperand(0).getValueType());
3268 // No extra round required here.
3269 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3272 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3273 Node->getOperand(0));
3274 // Round if we cannot tolerate excess precision.
3275 if (NoExcessFPPrecision)
3276 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3277 DAG.getValueType(VT));
3282 case ISD::SIGN_EXTEND_INREG:
3283 Result = PromoteOp(Node->getOperand(0));
3284 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3285 Node->getOperand(1));
3287 case ISD::FP_TO_SINT:
3288 case ISD::FP_TO_UINT:
3289 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3292 Tmp1 = Node->getOperand(0);
3295 // The input result is prerounded, so we don't have to do anything
3297 Tmp1 = PromoteOp(Node->getOperand(0));
3300 // If we're promoting a UINT to a larger size, check to see if the new node
3301 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3302 // we can use that instead. This allows us to generate better code for
3303 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3304 // legal, such as PowerPC.
3305 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3306 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3307 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3308 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3309 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3311 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3317 Tmp1 = PromoteOp(Node->getOperand(0));
3318 assert(Tmp1.getValueType() == NVT);
3319 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3320 // NOTE: we do not have to do any extra rounding here for
3321 // NoExcessFPPrecision, because we know the input will have the appropriate
3322 // precision, and these operations don't modify precision at all.
3328 Tmp1 = PromoteOp(Node->getOperand(0));
3329 assert(Tmp1.getValueType() == NVT);
3330 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3331 if (NoExcessFPPrecision)
3332 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3333 DAG.getValueType(VT));
3337 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3338 // directly as well, which may be better.
3339 Tmp1 = PromoteOp(Node->getOperand(0));
3340 assert(Tmp1.getValueType() == NVT);
3341 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3342 if (NoExcessFPPrecision)
3343 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3344 DAG.getValueType(VT));
3354 // The input may have strange things in the top bits of the registers, but
3355 // these operations don't care. They may have weird bits going out, but
3356 // that too is okay if they are integer operations.
3357 Tmp1 = PromoteOp(Node->getOperand(0));
3358 Tmp2 = PromoteOp(Node->getOperand(1));
3359 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3360 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3365 Tmp1 = PromoteOp(Node->getOperand(0));
3366 Tmp2 = PromoteOp(Node->getOperand(1));
3367 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3368 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3370 // Floating point operations will give excess precision that we may not be
3371 // able to tolerate. If we DO allow excess precision, just leave it,
3372 // otherwise excise it.
3373 // FIXME: Why would we need to round FP ops more than integer ones?
3374 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3375 if (NoExcessFPPrecision)
3376 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3377 DAG.getValueType(VT));
3382 // These operators require that their input be sign extended.
3383 Tmp1 = PromoteOp(Node->getOperand(0));
3384 Tmp2 = PromoteOp(Node->getOperand(1));
3385 if (MVT::isInteger(NVT)) {
3386 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3387 DAG.getValueType(VT));
3388 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3389 DAG.getValueType(VT));
3391 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3393 // Perform FP_ROUND: this is probably overly pessimistic.
3394 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3395 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3396 DAG.getValueType(VT));
3400 case ISD::FCOPYSIGN:
3401 // These operators require that their input be fp extended.
3402 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3404 Tmp1 = LegalizeOp(Node->getOperand(0));
3407 Tmp1 = PromoteOp(Node->getOperand(0));
3410 assert(0 && "not implemented");
3412 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3414 Tmp2 = LegalizeOp(Node->getOperand(1));
3417 Tmp2 = PromoteOp(Node->getOperand(1));
3420 assert(0 && "not implemented");
3422 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3424 // Perform FP_ROUND: this is probably overly pessimistic.
3425 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3426 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3427 DAG.getValueType(VT));
3432 // These operators require that their input be zero extended.
3433 Tmp1 = PromoteOp(Node->getOperand(0));
3434 Tmp2 = PromoteOp(Node->getOperand(1));
3435 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3436 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3437 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3438 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3442 Tmp1 = PromoteOp(Node->getOperand(0));
3443 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3446 // The input value must be properly sign extended.
3447 Tmp1 = PromoteOp(Node->getOperand(0));
3448 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3449 DAG.getValueType(VT));
3450 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3453 // The input value must be properly zero extended.
3454 Tmp1 = PromoteOp(Node->getOperand(0));
3455 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3456 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3460 Tmp1 = Node->getOperand(0); // Get the chain.
3461 Tmp2 = Node->getOperand(1); // Get the pointer.
3462 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3463 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3464 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3466 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3467 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3468 SV->getValue(), SV->getOffset());
3469 // Increment the pointer, VAList, to the next vaarg
3470 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3471 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3472 TLI.getPointerTy()));
3473 // Store the incremented VAList to the legalized pointer
3474 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3476 // Load the actual argument out of the pointer VAList
3477 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3479 // Remember that we legalized the chain.
3480 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3484 LoadSDNode *LD = cast<LoadSDNode>(Node);
3485 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3486 ? ISD::EXTLOAD : LD->getExtensionType();
3487 Result = DAG.getExtLoad(ExtType, NVT,
3488 LD->getChain(), LD->getBasePtr(),
3489 LD->getSrcValue(), LD->getSrcValueOffset(),
3492 LD->getAlignment());
3493 // Remember that we legalized the chain.
3494 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3498 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3499 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3500 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3502 case ISD::SELECT_CC:
3503 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3504 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3505 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3506 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3509 Tmp1 = Node->getOperand(0);
3510 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3511 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3512 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3513 DAG.getConstant(MVT::getSizeInBits(NVT) -
3514 MVT::getSizeInBits(VT),
3515 TLI.getShiftAmountTy()));
3520 // Zero extend the argument
3521 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3522 // Perform the larger operation, then subtract if needed.
3523 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3524 switch(Node->getOpcode()) {
3529 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3530 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3531 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3533 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3534 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3537 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3538 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3539 DAG.getConstant(MVT::getSizeInBits(NVT) -
3540 MVT::getSizeInBits(VT), NVT));
3544 case ISD::EXTRACT_SUBVECTOR:
3545 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3547 case ISD::EXTRACT_VECTOR_ELT:
3548 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3552 assert(Result.Val && "Didn't set a result!");
3554 // Make sure the result is itself legal.
3555 Result = LegalizeOp(Result);
3557 // Remember that we promoted this!
3558 AddPromotedOperand(Op, Result);
3562 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3563 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3564 /// based on the vector type. The return type of this matches the element type
3565 /// of the vector, which may not be legal for the target.
3566 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3567 // We know that operand #0 is the Vec vector. If the index is a constant
3568 // or if the invec is a supported hardware type, we can use it. Otherwise,
3569 // lower to a store then an indexed load.
3570 SDOperand Vec = Op.getOperand(0);
3571 SDOperand Idx = Op.getOperand(1);
3573 SDNode *InVal = Vec.Val;
3574 MVT::ValueType TVT = InVal->getValueType(0);
3575 unsigned NumElems = MVT::getVectorNumElements(TVT);
3577 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3578 default: assert(0 && "This action is not supported yet!");
3579 case TargetLowering::Custom: {
3580 Vec = LegalizeOp(Vec);
3581 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3582 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3587 case TargetLowering::Legal:
3588 if (isTypeLegal(TVT)) {
3589 Vec = LegalizeOp(Vec);
3590 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3591 Op = LegalizeOp(Op);
3594 case TargetLowering::Expand:
3598 if (NumElems == 1) {
3599 // This must be an access of the only element. Return it.
3600 Op = ScalarizeVectorOp(Vec);
3601 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3602 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3604 SplitVectorOp(Vec, Lo, Hi);
3605 if (CIdx->getValue() < NumElems/2) {
3609 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3610 Idx.getValueType());
3613 // It's now an extract from the appropriate high or low part. Recurse.
3614 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3615 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3617 // Store the value to a temporary stack slot, then LOAD the scalar
3618 // element back out.
3619 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3620 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3622 // Add the offset to the index.
3623 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3624 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3625 DAG.getConstant(EltSize, Idx.getValueType()));
3626 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3628 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3633 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3634 /// we assume the operation can be split if it is not already legal.
3635 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3636 // We know that operand #0 is the Vec vector. For now we assume the index
3637 // is a constant and that the extracted result is a supported hardware type.
3638 SDOperand Vec = Op.getOperand(0);
3639 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3641 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3643 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3644 // This must be an access of the desired vector length. Return it.
3648 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3650 SplitVectorOp(Vec, Lo, Hi);
3651 if (CIdx->getValue() < NumElems/2) {
3655 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3658 // It's now an extract from the appropriate high or low part. Recurse.
3659 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3660 return ExpandEXTRACT_SUBVECTOR(Op);
3663 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3664 /// with condition CC on the current target. This usually involves legalizing
3665 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3666 /// there may be no choice but to create a new SetCC node to represent the
3667 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3668 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3669 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3672 SDOperand Tmp1, Tmp2, Result;
3674 switch (getTypeAction(LHS.getValueType())) {
3676 Tmp1 = LegalizeOp(LHS); // LHS
3677 Tmp2 = LegalizeOp(RHS); // RHS
3680 Tmp1 = PromoteOp(LHS); // LHS
3681 Tmp2 = PromoteOp(RHS); // RHS
3683 // If this is an FP compare, the operands have already been extended.
3684 if (MVT::isInteger(LHS.getValueType())) {
3685 MVT::ValueType VT = LHS.getValueType();
3686 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3688 // Otherwise, we have to insert explicit sign or zero extends. Note
3689 // that we could insert sign extends for ALL conditions, but zero extend
3690 // is cheaper on many machines (an AND instead of two shifts), so prefer
3692 switch (cast<CondCodeSDNode>(CC)->get()) {
3693 default: assert(0 && "Unknown integer comparison!");
3700 // ALL of these operations will work if we either sign or zero extend
3701 // the operands (including the unsigned comparisons!). Zero extend is
3702 // usually a simpler/cheaper operation, so prefer it.
3703 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3704 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3710 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3711 DAG.getValueType(VT));
3712 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3713 DAG.getValueType(VT));
3719 MVT::ValueType VT = LHS.getValueType();
3720 if (VT == MVT::f32 || VT == MVT::f64) {
3721 // Expand into one or more soft-fp libcall(s).
3722 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3723 switch (cast<CondCodeSDNode>(CC)->get()) {
3726 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3730 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3734 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3738 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3742 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3746 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3749 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3752 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3755 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3756 switch (cast<CondCodeSDNode>(CC)->get()) {
3758 // SETONE = SETOLT | SETOGT
3759 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3762 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3765 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3768 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3771 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3774 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3776 default: assert(0 && "Unsupported FP setcc!");
3781 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3782 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3783 false /*sign irrelevant*/, Dummy);
3784 Tmp2 = DAG.getConstant(0, MVT::i32);
3785 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
3786 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3787 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3788 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3789 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3790 false /*sign irrelevant*/, Dummy);
3791 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3792 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
3793 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3801 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3802 ExpandOp(LHS, LHSLo, LHSHi);
3803 ExpandOp(RHS, RHSLo, RHSHi);
3804 switch (cast<CondCodeSDNode>(CC)->get()) {
3808 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3809 if (RHSCST->isAllOnesValue()) {
3810 // Comparison to -1.
3811 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3816 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3817 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3818 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3819 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3822 // If this is a comparison of the sign bit, just look at the top part.
3824 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3825 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3826 CST->getValue() == 0) || // X < 0
3827 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3828 CST->isAllOnesValue())) { // X > -1
3834 // FIXME: This generated code sucks.
3835 ISD::CondCode LowCC;
3836 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
3838 default: assert(0 && "Unknown integer setcc!");
3840 case ISD::SETULT: LowCC = ISD::SETULT; break;
3842 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3844 case ISD::SETULE: LowCC = ISD::SETULE; break;
3846 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3849 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3850 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3851 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3853 // NOTE: on targets without efficient SELECT of bools, we can always use
3854 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3855 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
3856 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
3857 false, DagCombineInfo);
3859 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3860 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3861 CCCode, false, DagCombineInfo);
3863 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3865 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
3866 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
3867 if ((Tmp1C && Tmp1C->getValue() == 0) ||
3868 (Tmp2C && Tmp2C->getValue() == 0 &&
3869 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3870 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
3871 (Tmp2C && Tmp2C->getValue() == 1 &&
3872 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
3873 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
3874 // low part is known false, returns high part.
3875 // For LE / GE, if high part is known false, ignore the low part.
3876 // For LT / GT, if high part is known true, ignore the low part.
3880 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3881 ISD::SETEQ, false, DagCombineInfo);
3883 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3884 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3885 Result, Tmp1, Tmp2));
3896 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3897 /// The resultant code need not be legal. Note that SrcOp is the input operand
3898 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3899 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3901 // Create the stack frame object.
3902 SDOperand FIPtr = CreateStackTemporary(DestVT);
3904 // Emit a store to the stack slot.
3905 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3906 // Result is a load from the stack slot.
3907 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3910 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3911 // Create a vector sized/aligned stack slot, store the value to element #0,
3912 // then load the whole vector back out.
3913 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3914 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3916 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3920 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3921 /// support the operation, but do support the resultant packed vector type.
3922 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3924 // If the only non-undef value is the low element, turn this into a
3925 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3926 unsigned NumElems = Node->getNumOperands();
3927 bool isOnlyLowElement = true;
3928 SDOperand SplatValue = Node->getOperand(0);
3929 std::map<SDOperand, std::vector<unsigned> > Values;
3930 Values[SplatValue].push_back(0);
3931 bool isConstant = true;
3932 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3933 SplatValue.getOpcode() != ISD::UNDEF)
3936 for (unsigned i = 1; i < NumElems; ++i) {
3937 SDOperand V = Node->getOperand(i);
3938 Values[V].push_back(i);
3939 if (V.getOpcode() != ISD::UNDEF)
3940 isOnlyLowElement = false;
3941 if (SplatValue != V)
3942 SplatValue = SDOperand(0,0);
3944 // If this isn't a constant element or an undef, we can't use a constant
3946 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3947 V.getOpcode() != ISD::UNDEF)
3951 if (isOnlyLowElement) {
3952 // If the low element is an undef too, then this whole things is an undef.
3953 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3954 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3955 // Otherwise, turn this into a scalar_to_vector node.
3956 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3957 Node->getOperand(0));
3960 // If all elements are constants, create a load from the constant pool.
3962 MVT::ValueType VT = Node->getValueType(0);
3964 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3965 std::vector<Constant*> CV;
3966 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3967 if (ConstantFPSDNode *V =
3968 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3969 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3970 } else if (ConstantSDNode *V =
3971 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3972 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3974 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3975 CV.push_back(UndefValue::get(OpNTy));
3978 Constant *CP = ConstantVector::get(CV);
3979 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3980 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3983 if (SplatValue.Val) { // Splat of one value?
3984 // Build the shuffle constant vector: <0, 0, 0, 0>
3985 MVT::ValueType MaskVT =
3986 MVT::getIntVectorWithNumElements(NumElems);
3987 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
3988 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3989 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3990 &ZeroVec[0], ZeroVec.size());
3992 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3993 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3994 // Get the splatted value into the low element of a vector register.
3995 SDOperand LowValVec =
3996 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3998 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3999 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4000 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4005 // If there are only two unique elements, we may be able to turn this into a
4007 if (Values.size() == 2) {
4008 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4009 MVT::ValueType MaskVT =
4010 MVT::getIntVectorWithNumElements(NumElems);
4011 std::vector<SDOperand> MaskVec(NumElems);
4013 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4014 E = Values.end(); I != E; ++I) {
4015 for (std::vector<unsigned>::iterator II = I->second.begin(),
4016 EE = I->second.end(); II != EE; ++II)
4017 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4020 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4021 &MaskVec[0], MaskVec.size());
4023 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4024 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4025 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4026 SmallVector<SDOperand, 8> Ops;
4027 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4028 E = Values.end(); I != E; ++I) {
4029 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4033 Ops.push_back(ShuffleMask);
4035 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4036 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4037 &Ops[0], Ops.size());
4041 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4042 // aligned object on the stack, store each element into it, then load
4043 // the result as a vector.
4044 MVT::ValueType VT = Node->getValueType(0);
4045 // Create the stack frame object.
4046 SDOperand FIPtr = CreateStackTemporary(VT);
4048 // Emit a store of each element to the stack slot.
4049 SmallVector<SDOperand, 8> Stores;
4050 unsigned TypeByteSize =
4051 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4052 // Store (in the right endianness) the elements to memory.
4053 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4054 // Ignore undef elements.
4055 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4057 unsigned Offset = TypeByteSize*i;
4059 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4060 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4062 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4066 SDOperand StoreChain;
4067 if (!Stores.empty()) // Not all undef elements?
4068 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4069 &Stores[0], Stores.size());
4071 StoreChain = DAG.getEntryNode();
4073 // Result is a load from the stack slot.
4074 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4077 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4078 /// specified value type.
4079 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4080 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4081 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4082 const Type *Ty = MVT::getTypeForValueType(VT);
4083 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4084 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4085 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4088 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4089 SDOperand Op, SDOperand Amt,
4090 SDOperand &Lo, SDOperand &Hi) {
4091 // Expand the subcomponents.
4092 SDOperand LHSL, LHSH;
4093 ExpandOp(Op, LHSL, LHSH);
4095 SDOperand Ops[] = { LHSL, LHSH, Amt };
4096 MVT::ValueType VT = LHSL.getValueType();
4097 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4098 Hi = Lo.getValue(1);
4102 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4103 /// smaller elements. If we can't find a way that is more efficient than a
4104 /// libcall on this target, return false. Otherwise, return true with the
4105 /// low-parts expanded into Lo and Hi.
4106 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4107 SDOperand &Lo, SDOperand &Hi) {
4108 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4109 "This is not a shift!");
4111 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4112 SDOperand ShAmt = LegalizeOp(Amt);
4113 MVT::ValueType ShTy = ShAmt.getValueType();
4114 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4115 unsigned NVTBits = MVT::getSizeInBits(NVT);
4117 // Handle the case when Amt is an immediate. Other cases are currently broken
4118 // and are disabled.
4119 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4120 unsigned Cst = CN->getValue();
4121 // Expand the incoming operand to be shifted, so that we have its parts
4123 ExpandOp(Op, InL, InH);
4127 Lo = DAG.getConstant(0, NVT);
4128 Hi = DAG.getConstant(0, NVT);
4129 } else if (Cst > NVTBits) {
4130 Lo = DAG.getConstant(0, NVT);
4131 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4132 } else if (Cst == NVTBits) {
4133 Lo = DAG.getConstant(0, NVT);
4136 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4137 Hi = DAG.getNode(ISD::OR, NVT,
4138 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4139 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4144 Lo = DAG.getConstant(0, NVT);
4145 Hi = DAG.getConstant(0, NVT);
4146 } else if (Cst > NVTBits) {
4147 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4148 Hi = DAG.getConstant(0, NVT);
4149 } else if (Cst == NVTBits) {
4151 Hi = DAG.getConstant(0, NVT);
4153 Lo = DAG.getNode(ISD::OR, NVT,
4154 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4155 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4156 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4161 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4162 DAG.getConstant(NVTBits-1, ShTy));
4163 } else if (Cst > NVTBits) {
4164 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4165 DAG.getConstant(Cst-NVTBits, ShTy));
4166 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4167 DAG.getConstant(NVTBits-1, ShTy));
4168 } else if (Cst == NVTBits) {
4170 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4171 DAG.getConstant(NVTBits-1, ShTy));
4173 Lo = DAG.getNode(ISD::OR, NVT,
4174 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4175 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4176 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4182 // Okay, the shift amount isn't constant. However, if we can tell that it is
4183 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4184 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4185 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4187 // If we know that the high bit of the shift amount is one, then we can do
4188 // this as a couple of simple shifts.
4189 if (KnownOne & Mask) {
4190 // Mask out the high bit, which we know is set.
4191 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4192 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4194 // Expand the incoming operand to be shifted, so that we have its parts
4196 ExpandOp(Op, InL, InH);
4199 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4200 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4203 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4204 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4207 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4208 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4209 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4214 // If we know that the high bit of the shift amount is zero, then we can do
4215 // this as a couple of simple shifts.
4216 if (KnownZero & Mask) {
4218 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4219 DAG.getConstant(NVTBits, Amt.getValueType()),
4222 // Expand the incoming operand to be shifted, so that we have its parts
4224 ExpandOp(Op, InL, InH);
4227 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4228 Hi = DAG.getNode(ISD::OR, NVT,
4229 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4230 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4233 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4234 Lo = DAG.getNode(ISD::OR, NVT,
4235 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4236 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4239 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4240 Lo = DAG.getNode(ISD::OR, NVT,
4241 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4242 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4251 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4252 // does not fit into a register, return the lo part and set the hi part to the
4253 // by-reg argument. If it does fit into a single register, return the result
4254 // and leave the Hi part unset.
4255 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4256 bool isSigned, SDOperand &Hi) {
4257 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4258 // The input chain to this libcall is the entry node of the function.
4259 // Legalizing the call will automatically add the previous call to the
4261 SDOperand InChain = DAG.getEntryNode();
4263 TargetLowering::ArgListTy Args;
4264 TargetLowering::ArgListEntry Entry;
4265 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4266 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4267 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4268 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4269 Entry.isSExt = isSigned;
4270 Args.push_back(Entry);
4272 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4274 // Splice the libcall in wherever FindInputOutputChains tells us to.
4275 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4276 std::pair<SDOperand,SDOperand> CallInfo =
4277 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4280 // Legalize the call sequence, starting with the chain. This will advance
4281 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4282 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4283 LegalizeOp(CallInfo.second);
4285 switch (getTypeAction(CallInfo.first.getValueType())) {
4286 default: assert(0 && "Unknown thing");
4288 Result = CallInfo.first;
4291 ExpandOp(CallInfo.first, Result, Hi);
4298 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4300 SDOperand SelectionDAGLegalize::
4301 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4302 assert(getTypeAction(Source.getValueType()) == Expand &&
4303 "This is not an expansion!");
4304 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4307 assert(Source.getValueType() == MVT::i64 &&
4308 "This only works for 64-bit -> FP");
4309 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4310 // incoming integer is set. To handle this, we dynamically test to see if
4311 // it is set, and, if so, add a fudge factor.
4313 ExpandOp(Source, Lo, Hi);
4315 // If this is unsigned, and not supported, first perform the conversion to
4316 // signed, then adjust the result if the sign bit is set.
4317 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4318 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4320 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4321 DAG.getConstant(0, Hi.getValueType()),
4323 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4324 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4325 SignSet, Four, Zero);
4326 uint64_t FF = 0x5f800000ULL;
4327 if (TLI.isLittleEndian()) FF <<= 32;
4328 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4330 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4331 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4332 SDOperand FudgeInReg;
4333 if (DestTy == MVT::f32)
4334 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4336 assert(DestTy == MVT::f64 && "Unexpected conversion");
4337 // FIXME: Avoid the extend by construction the right constantpool?
4338 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4339 CPIdx, NULL, 0, MVT::f32);
4341 MVT::ValueType SCVT = SignedConv.getValueType();
4342 if (SCVT != DestTy) {
4343 // Destination type needs to be expanded as well. The FADD now we are
4344 // constructing will be expanded into a libcall.
4345 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4346 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4347 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4348 SignedConv, SignedConv.getValue(1));
4350 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4352 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4355 // Check to see if the target has a custom way to lower this. If so, use it.
4356 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4357 default: assert(0 && "This action not implemented for this operation!");
4358 case TargetLowering::Legal:
4359 case TargetLowering::Expand:
4360 break; // This case is handled below.
4361 case TargetLowering::Custom: {
4362 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4365 return LegalizeOp(NV);
4366 break; // The target decided this was legal after all
4370 // Expand the source, then glue it back together for the call. We must expand
4371 // the source in case it is shared (this pass of legalize must traverse it).
4372 SDOperand SrcLo, SrcHi;
4373 ExpandOp(Source, SrcLo, SrcHi);
4374 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4377 if (DestTy == MVT::f32)
4378 LC = RTLIB::SINTTOFP_I64_F32;
4380 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4381 LC = RTLIB::SINTTOFP_I64_F64;
4384 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4385 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4386 SDOperand UnusedHiPart;
4387 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4391 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4392 /// INT_TO_FP operation of the specified operand when the target requests that
4393 /// we expand it. At this point, we know that the result and operand types are
4394 /// legal for the target.
4395 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4397 MVT::ValueType DestVT) {
4398 if (Op0.getValueType() == MVT::i32) {
4399 // simple 32-bit [signed|unsigned] integer to float/double expansion
4401 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4402 MachineFunction &MF = DAG.getMachineFunction();
4403 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4404 unsigned StackAlign =
4405 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4406 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4407 // get address of 8 byte buffer
4408 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4409 // word offset constant for Hi/Lo address computation
4410 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4411 // set up Hi and Lo (into buffer) address based on endian
4412 SDOperand Hi = StackSlot;
4413 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4414 if (TLI.isLittleEndian())
4417 // if signed map to unsigned space
4418 SDOperand Op0Mapped;
4420 // constant used to invert sign bit (signed to unsigned mapping)
4421 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4422 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4426 // store the lo of the constructed double - based on integer input
4427 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4428 Op0Mapped, Lo, NULL, 0);
4429 // initial hi portion of constructed double
4430 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4431 // store the hi of the constructed double - biased exponent
4432 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4433 // load the constructed double
4434 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4435 // FP constant to bias correct the final result
4436 SDOperand Bias = DAG.getConstantFP(isSigned ?
4437 BitsToDouble(0x4330000080000000ULL)
4438 : BitsToDouble(0x4330000000000000ULL),
4440 // subtract the bias
4441 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4444 // handle final rounding
4445 if (DestVT == MVT::f64) {
4449 // if f32 then cast to f32
4450 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4454 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4455 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4457 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4458 DAG.getConstant(0, Op0.getValueType()),
4460 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4461 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4462 SignSet, Four, Zero);
4464 // If the sign bit of the integer is set, the large number will be treated
4465 // as a negative number. To counteract this, the dynamic code adds an
4466 // offset depending on the data type.
4468 switch (Op0.getValueType()) {
4469 default: assert(0 && "Unsupported integer type!");
4470 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4471 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4472 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4473 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4475 if (TLI.isLittleEndian()) FF <<= 32;
4476 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4478 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4479 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4480 SDOperand FudgeInReg;
4481 if (DestVT == MVT::f32)
4482 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4484 assert(DestVT == MVT::f64 && "Unexpected conversion");
4485 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4486 DAG.getEntryNode(), CPIdx,
4487 NULL, 0, MVT::f32));
4490 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4493 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4494 /// *INT_TO_FP operation of the specified operand when the target requests that
4495 /// we promote it. At this point, we know that the result and operand types are
4496 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4497 /// operation that takes a larger input.
4498 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4499 MVT::ValueType DestVT,
4501 // First step, figure out the appropriate *INT_TO_FP operation to use.
4502 MVT::ValueType NewInTy = LegalOp.getValueType();
4504 unsigned OpToUse = 0;
4506 // Scan for the appropriate larger type to use.
4508 NewInTy = (MVT::ValueType)(NewInTy+1);
4509 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4511 // If the target supports SINT_TO_FP of this type, use it.
4512 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4514 case TargetLowering::Legal:
4515 if (!TLI.isTypeLegal(NewInTy))
4516 break; // Can't use this datatype.
4518 case TargetLowering::Custom:
4519 OpToUse = ISD::SINT_TO_FP;
4523 if (isSigned) continue;
4525 // If the target supports UINT_TO_FP of this type, use it.
4526 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4528 case TargetLowering::Legal:
4529 if (!TLI.isTypeLegal(NewInTy))
4530 break; // Can't use this datatype.
4532 case TargetLowering::Custom:
4533 OpToUse = ISD::UINT_TO_FP;
4538 // Otherwise, try a larger type.
4541 // Okay, we found the operation and type to use. Zero extend our input to the
4542 // desired type then run the operation on it.
4543 return DAG.getNode(OpToUse, DestVT,
4544 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4548 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4549 /// FP_TO_*INT operation of the specified operand when the target requests that
4550 /// we promote it. At this point, we know that the result and operand types are
4551 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4552 /// operation that returns a larger result.
4553 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4554 MVT::ValueType DestVT,
4556 // First step, figure out the appropriate FP_TO*INT operation to use.
4557 MVT::ValueType NewOutTy = DestVT;
4559 unsigned OpToUse = 0;
4561 // Scan for the appropriate larger type to use.
4563 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4564 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4566 // If the target supports FP_TO_SINT returning this type, use it.
4567 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4569 case TargetLowering::Legal:
4570 if (!TLI.isTypeLegal(NewOutTy))
4571 break; // Can't use this datatype.
4573 case TargetLowering::Custom:
4574 OpToUse = ISD::FP_TO_SINT;
4579 // If the target supports FP_TO_UINT of this type, use it.
4580 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4582 case TargetLowering::Legal:
4583 if (!TLI.isTypeLegal(NewOutTy))
4584 break; // Can't use this datatype.
4586 case TargetLowering::Custom:
4587 OpToUse = ISD::FP_TO_UINT;
4592 // Otherwise, try a larger type.
4595 // Okay, we found the operation and type to use. Truncate the result of the
4596 // extended FP_TO_*INT operation to the desired size.
4597 return DAG.getNode(ISD::TRUNCATE, DestVT,
4598 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4601 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4603 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4604 MVT::ValueType VT = Op.getValueType();
4605 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4606 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4608 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4610 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4611 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4612 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4614 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4615 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4616 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4617 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4618 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4619 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4620 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4621 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4622 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4624 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4625 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4626 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4627 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4628 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4629 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4630 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4631 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4632 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4633 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4634 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4635 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4636 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4637 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4638 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4639 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4640 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4641 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4642 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4643 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4644 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4648 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4650 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4652 default: assert(0 && "Cannot expand this yet!");
4654 static const uint64_t mask[6] = {
4655 0x5555555555555555ULL, 0x3333333333333333ULL,
4656 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4657 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4659 MVT::ValueType VT = Op.getValueType();
4660 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4661 unsigned len = MVT::getSizeInBits(VT);
4662 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4663 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4664 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4665 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4666 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4667 DAG.getNode(ISD::AND, VT,
4668 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4673 // for now, we do this:
4674 // x = x | (x >> 1);
4675 // x = x | (x >> 2);
4677 // x = x | (x >>16);
4678 // x = x | (x >>32); // for 64-bit input
4679 // return popcount(~x);
4681 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4682 MVT::ValueType VT = Op.getValueType();
4683 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4684 unsigned len = MVT::getSizeInBits(VT);
4685 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4686 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4687 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4689 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4690 return DAG.getNode(ISD::CTPOP, VT, Op);
4693 // for now, we use: { return popcount(~x & (x - 1)); }
4694 // unless the target has ctlz but not ctpop, in which case we use:
4695 // { return 32 - nlz(~x & (x-1)); }
4696 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4697 MVT::ValueType VT = Op.getValueType();
4698 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4699 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4700 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4701 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4702 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4703 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4704 TLI.isOperationLegal(ISD::CTLZ, VT))
4705 return DAG.getNode(ISD::SUB, VT,
4706 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4707 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4708 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4713 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4714 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4715 /// LegalizeNodes map is filled in for any results that are not expanded, the
4716 /// ExpandedNodes map is filled in for any results that are expanded, and the
4717 /// Lo/Hi values are returned.
4718 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4719 MVT::ValueType VT = Op.getValueType();
4720 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4721 SDNode *Node = Op.Val;
4722 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4723 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4724 MVT::isVector(VT)) &&
4725 "Cannot expand to FP value or to larger int value!");
4727 // See if we already expanded it.
4728 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4729 = ExpandedNodes.find(Op);
4730 if (I != ExpandedNodes.end()) {
4731 Lo = I->second.first;
4732 Hi = I->second.second;
4736 switch (Node->getOpcode()) {
4737 case ISD::CopyFromReg:
4738 assert(0 && "CopyFromReg must be legal!");
4741 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4743 assert(0 && "Do not know how to expand this operator!");
4746 NVT = TLI.getTypeToExpandTo(VT);
4747 Lo = DAG.getNode(ISD::UNDEF, NVT);
4748 Hi = DAG.getNode(ISD::UNDEF, NVT);
4750 case ISD::Constant: {
4751 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4752 Lo = DAG.getConstant(Cst, NVT);
4753 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4756 case ISD::ConstantFP: {
4757 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4758 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4759 if (getTypeAction(Lo.getValueType()) == Expand)
4760 ExpandOp(Lo, Lo, Hi);
4763 case ISD::BUILD_PAIR:
4764 // Return the operands.
4765 Lo = Node->getOperand(0);
4766 Hi = Node->getOperand(1);
4769 case ISD::SIGN_EXTEND_INREG:
4770 ExpandOp(Node->getOperand(0), Lo, Hi);
4771 // sext_inreg the low part if needed.
4772 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4774 // The high part gets the sign extension from the lo-part. This handles
4775 // things like sextinreg V:i64 from i8.
4776 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4777 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4778 TLI.getShiftAmountTy()));
4782 ExpandOp(Node->getOperand(0), Lo, Hi);
4783 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4784 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4790 ExpandOp(Node->getOperand(0), Lo, Hi);
4791 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4792 DAG.getNode(ISD::CTPOP, NVT, Lo),
4793 DAG.getNode(ISD::CTPOP, NVT, Hi));
4794 Hi = DAG.getConstant(0, NVT);
4798 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4799 ExpandOp(Node->getOperand(0), Lo, Hi);
4800 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4801 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4802 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4804 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4805 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4807 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4808 Hi = DAG.getConstant(0, NVT);
4813 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4814 ExpandOp(Node->getOperand(0), Lo, Hi);
4815 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4816 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4817 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4819 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4820 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4822 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4823 Hi = DAG.getConstant(0, NVT);
4828 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4829 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4830 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4831 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4833 // Remember that we legalized the chain.
4834 Hi = LegalizeOp(Hi);
4835 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4836 if (!TLI.isLittleEndian())
4842 LoadSDNode *LD = cast<LoadSDNode>(Node);
4843 SDOperand Ch = LD->getChain(); // Legalize the chain.
4844 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4845 ISD::LoadExtType ExtType = LD->getExtensionType();
4846 int SVOffset = LD->getSrcValueOffset();
4847 unsigned Alignment = LD->getAlignment();
4848 bool isVolatile = LD->isVolatile();
4850 if (ExtType == ISD::NON_EXTLOAD) {
4851 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
4852 isVolatile, Alignment);
4853 if (VT == MVT::f32 || VT == MVT::f64) {
4854 // f32->i32 or f64->i64 one to one expansion.
4855 // Remember that we legalized the chain.
4856 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4857 // Recursively expand the new load.
4858 if (getTypeAction(NVT) == Expand)
4859 ExpandOp(Lo, Lo, Hi);
4863 // Increment the pointer to the other half.
4864 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4865 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4866 getIntPtrConstant(IncrementSize));
4867 SVOffset += IncrementSize;
4868 if (Alignment > IncrementSize)
4869 Alignment = IncrementSize;
4870 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
4871 isVolatile, Alignment);
4873 // Build a factor node to remember that this load is independent of the
4875 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4878 // Remember that we legalized the chain.
4879 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4880 if (!TLI.isLittleEndian())
4883 MVT::ValueType EVT = LD->getLoadedVT();
4885 if (VT == MVT::f64 && EVT == MVT::f32) {
4886 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4887 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4888 SVOffset, isVolatile, Alignment);
4889 // Remember that we legalized the chain.
4890 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4891 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4896 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4897 SVOffset, isVolatile, Alignment);
4899 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4900 SVOffset, EVT, isVolatile,
4903 // Remember that we legalized the chain.
4904 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4906 if (ExtType == ISD::SEXTLOAD) {
4907 // The high part is obtained by SRA'ing all but one of the bits of the
4909 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4910 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4911 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4912 } else if (ExtType == ISD::ZEXTLOAD) {
4913 // The high part is just a zero.
4914 Hi = DAG.getConstant(0, NVT);
4915 } else /* if (ExtType == ISD::EXTLOAD) */ {
4916 // The high part is undefined.
4917 Hi = DAG.getNode(ISD::UNDEF, NVT);
4924 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4925 SDOperand LL, LH, RL, RH;
4926 ExpandOp(Node->getOperand(0), LL, LH);
4927 ExpandOp(Node->getOperand(1), RL, RH);
4928 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4929 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4933 SDOperand LL, LH, RL, RH;
4934 ExpandOp(Node->getOperand(1), LL, LH);
4935 ExpandOp(Node->getOperand(2), RL, RH);
4936 if (getTypeAction(NVT) == Expand)
4937 NVT = TLI.getTypeToExpandTo(NVT);
4938 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4940 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4943 case ISD::SELECT_CC: {
4944 SDOperand TL, TH, FL, FH;
4945 ExpandOp(Node->getOperand(2), TL, TH);
4946 ExpandOp(Node->getOperand(3), FL, FH);
4947 if (getTypeAction(NVT) == Expand)
4948 NVT = TLI.getTypeToExpandTo(NVT);
4949 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4950 Node->getOperand(1), TL, FL, Node->getOperand(4));
4952 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4953 Node->getOperand(1), TH, FH, Node->getOperand(4));
4956 case ISD::ANY_EXTEND:
4957 // The low part is any extension of the input (which degenerates to a copy).
4958 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4959 // The high part is undefined.
4960 Hi = DAG.getNode(ISD::UNDEF, NVT);
4962 case ISD::SIGN_EXTEND: {
4963 // The low part is just a sign extension of the input (which degenerates to
4965 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4967 // The high part is obtained by SRA'ing all but one of the bits of the lo
4969 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4970 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4971 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4974 case ISD::ZERO_EXTEND:
4975 // The low part is just a zero extension of the input (which degenerates to
4977 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4979 // The high part is just a zero.
4980 Hi = DAG.getConstant(0, NVT);
4983 case ISD::TRUNCATE: {
4984 // The input value must be larger than this value. Expand *it*.
4986 ExpandOp(Node->getOperand(0), NewLo, Hi);
4988 // The low part is now either the right size, or it is closer. If not the
4989 // right size, make an illegal truncate so we recursively expand it.
4990 if (NewLo.getValueType() != Node->getValueType(0))
4991 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
4992 ExpandOp(NewLo, Lo, Hi);
4996 case ISD::BIT_CONVERT: {
4998 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4999 // If the target wants to, allow it to lower this itself.
5000 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5001 case Expand: assert(0 && "cannot expand FP!");
5002 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5003 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5005 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5008 // f32 / f64 must be expanded to i32 / i64.
5009 if (VT == MVT::f32 || VT == MVT::f64) {
5010 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5011 if (getTypeAction(NVT) == Expand)
5012 ExpandOp(Lo, Lo, Hi);
5016 // If source operand will be expanded to the same type as VT, i.e.
5017 // i64 <- f64, i32 <- f32, expand the source operand instead.
5018 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5019 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5020 ExpandOp(Node->getOperand(0), Lo, Hi);
5024 // Turn this into a load/store pair by default.
5026 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5028 ExpandOp(Tmp, Lo, Hi);
5032 case ISD::READCYCLECOUNTER:
5033 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5034 TargetLowering::Custom &&
5035 "Must custom expand ReadCycleCounter");
5036 Lo = TLI.LowerOperation(Op, DAG);
5037 assert(Lo.Val && "Node must be custom expanded!");
5038 Hi = Lo.getValue(1);
5039 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5040 LegalizeOp(Lo.getValue(2)));
5043 // These operators cannot be expanded directly, emit them as calls to
5044 // library functions.
5045 case ISD::FP_TO_SINT: {
5046 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5048 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5049 case Expand: assert(0 && "cannot expand FP!");
5050 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5051 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5054 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5056 // Now that the custom expander is done, expand the result, which is still
5059 ExpandOp(Op, Lo, Hi);
5065 if (Node->getOperand(0).getValueType() == MVT::f32)
5066 LC = RTLIB::FPTOSINT_F32_I64;
5068 LC = RTLIB::FPTOSINT_F64_I64;
5069 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5070 false/*sign irrelevant*/, Hi);
5074 case ISD::FP_TO_UINT: {
5075 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5077 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5078 case Expand: assert(0 && "cannot expand FP!");
5079 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5080 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5083 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5085 // Now that the custom expander is done, expand the result.
5087 ExpandOp(Op, Lo, Hi);
5093 if (Node->getOperand(0).getValueType() == MVT::f32)
5094 LC = RTLIB::FPTOUINT_F32_I64;
5096 LC = RTLIB::FPTOUINT_F64_I64;
5097 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5098 false/*sign irrelevant*/, Hi);
5103 // If the target wants custom lowering, do so.
5104 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5105 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5106 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5107 Op = TLI.LowerOperation(Op, DAG);
5109 // Now that the custom expander is done, expand the result, which is
5111 ExpandOp(Op, Lo, Hi);
5116 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5117 // this X << 1 as X+X.
5118 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5119 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5120 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5121 SDOperand LoOps[2], HiOps[3];
5122 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5123 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5124 LoOps[1] = LoOps[0];
5125 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5127 HiOps[1] = HiOps[0];
5128 HiOps[2] = Lo.getValue(1);
5129 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5134 // If we can emit an efficient shift operation, do so now.
5135 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5138 // If this target supports SHL_PARTS, use it.
5139 TargetLowering::LegalizeAction Action =
5140 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5141 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5142 Action == TargetLowering::Custom) {
5143 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5147 // Otherwise, emit a libcall.
5148 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5149 false/*left shift=unsigned*/, Hi);
5154 // If the target wants custom lowering, do so.
5155 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5156 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5157 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5158 Op = TLI.LowerOperation(Op, DAG);
5160 // Now that the custom expander is done, expand the result, which is
5162 ExpandOp(Op, Lo, Hi);
5167 // If we can emit an efficient shift operation, do so now.
5168 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5171 // If this target supports SRA_PARTS, use it.
5172 TargetLowering::LegalizeAction Action =
5173 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5174 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5175 Action == TargetLowering::Custom) {
5176 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5180 // Otherwise, emit a libcall.
5181 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5182 true/*ashr is signed*/, Hi);
5187 // If the target wants custom lowering, do so.
5188 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5189 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5190 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5191 Op = TLI.LowerOperation(Op, DAG);
5193 // Now that the custom expander is done, expand the result, which is
5195 ExpandOp(Op, Lo, Hi);
5200 // If we can emit an efficient shift operation, do so now.
5201 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5204 // If this target supports SRL_PARTS, use it.
5205 TargetLowering::LegalizeAction Action =
5206 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5207 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5208 Action == TargetLowering::Custom) {
5209 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5213 // Otherwise, emit a libcall.
5214 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5215 false/*lshr is unsigned*/, Hi);
5221 // If the target wants to custom expand this, let them.
5222 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5223 TargetLowering::Custom) {
5224 Op = TLI.LowerOperation(Op, DAG);
5226 ExpandOp(Op, Lo, Hi);
5231 // Expand the subcomponents.
5232 SDOperand LHSL, LHSH, RHSL, RHSH;
5233 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5234 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5235 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5236 SDOperand LoOps[2], HiOps[3];
5241 if (Node->getOpcode() == ISD::ADD) {
5242 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5243 HiOps[2] = Lo.getValue(1);
5244 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5246 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5247 HiOps[2] = Lo.getValue(1);
5248 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5255 // Expand the subcomponents.
5256 SDOperand LHSL, LHSH, RHSL, RHSH;
5257 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5258 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5259 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5260 SDOperand LoOps[2] = { LHSL, RHSL };
5261 SDOperand HiOps[3] = { LHSH, RHSH };
5263 if (Node->getOpcode() == ISD::ADDC) {
5264 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5265 HiOps[2] = Lo.getValue(1);
5266 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5268 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5269 HiOps[2] = Lo.getValue(1);
5270 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5272 // Remember that we legalized the flag.
5273 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5278 // Expand the subcomponents.
5279 SDOperand LHSL, LHSH, RHSL, RHSH;
5280 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5281 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5282 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5283 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5284 SDOperand HiOps[3] = { LHSH, RHSH };
5286 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5287 HiOps[2] = Lo.getValue(1);
5288 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5290 // Remember that we legalized the flag.
5291 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5295 // If the target wants to custom expand this, let them.
5296 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5297 SDOperand New = TLI.LowerOperation(Op, DAG);
5299 ExpandOp(New, Lo, Hi);
5304 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5305 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5306 if (HasMULHS || HasMULHU) {
5307 SDOperand LL, LH, RL, RH;
5308 ExpandOp(Node->getOperand(0), LL, LH);
5309 ExpandOp(Node->getOperand(1), RL, RH);
5310 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5311 // FIXME: Move this to the dag combiner.
5312 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5313 // extended the sign bit of the low half through the upper half, and if so
5314 // emit a MULHS instead of the alternate sequence that is valid for any
5315 // i64 x i64 multiply.
5317 // is RH an extension of the sign bit of RL?
5318 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5319 RH.getOperand(1).getOpcode() == ISD::Constant &&
5320 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5321 // is LH an extension of the sign bit of LL?
5322 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5323 LH.getOperand(1).getOpcode() == ISD::Constant &&
5324 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5326 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5328 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5330 } else if (HasMULHU) {
5332 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5335 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5336 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5337 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5338 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5339 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5344 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5345 false/*sign irrelevant*/, Hi);
5349 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5352 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5355 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5358 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5362 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5363 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5367 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5368 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5372 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5373 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5377 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5378 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5381 case ISD::FP_EXTEND:
5382 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5385 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5390 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5391 switch(Node->getOpcode()) {
5393 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5396 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5399 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5401 default: assert(0 && "Unreachable!");
5403 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5407 SDOperand Mask = (VT == MVT::f64)
5408 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5409 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5410 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5411 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5412 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5413 if (getTypeAction(NVT) == Expand)
5414 ExpandOp(Lo, Lo, Hi);
5418 SDOperand Mask = (VT == MVT::f64)
5419 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5420 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5421 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5422 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5423 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5424 if (getTypeAction(NVT) == Expand)
5425 ExpandOp(Lo, Lo, Hi);
5428 case ISD::FCOPYSIGN: {
5429 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5430 if (getTypeAction(NVT) == Expand)
5431 ExpandOp(Lo, Lo, Hi);
5434 case ISD::SINT_TO_FP:
5435 case ISD::UINT_TO_FP: {
5436 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5437 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5439 if (Node->getOperand(0).getValueType() == MVT::i64) {
5441 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5443 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5446 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5448 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5451 // Promote the operand if needed.
5452 if (getTypeAction(SrcVT) == Promote) {
5453 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5455 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5456 DAG.getValueType(SrcVT))
5457 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5458 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5461 const char *LibCall = TLI.getLibcallName(LC);
5463 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5465 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5466 Node->getOperand(0));
5467 if (getTypeAction(Lo.getValueType()) == Expand)
5468 ExpandOp(Lo, Lo, Hi);
5474 // Make sure the resultant values have been legalized themselves, unless this
5475 // is a type that requires multi-step expansion.
5476 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5477 Lo = LegalizeOp(Lo);
5479 // Don't legalize the high part if it is expanded to a single node.
5480 Hi = LegalizeOp(Hi);
5483 // Remember in a map if the values will be reused later.
5484 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5485 assert(isNew && "Value already expanded?!?");
5488 /// SplitVectorOp - Given an operand of vector type, break it down into
5489 /// two smaller values, still of vector type.
5490 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5492 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5493 SDNode *Node = Op.Val;
5494 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5495 assert(NumElements > 1 && "Cannot split a single element vector!");
5496 unsigned NewNumElts = NumElements/2;
5497 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5498 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5500 // See if we already split it.
5501 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5502 = SplitNodes.find(Op);
5503 if (I != SplitNodes.end()) {
5504 Lo = I->second.first;
5505 Hi = I->second.second;
5509 switch (Node->getOpcode()) {
5514 assert(0 && "Unhandled operation in SplitVectorOp!");
5515 case ISD::BUILD_PAIR:
5516 Lo = Node->getOperand(0);
5517 Hi = Node->getOperand(1);
5519 case ISD::BUILD_VECTOR: {
5520 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5521 Node->op_begin()+NewNumElts);
5522 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5524 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5526 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5529 case ISD::CONCAT_VECTORS: {
5530 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5531 if (NewNumSubvectors == 1) {
5532 Lo = Node->getOperand(0);
5533 Hi = Node->getOperand(1);
5535 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5536 Node->op_begin()+NewNumSubvectors);
5537 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5539 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5541 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5557 SDOperand LL, LH, RL, RH;
5558 SplitVectorOp(Node->getOperand(0), LL, LH);
5559 SplitVectorOp(Node->getOperand(1), RL, RH);
5561 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5562 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5566 LoadSDNode *LD = cast<LoadSDNode>(Node);
5567 SDOperand Ch = LD->getChain();
5568 SDOperand Ptr = LD->getBasePtr();
5569 const Value *SV = LD->getSrcValue();
5570 int SVOffset = LD->getSrcValueOffset();
5571 unsigned Alignment = LD->getAlignment();
5572 bool isVolatile = LD->isVolatile();
5574 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5575 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5576 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5577 getIntPtrConstant(IncrementSize));
5578 SVOffset += IncrementSize;
5579 if (Alignment > IncrementSize)
5580 Alignment = IncrementSize;
5581 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5583 // Build a factor node to remember that this load is independent of the
5585 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5588 // Remember that we legalized the chain.
5589 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5592 case ISD::BIT_CONVERT: {
5593 // We know the result is a vector. The input may be either a vector or a
5595 SDOperand InOp = Node->getOperand(0);
5596 if (!MVT::isVector(InOp.getValueType()) ||
5597 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5598 // The input is a scalar or single-element vector.
5599 // Lower to a store/load so that it can be split.
5600 // FIXME: this could be improved probably.
5601 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5603 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5604 InOp, Ptr, NULL, 0);
5605 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5607 // Split the vector and convert each of the pieces now.
5608 SplitVectorOp(InOp, Lo, Hi);
5609 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5610 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5615 // Remember in a map if the values will be reused later.
5617 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5618 assert(isNew && "Value already split?!?");
5622 /// ScalarizeVectorOp - Given an operand of single-element vector type
5623 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5624 /// scalar (e.g. f32) value.
5625 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5626 assert(MVT::isVector(Op.getValueType()) &&
5627 "Bad ScalarizeVectorOp invocation!");
5628 SDNode *Node = Op.Val;
5629 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5630 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5632 // See if we already scalarized it.
5633 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5634 if (I != ScalarizedNodes.end()) return I->second;
5637 switch (Node->getOpcode()) {
5640 Node->dump(&DAG); cerr << "\n";
5642 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5658 Result = DAG.getNode(Node->getOpcode(),
5660 ScalarizeVectorOp(Node->getOperand(0)),
5661 ScalarizeVectorOp(Node->getOperand(1)));
5668 Result = DAG.getNode(Node->getOpcode(),
5670 ScalarizeVectorOp(Node->getOperand(0)));
5673 LoadSDNode *LD = cast<LoadSDNode>(Node);
5674 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5675 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5677 const Value *SV = LD->getSrcValue();
5678 int SVOffset = LD->getSrcValueOffset();
5679 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5680 LD->isVolatile(), LD->getAlignment());
5682 // Remember that we legalized the chain.
5683 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5686 case ISD::BUILD_VECTOR:
5687 Result = Node->getOperand(0);
5689 case ISD::INSERT_VECTOR_ELT:
5690 // Returning the inserted scalar element.
5691 Result = Node->getOperand(1);
5693 case ISD::CONCAT_VECTORS:
5694 assert(Node->getOperand(0).getValueType() == NewVT &&
5695 "Concat of non-legal vectors not yet supported!");
5696 Result = Node->getOperand(0);
5698 case ISD::VECTOR_SHUFFLE: {
5699 // Figure out if the scalar is the LHS or RHS and return it.
5700 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5701 if (cast<ConstantSDNode>(EltNum)->getValue())
5702 Result = ScalarizeVectorOp(Node->getOperand(1));
5704 Result = ScalarizeVectorOp(Node->getOperand(0));
5707 case ISD::EXTRACT_SUBVECTOR:
5708 Result = Node->getOperand(0);
5709 assert(Result.getValueType() == NewVT);
5711 case ISD::BIT_CONVERT:
5712 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5715 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5716 ScalarizeVectorOp(Op.getOperand(1)),
5717 ScalarizeVectorOp(Op.getOperand(2)));
5721 if (TLI.isTypeLegal(NewVT))
5722 Result = LegalizeOp(Result);
5723 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
5724 assert(isNew && "Value already scalarized?");
5729 // SelectionDAG::Legalize - This is the entry point for the file.
5731 void SelectionDAG::Legalize() {
5732 if (ViewLegalizeDAGs) viewGraph();
5734 /// run - This is the main entry point to this class.
5736 SelectionDAGLegalize(*this).LegalizeDAG();