1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineJumpTableInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/Function.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class SelectionDAGLegalize {
57 const TargetMachine &TM;
58 const TargetLowering &TLI;
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDValue LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDValue, SDValue> LegalizedNodes;
90 void AddLegalizedOperand(SDValue From, SDValue To) {
91 LegalizedNodes.insert(std::make_pair(From, To));
92 // If someone requests legalization of the new node, return itself.
94 LegalizedNodes.insert(std::make_pair(To, To));
98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
100 /// getTypeAction - Return how we should legalize values of this type, either
101 /// it is already legal or we need to expand it into multiple registers of
102 /// smaller integer type, or we need to promote it to a larger type.
103 LegalizeAction getTypeAction(EVT VT) const {
104 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
107 /// isTypeLegal - Return true if this type is legal on this target.
109 bool isTypeLegal(EVT VT) const {
110 return getTypeAction(VT) == Legal;
116 /// LegalizeOp - We know that the specified value has a legal type.
117 /// Recursively ensure that the operands have legal types, then return the
119 SDValue LegalizeOp(SDValue O);
121 SDValue OptimizeFloatStore(StoreSDNode *ST);
123 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
124 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
125 /// is necessary to spill the vector being inserted into to memory, perform
126 /// the insert there, and then read the result back.
127 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
129 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
130 SDValue Idx, DebugLoc dl);
132 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
133 /// performs the same shuffe in terms of order or result bytes, but on a type
134 /// whose vector element type is narrower than the original shuffle type.
135 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
136 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
137 SDValue N1, SDValue N2,
138 SmallVectorImpl<int> &Mask) const;
140 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
141 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
143 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
146 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
147 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
148 SDNode *Node, bool isSigned);
149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
151 RTLIB::Libcall Call_PPCF128);
152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
153 RTLIB::Libcall Call_I8,
154 RTLIB::Libcall Call_I16,
155 RTLIB::Libcall Call_I32,
156 RTLIB::Libcall Call_I64,
157 RTLIB::Libcall Call_I128);
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
160 SDValue ExpandBUILD_VECTOR(SDNode *Node);
161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
163 SmallVectorImpl<SDValue> &Results);
164 SDValue ExpandFCOPYSIGN(SDNode *Node);
165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
176 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
178 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
180 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
181 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
185 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
186 /// performs the same shuffe in terms of order or result bytes, but on a type
187 /// whose vector element type is narrower than the original shuffle type.
188 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
190 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
191 SDValue N1, SDValue N2,
192 SmallVectorImpl<int> &Mask) const {
193 unsigned NumMaskElts = VT.getVectorNumElements();
194 unsigned NumDestElts = NVT.getVectorNumElements();
195 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
197 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
199 if (NumEltsGrowth == 1)
200 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
202 SmallVector<int, 8> NewMask;
203 for (unsigned i = 0; i != NumMaskElts; ++i) {
205 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
207 NewMask.push_back(-1);
209 NewMask.push_back(Idx * NumEltsGrowth + j);
212 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
213 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
214 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
217 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
218 CodeGenOpt::Level ol)
219 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
220 DAG(dag), OptLevel(ol),
221 ValueTypeActions(TLI.getValueTypeActions()) {
222 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
223 "Too many value types for ValueTypeActions to hold!");
226 void SelectionDAGLegalize::LegalizeDAG() {
227 LastCALLSEQ_END = DAG.getEntryNode();
228 IsLegalizingCall = false;
230 // The legalize process is inherently a bottom-up recursive process (users
231 // legalize their uses before themselves). Given infinite stack space, we
232 // could just start legalizing on the root and traverse the whole graph. In
233 // practice however, this causes us to run out of stack space on large basic
234 // blocks. To avoid this problem, compute an ordering of the nodes where each
235 // node is only legalized after all of its operands are legalized.
236 DAG.AssignTopologicalOrder();
237 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
238 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
239 LegalizeOp(SDValue(I, 0));
241 // Finally, it's possible the root changed. Get the new root.
242 SDValue OldRoot = DAG.getRoot();
243 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
244 DAG.setRoot(LegalizedNodes[OldRoot]);
246 LegalizedNodes.clear();
248 // Remove dead nodes now.
249 DAG.RemoveDeadNodes();
253 /// FindCallEndFromCallStart - Given a chained node that is part of a call
254 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
255 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
256 if (Node->getOpcode() == ISD::CALLSEQ_START)
258 if ((Node->getOpcode() == ISD::CALLSEQ_END) && (depth == 1))
260 if (Node->use_empty())
261 return 0; // No CallSeqEnd
263 // The chain is usually at the end.
264 SDValue TheChain(Node, Node->getNumValues()-1);
265 if (TheChain.getValueType() != MVT::Other) {
266 // Sometimes it's at the beginning.
267 TheChain = SDValue(Node, 0);
268 if (TheChain.getValueType() != MVT::Other) {
269 // Otherwise, hunt for it.
270 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
271 if (Node->getValueType(i) == MVT::Other) {
272 TheChain = SDValue(Node, i);
276 // Otherwise, we walked into a node without a chain.
277 if (TheChain.getValueType() != MVT::Other)
282 for (SDNode::use_iterator UI = Node->use_begin(),
283 E = Node->use_end(); UI != E; ++UI) {
285 // Make sure to only follow users of our token chain.
287 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
288 if (User->getOperand(i) == TheChain)
289 if (SDNode *Result = FindCallEndFromCallStart(User, depth))
295 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
296 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
297 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
299 assert(Node && "Didn't find callseq_start for a call??");
300 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
301 Node = Node->getOperand(0).getNode();
302 assert(Node->getOperand(0).getValueType() == MVT::Other &&
303 "Node doesn't have a token chain argument!");
304 switch (Node->getOpcode()) {
307 case ISD::CALLSEQ_START:
312 case ISD::CALLSEQ_END:
320 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
321 /// see if any uses can reach Dest. If no dest operands can get to dest,
322 /// legalize them, legalize ourself, and return false, otherwise, return true.
324 /// Keep track of the nodes we fine that actually do lead to Dest in
325 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
327 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
328 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
329 if (N == Dest) return true; // N certainly leads to Dest :)
331 // If we've already processed this node and it does lead to Dest, there is no
332 // need to reprocess it.
333 if (NodesLeadingTo.count(N)) return true;
335 // If the first result of this node has been already legalized, then it cannot
337 if (LegalizedNodes.count(SDValue(N, 0))) return false;
339 // Okay, this node has not already been legalized. Check and legalize all
340 // operands. If none lead to Dest, then we can legalize this node.
341 bool OperandsLeadToDest = false;
342 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
343 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
344 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
347 if (OperandsLeadToDest) {
348 NodesLeadingTo.insert(N);
352 // Okay, this node looks safe, legalize it and return false.
353 LegalizeOp(SDValue(N, 0));
357 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
358 /// a load from the constant pool.
359 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
360 SelectionDAG &DAG, const TargetLowering &TLI) {
362 DebugLoc dl = CFP->getDebugLoc();
364 // If a FP immediate is precise when represented as a float and if the
365 // target can do an extending load from float to double, we put it into
366 // the constant pool as a float, even if it's is statically typed as a
367 // double. This shrinks FP constants and canonicalizes them for targets where
368 // an FP extending load is the same cost as a normal load (such as on the x87
369 // fp stack or PPC FP unit).
370 EVT VT = CFP->getValueType(0);
371 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
373 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
374 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
375 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
380 while (SVT != MVT::f32) {
381 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
382 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
383 // Only do this if the target has a native EXTLOAD instruction from
385 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
386 TLI.ShouldShrinkFPConstant(OrigVT)) {
387 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
388 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
394 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
395 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
397 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
399 CPIdx, MachinePointerInfo::getConstantPool(),
400 VT, false, false, Alignment);
401 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
402 MachinePointerInfo::getConstantPool(), false, false,
406 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
408 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
409 const TargetLowering &TLI) {
410 SDValue Chain = ST->getChain();
411 SDValue Ptr = ST->getBasePtr();
412 SDValue Val = ST->getValue();
413 EVT VT = Val.getValueType();
414 int Alignment = ST->getAlignment();
415 DebugLoc dl = ST->getDebugLoc();
416 if (ST->getMemoryVT().isFloatingPoint() ||
417 ST->getMemoryVT().isVector()) {
418 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
419 if (TLI.isTypeLegal(intVT)) {
420 // Expand to a bitconvert of the value to the integer type of the
421 // same size, then a (misaligned) int store.
422 // FIXME: Does not handle truncating floating point stores!
423 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
424 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
425 ST->isVolatile(), ST->isNonTemporal(), Alignment);
427 // Do a (aligned) store to a stack slot, then copy from the stack slot
428 // to the final destination using (unaligned) integer loads and stores.
429 EVT StoredVT = ST->getMemoryVT();
431 TLI.getRegisterType(*DAG.getContext(),
432 EVT::getIntegerVT(*DAG.getContext(),
433 StoredVT.getSizeInBits()));
434 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
435 unsigned RegBytes = RegVT.getSizeInBits() / 8;
436 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
438 // Make sure the stack slot is also aligned for the register type.
439 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
441 // Perform the original store, only redirected to the stack slot.
442 SDValue Store = DAG.getTruncStore(Chain, dl,
443 Val, StackPtr, MachinePointerInfo(),
444 StoredVT, false, false, 0);
445 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
446 SmallVector<SDValue, 8> Stores;
449 // Do all but one copies using the full register width.
450 for (unsigned i = 1; i < NumRegs; i++) {
451 // Load one integer register's worth from the stack slot.
452 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
453 MachinePointerInfo(),
455 // Store it to the final location. Remember the store.
456 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
457 ST->getPointerInfo().getWithOffset(Offset),
458 ST->isVolatile(), ST->isNonTemporal(),
459 MinAlign(ST->getAlignment(), Offset)));
460 // Increment the pointers.
462 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
464 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
467 // The last store may be partial. Do a truncating store. On big-endian
468 // machines this requires an extending load from the stack slot to ensure
469 // that the bits are in the right place.
470 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
471 8 * (StoredBytes - Offset));
473 // Load from the stack slot.
474 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
475 MachinePointerInfo(),
476 MemVT, false, false, 0);
478 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
480 .getWithOffset(Offset),
481 MemVT, ST->isVolatile(),
483 MinAlign(ST->getAlignment(), Offset)));
484 // The order of the stores doesn't matter - say it with a TokenFactor.
485 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
489 assert(ST->getMemoryVT().isInteger() &&
490 !ST->getMemoryVT().isVector() &&
491 "Unaligned store of unknown type.");
492 // Get the half-size VT
493 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
494 int NumBits = NewStoredVT.getSizeInBits();
495 int IncrementSize = NumBits / 8;
497 // Divide the stored value in two parts.
498 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
500 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
502 // Store the two parts
503 SDValue Store1, Store2;
504 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
505 ST->getPointerInfo(), NewStoredVT,
506 ST->isVolatile(), ST->isNonTemporal(), Alignment);
507 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
508 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
509 Alignment = MinAlign(Alignment, IncrementSize);
510 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
511 ST->getPointerInfo().getWithOffset(IncrementSize),
512 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
515 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
518 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
520 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
521 const TargetLowering &TLI) {
522 SDValue Chain = LD->getChain();
523 SDValue Ptr = LD->getBasePtr();
524 EVT VT = LD->getValueType(0);
525 EVT LoadedVT = LD->getMemoryVT();
526 DebugLoc dl = LD->getDebugLoc();
527 if (VT.isFloatingPoint() || VT.isVector()) {
528 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
529 if (TLI.isTypeLegal(intVT)) {
530 // Expand to a (misaligned) integer load of the same size,
531 // then bitconvert to floating point or vector.
532 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
534 LD->isNonTemporal(), LD->getAlignment());
535 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
536 if (VT.isFloatingPoint() && LoadedVT != VT)
537 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
539 SDValue Ops[] = { Result, Chain };
540 return DAG.getMergeValues(Ops, 2, dl);
543 // Copy the value to a (aligned) stack slot using (unaligned) integer
544 // loads and stores, then do a (aligned) load from the stack slot.
545 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
546 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
547 unsigned RegBytes = RegVT.getSizeInBits() / 8;
548 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
550 // Make sure the stack slot is also aligned for the register type.
551 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
553 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
554 SmallVector<SDValue, 8> Stores;
555 SDValue StackPtr = StackBase;
558 // Do all but one copies using the full register width.
559 for (unsigned i = 1; i < NumRegs; i++) {
560 // Load one integer register's worth from the original location.
561 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
562 LD->getPointerInfo().getWithOffset(Offset),
563 LD->isVolatile(), LD->isNonTemporal(),
564 MinAlign(LD->getAlignment(), Offset));
565 // Follow the load with a store to the stack slot. Remember the store.
566 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
567 MachinePointerInfo(), false, false, 0));
568 // Increment the pointers.
570 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
571 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
575 // The last copy may be partial. Do an extending load.
576 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
577 8 * (LoadedBytes - Offset));
578 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
579 LD->getPointerInfo().getWithOffset(Offset),
580 MemVT, LD->isVolatile(),
582 MinAlign(LD->getAlignment(), Offset));
583 // Follow the load with a store to the stack slot. Remember the store.
584 // On big-endian machines this requires a truncating store to ensure
585 // that the bits end up in the right place.
586 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
587 MachinePointerInfo(), MemVT,
590 // The order of the stores doesn't matter - say it with a TokenFactor.
591 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
594 // Finally, perform the original load only redirected to the stack slot.
595 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
596 MachinePointerInfo(), LoadedVT, false, false, 0);
598 // Callers expect a MERGE_VALUES node.
599 SDValue Ops[] = { Load, TF };
600 return DAG.getMergeValues(Ops, 2, dl);
602 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
603 "Unaligned load of unsupported type.");
605 // Compute the new VT that is half the size of the old one. This is an
607 unsigned NumBits = LoadedVT.getSizeInBits();
609 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
612 unsigned Alignment = LD->getAlignment();
613 unsigned IncrementSize = NumBits / 8;
614 ISD::LoadExtType HiExtType = LD->getExtensionType();
616 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
617 if (HiExtType == ISD::NON_EXTLOAD)
618 HiExtType = ISD::ZEXTLOAD;
620 // Load the value in two parts
622 if (TLI.isLittleEndian()) {
623 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getPointerInfo(),
624 NewLoadedVT, LD->isVolatile(),
625 LD->isNonTemporal(), Alignment);
626 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
627 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
628 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr,
629 LD->getPointerInfo().getWithOffset(IncrementSize),
630 NewLoadedVT, LD->isVolatile(),
631 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
633 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getPointerInfo(),
634 NewLoadedVT, LD->isVolatile(),
635 LD->isNonTemporal(), Alignment);
636 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
637 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
638 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr,
639 LD->getPointerInfo().getWithOffset(IncrementSize),
640 NewLoadedVT, LD->isVolatile(),
641 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
644 // aggregate the two parts
645 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
646 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
647 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
649 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
652 SDValue Ops[] = { Result, TF };
653 return DAG.getMergeValues(Ops, 2, dl);
656 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
657 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
658 /// is necessary to spill the vector being inserted into to memory, perform
659 /// the insert there, and then read the result back.
660 SDValue SelectionDAGLegalize::
661 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
667 // If the target doesn't support this, we have to spill the input vector
668 // to a temporary stack slot, update the element, then reload it. This is
669 // badness. We could also load the value into a vector register (either
670 // with a "move to register" or "extload into register" instruction, then
671 // permute it into place, if the idx is a constant and if the idx is
672 // supported by the target.
673 EVT VT = Tmp1.getValueType();
674 EVT EltVT = VT.getVectorElementType();
675 EVT IdxVT = Tmp3.getValueType();
676 EVT PtrVT = TLI.getPointerTy();
677 SDValue StackPtr = DAG.CreateStackTemporary(VT);
679 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
682 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
683 MachinePointerInfo::getFixedStack(SPFI),
686 // Truncate or zero extend offset to target pointer type.
687 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
688 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
689 // Add the offset to the index.
690 unsigned EltSize = EltVT.getSizeInBits()/8;
691 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
692 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
693 // Store the scalar value.
694 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
696 // Load the updated vector.
697 return DAG.getLoad(VT, dl, Ch, StackPtr,
698 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
702 SDValue SelectionDAGLegalize::
703 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
704 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
705 // SCALAR_TO_VECTOR requires that the type of the value being inserted
706 // match the element type of the vector being created, except for
707 // integers in which case the inserted value can be over width.
708 EVT EltVT = Vec.getValueType().getVectorElementType();
709 if (Val.getValueType() == EltVT ||
710 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
711 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
712 Vec.getValueType(), Val);
714 unsigned NumElts = Vec.getValueType().getVectorNumElements();
715 // We generate a shuffle of InVec and ScVec, so the shuffle mask
716 // should be 0,1,2,3,4,5... with the appropriate element replaced with
718 SmallVector<int, 8> ShufOps;
719 for (unsigned i = 0; i != NumElts; ++i)
720 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
722 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
726 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
729 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
730 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
731 // FIXME: We shouldn't do this for TargetConstantFP's.
732 // FIXME: move this to the DAG Combiner! Note that we can't regress due
733 // to phase ordering between legalized code and the dag combiner. This
734 // probably means that we need to integrate dag combiner and legalizer
736 // We generally can't do this one for long doubles.
737 SDValue Tmp1 = ST->getChain();
738 SDValue Tmp2 = ST->getBasePtr();
740 unsigned Alignment = ST->getAlignment();
741 bool isVolatile = ST->isVolatile();
742 bool isNonTemporal = ST->isNonTemporal();
743 DebugLoc dl = ST->getDebugLoc();
744 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
745 if (CFP->getValueType(0) == MVT::f32 &&
746 getTypeAction(MVT::i32) == Legal) {
747 Tmp3 = DAG.getConstant(CFP->getValueAPF().
748 bitcastToAPInt().zextOrTrunc(32),
750 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
751 isVolatile, isNonTemporal, Alignment);
754 if (CFP->getValueType(0) == MVT::f64) {
755 // If this target supports 64-bit registers, do a single 64-bit store.
756 if (getTypeAction(MVT::i64) == Legal) {
757 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
758 zextOrTrunc(64), MVT::i64);
759 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
760 isVolatile, isNonTemporal, Alignment);
763 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
764 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
765 // stores. If the target supports neither 32- nor 64-bits, this
766 // xform is certainly not worth it.
767 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
768 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
769 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
770 if (TLI.isBigEndian()) std::swap(Lo, Hi);
772 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
773 isNonTemporal, Alignment);
774 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
775 DAG.getIntPtrConstant(4));
776 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
777 ST->getPointerInfo().getWithOffset(4),
778 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
780 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
787 /// LegalizeOp - We know that the specified value has a legal type, and
788 /// that its operands are legal. Now ensure that the operation itself
789 /// is legal, recursively ensuring that the operands' operations remain
791 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
792 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
795 SDNode *Node = Op.getNode();
796 DebugLoc dl = Node->getDebugLoc();
798 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
799 assert(getTypeAction(Node->getValueType(i)) == Legal &&
800 "Unexpected illegal type!");
802 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
803 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
804 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
805 "Unexpected illegal type!");
807 // Note that LegalizeOp may be reentered even from single-use nodes, which
808 // means that we always must cache transformed nodes.
809 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
810 if (I != LegalizedNodes.end()) return I->second;
812 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
814 bool isCustom = false;
816 // Figure out the correct action; the way to query this varies by opcode
817 TargetLowering::LegalizeAction Action;
818 bool SimpleFinishLegalizing = true;
819 switch (Node->getOpcode()) {
820 case ISD::INTRINSIC_W_CHAIN:
821 case ISD::INTRINSIC_WO_CHAIN:
822 case ISD::INTRINSIC_VOID:
825 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
827 case ISD::SINT_TO_FP:
828 case ISD::UINT_TO_FP:
829 case ISD::EXTRACT_VECTOR_ELT:
830 Action = TLI.getOperationAction(Node->getOpcode(),
831 Node->getOperand(0).getValueType());
833 case ISD::FP_ROUND_INREG:
834 case ISD::SIGN_EXTEND_INREG: {
835 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
836 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
842 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
843 Node->getOpcode() == ISD::SETCC ? 2 : 1;
844 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
845 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
846 ISD::CondCode CCCode =
847 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
848 Action = TLI.getCondCodeAction(CCCode, OpVT);
849 if (Action == TargetLowering::Legal) {
850 if (Node->getOpcode() == ISD::SELECT_CC)
851 Action = TLI.getOperationAction(Node->getOpcode(),
852 Node->getValueType(0));
854 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
860 // FIXME: Model these properly. LOAD and STORE are complicated, and
861 // STORE expects the unlegalized operand in some cases.
862 SimpleFinishLegalizing = false;
864 case ISD::CALLSEQ_START:
865 case ISD::CALLSEQ_END:
866 // FIXME: This shouldn't be necessary. These nodes have special properties
867 // dealing with the recursive nature of legalization. Removing this
868 // special case should be done as part of making LegalizeDAG non-recursive.
869 SimpleFinishLegalizing = false;
871 case ISD::EXTRACT_ELEMENT:
872 case ISD::FLT_ROUNDS_:
880 case ISD::MERGE_VALUES:
882 case ISD::FRAME_TO_ARGS_OFFSET:
883 case ISD::EH_SJLJ_SETJMP:
884 case ISD::EH_SJLJ_LONGJMP:
885 case ISD::EH_SJLJ_DISPATCHSETUP:
886 // These operations lie about being legal: when they claim to be legal,
887 // they should actually be expanded.
888 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
889 if (Action == TargetLowering::Legal)
890 Action = TargetLowering::Expand;
892 case ISD::TRAMPOLINE:
894 case ISD::RETURNADDR:
895 // These operations lie about being legal: when they claim to be legal,
896 // they should actually be custom-lowered.
897 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
898 if (Action == TargetLowering::Legal)
899 Action = TargetLowering::Custom;
901 case ISD::BUILD_VECTOR:
902 // A weird case: legalization for BUILD_VECTOR never legalizes the
904 // FIXME: This really sucks... changing it isn't semantically incorrect,
905 // but it massively pessimizes the code for floating-point BUILD_VECTORs
906 // because ConstantFP operands get legalized into constant pool loads
907 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
908 // though, because BUILD_VECTORS usually get lowered into other nodes
909 // which get legalized properly.
910 SimpleFinishLegalizing = false;
913 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
914 Action = TargetLowering::Legal;
916 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
921 if (SimpleFinishLegalizing) {
922 SmallVector<SDValue, 8> Ops, ResultVals;
923 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
924 Ops.push_back(LegalizeOp(Node->getOperand(i)));
925 switch (Node->getOpcode()) {
932 // Branches tweak the chain to include LastCALLSEQ_END
933 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
935 Ops[0] = LegalizeOp(Ops[0]);
936 LastCALLSEQ_END = DAG.getEntryNode();
943 // Legalizing shifts/rotates requires adjusting the shift amount
944 // to the appropriate width.
945 if (!Ops[1].getValueType().isVector())
946 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
951 // Legalizing shifts/rotates requires adjusting the shift amount
952 // to the appropriate width.
953 if (!Ops[2].getValueType().isVector())
954 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
958 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
961 case TargetLowering::Legal:
962 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
963 ResultVals.push_back(Result.getValue(i));
965 case TargetLowering::Custom:
966 // FIXME: The handling for custom lowering with multiple results is
968 Tmp1 = TLI.LowerOperation(Result, DAG);
969 if (Tmp1.getNode()) {
970 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
972 ResultVals.push_back(Tmp1);
974 ResultVals.push_back(Tmp1.getValue(i));
980 case TargetLowering::Expand:
981 ExpandNode(Result.getNode(), ResultVals);
983 case TargetLowering::Promote:
984 PromoteNode(Result.getNode(), ResultVals);
987 if (!ResultVals.empty()) {
988 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
989 if (ResultVals[i] != SDValue(Node, i))
990 ResultVals[i] = LegalizeOp(ResultVals[i]);
991 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
993 return ResultVals[Op.getResNo()];
997 switch (Node->getOpcode()) {
1004 assert(0 && "Do not know how to legalize this operator!");
1006 case ISD::BUILD_VECTOR:
1007 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1008 default: assert(0 && "This action is not supported yet!");
1009 case TargetLowering::Custom:
1010 Tmp3 = TLI.LowerOperation(Result, DAG);
1011 if (Tmp3.getNode()) {
1016 case TargetLowering::Expand:
1017 Result = ExpandBUILD_VECTOR(Result.getNode());
1021 case ISD::CALLSEQ_START: {
1022 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1024 // Recursively Legalize all of the inputs of the call end that do not lead
1025 // to this call start. This ensures that any libcalls that need be inserted
1026 // are inserted *before* the CALLSEQ_START.
1027 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1028 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1029 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1033 // Now that we have legalized all of the inputs (which may have inserted
1034 // libcalls), create the new CALLSEQ_START node.
1035 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1037 // Merge in the last call to ensure that this call starts after the last
1039 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1040 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1041 Tmp1, LastCALLSEQ_END);
1042 Tmp1 = LegalizeOp(Tmp1);
1045 // Do not try to legalize the target-specific arguments (#1+).
1046 if (Tmp1 != Node->getOperand(0)) {
1047 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1049 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1050 Ops.size()), Result.getResNo());
1053 // Remember that the CALLSEQ_START is legalized.
1054 AddLegalizedOperand(Op.getValue(0), Result);
1055 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1056 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1058 // Now that the callseq_start and all of the non-call nodes above this call
1059 // sequence have been legalized, legalize the call itself. During this
1060 // process, no libcalls can/will be inserted, guaranteeing that no calls
1062 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1063 // Note that we are selecting this call!
1064 LastCALLSEQ_END = SDValue(CallEnd, 0);
1065 IsLegalizingCall = true;
1067 // Legalize the call, starting from the CALLSEQ_END.
1068 LegalizeOp(LastCALLSEQ_END);
1069 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1072 case ISD::CALLSEQ_END:
1073 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1074 // will cause this node to be legalized as well as handling libcalls right.
1075 if (LastCALLSEQ_END.getNode() != Node) {
1076 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1077 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1078 assert(I != LegalizedNodes.end() &&
1079 "Legalizing the call start should have legalized this node!");
1083 // Otherwise, the call start has been legalized and everything is going
1084 // according to plan. Just legalize ourselves normally here.
1085 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1086 // Do not try to legalize the target-specific arguments (#1+), except for
1087 // an optional flag input.
1088 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1089 if (Tmp1 != Node->getOperand(0)) {
1090 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1092 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1093 &Ops[0], Ops.size()),
1097 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1098 if (Tmp1 != Node->getOperand(0) ||
1099 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1100 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1103 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1104 &Ops[0], Ops.size()),
1108 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1109 // This finishes up call legalization.
1110 IsLegalizingCall = false;
1112 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1113 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1114 if (Node->getNumValues() == 2)
1115 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1116 return Result.getValue(Op.getResNo());
1118 LoadSDNode *LD = cast<LoadSDNode>(Node);
1119 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1120 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1122 ISD::LoadExtType ExtType = LD->getExtensionType();
1123 if (ExtType == ISD::NON_EXTLOAD) {
1124 EVT VT = Node->getValueType(0);
1125 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1126 Tmp1, Tmp2, LD->getOffset()),
1128 Tmp3 = Result.getValue(0);
1129 Tmp4 = Result.getValue(1);
1131 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Legal:
1134 // If this is an unaligned load and the target doesn't support it,
1136 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1137 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1138 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1139 if (LD->getAlignment() < ABIAlignment){
1140 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1142 Tmp3 = Result.getOperand(0);
1143 Tmp4 = Result.getOperand(1);
1144 Tmp3 = LegalizeOp(Tmp3);
1145 Tmp4 = LegalizeOp(Tmp4);
1149 case TargetLowering::Custom:
1150 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1151 if (Tmp1.getNode()) {
1152 Tmp3 = LegalizeOp(Tmp1);
1153 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1156 case TargetLowering::Promote: {
1157 // Only promote a load of vector type to another.
1158 assert(VT.isVector() && "Cannot promote this load!");
1159 // Change base type to a different vector type.
1160 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1162 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1163 LD->isVolatile(), LD->isNonTemporal(),
1164 LD->getAlignment());
1165 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1166 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1170 // Since loads produce two values, make sure to remember that we
1171 // legalized both of them.
1172 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1173 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1174 return Op.getResNo() ? Tmp4 : Tmp3;
1177 EVT SrcVT = LD->getMemoryVT();
1178 unsigned SrcWidth = SrcVT.getSizeInBits();
1179 unsigned Alignment = LD->getAlignment();
1180 bool isVolatile = LD->isVolatile();
1181 bool isNonTemporal = LD->isNonTemporal();
1183 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1184 // Some targets pretend to have an i1 loading operation, and actually
1185 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1186 // bits are guaranteed to be zero; it helps the optimizers understand
1187 // that these bits are zero. It is also useful for EXTLOAD, since it
1188 // tells the optimizers that those bits are undefined. It would be
1189 // nice to have an effective generic way of getting these benefits...
1190 // Until such a way is found, don't insist on promoting i1 here.
1191 (SrcVT != MVT::i1 ||
1192 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1193 // Promote to a byte-sized load if not loading an integral number of
1194 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1195 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1196 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1199 // The extra bits are guaranteed to be zero, since we stored them that
1200 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1202 ISD::LoadExtType NewExtType =
1203 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1205 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
1206 Tmp1, Tmp2, LD->getPointerInfo(),
1207 NVT, isVolatile, isNonTemporal, Alignment);
1209 Ch = Result.getValue(1); // The chain.
1211 if (ExtType == ISD::SEXTLOAD)
1212 // Having the top bits zero doesn't help when sign extending.
1213 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1214 Result.getValueType(),
1215 Result, DAG.getValueType(SrcVT));
1216 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1217 // All the top bits are guaranteed to be zero - inform the optimizers.
1218 Result = DAG.getNode(ISD::AssertZext, dl,
1219 Result.getValueType(), Result,
1220 DAG.getValueType(SrcVT));
1222 Tmp1 = LegalizeOp(Result);
1223 Tmp2 = LegalizeOp(Ch);
1224 } else if (SrcWidth & (SrcWidth - 1)) {
1225 // If not loading a power-of-2 number of bits, expand as two loads.
1226 assert(!SrcVT.isVector() && "Unsupported extload!");
1227 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1228 assert(RoundWidth < SrcWidth);
1229 unsigned ExtraWidth = SrcWidth - RoundWidth;
1230 assert(ExtraWidth < RoundWidth);
1231 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1232 "Load size not an integral number of bytes!");
1233 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1234 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1236 unsigned IncrementSize;
1238 if (TLI.isLittleEndian()) {
1239 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1240 // Load the bottom RoundWidth bits.
1241 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
1243 LD->getPointerInfo(), RoundVT, isVolatile,
1244 isNonTemporal, Alignment);
1246 // Load the remaining ExtraWidth bits.
1247 IncrementSize = RoundWidth / 8;
1248 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1249 DAG.getIntPtrConstant(IncrementSize));
1250 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1251 LD->getPointerInfo().getWithOffset(IncrementSize),
1252 ExtraVT, isVolatile, isNonTemporal,
1253 MinAlign(Alignment, IncrementSize));
1255 // Build a factor node to remember that this load is independent of
1257 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1260 // Move the top bits to the right place.
1261 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1262 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1264 // Join the hi and lo parts.
1265 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1267 // Big endian - avoid unaligned loads.
1268 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1269 // Load the top RoundWidth bits.
1270 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1271 LD->getPointerInfo(), RoundVT, isVolatile,
1272 isNonTemporal, Alignment);
1274 // Load the remaining ExtraWidth bits.
1275 IncrementSize = RoundWidth / 8;
1276 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1277 DAG.getIntPtrConstant(IncrementSize));
1278 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1279 Node->getValueType(0), dl, Tmp1, Tmp2,
1280 LD->getPointerInfo().getWithOffset(IncrementSize),
1281 ExtraVT, isVolatile, isNonTemporal,
1282 MinAlign(Alignment, IncrementSize));
1284 // Build a factor node to remember that this load is independent of
1286 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1289 // Move the top bits to the right place.
1290 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1291 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1293 // Join the hi and lo parts.
1294 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1297 Tmp1 = LegalizeOp(Result);
1298 Tmp2 = LegalizeOp(Ch);
1300 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1301 default: assert(0 && "This action is not supported yet!");
1302 case TargetLowering::Custom:
1305 case TargetLowering::Legal:
1306 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1307 Tmp1, Tmp2, LD->getOffset()),
1309 Tmp1 = Result.getValue(0);
1310 Tmp2 = Result.getValue(1);
1313 Tmp3 = TLI.LowerOperation(Result, DAG);
1314 if (Tmp3.getNode()) {
1315 Tmp1 = LegalizeOp(Tmp3);
1316 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1319 // If this is an unaligned load and the target doesn't support it,
1321 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1323 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1324 unsigned ABIAlignment =
1325 TLI.getTargetData()->getABITypeAlignment(Ty);
1326 if (LD->getAlignment() < ABIAlignment){
1327 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1329 Tmp1 = Result.getOperand(0);
1330 Tmp2 = Result.getOperand(1);
1331 Tmp1 = LegalizeOp(Tmp1);
1332 Tmp2 = LegalizeOp(Tmp2);
1337 case TargetLowering::Expand:
1338 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1339 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1340 LD->getPointerInfo(),
1341 LD->isVolatile(), LD->isNonTemporal(),
1342 LD->getAlignment());
1346 ExtendOp = (SrcVT.isFloatingPoint() ?
1347 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1349 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1350 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1351 default: llvm_unreachable("Unexpected extend load type!");
1353 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1354 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1355 Tmp2 = LegalizeOp(Load.getValue(1));
1358 // FIXME: This does not work for vectors on most targets. Sign- and
1359 // zero-extend operations are currently folded into extending loads,
1360 // whether they are legal or not, and then we end up here without any
1361 // support for legalizing them.
1362 assert(ExtType != ISD::EXTLOAD &&
1363 "EXTLOAD should always be supported!");
1364 // Turn the unsupported load into an EXTLOAD followed by an explicit
1365 // zero/sign extend inreg.
1366 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
1367 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1368 LD->isVolatile(), LD->isNonTemporal(),
1369 LD->getAlignment());
1371 if (ExtType == ISD::SEXTLOAD)
1372 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1373 Result.getValueType(),
1374 Result, DAG.getValueType(SrcVT));
1376 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1377 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1378 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1383 // Since loads produce two values, make sure to remember that we legalized
1385 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1386 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1387 return Op.getResNo() ? Tmp2 : Tmp1;
1390 StoreSDNode *ST = cast<StoreSDNode>(Node);
1391 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1392 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1393 unsigned Alignment = ST->getAlignment();
1394 bool isVolatile = ST->isVolatile();
1395 bool isNonTemporal = ST->isNonTemporal();
1397 if (!ST->isTruncatingStore()) {
1398 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1399 Result = SDValue(OptStore, 0);
1404 Tmp3 = LegalizeOp(ST->getValue());
1405 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1410 EVT VT = Tmp3.getValueType();
1411 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1412 default: assert(0 && "This action is not supported yet!");
1413 case TargetLowering::Legal:
1414 // If this is an unaligned store and the target doesn't support it,
1416 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1417 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1418 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1419 if (ST->getAlignment() < ABIAlignment)
1420 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1424 case TargetLowering::Custom:
1425 Tmp1 = TLI.LowerOperation(Result, DAG);
1426 if (Tmp1.getNode()) Result = Tmp1;
1428 case TargetLowering::Promote:
1429 assert(VT.isVector() && "Unknown legal promote case!");
1430 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1431 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1432 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1433 ST->getPointerInfo(), isVolatile,
1434 isNonTemporal, Alignment);
1440 Tmp3 = LegalizeOp(ST->getValue());
1442 EVT StVT = ST->getMemoryVT();
1443 unsigned StWidth = StVT.getSizeInBits();
1445 if (StWidth != StVT.getStoreSizeInBits()) {
1446 // Promote to a byte-sized store with upper bits zero if not
1447 // storing an integral number of bytes. For example, promote
1448 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1449 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1450 StVT.getStoreSizeInBits());
1451 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1452 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1453 NVT, isVolatile, isNonTemporal, Alignment);
1454 } else if (StWidth & (StWidth - 1)) {
1455 // If not storing a power-of-2 number of bits, expand as two stores.
1456 assert(!StVT.isVector() && "Unsupported truncstore!");
1457 unsigned RoundWidth = 1 << Log2_32(StWidth);
1458 assert(RoundWidth < StWidth);
1459 unsigned ExtraWidth = StWidth - RoundWidth;
1460 assert(ExtraWidth < RoundWidth);
1461 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1462 "Store size not an integral number of bytes!");
1463 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1464 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1466 unsigned IncrementSize;
1468 if (TLI.isLittleEndian()) {
1469 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1470 // Store the bottom RoundWidth bits.
1471 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1473 isVolatile, isNonTemporal, Alignment);
1475 // Store the remaining ExtraWidth bits.
1476 IncrementSize = RoundWidth / 8;
1477 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1478 DAG.getIntPtrConstant(IncrementSize));
1479 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1480 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1481 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1482 ST->getPointerInfo().getWithOffset(IncrementSize),
1483 ExtraVT, isVolatile, isNonTemporal,
1484 MinAlign(Alignment, IncrementSize));
1486 // Big endian - avoid unaligned stores.
1487 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1488 // Store the top RoundWidth bits.
1489 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1490 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1491 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1492 RoundVT, isVolatile, isNonTemporal, Alignment);
1494 // Store the remaining ExtraWidth bits.
1495 IncrementSize = RoundWidth / 8;
1496 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1497 DAG.getIntPtrConstant(IncrementSize));
1498 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1499 ST->getPointerInfo().getWithOffset(IncrementSize),
1500 ExtraVT, isVolatile, isNonTemporal,
1501 MinAlign(Alignment, IncrementSize));
1504 // The order of the stores doesn't matter.
1505 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1507 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1508 Tmp2 != ST->getBasePtr())
1509 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1514 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1515 default: assert(0 && "This action is not supported yet!");
1516 case TargetLowering::Legal:
1517 // If this is an unaligned store and the target doesn't support it,
1519 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1520 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1521 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1522 if (ST->getAlignment() < ABIAlignment)
1523 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1527 case TargetLowering::Custom:
1528 Result = TLI.LowerOperation(Result, DAG);
1531 // TRUNCSTORE:i16 i32 -> STORE i16
1532 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1533 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1534 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1535 isVolatile, isNonTemporal, Alignment);
1543 assert(Result.getValueType() == Op.getValueType() &&
1544 "Bad legalization!");
1546 // Make sure that the generated code is itself legal.
1548 Result = LegalizeOp(Result);
1550 // Note that LegalizeOp may be reentered even from single-use nodes, which
1551 // means that we always must cache transformed nodes.
1552 AddLegalizedOperand(Op, Result);
1556 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1557 SDValue Vec = Op.getOperand(0);
1558 SDValue Idx = Op.getOperand(1);
1559 DebugLoc dl = Op.getDebugLoc();
1560 // Store the value to a temporary stack slot, then LOAD the returned part.
1561 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1562 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1563 MachinePointerInfo(), false, false, 0);
1565 // Add the offset to the index.
1567 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1568 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1569 DAG.getConstant(EltSize, Idx.getValueType()));
1571 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1572 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1574 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1576 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1578 if (Op.getValueType().isVector())
1579 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1581 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
1582 MachinePointerInfo(),
1583 Vec.getValueType().getVectorElementType(),
1587 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1588 // We can't handle this case efficiently. Allocate a sufficiently
1589 // aligned object on the stack, store each element into it, then load
1590 // the result as a vector.
1591 // Create the stack frame object.
1592 EVT VT = Node->getValueType(0);
1593 EVT EltVT = VT.getVectorElementType();
1594 DebugLoc dl = Node->getDebugLoc();
1595 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1596 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1597 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1599 // Emit a store of each element to the stack slot.
1600 SmallVector<SDValue, 8> Stores;
1601 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1602 // Store (in the right endianness) the elements to memory.
1603 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1604 // Ignore undef elements.
1605 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1607 unsigned Offset = TypeByteSize*i;
1609 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1610 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1612 // If the destination vector element type is narrower than the source
1613 // element type, only store the bits necessary.
1614 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1615 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1616 Node->getOperand(i), Idx,
1617 PtrInfo.getWithOffset(Offset),
1618 EltVT, false, false, 0));
1620 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1621 Node->getOperand(i), Idx,
1622 PtrInfo.getWithOffset(Offset),
1627 if (!Stores.empty()) // Not all undef elements?
1628 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1629 &Stores[0], Stores.size());
1631 StoreChain = DAG.getEntryNode();
1633 // Result is a load from the stack slot.
1634 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1637 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1638 DebugLoc dl = Node->getDebugLoc();
1639 SDValue Tmp1 = Node->getOperand(0);
1640 SDValue Tmp2 = Node->getOperand(1);
1642 // Get the sign bit of the RHS. First obtain a value that has the same
1643 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1645 EVT FloatVT = Tmp2.getValueType();
1646 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1647 if (isTypeLegal(IVT)) {
1648 // Convert to an integer with the same sign bit.
1649 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1651 // Store the float to memory, then load the sign part out as an integer.
1652 MVT LoadTy = TLI.getPointerTy();
1653 // First create a temporary that is aligned for both the load and store.
1654 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1655 // Then store the float to it.
1657 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1659 if (TLI.isBigEndian()) {
1660 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1661 // Load out a legal integer with the same sign bit as the float.
1662 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1664 } else { // Little endian
1665 SDValue LoadPtr = StackPtr;
1666 // The float may be wider than the integer we are going to load. Advance
1667 // the pointer so that the loaded integer will contain the sign bit.
1668 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1669 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1670 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1671 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1672 // Load a legal integer containing the sign bit.
1673 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1675 // Move the sign bit to the top bit of the loaded integer.
1676 unsigned BitShift = LoadTy.getSizeInBits() -
1677 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1678 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1680 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1681 DAG.getConstant(BitShift,TLI.getShiftAmountTy()));
1684 // Now get the sign bit proper, by seeing whether the value is negative.
1685 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1686 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1688 // Get the absolute value of the result.
1689 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1690 // Select between the nabs and abs value based on the sign bit of
1692 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1693 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1697 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1698 SmallVectorImpl<SDValue> &Results) {
1699 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1700 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1701 " not tell us which reg is the stack pointer!");
1702 DebugLoc dl = Node->getDebugLoc();
1703 EVT VT = Node->getValueType(0);
1704 SDValue Tmp1 = SDValue(Node, 0);
1705 SDValue Tmp2 = SDValue(Node, 1);
1706 SDValue Tmp3 = Node->getOperand(2);
1707 SDValue Chain = Tmp1.getOperand(0);
1709 // Chain the dynamic stack allocation so that it doesn't modify the stack
1710 // pointer when other instructions are using the stack.
1711 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1713 SDValue Size = Tmp2.getOperand(1);
1714 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1715 Chain = SP.getValue(1);
1716 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1717 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
1718 if (Align > StackAlign)
1719 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1720 DAG.getConstant(-(uint64_t)Align, VT));
1721 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1722 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1724 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1725 DAG.getIntPtrConstant(0, true), SDValue());
1727 Results.push_back(Tmp1);
1728 Results.push_back(Tmp2);
1731 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1732 /// condition code CC on the current target. This routine expands SETCC with
1733 /// illegal condition code into AND / OR of multiple SETCC values.
1734 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1735 SDValue &LHS, SDValue &RHS,
1738 EVT OpVT = LHS.getValueType();
1739 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1740 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1741 default: assert(0 && "Unknown condition code action!");
1742 case TargetLowering::Legal:
1745 case TargetLowering::Expand: {
1746 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1749 default: assert(0 && "Don't know how to expand this condition!");
1750 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1751 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1752 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1753 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1754 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1755 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1756 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1757 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1758 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1759 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1760 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1761 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1762 // FIXME: Implement more expansions.
1765 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1766 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1767 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1775 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1776 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1777 /// a load from the stack slot to DestVT, extending it if needed.
1778 /// The resultant code need not be legal.
1779 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1783 // Create the stack frame object.
1785 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1786 getTypeForEVT(*DAG.getContext()));
1787 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1789 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1790 int SPFI = StackPtrFI->getIndex();
1791 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1793 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1794 unsigned SlotSize = SlotVT.getSizeInBits();
1795 unsigned DestSize = DestVT.getSizeInBits();
1796 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1797 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1799 // Emit a store to the stack slot. Use a truncstore if the input value is
1800 // later than DestVT.
1803 if (SrcSize > SlotSize)
1804 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1805 PtrInfo, SlotVT, false, false, SrcAlign);
1807 assert(SrcSize == SlotSize && "Invalid store");
1808 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1809 PtrInfo, false, false, SrcAlign);
1812 // Result is a load from the stack slot.
1813 if (SlotSize == DestSize)
1814 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1815 false, false, DestAlign);
1817 assert(SlotSize < DestSize && "Unknown extension!");
1818 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr,
1819 PtrInfo, SlotVT, false, false, DestAlign);
1822 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1823 DebugLoc dl = Node->getDebugLoc();
1824 // Create a vector sized/aligned stack slot, store the value to element #0,
1825 // then load the whole vector back out.
1826 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1828 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1829 int SPFI = StackPtrFI->getIndex();
1831 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1833 MachinePointerInfo::getFixedStack(SPFI),
1834 Node->getValueType(0).getVectorElementType(),
1836 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1837 MachinePointerInfo::getFixedStack(SPFI),
1842 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1843 /// support the operation, but do support the resultant vector type.
1844 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1845 unsigned NumElems = Node->getNumOperands();
1846 SDValue Value1, Value2;
1847 DebugLoc dl = Node->getDebugLoc();
1848 EVT VT = Node->getValueType(0);
1849 EVT OpVT = Node->getOperand(0).getValueType();
1850 EVT EltVT = VT.getVectorElementType();
1852 // If the only non-undef value is the low element, turn this into a
1853 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1854 bool isOnlyLowElement = true;
1855 bool MoreThanTwoValues = false;
1856 bool isConstant = true;
1857 for (unsigned i = 0; i < NumElems; ++i) {
1858 SDValue V = Node->getOperand(i);
1859 if (V.getOpcode() == ISD::UNDEF)
1862 isOnlyLowElement = false;
1863 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1866 if (!Value1.getNode()) {
1868 } else if (!Value2.getNode()) {
1871 } else if (V != Value1 && V != Value2) {
1872 MoreThanTwoValues = true;
1876 if (!Value1.getNode())
1877 return DAG.getUNDEF(VT);
1879 if (isOnlyLowElement)
1880 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1882 // If all elements are constants, create a load from the constant pool.
1884 std::vector<Constant*> CV;
1885 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1886 if (ConstantFPSDNode *V =
1887 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1888 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1889 } else if (ConstantSDNode *V =
1890 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1892 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1894 // If OpVT and EltVT don't match, EltVT is not legal and the
1895 // element values have been promoted/truncated earlier. Undo this;
1896 // we don't want a v16i8 to become a v16i32 for example.
1897 const ConstantInt *CI = V->getConstantIntValue();
1898 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1899 CI->getZExtValue()));
1902 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1903 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1904 CV.push_back(UndefValue::get(OpNTy));
1907 Constant *CP = ConstantVector::get(CV);
1908 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1909 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1910 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1911 MachinePointerInfo::getConstantPool(),
1912 false, false, Alignment);
1915 if (!MoreThanTwoValues) {
1916 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1917 for (unsigned i = 0; i < NumElems; ++i) {
1918 SDValue V = Node->getOperand(i);
1919 if (V.getOpcode() == ISD::UNDEF)
1921 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1923 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1924 // Get the splatted value into the low element of a vector register.
1925 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1927 if (Value2.getNode())
1928 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1930 Vec2 = DAG.getUNDEF(VT);
1932 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1933 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1937 // Otherwise, we can't handle this case efficiently.
1938 return ExpandVectorBuildThroughStack(Node);
1941 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1942 // does not fit into a register, return the lo part and set the hi part to the
1943 // by-reg argument. If it does fit into a single register, return the result
1944 // and leave the Hi part unset.
1945 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1947 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1948 // The input chain to this libcall is the entry node of the function.
1949 // Legalizing the call will automatically add the previous call to the
1951 SDValue InChain = DAG.getEntryNode();
1953 TargetLowering::ArgListTy Args;
1954 TargetLowering::ArgListEntry Entry;
1955 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1956 EVT ArgVT = Node->getOperand(i).getValueType();
1957 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1958 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1959 Entry.isSExt = isSigned;
1960 Entry.isZExt = !isSigned;
1961 Args.push_back(Entry);
1963 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1964 TLI.getPointerTy());
1966 // Splice the libcall in wherever FindInputOutputChains tells us to.
1967 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1969 // isTailCall may be true since the callee does not reference caller stack
1970 // frame. Check if it's in the right position.
1971 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
1972 std::pair<SDValue, SDValue> CallInfo =
1973 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1974 0, TLI.getLibcallCallingConv(LC), isTailCall,
1975 /*isReturnValueUsed=*/true,
1976 Callee, Args, DAG, Node->getDebugLoc());
1978 if (!CallInfo.second.getNode())
1979 // It's a tailcall, return the chain (which is the DAG root).
1980 return DAG.getRoot();
1982 // Legalize the call sequence, starting with the chain. This will advance
1983 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1984 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1985 LegalizeOp(CallInfo.second);
1986 return CallInfo.first;
1989 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1990 // ExpandLibCall except that the first operand is the in-chain.
1991 std::pair<SDValue, SDValue>
1992 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1995 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1996 SDValue InChain = Node->getOperand(0);
1998 TargetLowering::ArgListTy Args;
1999 TargetLowering::ArgListEntry Entry;
2000 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2001 EVT ArgVT = Node->getOperand(i).getValueType();
2002 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2003 Entry.Node = Node->getOperand(i);
2005 Entry.isSExt = isSigned;
2006 Entry.isZExt = !isSigned;
2007 Args.push_back(Entry);
2009 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2010 TLI.getPointerTy());
2012 // Splice the libcall in wherever FindInputOutputChains tells us to.
2013 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2014 std::pair<SDValue, SDValue> CallInfo =
2015 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2016 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2017 /*isReturnValueUsed=*/true,
2018 Callee, Args, DAG, Node->getDebugLoc());
2020 // Legalize the call sequence, starting with the chain. This will advance
2021 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2022 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2023 LegalizeOp(CallInfo.second);
2027 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2028 RTLIB::Libcall Call_F32,
2029 RTLIB::Libcall Call_F64,
2030 RTLIB::Libcall Call_F80,
2031 RTLIB::Libcall Call_PPCF128) {
2033 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2034 default: assert(0 && "Unexpected request for libcall!");
2035 case MVT::f32: LC = Call_F32; break;
2036 case MVT::f64: LC = Call_F64; break;
2037 case MVT::f80: LC = Call_F80; break;
2038 case MVT::ppcf128: LC = Call_PPCF128; break;
2040 return ExpandLibCall(LC, Node, false);
2043 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2044 RTLIB::Libcall Call_I8,
2045 RTLIB::Libcall Call_I16,
2046 RTLIB::Libcall Call_I32,
2047 RTLIB::Libcall Call_I64,
2048 RTLIB::Libcall Call_I128) {
2050 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2051 default: assert(0 && "Unexpected request for libcall!");
2052 case MVT::i8: LC = Call_I8; break;
2053 case MVT::i16: LC = Call_I16; break;
2054 case MVT::i32: LC = Call_I32; break;
2055 case MVT::i64: LC = Call_I64; break;
2056 case MVT::i128: LC = Call_I128; break;
2058 return ExpandLibCall(LC, Node, isSigned);
2061 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2062 /// INT_TO_FP operation of the specified operand when the target requests that
2063 /// we expand it. At this point, we know that the result and operand types are
2064 /// legal for the target.
2065 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2069 if (Op0.getValueType() == MVT::i32) {
2070 // simple 32-bit [signed|unsigned] integer to float/double expansion
2072 // Get the stack frame index of a 8 byte buffer.
2073 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2075 // word offset constant for Hi/Lo address computation
2076 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2077 // set up Hi and Lo (into buffer) address based on endian
2078 SDValue Hi = StackSlot;
2079 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2080 TLI.getPointerTy(), StackSlot, WordOff);
2081 if (TLI.isLittleEndian())
2084 // if signed map to unsigned space
2087 // constant used to invert sign bit (signed to unsigned mapping)
2088 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2089 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2093 // store the lo of the constructed double - based on integer input
2094 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2095 Op0Mapped, Lo, MachinePointerInfo(),
2097 // initial hi portion of constructed double
2098 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2099 // store the hi of the constructed double - biased exponent
2100 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2101 MachinePointerInfo(),
2103 // load the constructed double
2104 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2105 MachinePointerInfo(), false, false, 0);
2106 // FP constant to bias correct the final result
2107 SDValue Bias = DAG.getConstantFP(isSigned ?
2108 BitsToDouble(0x4330000080000000ULL) :
2109 BitsToDouble(0x4330000000000000ULL),
2111 // subtract the bias
2112 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2115 // handle final rounding
2116 if (DestVT == MVT::f64) {
2119 } else if (DestVT.bitsLT(MVT::f64)) {
2120 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2121 DAG.getIntPtrConstant(0));
2122 } else if (DestVT.bitsGT(MVT::f64)) {
2123 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2127 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2128 // Code below here assumes !isSigned without checking again.
2130 // Implementation of unsigned i64 to f64 following the algorithm in
2131 // __floatundidf in compiler_rt. This implementation has the advantage
2132 // of performing rounding correctly, both in the default rounding mode
2133 // and in all alternate rounding modes.
2134 // TODO: Generalize this for use with other types.
2135 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2137 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2138 SDValue TwoP84PlusTwoP52 =
2139 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2141 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2143 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2144 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2145 DAG.getConstant(32, MVT::i64));
2146 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2147 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2148 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2149 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2150 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2152 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2155 // Implementation of unsigned i64 to f32.
2156 // TODO: Generalize this for use with other types.
2157 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2158 // For unsigned conversions, convert them to signed conversions using the
2159 // algorithm from the x86_64 __floatundidf in compiler_rt.
2161 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2163 SDValue ShiftConst = DAG.getConstant(1, TLI.getShiftAmountTy());
2164 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2165 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2166 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2167 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2169 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2170 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2172 // TODO: This really should be implemented using a branch rather than a
2173 // select. We happen to get lucky and machinesink does the right
2174 // thing most of the time. This would be a good candidate for a
2175 //pseudo-op, or, even better, for whole-function isel.
2176 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2177 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2178 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2181 // Otherwise, implement the fully general conversion.
2182 EVT SHVT = TLI.getShiftAmountTy();
2184 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2185 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2186 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2187 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2188 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2189 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2190 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2191 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2192 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2193 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2194 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2196 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2198 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2199 DAG.getConstant(32, SHVT));
2200 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2201 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2203 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2204 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2205 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2206 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2207 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2208 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2209 DAG.getIntPtrConstant(0));
2212 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2214 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2215 Op0, DAG.getConstant(0, Op0.getValueType()),
2217 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2218 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2219 SignSet, Four, Zero);
2221 // If the sign bit of the integer is set, the large number will be treated
2222 // as a negative number. To counteract this, the dynamic code adds an
2223 // offset depending on the data type.
2225 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2226 default: assert(0 && "Unsupported integer type!");
2227 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2228 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2229 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2230 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2232 if (TLI.isLittleEndian()) FF <<= 32;
2233 Constant *FudgeFactor = ConstantInt::get(
2234 Type::getInt64Ty(*DAG.getContext()), FF);
2236 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2237 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2238 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2239 Alignment = std::min(Alignment, 4u);
2241 if (DestVT == MVT::f32)
2242 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2243 MachinePointerInfo::getConstantPool(),
2244 false, false, Alignment);
2247 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
2248 DAG.getEntryNode(), CPIdx,
2249 MachinePointerInfo::getConstantPool(),
2250 MVT::f32, false, false, Alignment));
2253 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2256 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2257 /// *INT_TO_FP operation of the specified operand when the target requests that
2258 /// we promote it. At this point, we know that the result and operand types are
2259 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2260 /// operation that takes a larger input.
2261 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2265 // First step, figure out the appropriate *INT_TO_FP operation to use.
2266 EVT NewInTy = LegalOp.getValueType();
2268 unsigned OpToUse = 0;
2270 // Scan for the appropriate larger type to use.
2272 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2273 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2275 // If the target supports SINT_TO_FP of this type, use it.
2276 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2277 OpToUse = ISD::SINT_TO_FP;
2280 if (isSigned) continue;
2282 // If the target supports UINT_TO_FP of this type, use it.
2283 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2284 OpToUse = ISD::UINT_TO_FP;
2288 // Otherwise, try a larger type.
2291 // Okay, we found the operation and type to use. Zero extend our input to the
2292 // desired type then run the operation on it.
2293 return DAG.getNode(OpToUse, dl, DestVT,
2294 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2295 dl, NewInTy, LegalOp));
2298 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2299 /// FP_TO_*INT operation of the specified operand when the target requests that
2300 /// we promote it. At this point, we know that the result and operand types are
2301 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2302 /// operation that returns a larger result.
2303 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2307 // First step, figure out the appropriate FP_TO*INT operation to use.
2308 EVT NewOutTy = DestVT;
2310 unsigned OpToUse = 0;
2312 // Scan for the appropriate larger type to use.
2314 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2315 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2317 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2318 OpToUse = ISD::FP_TO_SINT;
2322 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2323 OpToUse = ISD::FP_TO_UINT;
2327 // Otherwise, try a larger type.
2331 // Okay, we found the operation and type to use.
2332 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2334 // Truncate the result of the extended FP_TO_*INT operation to the desired
2336 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2339 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2341 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2342 EVT VT = Op.getValueType();
2343 EVT SHVT = TLI.getShiftAmountTy();
2344 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2345 switch (VT.getSimpleVT().SimpleTy) {
2346 default: assert(0 && "Unhandled Expand type in BSWAP!");
2348 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2349 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2350 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2352 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2353 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2354 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2355 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2356 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2357 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2358 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2359 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2360 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2362 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2363 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2364 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2365 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2366 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2367 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2368 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2369 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2370 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2371 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2372 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2373 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2374 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2375 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2376 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2377 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2378 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2379 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2380 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2381 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2382 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2386 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2388 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2391 default: assert(0 && "Cannot expand this yet!");
2393 static const uint64_t mask[6] = {
2394 0x5555555555555555ULL, 0x3333333333333333ULL,
2395 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2396 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2398 EVT VT = Op.getValueType();
2399 EVT ShVT = TLI.getShiftAmountTy();
2400 unsigned len = VT.getSizeInBits();
2401 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2402 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2403 unsigned EltSize = VT.isVector() ?
2404 VT.getVectorElementType().getSizeInBits() : len;
2405 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2406 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2407 Op = DAG.getNode(ISD::ADD, dl, VT,
2408 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2409 DAG.getNode(ISD::AND, dl, VT,
2410 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2416 // for now, we do this:
2417 // x = x | (x >> 1);
2418 // x = x | (x >> 2);
2420 // x = x | (x >>16);
2421 // x = x | (x >>32); // for 64-bit input
2422 // return popcount(~x);
2424 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2425 EVT VT = Op.getValueType();
2426 EVT ShVT = TLI.getShiftAmountTy();
2427 unsigned len = VT.getSizeInBits();
2428 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2429 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2430 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2431 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2433 Op = DAG.getNOT(dl, Op, VT);
2434 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2437 // for now, we use: { return popcount(~x & (x - 1)); }
2438 // unless the target has ctlz but not ctpop, in which case we use:
2439 // { return 32 - nlz(~x & (x-1)); }
2440 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2441 EVT VT = Op.getValueType();
2442 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2443 DAG.getNOT(dl, Op, VT),
2444 DAG.getNode(ISD::SUB, dl, VT, Op,
2445 DAG.getConstant(1, VT)));
2446 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2447 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2448 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2449 return DAG.getNode(ISD::SUB, dl, VT,
2450 DAG.getConstant(VT.getSizeInBits(), VT),
2451 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2452 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2457 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2458 unsigned Opc = Node->getOpcode();
2459 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2464 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2466 case ISD::ATOMIC_SWAP:
2467 switch (VT.SimpleTy) {
2468 default: llvm_unreachable("Unexpected value type for atomic!");
2469 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2470 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2471 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2472 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2475 case ISD::ATOMIC_CMP_SWAP:
2476 switch (VT.SimpleTy) {
2477 default: llvm_unreachable("Unexpected value type for atomic!");
2478 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2479 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2480 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2481 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2484 case ISD::ATOMIC_LOAD_ADD:
2485 switch (VT.SimpleTy) {
2486 default: llvm_unreachable("Unexpected value type for atomic!");
2487 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2488 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2489 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2490 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2493 case ISD::ATOMIC_LOAD_SUB:
2494 switch (VT.SimpleTy) {
2495 default: llvm_unreachable("Unexpected value type for atomic!");
2496 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2497 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2498 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2499 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2502 case ISD::ATOMIC_LOAD_AND:
2503 switch (VT.SimpleTy) {
2504 default: llvm_unreachable("Unexpected value type for atomic!");
2505 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2506 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2507 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2508 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2511 case ISD::ATOMIC_LOAD_OR:
2512 switch (VT.SimpleTy) {
2513 default: llvm_unreachable("Unexpected value type for atomic!");
2514 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2515 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2516 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2517 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2520 case ISD::ATOMIC_LOAD_XOR:
2521 switch (VT.SimpleTy) {
2522 default: llvm_unreachable("Unexpected value type for atomic!");
2523 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2524 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2525 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2526 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2529 case ISD::ATOMIC_LOAD_NAND:
2530 switch (VT.SimpleTy) {
2531 default: llvm_unreachable("Unexpected value type for atomic!");
2532 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2533 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2534 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2535 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2540 return ExpandChainLibCall(LC, Node, false);
2543 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2544 SmallVectorImpl<SDValue> &Results) {
2545 DebugLoc dl = Node->getDebugLoc();
2546 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2547 switch (Node->getOpcode()) {
2551 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2552 Results.push_back(Tmp1);
2555 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2557 case ISD::FRAMEADDR:
2558 case ISD::RETURNADDR:
2559 case ISD::FRAME_TO_ARGS_OFFSET:
2560 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2562 case ISD::FLT_ROUNDS_:
2563 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2565 case ISD::EH_RETURN:
2569 case ISD::EH_SJLJ_LONGJMP:
2570 case ISD::EH_SJLJ_DISPATCHSETUP:
2571 // If the target didn't expand these, there's nothing to do, so just
2572 // preserve the chain and be done.
2573 Results.push_back(Node->getOperand(0));
2575 case ISD::EH_SJLJ_SETJMP:
2576 // If the target didn't expand this, just return 'zero' and preserve the
2578 Results.push_back(DAG.getConstant(0, MVT::i32));
2579 Results.push_back(Node->getOperand(0));
2581 case ISD::MEMBARRIER: {
2582 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2583 TargetLowering::ArgListTy Args;
2584 std::pair<SDValue, SDValue> CallResult =
2585 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2586 false, false, false, false, 0, CallingConv::C,
2587 /*isTailCall=*/false,
2588 /*isReturnValueUsed=*/true,
2589 DAG.getExternalSymbol("__sync_synchronize",
2590 TLI.getPointerTy()),
2592 Results.push_back(CallResult.second);
2595 // By default, atomic intrinsics are marked Legal and lowered. Targets
2596 // which don't support them directly, however, may want libcalls, in which
2597 // case they mark them Expand, and we get here.
2598 // FIXME: Unimplemented for now. Add libcalls.
2599 case ISD::ATOMIC_SWAP:
2600 case ISD::ATOMIC_LOAD_ADD:
2601 case ISD::ATOMIC_LOAD_SUB:
2602 case ISD::ATOMIC_LOAD_AND:
2603 case ISD::ATOMIC_LOAD_OR:
2604 case ISD::ATOMIC_LOAD_XOR:
2605 case ISD::ATOMIC_LOAD_NAND:
2606 case ISD::ATOMIC_LOAD_MIN:
2607 case ISD::ATOMIC_LOAD_MAX:
2608 case ISD::ATOMIC_LOAD_UMIN:
2609 case ISD::ATOMIC_LOAD_UMAX:
2610 case ISD::ATOMIC_CMP_SWAP: {
2611 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2612 Results.push_back(Tmp.first);
2613 Results.push_back(Tmp.second);
2616 case ISD::DYNAMIC_STACKALLOC:
2617 ExpandDYNAMIC_STACKALLOC(Node, Results);
2619 case ISD::MERGE_VALUES:
2620 for (unsigned i = 0; i < Node->getNumValues(); i++)
2621 Results.push_back(Node->getOperand(i));
2624 EVT VT = Node->getValueType(0);
2626 Results.push_back(DAG.getConstant(0, VT));
2628 assert(VT.isFloatingPoint() && "Unknown value type!");
2629 Results.push_back(DAG.getConstantFP(0, VT));
2634 // If this operation is not supported, lower it to 'abort()' call
2635 TargetLowering::ArgListTy Args;
2636 std::pair<SDValue, SDValue> CallResult =
2637 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2638 false, false, false, false, 0, CallingConv::C,
2639 /*isTailCall=*/false,
2640 /*isReturnValueUsed=*/true,
2641 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2643 Results.push_back(CallResult.second);
2648 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2649 Node->getValueType(0), dl);
2650 Results.push_back(Tmp1);
2652 case ISD::FP_EXTEND:
2653 Tmp1 = EmitStackConvert(Node->getOperand(0),
2654 Node->getOperand(0).getValueType(),
2655 Node->getValueType(0), dl);
2656 Results.push_back(Tmp1);
2658 case ISD::SIGN_EXTEND_INREG: {
2659 // NOTE: we could fall back on load/store here too for targets without
2660 // SAR. However, it is doubtful that any exist.
2661 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2662 EVT VT = Node->getValueType(0);
2663 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2666 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2667 ExtraVT.getScalarType().getSizeInBits();
2668 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2669 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2670 Node->getOperand(0), ShiftCst);
2671 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2672 Results.push_back(Tmp1);
2675 case ISD::FP_ROUND_INREG: {
2676 // The only way we can lower this is to turn it into a TRUNCSTORE,
2677 // EXTLOAD pair, targetting a temporary location (a stack slot).
2679 // NOTE: there is a choice here between constantly creating new stack
2680 // slots and always reusing the same one. We currently always create
2681 // new ones, as reuse may inhibit scheduling.
2682 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2683 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2684 Node->getValueType(0), dl);
2685 Results.push_back(Tmp1);
2688 case ISD::SINT_TO_FP:
2689 case ISD::UINT_TO_FP:
2690 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2691 Node->getOperand(0), Node->getValueType(0), dl);
2692 Results.push_back(Tmp1);
2694 case ISD::FP_TO_UINT: {
2695 SDValue True, False;
2696 EVT VT = Node->getOperand(0).getValueType();
2697 EVT NVT = Node->getValueType(0);
2698 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
2699 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2700 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2701 Tmp1 = DAG.getConstantFP(apf, VT);
2702 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2703 Node->getOperand(0),
2705 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2706 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2707 DAG.getNode(ISD::FSUB, dl, VT,
2708 Node->getOperand(0), Tmp1));
2709 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2710 DAG.getConstant(x, NVT));
2711 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2712 Results.push_back(Tmp1);
2716 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2717 EVT VT = Node->getValueType(0);
2718 Tmp1 = Node->getOperand(0);
2719 Tmp2 = Node->getOperand(1);
2720 unsigned Align = Node->getConstantOperandVal(3);
2722 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2723 MachinePointerInfo(V), false, false, 0);
2724 SDValue VAList = VAListLoad;
2726 if (Align > TLI.getMinStackArgumentAlignment()) {
2727 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2729 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2730 DAG.getConstant(Align - 1,
2731 TLI.getPointerTy()));
2733 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2734 DAG.getConstant(-(int64_t)Align,
2735 TLI.getPointerTy()));
2738 // Increment the pointer, VAList, to the next vaarg
2739 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2740 DAG.getConstant(TLI.getTargetData()->
2741 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2742 TLI.getPointerTy()));
2743 // Store the incremented VAList to the legalized pointer
2744 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2745 MachinePointerInfo(V), false, false, 0);
2746 // Load the actual argument out of the pointer VAList
2747 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2749 Results.push_back(Results[0].getValue(1));
2753 // This defaults to loading a pointer from the input and storing it to the
2754 // output, returning the chain.
2755 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2756 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2757 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2758 Node->getOperand(2), MachinePointerInfo(VS),
2760 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2761 MachinePointerInfo(VD), false, false, 0);
2762 Results.push_back(Tmp1);
2765 case ISD::EXTRACT_VECTOR_ELT:
2766 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2767 // This must be an access of the only element. Return it.
2768 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2769 Node->getOperand(0));
2771 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2772 Results.push_back(Tmp1);
2774 case ISD::EXTRACT_SUBVECTOR:
2775 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2777 case ISD::CONCAT_VECTORS: {
2778 Results.push_back(ExpandVectorBuildThroughStack(Node));
2781 case ISD::SCALAR_TO_VECTOR:
2782 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2784 case ISD::INSERT_VECTOR_ELT:
2785 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2786 Node->getOperand(1),
2787 Node->getOperand(2), dl));
2789 case ISD::VECTOR_SHUFFLE: {
2790 SmallVector<int, 8> Mask;
2791 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2793 EVT VT = Node->getValueType(0);
2794 EVT EltVT = VT.getVectorElementType();
2795 if (getTypeAction(EltVT) == Promote)
2796 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2797 unsigned NumElems = VT.getVectorNumElements();
2798 SmallVector<SDValue, 8> Ops;
2799 for (unsigned i = 0; i != NumElems; ++i) {
2801 Ops.push_back(DAG.getUNDEF(EltVT));
2804 unsigned Idx = Mask[i];
2806 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2807 Node->getOperand(0),
2808 DAG.getIntPtrConstant(Idx)));
2810 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2811 Node->getOperand(1),
2812 DAG.getIntPtrConstant(Idx - NumElems)));
2814 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2815 Results.push_back(Tmp1);
2818 case ISD::EXTRACT_ELEMENT: {
2819 EVT OpTy = Node->getOperand(0).getValueType();
2820 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2822 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2823 DAG.getConstant(OpTy.getSizeInBits()/2,
2824 TLI.getShiftAmountTy()));
2825 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2828 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2829 Node->getOperand(0));
2831 Results.push_back(Tmp1);
2834 case ISD::STACKSAVE:
2835 // Expand to CopyFromReg if the target set
2836 // StackPointerRegisterToSaveRestore.
2837 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2838 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2839 Node->getValueType(0)));
2840 Results.push_back(Results[0].getValue(1));
2842 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2843 Results.push_back(Node->getOperand(0));
2846 case ISD::STACKRESTORE:
2847 // Expand to CopyToReg if the target set
2848 // StackPointerRegisterToSaveRestore.
2849 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2850 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2851 Node->getOperand(1)));
2853 Results.push_back(Node->getOperand(0));
2856 case ISD::FCOPYSIGN:
2857 Results.push_back(ExpandFCOPYSIGN(Node));
2860 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2861 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2862 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2863 Node->getOperand(0));
2864 Results.push_back(Tmp1);
2867 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2868 EVT VT = Node->getValueType(0);
2869 Tmp1 = Node->getOperand(0);
2870 Tmp2 = DAG.getConstantFP(0.0, VT);
2871 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2872 Tmp1, Tmp2, ISD::SETUGT);
2873 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2874 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2875 Results.push_back(Tmp1);
2879 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2880 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2883 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2884 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2887 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2888 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2891 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2892 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2895 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2896 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2899 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2900 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2903 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2904 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2907 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2908 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2911 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2912 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2915 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2916 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2919 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2920 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2923 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2924 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2926 case ISD::FNEARBYINT:
2927 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2928 RTLIB::NEARBYINT_F64,
2929 RTLIB::NEARBYINT_F80,
2930 RTLIB::NEARBYINT_PPCF128));
2933 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2934 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2937 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2938 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2941 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2942 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2945 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2946 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2948 case ISD::FP16_TO_FP32:
2949 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
2951 case ISD::FP32_TO_FP16:
2952 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
2954 case ISD::ConstantFP: {
2955 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2956 // Check to see if this FP immediate is already legal.
2957 // If this is a legal constant, turn it into a TargetConstantFP node.
2958 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2959 Results.push_back(SDValue(Node, 0));
2961 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2964 case ISD::EHSELECTION: {
2965 unsigned Reg = TLI.getExceptionSelectorRegister();
2966 assert(Reg && "Can't expand to unknown register!");
2967 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2968 Node->getValueType(0)));
2969 Results.push_back(Results[0].getValue(1));
2972 case ISD::EXCEPTIONADDR: {
2973 unsigned Reg = TLI.getExceptionAddressRegister();
2974 assert(Reg && "Can't expand to unknown register!");
2975 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2976 Node->getValueType(0)));
2977 Results.push_back(Results[0].getValue(1));
2981 EVT VT = Node->getValueType(0);
2982 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2983 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2984 "Don't know how to expand this subtraction!");
2985 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2986 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2987 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2988 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2993 EVT VT = Node->getValueType(0);
2994 SDVTList VTs = DAG.getVTList(VT, VT);
2995 bool isSigned = Node->getOpcode() == ISD::SREM;
2996 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2997 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2998 Tmp2 = Node->getOperand(0);
2999 Tmp3 = Node->getOperand(1);
3000 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3001 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3002 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3004 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3005 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3006 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3007 } else if (isSigned) {
3008 Tmp1 = ExpandIntLibCall(Node, true,
3010 RTLIB::SREM_I16, RTLIB::SREM_I32,
3011 RTLIB::SREM_I64, RTLIB::SREM_I128);
3013 Tmp1 = ExpandIntLibCall(Node, false,
3015 RTLIB::UREM_I16, RTLIB::UREM_I32,
3016 RTLIB::UREM_I64, RTLIB::UREM_I128);
3018 Results.push_back(Tmp1);
3023 bool isSigned = Node->getOpcode() == ISD::SDIV;
3024 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3025 EVT VT = Node->getValueType(0);
3026 SDVTList VTs = DAG.getVTList(VT, VT);
3027 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
3028 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3029 Node->getOperand(1));
3031 Tmp1 = ExpandIntLibCall(Node, true,
3033 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3034 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3036 Tmp1 = ExpandIntLibCall(Node, false,
3038 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3039 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3040 Results.push_back(Tmp1);
3045 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3047 EVT VT = Node->getValueType(0);
3048 SDVTList VTs = DAG.getVTList(VT, VT);
3049 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3050 "If this wasn't legal, it shouldn't have been created!");
3051 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3052 Node->getOperand(1));
3053 Results.push_back(Tmp1.getValue(1));
3057 EVT VT = Node->getValueType(0);
3058 SDVTList VTs = DAG.getVTList(VT, VT);
3059 // See if multiply or divide can be lowered using two-result operations.
3060 // We just need the low half of the multiply; try both the signed
3061 // and unsigned forms. If the target supports both SMUL_LOHI and
3062 // UMUL_LOHI, form a preference by checking which forms of plain
3063 // MULH it supports.
3064 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3065 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3066 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3067 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3068 unsigned OpToUse = 0;
3069 if (HasSMUL_LOHI && !HasMULHS) {
3070 OpToUse = ISD::SMUL_LOHI;
3071 } else if (HasUMUL_LOHI && !HasMULHU) {
3072 OpToUse = ISD::UMUL_LOHI;
3073 } else if (HasSMUL_LOHI) {
3074 OpToUse = ISD::SMUL_LOHI;
3075 } else if (HasUMUL_LOHI) {
3076 OpToUse = ISD::UMUL_LOHI;
3079 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3080 Node->getOperand(1)));
3083 Tmp1 = ExpandIntLibCall(Node, false,
3085 RTLIB::MUL_I16, RTLIB::MUL_I32,
3086 RTLIB::MUL_I64, RTLIB::MUL_I128);
3087 Results.push_back(Tmp1);
3092 SDValue LHS = Node->getOperand(0);
3093 SDValue RHS = Node->getOperand(1);
3094 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3095 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3097 Results.push_back(Sum);
3098 EVT OType = Node->getValueType(1);
3100 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3102 // LHSSign -> LHS >= 0
3103 // RHSSign -> RHS >= 0
3104 // SumSign -> Sum >= 0
3107 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3109 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3111 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3112 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3113 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3114 Node->getOpcode() == ISD::SADDO ?
3115 ISD::SETEQ : ISD::SETNE);
3117 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3118 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3120 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3121 Results.push_back(Cmp);
3126 SDValue LHS = Node->getOperand(0);
3127 SDValue RHS = Node->getOperand(1);
3128 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3129 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3131 Results.push_back(Sum);
3132 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3133 Node->getOpcode () == ISD::UADDO ?
3134 ISD::SETULT : ISD::SETUGT));
3139 EVT VT = Node->getValueType(0);
3140 SDValue LHS = Node->getOperand(0);
3141 SDValue RHS = Node->getOperand(1);
3144 static const unsigned Ops[2][3] =
3145 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3146 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3147 bool isSigned = Node->getOpcode() == ISD::SMULO;
3148 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3149 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3150 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3151 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3152 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3154 TopHalf = BottomHalf.getValue(1);
3156 // FIXME: We should be able to fall back to a libcall with an illegal
3157 // type in some cases.
3158 // Also, we can fall back to a division in some cases, but that's a big
3159 // performance hit in the general case.
3160 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3161 VT.getSizeInBits() * 2)) &&
3162 "Don't know how to expand this operation yet!");
3163 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3164 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3165 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3166 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3167 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3168 DAG.getIntPtrConstant(0));
3169 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3170 DAG.getIntPtrConstant(1));
3173 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
3174 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3175 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3178 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3179 DAG.getConstant(0, VT), ISD::SETNE);
3181 Results.push_back(BottomHalf);
3182 Results.push_back(TopHalf);
3185 case ISD::BUILD_PAIR: {
3186 EVT PairTy = Node->getValueType(0);
3187 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3188 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3189 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3190 DAG.getConstant(PairTy.getSizeInBits()/2,
3191 TLI.getShiftAmountTy()));
3192 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3196 Tmp1 = Node->getOperand(0);
3197 Tmp2 = Node->getOperand(1);
3198 Tmp3 = Node->getOperand(2);
3199 if (Tmp1.getOpcode() == ISD::SETCC) {
3200 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3202 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3204 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3205 DAG.getConstant(0, Tmp1.getValueType()),
3206 Tmp2, Tmp3, ISD::SETNE);
3208 Results.push_back(Tmp1);
3211 SDValue Chain = Node->getOperand(0);
3212 SDValue Table = Node->getOperand(1);
3213 SDValue Index = Node->getOperand(2);
3215 EVT PTy = TLI.getPointerTy();
3217 const TargetData &TD = *TLI.getTargetData();
3218 unsigned EntrySize =
3219 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3221 Index = DAG.getNode(ISD::MUL, dl, PTy,
3222 Index, DAG.getConstant(EntrySize, PTy));
3223 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3225 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3226 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
3227 MachinePointerInfo::getJumpTable(), MemVT,
3230 if (TM.getRelocationModel() == Reloc::PIC_) {
3231 // For PIC, the sequence is:
3232 // BRIND(load(Jumptable + index) + RelocBase)
3233 // RelocBase can be JumpTable, GOT or some sort of global base.
3234 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3235 TLI.getPICJumpTableRelocBase(Table, DAG));
3237 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3238 Results.push_back(Tmp1);
3242 // Expand brcond's setcc into its constituent parts and create a BR_CC
3244 Tmp1 = Node->getOperand(0);
3245 Tmp2 = Node->getOperand(1);
3246 if (Tmp2.getOpcode() == ISD::SETCC) {
3247 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3248 Tmp1, Tmp2.getOperand(2),
3249 Tmp2.getOperand(0), Tmp2.getOperand(1),
3250 Node->getOperand(2));
3252 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3253 DAG.getCondCode(ISD::SETNE), Tmp2,
3254 DAG.getConstant(0, Tmp2.getValueType()),
3255 Node->getOperand(2));
3257 Results.push_back(Tmp1);
3260 Tmp1 = Node->getOperand(0);
3261 Tmp2 = Node->getOperand(1);
3262 Tmp3 = Node->getOperand(2);
3263 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3265 // If we expanded the SETCC into an AND/OR, return the new node
3266 if (Tmp2.getNode() == 0) {
3267 Results.push_back(Tmp1);
3271 // Otherwise, SETCC for the given comparison type must be completely
3272 // illegal; expand it into a SELECT_CC.
3273 EVT VT = Node->getValueType(0);
3274 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3275 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3276 Results.push_back(Tmp1);
3279 case ISD::SELECT_CC: {
3280 Tmp1 = Node->getOperand(0); // LHS
3281 Tmp2 = Node->getOperand(1); // RHS
3282 Tmp3 = Node->getOperand(2); // True
3283 Tmp4 = Node->getOperand(3); // False
3284 SDValue CC = Node->getOperand(4);
3286 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3287 Tmp1, Tmp2, CC, dl);
3289 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3290 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3291 CC = DAG.getCondCode(ISD::SETNE);
3292 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3294 Results.push_back(Tmp1);
3298 Tmp1 = Node->getOperand(0); // Chain
3299 Tmp2 = Node->getOperand(2); // LHS
3300 Tmp3 = Node->getOperand(3); // RHS
3301 Tmp4 = Node->getOperand(1); // CC
3303 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3304 Tmp2, Tmp3, Tmp4, dl);
3305 LastCALLSEQ_END = DAG.getEntryNode();
3307 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3308 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3309 Tmp4 = DAG.getCondCode(ISD::SETNE);
3310 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3311 Tmp3, Node->getOperand(4));
3312 Results.push_back(Tmp1);
3315 case ISD::GLOBAL_OFFSET_TABLE:
3316 case ISD::GlobalAddress:
3317 case ISD::GlobalTLSAddress:
3318 case ISD::ExternalSymbol:
3319 case ISD::ConstantPool:
3320 case ISD::JumpTable:
3321 case ISD::INTRINSIC_W_CHAIN:
3322 case ISD::INTRINSIC_WO_CHAIN:
3323 case ISD::INTRINSIC_VOID:
3324 // FIXME: Custom lowering for these operations shouldn't return null!
3325 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3326 Results.push_back(SDValue(Node, i));
3330 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3331 SmallVectorImpl<SDValue> &Results) {
3332 EVT OVT = Node->getValueType(0);
3333 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3334 Node->getOpcode() == ISD::SINT_TO_FP ||
3335 Node->getOpcode() == ISD::SETCC) {
3336 OVT = Node->getOperand(0).getValueType();
3338 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3339 DebugLoc dl = Node->getDebugLoc();
3340 SDValue Tmp1, Tmp2, Tmp3;
3341 switch (Node->getOpcode()) {
3345 // Zero extend the argument.
3346 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3347 // Perform the larger operation.
3348 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3349 if (Node->getOpcode() == ISD::CTTZ) {
3350 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3351 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3352 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3354 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3355 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3356 } else if (Node->getOpcode() == ISD::CTLZ) {
3357 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3358 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3359 DAG.getConstant(NVT.getSizeInBits() -
3360 OVT.getSizeInBits(), NVT));
3362 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3365 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3366 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3367 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3368 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3369 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3370 Results.push_back(Tmp1);
3373 case ISD::FP_TO_UINT:
3374 case ISD::FP_TO_SINT:
3375 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3376 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3377 Results.push_back(Tmp1);
3379 case ISD::UINT_TO_FP:
3380 case ISD::SINT_TO_FP:
3381 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3382 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3383 Results.push_back(Tmp1);
3388 unsigned ExtOp, TruncOp;
3389 if (OVT.isVector()) {
3390 ExtOp = ISD::BITCAST;
3391 TruncOp = ISD::BITCAST;
3393 assert(OVT.isInteger() && "Cannot promote logic operation");
3394 ExtOp = ISD::ANY_EXTEND;
3395 TruncOp = ISD::TRUNCATE;
3397 // Promote each of the values to the new type.
3398 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3399 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3400 // Perform the larger operation, then convert back
3401 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3402 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3406 unsigned ExtOp, TruncOp;
3407 if (Node->getValueType(0).isVector()) {
3408 ExtOp = ISD::BITCAST;
3409 TruncOp = ISD::BITCAST;
3410 } else if (Node->getValueType(0).isInteger()) {
3411 ExtOp = ISD::ANY_EXTEND;
3412 TruncOp = ISD::TRUNCATE;
3414 ExtOp = ISD::FP_EXTEND;
3415 TruncOp = ISD::FP_ROUND;
3417 Tmp1 = Node->getOperand(0);
3418 // Promote each of the values to the new type.
3419 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3420 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3421 // Perform the larger operation, then round down.
3422 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3423 if (TruncOp != ISD::FP_ROUND)
3424 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3426 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3427 DAG.getIntPtrConstant(0));
3428 Results.push_back(Tmp1);
3431 case ISD::VECTOR_SHUFFLE: {
3432 SmallVector<int, 8> Mask;
3433 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3435 // Cast the two input vectors.
3436 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3437 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3439 // Convert the shuffle mask to the right # elements.
3440 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3441 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3442 Results.push_back(Tmp1);
3446 unsigned ExtOp = ISD::FP_EXTEND;
3447 if (NVT.isInteger()) {
3448 ISD::CondCode CCCode =
3449 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3450 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3452 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3453 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3454 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3455 Tmp1, Tmp2, Node->getOperand(2)));
3461 // SelectionDAG::Legalize - This is the entry point for the file.
3463 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3464 /// run - This is the main entry point to this class.
3466 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();