1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/SmallPtrSet.h"
36 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
37 cl::desc("Pop up a window to show dags before legalize"));
39 static const bool ViewLegalizeDAGs = 0;
44 struct DenseMapKeyInfo<SDOperand> {
45 static inline SDOperand getEmptyKey() { return SDOperand((SDNode*)-1, -1U); }
46 static inline SDOperand getTombstoneKey() { return SDOperand((SDNode*)-1, 0);}
47 static unsigned getHashValue(const SDOperand &Val) {
48 return DenseMapKeyInfo<void*>::getHashValue(Val.Val) + Val.ResNo;
50 static bool isPod() { return true; }
54 //===----------------------------------------------------------------------===//
55 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
56 /// hacks on it until the target machine can handle it. This involves
57 /// eliminating value sizes the machine cannot handle (promoting small sizes to
58 /// large sizes or splitting up large values into small values) as well as
59 /// eliminating operations the machine cannot handle.
61 /// This code also does a small amount of optimization and recognition of idioms
62 /// as part of its processing. For example, if a target does not support a
63 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
64 /// will attempt merge setcc and brc instructions into brcc's.
67 class VISIBILITY_HIDDEN SelectionDAGLegalize {
71 // Libcall insertion helpers.
73 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
74 /// legalized. We use this to ensure that calls are properly serialized
75 /// against each other, including inserted libcalls.
76 SDOperand LastCALLSEQ_END;
78 /// IsLegalizingCall - This member is used *only* for purposes of providing
79 /// helpful assertions that a libcall isn't created while another call is
80 /// being legalized (which could lead to non-serialized call sequences).
81 bool IsLegalizingCall;
84 Legal, // The target natively supports this operation.
85 Promote, // This operation should be executed in a larger type.
86 Expand // Try to expand this to other ops, otherwise use a libcall.
89 /// ValueTypeActions - This is a bitvector that contains two bits for each
90 /// value type, where the two bits correspond to the LegalizeAction enum.
91 /// This can be queried with "getTypeAction(VT)".
92 TargetLowering::ValueTypeActionImpl ValueTypeActions;
94 /// LegalizedNodes - For nodes that are of legal width, and that have more
95 /// than one use, this map indicates what regularized operand to use. This
96 /// allows us to avoid legalizing the same thing more than once.
97 DenseMap<SDOperand, SDOperand> LegalizedNodes;
99 /// PromotedNodes - For nodes that are below legal width, and that have more
100 /// than one use, this map indicates what promoted value to use. This allows
101 /// us to avoid promoting the same thing more than once.
102 std::map<SDOperand, SDOperand> PromotedNodes;
104 /// ExpandedNodes - For nodes that need to be expanded this map indicates
105 /// which which operands are the expanded version of the input. This allows
106 /// us to avoid expanding the same node more than once.
107 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
109 /// SplitNodes - For vector nodes that need to be split, this map indicates
110 /// which which operands are the split version of the input. This allows us
111 /// to avoid splitting the same node more than once.
112 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
114 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
115 /// concrete packed types, this contains the mapping of ones we have already
116 /// processed to the result.
117 std::map<SDOperand, SDOperand> PackedNodes;
119 void AddLegalizedOperand(SDOperand From, SDOperand To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDOperand From, SDOperand To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
128 // If someone requests legalization of the new node, return itself.
129 LegalizedNodes.insert(std::make_pair(To, To));
134 SelectionDAGLegalize(SelectionDAG &DAG);
136 /// getTypeAction - Return how we should legalize values of this type, either
137 /// it is already legal or we need to expand it into multiple registers of
138 /// smaller integer type, or we need to promote it to a larger type.
139 LegalizeAction getTypeAction(MVT::ValueType VT) const {
140 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
143 /// isTypeLegal - Return true if this type is legal on this target.
145 bool isTypeLegal(MVT::ValueType VT) const {
146 return getTypeAction(VT) == Legal;
152 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
153 /// appropriate for its type.
154 void HandleOp(SDOperand Op);
156 /// LegalizeOp - We know that the specified value has a legal type.
157 /// Recursively ensure that the operands have legal types, then return the
159 SDOperand LegalizeOp(SDOperand O);
161 /// PromoteOp - Given an operation that produces a value in an invalid type,
162 /// promote it to compute the value into a larger type. The produced value
163 /// will have the correct bits for the low portion of the register, but no
164 /// guarantee is made about the top bits: it may be zero, sign-extended, or
166 SDOperand PromoteOp(SDOperand O);
168 /// ExpandOp - Expand the specified SDOperand into its two component pieces
169 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
170 /// the LegalizeNodes map is filled in for any results that are not expanded,
171 /// the ExpandedNodes map is filled in for any results that are expanded, and
172 /// the Lo/Hi values are returned. This applies to integer types and Vector
174 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
176 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
177 /// two smaller values of MVT::Vector type.
178 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
180 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
181 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
182 /// this is called, we know that PackedVT is the right type for the result and
183 /// we know that this type is legal for the target.
184 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
186 /// isShuffleLegal - Return true if a vector shuffle is legal with the
187 /// specified mask and type. Targets can specify exactly which masks they
188 /// support and the code generator is tasked with not creating illegal masks.
190 /// Note that this will also return true for shuffles that are promoted to a
193 /// If this is a legal shuffle, this method returns the (possibly promoted)
194 /// build_vector Mask. If it's not a legal shuffle, it returns null.
195 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
197 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
198 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
200 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
202 SDOperand CreateStackTemporary(MVT::ValueType VT);
204 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
206 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
209 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
210 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
211 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
212 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
214 MVT::ValueType DestVT);
215 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
217 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
220 SDOperand ExpandBSWAP(SDOperand Op);
221 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
222 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
223 SDOperand &Lo, SDOperand &Hi);
224 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
225 SDOperand &Lo, SDOperand &Hi);
227 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
228 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
230 SDOperand getIntPtrConstant(uint64_t Val) {
231 return DAG.getConstant(Val, TLI.getPointerTy());
236 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
237 /// specified mask and type. Targets can specify exactly which masks they
238 /// support and the code generator is tasked with not creating illegal masks.
240 /// Note that this will also return true for shuffles that are promoted to a
242 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
243 SDOperand Mask) const {
244 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
246 case TargetLowering::Legal:
247 case TargetLowering::Custom:
249 case TargetLowering::Promote: {
250 // If this is promoted to a different type, convert the shuffle mask and
251 // ask if it is legal in the promoted type!
252 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
254 // If we changed # elements, change the shuffle mask.
255 unsigned NumEltsGrowth =
256 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
257 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
258 if (NumEltsGrowth > 1) {
259 // Renumber the elements.
260 SmallVector<SDOperand, 8> Ops;
261 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
262 SDOperand InOp = Mask.getOperand(i);
263 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
264 if (InOp.getOpcode() == ISD::UNDEF)
265 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
267 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
268 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
272 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
278 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
281 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
282 /// specified vector opcode.
283 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
285 default: assert(0 && "Don't know how to scalarize this opcode!");
286 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
287 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
288 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
289 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
290 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
291 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
292 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
293 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
297 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
298 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
299 ValueTypeActions(TLI.getValueTypeActions()) {
300 assert(MVT::LAST_VALUETYPE <= 32 &&
301 "Too many value types for ValueTypeActions to hold!");
304 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
305 /// not been visited yet and if all of its operands have already been visited.
306 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
307 DenseMap<SDNode*, unsigned> &Visited) {
308 if (++Visited[N] != N->getNumOperands())
309 return; // Haven't visited all operands yet
313 if (N->hasOneUse()) { // Tail recurse in common case.
314 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
318 // Now that we have N in, add anything that uses it if all of their operands
320 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
321 ComputeTopDownOrdering(*UI, Order, Visited);
325 void SelectionDAGLegalize::LegalizeDAG() {
326 LastCALLSEQ_END = DAG.getEntryNode();
327 IsLegalizingCall = false;
329 // The legalize process is inherently a bottom-up recursive process (users
330 // legalize their uses before themselves). Given infinite stack space, we
331 // could just start legalizing on the root and traverse the whole graph. In
332 // practice however, this causes us to run out of stack space on large basic
333 // blocks. To avoid this problem, compute an ordering of the nodes where each
334 // node is only legalized after all of its operands are legalized.
335 DenseMap<SDNode*, unsigned> Visited;
336 std::vector<SDNode*> Order;
338 // Compute ordering from all of the leaves in the graphs, those (like the
339 // entry node) that have no operands.
340 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
341 E = DAG.allnodes_end(); I != E; ++I) {
342 if (I->getNumOperands() == 0) {
344 ComputeTopDownOrdering(I, Order, Visited);
348 assert(Order.size() == Visited.size() &&
350 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
351 "Error: DAG is cyclic!");
354 for (unsigned i = 0, e = Order.size(); i != e; ++i)
355 HandleOp(SDOperand(Order[i], 0));
357 // Finally, it's possible the root changed. Get the new root.
358 SDOperand OldRoot = DAG.getRoot();
359 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
360 DAG.setRoot(LegalizedNodes[OldRoot]);
362 ExpandedNodes.clear();
363 LegalizedNodes.clear();
364 PromotedNodes.clear();
368 // Remove dead nodes now.
369 DAG.RemoveDeadNodes();
373 /// FindCallEndFromCallStart - Given a chained node that is part of a call
374 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
375 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
376 if (Node->getOpcode() == ISD::CALLSEQ_END)
378 if (Node->use_empty())
379 return 0; // No CallSeqEnd
381 // The chain is usually at the end.
382 SDOperand TheChain(Node, Node->getNumValues()-1);
383 if (TheChain.getValueType() != MVT::Other) {
384 // Sometimes it's at the beginning.
385 TheChain = SDOperand(Node, 0);
386 if (TheChain.getValueType() != MVT::Other) {
387 // Otherwise, hunt for it.
388 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
389 if (Node->getValueType(i) == MVT::Other) {
390 TheChain = SDOperand(Node, i);
394 // Otherwise, we walked into a node without a chain.
395 if (TheChain.getValueType() != MVT::Other)
400 for (SDNode::use_iterator UI = Node->use_begin(),
401 E = Node->use_end(); UI != E; ++UI) {
403 // Make sure to only follow users of our token chain.
405 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
406 if (User->getOperand(i) == TheChain)
407 if (SDNode *Result = FindCallEndFromCallStart(User))
413 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
414 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
415 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
416 assert(Node && "Didn't find callseq_start for a call??");
417 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
419 assert(Node->getOperand(0).getValueType() == MVT::Other &&
420 "Node doesn't have a token chain argument!");
421 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
424 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
425 /// see if any uses can reach Dest. If no dest operands can get to dest,
426 /// legalize them, legalize ourself, and return false, otherwise, return true.
428 /// Keep track of the nodes we fine that actually do lead to Dest in
429 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
431 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
432 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
433 if (N == Dest) return true; // N certainly leads to Dest :)
435 // If we've already processed this node and it does lead to Dest, there is no
436 // need to reprocess it.
437 if (NodesLeadingTo.count(N)) return true;
439 // If the first result of this node has been already legalized, then it cannot
441 switch (getTypeAction(N->getValueType(0))) {
443 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
446 if (PromotedNodes.count(SDOperand(N, 0))) return false;
449 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
453 // Okay, this node has not already been legalized. Check and legalize all
454 // operands. If none lead to Dest, then we can legalize this node.
455 bool OperandsLeadToDest = false;
456 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
457 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
458 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
460 if (OperandsLeadToDest) {
461 NodesLeadingTo.insert(N);
465 // Okay, this node looks safe, legalize it and return false.
466 HandleOp(SDOperand(N, 0));
470 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
471 /// appropriate for its type.
472 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
473 switch (getTypeAction(Op.getValueType())) {
474 default: assert(0 && "Bad type action!");
475 case Legal: LegalizeOp(Op); break;
476 case Promote: PromoteOp(Op); break;
478 if (Op.getValueType() != MVT::Vector) {
483 unsigned NumOps = N->getNumOperands();
484 unsigned NumElements =
485 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
486 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
487 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
488 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
489 // In the common case, this is a legal vector type, convert it to the
490 // packed operation and type now.
491 PackVectorOp(Op, PackedVT);
492 } else if (NumElements == 1) {
493 // Otherwise, if this is a single element vector, convert it to a
495 PackVectorOp(Op, EVT);
497 // Otherwise, this is a multiple element vector that isn't supported.
498 // Split it in half and legalize both parts.
500 SplitVectorOp(Op, X, Y);
507 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
508 /// a load from the constant pool.
509 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
510 SelectionDAG &DAG, TargetLowering &TLI) {
513 // If a FP immediate is precise when represented as a float and if the
514 // target can do an extending load from float to double, we put it into
515 // the constant pool as a float, even if it's is statically typed as a
517 MVT::ValueType VT = CFP->getValueType(0);
518 bool isDouble = VT == MVT::f64;
519 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
520 Type::FloatTy, CFP->getValue());
522 double Val = LLVMC->getValue();
524 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
525 : DAG.getConstant(FloatToBits(Val), MVT::i32);
528 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
529 // Only do this if the target has a native EXTLOAD instruction from f32.
530 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
531 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
536 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
538 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
539 CPIdx, NULL, 0, MVT::f32);
541 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
546 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
549 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
550 SelectionDAG &DAG, TargetLowering &TLI) {
551 MVT::ValueType VT = Node->getValueType(0);
552 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
553 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
555 // First get the sign bit of second operand.
556 SDOperand Mask1 = (SrcVT == MVT::f64)
557 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
558 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
559 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
560 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
561 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
562 // Shift right or sign-extend it if the two operands have different types.
563 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
565 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
566 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
567 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
568 } else if (SizeDiff < 0)
569 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
571 // Clear the sign bit of first operand.
572 SDOperand Mask2 = (VT == MVT::f64)
573 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
574 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
575 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
576 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
577 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
579 // Or the value with the sign bit.
580 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
585 /// LegalizeOp - We know that the specified value has a legal type.
586 /// Recursively ensure that the operands have legal types, then return the
588 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
589 assert(isTypeLegal(Op.getValueType()) &&
590 "Caller should expand or promote operands that are not legal!");
591 SDNode *Node = Op.Val;
593 // If this operation defines any values that cannot be represented in a
594 // register on this target, make sure to expand or promote them.
595 if (Node->getNumValues() > 1) {
596 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
597 if (getTypeAction(Node->getValueType(i)) != Legal) {
598 HandleOp(Op.getValue(i));
599 assert(LegalizedNodes.count(Op) &&
600 "Handling didn't add legal operands!");
601 return LegalizedNodes[Op];
605 // Note that LegalizeOp may be reentered even from single-use nodes, which
606 // means that we always must cache transformed nodes.
607 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
608 if (I != LegalizedNodes.end()) return I->second;
610 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
611 SDOperand Result = Op;
612 bool isCustom = false;
614 switch (Node->getOpcode()) {
615 case ISD::FrameIndex:
616 case ISD::EntryToken:
618 case ISD::BasicBlock:
619 case ISD::TargetFrameIndex:
620 case ISD::TargetJumpTable:
621 case ISD::TargetConstant:
622 case ISD::TargetConstantFP:
623 case ISD::TargetConstantPool:
624 case ISD::TargetGlobalAddress:
625 case ISD::TargetExternalSymbol:
630 case ISD::GLOBAL_OFFSET_TABLE:
631 // Primitives must all be legal.
632 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
633 "This must be legal!");
636 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
637 // If this is a target node, legalize it by legalizing the operands then
638 // passing it through.
639 SmallVector<SDOperand, 8> Ops;
640 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
641 Ops.push_back(LegalizeOp(Node->getOperand(i)));
643 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
645 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
646 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
647 return Result.getValue(Op.ResNo);
649 // Otherwise this is an unhandled builtin node. splat.
651 cerr << "NODE: "; Node->dump(); cerr << "\n";
653 assert(0 && "Do not know how to legalize this operator!");
655 case ISD::GlobalAddress:
656 case ISD::ExternalSymbol:
657 case ISD::ConstantPool:
658 case ISD::JumpTable: // Nothing to do.
659 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
660 default: assert(0 && "This action is not supported yet!");
661 case TargetLowering::Custom:
662 Tmp1 = TLI.LowerOperation(Op, DAG);
663 if (Tmp1.Val) Result = Tmp1;
664 // FALLTHROUGH if the target doesn't want to lower this op after all.
665 case TargetLowering::Legal:
670 case ISD::RETURNADDR:
671 // The only option for these nodes is to custom lower them. If the target
672 // does not custom lower them, then return zero.
673 Tmp1 = TLI.LowerOperation(Op, DAG);
677 Result = DAG.getConstant(0, TLI.getPointerTy());
679 case ISD::AssertSext:
680 case ISD::AssertZext:
681 Tmp1 = LegalizeOp(Node->getOperand(0));
682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
684 case ISD::MERGE_VALUES:
685 // Legalize eliminates MERGE_VALUES nodes.
686 Result = Node->getOperand(Op.ResNo);
688 case ISD::CopyFromReg:
689 Tmp1 = LegalizeOp(Node->getOperand(0));
690 Result = Op.getValue(0);
691 if (Node->getNumValues() == 2) {
692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
694 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
695 if (Node->getNumOperands() == 3) {
696 Tmp2 = LegalizeOp(Node->getOperand(2));
697 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
699 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
701 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
703 // Since CopyFromReg produces two values, make sure to remember that we
704 // legalized both of them.
705 AddLegalizedOperand(Op.getValue(0), Result);
706 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
707 return Result.getValue(Op.ResNo);
709 MVT::ValueType VT = Op.getValueType();
710 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
711 default: assert(0 && "This action is not supported yet!");
712 case TargetLowering::Expand:
713 if (MVT::isInteger(VT))
714 Result = DAG.getConstant(0, VT);
715 else if (MVT::isFloatingPoint(VT))
716 Result = DAG.getConstantFP(0, VT);
718 assert(0 && "Unknown value type!");
720 case TargetLowering::Legal:
726 case ISD::INTRINSIC_W_CHAIN:
727 case ISD::INTRINSIC_WO_CHAIN:
728 case ISD::INTRINSIC_VOID: {
729 SmallVector<SDOperand, 8> Ops;
730 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
731 Ops.push_back(LegalizeOp(Node->getOperand(i)));
732 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
734 // Allow the target to custom lower its intrinsics if it wants to.
735 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
736 TargetLowering::Custom) {
737 Tmp3 = TLI.LowerOperation(Result, DAG);
738 if (Tmp3.Val) Result = Tmp3;
741 if (Result.Val->getNumValues() == 1) break;
743 // Must have return value and chain result.
744 assert(Result.Val->getNumValues() == 2 &&
745 "Cannot return more than two values!");
747 // Since loads produce two values, make sure to remember that we
748 // legalized both of them.
749 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
750 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
751 return Result.getValue(Op.ResNo);
755 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
756 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
758 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
759 case TargetLowering::Promote:
760 default: assert(0 && "This action is not supported yet!");
761 case TargetLowering::Expand: {
762 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
763 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
764 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
766 if (MMI && (useDEBUG_LOC || useLABEL)) {
767 const std::string &FName =
768 cast<StringSDNode>(Node->getOperand(3))->getValue();
769 const std::string &DirName =
770 cast<StringSDNode>(Node->getOperand(4))->getValue();
771 unsigned SrcFile = MMI->RecordSource(DirName, FName);
773 SmallVector<SDOperand, 8> Ops;
774 Ops.push_back(Tmp1); // chain
775 SDOperand LineOp = Node->getOperand(1);
776 SDOperand ColOp = Node->getOperand(2);
779 Ops.push_back(LineOp); // line #
780 Ops.push_back(ColOp); // col #
781 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
782 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
784 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
785 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
786 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
787 Ops.push_back(DAG.getConstant(ID, MVT::i32));
788 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
791 Result = Tmp1; // chain
795 case TargetLowering::Legal:
796 if (Tmp1 != Node->getOperand(0) ||
797 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
798 SmallVector<SDOperand, 8> Ops;
800 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
801 Ops.push_back(Node->getOperand(1)); // line # must be legal.
802 Ops.push_back(Node->getOperand(2)); // col # must be legal.
804 // Otherwise promote them.
805 Ops.push_back(PromoteOp(Node->getOperand(1)));
806 Ops.push_back(PromoteOp(Node->getOperand(2)));
808 Ops.push_back(Node->getOperand(3)); // filename must be legal.
809 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
810 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
817 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
818 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
819 default: assert(0 && "This action is not supported yet!");
820 case TargetLowering::Legal:
821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
822 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
823 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
824 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
825 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
831 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
832 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
833 default: assert(0 && "This action is not supported yet!");
834 case TargetLowering::Legal:
835 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
836 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
837 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
843 // We know we don't need to expand constants here, constants only have one
844 // value and we check that it is fine above.
846 // FIXME: Maybe we should handle things like targets that don't support full
847 // 32-bit immediates?
849 case ISD::ConstantFP: {
850 // Spill FP immediates to the constant pool if the target cannot directly
851 // codegen them. Targets often have some immediate values that can be
852 // efficiently generated into an FP register without a load. We explicitly
853 // leave these constants as ConstantFP nodes for the target to deal with.
854 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
856 // Check to see if this FP immediate is already legal.
857 bool isLegal = false;
858 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
859 E = TLI.legal_fpimm_end(); I != E; ++I)
860 if (CFP->isExactlyValue(*I)) {
865 // If this is a legal constant, turn it into a TargetConstantFP node.
867 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
871 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
872 default: assert(0 && "This action is not supported yet!");
873 case TargetLowering::Custom:
874 Tmp3 = TLI.LowerOperation(Result, DAG);
880 case TargetLowering::Expand:
881 Result = ExpandConstantFP(CFP, true, DAG, TLI);
885 case ISD::TokenFactor:
886 if (Node->getNumOperands() == 2) {
887 Tmp1 = LegalizeOp(Node->getOperand(0));
888 Tmp2 = LegalizeOp(Node->getOperand(1));
889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
890 } else if (Node->getNumOperands() == 3) {
891 Tmp1 = LegalizeOp(Node->getOperand(0));
892 Tmp2 = LegalizeOp(Node->getOperand(1));
893 Tmp3 = LegalizeOp(Node->getOperand(2));
894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
896 SmallVector<SDOperand, 8> Ops;
897 // Legalize the operands.
898 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
899 Ops.push_back(LegalizeOp(Node->getOperand(i)));
900 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
904 case ISD::FORMAL_ARGUMENTS:
906 // The only option for this is to custom lower it.
907 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
908 assert(Tmp3.Val && "Target didn't custom lower this node!");
909 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
910 "Lowering call/formal_arguments produced unexpected # results!");
912 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
913 // remember that we legalized all of them, so it doesn't get relegalized.
914 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
915 Tmp1 = LegalizeOp(Tmp3.getValue(i));
918 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
922 case ISD::BUILD_VECTOR:
923 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
924 default: assert(0 && "This action is not supported yet!");
925 case TargetLowering::Custom:
926 Tmp3 = TLI.LowerOperation(Result, DAG);
932 case TargetLowering::Expand:
933 Result = ExpandBUILD_VECTOR(Result.Val);
937 case ISD::INSERT_VECTOR_ELT:
938 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
939 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
940 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
941 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
943 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
944 Node->getValueType(0))) {
945 default: assert(0 && "This action is not supported yet!");
946 case TargetLowering::Legal:
948 case TargetLowering::Custom:
949 Tmp3 = TLI.LowerOperation(Result, DAG);
955 case TargetLowering::Expand: {
956 // If the insert index is a constant, codegen this as a scalar_to_vector,
957 // then a shuffle that inserts it into the right position in the vector.
958 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
959 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
960 Tmp1.getValueType(), Tmp2);
962 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
963 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
964 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
966 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
967 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
969 SmallVector<SDOperand, 8> ShufOps;
970 for (unsigned i = 0; i != NumElts; ++i) {
971 if (i != InsertPos->getValue())
972 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
974 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
976 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
977 &ShufOps[0], ShufOps.size());
979 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
980 Tmp1, ScVec, ShufMask);
981 Result = LegalizeOp(Result);
985 // If the target doesn't support this, we have to spill the input vector
986 // to a temporary stack slot, update the element, then reload it. This is
987 // badness. We could also load the value into a vector register (either
988 // with a "move to register" or "extload into register" instruction, then
989 // permute it into place, if the idx is a constant and if the idx is
990 // supported by the target.
991 MVT::ValueType VT = Tmp1.getValueType();
992 MVT::ValueType EltVT = Tmp2.getValueType();
993 MVT::ValueType IdxVT = Tmp3.getValueType();
994 MVT::ValueType PtrVT = TLI.getPointerTy();
995 SDOperand StackPtr = CreateStackTemporary(VT);
997 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
999 // Truncate or zero extend offset to target pointer type.
1000 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1001 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1002 // Add the offset to the index.
1003 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1004 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1005 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1006 // Store the scalar value.
1007 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1008 // Load the updated vector.
1009 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1014 case ISD::SCALAR_TO_VECTOR:
1015 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1016 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1020 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1021 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1022 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1023 Node->getValueType(0))) {
1024 default: assert(0 && "This action is not supported yet!");
1025 case TargetLowering::Legal:
1027 case TargetLowering::Custom:
1028 Tmp3 = TLI.LowerOperation(Result, DAG);
1034 case TargetLowering::Expand:
1035 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1039 case ISD::VECTOR_SHUFFLE:
1040 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1041 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1044 // Allow targets to custom lower the SHUFFLEs they support.
1045 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1046 default: assert(0 && "Unknown operation action!");
1047 case TargetLowering::Legal:
1048 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1049 "vector shuffle should not be created if not legal!");
1051 case TargetLowering::Custom:
1052 Tmp3 = TLI.LowerOperation(Result, DAG);
1058 case TargetLowering::Expand: {
1059 MVT::ValueType VT = Node->getValueType(0);
1060 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
1061 MVT::ValueType PtrVT = TLI.getPointerTy();
1062 SDOperand Mask = Node->getOperand(2);
1063 unsigned NumElems = Mask.getNumOperands();
1064 SmallVector<SDOperand,8> Ops;
1065 for (unsigned i = 0; i != NumElems; ++i) {
1066 SDOperand Arg = Mask.getOperand(i);
1067 if (Arg.getOpcode() == ISD::UNDEF) {
1068 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1070 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1071 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1073 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1074 DAG.getConstant(Idx, PtrVT)));
1076 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1077 DAG.getConstant(Idx - NumElems, PtrVT)));
1080 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1083 case TargetLowering::Promote: {
1084 // Change base type to a different vector type.
1085 MVT::ValueType OVT = Node->getValueType(0);
1086 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1088 // Cast the two input vectors.
1089 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1090 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1092 // Convert the shuffle mask to the right # elements.
1093 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1094 assert(Tmp3.Val && "Shuffle not legal?");
1095 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1096 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1102 case ISD::EXTRACT_VECTOR_ELT:
1103 Tmp1 = LegalizeOp(Node->getOperand(0));
1104 Tmp2 = LegalizeOp(Node->getOperand(1));
1105 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1107 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1108 Tmp1.getValueType())) {
1109 default: assert(0 && "This action is not supported yet!");
1110 case TargetLowering::Legal:
1112 case TargetLowering::Custom:
1113 Tmp3 = TLI.LowerOperation(Result, DAG);
1119 case TargetLowering::Expand:
1120 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1125 case ISD::VEXTRACT_VECTOR_ELT:
1126 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1129 case ISD::CALLSEQ_START: {
1130 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1132 // Recursively Legalize all of the inputs of the call end that do not lead
1133 // to this call start. This ensures that any libcalls that need be inserted
1134 // are inserted *before* the CALLSEQ_START.
1135 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1136 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1137 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1141 // Now that we legalized all of the inputs (which may have inserted
1142 // libcalls) create the new CALLSEQ_START node.
1143 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1145 // Merge in the last call, to ensure that this call start after the last
1147 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1148 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1149 Tmp1 = LegalizeOp(Tmp1);
1152 // Do not try to legalize the target-specific arguments (#1+).
1153 if (Tmp1 != Node->getOperand(0)) {
1154 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1156 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1159 // Remember that the CALLSEQ_START is legalized.
1160 AddLegalizedOperand(Op.getValue(0), Result);
1161 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1162 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1164 // Now that the callseq_start and all of the non-call nodes above this call
1165 // sequence have been legalized, legalize the call itself. During this
1166 // process, no libcalls can/will be inserted, guaranteeing that no calls
1168 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1169 SDOperand InCallSEQ = LastCALLSEQ_END;
1170 // Note that we are selecting this call!
1171 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1172 IsLegalizingCall = true;
1174 // Legalize the call, starting from the CALLSEQ_END.
1175 LegalizeOp(LastCALLSEQ_END);
1176 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1179 case ISD::CALLSEQ_END:
1180 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1181 // will cause this node to be legalized as well as handling libcalls right.
1182 if (LastCALLSEQ_END.Val != Node) {
1183 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1184 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1185 assert(I != LegalizedNodes.end() &&
1186 "Legalizing the call start should have legalized this node!");
1190 // Otherwise, the call start has been legalized and everything is going
1191 // according to plan. Just legalize ourselves normally here.
1192 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1193 // Do not try to legalize the target-specific arguments (#1+), except for
1194 // an optional flag input.
1195 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1196 if (Tmp1 != Node->getOperand(0)) {
1197 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1199 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1202 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1203 if (Tmp1 != Node->getOperand(0) ||
1204 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1205 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1208 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1211 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1212 // This finishes up call legalization.
1213 IsLegalizingCall = false;
1215 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1216 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1217 if (Node->getNumValues() == 2)
1218 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1219 return Result.getValue(Op.ResNo);
1220 case ISD::DYNAMIC_STACKALLOC: {
1221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1222 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1223 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1224 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1226 Tmp1 = Result.getValue(0);
1227 Tmp2 = Result.getValue(1);
1228 switch (TLI.getOperationAction(Node->getOpcode(),
1229 Node->getValueType(0))) {
1230 default: assert(0 && "This action is not supported yet!");
1231 case TargetLowering::Expand: {
1232 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1233 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1234 " not tell us which reg is the stack pointer!");
1235 SDOperand Chain = Tmp1.getOperand(0);
1236 SDOperand Size = Tmp2.getOperand(1);
1237 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1238 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1239 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1240 Tmp1 = LegalizeOp(Tmp1);
1241 Tmp2 = LegalizeOp(Tmp2);
1244 case TargetLowering::Custom:
1245 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1247 Tmp1 = LegalizeOp(Tmp3);
1248 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1251 case TargetLowering::Legal:
1254 // Since this op produce two values, make sure to remember that we
1255 // legalized both of them.
1256 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1257 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1258 return Op.ResNo ? Tmp2 : Tmp1;
1260 case ISD::INLINEASM: {
1261 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1262 bool Changed = false;
1263 // Legalize all of the operands of the inline asm, in case they are nodes
1264 // that need to be expanded or something. Note we skip the asm string and
1265 // all of the TargetConstant flags.
1266 SDOperand Op = LegalizeOp(Ops[0]);
1267 Changed = Op != Ops[0];
1270 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1271 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1272 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1273 for (++i; NumVals; ++i, --NumVals) {
1274 SDOperand Op = LegalizeOp(Ops[i]);
1283 Op = LegalizeOp(Ops.back());
1284 Changed |= Op != Ops.back();
1289 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1291 // INLINE asm returns a chain and flag, make sure to add both to the map.
1292 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1293 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1294 return Result.getValue(Op.ResNo);
1297 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1298 // Ensure that libcalls are emitted before a branch.
1299 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1300 Tmp1 = LegalizeOp(Tmp1);
1301 LastCALLSEQ_END = DAG.getEntryNode();
1303 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1306 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1307 // Ensure that libcalls are emitted before a branch.
1308 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1309 Tmp1 = LegalizeOp(Tmp1);
1310 LastCALLSEQ_END = DAG.getEntryNode();
1312 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1313 default: assert(0 && "Indirect target must be legal type (pointer)!");
1315 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1322 // Ensure that libcalls are emitted before a branch.
1323 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1324 Tmp1 = LegalizeOp(Tmp1);
1325 LastCALLSEQ_END = DAG.getEntryNode();
1327 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1330 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1331 default: assert(0 && "This action is not supported yet!");
1332 case TargetLowering::Legal: break;
1333 case TargetLowering::Custom:
1334 Tmp1 = TLI.LowerOperation(Result, DAG);
1335 if (Tmp1.Val) Result = Tmp1;
1337 case TargetLowering::Expand: {
1338 SDOperand Chain = Result.getOperand(0);
1339 SDOperand Table = Result.getOperand(1);
1340 SDOperand Index = Result.getOperand(2);
1342 MVT::ValueType PTy = TLI.getPointerTy();
1343 MachineFunction &MF = DAG.getMachineFunction();
1344 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1345 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1346 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1349 switch (EntrySize) {
1350 default: assert(0 && "Size of jump table not supported yet."); break;
1351 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1352 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1355 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1356 // For PIC, the sequence is:
1357 // BRIND(load(Jumptable + index) + RelocBase)
1358 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1360 if (TLI.usesGlobalOffsetTable())
1361 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1364 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1365 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1366 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1368 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1374 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1375 // Ensure that libcalls are emitted before a return.
1376 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1377 Tmp1 = LegalizeOp(Tmp1);
1378 LastCALLSEQ_END = DAG.getEntryNode();
1380 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1381 case Expand: assert(0 && "It's impossible to expand bools");
1383 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1386 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1388 // The top bits of the promoted condition are not necessarily zero, ensure
1389 // that the value is properly zero extended.
1390 if (!TLI.MaskedValueIsZero(Tmp2,
1391 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1392 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1396 // Basic block destination (Op#2) is always legal.
1397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1399 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1400 default: assert(0 && "This action is not supported yet!");
1401 case TargetLowering::Legal: break;
1402 case TargetLowering::Custom:
1403 Tmp1 = TLI.LowerOperation(Result, DAG);
1404 if (Tmp1.Val) Result = Tmp1;
1406 case TargetLowering::Expand:
1407 // Expand brcond's setcc into its constituent parts and create a BR_CC
1409 if (Tmp2.getOpcode() == ISD::SETCC) {
1410 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1411 Tmp2.getOperand(0), Tmp2.getOperand(1),
1412 Node->getOperand(2));
1414 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1415 DAG.getCondCode(ISD::SETNE), Tmp2,
1416 DAG.getConstant(0, Tmp2.getValueType()),
1417 Node->getOperand(2));
1423 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1424 // Ensure that libcalls are emitted before a branch.
1425 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1426 Tmp1 = LegalizeOp(Tmp1);
1427 Tmp2 = Node->getOperand(2); // LHS
1428 Tmp3 = Node->getOperand(3); // RHS
1429 Tmp4 = Node->getOperand(1); // CC
1431 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1432 LastCALLSEQ_END = DAG.getEntryNode();
1434 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1435 // the LHS is a legal SETCC itself. In this case, we need to compare
1436 // the result against zero to select between true and false values.
1437 if (Tmp3.Val == 0) {
1438 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1439 Tmp4 = DAG.getCondCode(ISD::SETNE);
1442 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1443 Node->getOperand(4));
1445 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1446 default: assert(0 && "Unexpected action for BR_CC!");
1447 case TargetLowering::Legal: break;
1448 case TargetLowering::Custom:
1449 Tmp4 = TLI.LowerOperation(Result, DAG);
1450 if (Tmp4.Val) Result = Tmp4;
1455 LoadSDNode *LD = cast<LoadSDNode>(Node);
1456 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1457 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1459 ISD::LoadExtType ExtType = LD->getExtensionType();
1460 if (ExtType == ISD::NON_EXTLOAD) {
1461 MVT::ValueType VT = Node->getValueType(0);
1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1463 Tmp3 = Result.getValue(0);
1464 Tmp4 = Result.getValue(1);
1466 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1467 default: assert(0 && "This action is not supported yet!");
1468 case TargetLowering::Legal: break;
1469 case TargetLowering::Custom:
1470 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1472 Tmp3 = LegalizeOp(Tmp1);
1473 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1476 case TargetLowering::Promote: {
1477 // Only promote a load of vector type to another.
1478 assert(MVT::isVector(VT) && "Cannot promote this load!");
1479 // Change base type to a different vector type.
1480 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1482 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1483 LD->getSrcValueOffset());
1484 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1485 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1489 // Since loads produce two values, make sure to remember that we
1490 // legalized both of them.
1491 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1492 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1493 return Op.ResNo ? Tmp4 : Tmp3;
1495 MVT::ValueType SrcVT = LD->getLoadedVT();
1496 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1497 default: assert(0 && "This action is not supported yet!");
1498 case TargetLowering::Promote:
1499 assert(SrcVT == MVT::i1 &&
1500 "Can only promote extending LOAD from i1 -> i8!");
1501 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1502 LD->getSrcValue(), LD->getSrcValueOffset(),
1504 Tmp1 = Result.getValue(0);
1505 Tmp2 = Result.getValue(1);
1507 case TargetLowering::Custom:
1510 case TargetLowering::Legal:
1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1512 Tmp1 = Result.getValue(0);
1513 Tmp2 = Result.getValue(1);
1516 Tmp3 = TLI.LowerOperation(Result, DAG);
1518 Tmp1 = LegalizeOp(Tmp3);
1519 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1523 case TargetLowering::Expand:
1524 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1525 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1526 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1527 LD->getSrcValueOffset());
1528 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1529 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1530 Tmp2 = LegalizeOp(Load.getValue(1));
1533 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1534 // Turn the unsupported load into an EXTLOAD followed by an explicit
1535 // zero/sign extend inreg.
1536 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1537 Tmp1, Tmp2, LD->getSrcValue(),
1538 LD->getSrcValueOffset(), SrcVT);
1540 if (ExtType == ISD::SEXTLOAD)
1541 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1542 Result, DAG.getValueType(SrcVT));
1544 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1545 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1546 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1549 // Since loads produce two values, make sure to remember that we legalized
1551 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1552 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1553 return Op.ResNo ? Tmp2 : Tmp1;
1556 case ISD::EXTRACT_ELEMENT: {
1557 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1558 switch (getTypeAction(OpTy)) {
1559 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1561 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1563 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1564 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1565 TLI.getShiftAmountTy()));
1566 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1569 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1570 Node->getOperand(0));
1574 // Get both the low and high parts.
1575 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1576 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1577 Result = Tmp2; // 1 -> Hi
1579 Result = Tmp1; // 0 -> Lo
1585 case ISD::CopyToReg:
1586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1588 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1589 "Register type must be legal!");
1590 // Legalize the incoming value (must be a legal type).
1591 Tmp2 = LegalizeOp(Node->getOperand(2));
1592 if (Node->getNumValues() == 1) {
1593 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1595 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1596 if (Node->getNumOperands() == 4) {
1597 Tmp3 = LegalizeOp(Node->getOperand(3));
1598 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1601 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1604 // Since this produces two values, make sure to remember that we legalized
1606 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1607 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1613 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1615 // Ensure that libcalls are emitted before a return.
1616 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1617 Tmp1 = LegalizeOp(Tmp1);
1618 LastCALLSEQ_END = DAG.getEntryNode();
1620 switch (Node->getNumOperands()) {
1622 Tmp2 = Node->getOperand(1);
1623 Tmp3 = Node->getOperand(2); // Signness
1624 switch (getTypeAction(Tmp2.getValueType())) {
1626 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1629 if (Tmp2.getValueType() != MVT::Vector) {
1631 ExpandOp(Tmp2, Lo, Hi);
1633 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1635 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1636 Result = LegalizeOp(Result);
1638 SDNode *InVal = Tmp2.Val;
1640 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1641 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1643 // Figure out if there is a Packed type corresponding to this Vector
1644 // type. If so, convert to the packed type.
1645 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1646 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1647 // Turn this into a return of the packed type.
1648 Tmp2 = PackVectorOp(Tmp2, TVT);
1649 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1650 } else if (NumElems == 1) {
1651 // Turn this into a return of the scalar type.
1652 Tmp2 = PackVectorOp(Tmp2, EVT);
1653 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1655 // FIXME: Returns of gcc generic vectors smaller than a legal type
1656 // should be returned in integer registers!
1658 // The scalarized value type may not be legal, e.g. it might require
1659 // promotion or expansion. Relegalize the return.
1660 Result = LegalizeOp(Result);
1662 // FIXME: Returns of gcc generic vectors larger than a legal vector
1663 // type should be returned by reference!
1665 SplitVectorOp(Tmp2, Lo, Hi);
1666 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1667 Result = LegalizeOp(Result);
1672 Tmp2 = PromoteOp(Node->getOperand(1));
1673 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1674 Result = LegalizeOp(Result);
1679 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1681 default: { // ret <values>
1682 SmallVector<SDOperand, 8> NewValues;
1683 NewValues.push_back(Tmp1);
1684 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1685 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1687 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1688 NewValues.push_back(Node->getOperand(i+1));
1692 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1693 "FIXME: TODO: implement returning non-legal vector types!");
1694 ExpandOp(Node->getOperand(i), Lo, Hi);
1695 NewValues.push_back(Lo);
1696 NewValues.push_back(Node->getOperand(i+1));
1698 NewValues.push_back(Hi);
1699 NewValues.push_back(Node->getOperand(i+1));
1704 assert(0 && "Can't promote multiple return value yet!");
1707 if (NewValues.size() == Node->getNumOperands())
1708 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1710 Result = DAG.getNode(ISD::RET, MVT::Other,
1711 &NewValues[0], NewValues.size());
1716 if (Result.getOpcode() == ISD::RET) {
1717 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1718 default: assert(0 && "This action is not supported yet!");
1719 case TargetLowering::Legal: break;
1720 case TargetLowering::Custom:
1721 Tmp1 = TLI.LowerOperation(Result, DAG);
1722 if (Tmp1.Val) Result = Tmp1;
1728 StoreSDNode *ST = cast<StoreSDNode>(Node);
1729 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1730 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1732 if (!ST->isTruncatingStore()) {
1733 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1734 // FIXME: We shouldn't do this for TargetConstantFP's.
1735 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1736 // to phase ordering between legalized code and the dag combiner. This
1737 // probably means that we need to integrate dag combiner and legalizer
1739 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1740 if (CFP->getValueType(0) == MVT::f32) {
1741 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1743 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1744 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1746 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1747 ST->getSrcValueOffset());
1751 switch (getTypeAction(ST->getStoredVT())) {
1753 Tmp3 = LegalizeOp(ST->getValue());
1754 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1757 MVT::ValueType VT = Tmp3.getValueType();
1758 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1759 default: assert(0 && "This action is not supported yet!");
1760 case TargetLowering::Legal: break;
1761 case TargetLowering::Custom:
1762 Tmp1 = TLI.LowerOperation(Result, DAG);
1763 if (Tmp1.Val) Result = Tmp1;
1765 case TargetLowering::Promote:
1766 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1767 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1768 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1769 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1770 ST->getSrcValue(), ST->getSrcValueOffset());
1776 // Truncate the value and store the result.
1777 Tmp3 = PromoteOp(ST->getValue());
1778 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1779 ST->getSrcValueOffset(), ST->getStoredVT());
1783 unsigned IncrementSize = 0;
1786 // If this is a vector type, then we have to calculate the increment as
1787 // the product of the element size in bytes, and the number of elements
1788 // in the high half of the vector.
1789 if (ST->getValue().getValueType() == MVT::Vector) {
1790 SDNode *InVal = ST->getValue().Val;
1792 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1793 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1795 // Figure out if there is a Packed type corresponding to this Vector
1796 // type. If so, convert to the packed type.
1797 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1798 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1799 // Turn this into a normal store of the packed type.
1800 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1801 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1802 ST->getSrcValueOffset());
1803 Result = LegalizeOp(Result);
1805 } else if (NumElems == 1) {
1806 // Turn this into a normal store of the scalar type.
1807 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1808 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1809 ST->getSrcValueOffset());
1810 // The scalarized value type may not be legal, e.g. it might require
1811 // promotion or expansion. Relegalize the scalar store.
1812 Result = LegalizeOp(Result);
1815 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1816 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1819 ExpandOp(Node->getOperand(1), Lo, Hi);
1820 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1822 if (!TLI.isLittleEndian())
1826 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1827 ST->getSrcValueOffset());
1829 if (Hi.Val == NULL) {
1830 // Must be int <-> float one-to-one expansion.
1835 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1836 getIntPtrConstant(IncrementSize));
1837 assert(isTypeLegal(Tmp2.getValueType()) &&
1838 "Pointers must be legal!");
1839 // FIXME: This sets the srcvalue of both halves to be the same, which is
1841 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1842 ST->getSrcValueOffset());
1843 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1848 assert(isTypeLegal(ST->getValue().getValueType()) &&
1849 "Cannot handle illegal TRUNCSTORE yet!");
1850 Tmp3 = LegalizeOp(ST->getValue());
1852 // The only promote case we handle is TRUNCSTORE:i1 X into
1853 // -> TRUNCSTORE:i8 (and X, 1)
1854 if (ST->getStoredVT() == MVT::i1 &&
1855 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1856 // Promote the bool to a mask then store.
1857 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1858 DAG.getConstant(1, Tmp3.getValueType()));
1859 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1860 ST->getSrcValueOffset(), MVT::i8);
1861 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1862 Tmp2 != ST->getBasePtr()) {
1863 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1867 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1868 switch (TLI.getStoreXAction(StVT)) {
1869 default: assert(0 && "This action is not supported yet!");
1870 case TargetLowering::Legal: break;
1871 case TargetLowering::Custom:
1872 Tmp1 = TLI.LowerOperation(Result, DAG);
1873 if (Tmp1.Val) Result = Tmp1;
1880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1883 case ISD::STACKSAVE:
1884 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1885 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1886 Tmp1 = Result.getValue(0);
1887 Tmp2 = Result.getValue(1);
1889 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1890 default: assert(0 && "This action is not supported yet!");
1891 case TargetLowering::Legal: break;
1892 case TargetLowering::Custom:
1893 Tmp3 = TLI.LowerOperation(Result, DAG);
1895 Tmp1 = LegalizeOp(Tmp3);
1896 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1899 case TargetLowering::Expand:
1900 // Expand to CopyFromReg if the target set
1901 // StackPointerRegisterToSaveRestore.
1902 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1903 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1904 Node->getValueType(0));
1905 Tmp2 = Tmp1.getValue(1);
1907 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1908 Tmp2 = Node->getOperand(0);
1913 // Since stacksave produce two values, make sure to remember that we
1914 // legalized both of them.
1915 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1916 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1917 return Op.ResNo ? Tmp2 : Tmp1;
1919 case ISD::STACKRESTORE:
1920 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1921 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1924 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1925 default: assert(0 && "This action is not supported yet!");
1926 case TargetLowering::Legal: break;
1927 case TargetLowering::Custom:
1928 Tmp1 = TLI.LowerOperation(Result, DAG);
1929 if (Tmp1.Val) Result = Tmp1;
1931 case TargetLowering::Expand:
1932 // Expand to CopyToReg if the target set
1933 // StackPointerRegisterToSaveRestore.
1934 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1935 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1943 case ISD::READCYCLECOUNTER:
1944 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1945 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1946 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1947 Node->getValueType(0))) {
1948 default: assert(0 && "This action is not supported yet!");
1949 case TargetLowering::Legal:
1950 Tmp1 = Result.getValue(0);
1951 Tmp2 = Result.getValue(1);
1953 case TargetLowering::Custom:
1954 Result = TLI.LowerOperation(Result, DAG);
1955 Tmp1 = LegalizeOp(Result.getValue(0));
1956 Tmp2 = LegalizeOp(Result.getValue(1));
1960 // Since rdcc produce two values, make sure to remember that we legalized
1962 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1963 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1967 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1968 case Expand: assert(0 && "It's impossible to expand bools");
1970 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1973 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1974 // Make sure the condition is either zero or one.
1975 if (!TLI.MaskedValueIsZero(Tmp1,
1976 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
1977 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1980 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1981 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1983 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1985 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1986 default: assert(0 && "This action is not supported yet!");
1987 case TargetLowering::Legal: break;
1988 case TargetLowering::Custom: {
1989 Tmp1 = TLI.LowerOperation(Result, DAG);
1990 if (Tmp1.Val) Result = Tmp1;
1993 case TargetLowering::Expand:
1994 if (Tmp1.getOpcode() == ISD::SETCC) {
1995 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1997 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1999 Result = DAG.getSelectCC(Tmp1,
2000 DAG.getConstant(0, Tmp1.getValueType()),
2001 Tmp2, Tmp3, ISD::SETNE);
2004 case TargetLowering::Promote: {
2005 MVT::ValueType NVT =
2006 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2007 unsigned ExtOp, TruncOp;
2008 if (MVT::isVector(Tmp2.getValueType())) {
2009 ExtOp = ISD::BIT_CONVERT;
2010 TruncOp = ISD::BIT_CONVERT;
2011 } else if (MVT::isInteger(Tmp2.getValueType())) {
2012 ExtOp = ISD::ANY_EXTEND;
2013 TruncOp = ISD::TRUNCATE;
2015 ExtOp = ISD::FP_EXTEND;
2016 TruncOp = ISD::FP_ROUND;
2018 // Promote each of the values to the new type.
2019 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2020 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2021 // Perform the larger operation, then round down.
2022 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2023 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2028 case ISD::SELECT_CC: {
2029 Tmp1 = Node->getOperand(0); // LHS
2030 Tmp2 = Node->getOperand(1); // RHS
2031 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2032 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2033 SDOperand CC = Node->getOperand(4);
2035 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2037 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2038 // the LHS is a legal SETCC itself. In this case, we need to compare
2039 // the result against zero to select between true and false values.
2040 if (Tmp2.Val == 0) {
2041 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2042 CC = DAG.getCondCode(ISD::SETNE);
2044 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2046 // Everything is legal, see if we should expand this op or something.
2047 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2048 default: assert(0 && "This action is not supported yet!");
2049 case TargetLowering::Legal: break;
2050 case TargetLowering::Custom:
2051 Tmp1 = TLI.LowerOperation(Result, DAG);
2052 if (Tmp1.Val) Result = Tmp1;
2058 Tmp1 = Node->getOperand(0);
2059 Tmp2 = Node->getOperand(1);
2060 Tmp3 = Node->getOperand(2);
2061 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2063 // If we had to Expand the SetCC operands into a SELECT node, then it may
2064 // not always be possible to return a true LHS & RHS. In this case, just
2065 // return the value we legalized, returned in the LHS
2066 if (Tmp2.Val == 0) {
2071 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2072 default: assert(0 && "Cannot handle this action for SETCC yet!");
2073 case TargetLowering::Custom:
2076 case TargetLowering::Legal:
2077 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2079 Tmp4 = TLI.LowerOperation(Result, DAG);
2080 if (Tmp4.Val) Result = Tmp4;
2083 case TargetLowering::Promote: {
2084 // First step, figure out the appropriate operation to use.
2085 // Allow SETCC to not be supported for all legal data types
2086 // Mostly this targets FP
2087 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2088 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2090 // Scan for the appropriate larger type to use.
2092 NewInTy = (MVT::ValueType)(NewInTy+1);
2094 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2095 "Fell off of the edge of the integer world");
2096 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2097 "Fell off of the edge of the floating point world");
2099 // If the target supports SETCC of this type, use it.
2100 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2103 if (MVT::isInteger(NewInTy))
2104 assert(0 && "Cannot promote Legal Integer SETCC yet");
2106 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2107 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2109 Tmp1 = LegalizeOp(Tmp1);
2110 Tmp2 = LegalizeOp(Tmp2);
2111 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2112 Result = LegalizeOp(Result);
2115 case TargetLowering::Expand:
2116 // Expand a setcc node into a select_cc of the same condition, lhs, and
2117 // rhs that selects between const 1 (true) and const 0 (false).
2118 MVT::ValueType VT = Node->getValueType(0);
2119 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2120 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2127 case ISD::MEMMOVE: {
2128 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2129 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2131 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2132 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2133 case Expand: assert(0 && "Cannot expand a byte!");
2135 Tmp3 = LegalizeOp(Node->getOperand(2));
2138 Tmp3 = PromoteOp(Node->getOperand(2));
2142 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2146 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2148 // Length is too big, just take the lo-part of the length.
2150 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2154 Tmp4 = LegalizeOp(Node->getOperand(3));
2157 Tmp4 = PromoteOp(Node->getOperand(3));
2162 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2163 case Expand: assert(0 && "Cannot expand this yet!");
2165 Tmp5 = LegalizeOp(Node->getOperand(4));
2168 Tmp5 = PromoteOp(Node->getOperand(4));
2172 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2173 default: assert(0 && "This action not implemented for this operation!");
2174 case TargetLowering::Custom:
2177 case TargetLowering::Legal:
2178 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2180 Tmp1 = TLI.LowerOperation(Result, DAG);
2181 if (Tmp1.Val) Result = Tmp1;
2184 case TargetLowering::Expand: {
2185 // Otherwise, the target does not support this operation. Lower the
2186 // operation to an explicit libcall as appropriate.
2187 MVT::ValueType IntPtr = TLI.getPointerTy();
2188 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2189 TargetLowering::ArgListTy Args;
2190 TargetLowering::ArgListEntry Entry;
2192 const char *FnName = 0;
2193 if (Node->getOpcode() == ISD::MEMSET) {
2194 Entry.Node = Tmp2; Entry.isSigned = false; Entry.Ty = IntPtrTy;
2195 Entry.isInReg = false; Entry.isSRet = false;
2196 Args.push_back(Entry);
2197 // Extend the (previously legalized) ubyte argument to be an int value
2199 if (Tmp3.getValueType() > MVT::i32)
2200 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2202 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2203 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSigned = true;
2204 Entry.isInReg = false; Entry.isSRet = false;
2205 Args.push_back(Entry);
2206 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSigned = false;
2207 Args.push_back(Entry);
2210 } else if (Node->getOpcode() == ISD::MEMCPY ||
2211 Node->getOpcode() == ISD::MEMMOVE) {
2212 Entry.Ty = IntPtrTy;
2213 Entry.isSigned = false; Entry.isInReg = false; Entry.isSRet = false;
2214 Entry.Node = Tmp2; Args.push_back(Entry);
2215 Entry.Node = Tmp3; Args.push_back(Entry);
2216 Entry.Node = Tmp4; Args.push_back(Entry);
2217 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2219 assert(0 && "Unknown op!");
2222 std::pair<SDOperand,SDOperand> CallResult =
2223 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2224 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2225 Result = CallResult.second;
2232 case ISD::SHL_PARTS:
2233 case ISD::SRA_PARTS:
2234 case ISD::SRL_PARTS: {
2235 SmallVector<SDOperand, 8> Ops;
2236 bool Changed = false;
2237 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2238 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2239 Changed |= Ops.back() != Node->getOperand(i);
2242 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2244 switch (TLI.getOperationAction(Node->getOpcode(),
2245 Node->getValueType(0))) {
2246 default: assert(0 && "This action is not supported yet!");
2247 case TargetLowering::Legal: break;
2248 case TargetLowering::Custom:
2249 Tmp1 = TLI.LowerOperation(Result, DAG);
2251 SDOperand Tmp2, RetVal(0, 0);
2252 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2253 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2254 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2258 assert(RetVal.Val && "Illegal result number");
2264 // Since these produce multiple values, make sure to remember that we
2265 // legalized all of them.
2266 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2267 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2268 return Result.getValue(Op.ResNo);
2289 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2290 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2291 case Expand: assert(0 && "Not possible");
2293 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2296 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2300 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2302 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2303 default: assert(0 && "BinOp legalize operation not supported");
2304 case TargetLowering::Legal: break;
2305 case TargetLowering::Custom:
2306 Tmp1 = TLI.LowerOperation(Result, DAG);
2307 if (Tmp1.Val) Result = Tmp1;
2309 case TargetLowering::Expand: {
2310 if (Node->getValueType(0) == MVT::i32) {
2311 switch (Node->getOpcode()) {
2312 default: assert(0 && "Do not know how to expand this integer BinOp!");
2315 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2316 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2318 bool isSigned = Node->getOpcode() == ISD::SDIV;
2319 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2324 assert(MVT::isVector(Node->getValueType(0)) &&
2325 "Cannot expand this binary operator!");
2326 // Expand the operation into a bunch of nasty scalar code.
2327 SmallVector<SDOperand, 8> Ops;
2328 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2329 MVT::ValueType PtrVT = TLI.getPointerTy();
2330 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2332 SDOperand Idx = DAG.getConstant(i, PtrVT);
2333 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2334 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2335 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2337 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2338 &Ops[0], Ops.size());
2341 case TargetLowering::Promote: {
2342 switch (Node->getOpcode()) {
2343 default: assert(0 && "Do not know how to promote this BinOp!");
2347 MVT::ValueType OVT = Node->getValueType(0);
2348 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2349 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2350 // Bit convert each of the values to the new type.
2351 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2352 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2353 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2354 // Bit convert the result back the original type.
2355 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2363 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2364 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2365 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2366 case Expand: assert(0 && "Not possible");
2368 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2371 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2375 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2377 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2378 default: assert(0 && "Operation not supported");
2379 case TargetLowering::Custom:
2380 Tmp1 = TLI.LowerOperation(Result, DAG);
2381 if (Tmp1.Val) Result = Tmp1;
2383 case TargetLowering::Legal: break;
2384 case TargetLowering::Expand: {
2385 // If this target supports fabs/fneg natively and select is cheap,
2386 // do this efficiently.
2387 if (!TLI.isSelectExpensive() &&
2388 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2389 TargetLowering::Legal &&
2390 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2391 TargetLowering::Legal) {
2392 // Get the sign bit of the RHS.
2393 MVT::ValueType IVT =
2394 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2395 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2396 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2397 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2398 // Get the absolute value of the result.
2399 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2400 // Select between the nabs and abs value based on the sign bit of
2402 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2403 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2406 Result = LegalizeOp(Result);
2410 // Otherwise, do bitwise ops!
2411 MVT::ValueType NVT =
2412 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2413 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2414 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2415 Result = LegalizeOp(Result);
2423 Tmp1 = LegalizeOp(Node->getOperand(0));
2424 Tmp2 = LegalizeOp(Node->getOperand(1));
2425 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2426 // Since this produces two values, make sure to remember that we legalized
2428 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2429 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2434 Tmp1 = LegalizeOp(Node->getOperand(0));
2435 Tmp2 = LegalizeOp(Node->getOperand(1));
2436 Tmp3 = LegalizeOp(Node->getOperand(2));
2437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2438 // Since this produces two values, make sure to remember that we legalized
2440 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2441 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2444 case ISD::BUILD_PAIR: {
2445 MVT::ValueType PairTy = Node->getValueType(0);
2446 // TODO: handle the case where the Lo and Hi operands are not of legal type
2447 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2448 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2449 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2450 case TargetLowering::Promote:
2451 case TargetLowering::Custom:
2452 assert(0 && "Cannot promote/custom this yet!");
2453 case TargetLowering::Legal:
2454 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2455 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2457 case TargetLowering::Expand:
2458 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2459 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2460 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2461 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2462 TLI.getShiftAmountTy()));
2463 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2472 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2473 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2475 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2476 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2477 case TargetLowering::Custom:
2480 case TargetLowering::Legal:
2481 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2483 Tmp1 = TLI.LowerOperation(Result, DAG);
2484 if (Tmp1.Val) Result = Tmp1;
2487 case TargetLowering::Expand:
2488 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2489 bool isSigned = DivOpc == ISD::SDIV;
2490 if (MVT::isInteger(Node->getValueType(0))) {
2491 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2492 TargetLowering::Legal) {
2494 MVT::ValueType VT = Node->getValueType(0);
2495 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2496 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2497 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2499 assert(Node->getValueType(0) == MVT::i32 &&
2500 "Cannot expand this binary operator!");
2501 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2502 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2504 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2507 // Floating point mod -> fmod libcall.
2508 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2509 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2511 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2512 false/*sign irrelevant*/, Dummy);
2518 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2519 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2521 MVT::ValueType VT = Node->getValueType(0);
2522 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2523 default: assert(0 && "This action is not supported yet!");
2524 case TargetLowering::Custom:
2527 case TargetLowering::Legal:
2528 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2529 Result = Result.getValue(0);
2530 Tmp1 = Result.getValue(1);
2533 Tmp2 = TLI.LowerOperation(Result, DAG);
2535 Result = LegalizeOp(Tmp2);
2536 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2540 case TargetLowering::Expand: {
2541 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2542 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2543 SV->getValue(), SV->getOffset());
2544 // Increment the pointer, VAList, to the next vaarg
2545 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2546 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2547 TLI.getPointerTy()));
2548 // Store the incremented VAList to the legalized pointer
2549 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2551 // Load the actual argument out of the pointer VAList
2552 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2553 Tmp1 = LegalizeOp(Result.getValue(1));
2554 Result = LegalizeOp(Result);
2558 // Since VAARG produces two values, make sure to remember that we
2559 // legalized both of them.
2560 AddLegalizedOperand(SDOperand(Node, 0), Result);
2561 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2562 return Op.ResNo ? Tmp1 : Result;
2566 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2567 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2568 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2570 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2571 default: assert(0 && "This action is not supported yet!");
2572 case TargetLowering::Custom:
2575 case TargetLowering::Legal:
2576 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2577 Node->getOperand(3), Node->getOperand(4));
2579 Tmp1 = TLI.LowerOperation(Result, DAG);
2580 if (Tmp1.Val) Result = Tmp1;
2583 case TargetLowering::Expand:
2584 // This defaults to loading a pointer from the input and storing it to the
2585 // output, returning the chain.
2586 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2587 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2588 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2590 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2597 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2598 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2600 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2601 default: assert(0 && "This action is not supported yet!");
2602 case TargetLowering::Custom:
2605 case TargetLowering::Legal:
2606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2608 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2609 if (Tmp1.Val) Result = Tmp1;
2612 case TargetLowering::Expand:
2613 Result = Tmp1; // Default to a no-op, return the chain
2619 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2620 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2624 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2625 default: assert(0 && "This action is not supported yet!");
2626 case TargetLowering::Legal: break;
2627 case TargetLowering::Custom:
2628 Tmp1 = TLI.LowerOperation(Result, DAG);
2629 if (Tmp1.Val) Result = Tmp1;
2636 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2637 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2639 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2640 "Cannot handle this yet!");
2641 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2645 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2646 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2647 case TargetLowering::Custom:
2648 assert(0 && "Cannot custom legalize this yet!");
2649 case TargetLowering::Legal:
2650 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2652 case TargetLowering::Promote: {
2653 MVT::ValueType OVT = Tmp1.getValueType();
2654 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2655 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2657 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2658 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2659 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2660 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2663 case TargetLowering::Expand:
2664 Result = ExpandBSWAP(Tmp1);
2672 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2673 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2674 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2675 case TargetLowering::Legal:
2676 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2678 case TargetLowering::Promote: {
2679 MVT::ValueType OVT = Tmp1.getValueType();
2680 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2682 // Zero extend the argument.
2683 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2684 // Perform the larger operation, then subtract if needed.
2685 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2686 switch (Node->getOpcode()) {
2691 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2692 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2693 DAG.getConstant(getSizeInBits(NVT), NVT),
2695 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2696 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2699 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2700 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2701 DAG.getConstant(getSizeInBits(NVT) -
2702 getSizeInBits(OVT), NVT));
2707 case TargetLowering::Expand:
2708 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2719 Tmp1 = LegalizeOp(Node->getOperand(0));
2720 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2721 case TargetLowering::Promote:
2722 case TargetLowering::Custom:
2725 case TargetLowering::Legal:
2726 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2728 Tmp1 = TLI.LowerOperation(Result, DAG);
2729 if (Tmp1.Val) Result = Tmp1;
2732 case TargetLowering::Expand:
2733 switch (Node->getOpcode()) {
2734 default: assert(0 && "Unreachable!");
2736 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2737 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2738 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2741 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2742 MVT::ValueType VT = Node->getValueType(0);
2743 Tmp2 = DAG.getConstantFP(0.0, VT);
2744 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2745 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2746 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2752 MVT::ValueType VT = Node->getValueType(0);
2753 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2754 switch(Node->getOpcode()) {
2756 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2759 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2762 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2764 default: assert(0 && "Unreachable!");
2767 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2768 false/*sign irrelevant*/, Dummy);
2776 // We always lower FPOWI into a libcall. No target support it yet.
2777 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2778 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2780 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2781 false/*sign irrelevant*/, Dummy);
2784 case ISD::BIT_CONVERT:
2785 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2786 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2788 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2789 Node->getOperand(0).getValueType())) {
2790 default: assert(0 && "Unknown operation action!");
2791 case TargetLowering::Expand:
2792 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2794 case TargetLowering::Legal:
2795 Tmp1 = LegalizeOp(Node->getOperand(0));
2796 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2801 case ISD::VBIT_CONVERT: {
2802 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2803 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2805 // The input has to be a vector type, we have to either scalarize it, pack
2806 // it, or convert it based on whether the input vector type is legal.
2807 SDNode *InVal = Node->getOperand(0).Val;
2809 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2810 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2812 // Figure out if there is a Packed type corresponding to this Vector
2813 // type. If so, convert to the packed type.
2814 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2815 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2816 // Turn this into a bit convert of the packed input.
2817 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2818 PackVectorOp(Node->getOperand(0), TVT));
2820 } else if (NumElems == 1) {
2821 // Turn this into a bit convert of the scalar input.
2822 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2823 PackVectorOp(Node->getOperand(0), EVT));
2826 // FIXME: UNIMP! Store then reload
2827 assert(0 && "Cast from unsupported vector type not implemented yet!");
2831 // Conversion operators. The source and destination have different types.
2832 case ISD::SINT_TO_FP:
2833 case ISD::UINT_TO_FP: {
2834 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2835 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2837 switch (TLI.getOperationAction(Node->getOpcode(),
2838 Node->getOperand(0).getValueType())) {
2839 default: assert(0 && "Unknown operation action!");
2840 case TargetLowering::Custom:
2843 case TargetLowering::Legal:
2844 Tmp1 = LegalizeOp(Node->getOperand(0));
2845 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2847 Tmp1 = TLI.LowerOperation(Result, DAG);
2848 if (Tmp1.Val) Result = Tmp1;
2851 case TargetLowering::Expand:
2852 Result = ExpandLegalINT_TO_FP(isSigned,
2853 LegalizeOp(Node->getOperand(0)),
2854 Node->getValueType(0));
2856 case TargetLowering::Promote:
2857 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2858 Node->getValueType(0),
2864 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2865 Node->getValueType(0), Node->getOperand(0));
2868 Tmp1 = PromoteOp(Node->getOperand(0));
2870 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2871 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2873 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2874 Node->getOperand(0).getValueType());
2876 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2877 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2883 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2885 Tmp1 = LegalizeOp(Node->getOperand(0));
2886 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2889 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2891 // Since the result is legal, we should just be able to truncate the low
2892 // part of the source.
2893 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2896 Result = PromoteOp(Node->getOperand(0));
2897 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2902 case ISD::FP_TO_SINT:
2903 case ISD::FP_TO_UINT:
2904 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2906 Tmp1 = LegalizeOp(Node->getOperand(0));
2908 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2909 default: assert(0 && "Unknown operation action!");
2910 case TargetLowering::Custom:
2913 case TargetLowering::Legal:
2914 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2916 Tmp1 = TLI.LowerOperation(Result, DAG);
2917 if (Tmp1.Val) Result = Tmp1;
2920 case TargetLowering::Promote:
2921 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2922 Node->getOpcode() == ISD::FP_TO_SINT);
2924 case TargetLowering::Expand:
2925 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2926 SDOperand True, False;
2927 MVT::ValueType VT = Node->getOperand(0).getValueType();
2928 MVT::ValueType NVT = Node->getValueType(0);
2929 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2930 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2931 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2932 Node->getOperand(0), Tmp2, ISD::SETLT);
2933 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2934 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2935 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2937 False = DAG.getNode(ISD::XOR, NVT, False,
2938 DAG.getConstant(1ULL << ShiftAmt, NVT));
2939 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2942 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2948 // Convert f32 / f64 to i32 / i64.
2949 MVT::ValueType VT = Op.getValueType();
2950 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2951 switch (Node->getOpcode()) {
2952 case ISD::FP_TO_SINT:
2953 if (Node->getOperand(0).getValueType() == MVT::f32)
2954 LC = (VT == MVT::i32)
2955 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
2957 LC = (VT == MVT::i32)
2958 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
2960 case ISD::FP_TO_UINT:
2961 if (Node->getOperand(0).getValueType() == MVT::f32)
2962 LC = (VT == MVT::i32)
2963 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
2965 LC = (VT == MVT::i32)
2966 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
2968 default: assert(0 && "Unreachable!");
2971 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2972 false/*sign irrelevant*/, Dummy);
2976 Tmp1 = PromoteOp(Node->getOperand(0));
2977 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2978 Result = LegalizeOp(Result);
2983 case ISD::ANY_EXTEND:
2984 case ISD::ZERO_EXTEND:
2985 case ISD::SIGN_EXTEND:
2986 case ISD::FP_EXTEND:
2988 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2989 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2991 Tmp1 = LegalizeOp(Node->getOperand(0));
2992 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2995 switch (Node->getOpcode()) {
2996 case ISD::ANY_EXTEND:
2997 Tmp1 = PromoteOp(Node->getOperand(0));
2998 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3000 case ISD::ZERO_EXTEND:
3001 Result = PromoteOp(Node->getOperand(0));
3002 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3003 Result = DAG.getZeroExtendInReg(Result,
3004 Node->getOperand(0).getValueType());
3006 case ISD::SIGN_EXTEND:
3007 Result = PromoteOp(Node->getOperand(0));
3008 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3009 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3011 DAG.getValueType(Node->getOperand(0).getValueType()));
3013 case ISD::FP_EXTEND:
3014 Result = PromoteOp(Node->getOperand(0));
3015 if (Result.getValueType() != Op.getValueType())
3016 // Dynamically dead while we have only 2 FP types.
3017 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3020 Result = PromoteOp(Node->getOperand(0));
3021 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3026 case ISD::FP_ROUND_INREG:
3027 case ISD::SIGN_EXTEND_INREG: {
3028 Tmp1 = LegalizeOp(Node->getOperand(0));
3029 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3031 // If this operation is not supported, convert it to a shl/shr or load/store
3033 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3034 default: assert(0 && "This action not supported for this op yet!");
3035 case TargetLowering::Legal:
3036 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3038 case TargetLowering::Expand:
3039 // If this is an integer extend and shifts are supported, do that.
3040 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3041 // NOTE: we could fall back on load/store here too for targets without
3042 // SAR. However, it is doubtful that any exist.
3043 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3044 MVT::getSizeInBits(ExtraVT);
3045 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3046 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3047 Node->getOperand(0), ShiftCst);
3048 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3050 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3051 // The only way we can lower this is to turn it into a TRUNCSTORE,
3052 // EXTLOAD pair, targetting a temporary location (a stack slot).
3054 // NOTE: there is a choice here between constantly creating new stack
3055 // slots and always reusing the same one. We currently always create
3056 // new ones, as reuse may inhibit scheduling.
3057 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3058 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
3059 unsigned Align = TLI.getTargetData()->getTypeAlignmentPref(Ty);
3060 MachineFunction &MF = DAG.getMachineFunction();
3062 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
3063 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3064 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3065 StackSlot, NULL, 0, ExtraVT);
3066 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3067 Result, StackSlot, NULL, 0, ExtraVT);
3069 assert(0 && "Unknown op");
3077 assert(Result.getValueType() == Op.getValueType() &&
3078 "Bad legalization!");
3080 // Make sure that the generated code is itself legal.
3082 Result = LegalizeOp(Result);
3084 // Note that LegalizeOp may be reentered even from single-use nodes, which
3085 // means that we always must cache transformed nodes.
3086 AddLegalizedOperand(Op, Result);
3090 /// PromoteOp - Given an operation that produces a value in an invalid type,
3091 /// promote it to compute the value into a larger type. The produced value will
3092 /// have the correct bits for the low portion of the register, but no guarantee
3093 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3094 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3095 MVT::ValueType VT = Op.getValueType();
3096 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3097 assert(getTypeAction(VT) == Promote &&
3098 "Caller should expand or legalize operands that are not promotable!");
3099 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3100 "Cannot promote to smaller type!");
3102 SDOperand Tmp1, Tmp2, Tmp3;
3104 SDNode *Node = Op.Val;
3106 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3107 if (I != PromotedNodes.end()) return I->second;
3109 switch (Node->getOpcode()) {
3110 case ISD::CopyFromReg:
3111 assert(0 && "CopyFromReg must be legal!");
3114 cerr << "NODE: "; Node->dump(); cerr << "\n";
3116 assert(0 && "Do not know how to promote this operator!");
3119 Result = DAG.getNode(ISD::UNDEF, NVT);
3123 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3125 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3126 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3128 case ISD::ConstantFP:
3129 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3130 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3134 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3135 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3136 Node->getOperand(1), Node->getOperand(2));
3140 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3142 Result = LegalizeOp(Node->getOperand(0));
3143 assert(Result.getValueType() >= NVT &&
3144 "This truncation doesn't make sense!");
3145 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3146 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3149 // The truncation is not required, because we don't guarantee anything
3150 // about high bits anyway.
3151 Result = PromoteOp(Node->getOperand(0));
3154 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3155 // Truncate the low part of the expanded value to the result type
3156 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3159 case ISD::SIGN_EXTEND:
3160 case ISD::ZERO_EXTEND:
3161 case ISD::ANY_EXTEND:
3162 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3163 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3165 // Input is legal? Just do extend all the way to the larger type.
3166 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3169 // Promote the reg if it's smaller.
3170 Result = PromoteOp(Node->getOperand(0));
3171 // The high bits are not guaranteed to be anything. Insert an extend.
3172 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3173 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3174 DAG.getValueType(Node->getOperand(0).getValueType()));
3175 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3176 Result = DAG.getZeroExtendInReg(Result,
3177 Node->getOperand(0).getValueType());
3181 case ISD::BIT_CONVERT:
3182 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3183 Result = PromoteOp(Result);
3186 case ISD::FP_EXTEND:
3187 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3189 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3190 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3191 case Promote: assert(0 && "Unreachable with 2 FP types!");
3193 // Input is legal? Do an FP_ROUND_INREG.
3194 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3195 DAG.getValueType(VT));
3200 case ISD::SINT_TO_FP:
3201 case ISD::UINT_TO_FP:
3202 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3204 // No extra round required here.
3205 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3209 Result = PromoteOp(Node->getOperand(0));
3210 if (Node->getOpcode() == ISD::SINT_TO_FP)
3211 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3213 DAG.getValueType(Node->getOperand(0).getValueType()));
3215 Result = DAG.getZeroExtendInReg(Result,
3216 Node->getOperand(0).getValueType());
3217 // No extra round required here.
3218 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3221 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3222 Node->getOperand(0));
3223 // Round if we cannot tolerate excess precision.
3224 if (NoExcessFPPrecision)
3225 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3226 DAG.getValueType(VT));
3231 case ISD::SIGN_EXTEND_INREG:
3232 Result = PromoteOp(Node->getOperand(0));
3233 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3234 Node->getOperand(1));
3236 case ISD::FP_TO_SINT:
3237 case ISD::FP_TO_UINT:
3238 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3241 Tmp1 = Node->getOperand(0);
3244 // The input result is prerounded, so we don't have to do anything
3246 Tmp1 = PromoteOp(Node->getOperand(0));
3249 // If we're promoting a UINT to a larger size, check to see if the new node
3250 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3251 // we can use that instead. This allows us to generate better code for
3252 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3253 // legal, such as PowerPC.
3254 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3255 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3256 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3257 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3258 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3260 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3266 Tmp1 = PromoteOp(Node->getOperand(0));
3267 assert(Tmp1.getValueType() == NVT);
3268 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3269 // NOTE: we do not have to do any extra rounding here for
3270 // NoExcessFPPrecision, because we know the input will have the appropriate
3271 // precision, and these operations don't modify precision at all.
3277 Tmp1 = PromoteOp(Node->getOperand(0));
3278 assert(Tmp1.getValueType() == NVT);
3279 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3280 if (NoExcessFPPrecision)
3281 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3282 DAG.getValueType(VT));
3291 // The input may have strange things in the top bits of the registers, but
3292 // these operations don't care. They may have weird bits going out, but
3293 // that too is okay if they are integer operations.
3294 Tmp1 = PromoteOp(Node->getOperand(0));
3295 Tmp2 = PromoteOp(Node->getOperand(1));
3296 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3297 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3302 Tmp1 = PromoteOp(Node->getOperand(0));
3303 Tmp2 = PromoteOp(Node->getOperand(1));
3304 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3305 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3307 // Floating point operations will give excess precision that we may not be
3308 // able to tolerate. If we DO allow excess precision, just leave it,
3309 // otherwise excise it.
3310 // FIXME: Why would we need to round FP ops more than integer ones?
3311 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3312 if (NoExcessFPPrecision)
3313 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3314 DAG.getValueType(VT));
3319 // These operators require that their input be sign extended.
3320 Tmp1 = PromoteOp(Node->getOperand(0));
3321 Tmp2 = PromoteOp(Node->getOperand(1));
3322 if (MVT::isInteger(NVT)) {
3323 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3324 DAG.getValueType(VT));
3325 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3326 DAG.getValueType(VT));
3328 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3330 // Perform FP_ROUND: this is probably overly pessimistic.
3331 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3332 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3333 DAG.getValueType(VT));
3337 case ISD::FCOPYSIGN:
3338 // These operators require that their input be fp extended.
3339 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3341 Tmp1 = LegalizeOp(Node->getOperand(0));
3344 Tmp1 = PromoteOp(Node->getOperand(0));
3347 assert(0 && "not implemented");
3349 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3351 Tmp2 = LegalizeOp(Node->getOperand(1));
3354 Tmp2 = PromoteOp(Node->getOperand(1));
3357 assert(0 && "not implemented");
3359 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3361 // Perform FP_ROUND: this is probably overly pessimistic.
3362 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3363 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3364 DAG.getValueType(VT));
3369 // These operators require that their input be zero extended.
3370 Tmp1 = PromoteOp(Node->getOperand(0));
3371 Tmp2 = PromoteOp(Node->getOperand(1));
3372 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3373 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3374 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3375 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3379 Tmp1 = PromoteOp(Node->getOperand(0));
3380 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3383 // The input value must be properly sign extended.
3384 Tmp1 = PromoteOp(Node->getOperand(0));
3385 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3386 DAG.getValueType(VT));
3387 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3390 // The input value must be properly zero extended.
3391 Tmp1 = PromoteOp(Node->getOperand(0));
3392 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3393 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3397 Tmp1 = Node->getOperand(0); // Get the chain.
3398 Tmp2 = Node->getOperand(1); // Get the pointer.
3399 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3400 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3401 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3403 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3404 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3405 SV->getValue(), SV->getOffset());
3406 // Increment the pointer, VAList, to the next vaarg
3407 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3408 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3409 TLI.getPointerTy()));
3410 // Store the incremented VAList to the legalized pointer
3411 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3413 // Load the actual argument out of the pointer VAList
3414 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3416 // Remember that we legalized the chain.
3417 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3421 LoadSDNode *LD = cast<LoadSDNode>(Node);
3422 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3423 ? ISD::EXTLOAD : LD->getExtensionType();
3424 Result = DAG.getExtLoad(ExtType, NVT,
3425 LD->getChain(), LD->getBasePtr(),
3426 LD->getSrcValue(), LD->getSrcValueOffset(),
3428 // Remember that we legalized the chain.
3429 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3433 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3434 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3435 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3437 case ISD::SELECT_CC:
3438 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3439 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3440 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3441 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3444 Tmp1 = Node->getOperand(0);
3445 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3446 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3447 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3448 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3449 TLI.getShiftAmountTy()));
3454 // Zero extend the argument
3455 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3456 // Perform the larger operation, then subtract if needed.
3457 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3458 switch(Node->getOpcode()) {
3463 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3464 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3465 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3466 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3467 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3470 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3471 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3472 DAG.getConstant(getSizeInBits(NVT) -
3473 getSizeInBits(VT), NVT));
3477 case ISD::VEXTRACT_VECTOR_ELT:
3478 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3480 case ISD::EXTRACT_VECTOR_ELT:
3481 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3485 assert(Result.Val && "Didn't set a result!");
3487 // Make sure the result is itself legal.
3488 Result = LegalizeOp(Result);
3490 // Remember that we promoted this!
3491 AddPromotedOperand(Op, Result);
3495 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3496 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3497 /// on the vector type. The return type of this matches the element type of the
3498 /// vector, which may not be legal for the target.
3499 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3500 // We know that operand #0 is the Vec vector. If the index is a constant
3501 // or if the invec is a supported hardware type, we can use it. Otherwise,
3502 // lower to a store then an indexed load.
3503 SDOperand Vec = Op.getOperand(0);
3504 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3506 SDNode *InVal = Vec.Val;
3507 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3508 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3510 // Figure out if there is a Packed type corresponding to this Vector
3511 // type. If so, convert to the packed type.
3512 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3513 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3514 // Turn this into a packed extract_vector_elt operation.
3515 Vec = PackVectorOp(Vec, TVT);
3516 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3517 } else if (NumElems == 1) {
3518 // This must be an access of the only element. Return it.
3519 return PackVectorOp(Vec, EVT);
3520 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3522 SplitVectorOp(Vec, Lo, Hi);
3523 if (CIdx->getValue() < NumElems/2) {
3527 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3530 // It's now an extract from the appropriate high or low part. Recurse.
3531 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3532 return LowerVEXTRACT_VECTOR_ELT(Op);
3534 // Variable index case for extract element.
3535 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3536 assert(0 && "unimp!");
3541 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3543 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3544 SDOperand Vector = Op.getOperand(0);
3545 SDOperand Idx = Op.getOperand(1);
3547 // If the target doesn't support this, store the value to a temporary
3548 // stack slot, then LOAD the scalar element back out.
3549 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3550 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3552 // Add the offset to the index.
3553 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3554 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3555 DAG.getConstant(EltSize, Idx.getValueType()));
3556 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3558 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3562 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3563 /// with condition CC on the current target. This usually involves legalizing
3564 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3565 /// there may be no choice but to create a new SetCC node to represent the
3566 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3567 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3568 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3571 SDOperand Tmp1, Tmp2, Result;
3573 switch (getTypeAction(LHS.getValueType())) {
3575 Tmp1 = LegalizeOp(LHS); // LHS
3576 Tmp2 = LegalizeOp(RHS); // RHS
3579 Tmp1 = PromoteOp(LHS); // LHS
3580 Tmp2 = PromoteOp(RHS); // RHS
3582 // If this is an FP compare, the operands have already been extended.
3583 if (MVT::isInteger(LHS.getValueType())) {
3584 MVT::ValueType VT = LHS.getValueType();
3585 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3587 // Otherwise, we have to insert explicit sign or zero extends. Note
3588 // that we could insert sign extends for ALL conditions, but zero extend
3589 // is cheaper on many machines (an AND instead of two shifts), so prefer
3591 switch (cast<CondCodeSDNode>(CC)->get()) {
3592 default: assert(0 && "Unknown integer comparison!");
3599 // ALL of these operations will work if we either sign or zero extend
3600 // the operands (including the unsigned comparisons!). Zero extend is
3601 // usually a simpler/cheaper operation, so prefer it.
3602 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3603 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3609 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3610 DAG.getValueType(VT));
3611 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3612 DAG.getValueType(VT));
3618 MVT::ValueType VT = LHS.getValueType();
3619 if (VT == MVT::f32 || VT == MVT::f64) {
3620 // Expand into one or more soft-fp libcall(s).
3621 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3622 switch (cast<CondCodeSDNode>(CC)->get()) {
3625 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3629 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3633 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3637 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3641 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3645 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3648 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3651 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3654 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3655 switch (cast<CondCodeSDNode>(CC)->get()) {
3657 // SETONE = SETOLT | SETOGT
3658 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3661 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3664 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3667 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3670 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3673 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3675 default: assert(0 && "Unsupported FP setcc!");
3680 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3681 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3682 false /*sign irrelevant*/, Dummy);
3683 Tmp2 = DAG.getConstant(0, MVT::i32);
3684 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
3685 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3686 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3687 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3688 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3689 false /*sign irrelevant*/, Dummy);
3690 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3691 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
3692 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3700 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3701 ExpandOp(LHS, LHSLo, LHSHi);
3702 ExpandOp(RHS, RHSLo, RHSHi);
3703 switch (cast<CondCodeSDNode>(CC)->get()) {
3707 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3708 if (RHSCST->isAllOnesValue()) {
3709 // Comparison to -1.
3710 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3715 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3716 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3717 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3718 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3721 // If this is a comparison of the sign bit, just look at the top part.
3723 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3724 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3725 CST->getValue() == 0) || // X < 0
3726 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3727 CST->isAllOnesValue())) { // X > -1
3733 // FIXME: This generated code sucks.
3734 ISD::CondCode LowCC;
3735 switch (cast<CondCodeSDNode>(CC)->get()) {
3736 default: assert(0 && "Unknown integer setcc!");
3738 case ISD::SETULT: LowCC = ISD::SETULT; break;
3740 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3742 case ISD::SETULE: LowCC = ISD::SETULE; break;
3744 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3747 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3748 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3749 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3751 // NOTE: on targets without efficient SELECT of bools, we can always use
3752 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3753 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3754 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3755 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3756 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3757 Result, Tmp1, Tmp2));
3767 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3768 /// The resultant code need not be legal. Note that SrcOp is the input operand
3769 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3770 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3772 // Create the stack frame object.
3773 SDOperand FIPtr = CreateStackTemporary(DestVT);
3775 // Emit a store to the stack slot.
3776 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3777 // Result is a load from the stack slot.
3778 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3781 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3782 // Create a vector sized/aligned stack slot, store the value to element #0,
3783 // then load the whole vector back out.
3784 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3785 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3787 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3791 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3792 /// support the operation, but do support the resultant packed vector type.
3793 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3795 // If the only non-undef value is the low element, turn this into a
3796 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3797 unsigned NumElems = Node->getNumOperands();
3798 bool isOnlyLowElement = true;
3799 SDOperand SplatValue = Node->getOperand(0);
3800 std::map<SDOperand, std::vector<unsigned> > Values;
3801 Values[SplatValue].push_back(0);
3802 bool isConstant = true;
3803 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3804 SplatValue.getOpcode() != ISD::UNDEF)
3807 for (unsigned i = 1; i < NumElems; ++i) {
3808 SDOperand V = Node->getOperand(i);
3809 Values[V].push_back(i);
3810 if (V.getOpcode() != ISD::UNDEF)
3811 isOnlyLowElement = false;
3812 if (SplatValue != V)
3813 SplatValue = SDOperand(0,0);
3815 // If this isn't a constant element or an undef, we can't use a constant
3817 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3818 V.getOpcode() != ISD::UNDEF)
3822 if (isOnlyLowElement) {
3823 // If the low element is an undef too, then this whole things is an undef.
3824 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3825 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3826 // Otherwise, turn this into a scalar_to_vector node.
3827 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3828 Node->getOperand(0));
3831 // If all elements are constants, create a load from the constant pool.
3833 MVT::ValueType VT = Node->getValueType(0);
3835 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3836 std::vector<Constant*> CV;
3837 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3838 if (ConstantFPSDNode *V =
3839 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3840 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3841 } else if (ConstantSDNode *V =
3842 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3843 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3845 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3846 CV.push_back(UndefValue::get(OpNTy));
3849 Constant *CP = ConstantPacked::get(CV);
3850 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3851 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3854 if (SplatValue.Val) { // Splat of one value?
3855 // Build the shuffle constant vector: <0, 0, 0, 0>
3856 MVT::ValueType MaskVT =
3857 MVT::getIntVectorWithNumElements(NumElems);
3858 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3859 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3860 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3861 &ZeroVec[0], ZeroVec.size());
3863 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3864 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3865 // Get the splatted value into the low element of a vector register.
3866 SDOperand LowValVec =
3867 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3869 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3870 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3871 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3876 // If there are only two unique elements, we may be able to turn this into a
3878 if (Values.size() == 2) {
3879 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3880 MVT::ValueType MaskVT =
3881 MVT::getIntVectorWithNumElements(NumElems);
3882 std::vector<SDOperand> MaskVec(NumElems);
3884 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3885 E = Values.end(); I != E; ++I) {
3886 for (std::vector<unsigned>::iterator II = I->second.begin(),
3887 EE = I->second.end(); II != EE; ++II)
3888 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3891 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3892 &MaskVec[0], MaskVec.size());
3894 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3895 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3896 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3897 SmallVector<SDOperand, 8> Ops;
3898 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3899 E = Values.end(); I != E; ++I) {
3900 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3904 Ops.push_back(ShuffleMask);
3906 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3907 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3908 &Ops[0], Ops.size());
3912 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3913 // aligned object on the stack, store each element into it, then load
3914 // the result as a vector.
3915 MVT::ValueType VT = Node->getValueType(0);
3916 // Create the stack frame object.
3917 SDOperand FIPtr = CreateStackTemporary(VT);
3919 // Emit a store of each element to the stack slot.
3920 SmallVector<SDOperand, 8> Stores;
3921 unsigned TypeByteSize =
3922 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3923 // Store (in the right endianness) the elements to memory.
3924 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3925 // Ignore undef elements.
3926 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3928 unsigned Offset = TypeByteSize*i;
3930 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3931 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3933 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3937 SDOperand StoreChain;
3938 if (!Stores.empty()) // Not all undef elements?
3939 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3940 &Stores[0], Stores.size());
3942 StoreChain = DAG.getEntryNode();
3944 // Result is a load from the stack slot.
3945 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3948 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3949 /// specified value type.
3950 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3951 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3952 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3953 const Type *Ty = MVT::getTypeForValueType(VT);
3954 unsigned StackAlign = (unsigned)TLI.getTargetData()->getTypeAlignmentPref(Ty);
3955 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
3956 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3959 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3960 SDOperand Op, SDOperand Amt,
3961 SDOperand &Lo, SDOperand &Hi) {
3962 // Expand the subcomponents.
3963 SDOperand LHSL, LHSH;
3964 ExpandOp(Op, LHSL, LHSH);
3966 SDOperand Ops[] = { LHSL, LHSH, Amt };
3967 MVT::ValueType VT = LHSL.getValueType();
3968 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3969 Hi = Lo.getValue(1);
3973 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3974 /// smaller elements. If we can't find a way that is more efficient than a
3975 /// libcall on this target, return false. Otherwise, return true with the
3976 /// low-parts expanded into Lo and Hi.
3977 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3978 SDOperand &Lo, SDOperand &Hi) {
3979 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3980 "This is not a shift!");
3982 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3983 SDOperand ShAmt = LegalizeOp(Amt);
3984 MVT::ValueType ShTy = ShAmt.getValueType();
3985 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3986 unsigned NVTBits = MVT::getSizeInBits(NVT);
3988 // Handle the case when Amt is an immediate. Other cases are currently broken
3989 // and are disabled.
3990 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3991 unsigned Cst = CN->getValue();
3992 // Expand the incoming operand to be shifted, so that we have its parts
3994 ExpandOp(Op, InL, InH);
3998 Lo = DAG.getConstant(0, NVT);
3999 Hi = DAG.getConstant(0, NVT);
4000 } else if (Cst > NVTBits) {
4001 Lo = DAG.getConstant(0, NVT);
4002 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4003 } else if (Cst == NVTBits) {
4004 Lo = DAG.getConstant(0, NVT);
4007 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4008 Hi = DAG.getNode(ISD::OR, NVT,
4009 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4010 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4015 Lo = DAG.getConstant(0, NVT);
4016 Hi = DAG.getConstant(0, NVT);
4017 } else if (Cst > NVTBits) {
4018 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4019 Hi = DAG.getConstant(0, NVT);
4020 } else if (Cst == NVTBits) {
4022 Hi = DAG.getConstant(0, NVT);
4024 Lo = DAG.getNode(ISD::OR, NVT,
4025 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4026 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4027 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4032 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4033 DAG.getConstant(NVTBits-1, ShTy));
4034 } else if (Cst > NVTBits) {
4035 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4036 DAG.getConstant(Cst-NVTBits, ShTy));
4037 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4038 DAG.getConstant(NVTBits-1, ShTy));
4039 } else if (Cst == NVTBits) {
4041 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4042 DAG.getConstant(NVTBits-1, ShTy));
4044 Lo = DAG.getNode(ISD::OR, NVT,
4045 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4046 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4047 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4053 // Okay, the shift amount isn't constant. However, if we can tell that it is
4054 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4055 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4056 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4058 // If we know that the high bit of the shift amount is one, then we can do
4059 // this as a couple of simple shifts.
4060 if (KnownOne & Mask) {
4061 // Mask out the high bit, which we know is set.
4062 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4063 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4065 // Expand the incoming operand to be shifted, so that we have its parts
4067 ExpandOp(Op, InL, InH);
4070 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4071 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4074 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4075 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4078 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4079 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4080 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4085 // If we know that the high bit of the shift amount is zero, then we can do
4086 // this as a couple of simple shifts.
4087 if (KnownZero & Mask) {
4089 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4090 DAG.getConstant(NVTBits, Amt.getValueType()),
4093 // Expand the incoming operand to be shifted, so that we have its parts
4095 ExpandOp(Op, InL, InH);
4098 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4099 Hi = DAG.getNode(ISD::OR, NVT,
4100 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4101 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4104 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4105 Lo = DAG.getNode(ISD::OR, NVT,
4106 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4107 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4110 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4111 Lo = DAG.getNode(ISD::OR, NVT,
4112 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4113 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4122 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4123 // does not fit into a register, return the lo part and set the hi part to the
4124 // by-reg argument. If it does fit into a single register, return the result
4125 // and leave the Hi part unset.
4126 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4127 bool isSigned, SDOperand &Hi) {
4128 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4129 // The input chain to this libcall is the entry node of the function.
4130 // Legalizing the call will automatically add the previous call to the
4132 SDOperand InChain = DAG.getEntryNode();
4134 TargetLowering::ArgListTy Args;
4135 TargetLowering::ArgListEntry Entry;
4136 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4137 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4138 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4139 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4140 Entry.isSigned = isSigned; Entry.isInReg = false; Entry.isSRet = false;
4141 Args.push_back(Entry);
4143 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4145 // Splice the libcall in wherever FindInputOutputChains tells us to.
4146 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4147 std::pair<SDOperand,SDOperand> CallInfo =
4148 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4151 // Legalize the call sequence, starting with the chain. This will advance
4152 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4153 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4154 LegalizeOp(CallInfo.second);
4156 switch (getTypeAction(CallInfo.first.getValueType())) {
4157 default: assert(0 && "Unknown thing");
4159 Result = CallInfo.first;
4162 ExpandOp(CallInfo.first, Result, Hi);
4169 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
4170 /// destination type is legal.
4171 SDOperand SelectionDAGLegalize::
4172 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4173 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
4174 assert(getTypeAction(Source.getValueType()) == Expand &&
4175 "This is not an expansion!");
4176 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4179 assert(Source.getValueType() == MVT::i64 &&
4180 "This only works for 64-bit -> FP");
4181 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4182 // incoming integer is set. To handle this, we dynamically test to see if
4183 // it is set, and, if so, add a fudge factor.
4185 ExpandOp(Source, Lo, Hi);
4187 // If this is unsigned, and not supported, first perform the conversion to
4188 // signed, then adjust the result if the sign bit is set.
4189 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4190 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4192 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4193 DAG.getConstant(0, Hi.getValueType()),
4195 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4196 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4197 SignSet, Four, Zero);
4198 uint64_t FF = 0x5f800000ULL;
4199 if (TLI.isLittleEndian()) FF <<= 32;
4200 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4202 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4203 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4204 SDOperand FudgeInReg;
4205 if (DestTy == MVT::f32)
4206 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4208 assert(DestTy == MVT::f64 && "Unexpected conversion");
4209 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4210 CPIdx, NULL, 0, MVT::f32);
4212 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4215 // Check to see if the target has a custom way to lower this. If so, use it.
4216 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4217 default: assert(0 && "This action not implemented for this operation!");
4218 case TargetLowering::Legal:
4219 case TargetLowering::Expand:
4220 break; // This case is handled below.
4221 case TargetLowering::Custom: {
4222 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4225 return LegalizeOp(NV);
4226 break; // The target decided this was legal after all
4230 // Expand the source, then glue it back together for the call. We must expand
4231 // the source in case it is shared (this pass of legalize must traverse it).
4232 SDOperand SrcLo, SrcHi;
4233 ExpandOp(Source, SrcLo, SrcHi);
4234 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4237 if (DestTy == MVT::f32)
4238 LC = RTLIB::SINTTOFP_I64_F32;
4240 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4241 LC = RTLIB::SINTTOFP_I64_F64;
4244 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4245 SDOperand UnusedHiPart;
4246 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4250 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4251 /// INT_TO_FP operation of the specified operand when the target requests that
4252 /// we expand it. At this point, we know that the result and operand types are
4253 /// legal for the target.
4254 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4256 MVT::ValueType DestVT) {
4257 if (Op0.getValueType() == MVT::i32) {
4258 // simple 32-bit [signed|unsigned] integer to float/double expansion
4260 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4261 MachineFunction &MF = DAG.getMachineFunction();
4262 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4263 unsigned StackAlign =
4264 (unsigned)TLI.getTargetData()->getTypeAlignmentPref(F64Type);
4265 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4266 // get address of 8 byte buffer
4267 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4268 // word offset constant for Hi/Lo address computation
4269 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4270 // set up Hi and Lo (into buffer) address based on endian
4271 SDOperand Hi = StackSlot;
4272 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4273 if (TLI.isLittleEndian())
4276 // if signed map to unsigned space
4277 SDOperand Op0Mapped;
4279 // constant used to invert sign bit (signed to unsigned mapping)
4280 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4281 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4285 // store the lo of the constructed double - based on integer input
4286 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4287 Op0Mapped, Lo, NULL, 0);
4288 // initial hi portion of constructed double
4289 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4290 // store the hi of the constructed double - biased exponent
4291 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4292 // load the constructed double
4293 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4294 // FP constant to bias correct the final result
4295 SDOperand Bias = DAG.getConstantFP(isSigned ?
4296 BitsToDouble(0x4330000080000000ULL)
4297 : BitsToDouble(0x4330000000000000ULL),
4299 // subtract the bias
4300 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4303 // handle final rounding
4304 if (DestVT == MVT::f64) {
4308 // if f32 then cast to f32
4309 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4313 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4314 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4316 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4317 DAG.getConstant(0, Op0.getValueType()),
4319 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4320 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4321 SignSet, Four, Zero);
4323 // If the sign bit of the integer is set, the large number will be treated
4324 // as a negative number. To counteract this, the dynamic code adds an
4325 // offset depending on the data type.
4327 switch (Op0.getValueType()) {
4328 default: assert(0 && "Unsupported integer type!");
4329 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4330 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4331 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4332 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4334 if (TLI.isLittleEndian()) FF <<= 32;
4335 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4337 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4338 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4339 SDOperand FudgeInReg;
4340 if (DestVT == MVT::f32)
4341 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4343 assert(DestVT == MVT::f64 && "Unexpected conversion");
4344 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4345 DAG.getEntryNode(), CPIdx,
4346 NULL, 0, MVT::f32));
4349 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4352 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4353 /// *INT_TO_FP operation of the specified operand when the target requests that
4354 /// we promote it. At this point, we know that the result and operand types are
4355 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4356 /// operation that takes a larger input.
4357 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4358 MVT::ValueType DestVT,
4360 // First step, figure out the appropriate *INT_TO_FP operation to use.
4361 MVT::ValueType NewInTy = LegalOp.getValueType();
4363 unsigned OpToUse = 0;
4365 // Scan for the appropriate larger type to use.
4367 NewInTy = (MVT::ValueType)(NewInTy+1);
4368 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4370 // If the target supports SINT_TO_FP of this type, use it.
4371 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4373 case TargetLowering::Legal:
4374 if (!TLI.isTypeLegal(NewInTy))
4375 break; // Can't use this datatype.
4377 case TargetLowering::Custom:
4378 OpToUse = ISD::SINT_TO_FP;
4382 if (isSigned) continue;
4384 // If the target supports UINT_TO_FP of this type, use it.
4385 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4387 case TargetLowering::Legal:
4388 if (!TLI.isTypeLegal(NewInTy))
4389 break; // Can't use this datatype.
4391 case TargetLowering::Custom:
4392 OpToUse = ISD::UINT_TO_FP;
4397 // Otherwise, try a larger type.
4400 // Okay, we found the operation and type to use. Zero extend our input to the
4401 // desired type then run the operation on it.
4402 return DAG.getNode(OpToUse, DestVT,
4403 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4407 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4408 /// FP_TO_*INT operation of the specified operand when the target requests that
4409 /// we promote it. At this point, we know that the result and operand types are
4410 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4411 /// operation that returns a larger result.
4412 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4413 MVT::ValueType DestVT,
4415 // First step, figure out the appropriate FP_TO*INT operation to use.
4416 MVT::ValueType NewOutTy = DestVT;
4418 unsigned OpToUse = 0;
4420 // Scan for the appropriate larger type to use.
4422 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4423 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4425 // If the target supports FP_TO_SINT returning this type, use it.
4426 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4428 case TargetLowering::Legal:
4429 if (!TLI.isTypeLegal(NewOutTy))
4430 break; // Can't use this datatype.
4432 case TargetLowering::Custom:
4433 OpToUse = ISD::FP_TO_SINT;
4438 // If the target supports FP_TO_UINT of this type, use it.
4439 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4441 case TargetLowering::Legal:
4442 if (!TLI.isTypeLegal(NewOutTy))
4443 break; // Can't use this datatype.
4445 case TargetLowering::Custom:
4446 OpToUse = ISD::FP_TO_UINT;
4451 // Otherwise, try a larger type.
4454 // Okay, we found the operation and type to use. Truncate the result of the
4455 // extended FP_TO_*INT operation to the desired size.
4456 return DAG.getNode(ISD::TRUNCATE, DestVT,
4457 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4460 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4462 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4463 MVT::ValueType VT = Op.getValueType();
4464 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4465 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4467 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4469 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4470 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4471 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4473 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4474 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4475 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4476 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4477 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4478 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4479 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4480 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4481 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4483 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4484 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4485 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4486 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4487 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4488 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4489 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4490 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4491 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4492 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4493 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4494 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4495 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4496 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4497 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4498 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4499 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4500 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4501 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4502 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4503 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4507 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4509 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4511 default: assert(0 && "Cannot expand this yet!");
4513 static const uint64_t mask[6] = {
4514 0x5555555555555555ULL, 0x3333333333333333ULL,
4515 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4516 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4518 MVT::ValueType VT = Op.getValueType();
4519 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4520 unsigned len = getSizeInBits(VT);
4521 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4522 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4523 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4524 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4525 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4526 DAG.getNode(ISD::AND, VT,
4527 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4532 // for now, we do this:
4533 // x = x | (x >> 1);
4534 // x = x | (x >> 2);
4536 // x = x | (x >>16);
4537 // x = x | (x >>32); // for 64-bit input
4538 // return popcount(~x);
4540 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4541 MVT::ValueType VT = Op.getValueType();
4542 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4543 unsigned len = getSizeInBits(VT);
4544 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4545 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4546 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4548 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4549 return DAG.getNode(ISD::CTPOP, VT, Op);
4552 // for now, we use: { return popcount(~x & (x - 1)); }
4553 // unless the target has ctlz but not ctpop, in which case we use:
4554 // { return 32 - nlz(~x & (x-1)); }
4555 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4556 MVT::ValueType VT = Op.getValueType();
4557 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4558 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4559 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4560 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4561 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4562 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4563 TLI.isOperationLegal(ISD::CTLZ, VT))
4564 return DAG.getNode(ISD::SUB, VT,
4565 DAG.getConstant(getSizeInBits(VT), VT),
4566 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4567 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4572 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4573 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4574 /// LegalizeNodes map is filled in for any results that are not expanded, the
4575 /// ExpandedNodes map is filled in for any results that are expanded, and the
4576 /// Lo/Hi values are returned.
4577 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4578 MVT::ValueType VT = Op.getValueType();
4579 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4580 SDNode *Node = Op.Val;
4581 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4582 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4583 VT == MVT::Vector) &&
4584 "Cannot expand to FP value or to larger int value!");
4586 // See if we already expanded it.
4587 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4588 = ExpandedNodes.find(Op);
4589 if (I != ExpandedNodes.end()) {
4590 Lo = I->second.first;
4591 Hi = I->second.second;
4595 switch (Node->getOpcode()) {
4596 case ISD::CopyFromReg:
4597 assert(0 && "CopyFromReg must be legal!");
4600 cerr << "NODE: "; Node->dump(); cerr << "\n";
4602 assert(0 && "Do not know how to expand this operator!");
4605 NVT = TLI.getTypeToExpandTo(VT);
4606 Lo = DAG.getNode(ISD::UNDEF, NVT);
4607 Hi = DAG.getNode(ISD::UNDEF, NVT);
4609 case ISD::Constant: {
4610 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4611 Lo = DAG.getConstant(Cst, NVT);
4612 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4615 case ISD::ConstantFP: {
4616 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4617 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4618 if (getTypeAction(Lo.getValueType()) == Expand)
4619 ExpandOp(Lo, Lo, Hi);
4622 case ISD::BUILD_PAIR:
4623 // Return the operands.
4624 Lo = Node->getOperand(0);
4625 Hi = Node->getOperand(1);
4628 case ISD::SIGN_EXTEND_INREG:
4629 ExpandOp(Node->getOperand(0), Lo, Hi);
4630 // sext_inreg the low part if needed.
4631 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4633 // The high part gets the sign extension from the lo-part. This handles
4634 // things like sextinreg V:i64 from i8.
4635 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4636 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4637 TLI.getShiftAmountTy()));
4641 ExpandOp(Node->getOperand(0), Lo, Hi);
4642 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4643 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4649 ExpandOp(Node->getOperand(0), Lo, Hi);
4650 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4651 DAG.getNode(ISD::CTPOP, NVT, Lo),
4652 DAG.getNode(ISD::CTPOP, NVT, Hi));
4653 Hi = DAG.getConstant(0, NVT);
4657 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4658 ExpandOp(Node->getOperand(0), Lo, Hi);
4659 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4660 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4661 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4663 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4664 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4666 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4667 Hi = DAG.getConstant(0, NVT);
4672 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4673 ExpandOp(Node->getOperand(0), Lo, Hi);
4674 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4675 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4676 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4678 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4679 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4681 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4682 Hi = DAG.getConstant(0, NVT);
4687 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4688 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4689 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4690 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4692 // Remember that we legalized the chain.
4693 Hi = LegalizeOp(Hi);
4694 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4695 if (!TLI.isLittleEndian())
4701 LoadSDNode *LD = cast<LoadSDNode>(Node);
4702 SDOperand Ch = LD->getChain(); // Legalize the chain.
4703 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4704 ISD::LoadExtType ExtType = LD->getExtensionType();
4706 if (ExtType == ISD::NON_EXTLOAD) {
4707 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset());
4708 if (VT == MVT::f32 || VT == MVT::f64) {
4709 // f32->i32 or f64->i64 one to one expansion.
4710 // Remember that we legalized the chain.
4711 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4712 // Recursively expand the new load.
4713 if (getTypeAction(NVT) == Expand)
4714 ExpandOp(Lo, Lo, Hi);
4718 // Increment the pointer to the other half.
4719 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4720 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4721 getIntPtrConstant(IncrementSize));
4722 // FIXME: This creates a bogus srcvalue!
4723 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),LD->getSrcValueOffset());
4725 // Build a factor node to remember that this load is independent of the
4727 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4730 // Remember that we legalized the chain.
4731 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4732 if (!TLI.isLittleEndian())
4735 MVT::ValueType EVT = LD->getLoadedVT();
4737 if (VT == MVT::f64 && EVT == MVT::f32) {
4738 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4739 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4740 LD->getSrcValueOffset());
4741 // Remember that we legalized the chain.
4742 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4743 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4748 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4749 LD->getSrcValueOffset());
4751 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4752 LD->getSrcValueOffset(), EVT);
4754 // Remember that we legalized the chain.
4755 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4757 if (ExtType == ISD::SEXTLOAD) {
4758 // The high part is obtained by SRA'ing all but one of the bits of the
4760 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4761 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4762 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4763 } else if (ExtType == ISD::ZEXTLOAD) {
4764 // The high part is just a zero.
4765 Hi = DAG.getConstant(0, NVT);
4766 } else /* if (ExtType == ISD::EXTLOAD) */ {
4767 // The high part is undefined.
4768 Hi = DAG.getNode(ISD::UNDEF, NVT);
4775 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4776 SDOperand LL, LH, RL, RH;
4777 ExpandOp(Node->getOperand(0), LL, LH);
4778 ExpandOp(Node->getOperand(1), RL, RH);
4779 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4780 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4784 SDOperand LL, LH, RL, RH;
4785 ExpandOp(Node->getOperand(1), LL, LH);
4786 ExpandOp(Node->getOperand(2), RL, RH);
4787 if (getTypeAction(NVT) == Expand)
4788 NVT = TLI.getTypeToExpandTo(NVT);
4789 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4791 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4794 case ISD::SELECT_CC: {
4795 SDOperand TL, TH, FL, FH;
4796 ExpandOp(Node->getOperand(2), TL, TH);
4797 ExpandOp(Node->getOperand(3), FL, FH);
4798 if (getTypeAction(NVT) == Expand)
4799 NVT = TLI.getTypeToExpandTo(NVT);
4800 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4801 Node->getOperand(1), TL, FL, Node->getOperand(4));
4803 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4804 Node->getOperand(1), TH, FH, Node->getOperand(4));
4807 case ISD::ANY_EXTEND:
4808 // The low part is any extension of the input (which degenerates to a copy).
4809 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4810 // The high part is undefined.
4811 Hi = DAG.getNode(ISD::UNDEF, NVT);
4813 case ISD::SIGN_EXTEND: {
4814 // The low part is just a sign extension of the input (which degenerates to
4816 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4818 // The high part is obtained by SRA'ing all but one of the bits of the lo
4820 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4821 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4822 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4825 case ISD::ZERO_EXTEND:
4826 // The low part is just a zero extension of the input (which degenerates to
4828 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4830 // The high part is just a zero.
4831 Hi = DAG.getConstant(0, NVT);
4834 case ISD::BIT_CONVERT: {
4836 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4837 // If the target wants to, allow it to lower this itself.
4838 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4839 case Expand: assert(0 && "cannot expand FP!");
4840 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4841 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4843 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4846 // f32 / f64 must be expanded to i32 / i64.
4847 if (VT == MVT::f32 || VT == MVT::f64) {
4848 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4849 if (getTypeAction(NVT) == Expand)
4850 ExpandOp(Lo, Lo, Hi);
4854 // If source operand will be expanded to the same type as VT, i.e.
4855 // i64 <- f64, i32 <- f32, expand the source operand instead.
4856 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
4857 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
4858 ExpandOp(Node->getOperand(0), Lo, Hi);
4862 // Turn this into a load/store pair by default.
4864 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
4866 ExpandOp(Tmp, Lo, Hi);
4870 case ISD::READCYCLECOUNTER:
4871 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4872 TargetLowering::Custom &&
4873 "Must custom expand ReadCycleCounter");
4874 Lo = TLI.LowerOperation(Op, DAG);
4875 assert(Lo.Val && "Node must be custom expanded!");
4876 Hi = Lo.getValue(1);
4877 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4878 LegalizeOp(Lo.getValue(2)));
4881 // These operators cannot be expanded directly, emit them as calls to
4882 // library functions.
4883 case ISD::FP_TO_SINT: {
4884 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4886 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4887 case Expand: assert(0 && "cannot expand FP!");
4888 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4889 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4892 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4894 // Now that the custom expander is done, expand the result, which is still
4897 ExpandOp(Op, Lo, Hi);
4903 if (Node->getOperand(0).getValueType() == MVT::f32)
4904 LC = RTLIB::FPTOSINT_F32_I64;
4906 LC = RTLIB::FPTOSINT_F64_I64;
4907 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
4908 false/*sign irrelevant*/, Hi);
4912 case ISD::FP_TO_UINT: {
4913 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4915 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4916 case Expand: assert(0 && "cannot expand FP!");
4917 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4918 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4921 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4923 // Now that the custom expander is done, expand the result.
4925 ExpandOp(Op, Lo, Hi);
4931 if (Node->getOperand(0).getValueType() == MVT::f32)
4932 LC = RTLIB::FPTOUINT_F32_I64;
4934 LC = RTLIB::FPTOUINT_F64_I64;
4935 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
4936 false/*sign irrelevant*/, Hi);
4941 // If the target wants custom lowering, do so.
4942 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4943 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4944 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4945 Op = TLI.LowerOperation(Op, DAG);
4947 // Now that the custom expander is done, expand the result, which is
4949 ExpandOp(Op, Lo, Hi);
4954 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4955 // this X << 1 as X+X.
4956 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4957 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4958 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4959 SDOperand LoOps[2], HiOps[3];
4960 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4961 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4962 LoOps[1] = LoOps[0];
4963 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4965 HiOps[1] = HiOps[0];
4966 HiOps[2] = Lo.getValue(1);
4967 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4972 // If we can emit an efficient shift operation, do so now.
4973 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4976 // If this target supports SHL_PARTS, use it.
4977 TargetLowering::LegalizeAction Action =
4978 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4979 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4980 Action == TargetLowering::Custom) {
4981 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4985 // Otherwise, emit a libcall.
4986 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
4987 false/*left shift=unsigned*/, Hi);
4992 // If the target wants custom lowering, do so.
4993 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4994 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4995 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4996 Op = TLI.LowerOperation(Op, DAG);
4998 // Now that the custom expander is done, expand the result, which is
5000 ExpandOp(Op, Lo, Hi);
5005 // If we can emit an efficient shift operation, do so now.
5006 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5009 // If this target supports SRA_PARTS, use it.
5010 TargetLowering::LegalizeAction Action =
5011 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5012 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5013 Action == TargetLowering::Custom) {
5014 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5018 // Otherwise, emit a libcall.
5019 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5020 true/*ashr is signed*/, Hi);
5025 // If the target wants custom lowering, do so.
5026 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5027 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5028 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5029 Op = TLI.LowerOperation(Op, DAG);
5031 // Now that the custom expander is done, expand the result, which is
5033 ExpandOp(Op, Lo, Hi);
5038 // If we can emit an efficient shift operation, do so now.
5039 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5042 // If this target supports SRL_PARTS, use it.
5043 TargetLowering::LegalizeAction Action =
5044 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5045 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5046 Action == TargetLowering::Custom) {
5047 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5051 // Otherwise, emit a libcall.
5052 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5053 false/*lshr is unsigned*/, Hi);
5059 // If the target wants to custom expand this, let them.
5060 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5061 TargetLowering::Custom) {
5062 Op = TLI.LowerOperation(Op, DAG);
5064 ExpandOp(Op, Lo, Hi);
5069 // Expand the subcomponents.
5070 SDOperand LHSL, LHSH, RHSL, RHSH;
5071 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5072 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5073 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5074 SDOperand LoOps[2], HiOps[3];
5079 if (Node->getOpcode() == ISD::ADD) {
5080 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5081 HiOps[2] = Lo.getValue(1);
5082 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5084 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5085 HiOps[2] = Lo.getValue(1);
5086 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5091 // If the target wants to custom expand this, let them.
5092 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5093 SDOperand New = TLI.LowerOperation(Op, DAG);
5095 ExpandOp(New, Lo, Hi);
5100 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5101 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5102 if (HasMULHS || HasMULHU) {
5103 SDOperand LL, LH, RL, RH;
5104 ExpandOp(Node->getOperand(0), LL, LH);
5105 ExpandOp(Node->getOperand(1), RL, RH);
5106 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5107 // FIXME: Move this to the dag combiner.
5108 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5109 // extended the sign bit of the low half through the upper half, and if so
5110 // emit a MULHS instead of the alternate sequence that is valid for any
5111 // i64 x i64 multiply.
5113 // is RH an extension of the sign bit of RL?
5114 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5115 RH.getOperand(1).getOpcode() == ISD::Constant &&
5116 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5117 // is LH an extension of the sign bit of LL?
5118 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5119 LH.getOperand(1).getOpcode() == ISD::Constant &&
5120 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5122 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5124 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5126 } else if (HasMULHU) {
5128 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5131 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5132 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5133 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5134 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5135 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5140 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5141 false/*sign irrelevant*/, Hi);
5145 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5148 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5151 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5154 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5158 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5159 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5163 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5164 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5168 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5169 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5173 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5174 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5177 case ISD::FP_EXTEND:
5178 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5181 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5186 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5187 switch(Node->getOpcode()) {
5189 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5192 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5195 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5197 default: assert(0 && "Unreachable!");
5199 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5203 SDOperand Mask = (VT == MVT::f64)
5204 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5205 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5206 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5207 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5208 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5209 if (getTypeAction(NVT) == Expand)
5210 ExpandOp(Lo, Lo, Hi);
5214 SDOperand Mask = (VT == MVT::f64)
5215 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5216 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5217 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5218 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5219 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5220 if (getTypeAction(NVT) == Expand)
5221 ExpandOp(Lo, Lo, Hi);
5224 case ISD::FCOPYSIGN: {
5225 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5226 if (getTypeAction(NVT) == Expand)
5227 ExpandOp(Lo, Lo, Hi);
5230 case ISD::SINT_TO_FP:
5231 case ISD::UINT_TO_FP: {
5232 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5233 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5235 if (Node->getOperand(0).getValueType() == MVT::i64) {
5237 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5239 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5242 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5244 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5247 // Promote the operand if needed.
5248 if (getTypeAction(SrcVT) == Promote) {
5249 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5251 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5252 DAG.getValueType(SrcVT))
5253 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5254 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5256 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5261 // Make sure the resultant values have been legalized themselves, unless this
5262 // is a type that requires multi-step expansion.
5263 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5264 Lo = LegalizeOp(Lo);
5266 // Don't legalize the high part if it is expanded to a single node.
5267 Hi = LegalizeOp(Hi);
5270 // Remember in a map if the values will be reused later.
5272 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5273 assert(isNew && "Value already expanded?!?");
5276 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
5277 /// two smaller values of MVT::Vector type.
5278 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5280 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
5281 SDNode *Node = Op.Val;
5282 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
5283 assert(NumElements > 1 && "Cannot split a single element vector!");
5284 unsigned NewNumElts = NumElements/2;
5285 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
5286 SDOperand TypeNode = *(Node->op_end()-1);
5288 // See if we already split it.
5289 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5290 = SplitNodes.find(Op);
5291 if (I != SplitNodes.end()) {
5292 Lo = I->second.first;
5293 Hi = I->second.second;
5297 switch (Node->getOpcode()) {
5302 assert(0 && "Unhandled operation in SplitVectorOp!");
5303 case ISD::VBUILD_VECTOR: {
5304 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5305 Node->op_begin()+NewNumElts);
5306 LoOps.push_back(NewNumEltsNode);
5307 LoOps.push_back(TypeNode);
5308 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
5310 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5312 HiOps.push_back(NewNumEltsNode);
5313 HiOps.push_back(TypeNode);
5314 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
5325 SDOperand LL, LH, RL, RH;
5326 SplitVectorOp(Node->getOperand(0), LL, LH);
5327 SplitVectorOp(Node->getOperand(1), RL, RH);
5329 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
5330 NewNumEltsNode, TypeNode);
5331 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
5332 NewNumEltsNode, TypeNode);
5336 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5337 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5338 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5340 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5341 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
5342 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5343 getIntPtrConstant(IncrementSize));
5344 // FIXME: This creates a bogus srcvalue!
5345 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
5347 // Build a factor node to remember that this load is independent of the
5349 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5352 // Remember that we legalized the chain.
5353 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5356 case ISD::VBIT_CONVERT: {
5357 // We know the result is a vector. The input may be either a vector or a
5359 if (Op.getOperand(0).getValueType() != MVT::Vector) {
5360 // Lower to a store/load. FIXME: this could be improved probably.
5361 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
5363 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5364 Op.getOperand(0), Ptr, NULL, 0);
5365 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
5366 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
5367 SplitVectorOp(St, Lo, Hi);
5369 // If the input is a vector type, we have to either scalarize it, pack it
5370 // or convert it based on whether the input vector type is legal.
5371 SDNode *InVal = Node->getOperand(0).Val;
5373 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5374 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5376 // If the input is from a single element vector, scalarize the vector,
5377 // then treat like a scalar.
5378 if (NumElems == 1) {
5379 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
5380 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
5381 Op.getOperand(1), Op.getOperand(2));
5382 SplitVectorOp(Scalar, Lo, Hi);
5384 // Split the input vector.
5385 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5387 // Convert each of the pieces now.
5388 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
5389 NewNumEltsNode, TypeNode);
5390 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
5391 NewNumEltsNode, TypeNode);
5398 // Remember in a map if the values will be reused later.
5400 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5401 assert(isNew && "Value already expanded?!?");
5405 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
5406 /// equivalent operation that returns a scalar (e.g. F32) or packed value
5407 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
5408 /// type for the result.
5409 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
5410 MVT::ValueType NewVT) {
5411 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5412 SDNode *Node = Op.Val;
5414 // See if we already packed it.
5415 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5416 if (I != PackedNodes.end()) return I->second;
5419 switch (Node->getOpcode()) {
5422 Node->dump(); cerr << "\n";
5424 assert(0 && "Unknown vector operation in PackVectorOp!");
5433 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5435 PackVectorOp(Node->getOperand(0), NewVT),
5436 PackVectorOp(Node->getOperand(1), NewVT));
5439 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5440 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5442 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5443 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5445 // Remember that we legalized the chain.
5446 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5449 case ISD::VBUILD_VECTOR:
5450 if (Node->getOperand(0).getValueType() == NewVT) {
5451 // Returning a scalar?
5452 Result = Node->getOperand(0);
5454 // Returning a BUILD_VECTOR?
5456 // If all elements of the build_vector are undefs, return an undef.
5457 bool AllUndef = true;
5458 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5459 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5464 Result = DAG.getNode(ISD::UNDEF, NewVT);
5466 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5467 Node->getNumOperands()-2);
5471 case ISD::VINSERT_VECTOR_ELT:
5472 if (!MVT::isVector(NewVT)) {
5473 // Returning a scalar? Must be the inserted element.
5474 Result = Node->getOperand(1);
5476 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5477 PackVectorOp(Node->getOperand(0), NewVT),
5478 Node->getOperand(1), Node->getOperand(2));
5481 case ISD::VVECTOR_SHUFFLE:
5482 if (!MVT::isVector(NewVT)) {
5483 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5484 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5485 if (cast<ConstantSDNode>(EltNum)->getValue())
5486 Result = PackVectorOp(Node->getOperand(1), NewVT);
5488 Result = PackVectorOp(Node->getOperand(0), NewVT);
5490 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5491 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5492 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5493 Node->getOperand(2).Val->op_end()-2);
5494 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5495 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5496 Node->getOperand(2).Val->op_begin(),
5497 Node->getOperand(2).Val->getNumOperands()-2);
5499 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5500 PackVectorOp(Node->getOperand(0), NewVT),
5501 PackVectorOp(Node->getOperand(1), NewVT), BV);
5504 case ISD::VBIT_CONVERT:
5505 if (Op.getOperand(0).getValueType() != MVT::Vector)
5506 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5508 // If the input is a vector type, we have to either scalarize it, pack it
5509 // or convert it based on whether the input vector type is legal.
5510 SDNode *InVal = Node->getOperand(0).Val;
5512 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5513 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5515 // Figure out if there is a Packed type corresponding to this Vector
5516 // type. If so, convert to the packed type.
5517 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5518 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5519 // Turn this into a bit convert of the packed input.
5520 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5521 PackVectorOp(Node->getOperand(0), TVT));
5523 } else if (NumElems == 1) {
5524 // Turn this into a bit convert of the scalar input.
5525 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5526 PackVectorOp(Node->getOperand(0), EVT));
5530 assert(0 && "Cast from unsupported vector type not implemented yet!");
5535 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5536 PackVectorOp(Op.getOperand(1), NewVT),
5537 PackVectorOp(Op.getOperand(2), NewVT));
5541 if (TLI.isTypeLegal(NewVT))
5542 Result = LegalizeOp(Result);
5543 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5544 assert(isNew && "Value already packed?");
5549 // SelectionDAG::Legalize - This is the entry point for the file.
5551 void SelectionDAG::Legalize() {
5552 if (ViewLegalizeDAGs) viewGraph();
5554 /// run - This is the main entry point to this class.
5556 SelectionDAGLegalize(*this).LegalizeDAG();