1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// PromoteOp - Given an operation that produces a value in an invalid type,
151 /// promote it to compute the value into a larger type. The produced value
152 /// will have the correct bits for the low portion of the register, but no
153 /// guarantee is made about the top bits: it may be zero, sign-extended, or
155 SDOperand PromoteOp(SDOperand O);
157 /// ExpandOp - Expand the specified SDOperand into its two component pieces
158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
159 /// the LegalizeNodes map is filled in for any results that are not expanded,
160 /// the ExpandedNodes map is filled in for any results that are expanded, and
161 /// the Lo/Hi values are returned. This applies to integer types and Vector
163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// SplitVectorOp - Given an operand of vector type, break it down into
166 /// two smaller values.
167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
169 /// ScalarizeVectorOp - Given an operand of single-element vector type
170 /// (e.g. v1f32), convert it into the equivalent operation that returns a
171 /// scalar (e.g. f32) value.
172 SDOperand ScalarizeVectorOp(SDOperand O);
174 /// isShuffleLegal - Return true if a vector shuffle is legal with the
175 /// specified mask and type. Targets can specify exactly which masks they
176 /// support and the code generator is tasked with not creating illegal masks.
178 /// Note that this will also return true for shuffles that are promoted to a
181 /// If this is a legal shuffle, this method returns the (possibly promoted)
182 /// build_vector Mask. If it's not a legal shuffle, it returns null.
183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
190 SDOperand CreateStackTemporary(MVT::ValueType VT);
192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
198 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
200 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
202 MVT::ValueType DestVT);
203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
208 SDOperand ExpandBSWAP(SDOperand Op);
209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
211 SDOperand &Lo, SDOperand &Hi);
212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
213 SDOperand &Lo, SDOperand &Hi);
215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
218 SDOperand getIntPtrConstant(uint64_t Val) {
219 return DAG.getConstant(Val, TLI.getPointerTy());
224 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
225 /// specified mask and type. Targets can specify exactly which masks they
226 /// support and the code generator is tasked with not creating illegal masks.
228 /// Note that this will also return true for shuffles that are promoted to a
230 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
231 SDOperand Mask) const {
232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
234 case TargetLowering::Legal:
235 case TargetLowering::Custom:
237 case TargetLowering::Promote: {
238 // If this is promoted to a different type, convert the shuffle mask and
239 // ask if it is legal in the promoted type!
240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
242 // If we changed # elements, change the shuffle mask.
243 unsigned NumEltsGrowth =
244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
246 if (NumEltsGrowth > 1) {
247 // Renumber the elements.
248 SmallVector<SDOperand, 8> Ops;
249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
250 SDOperand InOp = Mask.getOperand(i);
251 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
252 if (InOp.getOpcode() == ISD::UNDEF)
253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
269 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
270 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
271 ValueTypeActions(TLI.getValueTypeActions()) {
272 assert(MVT::LAST_VALUETYPE <= 32 &&
273 "Too many value types for ValueTypeActions to hold!");
276 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
277 /// contains all of a nodes operands before it contains the node.
278 static void ComputeTopDownOrdering(SelectionDAG &DAG,
279 SmallVector<SDNode*, 64> &Order) {
281 DenseMap<SDNode*, unsigned> Visited;
282 std::vector<SDNode*> Worklist;
283 Worklist.reserve(128);
285 // Compute ordering from all of the leaves in the graphs, those (like the
286 // entry node) that have no operands.
287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
288 E = DAG.allnodes_end(); I != E; ++I) {
289 if (I->getNumOperands() == 0) {
291 Worklist.push_back(I);
295 while (!Worklist.empty()) {
296 SDNode *N = Worklist.back();
299 if (++Visited[N] != N->getNumOperands())
300 continue; // Haven't visited all operands yet
304 // Now that we have N in, add anything that uses it if all of their operands
306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
308 Worklist.push_back(*UI);
311 assert(Order.size() == Visited.size() &&
313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
314 "Error: DAG is cyclic!");
318 void SelectionDAGLegalize::LegalizeDAG() {
319 LastCALLSEQ_END = DAG.getEntryNode();
320 IsLegalizingCall = false;
322 // The legalize process is inherently a bottom-up recursive process (users
323 // legalize their uses before themselves). Given infinite stack space, we
324 // could just start legalizing on the root and traverse the whole graph. In
325 // practice however, this causes us to run out of stack space on large basic
326 // blocks. To avoid this problem, compute an ordering of the nodes where each
327 // node is only legalized after all of its operands are legalized.
328 SmallVector<SDNode*, 64> Order;
329 ComputeTopDownOrdering(DAG, Order);
331 for (unsigned i = 0, e = Order.size(); i != e; ++i)
332 HandleOp(SDOperand(Order[i], 0));
334 // Finally, it's possible the root changed. Get the new root.
335 SDOperand OldRoot = DAG.getRoot();
336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
337 DAG.setRoot(LegalizedNodes[OldRoot]);
339 ExpandedNodes.clear();
340 LegalizedNodes.clear();
341 PromotedNodes.clear();
343 ScalarizedNodes.clear();
345 // Remove dead nodes now.
346 DAG.RemoveDeadNodes();
350 /// FindCallEndFromCallStart - Given a chained node that is part of a call
351 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
352 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
353 if (Node->getOpcode() == ISD::CALLSEQ_END)
355 if (Node->use_empty())
356 return 0; // No CallSeqEnd
358 // The chain is usually at the end.
359 SDOperand TheChain(Node, Node->getNumValues()-1);
360 if (TheChain.getValueType() != MVT::Other) {
361 // Sometimes it's at the beginning.
362 TheChain = SDOperand(Node, 0);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Otherwise, hunt for it.
365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
366 if (Node->getValueType(i) == MVT::Other) {
367 TheChain = SDOperand(Node, i);
371 // Otherwise, we walked into a node without a chain.
372 if (TheChain.getValueType() != MVT::Other)
377 for (SDNode::use_iterator UI = Node->use_begin(),
378 E = Node->use_end(); UI != E; ++UI) {
380 // Make sure to only follow users of our token chain.
382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
383 if (User->getOperand(i) == TheChain)
384 if (SDNode *Result = FindCallEndFromCallStart(User))
390 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
391 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
392 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
393 assert(Node && "Didn't find callseq_start for a call??");
394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
396 assert(Node->getOperand(0).getValueType() == MVT::Other &&
397 "Node doesn't have a token chain argument!");
398 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
401 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
402 /// see if any uses can reach Dest. If no dest operands can get to dest,
403 /// legalize them, legalize ourself, and return false, otherwise, return true.
405 /// Keep track of the nodes we fine that actually do lead to Dest in
406 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If we've already processed this node and it does lead to Dest, there is no
413 // need to reprocess it.
414 if (NodesLeadingTo.count(N)) return true;
416 // If the first result of this node has been already legalized, then it cannot
418 switch (getTypeAction(N->getValueType(0))) {
420 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
423 if (PromotedNodes.count(SDOperand(N, 0))) return false;
426 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
430 // Okay, this node has not already been legalized. Check and legalize all
431 // operands. If none lead to Dest, then we can legalize this node.
432 bool OperandsLeadToDest = false;
433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
434 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
437 if (OperandsLeadToDest) {
438 NodesLeadingTo.insert(N);
442 // Okay, this node looks safe, legalize it and return false.
443 HandleOp(SDOperand(N, 0));
447 /// HandleOp - Legalize, Promote, or Expand the specified operand as
448 /// appropriate for its type.
449 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
450 MVT::ValueType VT = Op.getValueType();
451 switch (getTypeAction(VT)) {
452 default: assert(0 && "Bad type action!");
453 case Legal: (void)LegalizeOp(Op); break;
454 case Promote: (void)PromoteOp(Op); break;
456 if (!MVT::isVector(VT)) {
457 // If this is an illegal scalar, expand it into its two component
460 if (Op.getOpcode() == ISD::TargetConstant)
461 break; // Allow illegal target nodes.
463 } else if (MVT::getVectorNumElements(VT) == 1) {
464 // If this is an illegal single element vector, convert it to a
466 (void)ScalarizeVectorOp(Op);
468 // Otherwise, this is an illegal multiple element vector.
469 // Split it in half and legalize both parts.
471 SplitVectorOp(Op, X, Y);
477 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
478 /// a load from the constant pool.
479 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
480 SelectionDAG &DAG, TargetLowering &TLI) {
483 // If a FP immediate is precise when represented as a float and if the
484 // target can do an extending load from float to double, we put it into
485 // the constant pool as a float, even if it's is statically typed as a
487 MVT::ValueType VT = CFP->getValueType(0);
488 bool isDouble = VT == MVT::f64;
489 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
492 if (VT!=MVT::f64 && VT!=MVT::f32)
493 assert(0 && "Invalid type expansion");
494 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
495 isDouble ? MVT::i64 : MVT::i32);
498 if (isDouble && CFP->isValueValidForType(MVT::f32, CFP->getValueAPF()) &&
499 // Only do this if the target has a native EXTLOAD instruction from f32.
500 // Do not try to be clever about long doubles (so far)
501 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
502 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
507 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
509 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
510 CPIdx, NULL, 0, MVT::f32);
512 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
517 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
520 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
521 SelectionDAG &DAG, TargetLowering &TLI) {
522 MVT::ValueType VT = Node->getValueType(0);
523 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
524 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
525 "fcopysign expansion only supported for f32 and f64");
526 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
528 // First get the sign bit of second operand.
529 SDOperand Mask1 = (SrcVT == MVT::f64)
530 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
531 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
532 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
533 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
534 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
535 // Shift right or sign-extend it if the two operands have different types.
536 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
538 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
539 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
540 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
541 } else if (SizeDiff < 0)
542 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
544 // Clear the sign bit of first operand.
545 SDOperand Mask2 = (VT == MVT::f64)
546 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
547 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
548 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
549 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
550 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
552 // Or the value with the sign bit.
553 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
557 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
559 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
560 TargetLowering &TLI) {
561 SDOperand Chain = ST->getChain();
562 SDOperand Ptr = ST->getBasePtr();
563 SDOperand Val = ST->getValue();
564 MVT::ValueType VT = Val.getValueType();
565 int Alignment = ST->getAlignment();
566 int SVOffset = ST->getSrcValueOffset();
567 if (MVT::isFloatingPoint(ST->getStoredVT())) {
568 // Expand to a bitconvert of the value to the integer type of the
569 // same size, then a (misaligned) int store.
570 MVT::ValueType intVT;
573 else if (VT==MVT::f32)
576 assert(0 && "Unaligned load of unsupported floating point type");
578 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
579 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
580 SVOffset, ST->isVolatile(), Alignment);
582 assert(MVT::isInteger(ST->getStoredVT()) &&
583 "Unaligned store of unknown type.");
584 // Get the half-size VT
585 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
586 int NumBits = MVT::getSizeInBits(NewStoredVT);
587 int IncrementSize = NumBits / 8;
589 // Divide the stored value in two parts.
590 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
592 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
594 // Store the two parts
595 SDOperand Store1, Store2;
596 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
597 ST->getSrcValue(), SVOffset, NewStoredVT,
598 ST->isVolatile(), Alignment);
599 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
600 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
601 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
602 ST->getSrcValue(), SVOffset + IncrementSize,
603 NewStoredVT, ST->isVolatile(), Alignment);
605 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
608 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
610 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
611 TargetLowering &TLI) {
612 int SVOffset = LD->getSrcValueOffset();
613 SDOperand Chain = LD->getChain();
614 SDOperand Ptr = LD->getBasePtr();
615 MVT::ValueType VT = LD->getValueType(0);
616 MVT::ValueType LoadedVT = LD->getLoadedVT();
617 if (MVT::isFloatingPoint(VT)) {
618 // Expand to a (misaligned) integer load of the same size,
619 // then bitconvert to floating point.
620 MVT::ValueType intVT;
621 if (LoadedVT==MVT::f64)
623 else if (LoadedVT==MVT::f32)
626 assert(0 && "Unaligned load of unsupported floating point type");
628 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
629 SVOffset, LD->isVolatile(),
631 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
633 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
635 SDOperand Ops[] = { Result, Chain };
636 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
639 assert(MVT::isInteger(LoadedVT) && "Unaligned load of unsupported type.");
640 MVT::ValueType NewLoadedVT = LoadedVT - 1;
641 int NumBits = MVT::getSizeInBits(NewLoadedVT);
642 int Alignment = LD->getAlignment();
643 int IncrementSize = NumBits / 8;
644 ISD::LoadExtType HiExtType = LD->getExtensionType();
646 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
647 if (HiExtType == ISD::NON_EXTLOAD)
648 HiExtType = ISD::ZEXTLOAD;
650 // Load the value in two parts
652 if (TLI.isLittleEndian()) {
653 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
654 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
655 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
656 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
657 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
658 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
661 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
662 NewLoadedVT,LD->isVolatile(), Alignment);
663 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
664 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
665 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
666 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
670 // aggregate the two parts
671 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
672 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
673 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
675 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
678 SDOperand Ops[] = { Result, TF };
679 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
682 /// LegalizeOp - We know that the specified value has a legal type, and
683 /// that its operands are legal. Now ensure that the operation itself
684 /// is legal, recursively ensuring that the operands' operations remain
686 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
687 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
690 assert(isTypeLegal(Op.getValueType()) &&
691 "Caller should expand or promote operands that are not legal!");
692 SDNode *Node = Op.Val;
694 // If this operation defines any values that cannot be represented in a
695 // register on this target, make sure to expand or promote them.
696 if (Node->getNumValues() > 1) {
697 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
698 if (getTypeAction(Node->getValueType(i)) != Legal) {
699 HandleOp(Op.getValue(i));
700 assert(LegalizedNodes.count(Op) &&
701 "Handling didn't add legal operands!");
702 return LegalizedNodes[Op];
706 // Note that LegalizeOp may be reentered even from single-use nodes, which
707 // means that we always must cache transformed nodes.
708 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
709 if (I != LegalizedNodes.end()) return I->second;
711 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
712 SDOperand Result = Op;
713 bool isCustom = false;
715 switch (Node->getOpcode()) {
716 case ISD::FrameIndex:
717 case ISD::EntryToken:
719 case ISD::BasicBlock:
720 case ISD::TargetFrameIndex:
721 case ISD::TargetJumpTable:
722 case ISD::TargetConstant:
723 case ISD::TargetConstantFP:
724 case ISD::TargetConstantPool:
725 case ISD::TargetGlobalAddress:
726 case ISD::TargetGlobalTLSAddress:
727 case ISD::TargetExternalSymbol:
732 // Primitives must all be legal.
733 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
734 "This must be legal!");
737 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
738 // If this is a target node, legalize it by legalizing the operands then
739 // passing it through.
740 SmallVector<SDOperand, 8> Ops;
741 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
742 Ops.push_back(LegalizeOp(Node->getOperand(i)));
744 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
746 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
747 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
748 return Result.getValue(Op.ResNo);
750 // Otherwise this is an unhandled builtin node. splat.
752 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
754 assert(0 && "Do not know how to legalize this operator!");
756 case ISD::GLOBAL_OFFSET_TABLE:
757 case ISD::GlobalAddress:
758 case ISD::GlobalTLSAddress:
759 case ISD::ExternalSymbol:
760 case ISD::ConstantPool:
761 case ISD::JumpTable: // Nothing to do.
762 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
763 default: assert(0 && "This action is not supported yet!");
764 case TargetLowering::Custom:
765 Tmp1 = TLI.LowerOperation(Op, DAG);
766 if (Tmp1.Val) Result = Tmp1;
767 // FALLTHROUGH if the target doesn't want to lower this op after all.
768 case TargetLowering::Legal:
773 case ISD::RETURNADDR:
774 // The only option for these nodes is to custom lower them. If the target
775 // does not custom lower them, then return zero.
776 Tmp1 = TLI.LowerOperation(Op, DAG);
780 Result = DAG.getConstant(0, TLI.getPointerTy());
782 case ISD::FRAME_TO_ARGS_OFFSET: {
783 MVT::ValueType VT = Node->getValueType(0);
784 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
785 default: assert(0 && "This action is not supported yet!");
786 case TargetLowering::Custom:
787 Result = TLI.LowerOperation(Op, DAG);
788 if (Result.Val) break;
790 case TargetLowering::Legal:
791 Result = DAG.getConstant(0, VT);
796 case ISD::EXCEPTIONADDR: {
797 Tmp1 = LegalizeOp(Node->getOperand(0));
798 MVT::ValueType VT = Node->getValueType(0);
799 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
800 default: assert(0 && "This action is not supported yet!");
801 case TargetLowering::Expand: {
802 unsigned Reg = TLI.getExceptionAddressRegister();
803 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
806 case TargetLowering::Custom:
807 Result = TLI.LowerOperation(Op, DAG);
808 if (Result.Val) break;
810 case TargetLowering::Legal: {
811 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
812 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
813 Ops, 2).getValue(Op.ResNo);
819 case ISD::EHSELECTION: {
820 Tmp1 = LegalizeOp(Node->getOperand(0));
821 Tmp2 = LegalizeOp(Node->getOperand(1));
822 MVT::ValueType VT = Node->getValueType(0);
823 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
824 default: assert(0 && "This action is not supported yet!");
825 case TargetLowering::Expand: {
826 unsigned Reg = TLI.getExceptionSelectorRegister();
827 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
830 case TargetLowering::Custom:
831 Result = TLI.LowerOperation(Op, DAG);
832 if (Result.Val) break;
834 case TargetLowering::Legal: {
835 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
836 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
837 Ops, 2).getValue(Op.ResNo);
843 case ISD::EH_RETURN: {
844 MVT::ValueType VT = Node->getValueType(0);
845 // The only "good" option for this node is to custom lower it.
846 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
847 default: assert(0 && "This action is not supported at all!");
848 case TargetLowering::Custom:
849 Result = TLI.LowerOperation(Op, DAG);
850 if (Result.Val) break;
852 case TargetLowering::Legal:
853 // Target does not know, how to lower this, lower to noop
854 Result = LegalizeOp(Node->getOperand(0));
859 case ISD::AssertSext:
860 case ISD::AssertZext:
861 Tmp1 = LegalizeOp(Node->getOperand(0));
862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
864 case ISD::MERGE_VALUES:
865 // Legalize eliminates MERGE_VALUES nodes.
866 Result = Node->getOperand(Op.ResNo);
868 case ISD::CopyFromReg:
869 Tmp1 = LegalizeOp(Node->getOperand(0));
870 Result = Op.getValue(0);
871 if (Node->getNumValues() == 2) {
872 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
874 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
875 if (Node->getNumOperands() == 3) {
876 Tmp2 = LegalizeOp(Node->getOperand(2));
877 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
881 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
883 // Since CopyFromReg produces two values, make sure to remember that we
884 // legalized both of them.
885 AddLegalizedOperand(Op.getValue(0), Result);
886 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
887 return Result.getValue(Op.ResNo);
889 MVT::ValueType VT = Op.getValueType();
890 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
891 default: assert(0 && "This action is not supported yet!");
892 case TargetLowering::Expand:
893 if (MVT::isInteger(VT))
894 Result = DAG.getConstant(0, VT);
895 else if (MVT::isFloatingPoint(VT))
896 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
899 assert(0 && "Unknown value type!");
901 case TargetLowering::Legal:
907 case ISD::INTRINSIC_W_CHAIN:
908 case ISD::INTRINSIC_WO_CHAIN:
909 case ISD::INTRINSIC_VOID: {
910 SmallVector<SDOperand, 8> Ops;
911 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
912 Ops.push_back(LegalizeOp(Node->getOperand(i)));
913 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
915 // Allow the target to custom lower its intrinsics if it wants to.
916 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
917 TargetLowering::Custom) {
918 Tmp3 = TLI.LowerOperation(Result, DAG);
919 if (Tmp3.Val) Result = Tmp3;
922 if (Result.Val->getNumValues() == 1) break;
924 // Must have return value and chain result.
925 assert(Result.Val->getNumValues() == 2 &&
926 "Cannot return more than two values!");
928 // Since loads produce two values, make sure to remember that we
929 // legalized both of them.
930 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
931 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
932 return Result.getValue(Op.ResNo);
936 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
937 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
939 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
940 case TargetLowering::Promote:
941 default: assert(0 && "This action is not supported yet!");
942 case TargetLowering::Expand: {
943 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
944 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
945 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
947 if (MMI && (useDEBUG_LOC || useLABEL)) {
948 const std::string &FName =
949 cast<StringSDNode>(Node->getOperand(3))->getValue();
950 const std::string &DirName =
951 cast<StringSDNode>(Node->getOperand(4))->getValue();
952 unsigned SrcFile = MMI->RecordSource(DirName, FName);
954 SmallVector<SDOperand, 8> Ops;
955 Ops.push_back(Tmp1); // chain
956 SDOperand LineOp = Node->getOperand(1);
957 SDOperand ColOp = Node->getOperand(2);
960 Ops.push_back(LineOp); // line #
961 Ops.push_back(ColOp); // col #
962 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
963 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
965 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
966 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
967 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
968 Ops.push_back(DAG.getConstant(ID, MVT::i32));
969 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
972 Result = Tmp1; // chain
976 case TargetLowering::Legal:
977 if (Tmp1 != Node->getOperand(0) ||
978 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
979 SmallVector<SDOperand, 8> Ops;
981 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
982 Ops.push_back(Node->getOperand(1)); // line # must be legal.
983 Ops.push_back(Node->getOperand(2)); // col # must be legal.
985 // Otherwise promote them.
986 Ops.push_back(PromoteOp(Node->getOperand(1)));
987 Ops.push_back(PromoteOp(Node->getOperand(2)));
989 Ops.push_back(Node->getOperand(3)); // filename must be legal.
990 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
991 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
998 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
999 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1000 default: assert(0 && "This action is not supported yet!");
1001 case TargetLowering::Legal:
1002 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1003 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1004 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1005 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1006 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1012 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
1013 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1014 default: assert(0 && "This action is not supported yet!");
1015 case TargetLowering::Legal:
1016 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1017 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1018 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1020 case TargetLowering::Expand:
1021 Result = LegalizeOp(Node->getOperand(0));
1026 case ISD::Constant: {
1027 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1029 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1031 // We know we don't need to expand constants here, constants only have one
1032 // value and we check that it is fine above.
1034 if (opAction == TargetLowering::Custom) {
1035 Tmp1 = TLI.LowerOperation(Result, DAG);
1041 case ISD::ConstantFP: {
1042 // Spill FP immediates to the constant pool if the target cannot directly
1043 // codegen them. Targets often have some immediate values that can be
1044 // efficiently generated into an FP register without a load. We explicitly
1045 // leave these constants as ConstantFP nodes for the target to deal with.
1046 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1048 // Check to see if this FP immediate is already legal.
1049 bool isLegal = false;
1050 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1051 E = TLI.legal_fpimm_end(); I != E; ++I)
1052 if (CFP->isExactlyValue(*I)) {
1057 // If this is a legal constant, turn it into a TargetConstantFP node.
1059 Result = DAG.getTargetConstantFP(CFP->getValueAPF(),
1060 CFP->getValueType(0));
1064 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1065 default: assert(0 && "This action is not supported yet!");
1066 case TargetLowering::Custom:
1067 Tmp3 = TLI.LowerOperation(Result, DAG);
1073 case TargetLowering::Expand:
1074 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1078 case ISD::TokenFactor:
1079 if (Node->getNumOperands() == 2) {
1080 Tmp1 = LegalizeOp(Node->getOperand(0));
1081 Tmp2 = LegalizeOp(Node->getOperand(1));
1082 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1083 } else if (Node->getNumOperands() == 3) {
1084 Tmp1 = LegalizeOp(Node->getOperand(0));
1085 Tmp2 = LegalizeOp(Node->getOperand(1));
1086 Tmp3 = LegalizeOp(Node->getOperand(2));
1087 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1089 SmallVector<SDOperand, 8> Ops;
1090 // Legalize the operands.
1091 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1092 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1093 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1097 case ISD::FORMAL_ARGUMENTS:
1099 // The only option for this is to custom lower it.
1100 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1101 assert(Tmp3.Val && "Target didn't custom lower this node!");
1102 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1103 "Lowering call/formal_arguments produced unexpected # results!");
1105 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1106 // remember that we legalized all of them, so it doesn't get relegalized.
1107 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1108 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1111 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1114 case ISD::EXTRACT_SUBREG: {
1115 Tmp1 = LegalizeOp(Node->getOperand(0));
1116 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1117 assert(idx && "Operand must be a constant");
1118 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1122 case ISD::INSERT_SUBREG: {
1123 Tmp1 = LegalizeOp(Node->getOperand(0));
1124 Tmp2 = LegalizeOp(Node->getOperand(1));
1125 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1126 assert(idx && "Operand must be a constant");
1127 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1131 case ISD::BUILD_VECTOR:
1132 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1133 default: assert(0 && "This action is not supported yet!");
1134 case TargetLowering::Custom:
1135 Tmp3 = TLI.LowerOperation(Result, DAG);
1141 case TargetLowering::Expand:
1142 Result = ExpandBUILD_VECTOR(Result.Val);
1146 case ISD::INSERT_VECTOR_ELT:
1147 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1148 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1149 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1150 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1152 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1153 Node->getValueType(0))) {
1154 default: assert(0 && "This action is not supported yet!");
1155 case TargetLowering::Legal:
1157 case TargetLowering::Custom:
1158 Tmp3 = TLI.LowerOperation(Result, DAG);
1164 case TargetLowering::Expand: {
1165 // If the insert index is a constant, codegen this as a scalar_to_vector,
1166 // then a shuffle that inserts it into the right position in the vector.
1167 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1168 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1169 Tmp1.getValueType(), Tmp2);
1171 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1172 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1173 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1175 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1176 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1178 SmallVector<SDOperand, 8> ShufOps;
1179 for (unsigned i = 0; i != NumElts; ++i) {
1180 if (i != InsertPos->getValue())
1181 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1183 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1185 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1186 &ShufOps[0], ShufOps.size());
1188 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1189 Tmp1, ScVec, ShufMask);
1190 Result = LegalizeOp(Result);
1194 // If the target doesn't support this, we have to spill the input vector
1195 // to a temporary stack slot, update the element, then reload it. This is
1196 // badness. We could also load the value into a vector register (either
1197 // with a "move to register" or "extload into register" instruction, then
1198 // permute it into place, if the idx is a constant and if the idx is
1199 // supported by the target.
1200 MVT::ValueType VT = Tmp1.getValueType();
1201 MVT::ValueType EltVT = Tmp2.getValueType();
1202 MVT::ValueType IdxVT = Tmp3.getValueType();
1203 MVT::ValueType PtrVT = TLI.getPointerTy();
1204 SDOperand StackPtr = CreateStackTemporary(VT);
1205 // Store the vector.
1206 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1208 // Truncate or zero extend offset to target pointer type.
1209 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1210 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1211 // Add the offset to the index.
1212 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1213 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1214 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1215 // Store the scalar value.
1216 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1217 // Load the updated vector.
1218 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1223 case ISD::SCALAR_TO_VECTOR:
1224 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1225 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1230 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1231 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1232 Node->getValueType(0))) {
1233 default: assert(0 && "This action is not supported yet!");
1234 case TargetLowering::Legal:
1236 case TargetLowering::Custom:
1237 Tmp3 = TLI.LowerOperation(Result, DAG);
1243 case TargetLowering::Expand:
1244 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1248 case ISD::VECTOR_SHUFFLE:
1249 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1250 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1251 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1253 // Allow targets to custom lower the SHUFFLEs they support.
1254 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1255 default: assert(0 && "Unknown operation action!");
1256 case TargetLowering::Legal:
1257 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1258 "vector shuffle should not be created if not legal!");
1260 case TargetLowering::Custom:
1261 Tmp3 = TLI.LowerOperation(Result, DAG);
1267 case TargetLowering::Expand: {
1268 MVT::ValueType VT = Node->getValueType(0);
1269 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1270 MVT::ValueType PtrVT = TLI.getPointerTy();
1271 SDOperand Mask = Node->getOperand(2);
1272 unsigned NumElems = Mask.getNumOperands();
1273 SmallVector<SDOperand,8> Ops;
1274 for (unsigned i = 0; i != NumElems; ++i) {
1275 SDOperand Arg = Mask.getOperand(i);
1276 if (Arg.getOpcode() == ISD::UNDEF) {
1277 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1279 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1280 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1282 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1283 DAG.getConstant(Idx, PtrVT)));
1285 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1286 DAG.getConstant(Idx - NumElems, PtrVT)));
1289 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1292 case TargetLowering::Promote: {
1293 // Change base type to a different vector type.
1294 MVT::ValueType OVT = Node->getValueType(0);
1295 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1297 // Cast the two input vectors.
1298 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1299 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1301 // Convert the shuffle mask to the right # elements.
1302 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1303 assert(Tmp3.Val && "Shuffle not legal?");
1304 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1305 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1311 case ISD::EXTRACT_VECTOR_ELT:
1312 Tmp1 = Node->getOperand(0);
1313 Tmp2 = LegalizeOp(Node->getOperand(1));
1314 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1315 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1318 case ISD::EXTRACT_SUBVECTOR:
1319 Tmp1 = Node->getOperand(0);
1320 Tmp2 = LegalizeOp(Node->getOperand(1));
1321 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1322 Result = ExpandEXTRACT_SUBVECTOR(Result);
1325 case ISD::CALLSEQ_START: {
1326 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1328 // Recursively Legalize all of the inputs of the call end that do not lead
1329 // to this call start. This ensures that any libcalls that need be inserted
1330 // are inserted *before* the CALLSEQ_START.
1331 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1332 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1333 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1337 // Now that we legalized all of the inputs (which may have inserted
1338 // libcalls) create the new CALLSEQ_START node.
1339 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1341 // Merge in the last call, to ensure that this call start after the last
1343 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1344 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1345 Tmp1 = LegalizeOp(Tmp1);
1348 // Do not try to legalize the target-specific arguments (#1+).
1349 if (Tmp1 != Node->getOperand(0)) {
1350 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1352 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1355 // Remember that the CALLSEQ_START is legalized.
1356 AddLegalizedOperand(Op.getValue(0), Result);
1357 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1358 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1360 // Now that the callseq_start and all of the non-call nodes above this call
1361 // sequence have been legalized, legalize the call itself. During this
1362 // process, no libcalls can/will be inserted, guaranteeing that no calls
1364 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1365 SDOperand InCallSEQ = LastCALLSEQ_END;
1366 // Note that we are selecting this call!
1367 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1368 IsLegalizingCall = true;
1370 // Legalize the call, starting from the CALLSEQ_END.
1371 LegalizeOp(LastCALLSEQ_END);
1372 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1375 case ISD::CALLSEQ_END:
1376 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1377 // will cause this node to be legalized as well as handling libcalls right.
1378 if (LastCALLSEQ_END.Val != Node) {
1379 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1380 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1381 assert(I != LegalizedNodes.end() &&
1382 "Legalizing the call start should have legalized this node!");
1386 // Otherwise, the call start has been legalized and everything is going
1387 // according to plan. Just legalize ourselves normally here.
1388 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1389 // Do not try to legalize the target-specific arguments (#1+), except for
1390 // an optional flag input.
1391 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1392 if (Tmp1 != Node->getOperand(0)) {
1393 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1395 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1398 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1399 if (Tmp1 != Node->getOperand(0) ||
1400 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1401 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1404 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1407 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1408 // This finishes up call legalization.
1409 IsLegalizingCall = false;
1411 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1412 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1413 if (Node->getNumValues() == 2)
1414 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1415 return Result.getValue(Op.ResNo);
1416 case ISD::DYNAMIC_STACKALLOC: {
1417 MVT::ValueType VT = Node->getValueType(0);
1418 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1419 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1420 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1423 Tmp1 = Result.getValue(0);
1424 Tmp2 = Result.getValue(1);
1425 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1426 default: assert(0 && "This action is not supported yet!");
1427 case TargetLowering::Expand: {
1428 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1429 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1430 " not tell us which reg is the stack pointer!");
1431 SDOperand Chain = Tmp1.getOperand(0);
1432 SDOperand Size = Tmp2.getOperand(1);
1433 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1434 Chain = SP.getValue(1);
1435 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1436 unsigned StackAlign =
1437 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1438 if (Align > StackAlign)
1439 SP = DAG.getNode(ISD::AND, VT, SP,
1440 DAG.getConstant(-(uint64_t)Align, VT));
1441 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1442 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1443 Tmp1 = LegalizeOp(Tmp1);
1444 Tmp2 = LegalizeOp(Tmp2);
1447 case TargetLowering::Custom:
1448 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1450 Tmp1 = LegalizeOp(Tmp3);
1451 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1454 case TargetLowering::Legal:
1457 // Since this op produce two values, make sure to remember that we
1458 // legalized both of them.
1459 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1460 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1461 return Op.ResNo ? Tmp2 : Tmp1;
1463 case ISD::INLINEASM: {
1464 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1465 bool Changed = false;
1466 // Legalize all of the operands of the inline asm, in case they are nodes
1467 // that need to be expanded or something. Note we skip the asm string and
1468 // all of the TargetConstant flags.
1469 SDOperand Op = LegalizeOp(Ops[0]);
1470 Changed = Op != Ops[0];
1473 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1474 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1475 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1476 for (++i; NumVals; ++i, --NumVals) {
1477 SDOperand Op = LegalizeOp(Ops[i]);
1486 Op = LegalizeOp(Ops.back());
1487 Changed |= Op != Ops.back();
1492 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1494 // INLINE asm returns a chain and flag, make sure to add both to the map.
1495 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1496 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1497 return Result.getValue(Op.ResNo);
1500 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1501 // Ensure that libcalls are emitted before a branch.
1502 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1503 Tmp1 = LegalizeOp(Tmp1);
1504 LastCALLSEQ_END = DAG.getEntryNode();
1506 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1509 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1510 // Ensure that libcalls are emitted before a branch.
1511 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1512 Tmp1 = LegalizeOp(Tmp1);
1513 LastCALLSEQ_END = DAG.getEntryNode();
1515 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1516 default: assert(0 && "Indirect target must be legal type (pointer)!");
1518 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1521 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1524 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1525 // Ensure that libcalls are emitted before a branch.
1526 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1527 Tmp1 = LegalizeOp(Tmp1);
1528 LastCALLSEQ_END = DAG.getEntryNode();
1530 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1531 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1533 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1534 default: assert(0 && "This action is not supported yet!");
1535 case TargetLowering::Legal: break;
1536 case TargetLowering::Custom:
1537 Tmp1 = TLI.LowerOperation(Result, DAG);
1538 if (Tmp1.Val) Result = Tmp1;
1540 case TargetLowering::Expand: {
1541 SDOperand Chain = Result.getOperand(0);
1542 SDOperand Table = Result.getOperand(1);
1543 SDOperand Index = Result.getOperand(2);
1545 MVT::ValueType PTy = TLI.getPointerTy();
1546 MachineFunction &MF = DAG.getMachineFunction();
1547 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1548 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1549 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1552 switch (EntrySize) {
1553 default: assert(0 && "Size of jump table not supported yet."); break;
1554 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1555 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1558 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1559 // For PIC, the sequence is:
1560 // BRIND(load(Jumptable + index) + RelocBase)
1561 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1563 if (TLI.usesGlobalOffsetTable())
1564 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1567 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1568 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1569 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1571 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1577 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1578 // Ensure that libcalls are emitted before a return.
1579 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1580 Tmp1 = LegalizeOp(Tmp1);
1581 LastCALLSEQ_END = DAG.getEntryNode();
1583 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1584 case Expand: assert(0 && "It's impossible to expand bools");
1586 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1589 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1591 // The top bits of the promoted condition are not necessarily zero, ensure
1592 // that the value is properly zero extended.
1593 if (!DAG.MaskedValueIsZero(Tmp2,
1594 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1595 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1599 // Basic block destination (Op#2) is always legal.
1600 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1602 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1603 default: assert(0 && "This action is not supported yet!");
1604 case TargetLowering::Legal: break;
1605 case TargetLowering::Custom:
1606 Tmp1 = TLI.LowerOperation(Result, DAG);
1607 if (Tmp1.Val) Result = Tmp1;
1609 case TargetLowering::Expand:
1610 // Expand brcond's setcc into its constituent parts and create a BR_CC
1612 if (Tmp2.getOpcode() == ISD::SETCC) {
1613 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1614 Tmp2.getOperand(0), Tmp2.getOperand(1),
1615 Node->getOperand(2));
1617 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1618 DAG.getCondCode(ISD::SETNE), Tmp2,
1619 DAG.getConstant(0, Tmp2.getValueType()),
1620 Node->getOperand(2));
1626 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1627 // Ensure that libcalls are emitted before a branch.
1628 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1629 Tmp1 = LegalizeOp(Tmp1);
1630 Tmp2 = Node->getOperand(2); // LHS
1631 Tmp3 = Node->getOperand(3); // RHS
1632 Tmp4 = Node->getOperand(1); // CC
1634 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1635 LastCALLSEQ_END = DAG.getEntryNode();
1637 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1638 // the LHS is a legal SETCC itself. In this case, we need to compare
1639 // the result against zero to select between true and false values.
1640 if (Tmp3.Val == 0) {
1641 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1642 Tmp4 = DAG.getCondCode(ISD::SETNE);
1645 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1646 Node->getOperand(4));
1648 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1649 default: assert(0 && "Unexpected action for BR_CC!");
1650 case TargetLowering::Legal: break;
1651 case TargetLowering::Custom:
1652 Tmp4 = TLI.LowerOperation(Result, DAG);
1653 if (Tmp4.Val) Result = Tmp4;
1658 LoadSDNode *LD = cast<LoadSDNode>(Node);
1659 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1660 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1662 ISD::LoadExtType ExtType = LD->getExtensionType();
1663 if (ExtType == ISD::NON_EXTLOAD) {
1664 MVT::ValueType VT = Node->getValueType(0);
1665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1666 Tmp3 = Result.getValue(0);
1667 Tmp4 = Result.getValue(1);
1669 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1670 default: assert(0 && "This action is not supported yet!");
1671 case TargetLowering::Legal:
1672 // If this is an unaligned load and the target doesn't support it,
1674 if (!TLI.allowsUnalignedMemoryAccesses()) {
1675 unsigned ABIAlignment = TLI.getTargetData()->
1676 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1677 if (LD->getAlignment() < ABIAlignment){
1678 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1680 Tmp3 = Result.getOperand(0);
1681 Tmp4 = Result.getOperand(1);
1682 Tmp3 = LegalizeOp(Tmp3);
1683 Tmp4 = LegalizeOp(Tmp4);
1687 case TargetLowering::Custom:
1688 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1690 Tmp3 = LegalizeOp(Tmp1);
1691 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1694 case TargetLowering::Promote: {
1695 // Only promote a load of vector type to another.
1696 assert(MVT::isVector(VT) && "Cannot promote this load!");
1697 // Change base type to a different vector type.
1698 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1700 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1701 LD->getSrcValueOffset(),
1702 LD->isVolatile(), LD->getAlignment());
1703 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1704 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1708 // Since loads produce two values, make sure to remember that we
1709 // legalized both of them.
1710 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1711 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1712 return Op.ResNo ? Tmp4 : Tmp3;
1714 MVT::ValueType SrcVT = LD->getLoadedVT();
1715 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1716 default: assert(0 && "This action is not supported yet!");
1717 case TargetLowering::Promote:
1718 assert(SrcVT == MVT::i1 &&
1719 "Can only promote extending LOAD from i1 -> i8!");
1720 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1721 LD->getSrcValue(), LD->getSrcValueOffset(),
1722 MVT::i8, LD->isVolatile(), LD->getAlignment());
1723 Tmp1 = Result.getValue(0);
1724 Tmp2 = Result.getValue(1);
1726 case TargetLowering::Custom:
1729 case TargetLowering::Legal:
1730 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1731 Tmp1 = Result.getValue(0);
1732 Tmp2 = Result.getValue(1);
1735 Tmp3 = TLI.LowerOperation(Result, DAG);
1737 Tmp1 = LegalizeOp(Tmp3);
1738 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1741 // If this is an unaligned load and the target doesn't support it,
1743 if (!TLI.allowsUnalignedMemoryAccesses()) {
1744 unsigned ABIAlignment = TLI.getTargetData()->
1745 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1746 if (LD->getAlignment() < ABIAlignment){
1747 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1749 Tmp1 = Result.getOperand(0);
1750 Tmp2 = Result.getOperand(1);
1751 Tmp1 = LegalizeOp(Tmp1);
1752 Tmp2 = LegalizeOp(Tmp2);
1757 case TargetLowering::Expand:
1758 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1759 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1760 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1761 LD->getSrcValueOffset(),
1762 LD->isVolatile(), LD->getAlignment());
1763 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1764 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1765 Tmp2 = LegalizeOp(Load.getValue(1));
1768 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1769 // Turn the unsupported load into an EXTLOAD followed by an explicit
1770 // zero/sign extend inreg.
1771 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1772 Tmp1, Tmp2, LD->getSrcValue(),
1773 LD->getSrcValueOffset(), SrcVT,
1774 LD->isVolatile(), LD->getAlignment());
1776 if (ExtType == ISD::SEXTLOAD)
1777 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1778 Result, DAG.getValueType(SrcVT));
1780 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1781 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1782 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1785 // Since loads produce two values, make sure to remember that we legalized
1787 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1788 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1789 return Op.ResNo ? Tmp2 : Tmp1;
1792 case ISD::EXTRACT_ELEMENT: {
1793 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1794 switch (getTypeAction(OpTy)) {
1795 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1797 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1799 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1800 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1801 TLI.getShiftAmountTy()));
1802 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1805 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1806 Node->getOperand(0));
1810 // Get both the low and high parts.
1811 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1812 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1813 Result = Tmp2; // 1 -> Hi
1815 Result = Tmp1; // 0 -> Lo
1821 case ISD::CopyToReg:
1822 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1824 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1825 "Register type must be legal!");
1826 // Legalize the incoming value (must be a legal type).
1827 Tmp2 = LegalizeOp(Node->getOperand(2));
1828 if (Node->getNumValues() == 1) {
1829 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1831 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1832 if (Node->getNumOperands() == 4) {
1833 Tmp3 = LegalizeOp(Node->getOperand(3));
1834 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1837 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1840 // Since this produces two values, make sure to remember that we legalized
1842 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1843 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1849 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1851 // Ensure that libcalls are emitted before a return.
1852 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1853 Tmp1 = LegalizeOp(Tmp1);
1854 LastCALLSEQ_END = DAG.getEntryNode();
1856 switch (Node->getNumOperands()) {
1858 Tmp2 = Node->getOperand(1);
1859 Tmp3 = Node->getOperand(2); // Signness
1860 switch (getTypeAction(Tmp2.getValueType())) {
1862 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1865 if (!MVT::isVector(Tmp2.getValueType())) {
1867 ExpandOp(Tmp2, Lo, Hi);
1869 // Big endian systems want the hi reg first.
1870 if (!TLI.isLittleEndian())
1874 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1876 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1877 Result = LegalizeOp(Result);
1879 SDNode *InVal = Tmp2.Val;
1880 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1881 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1883 // Figure out if there is a simple type corresponding to this Vector
1884 // type. If so, convert to the vector type.
1885 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1886 if (TLI.isTypeLegal(TVT)) {
1887 // Turn this into a return of the vector type.
1888 Tmp2 = LegalizeOp(Tmp2);
1889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1890 } else if (NumElems == 1) {
1891 // Turn this into a return of the scalar type.
1892 Tmp2 = ScalarizeVectorOp(Tmp2);
1893 Tmp2 = LegalizeOp(Tmp2);
1894 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1896 // FIXME: Returns of gcc generic vectors smaller than a legal type
1897 // should be returned in integer registers!
1899 // The scalarized value type may not be legal, e.g. it might require
1900 // promotion or expansion. Relegalize the return.
1901 Result = LegalizeOp(Result);
1903 // FIXME: Returns of gcc generic vectors larger than a legal vector
1904 // type should be returned by reference!
1906 SplitVectorOp(Tmp2, Lo, Hi);
1907 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1908 Result = LegalizeOp(Result);
1913 Tmp2 = PromoteOp(Node->getOperand(1));
1914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1915 Result = LegalizeOp(Result);
1920 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1922 default: { // ret <values>
1923 SmallVector<SDOperand, 8> NewValues;
1924 NewValues.push_back(Tmp1);
1925 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1926 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1928 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1929 NewValues.push_back(Node->getOperand(i+1));
1933 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1934 "FIXME: TODO: implement returning non-legal vector types!");
1935 ExpandOp(Node->getOperand(i), Lo, Hi);
1936 NewValues.push_back(Lo);
1937 NewValues.push_back(Node->getOperand(i+1));
1939 NewValues.push_back(Hi);
1940 NewValues.push_back(Node->getOperand(i+1));
1945 assert(0 && "Can't promote multiple return value yet!");
1948 if (NewValues.size() == Node->getNumOperands())
1949 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1951 Result = DAG.getNode(ISD::RET, MVT::Other,
1952 &NewValues[0], NewValues.size());
1957 if (Result.getOpcode() == ISD::RET) {
1958 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1959 default: assert(0 && "This action is not supported yet!");
1960 case TargetLowering::Legal: break;
1961 case TargetLowering::Custom:
1962 Tmp1 = TLI.LowerOperation(Result, DAG);
1963 if (Tmp1.Val) Result = Tmp1;
1969 StoreSDNode *ST = cast<StoreSDNode>(Node);
1970 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1971 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1972 int SVOffset = ST->getSrcValueOffset();
1973 unsigned Alignment = ST->getAlignment();
1974 bool isVolatile = ST->isVolatile();
1976 if (!ST->isTruncatingStore()) {
1977 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1978 // FIXME: We shouldn't do this for TargetConstantFP's.
1979 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1980 // to phase ordering between legalized code and the dag combiner. This
1981 // probably means that we need to integrate dag combiner and legalizer
1983 // We generally can't do this one for long doubles.
1984 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1985 if (CFP->getValueType(0) == MVT::f32) {
1986 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
1987 convertToAPInt().getZExtValue(),
1989 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1990 SVOffset, isVolatile, Alignment);
1992 } else if (CFP->getValueType(0) == MVT::f64) {
1993 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
1994 getZExtValue(), MVT::i64);
1995 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1996 SVOffset, isVolatile, Alignment);
2001 switch (getTypeAction(ST->getStoredVT())) {
2003 Tmp3 = LegalizeOp(ST->getValue());
2004 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2007 MVT::ValueType VT = Tmp3.getValueType();
2008 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2009 default: assert(0 && "This action is not supported yet!");
2010 case TargetLowering::Legal:
2011 // If this is an unaligned store and the target doesn't support it,
2013 if (!TLI.allowsUnalignedMemoryAccesses()) {
2014 unsigned ABIAlignment = TLI.getTargetData()->
2015 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2016 if (ST->getAlignment() < ABIAlignment)
2017 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2021 case TargetLowering::Custom:
2022 Tmp1 = TLI.LowerOperation(Result, DAG);
2023 if (Tmp1.Val) Result = Tmp1;
2025 case TargetLowering::Promote:
2026 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2027 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2028 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2029 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2030 ST->getSrcValue(), SVOffset, isVolatile,
2037 // Truncate the value and store the result.
2038 Tmp3 = PromoteOp(ST->getValue());
2039 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2040 SVOffset, ST->getStoredVT(),
2041 isVolatile, Alignment);
2045 unsigned IncrementSize = 0;
2048 // If this is a vector type, then we have to calculate the increment as
2049 // the product of the element size in bytes, and the number of elements
2050 // in the high half of the vector.
2051 if (MVT::isVector(ST->getValue().getValueType())) {
2052 SDNode *InVal = ST->getValue().Val;
2053 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2054 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2056 // Figure out if there is a simple type corresponding to this Vector
2057 // type. If so, convert to the vector type.
2058 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2059 if (TLI.isTypeLegal(TVT)) {
2060 // Turn this into a normal store of the vector type.
2061 Tmp3 = LegalizeOp(Node->getOperand(1));
2062 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2063 SVOffset, isVolatile, Alignment);
2064 Result = LegalizeOp(Result);
2066 } else if (NumElems == 1) {
2067 // Turn this into a normal store of the scalar type.
2068 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2069 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2070 SVOffset, isVolatile, Alignment);
2071 // The scalarized value type may not be legal, e.g. it might require
2072 // promotion or expansion. Relegalize the scalar store.
2073 Result = LegalizeOp(Result);
2076 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2077 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2080 ExpandOp(Node->getOperand(1), Lo, Hi);
2081 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2083 if (!TLI.isLittleEndian())
2087 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2088 SVOffset, isVolatile, Alignment);
2090 if (Hi.Val == NULL) {
2091 // Must be int <-> float one-to-one expansion.
2096 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2097 getIntPtrConstant(IncrementSize));
2098 assert(isTypeLegal(Tmp2.getValueType()) &&
2099 "Pointers must be legal!");
2100 SVOffset += IncrementSize;
2101 if (Alignment > IncrementSize)
2102 Alignment = IncrementSize;
2103 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2104 SVOffset, isVolatile, Alignment);
2105 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2110 assert(isTypeLegal(ST->getValue().getValueType()) &&
2111 "Cannot handle illegal TRUNCSTORE yet!");
2112 Tmp3 = LegalizeOp(ST->getValue());
2114 // The only promote case we handle is TRUNCSTORE:i1 X into
2115 // -> TRUNCSTORE:i8 (and X, 1)
2116 if (ST->getStoredVT() == MVT::i1 &&
2117 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2118 // Promote the bool to a mask then store.
2119 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2120 DAG.getConstant(1, Tmp3.getValueType()));
2121 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2123 isVolatile, Alignment);
2124 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2125 Tmp2 != ST->getBasePtr()) {
2126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2130 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2131 switch (TLI.getStoreXAction(StVT)) {
2132 default: assert(0 && "This action is not supported yet!");
2133 case TargetLowering::Legal:
2134 // If this is an unaligned store and the target doesn't support it,
2136 if (!TLI.allowsUnalignedMemoryAccesses()) {
2137 unsigned ABIAlignment = TLI.getTargetData()->
2138 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2139 if (ST->getAlignment() < ABIAlignment)
2140 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2144 case TargetLowering::Custom:
2145 Tmp1 = TLI.LowerOperation(Result, DAG);
2146 if (Tmp1.Val) Result = Tmp1;
2153 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2154 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2156 case ISD::STACKSAVE:
2157 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2158 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2159 Tmp1 = Result.getValue(0);
2160 Tmp2 = Result.getValue(1);
2162 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2163 default: assert(0 && "This action is not supported yet!");
2164 case TargetLowering::Legal: break;
2165 case TargetLowering::Custom:
2166 Tmp3 = TLI.LowerOperation(Result, DAG);
2168 Tmp1 = LegalizeOp(Tmp3);
2169 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2172 case TargetLowering::Expand:
2173 // Expand to CopyFromReg if the target set
2174 // StackPointerRegisterToSaveRestore.
2175 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2176 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2177 Node->getValueType(0));
2178 Tmp2 = Tmp1.getValue(1);
2180 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2181 Tmp2 = Node->getOperand(0);
2186 // Since stacksave produce two values, make sure to remember that we
2187 // legalized both of them.
2188 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2189 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2190 return Op.ResNo ? Tmp2 : Tmp1;
2192 case ISD::STACKRESTORE:
2193 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2194 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2195 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2197 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2198 default: assert(0 && "This action is not supported yet!");
2199 case TargetLowering::Legal: break;
2200 case TargetLowering::Custom:
2201 Tmp1 = TLI.LowerOperation(Result, DAG);
2202 if (Tmp1.Val) Result = Tmp1;
2204 case TargetLowering::Expand:
2205 // Expand to CopyToReg if the target set
2206 // StackPointerRegisterToSaveRestore.
2207 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2208 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2216 case ISD::READCYCLECOUNTER:
2217 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2218 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2219 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2220 Node->getValueType(0))) {
2221 default: assert(0 && "This action is not supported yet!");
2222 case TargetLowering::Legal:
2223 Tmp1 = Result.getValue(0);
2224 Tmp2 = Result.getValue(1);
2226 case TargetLowering::Custom:
2227 Result = TLI.LowerOperation(Result, DAG);
2228 Tmp1 = LegalizeOp(Result.getValue(0));
2229 Tmp2 = LegalizeOp(Result.getValue(1));
2233 // Since rdcc produce two values, make sure to remember that we legalized
2235 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2236 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2240 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2241 case Expand: assert(0 && "It's impossible to expand bools");
2243 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2246 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2247 // Make sure the condition is either zero or one.
2248 if (!DAG.MaskedValueIsZero(Tmp1,
2249 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2250 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2253 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2254 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2256 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2258 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2259 default: assert(0 && "This action is not supported yet!");
2260 case TargetLowering::Legal: break;
2261 case TargetLowering::Custom: {
2262 Tmp1 = TLI.LowerOperation(Result, DAG);
2263 if (Tmp1.Val) Result = Tmp1;
2266 case TargetLowering::Expand:
2267 if (Tmp1.getOpcode() == ISD::SETCC) {
2268 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2270 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2272 Result = DAG.getSelectCC(Tmp1,
2273 DAG.getConstant(0, Tmp1.getValueType()),
2274 Tmp2, Tmp3, ISD::SETNE);
2277 case TargetLowering::Promote: {
2278 MVT::ValueType NVT =
2279 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2280 unsigned ExtOp, TruncOp;
2281 if (MVT::isVector(Tmp2.getValueType())) {
2282 ExtOp = ISD::BIT_CONVERT;
2283 TruncOp = ISD::BIT_CONVERT;
2284 } else if (MVT::isInteger(Tmp2.getValueType())) {
2285 ExtOp = ISD::ANY_EXTEND;
2286 TruncOp = ISD::TRUNCATE;
2288 ExtOp = ISD::FP_EXTEND;
2289 TruncOp = ISD::FP_ROUND;
2291 // Promote each of the values to the new type.
2292 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2293 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2294 // Perform the larger operation, then round down.
2295 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2296 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2301 case ISD::SELECT_CC: {
2302 Tmp1 = Node->getOperand(0); // LHS
2303 Tmp2 = Node->getOperand(1); // RHS
2304 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2305 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2306 SDOperand CC = Node->getOperand(4);
2308 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2310 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2311 // the LHS is a legal SETCC itself. In this case, we need to compare
2312 // the result against zero to select between true and false values.
2313 if (Tmp2.Val == 0) {
2314 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2315 CC = DAG.getCondCode(ISD::SETNE);
2317 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2319 // Everything is legal, see if we should expand this op or something.
2320 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2321 default: assert(0 && "This action is not supported yet!");
2322 case TargetLowering::Legal: break;
2323 case TargetLowering::Custom:
2324 Tmp1 = TLI.LowerOperation(Result, DAG);
2325 if (Tmp1.Val) Result = Tmp1;
2331 Tmp1 = Node->getOperand(0);
2332 Tmp2 = Node->getOperand(1);
2333 Tmp3 = Node->getOperand(2);
2334 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2336 // If we had to Expand the SetCC operands into a SELECT node, then it may
2337 // not always be possible to return a true LHS & RHS. In this case, just
2338 // return the value we legalized, returned in the LHS
2339 if (Tmp2.Val == 0) {
2344 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2345 default: assert(0 && "Cannot handle this action for SETCC yet!");
2346 case TargetLowering::Custom:
2349 case TargetLowering::Legal:
2350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2352 Tmp4 = TLI.LowerOperation(Result, DAG);
2353 if (Tmp4.Val) Result = Tmp4;
2356 case TargetLowering::Promote: {
2357 // First step, figure out the appropriate operation to use.
2358 // Allow SETCC to not be supported for all legal data types
2359 // Mostly this targets FP
2360 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2361 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2363 // Scan for the appropriate larger type to use.
2365 NewInTy = (MVT::ValueType)(NewInTy+1);
2367 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2368 "Fell off of the edge of the integer world");
2369 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2370 "Fell off of the edge of the floating point world");
2372 // If the target supports SETCC of this type, use it.
2373 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2376 if (MVT::isInteger(NewInTy))
2377 assert(0 && "Cannot promote Legal Integer SETCC yet");
2379 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2380 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2382 Tmp1 = LegalizeOp(Tmp1);
2383 Tmp2 = LegalizeOp(Tmp2);
2384 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2385 Result = LegalizeOp(Result);
2388 case TargetLowering::Expand:
2389 // Expand a setcc node into a select_cc of the same condition, lhs, and
2390 // rhs that selects between const 1 (true) and const 0 (false).
2391 MVT::ValueType VT = Node->getValueType(0);
2392 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2393 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2400 case ISD::MEMMOVE: {
2401 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2402 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2404 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2405 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2406 case Expand: assert(0 && "Cannot expand a byte!");
2408 Tmp3 = LegalizeOp(Node->getOperand(2));
2411 Tmp3 = PromoteOp(Node->getOperand(2));
2415 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2419 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2421 // Length is too big, just take the lo-part of the length.
2423 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2427 Tmp4 = LegalizeOp(Node->getOperand(3));
2430 Tmp4 = PromoteOp(Node->getOperand(3));
2435 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2436 case Expand: assert(0 && "Cannot expand this yet!");
2438 Tmp5 = LegalizeOp(Node->getOperand(4));
2441 Tmp5 = PromoteOp(Node->getOperand(4));
2445 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2446 default: assert(0 && "This action not implemented for this operation!");
2447 case TargetLowering::Custom:
2450 case TargetLowering::Legal:
2451 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2453 Tmp1 = TLI.LowerOperation(Result, DAG);
2454 if (Tmp1.Val) Result = Tmp1;
2457 case TargetLowering::Expand: {
2458 // Otherwise, the target does not support this operation. Lower the
2459 // operation to an explicit libcall as appropriate.
2460 MVT::ValueType IntPtr = TLI.getPointerTy();
2461 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2462 TargetLowering::ArgListTy Args;
2463 TargetLowering::ArgListEntry Entry;
2465 const char *FnName = 0;
2466 if (Node->getOpcode() == ISD::MEMSET) {
2467 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2468 Args.push_back(Entry);
2469 // Extend the (previously legalized) ubyte argument to be an int value
2471 if (Tmp3.getValueType() > MVT::i32)
2472 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2474 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2475 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2476 Args.push_back(Entry);
2477 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2478 Args.push_back(Entry);
2481 } else if (Node->getOpcode() == ISD::MEMCPY ||
2482 Node->getOpcode() == ISD::MEMMOVE) {
2483 Entry.Ty = IntPtrTy;
2484 Entry.Node = Tmp2; Args.push_back(Entry);
2485 Entry.Node = Tmp3; Args.push_back(Entry);
2486 Entry.Node = Tmp4; Args.push_back(Entry);
2487 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2489 assert(0 && "Unknown op!");
2492 std::pair<SDOperand,SDOperand> CallResult =
2493 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2494 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2495 Result = CallResult.second;
2502 case ISD::SHL_PARTS:
2503 case ISD::SRA_PARTS:
2504 case ISD::SRL_PARTS: {
2505 SmallVector<SDOperand, 8> Ops;
2506 bool Changed = false;
2507 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2508 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2509 Changed |= Ops.back() != Node->getOperand(i);
2512 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2514 switch (TLI.getOperationAction(Node->getOpcode(),
2515 Node->getValueType(0))) {
2516 default: assert(0 && "This action is not supported yet!");
2517 case TargetLowering::Legal: break;
2518 case TargetLowering::Custom:
2519 Tmp1 = TLI.LowerOperation(Result, DAG);
2521 SDOperand Tmp2, RetVal(0, 0);
2522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2523 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2524 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2528 assert(RetVal.Val && "Illegal result number");
2534 // Since these produce multiple values, make sure to remember that we
2535 // legalized all of them.
2536 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2537 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2538 return Result.getValue(Op.ResNo);
2559 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2560 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2561 case Expand: assert(0 && "Not possible");
2563 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2566 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2570 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2572 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2573 default: assert(0 && "BinOp legalize operation not supported");
2574 case TargetLowering::Legal: break;
2575 case TargetLowering::Custom:
2576 Tmp1 = TLI.LowerOperation(Result, DAG);
2577 if (Tmp1.Val) Result = Tmp1;
2579 case TargetLowering::Expand: {
2580 if (Node->getValueType(0) == MVT::i32) {
2581 switch (Node->getOpcode()) {
2582 default: assert(0 && "Do not know how to expand this integer BinOp!");
2585 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2586 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2588 bool isSigned = Node->getOpcode() == ISD::SDIV;
2589 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2594 assert(MVT::isVector(Node->getValueType(0)) &&
2595 "Cannot expand this binary operator!");
2596 // Expand the operation into a bunch of nasty scalar code.
2597 SmallVector<SDOperand, 8> Ops;
2598 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2599 MVT::ValueType PtrVT = TLI.getPointerTy();
2600 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2602 SDOperand Idx = DAG.getConstant(i, PtrVT);
2603 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2604 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2605 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2607 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2608 &Ops[0], Ops.size());
2611 case TargetLowering::Promote: {
2612 switch (Node->getOpcode()) {
2613 default: assert(0 && "Do not know how to promote this BinOp!");
2617 MVT::ValueType OVT = Node->getValueType(0);
2618 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2619 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2620 // Bit convert each of the values to the new type.
2621 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2622 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2623 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2624 // Bit convert the result back the original type.
2625 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2633 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2634 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2635 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2636 case Expand: assert(0 && "Not possible");
2638 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2641 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2645 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2647 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2648 default: assert(0 && "Operation not supported");
2649 case TargetLowering::Custom:
2650 Tmp1 = TLI.LowerOperation(Result, DAG);
2651 if (Tmp1.Val) Result = Tmp1;
2653 case TargetLowering::Legal: break;
2654 case TargetLowering::Expand: {
2655 // If this target supports fabs/fneg natively and select is cheap,
2656 // do this efficiently.
2657 if (!TLI.isSelectExpensive() &&
2658 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2659 TargetLowering::Legal &&
2660 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2661 TargetLowering::Legal) {
2662 // Get the sign bit of the RHS.
2663 MVT::ValueType IVT =
2664 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2665 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2666 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2667 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2668 // Get the absolute value of the result.
2669 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2670 // Select between the nabs and abs value based on the sign bit of
2672 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2673 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2676 Result = LegalizeOp(Result);
2680 // Otherwise, do bitwise ops!
2681 MVT::ValueType NVT =
2682 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2683 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2684 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2685 Result = LegalizeOp(Result);
2693 Tmp1 = LegalizeOp(Node->getOperand(0));
2694 Tmp2 = LegalizeOp(Node->getOperand(1));
2695 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2696 // Since this produces two values, make sure to remember that we legalized
2698 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2699 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2704 Tmp1 = LegalizeOp(Node->getOperand(0));
2705 Tmp2 = LegalizeOp(Node->getOperand(1));
2706 Tmp3 = LegalizeOp(Node->getOperand(2));
2707 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2708 // Since this produces two values, make sure to remember that we legalized
2710 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2711 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2714 case ISD::BUILD_PAIR: {
2715 MVT::ValueType PairTy = Node->getValueType(0);
2716 // TODO: handle the case where the Lo and Hi operands are not of legal type
2717 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2718 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2719 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2720 case TargetLowering::Promote:
2721 case TargetLowering::Custom:
2722 assert(0 && "Cannot promote/custom this yet!");
2723 case TargetLowering::Legal:
2724 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2725 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2727 case TargetLowering::Expand:
2728 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2729 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2730 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2731 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2732 TLI.getShiftAmountTy()));
2733 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2742 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2743 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2745 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2746 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2747 case TargetLowering::Custom:
2750 case TargetLowering::Legal:
2751 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2753 Tmp1 = TLI.LowerOperation(Result, DAG);
2754 if (Tmp1.Val) Result = Tmp1;
2757 case TargetLowering::Expand:
2758 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2759 bool isSigned = DivOpc == ISD::SDIV;
2760 if (MVT::isInteger(Node->getValueType(0))) {
2761 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2762 TargetLowering::Legal) {
2764 MVT::ValueType VT = Node->getValueType(0);
2765 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2766 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2767 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2769 assert(Node->getValueType(0) == MVT::i32 &&
2770 "Cannot expand this binary operator!");
2771 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2772 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2774 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2777 // Floating point mod -> fmod libcall.
2778 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2779 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2781 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2782 false/*sign irrelevant*/, Dummy);
2788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2789 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2791 MVT::ValueType VT = Node->getValueType(0);
2792 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2793 default: assert(0 && "This action is not supported yet!");
2794 case TargetLowering::Custom:
2797 case TargetLowering::Legal:
2798 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2799 Result = Result.getValue(0);
2800 Tmp1 = Result.getValue(1);
2803 Tmp2 = TLI.LowerOperation(Result, DAG);
2805 Result = LegalizeOp(Tmp2);
2806 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2810 case TargetLowering::Expand: {
2811 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2812 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2813 SV->getValue(), SV->getOffset());
2814 // Increment the pointer, VAList, to the next vaarg
2815 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2816 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2817 TLI.getPointerTy()));
2818 // Store the incremented VAList to the legalized pointer
2819 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2821 // Load the actual argument out of the pointer VAList
2822 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2823 Tmp1 = LegalizeOp(Result.getValue(1));
2824 Result = LegalizeOp(Result);
2828 // Since VAARG produces two values, make sure to remember that we
2829 // legalized both of them.
2830 AddLegalizedOperand(SDOperand(Node, 0), Result);
2831 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2832 return Op.ResNo ? Tmp1 : Result;
2836 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2837 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2838 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2840 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2841 default: assert(0 && "This action is not supported yet!");
2842 case TargetLowering::Custom:
2845 case TargetLowering::Legal:
2846 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2847 Node->getOperand(3), Node->getOperand(4));
2849 Tmp1 = TLI.LowerOperation(Result, DAG);
2850 if (Tmp1.Val) Result = Tmp1;
2853 case TargetLowering::Expand:
2854 // This defaults to loading a pointer from the input and storing it to the
2855 // output, returning the chain.
2856 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2857 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2858 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2860 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2867 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2868 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2870 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2871 default: assert(0 && "This action is not supported yet!");
2872 case TargetLowering::Custom:
2875 case TargetLowering::Legal:
2876 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2878 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2879 if (Tmp1.Val) Result = Tmp1;
2882 case TargetLowering::Expand:
2883 Result = Tmp1; // Default to a no-op, return the chain
2889 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2890 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2892 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2894 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2895 default: assert(0 && "This action is not supported yet!");
2896 case TargetLowering::Legal: break;
2897 case TargetLowering::Custom:
2898 Tmp1 = TLI.LowerOperation(Result, DAG);
2899 if (Tmp1.Val) Result = Tmp1;
2906 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2907 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2908 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2909 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2911 assert(0 && "ROTL/ROTR legalize operation not supported");
2913 case TargetLowering::Legal:
2915 case TargetLowering::Custom:
2916 Tmp1 = TLI.LowerOperation(Result, DAG);
2917 if (Tmp1.Val) Result = Tmp1;
2919 case TargetLowering::Promote:
2920 assert(0 && "Do not know how to promote ROTL/ROTR");
2922 case TargetLowering::Expand:
2923 assert(0 && "Do not know how to expand ROTL/ROTR");
2929 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2930 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2931 case TargetLowering::Custom:
2932 assert(0 && "Cannot custom legalize this yet!");
2933 case TargetLowering::Legal:
2934 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2936 case TargetLowering::Promote: {
2937 MVT::ValueType OVT = Tmp1.getValueType();
2938 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2939 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2941 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2942 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2943 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2944 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2947 case TargetLowering::Expand:
2948 Result = ExpandBSWAP(Tmp1);
2956 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2957 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2958 case TargetLowering::Custom:
2959 case TargetLowering::Legal:
2960 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2961 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
2962 TargetLowering::Custom) {
2963 Tmp1 = TLI.LowerOperation(Result, DAG);
2969 case TargetLowering::Promote: {
2970 MVT::ValueType OVT = Tmp1.getValueType();
2971 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2973 // Zero extend the argument.
2974 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2975 // Perform the larger operation, then subtract if needed.
2976 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2977 switch (Node->getOpcode()) {
2982 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2983 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2984 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2986 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2987 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2990 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2991 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2992 DAG.getConstant(MVT::getSizeInBits(NVT) -
2993 MVT::getSizeInBits(OVT), NVT));
2998 case TargetLowering::Expand:
2999 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3010 Tmp1 = LegalizeOp(Node->getOperand(0));
3011 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3012 case TargetLowering::Promote:
3013 case TargetLowering::Custom:
3016 case TargetLowering::Legal:
3017 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3019 Tmp1 = TLI.LowerOperation(Result, DAG);
3020 if (Tmp1.Val) Result = Tmp1;
3023 case TargetLowering::Expand:
3024 switch (Node->getOpcode()) {
3025 default: assert(0 && "Unreachable!");
3027 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3028 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3029 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3032 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3033 MVT::ValueType VT = Node->getValueType(0);
3034 Tmp2 = DAG.getConstantFP(0.0, VT);
3035 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3036 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3037 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3043 MVT::ValueType VT = Node->getValueType(0);
3044 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3045 switch(Node->getOpcode()) {
3047 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
3050 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
3053 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
3055 default: assert(0 && "Unreachable!");
3058 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3059 false/*sign irrelevant*/, Dummy);
3067 // We always lower FPOWI into a libcall. No target support it yet.
3068 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
3069 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
3071 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3072 false/*sign irrelevant*/, Dummy);
3075 case ISD::BIT_CONVERT:
3076 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3077 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3078 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3079 // The input has to be a vector type, we have to either scalarize it, pack
3080 // it, or convert it based on whether the input vector type is legal.
3081 SDNode *InVal = Node->getOperand(0).Val;
3082 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3083 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3085 // Figure out if there is a simple type corresponding to this Vector
3086 // type. If so, convert to the vector type.
3087 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3088 if (TLI.isTypeLegal(TVT)) {
3089 // Turn this into a bit convert of the vector input.
3090 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3091 LegalizeOp(Node->getOperand(0)));
3093 } else if (NumElems == 1) {
3094 // Turn this into a bit convert of the scalar input.
3095 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3096 ScalarizeVectorOp(Node->getOperand(0)));
3099 // FIXME: UNIMP! Store then reload
3100 assert(0 && "Cast from unsupported vector type not implemented yet!");
3103 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3104 Node->getOperand(0).getValueType())) {
3105 default: assert(0 && "Unknown operation action!");
3106 case TargetLowering::Expand:
3107 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3109 case TargetLowering::Legal:
3110 Tmp1 = LegalizeOp(Node->getOperand(0));
3111 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3117 // Conversion operators. The source and destination have different types.
3118 case ISD::SINT_TO_FP:
3119 case ISD::UINT_TO_FP: {
3120 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3121 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3123 switch (TLI.getOperationAction(Node->getOpcode(),
3124 Node->getOperand(0).getValueType())) {
3125 default: assert(0 && "Unknown operation action!");
3126 case TargetLowering::Custom:
3129 case TargetLowering::Legal:
3130 Tmp1 = LegalizeOp(Node->getOperand(0));
3131 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3133 Tmp1 = TLI.LowerOperation(Result, DAG);
3134 if (Tmp1.Val) Result = Tmp1;
3137 case TargetLowering::Expand:
3138 Result = ExpandLegalINT_TO_FP(isSigned,
3139 LegalizeOp(Node->getOperand(0)),
3140 Node->getValueType(0));
3142 case TargetLowering::Promote:
3143 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3144 Node->getValueType(0),
3150 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3151 Node->getValueType(0), Node->getOperand(0));
3154 Tmp1 = PromoteOp(Node->getOperand(0));
3156 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3157 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3159 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3160 Node->getOperand(0).getValueType());
3162 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3163 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3169 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3171 Tmp1 = LegalizeOp(Node->getOperand(0));
3172 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3175 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3177 // Since the result is legal, we should just be able to truncate the low
3178 // part of the source.
3179 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3182 Result = PromoteOp(Node->getOperand(0));
3183 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3188 case ISD::FP_TO_SINT:
3189 case ISD::FP_TO_UINT:
3190 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3192 Tmp1 = LegalizeOp(Node->getOperand(0));
3194 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3195 default: assert(0 && "Unknown operation action!");
3196 case TargetLowering::Custom:
3199 case TargetLowering::Legal:
3200 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3202 Tmp1 = TLI.LowerOperation(Result, DAG);
3203 if (Tmp1.Val) Result = Tmp1;
3206 case TargetLowering::Promote:
3207 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3208 Node->getOpcode() == ISD::FP_TO_SINT);
3210 case TargetLowering::Expand:
3211 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3212 SDOperand True, False;
3213 MVT::ValueType VT = Node->getOperand(0).getValueType();
3214 MVT::ValueType NVT = Node->getValueType(0);
3215 unsigned ShiftAmt = MVT::getSizeInBits(NVT)-1;
3216 const uint64_t zero[] = {0, 0};
3217 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3218 uint64_t x = 1ULL << ShiftAmt;
3219 (void)apf.convertFromInteger(&x, MVT::getSizeInBits(NVT), false,
3220 APFloat::rmTowardZero);
3221 Tmp2 = DAG.getConstantFP(apf, VT);
3222 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3223 Node->getOperand(0), Tmp2, ISD::SETLT);
3224 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3225 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3226 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3228 False = DAG.getNode(ISD::XOR, NVT, False,
3229 DAG.getConstant(1ULL << ShiftAmt, NVT));
3230 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3233 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3239 // Convert f32 / f64 to i32 / i64.
3240 MVT::ValueType VT = Op.getValueType();
3241 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3242 switch (Node->getOpcode()) {
3243 case ISD::FP_TO_SINT: {
3244 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3245 if (OVT == MVT::f32)
3246 LC = (VT == MVT::i32)
3247 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3248 else if (OVT == MVT::f64)
3249 LC = (VT == MVT::i32)
3250 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3251 else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
3252 assert(VT == MVT::i64);
3253 LC = RTLIB::FPTOSINT_LD_I64;
3257 case ISD::FP_TO_UINT: {
3258 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3259 if (OVT == MVT::f32)
3260 LC = (VT == MVT::i32)
3261 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3262 else if (OVT == MVT::f64)
3263 LC = (VT == MVT::i32)
3264 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3265 else if (OVT == MVT::f80 || OVT == MVT::f128 || OVT == MVT::ppcf128) {
3266 LC = (VT == MVT::i32)
3267 ? RTLIB::FPTOUINT_LD_I32 : RTLIB::FPTOUINT_LD_I64;
3271 default: assert(0 && "Unreachable!");
3274 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3275 false/*sign irrelevant*/, Dummy);
3279 Tmp1 = PromoteOp(Node->getOperand(0));
3280 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3281 Result = LegalizeOp(Result);
3286 case ISD::FP_EXTEND:
3287 case ISD::FP_ROUND: {
3288 MVT::ValueType newVT = Op.getValueType();
3289 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3290 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3291 // The only way we can lower this is to turn it into a STORE,
3292 // LOAD pair, targetting a temporary location (a stack slot).
3294 // NOTE: there is a choice here between constantly creating new stack
3295 // slots and always reusing the same one. We currently always create
3296 // new ones, as reuse may inhibit scheduling.
3297 MVT::ValueType slotVT =
3298 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3299 const Type *Ty = MVT::getTypeForValueType(slotVT);
3300 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3301 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3302 MachineFunction &MF = DAG.getMachineFunction();
3304 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3305 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3306 if (Node->getOpcode() == ISD::FP_EXTEND) {
3307 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3308 StackSlot, NULL, 0);
3309 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3310 Result, StackSlot, NULL, 0, oldVT);
3312 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3313 StackSlot, NULL, 0, newVT);
3314 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
3320 case ISD::ANY_EXTEND:
3321 case ISD::ZERO_EXTEND:
3322 case ISD::SIGN_EXTEND:
3323 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3324 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3326 Tmp1 = LegalizeOp(Node->getOperand(0));
3327 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3330 switch (Node->getOpcode()) {
3331 case ISD::ANY_EXTEND:
3332 Tmp1 = PromoteOp(Node->getOperand(0));
3333 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3335 case ISD::ZERO_EXTEND:
3336 Result = PromoteOp(Node->getOperand(0));
3337 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3338 Result = DAG.getZeroExtendInReg(Result,
3339 Node->getOperand(0).getValueType());
3341 case ISD::SIGN_EXTEND:
3342 Result = PromoteOp(Node->getOperand(0));
3343 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3344 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3346 DAG.getValueType(Node->getOperand(0).getValueType()));
3348 case ISD::FP_EXTEND:
3349 Result = PromoteOp(Node->getOperand(0));
3350 if (Result.getValueType() != Op.getValueType())
3351 // Dynamically dead while we have only 2 FP types.
3352 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3355 Result = PromoteOp(Node->getOperand(0));
3356 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3361 case ISD::FP_ROUND_INREG:
3362 case ISD::SIGN_EXTEND_INREG: {
3363 Tmp1 = LegalizeOp(Node->getOperand(0));
3364 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3366 // If this operation is not supported, convert it to a shl/shr or load/store
3368 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3369 default: assert(0 && "This action not supported for this op yet!");
3370 case TargetLowering::Legal:
3371 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3373 case TargetLowering::Expand:
3374 // If this is an integer extend and shifts are supported, do that.
3375 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3376 // NOTE: we could fall back on load/store here too for targets without
3377 // SAR. However, it is doubtful that any exist.
3378 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3379 MVT::getSizeInBits(ExtraVT);
3380 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3381 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3382 Node->getOperand(0), ShiftCst);
3383 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3385 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3386 // The only way we can lower this is to turn it into a TRUNCSTORE,
3387 // EXTLOAD pair, targetting a temporary location (a stack slot).
3389 // NOTE: there is a choice here between constantly creating new stack
3390 // slots and always reusing the same one. We currently always create
3391 // new ones, as reuse may inhibit scheduling.
3392 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3393 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3394 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3395 MachineFunction &MF = DAG.getMachineFunction();
3397 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3398 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3399 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3400 StackSlot, NULL, 0, ExtraVT);
3401 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3402 Result, StackSlot, NULL, 0, ExtraVT);
3404 assert(0 && "Unknown op");
3410 case ISD::TRAMPOLINE: {
3412 for (unsigned i = 0; i != 6; ++i)
3413 Ops[i] = LegalizeOp(Node->getOperand(i));
3414 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3415 // The only option for this node is to custom lower it.
3416 Result = TLI.LowerOperation(Result, DAG);
3417 assert(Result.Val && "Should always custom lower!");
3419 // Since trampoline produces two values, make sure to remember that we
3420 // legalized both of them.
3421 Tmp1 = LegalizeOp(Result.getValue(1));
3422 Result = LegalizeOp(Result);
3423 AddLegalizedOperand(SDOperand(Node, 0), Result);
3424 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3425 return Op.ResNo ? Tmp1 : Result;
3429 assert(Result.getValueType() == Op.getValueType() &&
3430 "Bad legalization!");
3432 // Make sure that the generated code is itself legal.
3434 Result = LegalizeOp(Result);
3436 // Note that LegalizeOp may be reentered even from single-use nodes, which
3437 // means that we always must cache transformed nodes.
3438 AddLegalizedOperand(Op, Result);
3442 /// PromoteOp - Given an operation that produces a value in an invalid type,
3443 /// promote it to compute the value into a larger type. The produced value will
3444 /// have the correct bits for the low portion of the register, but no guarantee
3445 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3446 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3447 MVT::ValueType VT = Op.getValueType();
3448 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3449 assert(getTypeAction(VT) == Promote &&
3450 "Caller should expand or legalize operands that are not promotable!");
3451 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3452 "Cannot promote to smaller type!");
3454 SDOperand Tmp1, Tmp2, Tmp3;
3456 SDNode *Node = Op.Val;
3458 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3459 if (I != PromotedNodes.end()) return I->second;
3461 switch (Node->getOpcode()) {
3462 case ISD::CopyFromReg:
3463 assert(0 && "CopyFromReg must be legal!");
3466 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3468 assert(0 && "Do not know how to promote this operator!");
3471 Result = DAG.getNode(ISD::UNDEF, NVT);
3475 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3477 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3478 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3480 case ISD::ConstantFP:
3481 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3482 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3486 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3487 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3488 Node->getOperand(1), Node->getOperand(2));
3492 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3494 Result = LegalizeOp(Node->getOperand(0));
3495 assert(Result.getValueType() >= NVT &&
3496 "This truncation doesn't make sense!");
3497 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3498 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3501 // The truncation is not required, because we don't guarantee anything
3502 // about high bits anyway.
3503 Result = PromoteOp(Node->getOperand(0));
3506 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3507 // Truncate the low part of the expanded value to the result type
3508 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3511 case ISD::SIGN_EXTEND:
3512 case ISD::ZERO_EXTEND:
3513 case ISD::ANY_EXTEND:
3514 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3515 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3517 // Input is legal? Just do extend all the way to the larger type.
3518 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3521 // Promote the reg if it's smaller.
3522 Result = PromoteOp(Node->getOperand(0));
3523 // The high bits are not guaranteed to be anything. Insert an extend.
3524 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3525 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3526 DAG.getValueType(Node->getOperand(0).getValueType()));
3527 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3528 Result = DAG.getZeroExtendInReg(Result,
3529 Node->getOperand(0).getValueType());
3533 case ISD::BIT_CONVERT:
3534 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3535 Result = PromoteOp(Result);
3538 case ISD::FP_EXTEND:
3539 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3541 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3542 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3543 case Promote: assert(0 && "Unreachable with 2 FP types!");
3545 // Input is legal? Do an FP_ROUND_INREG.
3546 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3547 DAG.getValueType(VT));
3552 case ISD::SINT_TO_FP:
3553 case ISD::UINT_TO_FP:
3554 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3556 // No extra round required here.
3557 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3561 Result = PromoteOp(Node->getOperand(0));
3562 if (Node->getOpcode() == ISD::SINT_TO_FP)
3563 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3565 DAG.getValueType(Node->getOperand(0).getValueType()));
3567 Result = DAG.getZeroExtendInReg(Result,
3568 Node->getOperand(0).getValueType());
3569 // No extra round required here.
3570 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3573 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3574 Node->getOperand(0));
3575 // Round if we cannot tolerate excess precision.
3576 if (NoExcessFPPrecision)
3577 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3578 DAG.getValueType(VT));
3583 case ISD::SIGN_EXTEND_INREG:
3584 Result = PromoteOp(Node->getOperand(0));
3585 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3586 Node->getOperand(1));
3588 case ISD::FP_TO_SINT:
3589 case ISD::FP_TO_UINT:
3590 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3593 Tmp1 = Node->getOperand(0);
3596 // The input result is prerounded, so we don't have to do anything
3598 Tmp1 = PromoteOp(Node->getOperand(0));
3601 // If we're promoting a UINT to a larger size, check to see if the new node
3602 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3603 // we can use that instead. This allows us to generate better code for
3604 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3605 // legal, such as PowerPC.
3606 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3607 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3608 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3609 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3610 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3612 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3618 Tmp1 = PromoteOp(Node->getOperand(0));
3619 assert(Tmp1.getValueType() == NVT);
3620 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3621 // NOTE: we do not have to do any extra rounding here for
3622 // NoExcessFPPrecision, because we know the input will have the appropriate
3623 // precision, and these operations don't modify precision at all.
3629 Tmp1 = PromoteOp(Node->getOperand(0));
3630 assert(Tmp1.getValueType() == NVT);
3631 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3632 if (NoExcessFPPrecision)
3633 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3634 DAG.getValueType(VT));
3638 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3639 // directly as well, which may be better.
3640 Tmp1 = PromoteOp(Node->getOperand(0));
3641 assert(Tmp1.getValueType() == NVT);
3642 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3643 if (NoExcessFPPrecision)
3644 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3645 DAG.getValueType(VT));
3655 // The input may have strange things in the top bits of the registers, but
3656 // these operations don't care. They may have weird bits going out, but
3657 // that too is okay if they are integer operations.
3658 Tmp1 = PromoteOp(Node->getOperand(0));
3659 Tmp2 = PromoteOp(Node->getOperand(1));
3660 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3661 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3666 Tmp1 = PromoteOp(Node->getOperand(0));
3667 Tmp2 = PromoteOp(Node->getOperand(1));
3668 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3669 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3671 // Floating point operations will give excess precision that we may not be
3672 // able to tolerate. If we DO allow excess precision, just leave it,
3673 // otherwise excise it.
3674 // FIXME: Why would we need to round FP ops more than integer ones?
3675 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3676 if (NoExcessFPPrecision)
3677 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3678 DAG.getValueType(VT));
3683 // These operators require that their input be sign extended.
3684 Tmp1 = PromoteOp(Node->getOperand(0));
3685 Tmp2 = PromoteOp(Node->getOperand(1));
3686 if (MVT::isInteger(NVT)) {
3687 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3688 DAG.getValueType(VT));
3689 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3690 DAG.getValueType(VT));
3692 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3694 // Perform FP_ROUND: this is probably overly pessimistic.
3695 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3696 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3697 DAG.getValueType(VT));
3701 case ISD::FCOPYSIGN:
3702 // These operators require that their input be fp extended.
3703 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3705 Tmp1 = LegalizeOp(Node->getOperand(0));
3708 Tmp1 = PromoteOp(Node->getOperand(0));
3711 assert(0 && "not implemented");
3713 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3715 Tmp2 = LegalizeOp(Node->getOperand(1));
3718 Tmp2 = PromoteOp(Node->getOperand(1));
3721 assert(0 && "not implemented");
3723 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3725 // Perform FP_ROUND: this is probably overly pessimistic.
3726 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3727 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3728 DAG.getValueType(VT));
3733 // These operators require that their input be zero extended.
3734 Tmp1 = PromoteOp(Node->getOperand(0));
3735 Tmp2 = PromoteOp(Node->getOperand(1));
3736 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3737 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3738 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3739 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3743 Tmp1 = PromoteOp(Node->getOperand(0));
3744 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3747 // The input value must be properly sign extended.
3748 Tmp1 = PromoteOp(Node->getOperand(0));
3749 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3750 DAG.getValueType(VT));
3751 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3754 // The input value must be properly zero extended.
3755 Tmp1 = PromoteOp(Node->getOperand(0));
3756 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3757 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3761 Tmp1 = Node->getOperand(0); // Get the chain.
3762 Tmp2 = Node->getOperand(1); // Get the pointer.
3763 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3764 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3765 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3767 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3768 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3769 SV->getValue(), SV->getOffset());
3770 // Increment the pointer, VAList, to the next vaarg
3771 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3772 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3773 TLI.getPointerTy()));
3774 // Store the incremented VAList to the legalized pointer
3775 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3777 // Load the actual argument out of the pointer VAList
3778 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3780 // Remember that we legalized the chain.
3781 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3785 LoadSDNode *LD = cast<LoadSDNode>(Node);
3786 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3787 ? ISD::EXTLOAD : LD->getExtensionType();
3788 Result = DAG.getExtLoad(ExtType, NVT,
3789 LD->getChain(), LD->getBasePtr(),
3790 LD->getSrcValue(), LD->getSrcValueOffset(),
3793 LD->getAlignment());
3794 // Remember that we legalized the chain.
3795 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3799 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3800 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3801 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3803 case ISD::SELECT_CC:
3804 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3805 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3806 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3807 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3810 Tmp1 = Node->getOperand(0);
3811 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3812 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3813 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3814 DAG.getConstant(MVT::getSizeInBits(NVT) -
3815 MVT::getSizeInBits(VT),
3816 TLI.getShiftAmountTy()));
3821 // Zero extend the argument
3822 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3823 // Perform the larger operation, then subtract if needed.
3824 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3825 switch(Node->getOpcode()) {
3830 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3831 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3832 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3834 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3835 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3838 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3839 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3840 DAG.getConstant(MVT::getSizeInBits(NVT) -
3841 MVT::getSizeInBits(VT), NVT));
3845 case ISD::EXTRACT_SUBVECTOR:
3846 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3848 case ISD::EXTRACT_VECTOR_ELT:
3849 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3853 assert(Result.Val && "Didn't set a result!");
3855 // Make sure the result is itself legal.
3856 Result = LegalizeOp(Result);
3858 // Remember that we promoted this!
3859 AddPromotedOperand(Op, Result);
3863 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3864 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3865 /// based on the vector type. The return type of this matches the element type
3866 /// of the vector, which may not be legal for the target.
3867 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3868 // We know that operand #0 is the Vec vector. If the index is a constant
3869 // or if the invec is a supported hardware type, we can use it. Otherwise,
3870 // lower to a store then an indexed load.
3871 SDOperand Vec = Op.getOperand(0);
3872 SDOperand Idx = Op.getOperand(1);
3874 MVT::ValueType TVT = Vec.getValueType();
3875 unsigned NumElems = MVT::getVectorNumElements(TVT);
3877 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3878 default: assert(0 && "This action is not supported yet!");
3879 case TargetLowering::Custom: {
3880 Vec = LegalizeOp(Vec);
3881 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3882 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3887 case TargetLowering::Legal:
3888 if (isTypeLegal(TVT)) {
3889 Vec = LegalizeOp(Vec);
3890 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3894 case TargetLowering::Expand:
3898 if (NumElems == 1) {
3899 // This must be an access of the only element. Return it.
3900 Op = ScalarizeVectorOp(Vec);
3901 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3902 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3904 SplitVectorOp(Vec, Lo, Hi);
3905 if (CIdx->getValue() < NumElems/2) {
3909 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3910 Idx.getValueType());
3913 // It's now an extract from the appropriate high or low part. Recurse.
3914 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3915 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3917 // Store the value to a temporary stack slot, then LOAD the scalar
3918 // element back out.
3919 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3920 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3922 // Add the offset to the index.
3923 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3924 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3925 DAG.getConstant(EltSize, Idx.getValueType()));
3926 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3928 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3933 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3934 /// we assume the operation can be split if it is not already legal.
3935 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3936 // We know that operand #0 is the Vec vector. For now we assume the index
3937 // is a constant and that the extracted result is a supported hardware type.
3938 SDOperand Vec = Op.getOperand(0);
3939 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3941 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3943 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3944 // This must be an access of the desired vector length. Return it.
3948 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3950 SplitVectorOp(Vec, Lo, Hi);
3951 if (CIdx->getValue() < NumElems/2) {
3955 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3958 // It's now an extract from the appropriate high or low part. Recurse.
3959 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3960 return ExpandEXTRACT_SUBVECTOR(Op);
3963 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3964 /// with condition CC on the current target. This usually involves legalizing
3965 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3966 /// there may be no choice but to create a new SetCC node to represent the
3967 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3968 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3969 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3972 SDOperand Tmp1, Tmp2, Result;
3974 switch (getTypeAction(LHS.getValueType())) {
3976 Tmp1 = LegalizeOp(LHS); // LHS
3977 Tmp2 = LegalizeOp(RHS); // RHS
3980 Tmp1 = PromoteOp(LHS); // LHS
3981 Tmp2 = PromoteOp(RHS); // RHS
3983 // If this is an FP compare, the operands have already been extended.
3984 if (MVT::isInteger(LHS.getValueType())) {
3985 MVT::ValueType VT = LHS.getValueType();
3986 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3988 // Otherwise, we have to insert explicit sign or zero extends. Note
3989 // that we could insert sign extends for ALL conditions, but zero extend
3990 // is cheaper on many machines (an AND instead of two shifts), so prefer
3992 switch (cast<CondCodeSDNode>(CC)->get()) {
3993 default: assert(0 && "Unknown integer comparison!");
4000 // ALL of these operations will work if we either sign or zero extend
4001 // the operands (including the unsigned comparisons!). Zero extend is
4002 // usually a simpler/cheaper operation, so prefer it.
4003 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4004 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4010 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4011 DAG.getValueType(VT));
4012 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4013 DAG.getValueType(VT));
4019 MVT::ValueType VT = LHS.getValueType();
4020 if (VT == MVT::f32 || VT == MVT::f64) {
4021 // Expand into one or more soft-fp libcall(s).
4022 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4023 switch (cast<CondCodeSDNode>(CC)->get()) {
4026 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4030 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4034 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4038 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4042 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4046 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4049 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4052 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4055 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4056 switch (cast<CondCodeSDNode>(CC)->get()) {
4058 // SETONE = SETOLT | SETOGT
4059 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4062 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4065 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4068 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4071 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4074 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4076 default: assert(0 && "Unsupported FP setcc!");
4081 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4082 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4083 false /*sign irrelevant*/, Dummy);
4084 Tmp2 = DAG.getConstant(0, MVT::i32);
4085 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4086 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4087 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4088 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4089 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4090 false /*sign irrelevant*/, Dummy);
4091 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4092 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4093 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4101 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4102 ExpandOp(LHS, LHSLo, LHSHi);
4103 ExpandOp(RHS, RHSLo, RHSHi);
4104 switch (cast<CondCodeSDNode>(CC)->get()) {
4108 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4109 if (RHSCST->isAllOnesValue()) {
4110 // Comparison to -1.
4111 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4116 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4117 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4118 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4119 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4122 // If this is a comparison of the sign bit, just look at the top part.
4124 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4125 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4126 CST->getValue() == 0) || // X < 0
4127 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4128 CST->isAllOnesValue())) { // X > -1
4134 // FIXME: This generated code sucks.
4135 ISD::CondCode LowCC;
4136 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4138 default: assert(0 && "Unknown integer setcc!");
4140 case ISD::SETULT: LowCC = ISD::SETULT; break;
4142 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4144 case ISD::SETULE: LowCC = ISD::SETULE; break;
4146 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4149 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4150 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4151 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4153 // NOTE: on targets without efficient SELECT of bools, we can always use
4154 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4155 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4156 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4157 false, DagCombineInfo);
4159 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4160 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4161 CCCode, false, DagCombineInfo);
4163 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
4165 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4166 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4167 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4168 (Tmp2C && Tmp2C->getValue() == 0 &&
4169 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4170 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4171 (Tmp2C && Tmp2C->getValue() == 1 &&
4172 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4173 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4174 // low part is known false, returns high part.
4175 // For LE / GE, if high part is known false, ignore the low part.
4176 // For LT / GT, if high part is known true, ignore the low part.
4180 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4181 ISD::SETEQ, false, DagCombineInfo);
4183 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4184 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4185 Result, Tmp1, Tmp2));
4196 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4197 /// The resultant code need not be legal. Note that SrcOp is the input operand
4198 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4199 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4201 // Create the stack frame object.
4202 SDOperand FIPtr = CreateStackTemporary(DestVT);
4204 // Emit a store to the stack slot.
4205 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4206 // Result is a load from the stack slot.
4207 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4210 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4211 // Create a vector sized/aligned stack slot, store the value to element #0,
4212 // then load the whole vector back out.
4213 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
4214 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4216 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4220 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4221 /// support the operation, but do support the resultant vector type.
4222 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4224 // If the only non-undef value is the low element, turn this into a
4225 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4226 unsigned NumElems = Node->getNumOperands();
4227 bool isOnlyLowElement = true;
4228 SDOperand SplatValue = Node->getOperand(0);
4229 std::map<SDOperand, std::vector<unsigned> > Values;
4230 Values[SplatValue].push_back(0);
4231 bool isConstant = true;
4232 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4233 SplatValue.getOpcode() != ISD::UNDEF)
4236 for (unsigned i = 1; i < NumElems; ++i) {
4237 SDOperand V = Node->getOperand(i);
4238 Values[V].push_back(i);
4239 if (V.getOpcode() != ISD::UNDEF)
4240 isOnlyLowElement = false;
4241 if (SplatValue != V)
4242 SplatValue = SDOperand(0,0);
4244 // If this isn't a constant element or an undef, we can't use a constant
4246 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4247 V.getOpcode() != ISD::UNDEF)
4251 if (isOnlyLowElement) {
4252 // If the low element is an undef too, then this whole things is an undef.
4253 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4254 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4255 // Otherwise, turn this into a scalar_to_vector node.
4256 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4257 Node->getOperand(0));
4260 // If all elements are constants, create a load from the constant pool.
4262 MVT::ValueType VT = Node->getValueType(0);
4264 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4265 std::vector<Constant*> CV;
4266 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4267 if (ConstantFPSDNode *V =
4268 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4269 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4270 } else if (ConstantSDNode *V =
4271 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4272 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4274 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4275 CV.push_back(UndefValue::get(OpNTy));
4278 Constant *CP = ConstantVector::get(CV);
4279 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4280 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4283 if (SplatValue.Val) { // Splat of one value?
4284 // Build the shuffle constant vector: <0, 0, 0, 0>
4285 MVT::ValueType MaskVT =
4286 MVT::getIntVectorWithNumElements(NumElems);
4287 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4288 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4289 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4290 &ZeroVec[0], ZeroVec.size());
4292 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4293 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4294 // Get the splatted value into the low element of a vector register.
4295 SDOperand LowValVec =
4296 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4298 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4299 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4300 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4305 // If there are only two unique elements, we may be able to turn this into a
4307 if (Values.size() == 2) {
4308 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4309 MVT::ValueType MaskVT =
4310 MVT::getIntVectorWithNumElements(NumElems);
4311 std::vector<SDOperand> MaskVec(NumElems);
4313 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4314 E = Values.end(); I != E; ++I) {
4315 for (std::vector<unsigned>::iterator II = I->second.begin(),
4316 EE = I->second.end(); II != EE; ++II)
4317 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4320 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4321 &MaskVec[0], MaskVec.size());
4323 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4324 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4325 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4326 SmallVector<SDOperand, 8> Ops;
4327 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4328 E = Values.end(); I != E; ++I) {
4329 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4333 Ops.push_back(ShuffleMask);
4335 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4336 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4337 &Ops[0], Ops.size());
4341 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4342 // aligned object on the stack, store each element into it, then load
4343 // the result as a vector.
4344 MVT::ValueType VT = Node->getValueType(0);
4345 // Create the stack frame object.
4346 SDOperand FIPtr = CreateStackTemporary(VT);
4348 // Emit a store of each element to the stack slot.
4349 SmallVector<SDOperand, 8> Stores;
4350 unsigned TypeByteSize =
4351 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4352 // Store (in the right endianness) the elements to memory.
4353 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4354 // Ignore undef elements.
4355 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4357 unsigned Offset = TypeByteSize*i;
4359 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4360 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4362 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4366 SDOperand StoreChain;
4367 if (!Stores.empty()) // Not all undef elements?
4368 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4369 &Stores[0], Stores.size());
4371 StoreChain = DAG.getEntryNode();
4373 // Result is a load from the stack slot.
4374 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4377 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4378 /// specified value type.
4379 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4380 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4381 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4382 const Type *Ty = MVT::getTypeForValueType(VT);
4383 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4384 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4385 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4388 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4389 SDOperand Op, SDOperand Amt,
4390 SDOperand &Lo, SDOperand &Hi) {
4391 // Expand the subcomponents.
4392 SDOperand LHSL, LHSH;
4393 ExpandOp(Op, LHSL, LHSH);
4395 SDOperand Ops[] = { LHSL, LHSH, Amt };
4396 MVT::ValueType VT = LHSL.getValueType();
4397 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4398 Hi = Lo.getValue(1);
4402 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4403 /// smaller elements. If we can't find a way that is more efficient than a
4404 /// libcall on this target, return false. Otherwise, return true with the
4405 /// low-parts expanded into Lo and Hi.
4406 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4407 SDOperand &Lo, SDOperand &Hi) {
4408 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4409 "This is not a shift!");
4411 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4412 SDOperand ShAmt = LegalizeOp(Amt);
4413 MVT::ValueType ShTy = ShAmt.getValueType();
4414 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4415 unsigned NVTBits = MVT::getSizeInBits(NVT);
4417 // Handle the case when Amt is an immediate. Other cases are currently broken
4418 // and are disabled.
4419 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4420 unsigned Cst = CN->getValue();
4421 // Expand the incoming operand to be shifted, so that we have its parts
4423 ExpandOp(Op, InL, InH);
4427 Lo = DAG.getConstant(0, NVT);
4428 Hi = DAG.getConstant(0, NVT);
4429 } else if (Cst > NVTBits) {
4430 Lo = DAG.getConstant(0, NVT);
4431 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4432 } else if (Cst == NVTBits) {
4433 Lo = DAG.getConstant(0, NVT);
4436 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4437 Hi = DAG.getNode(ISD::OR, NVT,
4438 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4439 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4444 Lo = DAG.getConstant(0, NVT);
4445 Hi = DAG.getConstant(0, NVT);
4446 } else if (Cst > NVTBits) {
4447 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4448 Hi = DAG.getConstant(0, NVT);
4449 } else if (Cst == NVTBits) {
4451 Hi = DAG.getConstant(0, NVT);
4453 Lo = DAG.getNode(ISD::OR, NVT,
4454 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4455 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4456 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4461 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4462 DAG.getConstant(NVTBits-1, ShTy));
4463 } else if (Cst > NVTBits) {
4464 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4465 DAG.getConstant(Cst-NVTBits, ShTy));
4466 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4467 DAG.getConstant(NVTBits-1, ShTy));
4468 } else if (Cst == NVTBits) {
4470 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4471 DAG.getConstant(NVTBits-1, ShTy));
4473 Lo = DAG.getNode(ISD::OR, NVT,
4474 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4475 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4476 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4482 // Okay, the shift amount isn't constant. However, if we can tell that it is
4483 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4484 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4485 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4487 // If we know that the high bit of the shift amount is one, then we can do
4488 // this as a couple of simple shifts.
4489 if (KnownOne & Mask) {
4490 // Mask out the high bit, which we know is set.
4491 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4492 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4494 // Expand the incoming operand to be shifted, so that we have its parts
4496 ExpandOp(Op, InL, InH);
4499 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4500 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4503 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4504 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4507 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4508 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4509 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4514 // If we know that the high bit of the shift amount is zero, then we can do
4515 // this as a couple of simple shifts.
4516 if (KnownZero & Mask) {
4518 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4519 DAG.getConstant(NVTBits, Amt.getValueType()),
4522 // Expand the incoming operand to be shifted, so that we have its parts
4524 ExpandOp(Op, InL, InH);
4527 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4528 Hi = DAG.getNode(ISD::OR, NVT,
4529 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4530 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4533 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4534 Lo = DAG.getNode(ISD::OR, NVT,
4535 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4536 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4539 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4540 Lo = DAG.getNode(ISD::OR, NVT,
4541 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4542 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4551 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4552 // does not fit into a register, return the lo part and set the hi part to the
4553 // by-reg argument. If it does fit into a single register, return the result
4554 // and leave the Hi part unset.
4555 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4556 bool isSigned, SDOperand &Hi) {
4557 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4558 // The input chain to this libcall is the entry node of the function.
4559 // Legalizing the call will automatically add the previous call to the
4561 SDOperand InChain = DAG.getEntryNode();
4563 TargetLowering::ArgListTy Args;
4564 TargetLowering::ArgListEntry Entry;
4565 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4566 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4567 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4568 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4569 Entry.isSExt = isSigned;
4570 Args.push_back(Entry);
4572 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4574 // Splice the libcall in wherever FindInputOutputChains tells us to.
4575 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4576 std::pair<SDOperand,SDOperand> CallInfo =
4577 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4580 // Legalize the call sequence, starting with the chain. This will advance
4581 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4582 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4583 LegalizeOp(CallInfo.second);
4585 switch (getTypeAction(CallInfo.first.getValueType())) {
4586 default: assert(0 && "Unknown thing");
4588 Result = CallInfo.first;
4591 ExpandOp(CallInfo.first, Result, Hi);
4598 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4600 SDOperand SelectionDAGLegalize::
4601 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4602 assert(getTypeAction(Source.getValueType()) == Expand &&
4603 "This is not an expansion!");
4604 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4607 assert(Source.getValueType() == MVT::i64 &&
4608 "This only works for 64-bit -> FP");
4609 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4610 // incoming integer is set. To handle this, we dynamically test to see if
4611 // it is set, and, if so, add a fudge factor.
4613 ExpandOp(Source, Lo, Hi);
4615 // If this is unsigned, and not supported, first perform the conversion to
4616 // signed, then adjust the result if the sign bit is set.
4617 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4618 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4620 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4621 DAG.getConstant(0, Hi.getValueType()),
4623 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4624 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4625 SignSet, Four, Zero);
4626 uint64_t FF = 0x5f800000ULL;
4627 if (TLI.isLittleEndian()) FF <<= 32;
4628 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4630 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4631 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4632 SDOperand FudgeInReg;
4633 if (DestTy == MVT::f32)
4634 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4635 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
4636 // FIXME: Avoid the extend by construction the right constantpool?
4637 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
4638 CPIdx, NULL, 0, MVT::f32);
4640 assert(0 && "Unexpected conversion");
4642 MVT::ValueType SCVT = SignedConv.getValueType();
4643 if (SCVT != DestTy) {
4644 // Destination type needs to be expanded as well. The FADD now we are
4645 // constructing will be expanded into a libcall.
4646 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4647 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4648 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4649 SignedConv, SignedConv.getValue(1));
4651 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4653 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4656 // Check to see if the target has a custom way to lower this. If so, use it.
4657 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4658 default: assert(0 && "This action not implemented for this operation!");
4659 case TargetLowering::Legal:
4660 case TargetLowering::Expand:
4661 break; // This case is handled below.
4662 case TargetLowering::Custom: {
4663 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4666 return LegalizeOp(NV);
4667 break; // The target decided this was legal after all
4671 // Expand the source, then glue it back together for the call. We must expand
4672 // the source in case it is shared (this pass of legalize must traverse it).
4673 SDOperand SrcLo, SrcHi;
4674 ExpandOp(Source, SrcLo, SrcHi);
4675 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4678 if (DestTy == MVT::f32)
4679 LC = RTLIB::SINTTOFP_I64_F32;
4681 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4682 LC = RTLIB::SINTTOFP_I64_F64;
4685 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4686 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4687 SDOperand UnusedHiPart;
4688 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4692 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4693 /// INT_TO_FP operation of the specified operand when the target requests that
4694 /// we expand it. At this point, we know that the result and operand types are
4695 /// legal for the target.
4696 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4698 MVT::ValueType DestVT) {
4699 if (Op0.getValueType() == MVT::i32) {
4700 // simple 32-bit [signed|unsigned] integer to float/double expansion
4702 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4703 MachineFunction &MF = DAG.getMachineFunction();
4704 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4705 unsigned StackAlign =
4706 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4707 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4708 // get address of 8 byte buffer
4709 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4710 // word offset constant for Hi/Lo address computation
4711 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4712 // set up Hi and Lo (into buffer) address based on endian
4713 SDOperand Hi = StackSlot;
4714 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4715 if (TLI.isLittleEndian())
4718 // if signed map to unsigned space
4719 SDOperand Op0Mapped;
4721 // constant used to invert sign bit (signed to unsigned mapping)
4722 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4723 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4727 // store the lo of the constructed double - based on integer input
4728 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4729 Op0Mapped, Lo, NULL, 0);
4730 // initial hi portion of constructed double
4731 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4732 // store the hi of the constructed double - biased exponent
4733 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4734 // load the constructed double
4735 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4736 // FP constant to bias correct the final result
4737 SDOperand Bias = DAG.getConstantFP(isSigned ?
4738 BitsToDouble(0x4330000080000000ULL)
4739 : BitsToDouble(0x4330000000000000ULL),
4741 // subtract the bias
4742 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4745 // handle final rounding
4746 if (DestVT == MVT::f64) {
4749 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
4750 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
4751 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
4752 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
4756 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4757 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4759 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4760 DAG.getConstant(0, Op0.getValueType()),
4762 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4763 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4764 SignSet, Four, Zero);
4766 // If the sign bit of the integer is set, the large number will be treated
4767 // as a negative number. To counteract this, the dynamic code adds an
4768 // offset depending on the data type.
4770 switch (Op0.getValueType()) {
4771 default: assert(0 && "Unsupported integer type!");
4772 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4773 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4774 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4775 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4777 if (TLI.isLittleEndian()) FF <<= 32;
4778 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4780 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4781 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4782 SDOperand FudgeInReg;
4783 if (DestVT == MVT::f32)
4784 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4786 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
4787 DAG.getEntryNode(), CPIdx,
4788 NULL, 0, MVT::f32));
4791 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4794 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4795 /// *INT_TO_FP operation of the specified operand when the target requests that
4796 /// we promote it. At this point, we know that the result and operand types are
4797 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4798 /// operation that takes a larger input.
4799 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4800 MVT::ValueType DestVT,
4802 // First step, figure out the appropriate *INT_TO_FP operation to use.
4803 MVT::ValueType NewInTy = LegalOp.getValueType();
4805 unsigned OpToUse = 0;
4807 // Scan for the appropriate larger type to use.
4809 NewInTy = (MVT::ValueType)(NewInTy+1);
4810 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4812 // If the target supports SINT_TO_FP of this type, use it.
4813 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4815 case TargetLowering::Legal:
4816 if (!TLI.isTypeLegal(NewInTy))
4817 break; // Can't use this datatype.
4819 case TargetLowering::Custom:
4820 OpToUse = ISD::SINT_TO_FP;
4824 if (isSigned) continue;
4826 // If the target supports UINT_TO_FP of this type, use it.
4827 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4829 case TargetLowering::Legal:
4830 if (!TLI.isTypeLegal(NewInTy))
4831 break; // Can't use this datatype.
4833 case TargetLowering::Custom:
4834 OpToUse = ISD::UINT_TO_FP;
4839 // Otherwise, try a larger type.
4842 // Okay, we found the operation and type to use. Zero extend our input to the
4843 // desired type then run the operation on it.
4844 return DAG.getNode(OpToUse, DestVT,
4845 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4849 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4850 /// FP_TO_*INT operation of the specified operand when the target requests that
4851 /// we promote it. At this point, we know that the result and operand types are
4852 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4853 /// operation that returns a larger result.
4854 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4855 MVT::ValueType DestVT,
4857 // First step, figure out the appropriate FP_TO*INT operation to use.
4858 MVT::ValueType NewOutTy = DestVT;
4860 unsigned OpToUse = 0;
4862 // Scan for the appropriate larger type to use.
4864 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4865 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4867 // If the target supports FP_TO_SINT returning this type, use it.
4868 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4870 case TargetLowering::Legal:
4871 if (!TLI.isTypeLegal(NewOutTy))
4872 break; // Can't use this datatype.
4874 case TargetLowering::Custom:
4875 OpToUse = ISD::FP_TO_SINT;
4880 // If the target supports FP_TO_UINT of this type, use it.
4881 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4883 case TargetLowering::Legal:
4884 if (!TLI.isTypeLegal(NewOutTy))
4885 break; // Can't use this datatype.
4887 case TargetLowering::Custom:
4888 OpToUse = ISD::FP_TO_UINT;
4893 // Otherwise, try a larger type.
4896 // Okay, we found the operation and type to use. Truncate the result of the
4897 // extended FP_TO_*INT operation to the desired size.
4898 return DAG.getNode(ISD::TRUNCATE, DestVT,
4899 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4902 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4904 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4905 MVT::ValueType VT = Op.getValueType();
4906 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4907 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4909 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4911 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4912 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4913 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4915 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4916 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4917 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4918 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4919 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4920 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4921 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4922 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4923 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4925 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4926 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4927 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4928 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4929 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4930 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4931 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4932 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4933 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4934 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4935 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4936 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4937 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4938 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4939 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4940 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4941 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4942 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4943 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4944 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4945 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4949 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4951 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4953 default: assert(0 && "Cannot expand this yet!");
4955 static const uint64_t mask[6] = {
4956 0x5555555555555555ULL, 0x3333333333333333ULL,
4957 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4958 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4960 MVT::ValueType VT = Op.getValueType();
4961 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4962 unsigned len = MVT::getSizeInBits(VT);
4963 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4964 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4965 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4966 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4967 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4968 DAG.getNode(ISD::AND, VT,
4969 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4974 // for now, we do this:
4975 // x = x | (x >> 1);
4976 // x = x | (x >> 2);
4978 // x = x | (x >>16);
4979 // x = x | (x >>32); // for 64-bit input
4980 // return popcount(~x);
4982 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4983 MVT::ValueType VT = Op.getValueType();
4984 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4985 unsigned len = MVT::getSizeInBits(VT);
4986 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4987 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4988 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4990 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4991 return DAG.getNode(ISD::CTPOP, VT, Op);
4994 // for now, we use: { return popcount(~x & (x - 1)); }
4995 // unless the target has ctlz but not ctpop, in which case we use:
4996 // { return 32 - nlz(~x & (x-1)); }
4997 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4998 MVT::ValueType VT = Op.getValueType();
4999 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5000 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5001 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5002 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5003 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5004 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5005 TLI.isOperationLegal(ISD::CTLZ, VT))
5006 return DAG.getNode(ISD::SUB, VT,
5007 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5008 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5009 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5014 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5015 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5016 /// LegalizeNodes map is filled in for any results that are not expanded, the
5017 /// ExpandedNodes map is filled in for any results that are expanded, and the
5018 /// Lo/Hi values are returned.
5019 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5020 MVT::ValueType VT = Op.getValueType();
5021 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5022 SDNode *Node = Op.Val;
5023 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5024 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5025 MVT::isVector(VT)) &&
5026 "Cannot expand to FP value or to larger int value!");
5028 // See if we already expanded it.
5029 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5030 = ExpandedNodes.find(Op);
5031 if (I != ExpandedNodes.end()) {
5032 Lo = I->second.first;
5033 Hi = I->second.second;
5037 switch (Node->getOpcode()) {
5038 case ISD::CopyFromReg:
5039 assert(0 && "CopyFromReg must be legal!");
5042 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5044 assert(0 && "Do not know how to expand this operator!");
5047 NVT = TLI.getTypeToExpandTo(VT);
5048 Lo = DAG.getNode(ISD::UNDEF, NVT);
5049 Hi = DAG.getNode(ISD::UNDEF, NVT);
5051 case ISD::Constant: {
5052 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
5053 Lo = DAG.getConstant(Cst, NVT);
5054 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5057 case ISD::ConstantFP: {
5058 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5059 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5060 if (getTypeAction(Lo.getValueType()) == Expand)
5061 ExpandOp(Lo, Lo, Hi);
5064 case ISD::BUILD_PAIR:
5065 // Return the operands.
5066 Lo = Node->getOperand(0);
5067 Hi = Node->getOperand(1);
5070 case ISD::SIGN_EXTEND_INREG:
5071 ExpandOp(Node->getOperand(0), Lo, Hi);
5072 // sext_inreg the low part if needed.
5073 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5075 // The high part gets the sign extension from the lo-part. This handles
5076 // things like sextinreg V:i64 from i8.
5077 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5078 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5079 TLI.getShiftAmountTy()));
5083 ExpandOp(Node->getOperand(0), Lo, Hi);
5084 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5085 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5091 ExpandOp(Node->getOperand(0), Lo, Hi);
5092 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5093 DAG.getNode(ISD::CTPOP, NVT, Lo),
5094 DAG.getNode(ISD::CTPOP, NVT, Hi));
5095 Hi = DAG.getConstant(0, NVT);
5099 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5100 ExpandOp(Node->getOperand(0), Lo, Hi);
5101 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5102 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5103 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5105 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5106 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5108 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5109 Hi = DAG.getConstant(0, NVT);
5114 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5115 ExpandOp(Node->getOperand(0), Lo, Hi);
5116 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5117 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5118 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5120 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5121 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5123 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5124 Hi = DAG.getConstant(0, NVT);
5129 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5130 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5131 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5132 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5134 // Remember that we legalized the chain.
5135 Hi = LegalizeOp(Hi);
5136 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5137 if (!TLI.isLittleEndian())
5143 LoadSDNode *LD = cast<LoadSDNode>(Node);
5144 SDOperand Ch = LD->getChain(); // Legalize the chain.
5145 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5146 ISD::LoadExtType ExtType = LD->getExtensionType();
5147 int SVOffset = LD->getSrcValueOffset();
5148 unsigned Alignment = LD->getAlignment();
5149 bool isVolatile = LD->isVolatile();
5151 if (ExtType == ISD::NON_EXTLOAD) {
5152 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5153 isVolatile, Alignment);
5154 if (VT == MVT::f32 || VT == MVT::f64) {
5155 // f32->i32 or f64->i64 one to one expansion.
5156 // Remember that we legalized the chain.
5157 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5158 // Recursively expand the new load.
5159 if (getTypeAction(NVT) == Expand)
5160 ExpandOp(Lo, Lo, Hi);
5164 // Increment the pointer to the other half.
5165 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5166 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5167 getIntPtrConstant(IncrementSize));
5168 SVOffset += IncrementSize;
5169 if (Alignment > IncrementSize)
5170 Alignment = IncrementSize;
5171 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5172 isVolatile, Alignment);
5174 // Build a factor node to remember that this load is independent of the
5176 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5179 // Remember that we legalized the chain.
5180 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5181 if (!TLI.isLittleEndian())
5184 MVT::ValueType EVT = LD->getLoadedVT();
5186 if (VT == MVT::f64 && EVT == MVT::f32) {
5187 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5188 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5189 SVOffset, isVolatile, Alignment);
5190 // Remember that we legalized the chain.
5191 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5192 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5197 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5198 SVOffset, isVolatile, Alignment);
5200 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5201 SVOffset, EVT, isVolatile,
5204 // Remember that we legalized the chain.
5205 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5207 if (ExtType == ISD::SEXTLOAD) {
5208 // The high part is obtained by SRA'ing all but one of the bits of the
5210 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5211 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5212 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5213 } else if (ExtType == ISD::ZEXTLOAD) {
5214 // The high part is just a zero.
5215 Hi = DAG.getConstant(0, NVT);
5216 } else /* if (ExtType == ISD::EXTLOAD) */ {
5217 // The high part is undefined.
5218 Hi = DAG.getNode(ISD::UNDEF, NVT);
5225 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5226 SDOperand LL, LH, RL, RH;
5227 ExpandOp(Node->getOperand(0), LL, LH);
5228 ExpandOp(Node->getOperand(1), RL, RH);
5229 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5230 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5234 SDOperand LL, LH, RL, RH;
5235 ExpandOp(Node->getOperand(1), LL, LH);
5236 ExpandOp(Node->getOperand(2), RL, RH);
5237 if (getTypeAction(NVT) == Expand)
5238 NVT = TLI.getTypeToExpandTo(NVT);
5239 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5241 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5244 case ISD::SELECT_CC: {
5245 SDOperand TL, TH, FL, FH;
5246 ExpandOp(Node->getOperand(2), TL, TH);
5247 ExpandOp(Node->getOperand(3), FL, FH);
5248 if (getTypeAction(NVT) == Expand)
5249 NVT = TLI.getTypeToExpandTo(NVT);
5250 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5251 Node->getOperand(1), TL, FL, Node->getOperand(4));
5253 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5254 Node->getOperand(1), TH, FH, Node->getOperand(4));
5257 case ISD::ANY_EXTEND:
5258 // The low part is any extension of the input (which degenerates to a copy).
5259 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5260 // The high part is undefined.
5261 Hi = DAG.getNode(ISD::UNDEF, NVT);
5263 case ISD::SIGN_EXTEND: {
5264 // The low part is just a sign extension of the input (which degenerates to
5266 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5268 // The high part is obtained by SRA'ing all but one of the bits of the lo
5270 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5271 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5272 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5275 case ISD::ZERO_EXTEND:
5276 // The low part is just a zero extension of the input (which degenerates to
5278 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5280 // The high part is just a zero.
5281 Hi = DAG.getConstant(0, NVT);
5284 case ISD::TRUNCATE: {
5285 // The input value must be larger than this value. Expand *it*.
5287 ExpandOp(Node->getOperand(0), NewLo, Hi);
5289 // The low part is now either the right size, or it is closer. If not the
5290 // right size, make an illegal truncate so we recursively expand it.
5291 if (NewLo.getValueType() != Node->getValueType(0))
5292 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5293 ExpandOp(NewLo, Lo, Hi);
5297 case ISD::BIT_CONVERT: {
5299 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5300 // If the target wants to, allow it to lower this itself.
5301 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5302 case Expand: assert(0 && "cannot expand FP!");
5303 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5304 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5306 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5309 // f32 / f64 must be expanded to i32 / i64.
5310 if (VT == MVT::f32 || VT == MVT::f64) {
5311 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5312 if (getTypeAction(NVT) == Expand)
5313 ExpandOp(Lo, Lo, Hi);
5317 // If source operand will be expanded to the same type as VT, i.e.
5318 // i64 <- f64, i32 <- f32, expand the source operand instead.
5319 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5320 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5321 ExpandOp(Node->getOperand(0), Lo, Hi);
5325 // Turn this into a load/store pair by default.
5327 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5329 ExpandOp(Tmp, Lo, Hi);
5333 case ISD::READCYCLECOUNTER:
5334 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5335 TargetLowering::Custom &&
5336 "Must custom expand ReadCycleCounter");
5337 Lo = TLI.LowerOperation(Op, DAG);
5338 assert(Lo.Val && "Node must be custom expanded!");
5339 Hi = Lo.getValue(1);
5340 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5341 LegalizeOp(Lo.getValue(2)));
5344 // These operators cannot be expanded directly, emit them as calls to
5345 // library functions.
5346 case ISD::FP_TO_SINT: {
5347 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5349 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5350 case Expand: assert(0 && "cannot expand FP!");
5351 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5352 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5355 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5357 // Now that the custom expander is done, expand the result, which is still
5360 ExpandOp(Op, Lo, Hi);
5366 if (Node->getOperand(0).getValueType() == MVT::f32)
5367 LC = RTLIB::FPTOSINT_F32_I64;
5368 else if (Node->getOperand(0).getValueType() == MVT::f64)
5369 LC = RTLIB::FPTOSINT_F64_I64;
5371 LC = RTLIB::FPTOSINT_LD_I64;
5372 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5373 false/*sign irrelevant*/, Hi);
5377 case ISD::FP_TO_UINT: {
5378 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5380 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5381 case Expand: assert(0 && "cannot expand FP!");
5382 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5383 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5386 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5388 // Now that the custom expander is done, expand the result.
5390 ExpandOp(Op, Lo, Hi);
5396 if (Node->getOperand(0).getValueType() == MVT::f32)
5397 LC = RTLIB::FPTOUINT_F32_I64;
5399 LC = RTLIB::FPTOUINT_F64_I64;
5400 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5401 false/*sign irrelevant*/, Hi);
5406 // If the target wants custom lowering, do so.
5407 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5408 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5409 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5410 Op = TLI.LowerOperation(Op, DAG);
5412 // Now that the custom expander is done, expand the result, which is
5414 ExpandOp(Op, Lo, Hi);
5419 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5420 // this X << 1 as X+X.
5421 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5422 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5423 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5424 SDOperand LoOps[2], HiOps[3];
5425 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5426 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5427 LoOps[1] = LoOps[0];
5428 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5430 HiOps[1] = HiOps[0];
5431 HiOps[2] = Lo.getValue(1);
5432 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5437 // If we can emit an efficient shift operation, do so now.
5438 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5441 // If this target supports SHL_PARTS, use it.
5442 TargetLowering::LegalizeAction Action =
5443 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5444 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5445 Action == TargetLowering::Custom) {
5446 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5450 // Otherwise, emit a libcall.
5451 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5452 false/*left shift=unsigned*/, Hi);
5457 // If the target wants custom lowering, do so.
5458 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5459 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5460 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5461 Op = TLI.LowerOperation(Op, DAG);
5463 // Now that the custom expander is done, expand the result, which is
5465 ExpandOp(Op, Lo, Hi);
5470 // If we can emit an efficient shift operation, do so now.
5471 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5474 // If this target supports SRA_PARTS, use it.
5475 TargetLowering::LegalizeAction Action =
5476 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5477 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5478 Action == TargetLowering::Custom) {
5479 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5483 // Otherwise, emit a libcall.
5484 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5485 true/*ashr is signed*/, Hi);
5490 // If the target wants custom lowering, do so.
5491 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5492 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5493 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5494 Op = TLI.LowerOperation(Op, DAG);
5496 // Now that the custom expander is done, expand the result, which is
5498 ExpandOp(Op, Lo, Hi);
5503 // If we can emit an efficient shift operation, do so now.
5504 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5507 // If this target supports SRL_PARTS, use it.
5508 TargetLowering::LegalizeAction Action =
5509 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5510 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5511 Action == TargetLowering::Custom) {
5512 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5516 // Otherwise, emit a libcall.
5517 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5518 false/*lshr is unsigned*/, Hi);
5524 // If the target wants to custom expand this, let them.
5525 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5526 TargetLowering::Custom) {
5527 Op = TLI.LowerOperation(Op, DAG);
5529 ExpandOp(Op, Lo, Hi);
5534 // Expand the subcomponents.
5535 SDOperand LHSL, LHSH, RHSL, RHSH;
5536 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5537 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5538 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5539 SDOperand LoOps[2], HiOps[3];
5544 if (Node->getOpcode() == ISD::ADD) {
5545 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5546 HiOps[2] = Lo.getValue(1);
5547 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5549 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5550 HiOps[2] = Lo.getValue(1);
5551 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5558 // Expand the subcomponents.
5559 SDOperand LHSL, LHSH, RHSL, RHSH;
5560 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5561 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5562 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5563 SDOperand LoOps[2] = { LHSL, RHSL };
5564 SDOperand HiOps[3] = { LHSH, RHSH };
5566 if (Node->getOpcode() == ISD::ADDC) {
5567 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5568 HiOps[2] = Lo.getValue(1);
5569 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5571 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5572 HiOps[2] = Lo.getValue(1);
5573 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5575 // Remember that we legalized the flag.
5576 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5581 // Expand the subcomponents.
5582 SDOperand LHSL, LHSH, RHSL, RHSH;
5583 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5584 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5585 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5586 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5587 SDOperand HiOps[3] = { LHSH, RHSH };
5589 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5590 HiOps[2] = Lo.getValue(1);
5591 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5593 // Remember that we legalized the flag.
5594 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5598 // If the target wants to custom expand this, let them.
5599 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5600 SDOperand New = TLI.LowerOperation(Op, DAG);
5602 ExpandOp(New, Lo, Hi);
5607 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5608 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5609 if (HasMULHS || HasMULHU) {
5610 SDOperand LL, LH, RL, RH;
5611 ExpandOp(Node->getOperand(0), LL, LH);
5612 ExpandOp(Node->getOperand(1), RL, RH);
5613 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5614 // FIXME: Move this to the dag combiner.
5615 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5616 // extended the sign bit of the low half through the upper half, and if so
5617 // emit a MULHS instead of the alternate sequence that is valid for any
5618 // i64 x i64 multiply.
5620 // is RH an extension of the sign bit of RL?
5621 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5622 RH.getOperand(1).getOpcode() == ISD::Constant &&
5623 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5624 // is LH an extension of the sign bit of LL?
5625 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5626 LH.getOperand(1).getOpcode() == ISD::Constant &&
5627 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5629 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5631 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5633 } else if (HasMULHU) {
5635 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5638 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5639 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5640 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5641 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5642 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5647 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5648 false/*sign irrelevant*/, Hi);
5652 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5655 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5658 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5661 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5665 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5666 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5670 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5671 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5675 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5676 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5680 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5681 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5684 case ISD::FP_EXTEND:
5685 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5688 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5691 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5692 ? RTLIB::POWI_F32 : RTLIB::POWI_F64),
5698 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5699 switch(Node->getOpcode()) {
5701 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5704 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5707 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5709 default: assert(0 && "Unreachable!");
5711 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5715 SDOperand Mask = (VT == MVT::f64)
5716 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5717 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5718 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5719 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5720 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5721 if (getTypeAction(NVT) == Expand)
5722 ExpandOp(Lo, Lo, Hi);
5726 SDOperand Mask = (VT == MVT::f64)
5727 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5728 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5729 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5730 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5731 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5732 if (getTypeAction(NVT) == Expand)
5733 ExpandOp(Lo, Lo, Hi);
5736 case ISD::FCOPYSIGN: {
5737 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5738 if (getTypeAction(NVT) == Expand)
5739 ExpandOp(Lo, Lo, Hi);
5742 case ISD::SINT_TO_FP:
5743 case ISD::UINT_TO_FP: {
5744 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5745 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5746 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5747 if (Node->getOperand(0).getValueType() == MVT::i64) {
5749 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5750 else if (VT == MVT::f64)
5751 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5752 else if (VT == MVT::f80 || VT == MVT::f128 || VT == MVT::ppcf128) {
5754 LC = RTLIB::SINTTOFP_I64_LD;
5758 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5760 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5763 // Promote the operand if needed.
5764 if (getTypeAction(SrcVT) == Promote) {
5765 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5767 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5768 DAG.getValueType(SrcVT))
5769 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5770 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5773 const char *LibCall = TLI.getLibcallName(LC);
5775 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5777 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5778 Node->getOperand(0));
5779 if (getTypeAction(Lo.getValueType()) == Expand)
5780 ExpandOp(Lo, Lo, Hi);
5786 // Make sure the resultant values have been legalized themselves, unless this
5787 // is a type that requires multi-step expansion.
5788 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5789 Lo = LegalizeOp(Lo);
5791 // Don't legalize the high part if it is expanded to a single node.
5792 Hi = LegalizeOp(Hi);
5795 // Remember in a map if the values will be reused later.
5796 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5797 assert(isNew && "Value already expanded?!?");
5800 /// SplitVectorOp - Given an operand of vector type, break it down into
5801 /// two smaller values, still of vector type.
5802 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5804 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5805 SDNode *Node = Op.Val;
5806 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
5807 assert(NumElements > 1 && "Cannot split a single element vector!");
5808 unsigned NewNumElts = NumElements/2;
5809 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
5810 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5812 // See if we already split it.
5813 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5814 = SplitNodes.find(Op);
5815 if (I != SplitNodes.end()) {
5816 Lo = I->second.first;
5817 Hi = I->second.second;
5821 switch (Node->getOpcode()) {
5826 assert(0 && "Unhandled operation in SplitVectorOp!");
5827 case ISD::BUILD_PAIR:
5828 Lo = Node->getOperand(0);
5829 Hi = Node->getOperand(1);
5831 case ISD::BUILD_VECTOR: {
5832 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5833 Node->op_begin()+NewNumElts);
5834 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5836 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5838 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5841 case ISD::CONCAT_VECTORS: {
5842 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5843 if (NewNumSubvectors == 1) {
5844 Lo = Node->getOperand(0);
5845 Hi = Node->getOperand(1);
5847 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5848 Node->op_begin()+NewNumSubvectors);
5849 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5851 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5853 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5869 SDOperand LL, LH, RL, RH;
5870 SplitVectorOp(Node->getOperand(0), LL, LH);
5871 SplitVectorOp(Node->getOperand(1), RL, RH);
5873 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5874 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5878 LoadSDNode *LD = cast<LoadSDNode>(Node);
5879 SDOperand Ch = LD->getChain();
5880 SDOperand Ptr = LD->getBasePtr();
5881 const Value *SV = LD->getSrcValue();
5882 int SVOffset = LD->getSrcValueOffset();
5883 unsigned Alignment = LD->getAlignment();
5884 bool isVolatile = LD->isVolatile();
5886 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5887 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5888 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5889 getIntPtrConstant(IncrementSize));
5890 SVOffset += IncrementSize;
5891 if (Alignment > IncrementSize)
5892 Alignment = IncrementSize;
5893 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5895 // Build a factor node to remember that this load is independent of the
5897 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5900 // Remember that we legalized the chain.
5901 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5904 case ISD::BIT_CONVERT: {
5905 // We know the result is a vector. The input may be either a vector or a
5907 SDOperand InOp = Node->getOperand(0);
5908 if (!MVT::isVector(InOp.getValueType()) ||
5909 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5910 // The input is a scalar or single-element vector.
5911 // Lower to a store/load so that it can be split.
5912 // FIXME: this could be improved probably.
5913 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5915 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5916 InOp, Ptr, NULL, 0);
5917 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5919 // Split the vector and convert each of the pieces now.
5920 SplitVectorOp(InOp, Lo, Hi);
5921 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5922 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5927 // Remember in a map if the values will be reused later.
5929 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5930 assert(isNew && "Value already split?!?");
5934 /// ScalarizeVectorOp - Given an operand of single-element vector type
5935 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5936 /// scalar (e.g. f32) value.
5937 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5938 assert(MVT::isVector(Op.getValueType()) &&
5939 "Bad ScalarizeVectorOp invocation!");
5940 SDNode *Node = Op.Val;
5941 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5942 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5944 // See if we already scalarized it.
5945 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5946 if (I != ScalarizedNodes.end()) return I->second;
5949 switch (Node->getOpcode()) {
5952 Node->dump(&DAG); cerr << "\n";
5954 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5970 Result = DAG.getNode(Node->getOpcode(),
5972 ScalarizeVectorOp(Node->getOperand(0)),
5973 ScalarizeVectorOp(Node->getOperand(1)));
5980 Result = DAG.getNode(Node->getOpcode(),
5982 ScalarizeVectorOp(Node->getOperand(0)));
5985 LoadSDNode *LD = cast<LoadSDNode>(Node);
5986 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5987 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5989 const Value *SV = LD->getSrcValue();
5990 int SVOffset = LD->getSrcValueOffset();
5991 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5992 LD->isVolatile(), LD->getAlignment());
5994 // Remember that we legalized the chain.
5995 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5998 case ISD::BUILD_VECTOR:
5999 Result = Node->getOperand(0);
6001 case ISD::INSERT_VECTOR_ELT:
6002 // Returning the inserted scalar element.
6003 Result = Node->getOperand(1);
6005 case ISD::CONCAT_VECTORS:
6006 assert(Node->getOperand(0).getValueType() == NewVT &&
6007 "Concat of non-legal vectors not yet supported!");
6008 Result = Node->getOperand(0);
6010 case ISD::VECTOR_SHUFFLE: {
6011 // Figure out if the scalar is the LHS or RHS and return it.
6012 SDOperand EltNum = Node->getOperand(2).getOperand(0);
6013 if (cast<ConstantSDNode>(EltNum)->getValue())
6014 Result = ScalarizeVectorOp(Node->getOperand(1));
6016 Result = ScalarizeVectorOp(Node->getOperand(0));
6019 case ISD::EXTRACT_SUBVECTOR:
6020 Result = Node->getOperand(0);
6021 assert(Result.getValueType() == NewVT);
6023 case ISD::BIT_CONVERT:
6024 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
6027 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
6028 ScalarizeVectorOp(Op.getOperand(1)),
6029 ScalarizeVectorOp(Op.getOperand(2)));
6033 if (TLI.isTypeLegal(NewVT))
6034 Result = LegalizeOp(Result);
6035 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
6036 assert(isNew && "Value already scalarized?");
6041 // SelectionDAG::Legalize - This is the entry point for the file.
6043 void SelectionDAG::Legalize() {
6044 if (ViewLegalizeDAGs) viewGraph();
6046 /// run - This is the main entry point to this class.
6048 SelectionDAGLegalize(*this).LegalizeDAG();