1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 // Libcall insertion helpers.
46 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
47 /// legalized. We use this to ensure that calls are properly serialized
48 /// against each other, including inserted libcalls.
49 SDOperand LastCALLSEQ_END;
51 /// IsLegalizingCall - This member is used *only* for purposes of providing
52 /// helpful assertions that a libcall isn't created while another call is
53 /// being legalized (which could lead to non-serialized call sequences).
54 bool IsLegalizingCall;
57 Legal, // The target natively supports this operation.
58 Promote, // This operation should be executed in a larger type.
59 Expand, // Try to expand this to other ops, otherwise use a libcall.
62 /// ValueTypeActions - This is a bitvector that contains two bits for each
63 /// value type, where the two bits correspond to the LegalizeAction enum.
64 /// This can be queried with "getTypeAction(VT)".
65 TargetLowering::ValueTypeActionImpl ValueTypeActions;
67 /// LegalizedNodes - For nodes that are of legal width, and that have more
68 /// than one use, this map indicates what regularized operand to use. This
69 /// allows us to avoid legalizing the same thing more than once.
70 std::map<SDOperand, SDOperand> LegalizedNodes;
72 /// PromotedNodes - For nodes that are below legal width, and that have more
73 /// than one use, this map indicates what promoted value to use. This allows
74 /// us to avoid promoting the same thing more than once.
75 std::map<SDOperand, SDOperand> PromotedNodes;
77 /// ExpandedNodes - For nodes that need to be expanded this map indicates
78 /// which which operands are the expanded version of the input. This allows
79 /// us to avoid expanding the same node more than once.
80 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
82 /// SplitNodes - For vector nodes that need to be split, this map indicates
83 /// which which operands are the split version of the input. This allows us
84 /// to avoid splitting the same node more than once.
85 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
87 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
88 /// concrete packed types, this contains the mapping of ones we have already
89 /// processed to the result.
90 std::map<SDOperand, SDOperand> PackedNodes;
92 void AddLegalizedOperand(SDOperand From, SDOperand To) {
93 LegalizedNodes.insert(std::make_pair(From, To));
94 // If someone requests legalization of the new node, return itself.
96 LegalizedNodes.insert(std::make_pair(To, To));
98 void AddPromotedOperand(SDOperand From, SDOperand To) {
99 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
100 assert(isNew && "Got into the map somehow?");
101 // If someone requests legalization of the new node, return itself.
102 LegalizedNodes.insert(std::make_pair(To, To));
107 SelectionDAGLegalize(SelectionDAG &DAG);
109 /// getTypeAction - Return how we should legalize values of this type, either
110 /// it is already legal or we need to expand it into multiple registers of
111 /// smaller integer type, or we need to promote it to a larger type.
112 LegalizeAction getTypeAction(MVT::ValueType VT) const {
113 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
116 /// isTypeLegal - Return true if this type is legal on this target.
118 bool isTypeLegal(MVT::ValueType VT) const {
119 return getTypeAction(VT) == Legal;
125 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
126 /// appropriate for its type.
127 void HandleOp(SDOperand Op);
129 /// LegalizeOp - We know that the specified value has a legal type.
130 /// Recursively ensure that the operands have legal types, then return the
132 SDOperand LegalizeOp(SDOperand O);
134 /// PromoteOp - Given an operation that produces a value in an invalid type,
135 /// promote it to compute the value into a larger type. The produced value
136 /// will have the correct bits for the low portion of the register, but no
137 /// guarantee is made about the top bits: it may be zero, sign-extended, or
139 SDOperand PromoteOp(SDOperand O);
141 /// ExpandOp - Expand the specified SDOperand into its two component pieces
142 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
143 /// the LegalizeNodes map is filled in for any results that are not expanded,
144 /// the ExpandedNodes map is filled in for any results that are expanded, and
145 /// the Lo/Hi values are returned. This applies to integer types and Vector
147 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
149 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
150 /// two smaller values of MVT::Vector type.
151 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
153 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
154 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
155 /// this is called, we know that PackedVT is the right type for the result and
156 /// we know that this type is legal for the target.
157 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
159 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
161 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
163 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
165 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
168 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
169 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
171 MVT::ValueType DestVT);
172 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
174 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
177 SDOperand ExpandBSWAP(SDOperand Op);
178 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
179 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
180 SDOperand &Lo, SDOperand &Hi);
181 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
182 SDOperand &Lo, SDOperand &Hi);
184 SDOperand getIntPtrConstant(uint64_t Val) {
185 return DAG.getConstant(Val, TLI.getPointerTy());
190 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
191 /// specified vector opcode.
192 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
194 default: assert(0 && "Don't know how to scalarize this opcode!");
195 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
196 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
197 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
198 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
199 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
200 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
201 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
202 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
206 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
207 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
208 ValueTypeActions(TLI.getValueTypeActions()) {
209 assert(MVT::LAST_VALUETYPE <= 32 &&
210 "Too many value types for ValueTypeActions to hold!");
213 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
214 /// not been visited yet and if all of its operands have already been visited.
215 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
216 std::map<SDNode*, unsigned> &Visited) {
217 if (++Visited[N] != N->getNumOperands())
218 return; // Haven't visited all operands yet
222 if (N->hasOneUse()) { // Tail recurse in common case.
223 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
227 // Now that we have N in, add anything that uses it if all of their operands
229 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
230 ComputeTopDownOrdering(*UI, Order, Visited);
234 void SelectionDAGLegalize::LegalizeDAG() {
235 LastCALLSEQ_END = DAG.getEntryNode();
236 IsLegalizingCall = false;
238 // The legalize process is inherently a bottom-up recursive process (users
239 // legalize their uses before themselves). Given infinite stack space, we
240 // could just start legalizing on the root and traverse the whole graph. In
241 // practice however, this causes us to run out of stack space on large basic
242 // blocks. To avoid this problem, compute an ordering of the nodes where each
243 // node is only legalized after all of its operands are legalized.
244 std::map<SDNode*, unsigned> Visited;
245 std::vector<SDNode*> Order;
247 // Compute ordering from all of the leaves in the graphs, those (like the
248 // entry node) that have no operands.
249 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
250 E = DAG.allnodes_end(); I != E; ++I) {
251 if (I->getNumOperands() == 0) {
253 ComputeTopDownOrdering(I, Order, Visited);
257 assert(Order.size() == Visited.size() &&
259 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
260 "Error: DAG is cyclic!");
263 for (unsigned i = 0, e = Order.size(); i != e; ++i)
264 HandleOp(SDOperand(Order[i], 0));
266 // Finally, it's possible the root changed. Get the new root.
267 SDOperand OldRoot = DAG.getRoot();
268 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
269 DAG.setRoot(LegalizedNodes[OldRoot]);
271 ExpandedNodes.clear();
272 LegalizedNodes.clear();
273 PromotedNodes.clear();
277 // Remove dead nodes now.
278 DAG.RemoveDeadNodes(OldRoot.Val);
282 /// FindCallEndFromCallStart - Given a chained node that is part of a call
283 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
284 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
285 if (Node->getOpcode() == ISD::CALLSEQ_END)
287 if (Node->use_empty())
288 return 0; // No CallSeqEnd
290 // The chain is usually at the end.
291 SDOperand TheChain(Node, Node->getNumValues()-1);
292 if (TheChain.getValueType() != MVT::Other) {
293 // Sometimes it's at the beginning.
294 TheChain = SDOperand(Node, 0);
295 if (TheChain.getValueType() != MVT::Other) {
296 // Otherwise, hunt for it.
297 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
298 if (Node->getValueType(i) == MVT::Other) {
299 TheChain = SDOperand(Node, i);
303 // Otherwise, we walked into a node without a chain.
304 if (TheChain.getValueType() != MVT::Other)
309 for (SDNode::use_iterator UI = Node->use_begin(),
310 E = Node->use_end(); UI != E; ++UI) {
312 // Make sure to only follow users of our token chain.
314 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
315 if (User->getOperand(i) == TheChain)
316 if (SDNode *Result = FindCallEndFromCallStart(User))
322 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
323 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
324 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
325 assert(Node && "Didn't find callseq_start for a call??");
326 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
328 assert(Node->getOperand(0).getValueType() == MVT::Other &&
329 "Node doesn't have a token chain argument!");
330 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
333 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
334 /// see if any uses can reach Dest. If no dest operands can get to dest,
335 /// legalize them, legalize ourself, and return false, otherwise, return true.
336 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
338 if (N == Dest) return true; // N certainly leads to Dest :)
340 // If the first result of this node has been already legalized, then it cannot
342 switch (getTypeAction(N->getValueType(0))) {
344 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
347 if (PromotedNodes.count(SDOperand(N, 0))) return false;
350 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
354 // Okay, this node has not already been legalized. Check and legalize all
355 // operands. If none lead to Dest, then we can legalize this node.
356 bool OperandsLeadToDest = false;
357 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
358 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
359 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
361 if (OperandsLeadToDest) return true;
363 // Okay, this node looks safe, legalize it and return false.
364 switch (getTypeAction(N->getValueType(0))) {
366 LegalizeOp(SDOperand(N, 0));
369 PromoteOp(SDOperand(N, 0));
373 ExpandOp(SDOperand(N, 0), X, Y);
380 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
381 /// appropriate for its type.
382 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
383 switch (getTypeAction(Op.getValueType())) {
384 default: assert(0 && "Bad type action!");
385 case Legal: LegalizeOp(Op); break;
386 case Promote: PromoteOp(Op); break;
388 if (Op.getValueType() != MVT::Vector) {
393 unsigned NumOps = N->getNumOperands();
394 unsigned NumElements =
395 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
396 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
397 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
398 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
399 // In the common case, this is a legal vector type, convert it to the
400 // packed operation and type now.
401 PackVectorOp(Op, PackedVT);
402 } else if (NumElements == 1) {
403 // Otherwise, if this is a single element vector, convert it to a
405 PackVectorOp(Op, EVT);
407 // Otherwise, this is a multiple element vector that isn't supported.
408 // Split it in half and legalize both parts.
410 SplitVectorOp(Op, X, Y);
418 /// LegalizeOp - We know that the specified value has a legal type.
419 /// Recursively ensure that the operands have legal types, then return the
421 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
422 assert(isTypeLegal(Op.getValueType()) &&
423 "Caller should expand or promote operands that are not legal!");
424 SDNode *Node = Op.Val;
426 // If this operation defines any values that cannot be represented in a
427 // register on this target, make sure to expand or promote them.
428 if (Node->getNumValues() > 1) {
429 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
430 if (getTypeAction(Node->getValueType(i)) != Legal) {
431 HandleOp(Op.getValue(i));
432 assert(LegalizedNodes.count(Op) &&
433 "Handling didn't add legal operands!");
434 return LegalizedNodes[Op];
438 // Note that LegalizeOp may be reentered even from single-use nodes, which
439 // means that we always must cache transformed nodes.
440 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
441 if (I != LegalizedNodes.end()) return I->second;
443 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
444 SDOperand Result = Op;
445 bool isCustom = false;
447 switch (Node->getOpcode()) {
448 case ISD::FrameIndex:
449 case ISD::EntryToken:
451 case ISD::BasicBlock:
452 case ISD::TargetFrameIndex:
453 case ISD::TargetConstant:
454 case ISD::TargetConstantFP:
455 case ISD::TargetConstantPool:
456 case ISD::TargetGlobalAddress:
457 case ISD::TargetExternalSymbol:
462 // Primitives must all be legal.
463 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
464 "This must be legal!");
467 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
468 // If this is a target node, legalize it by legalizing the operands then
469 // passing it through.
470 std::vector<SDOperand> Ops;
471 bool Changed = false;
472 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
473 Ops.push_back(LegalizeOp(Node->getOperand(i)));
474 Changed = Changed || Node->getOperand(i) != Ops.back();
477 if (Node->getNumValues() == 1)
478 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
480 std::vector<MVT::ValueType> VTs(Node->value_begin(),
482 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
485 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
486 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
487 return Result.getValue(Op.ResNo);
489 // Otherwise this is an unhandled builtin node. splat.
490 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
491 assert(0 && "Do not know how to legalize this operator!");
493 case ISD::GlobalAddress:
494 case ISD::ExternalSymbol:
495 case ISD::ConstantPool: // Nothing to do.
496 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
497 default: assert(0 && "This action is not supported yet!");
498 case TargetLowering::Custom:
499 Tmp1 = TLI.LowerOperation(Op, DAG);
500 if (Tmp1.Val) Result = Tmp1;
501 // FALLTHROUGH if the target doesn't want to lower this op after all.
502 case TargetLowering::Legal:
506 case ISD::AssertSext:
507 case ISD::AssertZext:
508 Tmp1 = LegalizeOp(Node->getOperand(0));
509 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
511 case ISD::MERGE_VALUES:
512 // Legalize eliminates MERGE_VALUES nodes.
513 Result = Node->getOperand(Op.ResNo);
515 case ISD::CopyFromReg:
516 Tmp1 = LegalizeOp(Node->getOperand(0));
517 Result = Op.getValue(0);
518 if (Node->getNumValues() == 2) {
519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
521 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
522 if (Node->getNumOperands() == 3) {
523 Tmp2 = LegalizeOp(Node->getOperand(2));
524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
526 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
528 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
530 // Since CopyFromReg produces two values, make sure to remember that we
531 // legalized both of them.
532 AddLegalizedOperand(Op.getValue(0), Result);
533 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
534 return Result.getValue(Op.ResNo);
536 MVT::ValueType VT = Op.getValueType();
537 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
538 default: assert(0 && "This action is not supported yet!");
539 case TargetLowering::Expand:
540 if (MVT::isInteger(VT))
541 Result = DAG.getConstant(0, VT);
542 else if (MVT::isFloatingPoint(VT))
543 Result = DAG.getConstantFP(0, VT);
545 assert(0 && "Unknown value type!");
547 case TargetLowering::Legal:
554 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
555 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
557 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
558 case TargetLowering::Promote:
559 default: assert(0 && "This action is not supported yet!");
560 case TargetLowering::Expand: {
561 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
562 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
563 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
565 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
566 const std::string &FName =
567 cast<StringSDNode>(Node->getOperand(3))->getValue();
568 const std::string &DirName =
569 cast<StringSDNode>(Node->getOperand(4))->getValue();
570 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
572 std::vector<SDOperand> Ops;
573 Ops.push_back(Tmp1); // chain
574 SDOperand LineOp = Node->getOperand(1);
575 SDOperand ColOp = Node->getOperand(2);
578 Ops.push_back(LineOp); // line #
579 Ops.push_back(ColOp); // col #
580 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
581 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
583 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
584 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
585 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
586 Ops.push_back(DAG.getConstant(ID, MVT::i32));
587 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
590 Result = Tmp1; // chain
594 case TargetLowering::Legal:
595 if (Tmp1 != Node->getOperand(0) ||
596 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
597 std::vector<SDOperand> Ops;
599 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
600 Ops.push_back(Node->getOperand(1)); // line # must be legal.
601 Ops.push_back(Node->getOperand(2)); // col # must be legal.
603 // Otherwise promote them.
604 Ops.push_back(PromoteOp(Node->getOperand(1)));
605 Ops.push_back(PromoteOp(Node->getOperand(2)));
607 Ops.push_back(Node->getOperand(3)); // filename must be legal.
608 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
609 Result = DAG.UpdateNodeOperands(Result, Ops);
616 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
617 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
618 default: assert(0 && "This action is not supported yet!");
619 case TargetLowering::Legal:
620 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
621 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
622 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
623 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
629 case ISD::DEBUG_LABEL:
630 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
631 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
632 default: assert(0 && "This action is not supported yet!");
633 case TargetLowering::Legal:
634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
635 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
636 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
642 // We know we don't need to expand constants here, constants only have one
643 // value and we check that it is fine above.
645 // FIXME: Maybe we should handle things like targets that don't support full
646 // 32-bit immediates?
648 case ISD::ConstantFP: {
649 // Spill FP immediates to the constant pool if the target cannot directly
650 // codegen them. Targets often have some immediate values that can be
651 // efficiently generated into an FP register without a load. We explicitly
652 // leave these constants as ConstantFP nodes for the target to deal with.
653 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
655 // Check to see if this FP immediate is already legal.
656 bool isLegal = false;
657 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
658 E = TLI.legal_fpimm_end(); I != E; ++I)
659 if (CFP->isExactlyValue(*I)) {
664 // If this is a legal constant, turn it into a TargetConstantFP node.
666 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
670 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
671 default: assert(0 && "This action is not supported yet!");
672 case TargetLowering::Custom:
673 Tmp3 = TLI.LowerOperation(Result, DAG);
679 case TargetLowering::Expand:
680 // Otherwise we need to spill the constant to memory.
683 // If a FP immediate is precise when represented as a float and if the
684 // target can do an extending load from float to double, we put it into
685 // the constant pool as a float, even if it's is statically typed as a
687 MVT::ValueType VT = CFP->getValueType(0);
688 bool isDouble = VT == MVT::f64;
689 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
690 Type::FloatTy, CFP->getValue());
691 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
692 // Only do this if the target has a native EXTLOAD instruction from
694 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
695 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
700 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
702 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
703 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
705 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
706 DAG.getSrcValue(NULL));
711 case ISD::TokenFactor:
712 if (Node->getNumOperands() == 2) {
713 Tmp1 = LegalizeOp(Node->getOperand(0));
714 Tmp2 = LegalizeOp(Node->getOperand(1));
715 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
716 } else if (Node->getNumOperands() == 3) {
717 Tmp1 = LegalizeOp(Node->getOperand(0));
718 Tmp2 = LegalizeOp(Node->getOperand(1));
719 Tmp3 = LegalizeOp(Node->getOperand(2));
720 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
722 std::vector<SDOperand> Ops;
723 // Legalize the operands.
724 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
725 Ops.push_back(LegalizeOp(Node->getOperand(i)));
726 Result = DAG.UpdateNodeOperands(Result, Ops);
730 case ISD::BUILD_VECTOR:
731 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
732 default: assert(0 && "This action is not supported yet!");
733 case TargetLowering::Custom:
734 Tmp3 = TLI.LowerOperation(Result, DAG);
740 case TargetLowering::Expand: {
741 // We assume that built vectors are not legal, and will be immediately
742 // spilled to memory. If the values are all constants, turn this into a
743 // load from the constant pool.
744 bool isConstant = true;
745 for (SDNode::op_iterator I = Node->op_begin(), E = Node->op_end();
747 if (!isa<ConstantFPSDNode>(I) && !isa<ConstantSDNode>(I) &&
748 I->getOpcode() != ISD::UNDEF) {
754 // Create a ConstantPacked, and put it in the constant pool.
756 MVT::ValueType VT = Node->getValueType(0);
758 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
759 std::vector<Constant*> CV;
760 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
761 if (ConstantFPSDNode *V =
762 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
763 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
764 } else if (ConstantSDNode *V =
765 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
766 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
768 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
769 CV.push_back(UndefValue::get(OpNTy));
772 Constant *CP = ConstantPacked::get(CV);
773 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
774 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
775 DAG.getSrcValue(NULL));
779 // Otherwise, this isn't a constant entry. Allocate a sufficiently
780 // aligned object on the stack, store each element into it, then load
781 // the result as a vector.
782 MVT::ValueType VT = Node->getValueType(0);
783 // Create the stack frame object.
784 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
785 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
786 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
787 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
789 // Emit a store of each element to the stack slot.
790 std::vector<SDOperand> Stores;
791 bool isLittleEndian = TLI.isLittleEndian();
792 unsigned TypeByteSize =
793 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
794 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
795 // Store (in the right endianness) the elements to memory.
796 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
799 Offset = TypeByteSize*i;
801 Offset = TypeByteSize*(e-i-1);
803 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
804 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
806 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
807 Node->getOperand(i), Idx,
808 DAG.getSrcValue(NULL)));
810 SDOperand StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
812 // Result is a load from the stack slot.
813 Result = DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
818 case ISD::INSERT_VECTOR_ELT:
819 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
820 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
821 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
822 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
824 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
825 Node->getValueType(0))) {
826 default: assert(0 && "This action is not supported yet!");
827 case TargetLowering::Legal:
829 case TargetLowering::Custom:
830 Tmp3 = TLI.LowerOperation(Result, DAG);
836 case TargetLowering::Expand: {
837 // If the target doesn't support this, we have to spill the input vector
838 // to a temporary stack slot, update the element, then reload it. This is
839 // badness. We could also load the value into a vector register (either
840 // with a "move to register" or "extload into register" instruction, then
841 // permute it into place, if the idx is a constant and if the idx is
842 // supported by the target.
843 assert(0 && "INSERT_VECTOR_ELT expand not supported yet!");
848 case ISD::CALLSEQ_START: {
849 SDNode *CallEnd = FindCallEndFromCallStart(Node);
851 // Recursively Legalize all of the inputs of the call end that do not lead
852 // to this call start. This ensures that any libcalls that need be inserted
853 // are inserted *before* the CALLSEQ_START.
854 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
855 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
857 // Now that we legalized all of the inputs (which may have inserted
858 // libcalls) create the new CALLSEQ_START node.
859 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
861 // Merge in the last call, to ensure that this call start after the last
863 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
864 Tmp1 = LegalizeOp(Tmp1);
866 // Do not try to legalize the target-specific arguments (#1+).
867 if (Tmp1 != Node->getOperand(0)) {
868 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
870 Result = DAG.UpdateNodeOperands(Result, Ops);
873 // Remember that the CALLSEQ_START is legalized.
874 AddLegalizedOperand(Op.getValue(0), Result);
875 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
876 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
878 // Now that the callseq_start and all of the non-call nodes above this call
879 // sequence have been legalized, legalize the call itself. During this
880 // process, no libcalls can/will be inserted, guaranteeing that no calls
882 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
883 SDOperand InCallSEQ = LastCALLSEQ_END;
884 // Note that we are selecting this call!
885 LastCALLSEQ_END = SDOperand(CallEnd, 0);
886 IsLegalizingCall = true;
888 // Legalize the call, starting from the CALLSEQ_END.
889 LegalizeOp(LastCALLSEQ_END);
890 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
893 case ISD::CALLSEQ_END:
894 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
895 // will cause this node to be legalized as well as handling libcalls right.
896 if (LastCALLSEQ_END.Val != Node) {
897 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
898 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
899 assert(I != LegalizedNodes.end() &&
900 "Legalizing the call start should have legalized this node!");
904 // Otherwise, the call start has been legalized and everything is going
905 // according to plan. Just legalize ourselves normally here.
906 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
907 // Do not try to legalize the target-specific arguments (#1+), except for
908 // an optional flag input.
909 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
910 if (Tmp1 != Node->getOperand(0)) {
911 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
913 Result = DAG.UpdateNodeOperands(Result, Ops);
916 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
917 if (Tmp1 != Node->getOperand(0) ||
918 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
919 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
922 Result = DAG.UpdateNodeOperands(Result, Ops);
925 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
926 // This finishes up call legalization.
927 IsLegalizingCall = false;
929 // If the CALLSEQ_END node has a flag, remember that we legalized it.
930 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
931 if (Node->getNumValues() == 2)
932 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
933 return Result.getValue(Op.ResNo);
934 case ISD::DYNAMIC_STACKALLOC: {
935 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
936 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
937 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
938 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
940 Tmp1 = Result.getValue(0);
941 Tmp2 = Result.getValue(1);
942 switch (TLI.getOperationAction(Node->getOpcode(),
943 Node->getValueType(0))) {
944 default: assert(0 && "This action is not supported yet!");
945 case TargetLowering::Expand: {
946 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
947 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
948 " not tell us which reg is the stack pointer!");
949 SDOperand Chain = Tmp1.getOperand(0);
950 SDOperand Size = Tmp2.getOperand(1);
951 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
952 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
953 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
954 Tmp1 = LegalizeOp(Tmp1);
955 Tmp2 = LegalizeOp(Tmp2);
958 case TargetLowering::Custom:
959 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
961 Tmp1 = LegalizeOp(Tmp3);
962 Tmp2 = LegalizeOp(Tmp3.getValue(1));
965 case TargetLowering::Legal:
968 // Since this op produce two values, make sure to remember that we
969 // legalized both of them.
970 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
971 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
972 return Op.ResNo ? Tmp2 : Tmp1;
975 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain.
976 Tmp2 = Node->getOperand(Node->getNumOperands()-1);
977 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists.
978 Tmp2 = Tmp3 = SDOperand(0, 0);
980 Tmp3 = LegalizeOp(Tmp2);
982 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
983 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
985 if (Tmp3.Val) Ops.back() = Tmp3;
986 Result = DAG.UpdateNodeOperands(Result, Ops);
989 // INLINE asm returns a chain and flag, make sure to add both to the map.
990 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
991 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
992 return Result.getValue(Op.ResNo);
994 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
995 // Ensure that libcalls are emitted before a branch.
996 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
997 Tmp1 = LegalizeOp(Tmp1);
998 LastCALLSEQ_END = DAG.getEntryNode();
1000 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1004 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1005 // Ensure that libcalls are emitted before a return.
1006 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1007 Tmp1 = LegalizeOp(Tmp1);
1008 LastCALLSEQ_END = DAG.getEntryNode();
1010 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1011 case Expand: assert(0 && "It's impossible to expand bools");
1013 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1016 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1020 // Basic block destination (Op#2) is always legal.
1021 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1023 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1024 default: assert(0 && "This action is not supported yet!");
1025 case TargetLowering::Legal: break;
1026 case TargetLowering::Custom:
1027 Tmp1 = TLI.LowerOperation(Result, DAG);
1028 if (Tmp1.Val) Result = Tmp1;
1030 case TargetLowering::Expand:
1031 // Expand brcond's setcc into its constituent parts and create a BR_CC
1033 if (Tmp2.getOpcode() == ISD::SETCC) {
1034 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1035 Tmp2.getOperand(0), Tmp2.getOperand(1),
1036 Node->getOperand(2));
1038 // Make sure the condition is either zero or one. It may have been
1039 // promoted from something else.
1040 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1041 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1042 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1044 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1045 DAG.getCondCode(ISD::SETNE), Tmp2,
1046 DAG.getConstant(0, Tmp2.getValueType()),
1047 Node->getOperand(2));
1053 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1054 // Ensure that libcalls are emitted before a branch.
1055 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1056 Tmp1 = LegalizeOp(Tmp1);
1057 LastCALLSEQ_END = DAG.getEntryNode();
1059 Tmp2 = Node->getOperand(2); // LHS
1060 Tmp3 = Node->getOperand(3); // RHS
1061 Tmp4 = Node->getOperand(1); // CC
1063 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1065 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1066 // the LHS is a legal SETCC itself. In this case, we need to compare
1067 // the result against zero to select between true and false values.
1068 if (Tmp3.Val == 0) {
1069 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1070 Tmp4 = DAG.getCondCode(ISD::SETNE);
1073 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1074 Node->getOperand(4));
1076 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1077 default: assert(0 && "Unexpected action for BR_CC!");
1078 case TargetLowering::Legal: break;
1079 case TargetLowering::Custom:
1080 Tmp4 = TLI.LowerOperation(Result, DAG);
1081 if (Tmp4.Val) Result = Tmp4;
1086 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1087 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1089 MVT::ValueType VT = Node->getValueType(0);
1090 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1091 Tmp2 = Result.getValue(0);
1092 Tmp3 = Result.getValue(1);
1094 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1095 default: assert(0 && "This action is not supported yet!");
1096 case TargetLowering::Legal: break;
1097 case TargetLowering::Custom:
1098 Tmp1 = TLI.LowerOperation(Tmp2, DAG);
1100 Tmp2 = LegalizeOp(Tmp1);
1101 Tmp3 = LegalizeOp(Tmp1.getValue(1));
1105 // Since loads produce two values, make sure to remember that we
1106 // legalized both of them.
1107 AddLegalizedOperand(SDOperand(Node, 0), Tmp2);
1108 AddLegalizedOperand(SDOperand(Node, 1), Tmp3);
1109 return Op.ResNo ? Tmp3 : Tmp2;
1113 case ISD::ZEXTLOAD: {
1114 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1115 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1117 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1118 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1119 default: assert(0 && "This action is not supported yet!");
1120 case TargetLowering::Promote:
1121 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1122 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1123 DAG.getValueType(MVT::i8));
1124 Tmp1 = Result.getValue(0);
1125 Tmp2 = Result.getValue(1);
1127 case TargetLowering::Custom:
1130 case TargetLowering::Legal:
1131 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1132 Node->getOperand(3));
1133 Tmp1 = Result.getValue(0);
1134 Tmp2 = Result.getValue(1);
1137 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1139 Tmp1 = LegalizeOp(Tmp3);
1140 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1144 case TargetLowering::Expand:
1145 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1146 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1147 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1148 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1149 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1150 Tmp2 = LegalizeOp(Load.getValue(1));
1153 assert(Node->getOpcode() != ISD::EXTLOAD &&
1154 "EXTLOAD should always be supported!");
1155 // Turn the unsupported load into an EXTLOAD followed by an explicit
1156 // zero/sign extend inreg.
1157 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1158 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1160 if (Node->getOpcode() == ISD::SEXTLOAD)
1161 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1162 Result, DAG.getValueType(SrcVT));
1164 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1165 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1166 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1169 // Since loads produce two values, make sure to remember that we legalized
1171 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1172 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1173 return Op.ResNo ? Tmp2 : Tmp1;
1175 case ISD::EXTRACT_ELEMENT: {
1176 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1177 switch (getTypeAction(OpTy)) {
1178 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1180 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1182 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1183 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1184 TLI.getShiftAmountTy()));
1185 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1188 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1189 Node->getOperand(0));
1193 // Get both the low and high parts.
1194 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1195 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1196 Result = Tmp2; // 1 -> Hi
1198 Result = Tmp1; // 0 -> Lo
1204 case ISD::CopyToReg:
1205 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1207 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1208 "Register type must be legal!");
1209 // Legalize the incoming value (must be a legal type).
1210 Tmp2 = LegalizeOp(Node->getOperand(2));
1211 if (Node->getNumValues() == 1) {
1212 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1214 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1215 if (Node->getNumOperands() == 4) {
1216 Tmp3 = LegalizeOp(Node->getOperand(3));
1217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1223 // Since this produces two values, make sure to remember that we legalized
1225 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1226 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1232 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1234 // Ensure that libcalls are emitted before a return.
1235 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1236 Tmp1 = LegalizeOp(Tmp1);
1237 LastCALLSEQ_END = DAG.getEntryNode();
1239 switch (Node->getNumOperands()) {
1241 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1243 Tmp2 = LegalizeOp(Node->getOperand(1));
1244 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1248 ExpandOp(Node->getOperand(1), Lo, Hi);
1249 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1253 Tmp2 = PromoteOp(Node->getOperand(1));
1254 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1255 Result = LegalizeOp(Result);
1260 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1262 default: { // ret <values>
1263 std::vector<SDOperand> NewValues;
1264 NewValues.push_back(Tmp1);
1265 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1266 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1268 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1272 ExpandOp(Node->getOperand(i), Lo, Hi);
1273 NewValues.push_back(Lo);
1274 NewValues.push_back(Hi);
1278 assert(0 && "Can't promote multiple return value yet!");
1281 if (NewValues.size() == Node->getNumOperands())
1282 Result = DAG.UpdateNodeOperands(Result, NewValues);
1284 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1289 if (Result.getOpcode() == ISD::RET) {
1290 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1291 default: assert(0 && "This action is not supported yet!");
1292 case TargetLowering::Legal: break;
1293 case TargetLowering::Custom:
1294 Tmp1 = TLI.LowerOperation(Result, DAG);
1295 if (Tmp1.Val) Result = Tmp1;
1301 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1302 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1304 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1305 // FIXME: We shouldn't do this for TargetConstantFP's.
1306 // FIXME: move this to the DAG Combiner!
1307 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1308 if (CFP->getValueType(0) == MVT::f32) {
1309 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1311 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1312 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1314 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1315 Node->getOperand(3));
1319 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1321 Tmp3 = LegalizeOp(Node->getOperand(1));
1322 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1323 Node->getOperand(3));
1325 MVT::ValueType VT = Tmp3.getValueType();
1326 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1327 default: assert(0 && "This action is not supported yet!");
1328 case TargetLowering::Legal: break;
1329 case TargetLowering::Custom:
1330 Tmp1 = TLI.LowerOperation(Result, DAG);
1331 if (Tmp1.Val) Result = Tmp1;
1337 // Truncate the value and store the result.
1338 Tmp3 = PromoteOp(Node->getOperand(1));
1339 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1340 Node->getOperand(3),
1341 DAG.getValueType(Node->getOperand(1).getValueType()));
1345 unsigned IncrementSize = 0;
1348 // If this is a vector type, then we have to calculate the increment as
1349 // the product of the element size in bytes, and the number of elements
1350 // in the high half of the vector.
1351 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1352 SDNode *InVal = Node->getOperand(1).Val;
1354 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1355 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1357 // Figure out if there is a Packed type corresponding to this Vector
1358 // type. If so, convert to the packed type.
1359 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1360 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1361 // Turn this into a normal store of the packed type.
1362 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1363 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1364 Node->getOperand(3));
1366 } else if (NumElems == 1) {
1367 // Turn this into a normal store of the scalar type.
1368 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1369 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1370 Node->getOperand(3));
1373 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1374 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1377 ExpandOp(Node->getOperand(1), Lo, Hi);
1378 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1381 if (!TLI.isLittleEndian())
1384 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1385 Node->getOperand(3));
1386 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1387 getIntPtrConstant(IncrementSize));
1388 assert(isTypeLegal(Tmp2.getValueType()) &&
1389 "Pointers must be legal!");
1390 // FIXME: This sets the srcvalue of both halves to be the same, which is
1392 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1393 Node->getOperand(3));
1394 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1403 case ISD::STACKSAVE:
1404 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1405 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1406 Tmp1 = Result.getValue(0);
1407 Tmp2 = Result.getValue(1);
1409 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1410 default: assert(0 && "This action is not supported yet!");
1411 case TargetLowering::Legal: break;
1412 case TargetLowering::Custom:
1413 Tmp3 = TLI.LowerOperation(Result, DAG);
1415 Tmp1 = LegalizeOp(Tmp3);
1416 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1419 case TargetLowering::Expand:
1420 // Expand to CopyFromReg if the target set
1421 // StackPointerRegisterToSaveRestore.
1422 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1423 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1424 Node->getValueType(0));
1425 Tmp2 = Tmp1.getValue(1);
1427 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1428 Tmp2 = Node->getOperand(0);
1433 // Since stacksave produce two values, make sure to remember that we
1434 // legalized both of them.
1435 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1436 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1437 return Op.ResNo ? Tmp2 : Tmp1;
1439 case ISD::STACKRESTORE:
1440 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1441 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1442 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1444 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1445 default: assert(0 && "This action is not supported yet!");
1446 case TargetLowering::Legal: break;
1447 case TargetLowering::Custom:
1448 Tmp1 = TLI.LowerOperation(Result, DAG);
1449 if (Tmp1.Val) Result = Tmp1;
1451 case TargetLowering::Expand:
1452 // Expand to CopyToReg if the target set
1453 // StackPointerRegisterToSaveRestore.
1454 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1455 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1463 case ISD::READCYCLECOUNTER:
1464 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1465 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1467 // Since rdcc produce two values, make sure to remember that we legalized
1469 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1470 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1473 case ISD::TRUNCSTORE: {
1474 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1475 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1477 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1478 "Cannot handle illegal TRUNCSTORE yet!");
1479 Tmp2 = LegalizeOp(Node->getOperand(1));
1481 // The only promote case we handle is TRUNCSTORE:i1 X into
1482 // -> TRUNCSTORE:i8 (and X, 1)
1483 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1484 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1485 TargetLowering::Promote) {
1486 // Promote the bool to a mask then store.
1487 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1488 DAG.getConstant(1, Tmp2.getValueType()));
1489 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1490 Node->getOperand(3), DAG.getValueType(MVT::i8));
1492 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1493 Tmp3 != Node->getOperand(2)) {
1494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1495 Node->getOperand(3), Node->getOperand(4));
1498 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1499 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1500 default: assert(0 && "This action is not supported yet!");
1501 case TargetLowering::Legal: break;
1502 case TargetLowering::Custom:
1503 Tmp1 = TLI.LowerOperation(Result, DAG);
1504 if (Tmp1.Val) Result = Tmp1;
1510 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1511 case Expand: assert(0 && "It's impossible to expand bools");
1513 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1516 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1519 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1520 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1522 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1524 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1525 default: assert(0 && "This action is not supported yet!");
1526 case TargetLowering::Legal: break;
1527 case TargetLowering::Custom: {
1528 Tmp1 = TLI.LowerOperation(Result, DAG);
1529 if (Tmp1.Val) Result = Tmp1;
1532 case TargetLowering::Expand:
1533 if (Tmp1.getOpcode() == ISD::SETCC) {
1534 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1536 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1538 // Make sure the condition is either zero or one. It may have been
1539 // promoted from something else.
1540 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1541 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1542 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1543 Result = DAG.getSelectCC(Tmp1,
1544 DAG.getConstant(0, Tmp1.getValueType()),
1545 Tmp2, Tmp3, ISD::SETNE);
1548 case TargetLowering::Promote: {
1549 MVT::ValueType NVT =
1550 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1551 unsigned ExtOp, TruncOp;
1552 if (MVT::isInteger(Tmp2.getValueType())) {
1553 ExtOp = ISD::ANY_EXTEND;
1554 TruncOp = ISD::TRUNCATE;
1556 ExtOp = ISD::FP_EXTEND;
1557 TruncOp = ISD::FP_ROUND;
1559 // Promote each of the values to the new type.
1560 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1561 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1562 // Perform the larger operation, then round down.
1563 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1564 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1569 case ISD::SELECT_CC: {
1570 Tmp1 = Node->getOperand(0); // LHS
1571 Tmp2 = Node->getOperand(1); // RHS
1572 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1573 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1574 SDOperand CC = Node->getOperand(4);
1576 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1578 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1579 // the LHS is a legal SETCC itself. In this case, we need to compare
1580 // the result against zero to select between true and false values.
1581 if (Tmp2.Val == 0) {
1582 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1583 CC = DAG.getCondCode(ISD::SETNE);
1585 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1587 // Everything is legal, see if we should expand this op or something.
1588 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1589 default: assert(0 && "This action is not supported yet!");
1590 case TargetLowering::Legal: break;
1591 case TargetLowering::Custom:
1592 Tmp1 = TLI.LowerOperation(Result, DAG);
1593 if (Tmp1.Val) Result = Tmp1;
1599 Tmp1 = Node->getOperand(0);
1600 Tmp2 = Node->getOperand(1);
1601 Tmp3 = Node->getOperand(2);
1602 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1604 // If we had to Expand the SetCC operands into a SELECT node, then it may
1605 // not always be possible to return a true LHS & RHS. In this case, just
1606 // return the value we legalized, returned in the LHS
1607 if (Tmp2.Val == 0) {
1612 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1613 default: assert(0 && "Cannot handle this action for SETCC yet!");
1614 case TargetLowering::Custom:
1617 case TargetLowering::Legal:
1618 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1620 Tmp3 = TLI.LowerOperation(Result, DAG);
1621 if (Tmp3.Val) Result = Tmp3;
1624 case TargetLowering::Promote: {
1625 // First step, figure out the appropriate operation to use.
1626 // Allow SETCC to not be supported for all legal data types
1627 // Mostly this targets FP
1628 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1629 MVT::ValueType OldVT = NewInTy;
1631 // Scan for the appropriate larger type to use.
1633 NewInTy = (MVT::ValueType)(NewInTy+1);
1635 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1636 "Fell off of the edge of the integer world");
1637 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1638 "Fell off of the edge of the floating point world");
1640 // If the target supports SETCC of this type, use it.
1641 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1644 if (MVT::isInteger(NewInTy))
1645 assert(0 && "Cannot promote Legal Integer SETCC yet");
1647 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1648 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1650 Tmp1 = LegalizeOp(Tmp1);
1651 Tmp2 = LegalizeOp(Tmp2);
1652 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1653 Result = LegalizeOp(Result);
1656 case TargetLowering::Expand:
1657 // Expand a setcc node into a select_cc of the same condition, lhs, and
1658 // rhs that selects between const 1 (true) and const 0 (false).
1659 MVT::ValueType VT = Node->getValueType(0);
1660 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1661 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1662 Node->getOperand(2));
1668 case ISD::MEMMOVE: {
1669 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1670 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1672 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1673 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1674 case Expand: assert(0 && "Cannot expand a byte!");
1676 Tmp3 = LegalizeOp(Node->getOperand(2));
1679 Tmp3 = PromoteOp(Node->getOperand(2));
1683 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1687 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1689 // Length is too big, just take the lo-part of the length.
1691 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1695 Tmp4 = LegalizeOp(Node->getOperand(3));
1698 Tmp4 = PromoteOp(Node->getOperand(3));
1703 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1704 case Expand: assert(0 && "Cannot expand this yet!");
1706 Tmp5 = LegalizeOp(Node->getOperand(4));
1709 Tmp5 = PromoteOp(Node->getOperand(4));
1713 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1714 default: assert(0 && "This action not implemented for this operation!");
1715 case TargetLowering::Custom:
1718 case TargetLowering::Legal:
1719 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
1721 Tmp1 = TLI.LowerOperation(Result, DAG);
1722 if (Tmp1.Val) Result = Tmp1;
1725 case TargetLowering::Expand: {
1726 // Otherwise, the target does not support this operation. Lower the
1727 // operation to an explicit libcall as appropriate.
1728 MVT::ValueType IntPtr = TLI.getPointerTy();
1729 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1730 std::vector<std::pair<SDOperand, const Type*> > Args;
1732 const char *FnName = 0;
1733 if (Node->getOpcode() == ISD::MEMSET) {
1734 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1735 // Extend the (previously legalized) ubyte argument to be an int value
1737 if (Tmp3.getValueType() > MVT::i32)
1738 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
1740 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1741 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1742 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1745 } else if (Node->getOpcode() == ISD::MEMCPY ||
1746 Node->getOpcode() == ISD::MEMMOVE) {
1747 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1748 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1749 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1750 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1752 assert(0 && "Unknown op!");
1755 std::pair<SDOperand,SDOperand> CallResult =
1756 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1757 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1758 Result = CallResult.second;
1765 case ISD::SHL_PARTS:
1766 case ISD::SRA_PARTS:
1767 case ISD::SRL_PARTS: {
1768 std::vector<SDOperand> Ops;
1769 bool Changed = false;
1770 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1771 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1772 Changed |= Ops.back() != Node->getOperand(i);
1775 Result = DAG.UpdateNodeOperands(Result, Ops);
1777 switch (TLI.getOperationAction(Node->getOpcode(),
1778 Node->getValueType(0))) {
1779 default: assert(0 && "This action is not supported yet!");
1780 case TargetLowering::Legal: break;
1781 case TargetLowering::Custom:
1782 Tmp1 = TLI.LowerOperation(Result, DAG);
1784 SDOperand Tmp2, RetVal(0, 0);
1785 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
1786 Tmp2 = LegalizeOp(Tmp1.getValue(i));
1787 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
1791 assert(RetVal.Val && "Illegal result number");
1797 // Since these produce multiple values, make sure to remember that we
1798 // legalized all of them.
1799 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1800 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1801 return Result.getValue(Op.ResNo);
1822 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1823 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1824 case Expand: assert(0 && "Not possible");
1826 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1829 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1835 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1836 default: assert(0 && "Operation not supported");
1837 case TargetLowering::Legal: break;
1838 case TargetLowering::Custom:
1839 Tmp1 = TLI.LowerOperation(Result, DAG);
1840 if (Tmp1.Val) Result = Tmp1;
1845 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
1846 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1847 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1848 case Expand: assert(0 && "Not possible");
1850 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1853 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1857 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1859 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1860 default: assert(0 && "Operation not supported");
1861 case TargetLowering::Custom:
1862 Tmp1 = TLI.LowerOperation(Result, DAG);
1863 if (Tmp1.Val) Result = Tmp1;
1865 case TargetLowering::Legal: break;
1866 case TargetLowering::Expand:
1867 // If this target supports fabs/fneg natively, do this efficiently.
1868 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
1869 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
1870 // Get the sign bit of the RHS.
1871 MVT::ValueType IVT =
1872 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
1873 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
1874 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
1875 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
1876 // Get the absolute value of the result.
1877 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
1878 // Select between the nabs and abs value based on the sign bit of
1880 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
1881 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
1884 Result = LegalizeOp(Result);
1888 // Otherwise, do bitwise ops!
1890 // copysign -> copysignf/copysign libcall.
1892 if (Node->getValueType(0) == MVT::f32) {
1893 FnName = "copysignf";
1894 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
1895 Result = DAG.UpdateNodeOperands(Result, Tmp1,
1896 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
1898 FnName = "copysign";
1899 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
1900 Result = DAG.UpdateNodeOperands(Result, Tmp1,
1901 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
1904 Result = ExpandLibCall(FnName, Node, Dummy);
1911 Tmp1 = LegalizeOp(Node->getOperand(0));
1912 Tmp2 = LegalizeOp(Node->getOperand(1));
1913 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1914 // Since this produces two values, make sure to remember that we legalized
1916 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1917 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1922 Tmp1 = LegalizeOp(Node->getOperand(0));
1923 Tmp2 = LegalizeOp(Node->getOperand(1));
1924 Tmp3 = LegalizeOp(Node->getOperand(2));
1925 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1926 // Since this produces two values, make sure to remember that we legalized
1928 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1929 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1932 case ISD::BUILD_PAIR: {
1933 MVT::ValueType PairTy = Node->getValueType(0);
1934 // TODO: handle the case where the Lo and Hi operands are not of legal type
1935 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1936 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1937 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1938 case TargetLowering::Promote:
1939 case TargetLowering::Custom:
1940 assert(0 && "Cannot promote/custom this yet!");
1941 case TargetLowering::Legal:
1942 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1943 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1945 case TargetLowering::Expand:
1946 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
1947 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
1948 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
1949 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
1950 TLI.getShiftAmountTy()));
1951 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
1960 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1961 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1963 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1964 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
1965 case TargetLowering::Custom:
1968 case TargetLowering::Legal:
1969 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1971 Tmp1 = TLI.LowerOperation(Result, DAG);
1972 if (Tmp1.Val) Result = Tmp1;
1975 case TargetLowering::Expand:
1976 if (MVT::isInteger(Node->getValueType(0))) {
1978 MVT::ValueType VT = Node->getValueType(0);
1979 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
1980 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1981 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1982 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1984 // Floating point mod -> fmod libcall.
1985 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1987 Result = ExpandLibCall(FnName, Node, Dummy);
1993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1994 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1996 MVT::ValueType VT = Node->getValueType(0);
1997 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1998 default: assert(0 && "This action is not supported yet!");
1999 case TargetLowering::Custom:
2002 case TargetLowering::Legal:
2003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2004 Result = Result.getValue(0);
2005 Tmp1 = Result.getValue(1);
2008 Tmp2 = TLI.LowerOperation(Result, DAG);
2010 Result = LegalizeOp(Tmp2);
2011 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2015 case TargetLowering::Expand: {
2016 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2017 Node->getOperand(2));
2018 // Increment the pointer, VAList, to the next vaarg
2019 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2020 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2021 TLI.getPointerTy()));
2022 // Store the incremented VAList to the legalized pointer
2023 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2024 Node->getOperand(2));
2025 // Load the actual argument out of the pointer VAList
2026 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2027 Tmp1 = LegalizeOp(Result.getValue(1));
2028 Result = LegalizeOp(Result);
2032 // Since VAARG produces two values, make sure to remember that we
2033 // legalized both of them.
2034 AddLegalizedOperand(SDOperand(Node, 0), Result);
2035 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2036 return Op.ResNo ? Tmp1 : Result;
2040 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2041 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2042 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2044 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2045 default: assert(0 && "This action is not supported yet!");
2046 case TargetLowering::Custom:
2049 case TargetLowering::Legal:
2050 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2051 Node->getOperand(3), Node->getOperand(4));
2053 Tmp1 = TLI.LowerOperation(Result, DAG);
2054 if (Tmp1.Val) Result = Tmp1;
2057 case TargetLowering::Expand:
2058 // This defaults to loading a pointer from the input and storing it to the
2059 // output, returning the chain.
2060 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2061 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2062 Node->getOperand(4));
2068 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2069 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2071 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2072 default: assert(0 && "This action is not supported yet!");
2073 case TargetLowering::Custom:
2076 case TargetLowering::Legal:
2077 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2079 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2080 if (Tmp1.Val) Result = Tmp1;
2083 case TargetLowering::Expand:
2084 Result = Tmp1; // Default to a no-op, return the chain
2090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2091 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2093 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2095 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2096 default: assert(0 && "This action is not supported yet!");
2097 case TargetLowering::Legal: break;
2098 case TargetLowering::Custom:
2099 Tmp1 = TLI.LowerOperation(Result, DAG);
2100 if (Tmp1.Val) Result = Tmp1;
2107 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2108 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2110 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2111 "Cannot handle this yet!");
2112 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2116 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2117 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2118 case TargetLowering::Custom:
2119 assert(0 && "Cannot custom legalize this yet!");
2120 case TargetLowering::Legal:
2121 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2123 case TargetLowering::Promote: {
2124 MVT::ValueType OVT = Tmp1.getValueType();
2125 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2126 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2128 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2129 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2130 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2131 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2134 case TargetLowering::Expand:
2135 Result = ExpandBSWAP(Tmp1);
2143 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2144 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2145 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2146 case TargetLowering::Legal:
2147 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2149 case TargetLowering::Promote: {
2150 MVT::ValueType OVT = Tmp1.getValueType();
2151 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2153 // Zero extend the argument.
2154 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2155 // Perform the larger operation, then subtract if needed.
2156 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2157 switch (Node->getOpcode()) {
2162 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2163 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2164 DAG.getConstant(getSizeInBits(NVT), NVT),
2166 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2167 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2170 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2171 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2172 DAG.getConstant(getSizeInBits(NVT) -
2173 getSizeInBits(OVT), NVT));
2178 case TargetLowering::Expand:
2179 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2190 Tmp1 = LegalizeOp(Node->getOperand(0));
2191 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2192 case TargetLowering::Promote:
2193 case TargetLowering::Custom:
2196 case TargetLowering::Legal:
2197 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2199 Tmp1 = TLI.LowerOperation(Result, DAG);
2200 if (Tmp1.Val) Result = Tmp1;
2203 case TargetLowering::Expand:
2204 switch (Node->getOpcode()) {
2205 default: assert(0 && "Unreachable!");
2207 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2208 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2209 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2212 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2213 MVT::ValueType VT = Node->getValueType(0);
2214 Tmp2 = DAG.getConstantFP(0.0, VT);
2215 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2216 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2217 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2223 MVT::ValueType VT = Node->getValueType(0);
2224 const char *FnName = 0;
2225 switch(Node->getOpcode()) {
2226 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2227 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2228 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2229 default: assert(0 && "Unreachable!");
2232 Result = ExpandLibCall(FnName, Node, Dummy);
2240 case ISD::BIT_CONVERT:
2241 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2242 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2244 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2245 Node->getOperand(0).getValueType())) {
2246 default: assert(0 && "Unknown operation action!");
2247 case TargetLowering::Expand:
2248 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2250 case TargetLowering::Legal:
2251 Tmp1 = LegalizeOp(Node->getOperand(0));
2252 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2257 // Conversion operators. The source and destination have different types.
2258 case ISD::SINT_TO_FP:
2259 case ISD::UINT_TO_FP: {
2260 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2261 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2263 switch (TLI.getOperationAction(Node->getOpcode(),
2264 Node->getOperand(0).getValueType())) {
2265 default: assert(0 && "Unknown operation action!");
2266 case TargetLowering::Custom:
2269 case TargetLowering::Legal:
2270 Tmp1 = LegalizeOp(Node->getOperand(0));
2271 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2273 Tmp1 = TLI.LowerOperation(Result, DAG);
2274 if (Tmp1.Val) Result = Tmp1;
2277 case TargetLowering::Expand:
2278 Result = ExpandLegalINT_TO_FP(isSigned,
2279 LegalizeOp(Node->getOperand(0)),
2280 Node->getValueType(0));
2282 case TargetLowering::Promote:
2283 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2284 Node->getValueType(0),
2290 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2291 Node->getValueType(0), Node->getOperand(0));
2294 Tmp1 = PromoteOp(Node->getOperand(0));
2296 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2297 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2299 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2300 Node->getOperand(0).getValueType());
2302 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2303 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2309 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2311 Tmp1 = LegalizeOp(Node->getOperand(0));
2312 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2315 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2317 // Since the result is legal, we should just be able to truncate the low
2318 // part of the source.
2319 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2322 Result = PromoteOp(Node->getOperand(0));
2323 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2328 case ISD::FP_TO_SINT:
2329 case ISD::FP_TO_UINT:
2330 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2332 Tmp1 = LegalizeOp(Node->getOperand(0));
2334 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2335 default: assert(0 && "Unknown operation action!");
2336 case TargetLowering::Custom:
2339 case TargetLowering::Legal:
2340 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2342 Tmp1 = TLI.LowerOperation(Result, DAG);
2343 if (Tmp1.Val) Result = Tmp1;
2346 case TargetLowering::Promote:
2347 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2348 Node->getOpcode() == ISD::FP_TO_SINT);
2350 case TargetLowering::Expand:
2351 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2352 SDOperand True, False;
2353 MVT::ValueType VT = Node->getOperand(0).getValueType();
2354 MVT::ValueType NVT = Node->getValueType(0);
2355 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2356 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2357 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2358 Node->getOperand(0), Tmp2, ISD::SETLT);
2359 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2360 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2361 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2363 False = DAG.getNode(ISD::XOR, NVT, False,
2364 DAG.getConstant(1ULL << ShiftAmt, NVT));
2365 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2368 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2374 assert(0 && "Shouldn't need to expand other operators here!");
2376 Tmp1 = PromoteOp(Node->getOperand(0));
2377 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2378 Result = LegalizeOp(Result);
2383 case ISD::ANY_EXTEND:
2384 case ISD::ZERO_EXTEND:
2385 case ISD::SIGN_EXTEND:
2386 case ISD::FP_EXTEND:
2388 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2389 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2391 Tmp1 = LegalizeOp(Node->getOperand(0));
2392 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2395 switch (Node->getOpcode()) {
2396 case ISD::ANY_EXTEND:
2397 Tmp1 = PromoteOp(Node->getOperand(0));
2398 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2400 case ISD::ZERO_EXTEND:
2401 Result = PromoteOp(Node->getOperand(0));
2402 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2403 Result = DAG.getZeroExtendInReg(Result,
2404 Node->getOperand(0).getValueType());
2406 case ISD::SIGN_EXTEND:
2407 Result = PromoteOp(Node->getOperand(0));
2408 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2409 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2411 DAG.getValueType(Node->getOperand(0).getValueType()));
2413 case ISD::FP_EXTEND:
2414 Result = PromoteOp(Node->getOperand(0));
2415 if (Result.getValueType() != Op.getValueType())
2416 // Dynamically dead while we have only 2 FP types.
2417 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2420 Result = PromoteOp(Node->getOperand(0));
2421 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2426 case ISD::FP_ROUND_INREG:
2427 case ISD::SIGN_EXTEND_INREG: {
2428 Tmp1 = LegalizeOp(Node->getOperand(0));
2429 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2431 // If this operation is not supported, convert it to a shl/shr or load/store
2433 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2434 default: assert(0 && "This action not supported for this op yet!");
2435 case TargetLowering::Legal:
2436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2438 case TargetLowering::Expand:
2439 // If this is an integer extend and shifts are supported, do that.
2440 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2441 // NOTE: we could fall back on load/store here too for targets without
2442 // SAR. However, it is doubtful that any exist.
2443 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2444 MVT::getSizeInBits(ExtraVT);
2445 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2446 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2447 Node->getOperand(0), ShiftCst);
2448 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2450 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2451 // The only way we can lower this is to turn it into a STORETRUNC,
2452 // EXTLOAD pair, targetting a temporary location (a stack slot).
2454 // NOTE: there is a choice here between constantly creating new stack
2455 // slots and always reusing the same one. We currently always create
2456 // new ones, as reuse may inhibit scheduling.
2457 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2458 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2459 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2460 MachineFunction &MF = DAG.getMachineFunction();
2462 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2463 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2464 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2465 Node->getOperand(0), StackSlot,
2466 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2467 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2468 Result, StackSlot, DAG.getSrcValue(NULL),
2471 assert(0 && "Unknown op");
2479 // Make sure that the generated code is itself legal.
2481 Result = LegalizeOp(Result);
2483 // Note that LegalizeOp may be reentered even from single-use nodes, which
2484 // means that we always must cache transformed nodes.
2485 AddLegalizedOperand(Op, Result);
2489 /// PromoteOp - Given an operation that produces a value in an invalid type,
2490 /// promote it to compute the value into a larger type. The produced value will
2491 /// have the correct bits for the low portion of the register, but no guarantee
2492 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2493 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2494 MVT::ValueType VT = Op.getValueType();
2495 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2496 assert(getTypeAction(VT) == Promote &&
2497 "Caller should expand or legalize operands that are not promotable!");
2498 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2499 "Cannot promote to smaller type!");
2501 SDOperand Tmp1, Tmp2, Tmp3;
2503 SDNode *Node = Op.Val;
2505 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2506 if (I != PromotedNodes.end()) return I->second;
2508 switch (Node->getOpcode()) {
2509 case ISD::CopyFromReg:
2510 assert(0 && "CopyFromReg must be legal!");
2512 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2513 assert(0 && "Do not know how to promote this operator!");
2516 Result = DAG.getNode(ISD::UNDEF, NVT);
2520 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2522 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2523 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2525 case ISD::ConstantFP:
2526 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2527 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2531 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2532 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2533 Node->getOperand(1), Node->getOperand(2));
2537 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2539 Result = LegalizeOp(Node->getOperand(0));
2540 assert(Result.getValueType() >= NVT &&
2541 "This truncation doesn't make sense!");
2542 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2543 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2546 // The truncation is not required, because we don't guarantee anything
2547 // about high bits anyway.
2548 Result = PromoteOp(Node->getOperand(0));
2551 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2552 // Truncate the low part of the expanded value to the result type
2553 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2556 case ISD::SIGN_EXTEND:
2557 case ISD::ZERO_EXTEND:
2558 case ISD::ANY_EXTEND:
2559 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2560 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2562 // Input is legal? Just do extend all the way to the larger type.
2563 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2566 // Promote the reg if it's smaller.
2567 Result = PromoteOp(Node->getOperand(0));
2568 // The high bits are not guaranteed to be anything. Insert an extend.
2569 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2570 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2571 DAG.getValueType(Node->getOperand(0).getValueType()));
2572 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2573 Result = DAG.getZeroExtendInReg(Result,
2574 Node->getOperand(0).getValueType());
2578 case ISD::BIT_CONVERT:
2579 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2580 Result = PromoteOp(Result);
2583 case ISD::FP_EXTEND:
2584 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2586 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2587 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2588 case Promote: assert(0 && "Unreachable with 2 FP types!");
2590 // Input is legal? Do an FP_ROUND_INREG.
2591 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2592 DAG.getValueType(VT));
2597 case ISD::SINT_TO_FP:
2598 case ISD::UINT_TO_FP:
2599 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2601 // No extra round required here.
2602 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2606 Result = PromoteOp(Node->getOperand(0));
2607 if (Node->getOpcode() == ISD::SINT_TO_FP)
2608 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2610 DAG.getValueType(Node->getOperand(0).getValueType()));
2612 Result = DAG.getZeroExtendInReg(Result,
2613 Node->getOperand(0).getValueType());
2614 // No extra round required here.
2615 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2618 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2619 Node->getOperand(0));
2620 // Round if we cannot tolerate excess precision.
2621 if (NoExcessFPPrecision)
2622 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2623 DAG.getValueType(VT));
2628 case ISD::SIGN_EXTEND_INREG:
2629 Result = PromoteOp(Node->getOperand(0));
2630 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2631 Node->getOperand(1));
2633 case ISD::FP_TO_SINT:
2634 case ISD::FP_TO_UINT:
2635 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2637 Tmp1 = Node->getOperand(0);
2640 // The input result is prerounded, so we don't have to do anything
2642 Tmp1 = PromoteOp(Node->getOperand(0));
2645 assert(0 && "not implemented");
2647 // If we're promoting a UINT to a larger size, check to see if the new node
2648 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2649 // we can use that instead. This allows us to generate better code for
2650 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2651 // legal, such as PowerPC.
2652 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2653 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2654 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2655 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2656 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2658 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2664 Tmp1 = PromoteOp(Node->getOperand(0));
2665 assert(Tmp1.getValueType() == NVT);
2666 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2667 // NOTE: we do not have to do any extra rounding here for
2668 // NoExcessFPPrecision, because we know the input will have the appropriate
2669 // precision, and these operations don't modify precision at all.
2675 Tmp1 = PromoteOp(Node->getOperand(0));
2676 assert(Tmp1.getValueType() == NVT);
2677 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2678 if (NoExcessFPPrecision)
2679 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2680 DAG.getValueType(VT));
2689 // The input may have strange things in the top bits of the registers, but
2690 // these operations don't care. They may have weird bits going out, but
2691 // that too is okay if they are integer operations.
2692 Tmp1 = PromoteOp(Node->getOperand(0));
2693 Tmp2 = PromoteOp(Node->getOperand(1));
2694 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2695 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2700 Tmp1 = PromoteOp(Node->getOperand(0));
2701 Tmp2 = PromoteOp(Node->getOperand(1));
2702 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2703 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2705 // Floating point operations will give excess precision that we may not be
2706 // able to tolerate. If we DO allow excess precision, just leave it,
2707 // otherwise excise it.
2708 // FIXME: Why would we need to round FP ops more than integer ones?
2709 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2710 if (NoExcessFPPrecision)
2711 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2712 DAG.getValueType(VT));
2717 // These operators require that their input be sign extended.
2718 Tmp1 = PromoteOp(Node->getOperand(0));
2719 Tmp2 = PromoteOp(Node->getOperand(1));
2720 if (MVT::isInteger(NVT)) {
2721 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2722 DAG.getValueType(VT));
2723 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2724 DAG.getValueType(VT));
2726 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2728 // Perform FP_ROUND: this is probably overly pessimistic.
2729 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2730 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2731 DAG.getValueType(VT));
2735 case ISD::FCOPYSIGN:
2736 // These operators require that their input be fp extended.
2737 Tmp1 = PromoteOp(Node->getOperand(0));
2738 Tmp2 = PromoteOp(Node->getOperand(1));
2739 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2741 // Perform FP_ROUND: this is probably overly pessimistic.
2742 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
2743 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2744 DAG.getValueType(VT));
2749 // These operators require that their input be zero extended.
2750 Tmp1 = PromoteOp(Node->getOperand(0));
2751 Tmp2 = PromoteOp(Node->getOperand(1));
2752 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2753 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2754 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2755 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2759 Tmp1 = PromoteOp(Node->getOperand(0));
2760 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
2763 // The input value must be properly sign extended.
2764 Tmp1 = PromoteOp(Node->getOperand(0));
2765 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2766 DAG.getValueType(VT));
2767 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
2770 // The input value must be properly zero extended.
2771 Tmp1 = PromoteOp(Node->getOperand(0));
2772 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2773 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
2777 Tmp1 = Node->getOperand(0); // Get the chain.
2778 Tmp2 = Node->getOperand(1); // Get the pointer.
2779 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
2780 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
2781 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
2783 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2784 Node->getOperand(2));
2785 // Increment the pointer, VAList, to the next vaarg
2786 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2787 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2788 TLI.getPointerTy()));
2789 // Store the incremented VAList to the legalized pointer
2790 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2791 Node->getOperand(2));
2792 // Load the actual argument out of the pointer VAList
2793 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
2794 DAG.getSrcValue(0), VT);
2796 // Remember that we legalized the chain.
2797 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2801 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
2802 Node->getOperand(1), Node->getOperand(2), VT);
2803 // Remember that we legalized the chain.
2804 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2809 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
2810 Node->getOperand(1), Node->getOperand(2),
2811 cast<VTSDNode>(Node->getOperand(3))->getVT());
2812 // Remember that we legalized the chain.
2813 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
2816 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2817 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2818 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
2820 case ISD::SELECT_CC:
2821 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2822 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2823 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2824 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
2827 Tmp1 = Node->getOperand(0);
2828 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2829 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2830 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2831 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
2832 TLI.getShiftAmountTy()));
2837 // Zero extend the argument
2838 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
2839 // Perform the larger operation, then subtract if needed.
2840 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2841 switch(Node->getOpcode()) {
2846 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2847 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2848 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2849 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2850 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
2853 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2854 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2855 DAG.getConstant(getSizeInBits(NVT) -
2856 getSizeInBits(VT), NVT));
2862 assert(Result.Val && "Didn't set a result!");
2864 // Make sure the result is itself legal.
2865 Result = LegalizeOp(Result);
2867 // Remember that we promoted this!
2868 AddPromotedOperand(Op, Result);
2872 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
2873 /// with condition CC on the current target. This usually involves legalizing
2874 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
2875 /// there may be no choice but to create a new SetCC node to represent the
2876 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
2877 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
2878 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
2881 SDOperand Tmp1, Tmp2, Result;
2883 switch (getTypeAction(LHS.getValueType())) {
2885 Tmp1 = LegalizeOp(LHS); // LHS
2886 Tmp2 = LegalizeOp(RHS); // RHS
2889 Tmp1 = PromoteOp(LHS); // LHS
2890 Tmp2 = PromoteOp(RHS); // RHS
2892 // If this is an FP compare, the operands have already been extended.
2893 if (MVT::isInteger(LHS.getValueType())) {
2894 MVT::ValueType VT = LHS.getValueType();
2895 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2897 // Otherwise, we have to insert explicit sign or zero extends. Note
2898 // that we could insert sign extends for ALL conditions, but zero extend
2899 // is cheaper on many machines (an AND instead of two shifts), so prefer
2901 switch (cast<CondCodeSDNode>(CC)->get()) {
2902 default: assert(0 && "Unknown integer comparison!");
2909 // ALL of these operations will work if we either sign or zero extend
2910 // the operands (including the unsigned comparisons!). Zero extend is
2911 // usually a simpler/cheaper operation, so prefer it.
2912 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2913 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2919 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2920 DAG.getValueType(VT));
2921 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2922 DAG.getValueType(VT));
2928 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
2929 ExpandOp(LHS, LHSLo, LHSHi);
2930 ExpandOp(RHS, RHSLo, RHSHi);
2931 switch (cast<CondCodeSDNode>(CC)->get()) {
2935 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
2936 if (RHSCST->isAllOnesValue()) {
2937 // Comparison to -1.
2938 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
2943 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
2944 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
2945 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
2946 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2949 // If this is a comparison of the sign bit, just look at the top part.
2951 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
2952 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
2953 CST->getValue() == 0) || // X < 0
2954 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
2955 CST->isAllOnesValue())) { // X > -1
2961 // FIXME: This generated code sucks.
2962 ISD::CondCode LowCC;
2963 switch (cast<CondCodeSDNode>(CC)->get()) {
2964 default: assert(0 && "Unknown integer setcc!");
2966 case ISD::SETULT: LowCC = ISD::SETULT; break;
2968 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
2970 case ISD::SETULE: LowCC = ISD::SETULE; break;
2972 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
2975 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2976 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
2977 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2979 // NOTE: on targets without efficient SELECT of bools, we can always use
2980 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
2981 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
2982 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
2983 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
2984 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
2985 Result, Tmp1, Tmp2));
2994 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
2995 /// The resultant code need not be legal. Note that SrcOp is the input operand
2996 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
2997 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
2999 // Create the stack frame object.
3000 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3001 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8;
3002 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3003 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3005 // Emit a store to the stack slot.
3006 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3007 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3008 // Result is a load from the stack slot.
3009 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3012 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3013 SDOperand Op, SDOperand Amt,
3014 SDOperand &Lo, SDOperand &Hi) {
3015 // Expand the subcomponents.
3016 SDOperand LHSL, LHSH;
3017 ExpandOp(Op, LHSL, LHSH);
3019 std::vector<SDOperand> Ops;
3020 Ops.push_back(LHSL);
3021 Ops.push_back(LHSH);
3023 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3024 Lo = DAG.getNode(NodeOp, VTs, Ops);
3025 Hi = Lo.getValue(1);
3029 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3030 /// smaller elements. If we can't find a way that is more efficient than a
3031 /// libcall on this target, return false. Otherwise, return true with the
3032 /// low-parts expanded into Lo and Hi.
3033 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3034 SDOperand &Lo, SDOperand &Hi) {
3035 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3036 "This is not a shift!");
3038 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3039 SDOperand ShAmt = LegalizeOp(Amt);
3040 MVT::ValueType ShTy = ShAmt.getValueType();
3041 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3042 unsigned NVTBits = MVT::getSizeInBits(NVT);
3044 // Handle the case when Amt is an immediate. Other cases are currently broken
3045 // and are disabled.
3046 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3047 unsigned Cst = CN->getValue();
3048 // Expand the incoming operand to be shifted, so that we have its parts
3050 ExpandOp(Op, InL, InH);
3054 Lo = DAG.getConstant(0, NVT);
3055 Hi = DAG.getConstant(0, NVT);
3056 } else if (Cst > NVTBits) {
3057 Lo = DAG.getConstant(0, NVT);
3058 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3059 } else if (Cst == NVTBits) {
3060 Lo = DAG.getConstant(0, NVT);
3063 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3064 Hi = DAG.getNode(ISD::OR, NVT,
3065 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3066 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3071 Lo = DAG.getConstant(0, NVT);
3072 Hi = DAG.getConstant(0, NVT);
3073 } else if (Cst > NVTBits) {
3074 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3075 Hi = DAG.getConstant(0, NVT);
3076 } else if (Cst == NVTBits) {
3078 Hi = DAG.getConstant(0, NVT);
3080 Lo = DAG.getNode(ISD::OR, NVT,
3081 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3082 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3083 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3088 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3089 DAG.getConstant(NVTBits-1, ShTy));
3090 } else if (Cst > NVTBits) {
3091 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3092 DAG.getConstant(Cst-NVTBits, ShTy));
3093 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3094 DAG.getConstant(NVTBits-1, ShTy));
3095 } else if (Cst == NVTBits) {
3097 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3098 DAG.getConstant(NVTBits-1, ShTy));
3100 Lo = DAG.getNode(ISD::OR, NVT,
3101 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3102 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3103 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3112 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3113 // does not fit into a register, return the lo part and set the hi part to the
3114 // by-reg argument. If it does fit into a single register, return the result
3115 // and leave the Hi part unset.
3116 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3118 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3119 // The input chain to this libcall is the entry node of the function.
3120 // Legalizing the call will automatically add the previous call to the
3122 SDOperand InChain = DAG.getEntryNode();
3124 TargetLowering::ArgListTy Args;
3125 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3126 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3127 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3128 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3130 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3132 // Splice the libcall in wherever FindInputOutputChains tells us to.
3133 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3134 std::pair<SDOperand,SDOperand> CallInfo =
3135 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3138 // Legalize the call sequence, starting with the chain. This will advance
3139 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3140 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3141 LegalizeOp(CallInfo.second);
3143 switch (getTypeAction(CallInfo.first.getValueType())) {
3144 default: assert(0 && "Unknown thing");
3146 Result = CallInfo.first;
3149 ExpandOp(CallInfo.first, Result, Hi);
3156 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3157 /// destination type is legal.
3158 SDOperand SelectionDAGLegalize::
3159 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3160 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3161 assert(getTypeAction(Source.getValueType()) == Expand &&
3162 "This is not an expansion!");
3163 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3166 assert(Source.getValueType() == MVT::i64 &&
3167 "This only works for 64-bit -> FP");
3168 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3169 // incoming integer is set. To handle this, we dynamically test to see if
3170 // it is set, and, if so, add a fudge factor.
3172 ExpandOp(Source, Lo, Hi);
3174 // If this is unsigned, and not supported, first perform the conversion to
3175 // signed, then adjust the result if the sign bit is set.
3176 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3177 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3179 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3180 DAG.getConstant(0, Hi.getValueType()),
3182 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3183 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3184 SignSet, Four, Zero);
3185 uint64_t FF = 0x5f800000ULL;
3186 if (TLI.isLittleEndian()) FF <<= 32;
3187 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3189 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3190 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3191 SDOperand FudgeInReg;
3192 if (DestTy == MVT::f32)
3193 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3194 DAG.getSrcValue(NULL));
3196 assert(DestTy == MVT::f64 && "Unexpected conversion");
3197 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3198 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3200 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3203 // Check to see if the target has a custom way to lower this. If so, use it.
3204 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3205 default: assert(0 && "This action not implemented for this operation!");
3206 case TargetLowering::Legal:
3207 case TargetLowering::Expand:
3208 break; // This case is handled below.
3209 case TargetLowering::Custom: {
3210 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3213 return LegalizeOp(NV);
3214 break; // The target decided this was legal after all
3218 // Expand the source, then glue it back together for the call. We must expand
3219 // the source in case it is shared (this pass of legalize must traverse it).
3220 SDOperand SrcLo, SrcHi;
3221 ExpandOp(Source, SrcLo, SrcHi);
3222 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3224 const char *FnName = 0;
3225 if (DestTy == MVT::f32)
3226 FnName = "__floatdisf";
3228 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3229 FnName = "__floatdidf";
3232 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3233 SDOperand UnusedHiPart;
3234 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3237 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3238 /// INT_TO_FP operation of the specified operand when the target requests that
3239 /// we expand it. At this point, we know that the result and operand types are
3240 /// legal for the target.
3241 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3243 MVT::ValueType DestVT) {
3244 if (Op0.getValueType() == MVT::i32) {
3245 // simple 32-bit [signed|unsigned] integer to float/double expansion
3247 // get the stack frame index of a 8 byte buffer
3248 MachineFunction &MF = DAG.getMachineFunction();
3249 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3250 // get address of 8 byte buffer
3251 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3252 // word offset constant for Hi/Lo address computation
3253 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3254 // set up Hi and Lo (into buffer) address based on endian
3256 if (TLI.isLittleEndian()) {
3257 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
3261 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
3263 // if signed map to unsigned space
3264 SDOperand Op0Mapped;
3266 // constant used to invert sign bit (signed to unsigned mapping)
3267 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3268 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3272 // store the lo of the constructed double - based on integer input
3273 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3274 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3275 // initial hi portion of constructed double
3276 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3277 // store the hi of the constructed double - biased exponent
3278 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3279 InitialHi, Hi, DAG.getSrcValue(NULL));
3280 // load the constructed double
3281 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3282 DAG.getSrcValue(NULL));
3283 // FP constant to bias correct the final result
3284 SDOperand Bias = DAG.getConstantFP(isSigned ?
3285 BitsToDouble(0x4330000080000000ULL)
3286 : BitsToDouble(0x4330000000000000ULL),
3288 // subtract the bias
3289 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3292 // handle final rounding
3293 if (DestVT == MVT::f64) {
3297 // if f32 then cast to f32
3298 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3302 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3303 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3305 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3306 DAG.getConstant(0, Op0.getValueType()),
3308 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3309 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3310 SignSet, Four, Zero);
3312 // If the sign bit of the integer is set, the large number will be treated
3313 // as a negative number. To counteract this, the dynamic code adds an
3314 // offset depending on the data type.
3316 switch (Op0.getValueType()) {
3317 default: assert(0 && "Unsupported integer type!");
3318 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3319 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3320 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3321 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3323 if (TLI.isLittleEndian()) FF <<= 32;
3324 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3326 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3327 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3328 SDOperand FudgeInReg;
3329 if (DestVT == MVT::f32)
3330 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3331 DAG.getSrcValue(NULL));
3333 assert(DestVT == MVT::f64 && "Unexpected conversion");
3334 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3335 DAG.getEntryNode(), CPIdx,
3336 DAG.getSrcValue(NULL), MVT::f32));
3339 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3342 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3343 /// *INT_TO_FP operation of the specified operand when the target requests that
3344 /// we promote it. At this point, we know that the result and operand types are
3345 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3346 /// operation that takes a larger input.
3347 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3348 MVT::ValueType DestVT,
3350 // First step, figure out the appropriate *INT_TO_FP operation to use.
3351 MVT::ValueType NewInTy = LegalOp.getValueType();
3353 unsigned OpToUse = 0;
3355 // Scan for the appropriate larger type to use.
3357 NewInTy = (MVT::ValueType)(NewInTy+1);
3358 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
3360 // If the target supports SINT_TO_FP of this type, use it.
3361 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
3363 case TargetLowering::Legal:
3364 if (!TLI.isTypeLegal(NewInTy))
3365 break; // Can't use this datatype.
3367 case TargetLowering::Custom:
3368 OpToUse = ISD::SINT_TO_FP;
3372 if (isSigned) continue;
3374 // If the target supports UINT_TO_FP of this type, use it.
3375 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
3377 case TargetLowering::Legal:
3378 if (!TLI.isTypeLegal(NewInTy))
3379 break; // Can't use this datatype.
3381 case TargetLowering::Custom:
3382 OpToUse = ISD::UINT_TO_FP;
3387 // Otherwise, try a larger type.
3390 // Okay, we found the operation and type to use. Zero extend our input to the
3391 // desired type then run the operation on it.
3392 return DAG.getNode(OpToUse, DestVT,
3393 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3397 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
3398 /// FP_TO_*INT operation of the specified operand when the target requests that
3399 /// we promote it. At this point, we know that the result and operand types are
3400 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
3401 /// operation that returns a larger result.
3402 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
3403 MVT::ValueType DestVT,
3405 // First step, figure out the appropriate FP_TO*INT operation to use.
3406 MVT::ValueType NewOutTy = DestVT;
3408 unsigned OpToUse = 0;
3410 // Scan for the appropriate larger type to use.
3412 NewOutTy = (MVT::ValueType)(NewOutTy+1);
3413 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
3415 // If the target supports FP_TO_SINT returning this type, use it.
3416 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
3418 case TargetLowering::Legal:
3419 if (!TLI.isTypeLegal(NewOutTy))
3420 break; // Can't use this datatype.
3422 case TargetLowering::Custom:
3423 OpToUse = ISD::FP_TO_SINT;
3428 // If the target supports FP_TO_UINT of this type, use it.
3429 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
3431 case TargetLowering::Legal:
3432 if (!TLI.isTypeLegal(NewOutTy))
3433 break; // Can't use this datatype.
3435 case TargetLowering::Custom:
3436 OpToUse = ISD::FP_TO_UINT;
3441 // Otherwise, try a larger type.
3444 // Okay, we found the operation and type to use. Truncate the result of the
3445 // extended FP_TO_*INT operation to the desired size.
3446 return DAG.getNode(ISD::TRUNCATE, DestVT,
3447 DAG.getNode(OpToUse, NewOutTy, LegalOp));
3450 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
3452 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
3453 MVT::ValueType VT = Op.getValueType();
3454 MVT::ValueType SHVT = TLI.getShiftAmountTy();
3455 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
3457 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
3459 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3460 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3461 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
3463 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
3464 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3465 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3466 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
3467 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
3468 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
3469 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
3470 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
3471 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
3473 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
3474 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
3475 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
3476 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
3477 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
3478 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
3479 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
3480 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
3481 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
3482 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
3483 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
3484 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
3485 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
3486 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
3487 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
3488 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
3489 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
3490 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
3491 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
3492 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
3493 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
3497 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
3499 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
3501 default: assert(0 && "Cannot expand this yet!");
3503 static const uint64_t mask[6] = {
3504 0x5555555555555555ULL, 0x3333333333333333ULL,
3505 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
3506 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
3508 MVT::ValueType VT = Op.getValueType();
3509 MVT::ValueType ShVT = TLI.getShiftAmountTy();
3510 unsigned len = getSizeInBits(VT);
3511 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
3512 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
3513 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
3514 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
3515 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
3516 DAG.getNode(ISD::AND, VT,
3517 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
3522 // for now, we do this:
3523 // x = x | (x >> 1);
3524 // x = x | (x >> 2);
3526 // x = x | (x >>16);
3527 // x = x | (x >>32); // for 64-bit input
3528 // return popcount(~x);
3530 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
3531 MVT::ValueType VT = Op.getValueType();
3532 MVT::ValueType ShVT = TLI.getShiftAmountTy();
3533 unsigned len = getSizeInBits(VT);
3534 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
3535 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
3536 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
3538 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
3539 return DAG.getNode(ISD::CTPOP, VT, Op);
3542 // for now, we use: { return popcount(~x & (x - 1)); }
3543 // unless the target has ctlz but not ctpop, in which case we use:
3544 // { return 32 - nlz(~x & (x-1)); }
3545 // see also http://www.hackersdelight.org/HDcode/ntz.cc
3546 MVT::ValueType VT = Op.getValueType();
3547 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
3548 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
3549 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
3550 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
3551 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
3552 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
3553 TLI.isOperationLegal(ISD::CTLZ, VT))
3554 return DAG.getNode(ISD::SUB, VT,
3555 DAG.getConstant(getSizeInBits(VT), VT),
3556 DAG.getNode(ISD::CTLZ, VT, Tmp3));
3557 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
3563 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3564 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3565 /// LegalizeNodes map is filled in for any results that are not expanded, the
3566 /// ExpandedNodes map is filled in for any results that are expanded, and the
3567 /// Lo/Hi values are returned.
3568 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3569 MVT::ValueType VT = Op.getValueType();
3570 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3571 SDNode *Node = Op.Val;
3572 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3573 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3574 "Cannot expand FP values!");
3575 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3576 "Cannot expand to FP value or to larger int value!");
3578 // See if we already expanded it.
3579 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3580 = ExpandedNodes.find(Op);
3581 if (I != ExpandedNodes.end()) {
3582 Lo = I->second.first;
3583 Hi = I->second.second;
3587 switch (Node->getOpcode()) {
3588 case ISD::CopyFromReg:
3589 assert(0 && "CopyFromReg must be legal!");
3591 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3592 assert(0 && "Do not know how to expand this operator!");
3595 Lo = DAG.getNode(ISD::UNDEF, NVT);
3596 Hi = DAG.getNode(ISD::UNDEF, NVT);
3598 case ISD::Constant: {
3599 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3600 Lo = DAG.getConstant(Cst, NVT);
3601 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3604 case ISD::BUILD_PAIR:
3605 // Return the operands.
3606 Lo = Node->getOperand(0);
3607 Hi = Node->getOperand(1);
3610 case ISD::SIGN_EXTEND_INREG:
3611 ExpandOp(Node->getOperand(0), Lo, Hi);
3612 // Sign extend the lo-part.
3613 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3614 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3615 TLI.getShiftAmountTy()));
3616 // sext_inreg the low part if needed.
3617 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3621 ExpandOp(Node->getOperand(0), Lo, Hi);
3622 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
3623 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
3629 ExpandOp(Node->getOperand(0), Lo, Hi);
3630 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3631 DAG.getNode(ISD::CTPOP, NVT, Lo),
3632 DAG.getNode(ISD::CTPOP, NVT, Hi));
3633 Hi = DAG.getConstant(0, NVT);
3637 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3638 ExpandOp(Node->getOperand(0), Lo, Hi);
3639 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3640 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3641 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3643 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3644 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3646 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3647 Hi = DAG.getConstant(0, NVT);
3652 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3653 ExpandOp(Node->getOperand(0), Lo, Hi);
3654 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3655 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3656 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3658 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3659 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3661 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3662 Hi = DAG.getConstant(0, NVT);
3667 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
3668 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
3669 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
3670 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
3672 // Remember that we legalized the chain.
3673 Hi = LegalizeOp(Hi);
3674 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
3675 if (!TLI.isLittleEndian())
3681 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
3682 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
3683 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3685 // Increment the pointer to the other half.
3686 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3687 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3688 getIntPtrConstant(IncrementSize));
3689 // FIXME: This creates a bogus srcvalue!
3690 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3692 // Build a factor node to remember that this load is independent of the
3694 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3697 // Remember that we legalized the chain.
3698 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
3699 if (!TLI.isLittleEndian())
3705 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3706 SDOperand LL, LH, RL, RH;
3707 ExpandOp(Node->getOperand(0), LL, LH);
3708 ExpandOp(Node->getOperand(1), RL, RH);
3709 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3710 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3714 SDOperand LL, LH, RL, RH;
3715 ExpandOp(Node->getOperand(1), LL, LH);
3716 ExpandOp(Node->getOperand(2), RL, RH);
3717 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
3718 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
3721 case ISD::SELECT_CC: {
3722 SDOperand TL, TH, FL, FH;
3723 ExpandOp(Node->getOperand(2), TL, TH);
3724 ExpandOp(Node->getOperand(3), FL, FH);
3725 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3726 Node->getOperand(1), TL, FL, Node->getOperand(4));
3727 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3728 Node->getOperand(1), TH, FH, Node->getOperand(4));
3731 case ISD::SEXTLOAD: {
3732 SDOperand Chain = Node->getOperand(0);
3733 SDOperand Ptr = Node->getOperand(1);
3734 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3737 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3739 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3742 // Remember that we legalized the chain.
3743 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3745 // The high part is obtained by SRA'ing all but one of the bits of the lo
3747 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3748 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3749 TLI.getShiftAmountTy()));
3752 case ISD::ZEXTLOAD: {
3753 SDOperand Chain = Node->getOperand(0);
3754 SDOperand Ptr = Node->getOperand(1);
3755 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3758 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3760 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3763 // Remember that we legalized the chain.
3764 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3766 // The high part is just a zero.
3767 Hi = DAG.getConstant(0, NVT);
3770 case ISD::EXTLOAD: {
3771 SDOperand Chain = Node->getOperand(0);
3772 SDOperand Ptr = Node->getOperand(1);
3773 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3776 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3778 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3781 // Remember that we legalized the chain.
3782 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
3784 // The high part is undefined.
3785 Hi = DAG.getNode(ISD::UNDEF, NVT);
3788 case ISD::ANY_EXTEND:
3789 // The low part is any extension of the input (which degenerates to a copy).
3790 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
3791 // The high part is undefined.
3792 Hi = DAG.getNode(ISD::UNDEF, NVT);
3794 case ISD::SIGN_EXTEND: {
3795 // The low part is just a sign extension of the input (which degenerates to
3797 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
3799 // The high part is obtained by SRA'ing all but one of the bits of the lo
3801 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3802 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3803 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
3806 case ISD::ZERO_EXTEND:
3807 // The low part is just a zero extension of the input (which degenerates to
3809 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3811 // The high part is just a zero.
3812 Hi = DAG.getConstant(0, NVT);
3815 case ISD::BIT_CONVERT: {
3816 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
3817 Node->getOperand(0));
3818 ExpandOp(Tmp, Lo, Hi);
3822 case ISD::READCYCLECOUNTER:
3823 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3824 TargetLowering::Custom &&
3825 "Must custom expand ReadCycleCounter");
3826 Lo = TLI.LowerOperation(Op, DAG);
3827 assert(Lo.Val && "Node must be custom expanded!");
3828 Hi = Lo.getValue(1);
3829 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3830 LegalizeOp(Lo.getValue(2)));
3833 // These operators cannot be expanded directly, emit them as calls to
3834 // library functions.
3835 case ISD::FP_TO_SINT:
3836 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3838 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3839 case Expand: assert(0 && "cannot expand FP!");
3840 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3841 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
3844 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3846 // Now that the custom expander is done, expand the result, which is still
3849 ExpandOp(Op, Lo, Hi);
3854 if (Node->getOperand(0).getValueType() == MVT::f32)
3855 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3857 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3860 case ISD::FP_TO_UINT:
3861 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3863 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3864 case Expand: assert(0 && "cannot expand FP!");
3865 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3866 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
3869 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
3871 // Now that the custom expander is done, expand the result.
3873 ExpandOp(Op, Lo, Hi);
3878 if (Node->getOperand(0).getValueType() == MVT::f32)
3879 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3881 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3885 // If the target wants custom lowering, do so.
3886 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
3887 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3888 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
3889 Op = TLI.LowerOperation(Op, DAG);
3891 // Now that the custom expander is done, expand the result, which is
3893 ExpandOp(Op, Lo, Hi);
3898 // If we can emit an efficient shift operation, do so now.
3899 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
3902 // If this target supports SHL_PARTS, use it.
3903 TargetLowering::LegalizeAction Action =
3904 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
3905 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3906 Action == TargetLowering::Custom) {
3907 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
3911 // Otherwise, emit a libcall.
3912 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3917 // If the target wants custom lowering, do so.
3918 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
3919 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3920 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
3921 Op = TLI.LowerOperation(Op, DAG);
3923 // Now that the custom expander is done, expand the result, which is
3925 ExpandOp(Op, Lo, Hi);
3930 // If we can emit an efficient shift operation, do so now.
3931 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
3934 // If this target supports SRA_PARTS, use it.
3935 TargetLowering::LegalizeAction Action =
3936 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
3937 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3938 Action == TargetLowering::Custom) {
3939 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
3943 // Otherwise, emit a libcall.
3944 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3949 // If the target wants custom lowering, do so.
3950 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
3951 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3952 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
3953 Op = TLI.LowerOperation(Op, DAG);
3955 // Now that the custom expander is done, expand the result, which is
3957 ExpandOp(Op, Lo, Hi);
3962 // If we can emit an efficient shift operation, do so now.
3963 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
3966 // If this target supports SRL_PARTS, use it.
3967 TargetLowering::LegalizeAction Action =
3968 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
3969 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
3970 Action == TargetLowering::Custom) {
3971 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
3975 // Otherwise, emit a libcall.
3976 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3982 // If the target wants to custom expand this, let them.
3983 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
3984 TargetLowering::Custom) {
3985 Op = TLI.LowerOperation(Op, DAG);
3987 ExpandOp(Op, Lo, Hi);
3992 // Expand the subcomponents.
3993 SDOperand LHSL, LHSH, RHSL, RHSH;
3994 ExpandOp(Node->getOperand(0), LHSL, LHSH);
3995 ExpandOp(Node->getOperand(1), RHSL, RHSH);
3996 std::vector<MVT::ValueType> VTs;
3997 std::vector<SDOperand> LoOps, HiOps;
3998 VTs.push_back(LHSL.getValueType());
3999 VTs.push_back(MVT::Flag);
4000 LoOps.push_back(LHSL);
4001 LoOps.push_back(RHSL);
4002 HiOps.push_back(LHSH);
4003 HiOps.push_back(RHSH);
4004 if (Node->getOpcode() == ISD::ADD) {
4005 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
4006 HiOps.push_back(Lo.getValue(1));
4007 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
4009 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
4010 HiOps.push_back(Lo.getValue(1));
4011 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
4016 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4017 SDOperand LL, LH, RL, RH;
4018 ExpandOp(Node->getOperand(0), LL, LH);
4019 ExpandOp(Node->getOperand(1), RL, RH);
4020 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4021 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4022 // extended the sign bit of the low half through the upper half, and if so
4023 // emit a MULHS instead of the alternate sequence that is valid for any
4024 // i64 x i64 multiply.
4025 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4026 // is RH an extension of the sign bit of RL?
4027 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4028 RH.getOperand(1).getOpcode() == ISD::Constant &&
4029 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4030 // is LH an extension of the sign bit of LL?
4031 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4032 LH.getOperand(1).getOpcode() == ISD::Constant &&
4033 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4034 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4036 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4037 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4038 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4039 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4040 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4042 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4044 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4048 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4049 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4050 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4051 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4054 // Make sure the resultant values have been legalized themselves, unless this
4055 // is a type that requires multi-step expansion.
4056 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4057 Lo = LegalizeOp(Lo);
4058 Hi = LegalizeOp(Hi);
4061 // Remember in a map if the values will be reused later.
4063 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4064 assert(isNew && "Value already expanded?!?");
4067 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4068 /// two smaller values of MVT::Vector type.
4069 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4071 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4072 SDNode *Node = Op.Val;
4073 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4074 assert(NumElements > 1 && "Cannot split a single element vector!");
4075 unsigned NewNumElts = NumElements/2;
4076 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4077 SDOperand TypeNode = *(Node->op_end()-1);
4079 // See if we already split it.
4080 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4081 = SplitNodes.find(Op);
4082 if (I != SplitNodes.end()) {
4083 Lo = I->second.first;
4084 Hi = I->second.second;
4088 switch (Node->getOpcode()) {
4089 default: assert(0 && "Unknown vector operation!");
4090 case ISD::VBUILD_VECTOR: {
4091 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
4092 LoOps.push_back(NewNumEltsNode);
4093 LoOps.push_back(TypeNode);
4094 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
4096 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
4097 HiOps.push_back(NewNumEltsNode);
4098 HiOps.push_back(TypeNode);
4099 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
4110 SDOperand LL, LH, RL, RH;
4111 SplitVectorOp(Node->getOperand(0), LL, LH);
4112 SplitVectorOp(Node->getOperand(1), RL, RH);
4114 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4115 NewNumEltsNode, TypeNode);
4116 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4117 NewNumEltsNode, TypeNode);
4121 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4122 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4123 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4125 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4126 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4127 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4128 getIntPtrConstant(IncrementSize));
4129 // FIXME: This creates a bogus srcvalue!
4130 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4132 // Build a factor node to remember that this load is independent of the
4134 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4137 // Remember that we legalized the chain.
4138 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4139 if (!TLI.isLittleEndian())
4145 // Remember in a map if the values will be reused later.
4147 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4148 assert(isNew && "Value already expanded?!?");
4152 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4153 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4154 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4155 /// type for the result.
4156 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4157 MVT::ValueType NewVT) {
4158 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4159 SDNode *Node = Op.Val;
4161 // See if we already packed it.
4162 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4163 if (I != PackedNodes.end()) return I->second;
4166 switch (Node->getOpcode()) {
4168 Node->dump(); std::cerr << "\n";
4169 assert(0 && "Unknown vector operation in PackVectorOp!");
4178 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4180 PackVectorOp(Node->getOperand(0), NewVT),
4181 PackVectorOp(Node->getOperand(1), NewVT));
4184 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4185 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4187 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4189 // Remember that we legalized the chain.
4190 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4193 case ISD::VBUILD_VECTOR:
4194 if (!MVT::isVector(NewVT)) {
4195 // Returning a scalar?
4196 Result = Node->getOperand(0);
4198 // Returning a BUILD_VECTOR?
4199 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
4200 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
4203 case ISD::VINSERT_VECTOR_ELT:
4204 if (!MVT::isVector(NewVT)) {
4205 // Returning a scalar? Must be the inserted element.
4206 Result = Node->getOperand(1);
4208 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4209 PackVectorOp(Node->getOperand(0), NewVT),
4210 Node->getOperand(1), Node->getOperand(2));
4215 if (TLI.isTypeLegal(NewVT))
4216 Result = LegalizeOp(Result);
4217 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4218 assert(isNew && "Value already packed?");
4223 // SelectionDAG::Legalize - This is the entry point for the file.
4225 void SelectionDAG::Legalize() {
4226 /// run - This is the main entry point to this class.
4228 SelectionDAGLegalize(*this).LegalizeDAG();