1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineJumpTableInfo.h"
19 #include "llvm/CodeGen/MachineModuleInfo.h"
20 #include "llvm/CodeGen/PseudoSourceValue.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/Function.h"
31 #include "llvm/GlobalVariable.h"
32 #include "llvm/LLVMContext.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/ADT/DenseMap.h"
39 #include "llvm/ADT/SmallVector.h"
40 #include "llvm/ADT/SmallPtrSet.h"
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class SelectionDAGLegalize {
57 const TargetMachine &TM;
58 const TargetLowering &TLI;
60 CodeGenOpt::Level OptLevel;
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDValue LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDValue, SDValue> LegalizedNodes;
90 void AddLegalizedOperand(SDValue From, SDValue To) {
91 LegalizedNodes.insert(std::make_pair(From, To));
92 // If someone requests legalization of the new node, return itself.
94 LegalizedNodes.insert(std::make_pair(To, To));
98 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
100 /// getTypeAction - Return how we should legalize values of this type, either
101 /// it is already legal or we need to expand it into multiple registers of
102 /// smaller integer type, or we need to promote it to a larger type.
103 LegalizeAction getTypeAction(EVT VT) const {
104 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
107 /// isTypeLegal - Return true if this type is legal on this target.
109 bool isTypeLegal(EVT VT) const {
110 return getTypeAction(VT) == Legal;
116 /// LegalizeOp - We know that the specified value has a legal type.
117 /// Recursively ensure that the operands have legal types, then return the
119 SDValue LegalizeOp(SDValue O);
121 SDValue OptimizeFloatStore(StoreSDNode *ST);
123 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
124 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
125 /// is necessary to spill the vector being inserted into to memory, perform
126 /// the insert there, and then read the result back.
127 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
129 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
130 SDValue Idx, DebugLoc dl);
132 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
133 /// performs the same shuffe in terms of order or result bytes, but on a type
134 /// whose vector element type is narrower than the original shuffle type.
135 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
136 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
137 SDValue N1, SDValue N2,
138 SmallVectorImpl<int> &Mask) const;
140 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
141 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
143 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
146 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
147 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
148 SDNode *Node, bool isSigned);
149 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
150 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
151 RTLIB::Libcall Call_PPCF128);
152 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
153 RTLIB::Libcall Call_I8,
154 RTLIB::Libcall Call_I16,
155 RTLIB::Libcall Call_I32,
156 RTLIB::Libcall Call_I64,
157 RTLIB::Libcall Call_I128);
159 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
160 SDValue ExpandBUILD_VECTOR(SDNode *Node);
161 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
162 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
163 SmallVectorImpl<SDValue> &Results);
164 SDValue ExpandFCOPYSIGN(SDNode *Node);
165 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
167 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
169 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
172 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
173 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
175 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
176 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
178 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
180 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
181 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
185 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
186 /// performs the same shuffe in terms of order or result bytes, but on a type
187 /// whose vector element type is narrower than the original shuffle type.
188 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
190 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
191 SDValue N1, SDValue N2,
192 SmallVectorImpl<int> &Mask) const {
193 unsigned NumMaskElts = VT.getVectorNumElements();
194 unsigned NumDestElts = NVT.getVectorNumElements();
195 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
197 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
199 if (NumEltsGrowth == 1)
200 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
202 SmallVector<int, 8> NewMask;
203 for (unsigned i = 0; i != NumMaskElts; ++i) {
205 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
207 NewMask.push_back(-1);
209 NewMask.push_back(Idx * NumEltsGrowth + j);
212 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
213 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
214 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
217 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
218 CodeGenOpt::Level ol)
219 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
220 DAG(dag), OptLevel(ol),
221 ValueTypeActions(TLI.getValueTypeActions()) {
222 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
223 "Too many value types for ValueTypeActions to hold!");
226 void SelectionDAGLegalize::LegalizeDAG() {
227 LastCALLSEQ_END = DAG.getEntryNode();
228 IsLegalizingCall = false;
230 // The legalize process is inherently a bottom-up recursive process (users
231 // legalize their uses before themselves). Given infinite stack space, we
232 // could just start legalizing on the root and traverse the whole graph. In
233 // practice however, this causes us to run out of stack space on large basic
234 // blocks. To avoid this problem, compute an ordering of the nodes where each
235 // node is only legalized after all of its operands are legalized.
236 DAG.AssignTopologicalOrder();
237 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
238 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
239 LegalizeOp(SDValue(I, 0));
241 // Finally, it's possible the root changed. Get the new root.
242 SDValue OldRoot = DAG.getRoot();
243 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
244 DAG.setRoot(LegalizedNodes[OldRoot]);
246 LegalizedNodes.clear();
248 // Remove dead nodes now.
249 DAG.RemoveDeadNodes();
253 /// FindCallEndFromCallStart - Given a chained node that is part of a call
254 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
255 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
256 if (Node->getOpcode() == ISD::CALLSEQ_END)
258 if (Node->use_empty())
259 return 0; // No CallSeqEnd
261 // The chain is usually at the end.
262 SDValue TheChain(Node, Node->getNumValues()-1);
263 if (TheChain.getValueType() != MVT::Other) {
264 // Sometimes it's at the beginning.
265 TheChain = SDValue(Node, 0);
266 if (TheChain.getValueType() != MVT::Other) {
267 // Otherwise, hunt for it.
268 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
269 if (Node->getValueType(i) == MVT::Other) {
270 TheChain = SDValue(Node, i);
274 // Otherwise, we walked into a node without a chain.
275 if (TheChain.getValueType() != MVT::Other)
280 for (SDNode::use_iterator UI = Node->use_begin(),
281 E = Node->use_end(); UI != E; ++UI) {
283 // Make sure to only follow users of our token chain.
285 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
286 if (User->getOperand(i) == TheChain)
287 if (SDNode *Result = FindCallEndFromCallStart(User))
293 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
294 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
295 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
296 assert(Node && "Didn't find callseq_start for a call??");
297 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
299 assert(Node->getOperand(0).getValueType() == MVT::Other &&
300 "Node doesn't have a token chain argument!");
301 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
304 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
305 /// see if any uses can reach Dest. If no dest operands can get to dest,
306 /// legalize them, legalize ourself, and return false, otherwise, return true.
308 /// Keep track of the nodes we fine that actually do lead to Dest in
309 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
311 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
312 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
313 if (N == Dest) return true; // N certainly leads to Dest :)
315 // If we've already processed this node and it does lead to Dest, there is no
316 // need to reprocess it.
317 if (NodesLeadingTo.count(N)) return true;
319 // If the first result of this node has been already legalized, then it cannot
321 if (LegalizedNodes.count(SDValue(N, 0))) return false;
323 // Okay, this node has not already been legalized. Check and legalize all
324 // operands. If none lead to Dest, then we can legalize this node.
325 bool OperandsLeadToDest = false;
326 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
327 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
328 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
331 if (OperandsLeadToDest) {
332 NodesLeadingTo.insert(N);
336 // Okay, this node looks safe, legalize it and return false.
337 LegalizeOp(SDValue(N, 0));
341 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
342 /// a load from the constant pool.
343 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
344 SelectionDAG &DAG, const TargetLowering &TLI) {
346 DebugLoc dl = CFP->getDebugLoc();
348 // If a FP immediate is precise when represented as a float and if the
349 // target can do an extending load from float to double, we put it into
350 // the constant pool as a float, even if it's is statically typed as a
351 // double. This shrinks FP constants and canonicalizes them for targets where
352 // an FP extending load is the same cost as a normal load (such as on the x87
353 // fp stack or PPC FP unit).
354 EVT VT = CFP->getValueType(0);
355 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
357 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
358 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
359 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
364 while (SVT != MVT::f32) {
365 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
366 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
367 // Only do this if the target has a native EXTLOAD instruction from
369 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
370 TLI.ShouldShrinkFPConstant(OrigVT)) {
371 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
372 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
378 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
379 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
381 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, dl,
383 CPIdx, MachinePointerInfo::getConstantPool(),
384 VT, false, false, Alignment);
385 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
386 MachinePointerInfo::getConstantPool(), false, false,
390 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
392 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
393 const TargetLowering &TLI) {
394 SDValue Chain = ST->getChain();
395 SDValue Ptr = ST->getBasePtr();
396 SDValue Val = ST->getValue();
397 EVT VT = Val.getValueType();
398 int Alignment = ST->getAlignment();
399 DebugLoc dl = ST->getDebugLoc();
400 if (ST->getMemoryVT().isFloatingPoint() ||
401 ST->getMemoryVT().isVector()) {
402 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
403 if (TLI.isTypeLegal(intVT)) {
404 // Expand to a bitconvert of the value to the integer type of the
405 // same size, then a (misaligned) int store.
406 // FIXME: Does not handle truncating floating point stores!
407 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
408 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
409 ST->isVolatile(), ST->isNonTemporal(), Alignment);
411 // Do a (aligned) store to a stack slot, then copy from the stack slot
412 // to the final destination using (unaligned) integer loads and stores.
413 EVT StoredVT = ST->getMemoryVT();
415 TLI.getRegisterType(*DAG.getContext(),
416 EVT::getIntegerVT(*DAG.getContext(),
417 StoredVT.getSizeInBits()));
418 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
419 unsigned RegBytes = RegVT.getSizeInBits() / 8;
420 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
422 // Make sure the stack slot is also aligned for the register type.
423 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
425 // Perform the original store, only redirected to the stack slot.
426 SDValue Store = DAG.getTruncStore(Chain, dl,
427 Val, StackPtr, MachinePointerInfo(),
428 StoredVT, false, false, 0);
429 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
430 SmallVector<SDValue, 8> Stores;
433 // Do all but one copies using the full register width.
434 for (unsigned i = 1; i < NumRegs; i++) {
435 // Load one integer register's worth from the stack slot.
436 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
437 MachinePointerInfo(),
439 // Store it to the final location. Remember the store.
440 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
441 ST->getPointerInfo().getWithOffset(Offset),
442 ST->isVolatile(), ST->isNonTemporal(),
443 MinAlign(ST->getAlignment(), Offset)));
444 // Increment the pointers.
446 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
448 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
451 // The last store may be partial. Do a truncating store. On big-endian
452 // machines this requires an extending load from the stack slot to ensure
453 // that the bits are in the right place.
454 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
455 8 * (StoredBytes - Offset));
457 // Load from the stack slot.
458 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Store, StackPtr,
459 MachinePointerInfo(),
460 MemVT, false, false, 0);
462 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
464 .getWithOffset(Offset),
465 MemVT, ST->isVolatile(),
467 MinAlign(ST->getAlignment(), Offset)));
468 // The order of the stores doesn't matter - say it with a TokenFactor.
469 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
473 assert(ST->getMemoryVT().isInteger() &&
474 !ST->getMemoryVT().isVector() &&
475 "Unaligned store of unknown type.");
476 // Get the half-size VT
477 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
478 int NumBits = NewStoredVT.getSizeInBits();
479 int IncrementSize = NumBits / 8;
481 // Divide the stored value in two parts.
482 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
484 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
486 // Store the two parts
487 SDValue Store1, Store2;
488 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
489 ST->getPointerInfo(), NewStoredVT,
490 ST->isVolatile(), ST->isNonTemporal(), Alignment);
491 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
492 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
493 Alignment = MinAlign(Alignment, IncrementSize);
494 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
495 ST->getPointerInfo().getWithOffset(IncrementSize),
496 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
499 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
502 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
504 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
505 const TargetLowering &TLI) {
506 SDValue Chain = LD->getChain();
507 SDValue Ptr = LD->getBasePtr();
508 EVT VT = LD->getValueType(0);
509 EVT LoadedVT = LD->getMemoryVT();
510 DebugLoc dl = LD->getDebugLoc();
511 if (VT.isFloatingPoint() || VT.isVector()) {
512 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
513 if (TLI.isTypeLegal(intVT)) {
514 // Expand to a (misaligned) integer load of the same size,
515 // then bitconvert to floating point or vector.
516 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
518 LD->isNonTemporal(), LD->getAlignment());
519 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
520 if (VT.isFloatingPoint() && LoadedVT != VT)
521 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
523 SDValue Ops[] = { Result, Chain };
524 return DAG.getMergeValues(Ops, 2, dl);
527 // Copy the value to a (aligned) stack slot using (unaligned) integer
528 // loads and stores, then do a (aligned) load from the stack slot.
529 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
530 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
531 unsigned RegBytes = RegVT.getSizeInBits() / 8;
532 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
534 // Make sure the stack slot is also aligned for the register type.
535 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
537 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
538 SmallVector<SDValue, 8> Stores;
539 SDValue StackPtr = StackBase;
542 // Do all but one copies using the full register width.
543 for (unsigned i = 1; i < NumRegs; i++) {
544 // Load one integer register's worth from the original location.
545 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
546 LD->getPointerInfo().getWithOffset(Offset),
547 LD->isVolatile(), LD->isNonTemporal(),
548 MinAlign(LD->getAlignment(), Offset));
549 // Follow the load with a store to the stack slot. Remember the store.
550 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
551 MachinePointerInfo(), false, false, 0));
552 // Increment the pointers.
554 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
555 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
559 // The last copy may be partial. Do an extending load.
560 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
561 8 * (LoadedBytes - Offset));
562 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, dl, Chain, Ptr,
563 LD->getPointerInfo().getWithOffset(Offset),
564 MemVT, LD->isVolatile(),
566 MinAlign(LD->getAlignment(), Offset));
567 // Follow the load with a store to the stack slot. Remember the store.
568 // On big-endian machines this requires a truncating store to ensure
569 // that the bits end up in the right place.
570 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
571 MachinePointerInfo(), MemVT,
574 // The order of the stores doesn't matter - say it with a TokenFactor.
575 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
578 // Finally, perform the original load only redirected to the stack slot.
579 Load = DAG.getExtLoad(LD->getExtensionType(), VT, dl, TF, StackBase,
580 MachinePointerInfo(), LoadedVT, false, false, 0);
582 // Callers expect a MERGE_VALUES node.
583 SDValue Ops[] = { Load, TF };
584 return DAG.getMergeValues(Ops, 2, dl);
586 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
587 "Unaligned load of unsupported type.");
589 // Compute the new VT that is half the size of the old one. This is an
591 unsigned NumBits = LoadedVT.getSizeInBits();
593 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
596 unsigned Alignment = LD->getAlignment();
597 unsigned IncrementSize = NumBits / 8;
598 ISD::LoadExtType HiExtType = LD->getExtensionType();
600 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
601 if (HiExtType == ISD::NON_EXTLOAD)
602 HiExtType = ISD::ZEXTLOAD;
604 // Load the value in two parts
606 if (TLI.isLittleEndian()) {
607 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr, LD->getPointerInfo(),
608 NewLoadedVT, LD->isVolatile(),
609 LD->isNonTemporal(), Alignment);
610 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
611 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
612 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr,
613 LD->getPointerInfo().getWithOffset(IncrementSize),
614 NewLoadedVT, LD->isVolatile(),
615 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
617 Hi = DAG.getExtLoad(HiExtType, VT, dl, Chain, Ptr, LD->getPointerInfo(),
618 NewLoadedVT, LD->isVolatile(),
619 LD->isNonTemporal(), Alignment);
620 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
621 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
622 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, dl, Chain, Ptr,
623 LD->getPointerInfo().getWithOffset(IncrementSize),
624 NewLoadedVT, LD->isVolatile(),
625 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
628 // aggregate the two parts
629 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
630 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
631 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
633 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
636 SDValue Ops[] = { Result, TF };
637 return DAG.getMergeValues(Ops, 2, dl);
640 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
641 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
642 /// is necessary to spill the vector being inserted into to memory, perform
643 /// the insert there, and then read the result back.
644 SDValue SelectionDAGLegalize::
645 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
651 // If the target doesn't support this, we have to spill the input vector
652 // to a temporary stack slot, update the element, then reload it. This is
653 // badness. We could also load the value into a vector register (either
654 // with a "move to register" or "extload into register" instruction, then
655 // permute it into place, if the idx is a constant and if the idx is
656 // supported by the target.
657 EVT VT = Tmp1.getValueType();
658 EVT EltVT = VT.getVectorElementType();
659 EVT IdxVT = Tmp3.getValueType();
660 EVT PtrVT = TLI.getPointerTy();
661 SDValue StackPtr = DAG.CreateStackTemporary(VT);
663 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
666 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
667 MachinePointerInfo::getFixedStack(SPFI),
670 // Truncate or zero extend offset to target pointer type.
671 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
672 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
673 // Add the offset to the index.
674 unsigned EltSize = EltVT.getSizeInBits()/8;
675 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
676 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
677 // Store the scalar value.
678 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
680 // Load the updated vector.
681 return DAG.getLoad(VT, dl, Ch, StackPtr,
682 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
686 SDValue SelectionDAGLegalize::
687 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
688 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
689 // SCALAR_TO_VECTOR requires that the type of the value being inserted
690 // match the element type of the vector being created, except for
691 // integers in which case the inserted value can be over width.
692 EVT EltVT = Vec.getValueType().getVectorElementType();
693 if (Val.getValueType() == EltVT ||
694 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
695 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
696 Vec.getValueType(), Val);
698 unsigned NumElts = Vec.getValueType().getVectorNumElements();
699 // We generate a shuffle of InVec and ScVec, so the shuffle mask
700 // should be 0,1,2,3,4,5... with the appropriate element replaced with
702 SmallVector<int, 8> ShufOps;
703 for (unsigned i = 0; i != NumElts; ++i)
704 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
706 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
710 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
713 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
714 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
715 // FIXME: We shouldn't do this for TargetConstantFP's.
716 // FIXME: move this to the DAG Combiner! Note that we can't regress due
717 // to phase ordering between legalized code and the dag combiner. This
718 // probably means that we need to integrate dag combiner and legalizer
720 // We generally can't do this one for long doubles.
721 SDValue Tmp1 = ST->getChain();
722 SDValue Tmp2 = ST->getBasePtr();
724 unsigned Alignment = ST->getAlignment();
725 bool isVolatile = ST->isVolatile();
726 bool isNonTemporal = ST->isNonTemporal();
727 DebugLoc dl = ST->getDebugLoc();
728 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
729 if (CFP->getValueType(0) == MVT::f32 &&
730 getTypeAction(MVT::i32) == Legal) {
731 Tmp3 = DAG.getConstant(CFP->getValueAPF().
732 bitcastToAPInt().zextOrTrunc(32),
734 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
735 isVolatile, isNonTemporal, Alignment);
738 if (CFP->getValueType(0) == MVT::f64) {
739 // If this target supports 64-bit registers, do a single 64-bit store.
740 if (getTypeAction(MVT::i64) == Legal) {
741 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
742 zextOrTrunc(64), MVT::i64);
743 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
744 isVolatile, isNonTemporal, Alignment);
747 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
748 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
749 // stores. If the target supports neither 32- nor 64-bits, this
750 // xform is certainly not worth it.
751 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
752 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
753 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
754 if (TLI.isBigEndian()) std::swap(Lo, Hi);
756 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
757 isNonTemporal, Alignment);
758 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
759 DAG.getIntPtrConstant(4));
760 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
761 ST->getPointerInfo().getWithOffset(4),
762 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
764 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
771 /// LegalizeOp - We know that the specified value has a legal type, and
772 /// that its operands are legal. Now ensure that the operation itself
773 /// is legal, recursively ensuring that the operands' operations remain
775 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
776 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
779 SDNode *Node = Op.getNode();
780 DebugLoc dl = Node->getDebugLoc();
782 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
783 assert(getTypeAction(Node->getValueType(i)) == Legal &&
784 "Unexpected illegal type!");
786 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
787 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
788 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
789 "Unexpected illegal type!");
791 // Note that LegalizeOp may be reentered even from single-use nodes, which
792 // means that we always must cache transformed nodes.
793 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
794 if (I != LegalizedNodes.end()) return I->second;
796 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
798 bool isCustom = false;
800 // Figure out the correct action; the way to query this varies by opcode
801 TargetLowering::LegalizeAction Action;
802 bool SimpleFinishLegalizing = true;
803 switch (Node->getOpcode()) {
804 case ISD::INTRINSIC_W_CHAIN:
805 case ISD::INTRINSIC_WO_CHAIN:
806 case ISD::INTRINSIC_VOID:
809 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
811 case ISD::SINT_TO_FP:
812 case ISD::UINT_TO_FP:
813 case ISD::EXTRACT_VECTOR_ELT:
814 Action = TLI.getOperationAction(Node->getOpcode(),
815 Node->getOperand(0).getValueType());
817 case ISD::FP_ROUND_INREG:
818 case ISD::SIGN_EXTEND_INREG: {
819 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
820 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
826 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
827 Node->getOpcode() == ISD::SETCC ? 2 : 1;
828 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
829 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
830 ISD::CondCode CCCode =
831 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
832 Action = TLI.getCondCodeAction(CCCode, OpVT);
833 if (Action == TargetLowering::Legal) {
834 if (Node->getOpcode() == ISD::SELECT_CC)
835 Action = TLI.getOperationAction(Node->getOpcode(),
836 Node->getValueType(0));
838 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
844 // FIXME: Model these properly. LOAD and STORE are complicated, and
845 // STORE expects the unlegalized operand in some cases.
846 SimpleFinishLegalizing = false;
848 case ISD::CALLSEQ_START:
849 case ISD::CALLSEQ_END:
850 // FIXME: This shouldn't be necessary. These nodes have special properties
851 // dealing with the recursive nature of legalization. Removing this
852 // special case should be done as part of making LegalizeDAG non-recursive.
853 SimpleFinishLegalizing = false;
855 case ISD::EXTRACT_ELEMENT:
856 case ISD::FLT_ROUNDS_:
864 case ISD::MERGE_VALUES:
866 case ISD::FRAME_TO_ARGS_OFFSET:
867 case ISD::EH_SJLJ_SETJMP:
868 case ISD::EH_SJLJ_LONGJMP:
869 case ISD::EH_SJLJ_DISPATCHSETUP:
870 // These operations lie about being legal: when they claim to be legal,
871 // they should actually be expanded.
872 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
873 if (Action == TargetLowering::Legal)
874 Action = TargetLowering::Expand;
876 case ISD::TRAMPOLINE:
878 case ISD::RETURNADDR:
879 // These operations lie about being legal: when they claim to be legal,
880 // they should actually be custom-lowered.
881 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
882 if (Action == TargetLowering::Legal)
883 Action = TargetLowering::Custom;
885 case ISD::BUILD_VECTOR:
886 // A weird case: legalization for BUILD_VECTOR never legalizes the
888 // FIXME: This really sucks... changing it isn't semantically incorrect,
889 // but it massively pessimizes the code for floating-point BUILD_VECTORs
890 // because ConstantFP operands get legalized into constant pool loads
891 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
892 // though, because BUILD_VECTORS usually get lowered into other nodes
893 // which get legalized properly.
894 SimpleFinishLegalizing = false;
897 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
898 Action = TargetLowering::Legal;
900 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
905 if (SimpleFinishLegalizing) {
906 SmallVector<SDValue, 8> Ops, ResultVals;
907 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
908 Ops.push_back(LegalizeOp(Node->getOperand(i)));
909 switch (Node->getOpcode()) {
916 // Branches tweak the chain to include LastCALLSEQ_END
917 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
919 Ops[0] = LegalizeOp(Ops[0]);
920 LastCALLSEQ_END = DAG.getEntryNode();
927 // Legalizing shifts/rotates requires adjusting the shift amount
928 // to the appropriate width.
929 if (!Ops[1].getValueType().isVector())
930 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
935 // Legalizing shifts/rotates requires adjusting the shift amount
936 // to the appropriate width.
937 if (!Ops[2].getValueType().isVector())
938 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
942 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
945 case TargetLowering::Legal:
946 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
947 ResultVals.push_back(Result.getValue(i));
949 case TargetLowering::Custom:
950 // FIXME: The handling for custom lowering with multiple results is
952 Tmp1 = TLI.LowerOperation(Result, DAG);
953 if (Tmp1.getNode()) {
954 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
956 ResultVals.push_back(Tmp1);
958 ResultVals.push_back(Tmp1.getValue(i));
964 case TargetLowering::Expand:
965 ExpandNode(Result.getNode(), ResultVals);
967 case TargetLowering::Promote:
968 PromoteNode(Result.getNode(), ResultVals);
971 if (!ResultVals.empty()) {
972 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
973 if (ResultVals[i] != SDValue(Node, i))
974 ResultVals[i] = LegalizeOp(ResultVals[i]);
975 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
977 return ResultVals[Op.getResNo()];
981 switch (Node->getOpcode()) {
988 assert(0 && "Do not know how to legalize this operator!");
990 case ISD::BUILD_VECTOR:
991 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
992 default: assert(0 && "This action is not supported yet!");
993 case TargetLowering::Custom:
994 Tmp3 = TLI.LowerOperation(Result, DAG);
995 if (Tmp3.getNode()) {
1000 case TargetLowering::Expand:
1001 Result = ExpandBUILD_VECTOR(Result.getNode());
1005 case ISD::CALLSEQ_START: {
1006 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1008 // Recursively Legalize all of the inputs of the call end that do not lead
1009 // to this call start. This ensures that any libcalls that need be inserted
1010 // are inserted *before* the CALLSEQ_START.
1011 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1012 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1013 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1017 // Now that we have legalized all of the inputs (which may have inserted
1018 // libcalls), create the new CALLSEQ_START node.
1019 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1021 // Merge in the last call to ensure that this call starts after the last
1023 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1024 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1025 Tmp1, LastCALLSEQ_END);
1026 Tmp1 = LegalizeOp(Tmp1);
1029 // Do not try to legalize the target-specific arguments (#1+).
1030 if (Tmp1 != Node->getOperand(0)) {
1031 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1033 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1034 Ops.size()), Result.getResNo());
1037 // Remember that the CALLSEQ_START is legalized.
1038 AddLegalizedOperand(Op.getValue(0), Result);
1039 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1040 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1042 // Now that the callseq_start and all of the non-call nodes above this call
1043 // sequence have been legalized, legalize the call itself. During this
1044 // process, no libcalls can/will be inserted, guaranteeing that no calls
1046 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1047 // Note that we are selecting this call!
1048 LastCALLSEQ_END = SDValue(CallEnd, 0);
1049 IsLegalizingCall = true;
1051 // Legalize the call, starting from the CALLSEQ_END.
1052 LegalizeOp(LastCALLSEQ_END);
1053 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1056 case ISD::CALLSEQ_END:
1057 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1058 // will cause this node to be legalized as well as handling libcalls right.
1059 if (LastCALLSEQ_END.getNode() != Node) {
1060 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1061 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1062 assert(I != LegalizedNodes.end() &&
1063 "Legalizing the call start should have legalized this node!");
1067 // Otherwise, the call start has been legalized and everything is going
1068 // according to plan. Just legalize ourselves normally here.
1069 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1070 // Do not try to legalize the target-specific arguments (#1+), except for
1071 // an optional flag input.
1072 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1073 if (Tmp1 != Node->getOperand(0)) {
1074 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1076 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1077 &Ops[0], Ops.size()),
1081 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1082 if (Tmp1 != Node->getOperand(0) ||
1083 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1084 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1087 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1088 &Ops[0], Ops.size()),
1092 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1093 // This finishes up call legalization.
1094 IsLegalizingCall = false;
1096 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1097 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1098 if (Node->getNumValues() == 2)
1099 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1100 return Result.getValue(Op.getResNo());
1102 LoadSDNode *LD = cast<LoadSDNode>(Node);
1103 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1104 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1106 ISD::LoadExtType ExtType = LD->getExtensionType();
1107 if (ExtType == ISD::NON_EXTLOAD) {
1108 EVT VT = Node->getValueType(0);
1109 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1110 Tmp1, Tmp2, LD->getOffset()),
1112 Tmp3 = Result.getValue(0);
1113 Tmp4 = Result.getValue(1);
1115 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1116 default: assert(0 && "This action is not supported yet!");
1117 case TargetLowering::Legal:
1118 // If this is an unaligned load and the target doesn't support it,
1120 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1121 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1122 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1123 if (LD->getAlignment() < ABIAlignment){
1124 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1126 Tmp3 = Result.getOperand(0);
1127 Tmp4 = Result.getOperand(1);
1128 Tmp3 = LegalizeOp(Tmp3);
1129 Tmp4 = LegalizeOp(Tmp4);
1133 case TargetLowering::Custom:
1134 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1135 if (Tmp1.getNode()) {
1136 Tmp3 = LegalizeOp(Tmp1);
1137 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1140 case TargetLowering::Promote: {
1141 // Only promote a load of vector type to another.
1142 assert(VT.isVector() && "Cannot promote this load!");
1143 // Change base type to a different vector type.
1144 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1146 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1147 LD->isVolatile(), LD->isNonTemporal(),
1148 LD->getAlignment());
1149 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1150 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1154 // Since loads produce two values, make sure to remember that we
1155 // legalized both of them.
1156 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1157 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1158 return Op.getResNo() ? Tmp4 : Tmp3;
1161 EVT SrcVT = LD->getMemoryVT();
1162 unsigned SrcWidth = SrcVT.getSizeInBits();
1163 unsigned Alignment = LD->getAlignment();
1164 bool isVolatile = LD->isVolatile();
1165 bool isNonTemporal = LD->isNonTemporal();
1167 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1168 // Some targets pretend to have an i1 loading operation, and actually
1169 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1170 // bits are guaranteed to be zero; it helps the optimizers understand
1171 // that these bits are zero. It is also useful for EXTLOAD, since it
1172 // tells the optimizers that those bits are undefined. It would be
1173 // nice to have an effective generic way of getting these benefits...
1174 // Until such a way is found, don't insist on promoting i1 here.
1175 (SrcVT != MVT::i1 ||
1176 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1177 // Promote to a byte-sized load if not loading an integral number of
1178 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1179 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1180 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1183 // The extra bits are guaranteed to be zero, since we stored them that
1184 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1186 ISD::LoadExtType NewExtType =
1187 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1189 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0), dl,
1190 Tmp1, Tmp2, LD->getPointerInfo(),
1191 NVT, isVolatile, isNonTemporal, Alignment);
1193 Ch = Result.getValue(1); // The chain.
1195 if (ExtType == ISD::SEXTLOAD)
1196 // Having the top bits zero doesn't help when sign extending.
1197 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1198 Result.getValueType(),
1199 Result, DAG.getValueType(SrcVT));
1200 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1201 // All the top bits are guaranteed to be zero - inform the optimizers.
1202 Result = DAG.getNode(ISD::AssertZext, dl,
1203 Result.getValueType(), Result,
1204 DAG.getValueType(SrcVT));
1206 Tmp1 = LegalizeOp(Result);
1207 Tmp2 = LegalizeOp(Ch);
1208 } else if (SrcWidth & (SrcWidth - 1)) {
1209 // If not loading a power-of-2 number of bits, expand as two loads.
1210 assert(!SrcVT.isVector() && "Unsupported extload!");
1211 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1212 assert(RoundWidth < SrcWidth);
1213 unsigned ExtraWidth = SrcWidth - RoundWidth;
1214 assert(ExtraWidth < RoundWidth);
1215 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1216 "Load size not an integral number of bytes!");
1217 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1218 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1220 unsigned IncrementSize;
1222 if (TLI.isLittleEndian()) {
1223 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1224 // Load the bottom RoundWidth bits.
1225 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), dl,
1227 LD->getPointerInfo(), RoundVT, isVolatile,
1228 isNonTemporal, Alignment);
1230 // Load the remaining ExtraWidth bits.
1231 IncrementSize = RoundWidth / 8;
1232 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1233 DAG.getIntPtrConstant(IncrementSize));
1234 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1235 LD->getPointerInfo().getWithOffset(IncrementSize),
1236 ExtraVT, isVolatile, isNonTemporal,
1237 MinAlign(Alignment, IncrementSize));
1239 // Build a factor node to remember that this load is independent of
1241 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1244 // Move the top bits to the right place.
1245 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1246 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1248 // Join the hi and lo parts.
1249 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1251 // Big endian - avoid unaligned loads.
1252 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1253 // Load the top RoundWidth bits.
1254 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), dl, Tmp1, Tmp2,
1255 LD->getPointerInfo(), RoundVT, isVolatile,
1256 isNonTemporal, Alignment);
1258 // Load the remaining ExtraWidth bits.
1259 IncrementSize = RoundWidth / 8;
1260 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1261 DAG.getIntPtrConstant(IncrementSize));
1262 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1263 Node->getValueType(0), dl, Tmp1, Tmp2,
1264 LD->getPointerInfo().getWithOffset(IncrementSize),
1265 ExtraVT, isVolatile, isNonTemporal,
1266 MinAlign(Alignment, IncrementSize));
1268 // Build a factor node to remember that this load is independent of
1270 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1273 // Move the top bits to the right place.
1274 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1275 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1277 // Join the hi and lo parts.
1278 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1281 Tmp1 = LegalizeOp(Result);
1282 Tmp2 = LegalizeOp(Ch);
1284 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1285 default: assert(0 && "This action is not supported yet!");
1286 case TargetLowering::Custom:
1289 case TargetLowering::Legal:
1290 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1291 Tmp1, Tmp2, LD->getOffset()),
1293 Tmp1 = Result.getValue(0);
1294 Tmp2 = Result.getValue(1);
1297 Tmp3 = TLI.LowerOperation(Result, DAG);
1298 if (Tmp3.getNode()) {
1299 Tmp1 = LegalizeOp(Tmp3);
1300 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1303 // If this is an unaligned load and the target doesn't support it,
1305 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1307 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1308 unsigned ABIAlignment =
1309 TLI.getTargetData()->getABITypeAlignment(Ty);
1310 if (LD->getAlignment() < ABIAlignment){
1311 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1313 Tmp1 = Result.getOperand(0);
1314 Tmp2 = Result.getOperand(1);
1315 Tmp1 = LegalizeOp(Tmp1);
1316 Tmp2 = LegalizeOp(Tmp2);
1321 case TargetLowering::Expand:
1322 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1323 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1324 LD->getPointerInfo(),
1325 LD->isVolatile(), LD->isNonTemporal(),
1326 LD->getAlignment());
1330 ExtendOp = (SrcVT.isFloatingPoint() ?
1331 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1333 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1334 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1335 default: llvm_unreachable("Unexpected extend load type!");
1337 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1338 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1339 Tmp2 = LegalizeOp(Load.getValue(1));
1342 // FIXME: This does not work for vectors on most targets. Sign- and
1343 // zero-extend operations are currently folded into extending loads,
1344 // whether they are legal or not, and then we end up here without any
1345 // support for legalizing them.
1346 assert(ExtType != ISD::EXTLOAD &&
1347 "EXTLOAD should always be supported!");
1348 // Turn the unsupported load into an EXTLOAD followed by an explicit
1349 // zero/sign extend inreg.
1350 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0), dl,
1351 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1352 LD->isVolatile(), LD->isNonTemporal(),
1353 LD->getAlignment());
1355 if (ExtType == ISD::SEXTLOAD)
1356 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1357 Result.getValueType(),
1358 Result, DAG.getValueType(SrcVT));
1360 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1361 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1362 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1367 // Since loads produce two values, make sure to remember that we legalized
1369 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1370 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1371 return Op.getResNo() ? Tmp2 : Tmp1;
1374 StoreSDNode *ST = cast<StoreSDNode>(Node);
1375 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1376 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1377 unsigned Alignment = ST->getAlignment();
1378 bool isVolatile = ST->isVolatile();
1379 bool isNonTemporal = ST->isNonTemporal();
1381 if (!ST->isTruncatingStore()) {
1382 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1383 Result = SDValue(OptStore, 0);
1388 Tmp3 = LegalizeOp(ST->getValue());
1389 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1394 EVT VT = Tmp3.getValueType();
1395 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1396 default: assert(0 && "This action is not supported yet!");
1397 case TargetLowering::Legal:
1398 // If this is an unaligned store and the target doesn't support it,
1400 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1401 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1402 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1403 if (ST->getAlignment() < ABIAlignment)
1404 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1408 case TargetLowering::Custom:
1409 Tmp1 = TLI.LowerOperation(Result, DAG);
1410 if (Tmp1.getNode()) Result = Tmp1;
1412 case TargetLowering::Promote:
1413 assert(VT.isVector() && "Unknown legal promote case!");
1414 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1415 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1416 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1417 ST->getPointerInfo(), isVolatile,
1418 isNonTemporal, Alignment);
1424 Tmp3 = LegalizeOp(ST->getValue());
1426 EVT StVT = ST->getMemoryVT();
1427 unsigned StWidth = StVT.getSizeInBits();
1429 if (StWidth != StVT.getStoreSizeInBits()) {
1430 // Promote to a byte-sized store with upper bits zero if not
1431 // storing an integral number of bytes. For example, promote
1432 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1433 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1434 StVT.getStoreSizeInBits());
1435 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1436 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1437 NVT, isVolatile, isNonTemporal, Alignment);
1438 } else if (StWidth & (StWidth - 1)) {
1439 // If not storing a power-of-2 number of bits, expand as two stores.
1440 assert(!StVT.isVector() && "Unsupported truncstore!");
1441 unsigned RoundWidth = 1 << Log2_32(StWidth);
1442 assert(RoundWidth < StWidth);
1443 unsigned ExtraWidth = StWidth - RoundWidth;
1444 assert(ExtraWidth < RoundWidth);
1445 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1446 "Store size not an integral number of bytes!");
1447 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1448 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1450 unsigned IncrementSize;
1452 if (TLI.isLittleEndian()) {
1453 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1454 // Store the bottom RoundWidth bits.
1455 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1457 isVolatile, isNonTemporal, Alignment);
1459 // Store the remaining ExtraWidth bits.
1460 IncrementSize = RoundWidth / 8;
1461 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1462 DAG.getIntPtrConstant(IncrementSize));
1463 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1464 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1465 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1466 ST->getPointerInfo().getWithOffset(IncrementSize),
1467 ExtraVT, isVolatile, isNonTemporal,
1468 MinAlign(Alignment, IncrementSize));
1470 // Big endian - avoid unaligned stores.
1471 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1472 // Store the top RoundWidth bits.
1473 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1474 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1475 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1476 RoundVT, isVolatile, isNonTemporal, Alignment);
1478 // Store the remaining ExtraWidth bits.
1479 IncrementSize = RoundWidth / 8;
1480 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1481 DAG.getIntPtrConstant(IncrementSize));
1482 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1483 ST->getPointerInfo().getWithOffset(IncrementSize),
1484 ExtraVT, isVolatile, isNonTemporal,
1485 MinAlign(Alignment, IncrementSize));
1488 // The order of the stores doesn't matter.
1489 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1491 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1492 Tmp2 != ST->getBasePtr())
1493 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1498 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1499 default: assert(0 && "This action is not supported yet!");
1500 case TargetLowering::Legal:
1501 // If this is an unaligned store and the target doesn't support it,
1503 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1504 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1505 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1506 if (ST->getAlignment() < ABIAlignment)
1507 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1511 case TargetLowering::Custom:
1512 Result = TLI.LowerOperation(Result, DAG);
1515 // TRUNCSTORE:i16 i32 -> STORE i16
1516 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1517 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1518 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1519 isVolatile, isNonTemporal, Alignment);
1527 assert(Result.getValueType() == Op.getValueType() &&
1528 "Bad legalization!");
1530 // Make sure that the generated code is itself legal.
1532 Result = LegalizeOp(Result);
1534 // Note that LegalizeOp may be reentered even from single-use nodes, which
1535 // means that we always must cache transformed nodes.
1536 AddLegalizedOperand(Op, Result);
1540 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1541 SDValue Vec = Op.getOperand(0);
1542 SDValue Idx = Op.getOperand(1);
1543 DebugLoc dl = Op.getDebugLoc();
1544 // Store the value to a temporary stack slot, then LOAD the returned part.
1545 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1546 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1547 MachinePointerInfo(), false, false, 0);
1549 // Add the offset to the index.
1551 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1552 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1553 DAG.getConstant(EltSize, Idx.getValueType()));
1555 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1556 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1558 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1560 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1562 if (Op.getValueType().isVector())
1563 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1565 return DAG.getExtLoad(ISD::EXTLOAD, Op.getValueType(), dl, Ch, StackPtr,
1566 MachinePointerInfo(),
1567 Vec.getValueType().getVectorElementType(),
1571 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1572 // We can't handle this case efficiently. Allocate a sufficiently
1573 // aligned object on the stack, store each element into it, then load
1574 // the result as a vector.
1575 // Create the stack frame object.
1576 EVT VT = Node->getValueType(0);
1577 EVT EltVT = VT.getVectorElementType();
1578 DebugLoc dl = Node->getDebugLoc();
1579 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1580 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1581 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1583 // Emit a store of each element to the stack slot.
1584 SmallVector<SDValue, 8> Stores;
1585 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1586 // Store (in the right endianness) the elements to memory.
1587 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1588 // Ignore undef elements.
1589 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1591 unsigned Offset = TypeByteSize*i;
1593 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1594 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1596 // If the destination vector element type is narrower than the source
1597 // element type, only store the bits necessary.
1598 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1599 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1600 Node->getOperand(i), Idx,
1601 PtrInfo.getWithOffset(Offset),
1602 EltVT, false, false, 0));
1604 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1605 Node->getOperand(i), Idx,
1606 PtrInfo.getWithOffset(Offset),
1611 if (!Stores.empty()) // Not all undef elements?
1612 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1613 &Stores[0], Stores.size());
1615 StoreChain = DAG.getEntryNode();
1617 // Result is a load from the stack slot.
1618 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1621 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1622 DebugLoc dl = Node->getDebugLoc();
1623 SDValue Tmp1 = Node->getOperand(0);
1624 SDValue Tmp2 = Node->getOperand(1);
1626 // Get the sign bit of the RHS. First obtain a value that has the same
1627 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1629 EVT FloatVT = Tmp2.getValueType();
1630 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1631 if (isTypeLegal(IVT)) {
1632 // Convert to an integer with the same sign bit.
1633 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1635 // Store the float to memory, then load the sign part out as an integer.
1636 MVT LoadTy = TLI.getPointerTy();
1637 // First create a temporary that is aligned for both the load and store.
1638 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1639 // Then store the float to it.
1641 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1643 if (TLI.isBigEndian()) {
1644 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1645 // Load out a legal integer with the same sign bit as the float.
1646 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1648 } else { // Little endian
1649 SDValue LoadPtr = StackPtr;
1650 // The float may be wider than the integer we are going to load. Advance
1651 // the pointer so that the loaded integer will contain the sign bit.
1652 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1653 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1654 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1655 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1656 // Load a legal integer containing the sign bit.
1657 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1659 // Move the sign bit to the top bit of the loaded integer.
1660 unsigned BitShift = LoadTy.getSizeInBits() -
1661 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1662 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1664 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1665 DAG.getConstant(BitShift,TLI.getShiftAmountTy()));
1668 // Now get the sign bit proper, by seeing whether the value is negative.
1669 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1670 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1672 // Get the absolute value of the result.
1673 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1674 // Select between the nabs and abs value based on the sign bit of
1676 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1677 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1681 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1682 SmallVectorImpl<SDValue> &Results) {
1683 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1684 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1685 " not tell us which reg is the stack pointer!");
1686 DebugLoc dl = Node->getDebugLoc();
1687 EVT VT = Node->getValueType(0);
1688 SDValue Tmp1 = SDValue(Node, 0);
1689 SDValue Tmp2 = SDValue(Node, 1);
1690 SDValue Tmp3 = Node->getOperand(2);
1691 SDValue Chain = Tmp1.getOperand(0);
1693 // Chain the dynamic stack allocation so that it doesn't modify the stack
1694 // pointer when other instructions are using the stack.
1695 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1697 SDValue Size = Tmp2.getOperand(1);
1698 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1699 Chain = SP.getValue(1);
1700 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1701 unsigned StackAlign = TM.getFrameInfo()->getStackAlignment();
1702 if (Align > StackAlign)
1703 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1704 DAG.getConstant(-(uint64_t)Align, VT));
1705 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1706 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1708 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1709 DAG.getIntPtrConstant(0, true), SDValue());
1711 Results.push_back(Tmp1);
1712 Results.push_back(Tmp2);
1715 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1716 /// condition code CC on the current target. This routine expands SETCC with
1717 /// illegal condition code into AND / OR of multiple SETCC values.
1718 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1719 SDValue &LHS, SDValue &RHS,
1722 EVT OpVT = LHS.getValueType();
1723 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1724 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1725 default: assert(0 && "Unknown condition code action!");
1726 case TargetLowering::Legal:
1729 case TargetLowering::Expand: {
1730 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1733 default: assert(0 && "Don't know how to expand this condition!");
1734 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1735 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1736 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1737 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1738 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1739 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1740 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1741 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1742 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1743 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1744 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1745 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1746 // FIXME: Implement more expansions.
1749 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1750 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1751 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1759 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1760 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1761 /// a load from the stack slot to DestVT, extending it if needed.
1762 /// The resultant code need not be legal.
1763 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1767 // Create the stack frame object.
1769 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1770 getTypeForEVT(*DAG.getContext()));
1771 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1773 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1774 int SPFI = StackPtrFI->getIndex();
1775 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1777 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1778 unsigned SlotSize = SlotVT.getSizeInBits();
1779 unsigned DestSize = DestVT.getSizeInBits();
1780 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1781 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
1783 // Emit a store to the stack slot. Use a truncstore if the input value is
1784 // later than DestVT.
1787 if (SrcSize > SlotSize)
1788 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1789 PtrInfo, SlotVT, false, false, SrcAlign);
1791 assert(SrcSize == SlotSize && "Invalid store");
1792 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1793 PtrInfo, false, false, SrcAlign);
1796 // Result is a load from the stack slot.
1797 if (SlotSize == DestSize)
1798 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1799 false, false, DestAlign);
1801 assert(SlotSize < DestSize && "Unknown extension!");
1802 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl, Store, FIPtr,
1803 PtrInfo, SlotVT, false, false, DestAlign);
1806 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1807 DebugLoc dl = Node->getDebugLoc();
1808 // Create a vector sized/aligned stack slot, store the value to element #0,
1809 // then load the whole vector back out.
1810 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1812 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1813 int SPFI = StackPtrFI->getIndex();
1815 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1817 MachinePointerInfo::getFixedStack(SPFI),
1818 Node->getValueType(0).getVectorElementType(),
1820 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1821 MachinePointerInfo::getFixedStack(SPFI),
1826 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1827 /// support the operation, but do support the resultant vector type.
1828 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1829 unsigned NumElems = Node->getNumOperands();
1830 SDValue Value1, Value2;
1831 DebugLoc dl = Node->getDebugLoc();
1832 EVT VT = Node->getValueType(0);
1833 EVT OpVT = Node->getOperand(0).getValueType();
1834 EVT EltVT = VT.getVectorElementType();
1836 // If the only non-undef value is the low element, turn this into a
1837 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1838 bool isOnlyLowElement = true;
1839 bool MoreThanTwoValues = false;
1840 bool isConstant = true;
1841 for (unsigned i = 0; i < NumElems; ++i) {
1842 SDValue V = Node->getOperand(i);
1843 if (V.getOpcode() == ISD::UNDEF)
1846 isOnlyLowElement = false;
1847 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1850 if (!Value1.getNode()) {
1852 } else if (!Value2.getNode()) {
1855 } else if (V != Value1 && V != Value2) {
1856 MoreThanTwoValues = true;
1860 if (!Value1.getNode())
1861 return DAG.getUNDEF(VT);
1863 if (isOnlyLowElement)
1864 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1866 // If all elements are constants, create a load from the constant pool.
1868 std::vector<Constant*> CV;
1869 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1870 if (ConstantFPSDNode *V =
1871 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1872 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1873 } else if (ConstantSDNode *V =
1874 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1876 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1878 // If OpVT and EltVT don't match, EltVT is not legal and the
1879 // element values have been promoted/truncated earlier. Undo this;
1880 // we don't want a v16i8 to become a v16i32 for example.
1881 const ConstantInt *CI = V->getConstantIntValue();
1882 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1883 CI->getZExtValue()));
1886 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1887 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1888 CV.push_back(UndefValue::get(OpNTy));
1891 Constant *CP = ConstantVector::get(CV);
1892 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1893 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1894 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1895 MachinePointerInfo::getConstantPool(),
1896 false, false, Alignment);
1899 if (!MoreThanTwoValues) {
1900 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1901 for (unsigned i = 0; i < NumElems; ++i) {
1902 SDValue V = Node->getOperand(i);
1903 if (V.getOpcode() == ISD::UNDEF)
1905 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1907 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1908 // Get the splatted value into the low element of a vector register.
1909 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1911 if (Value2.getNode())
1912 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1914 Vec2 = DAG.getUNDEF(VT);
1916 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1917 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1921 // Otherwise, we can't handle this case efficiently.
1922 return ExpandVectorBuildThroughStack(Node);
1925 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1926 // does not fit into a register, return the lo part and set the hi part to the
1927 // by-reg argument. If it does fit into a single register, return the result
1928 // and leave the Hi part unset.
1929 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1931 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1932 // The input chain to this libcall is the entry node of the function.
1933 // Legalizing the call will automatically add the previous call to the
1935 SDValue InChain = DAG.getEntryNode();
1937 TargetLowering::ArgListTy Args;
1938 TargetLowering::ArgListEntry Entry;
1939 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1940 EVT ArgVT = Node->getOperand(i).getValueType();
1941 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1942 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1943 Entry.isSExt = isSigned;
1944 Entry.isZExt = !isSigned;
1945 Args.push_back(Entry);
1947 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1948 TLI.getPointerTy());
1950 // Splice the libcall in wherever FindInputOutputChains tells us to.
1951 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1953 // isTailCall may be true since the callee does not reference caller stack
1954 // frame. Check if it's in the right position.
1955 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
1956 std::pair<SDValue, SDValue> CallInfo =
1957 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1958 0, TLI.getLibcallCallingConv(LC), isTailCall,
1959 /*isReturnValueUsed=*/true,
1960 Callee, Args, DAG, Node->getDebugLoc());
1962 if (!CallInfo.second.getNode())
1963 // It's a tailcall, return the chain (which is the DAG root).
1964 return DAG.getRoot();
1966 // Legalize the call sequence, starting with the chain. This will advance
1967 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1968 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1969 LegalizeOp(CallInfo.second);
1970 return CallInfo.first;
1973 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
1974 // ExpandLibCall except that the first operand is the in-chain.
1975 std::pair<SDValue, SDValue>
1976 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
1979 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1980 SDValue InChain = Node->getOperand(0);
1982 TargetLowering::ArgListTy Args;
1983 TargetLowering::ArgListEntry Entry;
1984 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
1985 EVT ArgVT = Node->getOperand(i).getValueType();
1986 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1987 Entry.Node = Node->getOperand(i);
1989 Entry.isSExt = isSigned;
1990 Entry.isZExt = !isSigned;
1991 Args.push_back(Entry);
1993 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1994 TLI.getPointerTy());
1996 // Splice the libcall in wherever FindInputOutputChains tells us to.
1997 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
1998 std::pair<SDValue, SDValue> CallInfo =
1999 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2000 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2001 /*isReturnValueUsed=*/true,
2002 Callee, Args, DAG, Node->getDebugLoc());
2004 // Legalize the call sequence, starting with the chain. This will advance
2005 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2006 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2007 LegalizeOp(CallInfo.second);
2011 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2012 RTLIB::Libcall Call_F32,
2013 RTLIB::Libcall Call_F64,
2014 RTLIB::Libcall Call_F80,
2015 RTLIB::Libcall Call_PPCF128) {
2017 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2018 default: assert(0 && "Unexpected request for libcall!");
2019 case MVT::f32: LC = Call_F32; break;
2020 case MVT::f64: LC = Call_F64; break;
2021 case MVT::f80: LC = Call_F80; break;
2022 case MVT::ppcf128: LC = Call_PPCF128; break;
2024 return ExpandLibCall(LC, Node, false);
2027 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2028 RTLIB::Libcall Call_I8,
2029 RTLIB::Libcall Call_I16,
2030 RTLIB::Libcall Call_I32,
2031 RTLIB::Libcall Call_I64,
2032 RTLIB::Libcall Call_I128) {
2034 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2035 default: assert(0 && "Unexpected request for libcall!");
2036 case MVT::i8: LC = Call_I8; break;
2037 case MVT::i16: LC = Call_I16; break;
2038 case MVT::i32: LC = Call_I32; break;
2039 case MVT::i64: LC = Call_I64; break;
2040 case MVT::i128: LC = Call_I128; break;
2042 return ExpandLibCall(LC, Node, isSigned);
2045 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2046 /// INT_TO_FP operation of the specified operand when the target requests that
2047 /// we expand it. At this point, we know that the result and operand types are
2048 /// legal for the target.
2049 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2053 if (Op0.getValueType() == MVT::i32) {
2054 // simple 32-bit [signed|unsigned] integer to float/double expansion
2056 // Get the stack frame index of a 8 byte buffer.
2057 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2059 // word offset constant for Hi/Lo address computation
2060 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2061 // set up Hi and Lo (into buffer) address based on endian
2062 SDValue Hi = StackSlot;
2063 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2064 TLI.getPointerTy(), StackSlot, WordOff);
2065 if (TLI.isLittleEndian())
2068 // if signed map to unsigned space
2071 // constant used to invert sign bit (signed to unsigned mapping)
2072 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2073 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2077 // store the lo of the constructed double - based on integer input
2078 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2079 Op0Mapped, Lo, MachinePointerInfo(),
2081 // initial hi portion of constructed double
2082 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2083 // store the hi of the constructed double - biased exponent
2084 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2085 MachinePointerInfo(),
2087 // load the constructed double
2088 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2089 MachinePointerInfo(), false, false, 0);
2090 // FP constant to bias correct the final result
2091 SDValue Bias = DAG.getConstantFP(isSigned ?
2092 BitsToDouble(0x4330000080000000ULL) :
2093 BitsToDouble(0x4330000000000000ULL),
2095 // subtract the bias
2096 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2099 // handle final rounding
2100 if (DestVT == MVT::f64) {
2103 } else if (DestVT.bitsLT(MVT::f64)) {
2104 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2105 DAG.getIntPtrConstant(0));
2106 } else if (DestVT.bitsGT(MVT::f64)) {
2107 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2111 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2112 // Code below here assumes !isSigned without checking again.
2114 // Implementation of unsigned i64 to f64 following the algorithm in
2115 // __floatundidf in compiler_rt. This implementation has the advantage
2116 // of performing rounding correctly, both in the default rounding mode
2117 // and in all alternate rounding modes.
2118 // TODO: Generalize this for use with other types.
2119 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2121 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2122 SDValue TwoP84PlusTwoP52 =
2123 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2125 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2127 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2128 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2129 DAG.getConstant(32, MVT::i64));
2130 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2131 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2132 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2133 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2134 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2136 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2139 // Implementation of unsigned i64 to f32.
2140 // TODO: Generalize this for use with other types.
2141 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2142 // For unsigned conversions, convert them to signed conversions using the
2143 // algorithm from the x86_64 __floatundidf in compiler_rt.
2145 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2147 SDValue ShiftConst = DAG.getConstant(1, TLI.getShiftAmountTy());
2148 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2149 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2150 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2151 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2153 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2154 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2156 // TODO: This really should be implemented using a branch rather than a
2157 // select. We happen to get lucky and machinesink does the right
2158 // thing most of the time. This would be a good candidate for a
2159 //pseudo-op, or, even better, for whole-function isel.
2160 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2161 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2162 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2165 // Otherwise, implement the fully general conversion.
2166 EVT SHVT = TLI.getShiftAmountTy();
2168 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2169 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2170 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2171 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2172 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2173 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2174 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2175 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2176 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2177 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2178 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2180 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2182 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2183 DAG.getConstant(32, SHVT));
2184 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2185 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2187 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2188 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2189 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2190 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2191 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2192 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2193 DAG.getIntPtrConstant(0));
2196 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2198 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2199 Op0, DAG.getConstant(0, Op0.getValueType()),
2201 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2202 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2203 SignSet, Four, Zero);
2205 // If the sign bit of the integer is set, the large number will be treated
2206 // as a negative number. To counteract this, the dynamic code adds an
2207 // offset depending on the data type.
2209 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2210 default: assert(0 && "Unsupported integer type!");
2211 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2212 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2213 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2214 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2216 if (TLI.isLittleEndian()) FF <<= 32;
2217 Constant *FudgeFactor = ConstantInt::get(
2218 Type::getInt64Ty(*DAG.getContext()), FF);
2220 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2221 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2222 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2223 Alignment = std::min(Alignment, 4u);
2225 if (DestVT == MVT::f32)
2226 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2227 MachinePointerInfo::getConstantPool(),
2228 false, false, Alignment);
2231 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT, dl,
2232 DAG.getEntryNode(), CPIdx,
2233 MachinePointerInfo::getConstantPool(),
2234 MVT::f32, false, false, Alignment));
2237 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2240 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2241 /// *INT_TO_FP operation of the specified operand when the target requests that
2242 /// we promote it. At this point, we know that the result and operand types are
2243 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2244 /// operation that takes a larger input.
2245 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2249 // First step, figure out the appropriate *INT_TO_FP operation to use.
2250 EVT NewInTy = LegalOp.getValueType();
2252 unsigned OpToUse = 0;
2254 // Scan for the appropriate larger type to use.
2256 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2257 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2259 // If the target supports SINT_TO_FP of this type, use it.
2260 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2261 OpToUse = ISD::SINT_TO_FP;
2264 if (isSigned) continue;
2266 // If the target supports UINT_TO_FP of this type, use it.
2267 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2268 OpToUse = ISD::UINT_TO_FP;
2272 // Otherwise, try a larger type.
2275 // Okay, we found the operation and type to use. Zero extend our input to the
2276 // desired type then run the operation on it.
2277 return DAG.getNode(OpToUse, dl, DestVT,
2278 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2279 dl, NewInTy, LegalOp));
2282 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2283 /// FP_TO_*INT operation of the specified operand when the target requests that
2284 /// we promote it. At this point, we know that the result and operand types are
2285 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2286 /// operation that returns a larger result.
2287 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2291 // First step, figure out the appropriate FP_TO*INT operation to use.
2292 EVT NewOutTy = DestVT;
2294 unsigned OpToUse = 0;
2296 // Scan for the appropriate larger type to use.
2298 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2299 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2301 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2302 OpToUse = ISD::FP_TO_SINT;
2306 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2307 OpToUse = ISD::FP_TO_UINT;
2311 // Otherwise, try a larger type.
2315 // Okay, we found the operation and type to use.
2316 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2318 // Truncate the result of the extended FP_TO_*INT operation to the desired
2320 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2323 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2325 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2326 EVT VT = Op.getValueType();
2327 EVT SHVT = TLI.getShiftAmountTy();
2328 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2329 switch (VT.getSimpleVT().SimpleTy) {
2330 default: assert(0 && "Unhandled Expand type in BSWAP!");
2332 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2333 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2334 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2336 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2337 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2338 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2339 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2340 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2341 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2342 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2343 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2344 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2346 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2347 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2348 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2349 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2350 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2351 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2352 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2353 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2354 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2355 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2356 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2357 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2358 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2359 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2360 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2361 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2362 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2363 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2364 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2365 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2366 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2370 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2372 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2375 default: assert(0 && "Cannot expand this yet!");
2377 static const uint64_t mask[6] = {
2378 0x5555555555555555ULL, 0x3333333333333333ULL,
2379 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2380 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2382 EVT VT = Op.getValueType();
2383 EVT ShVT = TLI.getShiftAmountTy();
2384 unsigned len = VT.getSizeInBits();
2385 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2386 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2387 unsigned EltSize = VT.isVector() ?
2388 VT.getVectorElementType().getSizeInBits() : len;
2389 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2390 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2391 Op = DAG.getNode(ISD::ADD, dl, VT,
2392 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2393 DAG.getNode(ISD::AND, dl, VT,
2394 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2400 // for now, we do this:
2401 // x = x | (x >> 1);
2402 // x = x | (x >> 2);
2404 // x = x | (x >>16);
2405 // x = x | (x >>32); // for 64-bit input
2406 // return popcount(~x);
2408 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2409 EVT VT = Op.getValueType();
2410 EVT ShVT = TLI.getShiftAmountTy();
2411 unsigned len = VT.getSizeInBits();
2412 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2413 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2414 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2415 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2417 Op = DAG.getNOT(dl, Op, VT);
2418 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2421 // for now, we use: { return popcount(~x & (x - 1)); }
2422 // unless the target has ctlz but not ctpop, in which case we use:
2423 // { return 32 - nlz(~x & (x-1)); }
2424 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2425 EVT VT = Op.getValueType();
2426 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2427 DAG.getNOT(dl, Op, VT),
2428 DAG.getNode(ISD::SUB, dl, VT, Op,
2429 DAG.getConstant(1, VT)));
2430 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2431 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2432 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2433 return DAG.getNode(ISD::SUB, dl, VT,
2434 DAG.getConstant(VT.getSizeInBits(), VT),
2435 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2436 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2441 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2442 unsigned Opc = Node->getOpcode();
2443 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2448 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2450 case ISD::ATOMIC_SWAP:
2451 switch (VT.SimpleTy) {
2452 default: llvm_unreachable("Unexpected value type for atomic!");
2453 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2454 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2455 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2456 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2459 case ISD::ATOMIC_CMP_SWAP:
2460 switch (VT.SimpleTy) {
2461 default: llvm_unreachable("Unexpected value type for atomic!");
2462 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2463 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2464 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2465 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2468 case ISD::ATOMIC_LOAD_ADD:
2469 switch (VT.SimpleTy) {
2470 default: llvm_unreachable("Unexpected value type for atomic!");
2471 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2472 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2473 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2474 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2477 case ISD::ATOMIC_LOAD_SUB:
2478 switch (VT.SimpleTy) {
2479 default: llvm_unreachable("Unexpected value type for atomic!");
2480 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2481 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2482 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2483 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2486 case ISD::ATOMIC_LOAD_AND:
2487 switch (VT.SimpleTy) {
2488 default: llvm_unreachable("Unexpected value type for atomic!");
2489 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2490 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2491 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2492 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2495 case ISD::ATOMIC_LOAD_OR:
2496 switch (VT.SimpleTy) {
2497 default: llvm_unreachable("Unexpected value type for atomic!");
2498 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2499 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2500 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2501 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2504 case ISD::ATOMIC_LOAD_XOR:
2505 switch (VT.SimpleTy) {
2506 default: llvm_unreachable("Unexpected value type for atomic!");
2507 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2508 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2509 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2510 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2513 case ISD::ATOMIC_LOAD_NAND:
2514 switch (VT.SimpleTy) {
2515 default: llvm_unreachable("Unexpected value type for atomic!");
2516 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2517 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2518 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2519 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2524 return ExpandChainLibCall(LC, Node, false);
2527 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2528 SmallVectorImpl<SDValue> &Results) {
2529 DebugLoc dl = Node->getDebugLoc();
2530 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2531 switch (Node->getOpcode()) {
2535 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2536 Results.push_back(Tmp1);
2539 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2541 case ISD::FRAMEADDR:
2542 case ISD::RETURNADDR:
2543 case ISD::FRAME_TO_ARGS_OFFSET:
2544 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2546 case ISD::FLT_ROUNDS_:
2547 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2549 case ISD::EH_RETURN:
2553 case ISD::EH_SJLJ_LONGJMP:
2554 case ISD::EH_SJLJ_DISPATCHSETUP:
2555 // If the target didn't expand these, there's nothing to do, so just
2556 // preserve the chain and be done.
2557 Results.push_back(Node->getOperand(0));
2559 case ISD::EH_SJLJ_SETJMP:
2560 // If the target didn't expand this, just return 'zero' and preserve the
2562 Results.push_back(DAG.getConstant(0, MVT::i32));
2563 Results.push_back(Node->getOperand(0));
2565 case ISD::MEMBARRIER: {
2566 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2567 TargetLowering::ArgListTy Args;
2568 std::pair<SDValue, SDValue> CallResult =
2569 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2570 false, false, false, false, 0, CallingConv::C,
2571 /*isTailCall=*/false,
2572 /*isReturnValueUsed=*/true,
2573 DAG.getExternalSymbol("__sync_synchronize",
2574 TLI.getPointerTy()),
2576 Results.push_back(CallResult.second);
2579 // By default, atomic intrinsics are marked Legal and lowered. Targets
2580 // which don't support them directly, however, may want libcalls, in which
2581 // case they mark them Expand, and we get here.
2582 // FIXME: Unimplemented for now. Add libcalls.
2583 case ISD::ATOMIC_SWAP:
2584 case ISD::ATOMIC_LOAD_ADD:
2585 case ISD::ATOMIC_LOAD_SUB:
2586 case ISD::ATOMIC_LOAD_AND:
2587 case ISD::ATOMIC_LOAD_OR:
2588 case ISD::ATOMIC_LOAD_XOR:
2589 case ISD::ATOMIC_LOAD_NAND:
2590 case ISD::ATOMIC_LOAD_MIN:
2591 case ISD::ATOMIC_LOAD_MAX:
2592 case ISD::ATOMIC_LOAD_UMIN:
2593 case ISD::ATOMIC_LOAD_UMAX:
2594 case ISD::ATOMIC_CMP_SWAP: {
2595 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2596 Results.push_back(Tmp.first);
2597 Results.push_back(Tmp.second);
2600 case ISD::DYNAMIC_STACKALLOC:
2601 ExpandDYNAMIC_STACKALLOC(Node, Results);
2603 case ISD::MERGE_VALUES:
2604 for (unsigned i = 0; i < Node->getNumValues(); i++)
2605 Results.push_back(Node->getOperand(i));
2608 EVT VT = Node->getValueType(0);
2610 Results.push_back(DAG.getConstant(0, VT));
2612 assert(VT.isFloatingPoint() && "Unknown value type!");
2613 Results.push_back(DAG.getConstantFP(0, VT));
2618 // If this operation is not supported, lower it to 'abort()' call
2619 TargetLowering::ArgListTy Args;
2620 std::pair<SDValue, SDValue> CallResult =
2621 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2622 false, false, false, false, 0, CallingConv::C,
2623 /*isTailCall=*/false,
2624 /*isReturnValueUsed=*/true,
2625 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2627 Results.push_back(CallResult.second);
2632 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2633 Node->getValueType(0), dl);
2634 Results.push_back(Tmp1);
2636 case ISD::FP_EXTEND:
2637 Tmp1 = EmitStackConvert(Node->getOperand(0),
2638 Node->getOperand(0).getValueType(),
2639 Node->getValueType(0), dl);
2640 Results.push_back(Tmp1);
2642 case ISD::SIGN_EXTEND_INREG: {
2643 // NOTE: we could fall back on load/store here too for targets without
2644 // SAR. However, it is doubtful that any exist.
2645 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2646 EVT VT = Node->getValueType(0);
2647 EVT ShiftAmountTy = TLI.getShiftAmountTy();
2650 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2651 ExtraVT.getScalarType().getSizeInBits();
2652 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
2653 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2654 Node->getOperand(0), ShiftCst);
2655 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2656 Results.push_back(Tmp1);
2659 case ISD::FP_ROUND_INREG: {
2660 // The only way we can lower this is to turn it into a TRUNCSTORE,
2661 // EXTLOAD pair, targetting a temporary location (a stack slot).
2663 // NOTE: there is a choice here between constantly creating new stack
2664 // slots and always reusing the same one. We currently always create
2665 // new ones, as reuse may inhibit scheduling.
2666 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2667 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2668 Node->getValueType(0), dl);
2669 Results.push_back(Tmp1);
2672 case ISD::SINT_TO_FP:
2673 case ISD::UINT_TO_FP:
2674 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2675 Node->getOperand(0), Node->getValueType(0), dl);
2676 Results.push_back(Tmp1);
2678 case ISD::FP_TO_UINT: {
2679 SDValue True, False;
2680 EVT VT = Node->getOperand(0).getValueType();
2681 EVT NVT = Node->getValueType(0);
2682 const uint64_t zero[] = {0, 0};
2683 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2684 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2685 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2686 Tmp1 = DAG.getConstantFP(apf, VT);
2687 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2688 Node->getOperand(0),
2690 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2691 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2692 DAG.getNode(ISD::FSUB, dl, VT,
2693 Node->getOperand(0), Tmp1));
2694 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2695 DAG.getConstant(x, NVT));
2696 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2697 Results.push_back(Tmp1);
2701 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2702 EVT VT = Node->getValueType(0);
2703 Tmp1 = Node->getOperand(0);
2704 Tmp2 = Node->getOperand(1);
2705 unsigned Align = Node->getConstantOperandVal(3);
2707 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
2708 MachinePointerInfo(V), false, false, 0);
2709 SDValue VAList = VAListLoad;
2711 if (Align > TLI.getMinStackArgumentAlignment()) {
2712 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
2714 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2715 DAG.getConstant(Align - 1,
2716 TLI.getPointerTy()));
2718 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
2719 DAG.getConstant(-(int64_t)Align,
2720 TLI.getPointerTy()));
2723 // Increment the pointer, VAList, to the next vaarg
2724 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2725 DAG.getConstant(TLI.getTargetData()->
2726 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2727 TLI.getPointerTy()));
2728 // Store the incremented VAList to the legalized pointer
2729 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
2730 MachinePointerInfo(V), false, false, 0);
2731 // Load the actual argument out of the pointer VAList
2732 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
2734 Results.push_back(Results[0].getValue(1));
2738 // This defaults to loading a pointer from the input and storing it to the
2739 // output, returning the chain.
2740 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2741 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2742 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2743 Node->getOperand(2), MachinePointerInfo(VS),
2745 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
2746 MachinePointerInfo(VD), false, false, 0);
2747 Results.push_back(Tmp1);
2750 case ISD::EXTRACT_VECTOR_ELT:
2751 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2752 // This must be an access of the only element. Return it.
2753 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
2754 Node->getOperand(0));
2756 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2757 Results.push_back(Tmp1);
2759 case ISD::EXTRACT_SUBVECTOR:
2760 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2762 case ISD::CONCAT_VECTORS: {
2763 Results.push_back(ExpandVectorBuildThroughStack(Node));
2766 case ISD::SCALAR_TO_VECTOR:
2767 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2769 case ISD::INSERT_VECTOR_ELT:
2770 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2771 Node->getOperand(1),
2772 Node->getOperand(2), dl));
2774 case ISD::VECTOR_SHUFFLE: {
2775 SmallVector<int, 8> Mask;
2776 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2778 EVT VT = Node->getValueType(0);
2779 EVT EltVT = VT.getVectorElementType();
2780 if (getTypeAction(EltVT) == Promote)
2781 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
2782 unsigned NumElems = VT.getVectorNumElements();
2783 SmallVector<SDValue, 8> Ops;
2784 for (unsigned i = 0; i != NumElems; ++i) {
2786 Ops.push_back(DAG.getUNDEF(EltVT));
2789 unsigned Idx = Mask[i];
2791 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2792 Node->getOperand(0),
2793 DAG.getIntPtrConstant(Idx)));
2795 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2796 Node->getOperand(1),
2797 DAG.getIntPtrConstant(Idx - NumElems)));
2799 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2800 Results.push_back(Tmp1);
2803 case ISD::EXTRACT_ELEMENT: {
2804 EVT OpTy = Node->getOperand(0).getValueType();
2805 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2807 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2808 DAG.getConstant(OpTy.getSizeInBits()/2,
2809 TLI.getShiftAmountTy()));
2810 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2813 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2814 Node->getOperand(0));
2816 Results.push_back(Tmp1);
2819 case ISD::STACKSAVE:
2820 // Expand to CopyFromReg if the target set
2821 // StackPointerRegisterToSaveRestore.
2822 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2823 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2824 Node->getValueType(0)));
2825 Results.push_back(Results[0].getValue(1));
2827 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2828 Results.push_back(Node->getOperand(0));
2831 case ISD::STACKRESTORE:
2832 // Expand to CopyToReg if the target set
2833 // StackPointerRegisterToSaveRestore.
2834 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2835 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2836 Node->getOperand(1)));
2838 Results.push_back(Node->getOperand(0));
2841 case ISD::FCOPYSIGN:
2842 Results.push_back(ExpandFCOPYSIGN(Node));
2845 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2846 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2847 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2848 Node->getOperand(0));
2849 Results.push_back(Tmp1);
2852 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2853 EVT VT = Node->getValueType(0);
2854 Tmp1 = Node->getOperand(0);
2855 Tmp2 = DAG.getConstantFP(0.0, VT);
2856 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2857 Tmp1, Tmp2, ISD::SETUGT);
2858 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2859 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2860 Results.push_back(Tmp1);
2864 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2865 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2868 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2869 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2872 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2873 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2876 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2877 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2880 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2881 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2884 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2885 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2888 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2889 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2892 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2893 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2896 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2897 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2900 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2901 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2904 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2905 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2908 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2909 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2911 case ISD::FNEARBYINT:
2912 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2913 RTLIB::NEARBYINT_F64,
2914 RTLIB::NEARBYINT_F80,
2915 RTLIB::NEARBYINT_PPCF128));
2918 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2919 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2922 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2923 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2926 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2927 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2930 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2931 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2933 case ISD::FP16_TO_FP32:
2934 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
2936 case ISD::FP32_TO_FP16:
2937 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
2939 case ISD::ConstantFP: {
2940 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2941 // Check to see if this FP immediate is already legal.
2942 // If this is a legal constant, turn it into a TargetConstantFP node.
2943 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
2944 Results.push_back(SDValue(Node, 0));
2946 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2949 case ISD::EHSELECTION: {
2950 unsigned Reg = TLI.getExceptionSelectorRegister();
2951 assert(Reg && "Can't expand to unknown register!");
2952 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2953 Node->getValueType(0)));
2954 Results.push_back(Results[0].getValue(1));
2957 case ISD::EXCEPTIONADDR: {
2958 unsigned Reg = TLI.getExceptionAddressRegister();
2959 assert(Reg && "Can't expand to unknown register!");
2960 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2961 Node->getValueType(0)));
2962 Results.push_back(Results[0].getValue(1));
2966 EVT VT = Node->getValueType(0);
2967 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2968 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2969 "Don't know how to expand this subtraction!");
2970 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2971 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2972 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2973 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2978 EVT VT = Node->getValueType(0);
2979 SDVTList VTs = DAG.getVTList(VT, VT);
2980 bool isSigned = Node->getOpcode() == ISD::SREM;
2981 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2982 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2983 Tmp2 = Node->getOperand(0);
2984 Tmp3 = Node->getOperand(1);
2985 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2986 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2987 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2989 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2990 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2991 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2992 } else if (isSigned) {
2993 Tmp1 = ExpandIntLibCall(Node, true,
2995 RTLIB::SREM_I16, RTLIB::SREM_I32,
2996 RTLIB::SREM_I64, RTLIB::SREM_I128);
2998 Tmp1 = ExpandIntLibCall(Node, false,
3000 RTLIB::UREM_I16, RTLIB::UREM_I32,
3001 RTLIB::UREM_I64, RTLIB::UREM_I128);
3003 Results.push_back(Tmp1);
3008 bool isSigned = Node->getOpcode() == ISD::SDIV;
3009 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3010 EVT VT = Node->getValueType(0);
3011 SDVTList VTs = DAG.getVTList(VT, VT);
3012 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
3013 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3014 Node->getOperand(1));
3016 Tmp1 = ExpandIntLibCall(Node, true,
3018 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3019 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3021 Tmp1 = ExpandIntLibCall(Node, false,
3023 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3024 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3025 Results.push_back(Tmp1);
3030 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3032 EVT VT = Node->getValueType(0);
3033 SDVTList VTs = DAG.getVTList(VT, VT);
3034 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3035 "If this wasn't legal, it shouldn't have been created!");
3036 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3037 Node->getOperand(1));
3038 Results.push_back(Tmp1.getValue(1));
3042 EVT VT = Node->getValueType(0);
3043 SDVTList VTs = DAG.getVTList(VT, VT);
3044 // See if multiply or divide can be lowered using two-result operations.
3045 // We just need the low half of the multiply; try both the signed
3046 // and unsigned forms. If the target supports both SMUL_LOHI and
3047 // UMUL_LOHI, form a preference by checking which forms of plain
3048 // MULH it supports.
3049 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3050 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3051 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3052 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3053 unsigned OpToUse = 0;
3054 if (HasSMUL_LOHI && !HasMULHS) {
3055 OpToUse = ISD::SMUL_LOHI;
3056 } else if (HasUMUL_LOHI && !HasMULHU) {
3057 OpToUse = ISD::UMUL_LOHI;
3058 } else if (HasSMUL_LOHI) {
3059 OpToUse = ISD::SMUL_LOHI;
3060 } else if (HasUMUL_LOHI) {
3061 OpToUse = ISD::UMUL_LOHI;
3064 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3065 Node->getOperand(1)));
3068 Tmp1 = ExpandIntLibCall(Node, false,
3070 RTLIB::MUL_I16, RTLIB::MUL_I32,
3071 RTLIB::MUL_I64, RTLIB::MUL_I128);
3072 Results.push_back(Tmp1);
3077 SDValue LHS = Node->getOperand(0);
3078 SDValue RHS = Node->getOperand(1);
3079 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3080 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3082 Results.push_back(Sum);
3083 EVT OType = Node->getValueType(1);
3085 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3087 // LHSSign -> LHS >= 0
3088 // RHSSign -> RHS >= 0
3089 // SumSign -> Sum >= 0
3092 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3094 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3096 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3097 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3098 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3099 Node->getOpcode() == ISD::SADDO ?
3100 ISD::SETEQ : ISD::SETNE);
3102 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3103 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3105 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3106 Results.push_back(Cmp);
3111 SDValue LHS = Node->getOperand(0);
3112 SDValue RHS = Node->getOperand(1);
3113 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3114 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3116 Results.push_back(Sum);
3117 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3118 Node->getOpcode () == ISD::UADDO ?
3119 ISD::SETULT : ISD::SETUGT));
3124 EVT VT = Node->getValueType(0);
3125 SDValue LHS = Node->getOperand(0);
3126 SDValue RHS = Node->getOperand(1);
3129 static const unsigned Ops[2][3] =
3130 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3131 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3132 bool isSigned = Node->getOpcode() == ISD::SMULO;
3133 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3134 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3135 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3136 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3137 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3139 TopHalf = BottomHalf.getValue(1);
3141 // FIXME: We should be able to fall back to a libcall with an illegal
3142 // type in some cases.
3143 // Also, we can fall back to a division in some cases, but that's a big
3144 // performance hit in the general case.
3145 assert(TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3146 VT.getSizeInBits() * 2)) &&
3147 "Don't know how to expand this operation yet!");
3148 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3149 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3150 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3151 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3152 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3153 DAG.getIntPtrConstant(0));
3154 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3155 DAG.getIntPtrConstant(1));
3158 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
3159 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3160 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3163 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3164 DAG.getConstant(0, VT), ISD::SETNE);
3166 Results.push_back(BottomHalf);
3167 Results.push_back(TopHalf);
3170 case ISD::BUILD_PAIR: {
3171 EVT PairTy = Node->getValueType(0);
3172 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3173 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3174 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3175 DAG.getConstant(PairTy.getSizeInBits()/2,
3176 TLI.getShiftAmountTy()));
3177 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3181 Tmp1 = Node->getOperand(0);
3182 Tmp2 = Node->getOperand(1);
3183 Tmp3 = Node->getOperand(2);
3184 if (Tmp1.getOpcode() == ISD::SETCC) {
3185 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3187 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3189 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3190 DAG.getConstant(0, Tmp1.getValueType()),
3191 Tmp2, Tmp3, ISD::SETNE);
3193 Results.push_back(Tmp1);
3196 SDValue Chain = Node->getOperand(0);
3197 SDValue Table = Node->getOperand(1);
3198 SDValue Index = Node->getOperand(2);
3200 EVT PTy = TLI.getPointerTy();
3202 const TargetData &TD = *TLI.getTargetData();
3203 unsigned EntrySize =
3204 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3206 Index = DAG.getNode(ISD::MUL, dl, PTy,
3207 Index, DAG.getConstant(EntrySize, PTy));
3208 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3210 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3211 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, dl, Chain, Addr,
3212 MachinePointerInfo::getJumpTable(), MemVT,
3215 if (TM.getRelocationModel() == Reloc::PIC_) {
3216 // For PIC, the sequence is:
3217 // BRIND(load(Jumptable + index) + RelocBase)
3218 // RelocBase can be JumpTable, GOT or some sort of global base.
3219 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3220 TLI.getPICJumpTableRelocBase(Table, DAG));
3222 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3223 Results.push_back(Tmp1);
3227 // Expand brcond's setcc into its constituent parts and create a BR_CC
3229 Tmp1 = Node->getOperand(0);
3230 Tmp2 = Node->getOperand(1);
3231 if (Tmp2.getOpcode() == ISD::SETCC) {
3232 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3233 Tmp1, Tmp2.getOperand(2),
3234 Tmp2.getOperand(0), Tmp2.getOperand(1),
3235 Node->getOperand(2));
3237 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3238 DAG.getCondCode(ISD::SETNE), Tmp2,
3239 DAG.getConstant(0, Tmp2.getValueType()),
3240 Node->getOperand(2));
3242 Results.push_back(Tmp1);
3245 Tmp1 = Node->getOperand(0);
3246 Tmp2 = Node->getOperand(1);
3247 Tmp3 = Node->getOperand(2);
3248 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3250 // If we expanded the SETCC into an AND/OR, return the new node
3251 if (Tmp2.getNode() == 0) {
3252 Results.push_back(Tmp1);
3256 // Otherwise, SETCC for the given comparison type must be completely
3257 // illegal; expand it into a SELECT_CC.
3258 EVT VT = Node->getValueType(0);
3259 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3260 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3261 Results.push_back(Tmp1);
3264 case ISD::SELECT_CC: {
3265 Tmp1 = Node->getOperand(0); // LHS
3266 Tmp2 = Node->getOperand(1); // RHS
3267 Tmp3 = Node->getOperand(2); // True
3268 Tmp4 = Node->getOperand(3); // False
3269 SDValue CC = Node->getOperand(4);
3271 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3272 Tmp1, Tmp2, CC, dl);
3274 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3275 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3276 CC = DAG.getCondCode(ISD::SETNE);
3277 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3279 Results.push_back(Tmp1);
3283 Tmp1 = Node->getOperand(0); // Chain
3284 Tmp2 = Node->getOperand(2); // LHS
3285 Tmp3 = Node->getOperand(3); // RHS
3286 Tmp4 = Node->getOperand(1); // CC
3288 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3289 Tmp2, Tmp3, Tmp4, dl);
3290 LastCALLSEQ_END = DAG.getEntryNode();
3292 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3293 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3294 Tmp4 = DAG.getCondCode(ISD::SETNE);
3295 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3296 Tmp3, Node->getOperand(4));
3297 Results.push_back(Tmp1);
3300 case ISD::GLOBAL_OFFSET_TABLE:
3301 case ISD::GlobalAddress:
3302 case ISD::GlobalTLSAddress:
3303 case ISD::ExternalSymbol:
3304 case ISD::ConstantPool:
3305 case ISD::JumpTable:
3306 case ISD::INTRINSIC_W_CHAIN:
3307 case ISD::INTRINSIC_WO_CHAIN:
3308 case ISD::INTRINSIC_VOID:
3309 // FIXME: Custom lowering for these operations shouldn't return null!
3310 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3311 Results.push_back(SDValue(Node, i));
3315 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3316 SmallVectorImpl<SDValue> &Results) {
3317 EVT OVT = Node->getValueType(0);
3318 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3319 Node->getOpcode() == ISD::SINT_TO_FP ||
3320 Node->getOpcode() == ISD::SETCC) {
3321 OVT = Node->getOperand(0).getValueType();
3323 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3324 DebugLoc dl = Node->getDebugLoc();
3325 SDValue Tmp1, Tmp2, Tmp3;
3326 switch (Node->getOpcode()) {
3330 // Zero extend the argument.
3331 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3332 // Perform the larger operation.
3333 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3334 if (Node->getOpcode() == ISD::CTTZ) {
3335 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3336 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3337 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3339 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3340 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3341 } else if (Node->getOpcode() == ISD::CTLZ) {
3342 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3343 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3344 DAG.getConstant(NVT.getSizeInBits() -
3345 OVT.getSizeInBits(), NVT));
3347 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3350 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3351 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3352 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3353 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3354 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3355 Results.push_back(Tmp1);
3358 case ISD::FP_TO_UINT:
3359 case ISD::FP_TO_SINT:
3360 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3361 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3362 Results.push_back(Tmp1);
3364 case ISD::UINT_TO_FP:
3365 case ISD::SINT_TO_FP:
3366 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3367 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3368 Results.push_back(Tmp1);
3373 unsigned ExtOp, TruncOp;
3374 if (OVT.isVector()) {
3375 ExtOp = ISD::BITCAST;
3376 TruncOp = ISD::BITCAST;
3378 assert(OVT.isInteger() && "Cannot promote logic operation");
3379 ExtOp = ISD::ANY_EXTEND;
3380 TruncOp = ISD::TRUNCATE;
3382 // Promote each of the values to the new type.
3383 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3384 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3385 // Perform the larger operation, then convert back
3386 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3387 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3391 unsigned ExtOp, TruncOp;
3392 if (Node->getValueType(0).isVector()) {
3393 ExtOp = ISD::BITCAST;
3394 TruncOp = ISD::BITCAST;
3395 } else if (Node->getValueType(0).isInteger()) {
3396 ExtOp = ISD::ANY_EXTEND;
3397 TruncOp = ISD::TRUNCATE;
3399 ExtOp = ISD::FP_EXTEND;
3400 TruncOp = ISD::FP_ROUND;
3402 Tmp1 = Node->getOperand(0);
3403 // Promote each of the values to the new type.
3404 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3405 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3406 // Perform the larger operation, then round down.
3407 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3408 if (TruncOp != ISD::FP_ROUND)
3409 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3411 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3412 DAG.getIntPtrConstant(0));
3413 Results.push_back(Tmp1);
3416 case ISD::VECTOR_SHUFFLE: {
3417 SmallVector<int, 8> Mask;
3418 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3420 // Cast the two input vectors.
3421 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3422 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3424 // Convert the shuffle mask to the right # elements.
3425 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3426 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3427 Results.push_back(Tmp1);
3431 unsigned ExtOp = ISD::FP_EXTEND;
3432 if (NVT.isInteger()) {
3433 ISD::CondCode CCCode =
3434 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3435 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3437 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3438 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3439 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3440 Tmp1, Tmp2, Node->getOperand(2)));
3446 // SelectionDAG::Legalize - This is the entry point for the file.
3448 void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) {
3449 /// run - This is the main entry point to this class.
3451 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();