1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 LegalizedNodes.insert(std::make_pair(From, To));
81 // If someone requests legalization of the new node, return itself.
83 LegalizedNodes.insert(std::make_pair(To, To));
85 void AddPromotedOperand(SDOperand From, SDOperand To) {
86 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
87 assert(isNew && "Got into the map somehow?");
88 // If someone requests legalization of the new node, return itself.
89 LegalizedNodes.insert(std::make_pair(To, To));
94 SelectionDAGLegalize(SelectionDAG &DAG);
96 /// Run - While there is still lowering to do, perform a pass over the DAG.
97 /// Most regularization can be done in a single pass, but targets that require
98 /// large values to be split into registers multiple times (e.g. i64 -> 4x
99 /// i16) require iteration for these values (the first iteration will demote
100 /// to i32, the second will demote to i16).
103 NeedsAnotherIteration = false;
105 } while (NeedsAnotherIteration);
108 /// getTypeAction - Return how we should legalize values of this type, either
109 /// it is already legal or we need to expand it into multiple registers of
110 /// smaller integer type, or we need to promote it to a larger type.
111 LegalizeAction getTypeAction(MVT::ValueType VT) const {
112 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
115 /// isTypeLegal - Return true if this type is legal on this target.
117 bool isTypeLegal(MVT::ValueType VT) const {
118 return getTypeAction(VT) == Legal;
124 SDOperand LegalizeOp(SDOperand O);
125 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
126 SDOperand PromoteOp(SDOperand O);
128 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
130 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
133 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
134 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
136 MVT::ValueType DestVT);
137 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
139 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
142 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
143 SDOperand &Lo, SDOperand &Hi);
144 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
145 SDOperand &Lo, SDOperand &Hi);
146 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
147 SDOperand &Lo, SDOperand &Hi);
149 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
151 SDOperand getIntPtrConstant(uint64_t Val) {
152 return DAG.getConstant(Val, TLI.getPointerTy());
157 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
159 default: assert(0 && "Don't know how to scalarize this opcode!");
160 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
161 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
162 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
166 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
167 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
168 ValueTypeActions(TLI.getValueTypeActions()) {
169 assert(MVT::LAST_VALUETYPE <= 32 &&
170 "Too many value types for ValueTypeActions to hold!");
173 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
174 /// INT_TO_FP operation of the specified operand when the target requests that
175 /// we expand it. At this point, we know that the result and operand types are
176 /// legal for the target.
177 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
179 MVT::ValueType DestVT) {
180 if (Op0.getValueType() == MVT::i32) {
181 // simple 32-bit [signed|unsigned] integer to float/double expansion
183 // get the stack frame index of a 8 byte buffer
184 MachineFunction &MF = DAG.getMachineFunction();
185 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
186 // get address of 8 byte buffer
187 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
188 // word offset constant for Hi/Lo address computation
189 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
190 // set up Hi and Lo (into buffer) address based on endian
192 if (TLI.isLittleEndian()) {
193 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
197 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
199 // if signed map to unsigned space
202 // constant used to invert sign bit (signed to unsigned mapping)
203 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
204 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
208 // store the lo of the constructed double - based on integer input
209 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
210 Op0Mapped, Lo, DAG.getSrcValue(NULL));
211 // initial hi portion of constructed double
212 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
213 // store the hi of the constructed double - biased exponent
214 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
215 InitialHi, Hi, DAG.getSrcValue(NULL));
216 // load the constructed double
217 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
218 DAG.getSrcValue(NULL));
219 // FP constant to bias correct the final result
220 SDOperand Bias = DAG.getConstantFP(isSigned ?
221 BitsToDouble(0x4330000080000000ULL)
222 : BitsToDouble(0x4330000000000000ULL),
225 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
228 // handle final rounding
229 if (DestVT == MVT::f64) {
233 // if f32 then cast to f32
234 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
236 return LegalizeOp(Result);
238 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
239 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
241 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
242 DAG.getConstant(0, Op0.getValueType()),
244 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
245 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
246 SignSet, Four, Zero);
248 // If the sign bit of the integer is set, the large number will be treated
249 // as a negative number. To counteract this, the dynamic code adds an
250 // offset depending on the data type.
252 switch (Op0.getValueType()) {
253 default: assert(0 && "Unsupported integer type!");
254 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
255 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
256 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
257 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
259 if (TLI.isLittleEndian()) FF <<= 32;
260 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
262 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
263 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
264 SDOperand FudgeInReg;
265 if (DestVT == MVT::f32)
266 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
267 DAG.getSrcValue(NULL));
269 assert(DestVT == MVT::f64 && "Unexpected conversion");
270 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
271 DAG.getEntryNode(), CPIdx,
272 DAG.getSrcValue(NULL), MVT::f32));
275 return LegalizeOp(DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg));
278 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
279 /// *INT_TO_FP operation of the specified operand when the target requests that
280 /// we promote it. At this point, we know that the result and operand types are
281 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
282 /// operation that takes a larger input.
283 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
284 MVT::ValueType DestVT,
286 // First step, figure out the appropriate *INT_TO_FP operation to use.
287 MVT::ValueType NewInTy = LegalOp.getValueType();
289 unsigned OpToUse = 0;
291 // Scan for the appropriate larger type to use.
293 NewInTy = (MVT::ValueType)(NewInTy+1);
294 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
296 // If the target supports SINT_TO_FP of this type, use it.
297 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
299 case TargetLowering::Legal:
300 if (!TLI.isTypeLegal(NewInTy))
301 break; // Can't use this datatype.
303 case TargetLowering::Custom:
304 OpToUse = ISD::SINT_TO_FP;
308 if (isSigned) continue;
310 // If the target supports UINT_TO_FP of this type, use it.
311 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
313 case TargetLowering::Legal:
314 if (!TLI.isTypeLegal(NewInTy))
315 break; // Can't use this datatype.
317 case TargetLowering::Custom:
318 OpToUse = ISD::UINT_TO_FP;
323 // Otherwise, try a larger type.
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 SDOperand N = DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
331 // Make sure to legalize any nodes we create here.
332 return LegalizeOp(N);
335 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
336 /// FP_TO_*INT operation of the specified operand when the target requests that
337 /// we promote it. At this point, we know that the result and operand types are
338 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
339 /// operation that returns a larger result.
340 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
341 MVT::ValueType DestVT,
343 // First step, figure out the appropriate FP_TO*INT operation to use.
344 MVT::ValueType NewOutTy = DestVT;
346 unsigned OpToUse = 0;
348 // Scan for the appropriate larger type to use.
350 NewOutTy = (MVT::ValueType)(NewOutTy+1);
351 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
353 // If the target supports FP_TO_SINT returning this type, use it.
354 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
356 case TargetLowering::Legal:
357 if (!TLI.isTypeLegal(NewOutTy))
358 break; // Can't use this datatype.
360 case TargetLowering::Custom:
361 OpToUse = ISD::FP_TO_SINT;
366 // If the target supports FP_TO_UINT of this type, use it.
367 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
369 case TargetLowering::Legal:
370 if (!TLI.isTypeLegal(NewOutTy))
371 break; // Can't use this datatype.
373 case TargetLowering::Custom:
374 OpToUse = ISD::FP_TO_UINT;
379 // Otherwise, try a larger type.
382 // Okay, we found the operation and type to use. Truncate the result of the
383 // extended FP_TO_*INT operation to the desired size.
384 SDOperand N = DAG.getNode(ISD::TRUNCATE, DestVT,
385 DAG.getNode(OpToUse, NewOutTy, LegalOp));
386 // Make sure to legalize any nodes we create here in the next pass.
387 return LegalizeOp(N);
390 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
391 /// not been visited yet and if all of its operands have already been visited.
392 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
393 std::map<SDNode*, unsigned> &Visited) {
394 if (++Visited[N] != N->getNumOperands())
395 return; // Haven't visited all operands yet
399 if (N->hasOneUse()) { // Tail recurse in common case.
400 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
404 // Now that we have N in, add anything that uses it if all of their operands
406 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
407 ComputeTopDownOrdering(*UI, Order, Visited);
411 void SelectionDAGLegalize::LegalizeDAG() {
412 // The legalize process is inherently a bottom-up recursive process (users
413 // legalize their uses before themselves). Given infinite stack space, we
414 // could just start legalizing on the root and traverse the whole graph. In
415 // practice however, this causes us to run out of stack space on large basic
416 // blocks. To avoid this problem, compute an ordering of the nodes where each
417 // node is only legalized after all of its operands are legalized.
418 std::map<SDNode*, unsigned> Visited;
419 std::vector<SDNode*> Order;
421 // Compute ordering from all of the leaves in the graphs, those (like the
422 // entry node) that have no operands.
423 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
424 E = DAG.allnodes_end(); I != E; ++I) {
425 if (I->getNumOperands() == 0) {
427 ComputeTopDownOrdering(I, Order, Visited);
431 assert(Order.size() == Visited.size() &&
433 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
434 "Error: DAG is cyclic!");
437 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
438 SDNode *N = Order[i];
439 switch (getTypeAction(N->getValueType(0))) {
440 default: assert(0 && "Bad type action!");
442 LegalizeOp(SDOperand(N, 0));
445 PromoteOp(SDOperand(N, 0));
449 ExpandOp(SDOperand(N, 0), X, Y);
455 // Finally, it's possible the root changed. Get the new root.
456 SDOperand OldRoot = DAG.getRoot();
457 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
458 DAG.setRoot(LegalizedNodes[OldRoot]);
460 ExpandedNodes.clear();
461 LegalizedNodes.clear();
462 PromotedNodes.clear();
464 // Remove dead nodes now.
465 DAG.RemoveDeadNodes(OldRoot.Val);
468 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
469 assert(isTypeLegal(Op.getValueType()) &&
470 "Caller should expand or promote operands that are not legal!");
471 SDNode *Node = Op.Val;
473 // If this operation defines any values that cannot be represented in a
474 // register on this target, make sure to expand or promote them.
475 if (Node->getNumValues() > 1) {
476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
477 switch (getTypeAction(Node->getValueType(i))) {
478 case Legal: break; // Nothing to do.
481 ExpandOp(Op.getValue(i), T1, T2);
482 assert(LegalizedNodes.count(Op) &&
483 "Expansion didn't add legal operands!");
484 return LegalizedNodes[Op];
487 PromoteOp(Op.getValue(i));
488 assert(LegalizedNodes.count(Op) &&
489 "Expansion didn't add legal operands!");
490 return LegalizedNodes[Op];
494 // Note that LegalizeOp may be reentered even from single-use nodes, which
495 // means that we always must cache transformed nodes.
496 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
497 if (I != LegalizedNodes.end()) return I->second;
499 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
501 SDOperand Result = Op;
503 switch (Node->getOpcode()) {
505 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
506 // If this is a target node, legalize it by legalizing the operands then
507 // passing it through.
508 std::vector<SDOperand> Ops;
509 bool Changed = false;
510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
511 Ops.push_back(LegalizeOp(Node->getOperand(i)));
512 Changed = Changed || Node->getOperand(i) != Ops.back();
515 if (Node->getNumValues() == 1)
516 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
518 std::vector<MVT::ValueType> VTs(Node->value_begin(),
520 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
523 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
524 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
525 return Result.getValue(Op.ResNo);
527 // Otherwise this is an unhandled builtin node. splat.
528 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
529 assert(0 && "Do not know how to legalize this operator!");
531 case ISD::EntryToken:
532 case ISD::FrameIndex:
533 case ISD::TargetFrameIndex:
535 case ISD::TargetConstant:
536 case ISD::TargetConstantPool:
537 case ISD::GlobalAddress:
538 case ISD::TargetGlobalAddress:
539 case ISD::ExternalSymbol:
540 case ISD::ConstantPool: // Nothing to do.
541 case ISD::BasicBlock:
546 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
547 default: assert(0 && "This action is not supported yet!");
548 case TargetLowering::Custom: {
549 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
551 Result = LegalizeOp(Tmp);
554 } // FALLTHROUGH if the target doesn't want to lower this op after all.
555 case TargetLowering::Legal:
556 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
560 case ISD::AssertSext:
561 case ISD::AssertZext:
562 Tmp1 = LegalizeOp(Node->getOperand(0));
563 if (Tmp1 != Node->getOperand(0))
564 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
565 Node->getOperand(1));
567 case ISD::MERGE_VALUES:
568 return LegalizeOp(Node->getOperand(Op.ResNo));
569 case ISD::CopyFromReg:
570 Tmp1 = LegalizeOp(Node->getOperand(0));
571 Result = Op.getValue(0);
572 if (Node->getNumValues() == 2) {
573 if (Tmp1 != Node->getOperand(0))
574 Result = DAG.getCopyFromReg(Tmp1,
575 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
576 Node->getValueType(0));
578 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
579 if (Node->getNumOperands() == 3)
580 Tmp2 = LegalizeOp(Node->getOperand(2));
581 if (Tmp1 != Node->getOperand(0) ||
582 (Node->getNumOperands() == 3 && Tmp2 != Node->getOperand(2)))
583 Result = DAG.getCopyFromReg(Tmp1,
584 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
585 Node->getValueType(0), Tmp2);
586 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
588 // Since CopyFromReg produces two values, make sure to remember that we
589 // legalized both of them.
590 AddLegalizedOperand(Op.getValue(0), Result);
591 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
592 return Result.getValue(Op.ResNo);
594 MVT::ValueType VT = Op.getValueType();
595 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
596 default: assert(0 && "This action is not supported yet!");
597 case TargetLowering::Expand:
598 case TargetLowering::Promote:
599 if (MVT::isInteger(VT))
600 Result = DAG.getConstant(0, VT);
601 else if (MVT::isFloatingPoint(VT))
602 Result = DAG.getConstantFP(0, VT);
604 assert(0 && "Unknown value type!");
606 case TargetLowering::Legal:
613 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
616 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
617 case TargetLowering::Promote:
618 default: assert(0 && "This action is not supported yet!");
619 case TargetLowering::Expand: {
620 if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other)) {
621 MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo();
622 std::vector<SDOperand> Ops;
623 Ops.push_back(Tmp1); // chain
624 Ops.push_back(Node->getOperand(1)); // line #
625 Ops.push_back(Node->getOperand(2)); // col #
626 const std::string &fname =
627 cast<StringSDNode>(Node->getOperand(3))->getValue();
628 const std::string &dirname =
629 cast<StringSDNode>(Node->getOperand(4))->getValue();
630 unsigned id = DebugInfo.RecordSource(fname, dirname);
631 Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id
632 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
634 Result = Tmp1; // chain
636 Result = LegalizeOp(Result); // Relegalize new nodes.
639 case TargetLowering::Legal:
640 if (Tmp1 != Node->getOperand(0) ||
641 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
642 std::vector<SDOperand> Ops;
644 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
645 Ops.push_back(Node->getOperand(1)); // line # must be legal.
646 Ops.push_back(Node->getOperand(2)); // col # must be legal.
648 // Otherwise promote them.
649 Ops.push_back(PromoteOp(Node->getOperand(1)));
650 Ops.push_back(PromoteOp(Node->getOperand(2)));
652 Ops.push_back(Node->getOperand(3)); // filename must be legal.
653 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
654 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
661 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
662 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
663 case TargetLowering::Promote:
664 case TargetLowering::Expand:
665 default: assert(0 && "This action is not supported yet!");
666 case TargetLowering::Legal:
667 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
668 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
669 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
670 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
672 if (Tmp1 != Node->getOperand(0) ||
673 Tmp2 != Node->getOperand(1) ||
674 Tmp3 != Node->getOperand(2) ||
675 Tmp4 != Node->getOperand(3)) {
676 Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4);
683 // We know we don't need to expand constants here, constants only have one
684 // value and we check that it is fine above.
686 // FIXME: Maybe we should handle things like targets that don't support full
687 // 32-bit immediates?
689 case ISD::ConstantFP: {
690 // Spill FP immediates to the constant pool if the target cannot directly
691 // codegen them. Targets often have some immediate values that can be
692 // efficiently generated into an FP register without a load. We explicitly
693 // leave these constants as ConstantFP nodes for the target to deal with.
695 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
697 // Check to see if this FP immediate is already legal.
698 bool isLegal = false;
699 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
700 E = TLI.legal_fpimm_end(); I != E; ++I)
701 if (CFP->isExactlyValue(*I)) {
707 // Otherwise we need to spill the constant to memory.
710 // If a FP immediate is precise when represented as a float, we put it
711 // into the constant pool as a float, even if it's is statically typed
713 MVT::ValueType VT = CFP->getValueType(0);
714 bool isDouble = VT == MVT::f64;
715 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
716 Type::FloatTy, CFP->getValue());
717 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
718 // Only do this if the target has a native EXTLOAD instruction from
720 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
721 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
727 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
729 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
730 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
732 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
733 DAG.getSrcValue(NULL));
738 case ISD::ConstantVec: {
739 // We assume that vector constants are not legal, and will be immediately
740 // spilled to the constant pool.
742 // FIXME: revisit this when we have some kind of mechanism by which targets
743 // can decided legality of vector constants, of which there may be very
746 // Create a ConstantPacked, and put it in the constant pool.
747 std::vector<Constant*> CV;
748 MVT::ValueType VT = Node->getValueType(0);
749 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
750 SDOperand OpN = Node->getOperand(I);
751 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
752 if (MVT::isFloatingPoint(VT))
753 CV.push_back(ConstantFP::get(OpNTy,
754 cast<ConstantFPSDNode>(OpN)->getValue()));
756 CV.push_back(ConstantUInt::get(OpNTy,
757 cast<ConstantSDNode>(OpN)->getValue()));
759 Constant *CP = ConstantPacked::get(CV);
760 SDOperand CPIdx = LegalizeOp(DAG.getConstantPool(CP, TLI.getPointerTy()));
761 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
764 case ISD::TokenFactor:
765 if (Node->getNumOperands() == 2) {
766 bool Changed = false;
767 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
768 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
769 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
770 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
772 std::vector<SDOperand> Ops;
773 bool Changed = false;
774 // Legalize the operands.
775 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
776 SDOperand Op = Node->getOperand(i);
777 Ops.push_back(LegalizeOp(Op));
778 Changed |= Ops[i] != Op;
781 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
785 case ISD::CALLSEQ_START:
786 case ISD::CALLSEQ_END:
787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
788 // Do not try to legalize the target-specific arguments (#1+)
789 Tmp2 = Node->getOperand(0);
791 Node->setAdjCallChain(Tmp1);
793 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
794 // nodes are treated specially and are mutated in place. This makes the dag
795 // legalization process more efficient and also makes libcall insertion
798 case ISD::DYNAMIC_STACKALLOC:
799 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
800 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
801 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
802 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
803 Tmp3 != Node->getOperand(2)) {
804 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
805 std::vector<SDOperand> Ops;
806 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
807 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
809 Result = Op.getValue(0);
811 // Since this op produces two values, make sure to remember that we
812 // legalized both of them.
813 AddLegalizedOperand(SDOperand(Node, 0), Result);
814 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
815 return Result.getValue(Op.ResNo);
819 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
820 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
822 bool Changed = false;
823 std::vector<SDOperand> Ops;
824 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
825 Ops.push_back(LegalizeOp(Node->getOperand(i)));
826 Changed |= Ops.back() != Node->getOperand(i);
829 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
830 std::vector<MVT::ValueType> RetTyVTs;
831 RetTyVTs.reserve(Node->getNumValues());
832 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
833 RetTyVTs.push_back(Node->getValueType(i));
834 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
835 Node->getOpcode() == ISD::TAILCALL), 0);
837 Result = Result.getValue(0);
839 // Since calls produce multiple values, make sure to remember that we
840 // legalized all of them.
841 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
842 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
843 return Result.getValue(Op.ResNo);
846 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
847 if (Tmp1 != Node->getOperand(0))
848 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
852 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
854 switch (getTypeAction(Node->getOperand(1).getValueType())) {
855 case Expand: assert(0 && "It's impossible to expand bools");
857 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
860 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
864 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
865 default: assert(0 && "This action is not supported yet!");
866 case TargetLowering::Expand:
867 // Expand brcond's setcc into its constituent parts and create a BR_CC
869 if (Tmp2.getOpcode() == ISD::SETCC) {
870 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
871 Tmp2.getOperand(0), Tmp2.getOperand(1),
872 Node->getOperand(2));
874 // Make sure the condition is either zero or one. It may have been
875 // promoted from something else.
876 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
878 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
879 DAG.getCondCode(ISD::SETNE), Tmp2,
880 DAG.getConstant(0, Tmp2.getValueType()),
881 Node->getOperand(2));
883 Result = LegalizeOp(Result); // Relegalize new nodes.
885 case TargetLowering::Custom: {
887 TLI.LowerOperation(DAG.getNode(ISD::BRCOND, Node->getValueType(0),
888 Tmp1, Tmp2, Node->getOperand(2)), DAG);
890 Result = LegalizeOp(Tmp);
893 // FALLTHROUGH if the target thinks it is legal.
895 case TargetLowering::Legal:
896 // Basic block destination (Op#2) is always legal.
897 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
898 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
899 Node->getOperand(2));
904 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
905 if (!isTypeLegal(Node->getOperand(2).getValueType())) {
906 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
907 Node->getOperand(2), // LHS
908 Node->getOperand(3), // RHS
909 Node->getOperand(1)));
910 // If we get a SETCC back from legalizing the SETCC node we just
911 // created, then use its LHS, RHS, and CC directly in creating a new
912 // node. Otherwise, select between the true and false value based on
913 // comparing the result of the legalized with zero.
914 if (Tmp2.getOpcode() == ISD::SETCC) {
915 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
916 Tmp2.getOperand(0), Tmp2.getOperand(1),
917 Node->getOperand(4));
919 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
920 DAG.getCondCode(ISD::SETNE),
921 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
922 Node->getOperand(4));
927 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
928 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
930 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
931 default: assert(0 && "Unexpected action for BR_CC!");
932 case TargetLowering::Custom: {
933 Tmp4 = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
934 Tmp2, Tmp3, Node->getOperand(4));
935 Tmp4 = TLI.LowerOperation(Tmp4, DAG);
937 Result = LegalizeOp(Tmp4);
940 } // FALLTHROUGH if the target doesn't want to lower this op after all.
941 case TargetLowering::Legal:
942 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
943 Tmp3 != Node->getOperand(3)) {
944 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
945 Tmp2, Tmp3, Node->getOperand(4));
950 case ISD::BRCONDTWOWAY:
951 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
952 switch (getTypeAction(Node->getOperand(1).getValueType())) {
953 case Expand: assert(0 && "It's impossible to expand bools");
955 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
958 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
961 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
963 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
964 case TargetLowering::Promote:
965 default: assert(0 && "This action is not supported yet!");
966 case TargetLowering::Legal:
967 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
968 std::vector<SDOperand> Ops;
971 Ops.push_back(Node->getOperand(2));
972 Ops.push_back(Node->getOperand(3));
973 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
976 case TargetLowering::Expand:
977 // If BRTWOWAY_CC is legal for this target, then simply expand this node
978 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
980 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
981 if (Tmp2.getOpcode() == ISD::SETCC) {
982 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
983 Tmp2.getOperand(0), Tmp2.getOperand(1),
984 Node->getOperand(2), Node->getOperand(3));
986 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
987 DAG.getConstant(0, Tmp2.getValueType()),
988 Node->getOperand(2), Node->getOperand(3));
991 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
992 Node->getOperand(2));
993 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
995 Result = LegalizeOp(Result); // Relegalize new nodes.
999 case ISD::BRTWOWAY_CC:
1000 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1001 if (isTypeLegal(Node->getOperand(2).getValueType())) {
1002 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
1003 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
1004 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1005 Tmp3 != Node->getOperand(3)) {
1006 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
1007 Node->getOperand(4), Node->getOperand(5));
1011 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1012 Node->getOperand(2), // LHS
1013 Node->getOperand(3), // RHS
1014 Node->getOperand(1)));
1015 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
1017 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
1018 default: assert(0 && "This action is not supported yet!");
1019 case TargetLowering::Legal:
1020 // If we get a SETCC back from legalizing the SETCC node we just
1021 // created, then use its LHS, RHS, and CC directly in creating a new
1022 // node. Otherwise, select between the true and false value based on
1023 // comparing the result of the legalized with zero.
1024 if (Tmp2.getOpcode() == ISD::SETCC) {
1025 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
1026 Tmp2.getOperand(0), Tmp2.getOperand(1),
1027 Node->getOperand(4), Node->getOperand(5));
1029 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
1030 DAG.getConstant(0, Tmp2.getValueType()),
1031 Node->getOperand(4), Node->getOperand(5));
1034 case TargetLowering::Expand:
1035 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
1036 Node->getOperand(4));
1037 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
1040 Result = LegalizeOp(Result); // Relegalize new nodes.
1044 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1045 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1047 if (Tmp1 != Node->getOperand(0) ||
1048 Tmp2 != Node->getOperand(1))
1049 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
1050 Node->getOperand(2));
1052 Result = SDOperand(Node, 0);
1054 // Since loads produce two values, make sure to remember that we legalized
1056 AddLegalizedOperand(SDOperand(Node, 0), Result);
1057 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1058 return Result.getValue(Op.ResNo);
1062 case ISD::ZEXTLOAD: {
1063 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1064 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1066 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1067 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1068 default: assert(0 && "This action is not supported yet!");
1069 case TargetLowering::Promote:
1070 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1071 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1072 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
1073 // Since loads produce two values, make sure to remember that we legalized
1075 AddLegalizedOperand(SDOperand(Node, 0), Result);
1076 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1077 return Result.getValue(Op.ResNo);
1079 case TargetLowering::Legal:
1080 if (Tmp1 != Node->getOperand(0) ||
1081 Tmp2 != Node->getOperand(1))
1082 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1083 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1085 Result = SDOperand(Node, 0);
1087 // Since loads produce two values, make sure to remember that we legalized
1089 AddLegalizedOperand(SDOperand(Node, 0), Result);
1090 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1091 return Result.getValue(Op.ResNo);
1092 case TargetLowering::Expand:
1093 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1094 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1095 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1096 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1097 Result = LegalizeOp(Result); // Relegalize new nodes.
1098 Load = LegalizeOp(Load);
1099 AddLegalizedOperand(SDOperand(Node, 0), Result);
1100 AddLegalizedOperand(SDOperand(Node, 1), Load.getValue(1));
1102 return Load.getValue(1);
1105 assert(Node->getOpcode() != ISD::EXTLOAD &&
1106 "EXTLOAD should always be supported!");
1107 // Turn the unsupported load into an EXTLOAD followed by an explicit
1108 // zero/sign extend inreg.
1109 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1110 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1112 if (Node->getOpcode() == ISD::SEXTLOAD)
1113 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1114 Result, DAG.getValueType(SrcVT));
1116 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1117 Result = LegalizeOp(Result); // Relegalize new nodes.
1118 ValRes = LegalizeOp(ValRes); // Relegalize new nodes.
1119 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1120 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1122 return Result.getValue(1);
1125 assert(0 && "Unreachable");
1127 case ISD::EXTRACT_ELEMENT: {
1128 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1129 switch (getTypeAction(OpTy)) {
1131 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1134 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1136 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1137 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1138 TLI.getShiftAmountTy()));
1139 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1142 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1143 Node->getOperand(0));
1145 Result = LegalizeOp(Result);
1148 // Get both the low and high parts.
1149 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1150 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1151 Result = Tmp2; // 1 -> Hi
1153 Result = Tmp1; // 0 -> Lo
1159 case ISD::CopyToReg:
1160 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1162 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1163 "Register type must be legal!");
1164 // Legalize the incoming value (must be a legal type).
1165 Tmp2 = LegalizeOp(Node->getOperand(2));
1166 if (Node->getNumValues() == 1) {
1167 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1168 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1169 Node->getOperand(1), Tmp2);
1171 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1172 if (Node->getNumOperands() == 4)
1173 Tmp3 = LegalizeOp(Node->getOperand(3));
1174 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
1175 (Node->getNumOperands() == 4 && Tmp3 != Node->getOperand(3))) {
1176 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
1177 Result = DAG.getCopyToReg(Tmp1, Reg, Tmp2, Tmp3);
1180 // Since this produces two values, make sure to remember that we legalized
1182 AddLegalizedOperand(SDOperand(Node, 0), Result);
1183 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1184 return Result.getValue(Op.ResNo);
1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1190 switch (Node->getNumOperands()) {
1192 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1194 Tmp2 = LegalizeOp(Node->getOperand(1));
1195 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1196 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1200 ExpandOp(Node->getOperand(1), Lo, Hi);
1201 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1205 Tmp2 = PromoteOp(Node->getOperand(1));
1206 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1211 if (Tmp1 != Node->getOperand(0))
1212 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1214 default: { // ret <values>
1215 std::vector<SDOperand> NewValues;
1216 NewValues.push_back(Tmp1);
1217 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1218 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1220 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1224 ExpandOp(Node->getOperand(i), Lo, Hi);
1225 NewValues.push_back(Lo);
1226 NewValues.push_back(Hi);
1230 assert(0 && "Can't promote multiple return value yet!");
1232 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1238 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1239 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1241 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1242 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1243 if (CFP->getValueType(0) == MVT::f32) {
1244 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1245 DAG.getConstant(FloatToBits(CFP->getValue()),
1248 Node->getOperand(3));
1250 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1251 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1252 DAG.getConstant(DoubleToBits(CFP->getValue()),
1255 Node->getOperand(3));
1260 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1262 SDOperand Val = LegalizeOp(Node->getOperand(1));
1263 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1264 Tmp2 != Node->getOperand(2))
1265 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1266 Node->getOperand(3));
1270 // Truncate the value and store the result.
1271 Tmp3 = PromoteOp(Node->getOperand(1));
1272 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1273 Node->getOperand(3),
1274 DAG.getValueType(Node->getOperand(1).getValueType()));
1279 unsigned IncrementSize;
1280 ExpandOp(Node->getOperand(1), Lo, Hi);
1282 if (!TLI.isLittleEndian())
1285 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1286 Node->getOperand(3));
1287 // If this is a vector type, then we have to calculate the increment as
1288 // the product of the element size in bytes, and the number of elements
1289 // in the high half of the vector.
1290 if (MVT::Vector == Hi.getValueType()) {
1291 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1292 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1293 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1295 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1297 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1298 getIntPtrConstant(IncrementSize));
1299 assert(isTypeLegal(Tmp2.getValueType()) &&
1300 "Pointers must be legal!");
1301 //Again, claiming both parts of the store came form the same Instr
1302 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1303 Node->getOperand(3));
1304 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1309 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1310 if (Tmp1 != Node->getOperand(0))
1311 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1313 case ISD::READCYCLECOUNTER:
1314 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1315 if (Tmp1 != Node->getOperand(0)) {
1316 std::vector<MVT::ValueType> rtypes;
1317 std::vector<SDOperand> rvals;
1318 rtypes.push_back(MVT::i64);
1319 rtypes.push_back(MVT::Other);
1320 rvals.push_back(Tmp1);
1321 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
1324 // Since rdcc produce two values, make sure to remember that we legalized
1326 AddLegalizedOperand(SDOperand(Node, 0), Result);
1327 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1328 return Result.getValue(Op.ResNo);
1330 case ISD::TRUNCSTORE:
1331 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1332 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1334 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1336 Tmp2 = LegalizeOp(Node->getOperand(1));
1338 // The only promote case we handle is TRUNCSTORE:i1 X into
1339 // -> TRUNCSTORE:i8 (and X, 1)
1340 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1341 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1342 TargetLowering::Promote) {
1343 // Promote the bool to a mask then store.
1344 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1345 DAG.getConstant(1, Tmp2.getValueType()));
1346 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1347 Node->getOperand(3), DAG.getValueType(MVT::i8));
1349 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1350 Tmp3 != Node->getOperand(2)) {
1351 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1352 Node->getOperand(3), Node->getOperand(4));
1357 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1361 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1362 case Expand: assert(0 && "It's impossible to expand bools");
1364 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1367 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1370 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1371 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1373 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1374 default: assert(0 && "This action is not supported yet!");
1375 case TargetLowering::Expand:
1376 if (Tmp1.getOpcode() == ISD::SETCC) {
1377 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1379 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1381 // Make sure the condition is either zero or one. It may have been
1382 // promoted from something else.
1383 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1384 Result = DAG.getSelectCC(Tmp1,
1385 DAG.getConstant(0, Tmp1.getValueType()),
1386 Tmp2, Tmp3, ISD::SETNE);
1388 Result = LegalizeOp(Result); // Relegalize new nodes.
1390 case TargetLowering::Custom: {
1392 TLI.LowerOperation(DAG.getNode(ISD::SELECT, Node->getValueType(0),
1393 Tmp1, Tmp2, Tmp3), DAG);
1395 Result = LegalizeOp(Tmp);
1398 // FALLTHROUGH if the target thinks it is legal.
1400 case TargetLowering::Legal:
1401 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1402 Tmp3 != Node->getOperand(2))
1403 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1406 case TargetLowering::Promote: {
1407 MVT::ValueType NVT =
1408 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1409 unsigned ExtOp, TruncOp;
1410 if (MVT::isInteger(Tmp2.getValueType())) {
1411 ExtOp = ISD::ANY_EXTEND;
1412 TruncOp = ISD::TRUNCATE;
1414 ExtOp = ISD::FP_EXTEND;
1415 TruncOp = ISD::FP_ROUND;
1417 // Promote each of the values to the new type.
1418 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1419 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1420 // Perform the larger operation, then round down.
1421 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1422 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1427 case ISD::SELECT_CC:
1428 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1429 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1431 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1432 // Everything is legal, see if we should expand this op or something.
1433 switch (TLI.getOperationAction(ISD::SELECT_CC,
1434 Node->getOperand(0).getValueType())) {
1435 default: assert(0 && "This action is not supported yet!");
1436 case TargetLowering::Custom: {
1438 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1439 Node->getOperand(0),
1440 Node->getOperand(1), Tmp3, Tmp4,
1441 Node->getOperand(4)), DAG);
1443 Result = LegalizeOp(Tmp);
1446 } // FALLTHROUGH if the target can't lower this operation after all.
1447 case TargetLowering::Legal:
1448 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1449 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1450 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1451 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1452 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1,Tmp2,
1453 Tmp3, Tmp4, Node->getOperand(4));
1459 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1460 Node->getOperand(0), // LHS
1461 Node->getOperand(1), // RHS
1462 Node->getOperand(4)));
1463 // If we get a SETCC back from legalizing the SETCC node we just
1464 // created, then use its LHS, RHS, and CC directly in creating a new
1465 // node. Otherwise, select between the true and false value based on
1466 // comparing the result of the legalized with zero.
1467 if (Tmp1.getOpcode() == ISD::SETCC) {
1468 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1469 Tmp1.getOperand(0), Tmp1.getOperand(1),
1470 Tmp3, Tmp4, Tmp1.getOperand(2));
1472 Result = DAG.getSelectCC(Tmp1,
1473 DAG.getConstant(0, Tmp1.getValueType()),
1474 Tmp3, Tmp4, ISD::SETNE);
1479 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1481 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1482 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1485 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1486 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1488 // If this is an FP compare, the operands have already been extended.
1489 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1490 MVT::ValueType VT = Node->getOperand(0).getValueType();
1491 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1493 // Otherwise, we have to insert explicit sign or zero extends. Note
1494 // that we could insert sign extends for ALL conditions, but zero extend
1495 // is cheaper on many machines (an AND instead of two shifts), so prefer
1497 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1498 default: assert(0 && "Unknown integer comparison!");
1505 // ALL of these operations will work if we either sign or zero extend
1506 // the operands (including the unsigned comparisons!). Zero extend is
1507 // usually a simpler/cheaper operation, so prefer it.
1508 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1509 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1515 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1516 DAG.getValueType(VT));
1517 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1518 DAG.getValueType(VT));
1524 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1525 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1526 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1527 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1531 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1532 if (RHSCST->isAllOnesValue()) {
1533 // Comparison to -1.
1534 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1539 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1540 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1541 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1542 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1545 // If this is a comparison of the sign bit, just look at the top part.
1547 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1548 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1549 CST->getValue() == 0) || // X < 0
1550 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1551 (CST->isAllOnesValue()))) { // X > -1
1557 // FIXME: This generated code sucks.
1558 ISD::CondCode LowCC;
1559 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1560 default: assert(0 && "Unknown integer setcc!");
1562 case ISD::SETULT: LowCC = ISD::SETULT; break;
1564 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1566 case ISD::SETULE: LowCC = ISD::SETULE; break;
1568 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1571 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1572 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1573 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1575 // NOTE: on targets without efficient SELECT of bools, we can always use
1576 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1577 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1578 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1579 Node->getOperand(2));
1580 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1581 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1582 Result, Tmp1, Tmp2));
1583 AddLegalizedOperand(SDOperand(Node, 0), Result);
1588 switch(TLI.getOperationAction(ISD::SETCC,
1589 Node->getOperand(0).getValueType())) {
1591 assert(0 && "Cannot handle this action for SETCC yet!");
1593 case TargetLowering::Promote: {
1594 // First step, figure out the appropriate operation to use.
1595 // Allow SETCC to not be supported for all legal data types
1596 // Mostly this targets FP
1597 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1598 MVT::ValueType OldVT = NewInTy;
1600 // Scan for the appropriate larger type to use.
1602 NewInTy = (MVT::ValueType)(NewInTy+1);
1604 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1605 "Fell off of the edge of the integer world");
1606 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1607 "Fell off of the edge of the floating point world");
1609 // If the target supports SETCC of this type, use it.
1610 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1613 if (MVT::isInteger(NewInTy))
1614 assert(0 && "Cannot promote Legal Integer SETCC yet");
1616 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1617 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1620 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1621 Node->getOperand(2));
1624 case TargetLowering::Custom: {
1626 TLI.LowerOperation(DAG.getNode(ISD::SETCC, Node->getValueType(0),
1627 Tmp1, Tmp2, Node->getOperand(2)), DAG);
1629 Result = LegalizeOp(Tmp);
1632 // FALLTHROUGH if the target thinks it is legal.
1634 case TargetLowering::Legal:
1635 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1636 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1637 Node->getOperand(2));
1639 case TargetLowering::Expand:
1640 // Expand a setcc node into a select_cc of the same condition, lhs, and
1641 // rhs that selects between const 1 (true) and const 0 (false).
1642 MVT::ValueType VT = Node->getValueType(0);
1643 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1644 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1645 Node->getOperand(2));
1646 Result = LegalizeOp(Result);
1653 case ISD::MEMMOVE: {
1654 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1655 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1657 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1658 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1659 case Expand: assert(0 && "Cannot expand a byte!");
1661 Tmp3 = LegalizeOp(Node->getOperand(2));
1664 Tmp3 = PromoteOp(Node->getOperand(2));
1668 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1672 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1674 // Length is too big, just take the lo-part of the length.
1676 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1680 Tmp4 = LegalizeOp(Node->getOperand(3));
1683 Tmp4 = PromoteOp(Node->getOperand(3));
1688 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1689 case Expand: assert(0 && "Cannot expand this yet!");
1691 Tmp5 = LegalizeOp(Node->getOperand(4));
1694 Tmp5 = PromoteOp(Node->getOperand(4));
1698 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1699 default: assert(0 && "This action not implemented for this operation!");
1700 case TargetLowering::Custom: {
1702 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1703 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1705 Result = LegalizeOp(Tmp);
1708 // FALLTHROUGH if the target thinks it is legal.
1710 case TargetLowering::Legal:
1711 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1712 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1713 Tmp5 != Node->getOperand(4)) {
1714 std::vector<SDOperand> Ops;
1715 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1716 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1717 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1720 case TargetLowering::Expand: {
1721 // Otherwise, the target does not support this operation. Lower the
1722 // operation to an explicit libcall as appropriate.
1723 MVT::ValueType IntPtr = TLI.getPointerTy();
1724 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1725 std::vector<std::pair<SDOperand, const Type*> > Args;
1727 const char *FnName = 0;
1728 if (Node->getOpcode() == ISD::MEMSET) {
1729 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1730 // Extend the ubyte argument to be an int value for the call.
1731 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1732 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1733 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1736 } else if (Node->getOpcode() == ISD::MEMCPY ||
1737 Node->getOpcode() == ISD::MEMMOVE) {
1738 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1739 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1740 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1741 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1743 assert(0 && "Unknown op!");
1746 std::pair<SDOperand,SDOperand> CallResult =
1747 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1748 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1749 Result = LegalizeOp(CallResult.second);
1757 Tmp1 = LegalizeOp(Node->getOperand(0));
1758 Tmp2 = LegalizeOp(Node->getOperand(1));
1760 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1761 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1762 std::vector<SDOperand> Ops;
1763 Ops.push_back(Tmp1);
1764 Ops.push_back(Tmp2);
1765 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1767 Result = SDOperand(Node, 0);
1768 // Since these produce two values, make sure to remember that we legalized
1770 AddLegalizedOperand(SDOperand(Node, 0), Result);
1771 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1772 return Result.getValue(Op.ResNo);
1773 case ISD::WRITEPORT:
1774 Tmp1 = LegalizeOp(Node->getOperand(0));
1775 Tmp2 = LegalizeOp(Node->getOperand(1));
1776 Tmp3 = LegalizeOp(Node->getOperand(2));
1777 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1778 Tmp3 != Node->getOperand(2))
1779 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1783 Tmp1 = LegalizeOp(Node->getOperand(0));
1784 Tmp2 = LegalizeOp(Node->getOperand(1));
1786 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1787 case TargetLowering::Custom:
1788 default: assert(0 && "This action not implemented for this operation!");
1789 case TargetLowering::Legal:
1790 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1791 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1792 std::vector<SDOperand> Ops;
1793 Ops.push_back(Tmp1);
1794 Ops.push_back(Tmp2);
1795 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1797 Result = SDOperand(Node, 0);
1799 case TargetLowering::Expand:
1800 // Replace this with a load from memory.
1801 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1802 Node->getOperand(1), DAG.getSrcValue(NULL));
1803 Result = LegalizeOp(Result);
1807 // Since these produce two values, make sure to remember that we legalized
1809 AddLegalizedOperand(SDOperand(Node, 0), Result);
1810 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1811 return Result.getValue(Op.ResNo);
1814 Tmp1 = LegalizeOp(Node->getOperand(0));
1815 Tmp2 = LegalizeOp(Node->getOperand(1));
1816 Tmp3 = LegalizeOp(Node->getOperand(2));
1818 switch (TLI.getOperationAction(Node->getOpcode(),
1819 Node->getOperand(1).getValueType())) {
1820 case TargetLowering::Custom:
1821 default: assert(0 && "This action not implemented for this operation!");
1822 case TargetLowering::Legal:
1823 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1824 Tmp3 != Node->getOperand(2))
1825 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1827 case TargetLowering::Expand:
1828 // Replace this with a store to memory.
1829 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1830 Node->getOperand(1), Node->getOperand(2),
1831 DAG.getSrcValue(NULL));
1832 Result = LegalizeOp(Result);
1837 case ISD::ADD_PARTS:
1838 case ISD::SUB_PARTS:
1839 case ISD::SHL_PARTS:
1840 case ISD::SRA_PARTS:
1841 case ISD::SRL_PARTS: {
1842 std::vector<SDOperand> Ops;
1843 bool Changed = false;
1844 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1845 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1846 Changed |= Ops.back() != Node->getOperand(i);
1849 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1850 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1853 // Since these produce multiple values, make sure to remember that we
1854 // legalized all of them.
1855 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1856 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1857 return Result.getValue(Op.ResNo);
1878 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1879 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1880 case Expand: assert(0 && "Not possible");
1882 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1885 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1888 if (Tmp1 != Node->getOperand(0) ||
1889 Tmp2 != Node->getOperand(1))
1890 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1893 case ISD::BUILD_PAIR: {
1894 MVT::ValueType PairTy = Node->getValueType(0);
1895 // TODO: handle the case where the Lo and Hi operands are not of legal type
1896 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1897 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1898 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1899 case TargetLowering::Legal:
1900 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1901 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1903 case TargetLowering::Promote:
1904 case TargetLowering::Custom:
1905 assert(0 && "Cannot promote/custom this yet!");
1906 case TargetLowering::Expand:
1907 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
1908 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
1909 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
1910 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
1911 TLI.getShiftAmountTy()));
1912 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
1921 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1922 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1923 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1924 case TargetLowering::Legal:
1925 if (Tmp1 != Node->getOperand(0) ||
1926 Tmp2 != Node->getOperand(1))
1927 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1930 case TargetLowering::Promote:
1931 case TargetLowering::Custom:
1932 assert(0 && "Cannot promote/custom handle this yet!");
1933 case TargetLowering::Expand:
1934 if (MVT::isInteger(Node->getValueType(0))) {
1935 MVT::ValueType VT = Node->getValueType(0);
1936 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1937 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1938 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1939 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1941 // Floating point mod -> fmod libcall.
1942 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1944 Result = ExpandLibCall(FnName, Node, Dummy);
1953 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1954 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1955 case TargetLowering::Legal:
1956 if (Tmp1 != Node->getOperand(0))
1957 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1959 case TargetLowering::Promote: {
1960 MVT::ValueType OVT = Tmp1.getValueType();
1961 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1963 // Zero extend the argument.
1964 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1965 // Perform the larger operation, then subtract if needed.
1966 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1967 switch(Node->getOpcode())
1973 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1974 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
1975 DAG.getConstant(getSizeInBits(NVT), NVT),
1977 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1978 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1981 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1982 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1983 DAG.getConstant(getSizeInBits(NVT) -
1984 getSizeInBits(OVT), NVT));
1989 case TargetLowering::Custom:
1990 assert(0 && "Cannot custom handle this yet!");
1991 case TargetLowering::Expand:
1992 switch(Node->getOpcode())
1995 static const uint64_t mask[6] = {
1996 0x5555555555555555ULL, 0x3333333333333333ULL,
1997 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1998 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2000 MVT::ValueType VT = Tmp1.getValueType();
2001 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2002 unsigned len = getSizeInBits(VT);
2003 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2004 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2005 Tmp2 = DAG.getConstant(mask[i], VT);
2006 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2007 Tmp1 = DAG.getNode(ISD::ADD, VT,
2008 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
2009 DAG.getNode(ISD::AND, VT,
2010 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
2017 /* for now, we do this:
2022 x = x | (x >>32); // for 64-bit input
2023 return popcount(~x);
2025 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
2026 MVT::ValueType VT = Tmp1.getValueType();
2027 MVT::ValueType ShVT = TLI.getShiftAmountTy();
2028 unsigned len = getSizeInBits(VT);
2029 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2030 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2031 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
2032 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
2034 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
2035 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2039 // for now, we use: { return popcount(~x & (x - 1)); }
2040 // unless the target has ctlz but not ctpop, in which case we use:
2041 // { return 32 - nlz(~x & (x-1)); }
2042 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2043 MVT::ValueType VT = Tmp1.getValueType();
2044 Tmp2 = DAG.getConstant(~0ULL, VT);
2045 Tmp3 = DAG.getNode(ISD::AND, VT,
2046 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
2047 DAG.getNode(ISD::SUB, VT, Tmp1,
2048 DAG.getConstant(1, VT)));
2049 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
2050 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
2051 TLI.isOperationLegal(ISD::CTLZ, VT)) {
2052 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
2053 DAG.getConstant(getSizeInBits(VT), VT),
2054 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
2056 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
2061 assert(0 && "Cannot expand this yet!");
2074 Tmp1 = LegalizeOp(Node->getOperand(0));
2075 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2076 case TargetLowering::Legal:
2077 if (Tmp1 != Node->getOperand(0))
2078 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2080 case TargetLowering::Promote:
2081 case TargetLowering::Custom:
2082 assert(0 && "Cannot promote/custom handle this yet!");
2083 case TargetLowering::Expand:
2084 switch(Node->getOpcode()) {
2086 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2087 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2088 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
2093 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2094 MVT::ValueType VT = Node->getValueType(0);
2095 Tmp2 = DAG.getConstantFP(0.0, VT);
2096 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2097 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2098 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2099 Result = LegalizeOp(Result);
2105 MVT::ValueType VT = Node->getValueType(0);
2106 const char *FnName = 0;
2107 switch(Node->getOpcode()) {
2108 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2109 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2110 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2111 default: assert(0 && "Unreachable!");
2114 Result = ExpandLibCall(FnName, Node, Dummy);
2118 assert(0 && "Unreachable!");
2124 case ISD::BIT_CONVERT:
2125 if (!isTypeLegal(Node->getOperand(0).getValueType()))
2126 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2128 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2129 Node->getOperand(0).getValueType())) {
2130 default: assert(0 && "Unknown operation action!");
2131 case TargetLowering::Expand:
2132 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2134 case TargetLowering::Legal:
2135 Tmp1 = LegalizeOp(Node->getOperand(0));
2136 if (Tmp1 != Node->getOperand(0))
2137 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Tmp1);
2142 // Conversion operators. The source and destination have different types.
2143 case ISD::SINT_TO_FP:
2144 case ISD::UINT_TO_FP: {
2145 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2146 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2148 switch (TLI.getOperationAction(Node->getOpcode(),
2149 Node->getOperand(0).getValueType())) {
2150 default: assert(0 && "Unknown operation action!");
2151 case TargetLowering::Expand:
2152 Result = ExpandLegalINT_TO_FP(isSigned,
2153 LegalizeOp(Node->getOperand(0)),
2154 Node->getValueType(0));
2155 AddLegalizedOperand(Op, Result);
2157 case TargetLowering::Promote:
2158 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2159 Node->getValueType(0),
2161 AddLegalizedOperand(Op, Result);
2163 case TargetLowering::Legal:
2165 case TargetLowering::Custom: {
2166 Tmp1 = LegalizeOp(Node->getOperand(0));
2168 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2169 Tmp = TLI.LowerOperation(Tmp, DAG);
2171 Tmp = LegalizeOp(Tmp); // Relegalize input.
2172 AddLegalizedOperand(Op, Tmp);
2175 assert(0 && "Target Must Lower this");
2180 Tmp1 = LegalizeOp(Node->getOperand(0));
2181 if (Tmp1 != Node->getOperand(0))
2182 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2185 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2186 Node->getValueType(0), Node->getOperand(0));
2190 Result = PromoteOp(Node->getOperand(0));
2191 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2192 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
2193 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
2195 Result = PromoteOp(Node->getOperand(0));
2196 Result = DAG.getZeroExtendInReg(Result,
2197 Node->getOperand(0).getValueType());
2198 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
2205 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2207 Tmp1 = LegalizeOp(Node->getOperand(0));
2208 if (Tmp1 != Node->getOperand(0))
2209 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2212 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2214 // Since the result is legal, we should just be able to truncate the low
2215 // part of the source.
2216 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2219 Result = PromoteOp(Node->getOperand(0));
2220 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2225 case ISD::FP_TO_SINT:
2226 case ISD::FP_TO_UINT:
2227 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2229 Tmp1 = LegalizeOp(Node->getOperand(0));
2231 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2232 default: assert(0 && "Unknown operation action!");
2233 case TargetLowering::Expand:
2234 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2235 SDOperand True, False;
2236 MVT::ValueType VT = Node->getOperand(0).getValueType();
2237 MVT::ValueType NVT = Node->getValueType(0);
2238 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2239 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2240 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2241 Node->getOperand(0), Tmp2, ISD::SETLT);
2242 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2243 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2244 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2246 False = DAG.getNode(ISD::XOR, NVT, False,
2247 DAG.getConstant(1ULL << ShiftAmt, NVT));
2248 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2249 AddLegalizedOperand(SDOperand(Node, 0), Result);
2252 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2255 case TargetLowering::Promote:
2256 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2257 Node->getOpcode() == ISD::FP_TO_SINT);
2258 AddLegalizedOperand(Op, Result);
2260 case TargetLowering::Custom: {
2262 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2263 Tmp = TLI.LowerOperation(Tmp, DAG);
2265 Tmp = LegalizeOp(Tmp);
2266 AddLegalizedOperand(Op, Tmp);
2269 // The target thinks this is legal afterall.
2273 case TargetLowering::Legal:
2277 if (Tmp1 != Node->getOperand(0))
2278 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2281 assert(0 && "Shouldn't need to expand other operators here!");
2283 Result = PromoteOp(Node->getOperand(0));
2284 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2289 case ISD::ANY_EXTEND:
2290 case ISD::ZERO_EXTEND:
2291 case ISD::SIGN_EXTEND:
2292 case ISD::FP_EXTEND:
2294 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2296 Tmp1 = LegalizeOp(Node->getOperand(0));
2297 if (Tmp1 != Node->getOperand(0))
2298 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2301 assert(0 && "Shouldn't need to expand other operators here!");
2304 switch (Node->getOpcode()) {
2305 case ISD::ANY_EXTEND:
2306 Result = PromoteOp(Node->getOperand(0));
2307 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2309 case ISD::ZERO_EXTEND:
2310 Result = PromoteOp(Node->getOperand(0));
2311 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2312 Result = DAG.getZeroExtendInReg(Result,
2313 Node->getOperand(0).getValueType());
2315 case ISD::SIGN_EXTEND:
2316 Result = PromoteOp(Node->getOperand(0));
2317 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2318 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2320 DAG.getValueType(Node->getOperand(0).getValueType()));
2322 case ISD::FP_EXTEND:
2323 Result = PromoteOp(Node->getOperand(0));
2324 if (Result.getValueType() != Op.getValueType())
2325 // Dynamically dead while we have only 2 FP types.
2326 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2329 Result = PromoteOp(Node->getOperand(0));
2330 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2335 case ISD::FP_ROUND_INREG:
2336 case ISD::SIGN_EXTEND_INREG: {
2337 Tmp1 = LegalizeOp(Node->getOperand(0));
2338 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2340 // If this operation is not supported, convert it to a shl/shr or load/store
2342 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2343 default: assert(0 && "This action not supported for this op yet!");
2344 case TargetLowering::Legal:
2345 if (Tmp1 != Node->getOperand(0))
2346 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2347 DAG.getValueType(ExtraVT));
2349 case TargetLowering::Expand:
2350 // If this is an integer extend and shifts are supported, do that.
2351 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2352 // NOTE: we could fall back on load/store here too for targets without
2353 // SAR. However, it is doubtful that any exist.
2354 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2355 MVT::getSizeInBits(ExtraVT);
2356 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2357 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2358 Node->getOperand(0), ShiftCst);
2359 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2361 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2362 // The only way we can lower this is to turn it into a STORETRUNC,
2363 // EXTLOAD pair, targetting a temporary location (a stack slot).
2365 // NOTE: there is a choice here between constantly creating new stack
2366 // slots and always reusing the same one. We currently always create
2367 // new ones, as reuse may inhibit scheduling.
2368 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2369 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2370 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2371 MachineFunction &MF = DAG.getMachineFunction();
2373 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2374 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2375 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2376 Node->getOperand(0), StackSlot,
2377 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2378 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2379 Result, StackSlot, DAG.getSrcValue(NULL),
2382 assert(0 && "Unknown op");
2384 Result = LegalizeOp(Result);
2391 // Note that LegalizeOp may be reentered even from single-use nodes, which
2392 // means that we always must cache transformed nodes.
2393 AddLegalizedOperand(Op, Result);
2397 /// PromoteOp - Given an operation that produces a value in an invalid type,
2398 /// promote it to compute the value into a larger type. The produced value will
2399 /// have the correct bits for the low portion of the register, but no guarantee
2400 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2401 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2402 MVT::ValueType VT = Op.getValueType();
2403 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2404 assert(getTypeAction(VT) == Promote &&
2405 "Caller should expand or legalize operands that are not promotable!");
2406 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2407 "Cannot promote to smaller type!");
2409 SDOperand Tmp1, Tmp2, Tmp3;
2412 SDNode *Node = Op.Val;
2414 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2415 if (I != PromotedNodes.end()) return I->second;
2417 // Promotion needs an optimization step to clean up after it, and is not
2418 // careful to avoid operations the target does not support. Make sure that
2419 // all generated operations are legalized in the next iteration.
2420 NeedsAnotherIteration = true;
2422 switch (Node->getOpcode()) {
2423 case ISD::CopyFromReg:
2424 assert(0 && "CopyFromReg must be legal!");
2426 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2427 assert(0 && "Do not know how to promote this operator!");
2430 Result = DAG.getNode(ISD::UNDEF, NVT);
2434 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2436 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2437 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2439 case ISD::ConstantFP:
2440 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2441 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2445 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2446 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2447 Node->getOperand(1), Node->getOperand(2));
2448 Result = LegalizeOp(Result);
2452 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2454 Result = LegalizeOp(Node->getOperand(0));
2455 assert(Result.getValueType() >= NVT &&
2456 "This truncation doesn't make sense!");
2457 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2458 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2461 // The truncation is not required, because we don't guarantee anything
2462 // about high bits anyway.
2463 Result = PromoteOp(Node->getOperand(0));
2466 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2467 // Truncate the low part of the expanded value to the result type
2468 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2471 case ISD::SIGN_EXTEND:
2472 case ISD::ZERO_EXTEND:
2473 case ISD::ANY_EXTEND:
2474 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2475 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2477 // Input is legal? Just do extend all the way to the larger type.
2478 Result = LegalizeOp(Node->getOperand(0));
2479 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2482 // Promote the reg if it's smaller.
2483 Result = PromoteOp(Node->getOperand(0));
2484 // The high bits are not guaranteed to be anything. Insert an extend.
2485 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2486 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2487 DAG.getValueType(Node->getOperand(0).getValueType()));
2488 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2489 Result = DAG.getZeroExtendInReg(Result,
2490 Node->getOperand(0).getValueType());
2494 case ISD::BIT_CONVERT:
2495 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2496 Result = PromoteOp(Result);
2499 case ISD::FP_EXTEND:
2500 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2502 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2503 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2504 case Promote: assert(0 && "Unreachable with 2 FP types!");
2506 // Input is legal? Do an FP_ROUND_INREG.
2507 Result = LegalizeOp(Node->getOperand(0));
2508 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2509 DAG.getValueType(VT));
2514 case ISD::SINT_TO_FP:
2515 case ISD::UINT_TO_FP:
2516 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2518 Result = LegalizeOp(Node->getOperand(0));
2519 // No extra round required here.
2520 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2524 Result = PromoteOp(Node->getOperand(0));
2525 if (Node->getOpcode() == ISD::SINT_TO_FP)
2526 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2528 DAG.getValueType(Node->getOperand(0).getValueType()));
2530 Result = DAG.getZeroExtendInReg(Result,
2531 Node->getOperand(0).getValueType());
2532 // No extra round required here.
2533 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2536 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2537 Node->getOperand(0));
2538 // Round if we cannot tolerate excess precision.
2539 if (NoExcessFPPrecision)
2540 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2541 DAG.getValueType(VT));
2546 case ISD::SIGN_EXTEND_INREG:
2547 Result = PromoteOp(Node->getOperand(0));
2548 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2549 Node->getOperand(1));
2551 case ISD::FP_TO_SINT:
2552 case ISD::FP_TO_UINT:
2553 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2555 Tmp1 = LegalizeOp(Node->getOperand(0));
2558 // The input result is prerounded, so we don't have to do anything
2560 Tmp1 = PromoteOp(Node->getOperand(0));
2563 assert(0 && "not implemented");
2565 // If we're promoting a UINT to a larger size, check to see if the new node
2566 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2567 // we can use that instead. This allows us to generate better code for
2568 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2569 // legal, such as PowerPC.
2570 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2571 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2572 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2573 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2574 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2576 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2582 Tmp1 = PromoteOp(Node->getOperand(0));
2583 assert(Tmp1.getValueType() == NVT);
2584 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2585 // NOTE: we do not have to do any extra rounding here for
2586 // NoExcessFPPrecision, because we know the input will have the appropriate
2587 // precision, and these operations don't modify precision at all.
2593 Tmp1 = PromoteOp(Node->getOperand(0));
2594 assert(Tmp1.getValueType() == NVT);
2595 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2596 if(NoExcessFPPrecision)
2597 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2598 DAG.getValueType(VT));
2607 // The input may have strange things in the top bits of the registers, but
2608 // these operations don't care. They may have weird bits going out, but
2609 // that too is okay if they are integer operations.
2610 Tmp1 = PromoteOp(Node->getOperand(0));
2611 Tmp2 = PromoteOp(Node->getOperand(1));
2612 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2613 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2618 // The input may have strange things in the top bits of the registers, but
2619 // these operations don't care.
2620 Tmp1 = PromoteOp(Node->getOperand(0));
2621 Tmp2 = PromoteOp(Node->getOperand(1));
2622 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2623 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2625 // Floating point operations will give excess precision that we may not be
2626 // able to tolerate. If we DO allow excess precision, just leave it,
2627 // otherwise excise it.
2628 // FIXME: Why would we need to round FP ops more than integer ones?
2629 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2630 if (NoExcessFPPrecision)
2631 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2632 DAG.getValueType(VT));
2637 // These operators require that their input be sign extended.
2638 Tmp1 = PromoteOp(Node->getOperand(0));
2639 Tmp2 = PromoteOp(Node->getOperand(1));
2640 if (MVT::isInteger(NVT)) {
2641 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2642 DAG.getValueType(VT));
2643 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2644 DAG.getValueType(VT));
2646 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2648 // Perform FP_ROUND: this is probably overly pessimistic.
2649 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2650 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2651 DAG.getValueType(VT));
2655 // These operators require that their input be fp extended.
2656 Tmp1 = PromoteOp(Node->getOperand(0));
2657 Tmp2 = PromoteOp(Node->getOperand(1));
2658 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2660 // Perform FP_ROUND: this is probably overly pessimistic.
2661 if (NoExcessFPPrecision)
2662 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2663 DAG.getValueType(VT));
2668 // These operators require that their input be zero extended.
2669 Tmp1 = PromoteOp(Node->getOperand(0));
2670 Tmp2 = PromoteOp(Node->getOperand(1));
2671 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2672 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2673 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2674 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2678 Tmp1 = PromoteOp(Node->getOperand(0));
2679 Tmp2 = LegalizeOp(Node->getOperand(1));
2680 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2683 // The input value must be properly sign extended.
2684 Tmp1 = PromoteOp(Node->getOperand(0));
2685 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2686 DAG.getValueType(VT));
2687 Tmp2 = LegalizeOp(Node->getOperand(1));
2688 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2691 // The input value must be properly zero extended.
2692 Tmp1 = PromoteOp(Node->getOperand(0));
2693 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2694 Tmp2 = LegalizeOp(Node->getOperand(1));
2695 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2698 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2699 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2700 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2701 Node->getOperand(2), VT);
2702 // Remember that we legalized the chain.
2703 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2709 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2710 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2711 Node->getOperand(2),
2712 cast<VTSDNode>(Node->getOperand(3))->getVT());
2713 // Remember that we legalized the chain.
2714 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2717 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2718 case Expand: assert(0 && "It's impossible to expand bools");
2720 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2723 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2726 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2727 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2728 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2730 case ISD::SELECT_CC:
2731 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2732 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2733 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2734 Node->getOperand(1), Tmp2, Tmp3,
2735 Node->getOperand(4));
2739 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2740 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2742 std::vector<SDOperand> Ops;
2743 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2744 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2746 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2747 "Can only promote single result calls");
2748 std::vector<MVT::ValueType> RetTyVTs;
2749 RetTyVTs.reserve(2);
2750 RetTyVTs.push_back(NVT);
2751 RetTyVTs.push_back(MVT::Other);
2752 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2753 Node->getOpcode() == ISD::TAILCALL);
2754 Result = SDOperand(NC, 0);
2756 // Insert the new chain mapping.
2757 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2763 Tmp1 = Node->getOperand(0);
2764 //Zero extend the argument
2765 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2766 // Perform the larger operation, then subtract if needed.
2767 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2768 switch(Node->getOpcode())
2774 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2775 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2776 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2777 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2778 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2781 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2782 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2783 DAG.getConstant(getSizeInBits(NVT) -
2784 getSizeInBits(VT), NVT));
2790 assert(Result.Val && "Didn't set a result!");
2791 AddPromotedOperand(Op, Result);
2795 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
2796 /// The resultant code need not be legal.
2797 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
2799 // Create the stack frame object.
2800 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2801 unsigned ByteSize = MVT::getSizeInBits(DestVT)/8;
2802 int FrameIdx = FrameInfo->CreateFixedObject(ByteSize, ByteSize);
2803 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
2805 // Emit a store to the stack slot.
2806 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2807 SrcOp.getOperand(0), FIPtr,
2808 DAG.getSrcValue(NULL));
2809 // Result is a load from the stack slot.
2810 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
2813 /// ExpandAddSub - Find a clever way to expand this add operation into
2815 void SelectionDAGLegalize::
2816 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2817 SDOperand &Lo, SDOperand &Hi) {
2818 // Expand the subcomponents.
2819 SDOperand LHSL, LHSH, RHSL, RHSH;
2820 ExpandOp(LHS, LHSL, LHSH);
2821 ExpandOp(RHS, RHSL, RHSH);
2823 std::vector<SDOperand> Ops;
2824 Ops.push_back(LHSL);
2825 Ops.push_back(LHSH);
2826 Ops.push_back(RHSL);
2827 Ops.push_back(RHSH);
2828 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2829 Lo = DAG.getNode(NodeOp, VTs, Ops);
2830 Hi = Lo.getValue(1);
2833 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2834 SDOperand Op, SDOperand Amt,
2835 SDOperand &Lo, SDOperand &Hi) {
2836 // Expand the subcomponents.
2837 SDOperand LHSL, LHSH;
2838 ExpandOp(Op, LHSL, LHSH);
2840 std::vector<SDOperand> Ops;
2841 Ops.push_back(LHSL);
2842 Ops.push_back(LHSH);
2844 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2845 Lo = DAG.getNode(NodeOp, VTs, Ops);
2846 Hi = Lo.getValue(1);
2850 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2851 /// smaller elements. If we can't find a way that is more efficient than a
2852 /// libcall on this target, return false. Otherwise, return true with the
2853 /// low-parts expanded into Lo and Hi.
2854 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2855 SDOperand &Lo, SDOperand &Hi) {
2856 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2857 "This is not a shift!");
2859 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2860 SDOperand ShAmt = LegalizeOp(Amt);
2861 MVT::ValueType ShTy = ShAmt.getValueType();
2862 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2863 unsigned NVTBits = MVT::getSizeInBits(NVT);
2865 // Handle the case when Amt is an immediate. Other cases are currently broken
2866 // and are disabled.
2867 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2868 unsigned Cst = CN->getValue();
2869 // Expand the incoming operand to be shifted, so that we have its parts
2871 ExpandOp(Op, InL, InH);
2875 Lo = DAG.getConstant(0, NVT);
2876 Hi = DAG.getConstant(0, NVT);
2877 } else if (Cst > NVTBits) {
2878 Lo = DAG.getConstant(0, NVT);
2879 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2880 } else if (Cst == NVTBits) {
2881 Lo = DAG.getConstant(0, NVT);
2884 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2885 Hi = DAG.getNode(ISD::OR, NVT,
2886 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2887 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2892 Lo = DAG.getConstant(0, NVT);
2893 Hi = DAG.getConstant(0, NVT);
2894 } else if (Cst > NVTBits) {
2895 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2896 Hi = DAG.getConstant(0, NVT);
2897 } else if (Cst == NVTBits) {
2899 Hi = DAG.getConstant(0, NVT);
2901 Lo = DAG.getNode(ISD::OR, NVT,
2902 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2903 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2904 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2909 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2910 DAG.getConstant(NVTBits-1, ShTy));
2911 } else if (Cst > NVTBits) {
2912 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2913 DAG.getConstant(Cst-NVTBits, ShTy));
2914 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2915 DAG.getConstant(NVTBits-1, ShTy));
2916 } else if (Cst == NVTBits) {
2918 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2919 DAG.getConstant(NVTBits-1, ShTy));
2921 Lo = DAG.getNode(ISD::OR, NVT,
2922 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2923 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2924 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2929 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2930 // so disable it for now. Currently targets are handling this via SHL_PARTS
2934 // If we have an efficient select operation (or if the selects will all fold
2935 // away), lower to some complex code, otherwise just emit the libcall.
2936 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
2940 ExpandOp(Op, InL, InH);
2941 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
2942 DAG.getConstant(NVTBits, ShTy), ShAmt);
2944 // Compare the unmasked shift amount against 32.
2945 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
2946 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
2948 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
2949 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
2950 DAG.getConstant(NVTBits-1, ShTy));
2951 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
2952 DAG.getConstant(NVTBits-1, ShTy));
2955 if (Opc == ISD::SHL) {
2956 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
2957 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
2958 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
2959 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
2961 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2962 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
2964 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
2965 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
2966 DAG.getConstant(32, ShTy),
2968 DAG.getConstant(0, NVT),
2969 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
2970 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
2972 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
2973 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
2976 if (Opc == ISD::SRA)
2977 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
2978 DAG.getConstant(NVTBits-1, ShTy));
2980 HiPart = DAG.getConstant(0, NVT);
2981 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2982 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
2987 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
2988 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
2990 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
2991 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
2993 // If we found an CALLSEQ_START, we already know this node occurs later
2994 // than the Found node. Just remember this node and return.
2995 if (Node->getOpcode() == ISD::CALLSEQ_START) {
3000 // Otherwise, scan the operands of Node to see if any of them is a call.
3001 assert(Node->getNumOperands() != 0 &&
3002 "All leaves should have depth equal to the entry node!");
3003 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
3004 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
3006 // Tail recurse for the last iteration.
3007 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
3012 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
3013 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
3015 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
3016 std::set<SDNode*> &Visited) {
3017 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
3018 !Visited.insert(Node).second) return;
3020 // If we found an CALLSEQ_END, we already know this node occurs earlier
3021 // than the Found node. Just remember this node and return.
3022 if (Node->getOpcode() == ISD::CALLSEQ_END) {
3027 // Otherwise, scan the operands of Node to see if any of them is a call.
3028 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
3029 if (UI == E) return;
3030 for (--E; UI != E; ++UI)
3031 FindEarliestCallSeqEnd(*UI, Found, Visited);
3033 // Tail recurse for the last iteration.
3034 FindEarliestCallSeqEnd(*UI, Found, Visited);
3037 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
3038 /// find the CALLSEQ_END node that terminates the call sequence.
3039 static SDNode *FindCallSeqEnd(SDNode *Node) {
3040 if (Node->getOpcode() == ISD::CALLSEQ_END)
3042 if (Node->use_empty())
3043 return 0; // No CallSeqEnd
3045 SDOperand TheChain(Node, Node->getNumValues()-1);
3046 if (TheChain.getValueType() != MVT::Other)
3047 TheChain = SDOperand(Node, 0);
3048 if (TheChain.getValueType() != MVT::Other)
3051 for (SDNode::use_iterator UI = Node->use_begin(),
3052 E = Node->use_end(); UI != E; ++UI) {
3054 // Make sure to only follow users of our token chain.
3056 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
3057 if (User->getOperand(i) == TheChain)
3058 if (SDNode *Result = FindCallSeqEnd(User))
3064 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
3065 /// find the CALLSEQ_START node that initiates the call sequence.
3066 static SDNode *FindCallSeqStart(SDNode *Node) {
3067 assert(Node && "Didn't find callseq_start for a call??");
3068 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
3070 assert(Node->getOperand(0).getValueType() == MVT::Other &&
3071 "Node doesn't have a token chain argument!");
3072 return FindCallSeqStart(Node->getOperand(0).Val);
3076 /// FindInputOutputChains - If we are replacing an operation with a call we need
3077 /// to find the call that occurs before and the call that occurs after it to
3078 /// properly serialize the calls in the block. The returned operand is the
3079 /// input chain value for the new call (e.g. the entry node or the previous
3080 /// call), and OutChain is set to be the chain node to update to point to the
3081 /// end of the call chain.
3082 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
3084 SDNode *LatestCallSeqStart = Entry.Val;
3085 SDNode *LatestCallSeqEnd = 0;
3086 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
3087 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
3089 // It is possible that no ISD::CALLSEQ_START was found because there is no
3090 // previous call in the function. LatestCallStackDown may in that case be
3091 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
3092 // unless LatestCallStackDown is an CALLSEQ_START.
3093 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
3094 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
3095 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
3097 LatestCallSeqEnd = Entry.Val;
3099 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
3101 // Finally, find the first call that this must come before, first we find the
3102 // CallSeqEnd that ends the call.
3104 std::set<SDNode*> Visited;
3105 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
3107 // If we found one, translate from the adj up to the callseq_start.
3109 OutChain = FindCallSeqStart(OutChain);
3111 return SDOperand(LatestCallSeqEnd, 0);
3114 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
3115 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
3117 // Nothing to splice it into?
3118 if (OutChain == 0) return;
3120 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
3123 // Form a token factor node merging the old inval and the new inval.
3124 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
3125 OutChain->getOperand(0));
3126 // Change the node to refer to the new token.
3127 OutChain->setAdjCallChain(InToken);
3131 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3132 // does not fit into a register, return the lo part and set the hi part to the
3133 // by-reg argument. If it does fit into a single register, return the result
3134 // and leave the Hi part unset.
3135 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3138 SDOperand InChain = FindInputOutputChains(Node, OutChain,
3139 DAG.getEntryNode());
3140 if (InChain.Val == 0)
3141 InChain = DAG.getEntryNode();
3143 TargetLowering::ArgListTy Args;
3144 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3145 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3146 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3147 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3149 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3151 // Splice the libcall in wherever FindInputOutputChains tells us to.
3152 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3153 std::pair<SDOperand,SDOperand> CallInfo =
3154 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3158 switch (getTypeAction(CallInfo.first.getValueType())) {
3159 default: assert(0 && "Unknown thing");
3161 Result = CallInfo.first;
3164 assert(0 && "Cannot promote this yet!");
3166 ExpandOp(CallInfo.first, Result, Hi);
3167 CallInfo.second = LegalizeOp(CallInfo.second);
3171 SpliceCallInto(CallInfo.second, OutChain);
3172 NeedsAnotherIteration = true;
3177 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3178 /// destination type is legal.
3179 SDOperand SelectionDAGLegalize::
3180 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3181 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3182 assert(getTypeAction(Source.getValueType()) == Expand &&
3183 "This is not an expansion!");
3184 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3187 assert(Source.getValueType() == MVT::i64 &&
3188 "This only works for 64-bit -> FP");
3189 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3190 // incoming integer is set. To handle this, we dynamically test to see if
3191 // it is set, and, if so, add a fudge factor.
3193 ExpandOp(Source, Lo, Hi);
3195 // If this is unsigned, and not supported, first perform the conversion to
3196 // signed, then adjust the result if the sign bit is set.
3197 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3198 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3200 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3201 DAG.getConstant(0, Hi.getValueType()),
3203 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3204 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3205 SignSet, Four, Zero);
3206 uint64_t FF = 0x5f800000ULL;
3207 if (TLI.isLittleEndian()) FF <<= 32;
3208 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3210 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3211 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3212 SDOperand FudgeInReg;
3213 if (DestTy == MVT::f32)
3214 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3215 DAG.getSrcValue(NULL));
3217 assert(DestTy == MVT::f64 && "Unexpected conversion");
3218 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3219 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3221 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3224 // Check to see if the target has a custom way to lower this. If so, use it.
3225 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3226 default: assert(0 && "This action not implemented for this operation!");
3227 case TargetLowering::Legal:
3228 case TargetLowering::Expand:
3229 break; // This case is handled below.
3230 case TargetLowering::Custom: {
3231 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3234 return LegalizeOp(NV);
3235 break; // The target decided this was legal after all
3239 // Expand the source, then glue it back together for the call. We must expand
3240 // the source in case it is shared (this pass of legalize must traverse it).
3241 SDOperand SrcLo, SrcHi;
3242 ExpandOp(Source, SrcLo, SrcHi);
3243 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3245 SDNode *OutChain = 0;
3246 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3247 DAG.getEntryNode());
3248 const char *FnName = 0;
3249 if (DestTy == MVT::f32)
3250 FnName = "__floatdisf";
3252 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3253 FnName = "__floatdidf";
3256 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3258 TargetLowering::ArgListTy Args;
3259 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3261 Args.push_back(std::make_pair(Source, ArgTy));
3263 // We don't care about token chains for libcalls. We just use the entry
3264 // node as our input and ignore the output chain. This allows us to place
3265 // calls wherever we need them to satisfy data dependences.
3266 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3268 std::pair<SDOperand,SDOperand> CallResult =
3269 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3272 SpliceCallInto(CallResult.second, OutChain);
3273 return CallResult.first;
3278 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3279 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3280 /// LegalizeNodes map is filled in for any results that are not expanded, the
3281 /// ExpandedNodes map is filled in for any results that are expanded, and the
3282 /// Lo/Hi values are returned.
3283 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3284 MVT::ValueType VT = Op.getValueType();
3285 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3286 SDNode *Node = Op.Val;
3287 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3288 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3289 "Cannot expand FP values!");
3290 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3291 "Cannot expand to FP value or to larger int value!");
3293 // See if we already expanded it.
3294 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3295 = ExpandedNodes.find(Op);
3296 if (I != ExpandedNodes.end()) {
3297 Lo = I->second.first;
3298 Hi = I->second.second;
3302 // Expanding to multiple registers needs to perform an optimization step, and
3303 // is not careful to avoid operations the target does not support. Make sure
3304 // that all generated operations are legalized in the next iteration.
3305 NeedsAnotherIteration = true;
3307 switch (Node->getOpcode()) {
3308 case ISD::CopyFromReg:
3309 assert(0 && "CopyFromReg must be legal!");
3311 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3312 assert(0 && "Do not know how to expand this operator!");
3315 Lo = DAG.getNode(ISD::UNDEF, NVT);
3316 Hi = DAG.getNode(ISD::UNDEF, NVT);
3318 case ISD::Constant: {
3319 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3320 Lo = DAG.getConstant(Cst, NVT);
3321 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3324 case ISD::ConstantVec: {
3325 unsigned NumElements = Node->getNumOperands();
3326 // If we only have two elements left in the constant vector, just break it
3327 // apart into the two scalar constants it contains. Otherwise, bisect the
3328 // ConstantVec, and return each half as a new ConstantVec.
3329 // FIXME: this is hard coded as big endian, it may have to change to support
3330 // SSE and Alpha MVI
3331 if (NumElements == 2) {
3332 Hi = Node->getOperand(0);
3333 Lo = Node->getOperand(1);
3336 std::vector<SDOperand> LoOps, HiOps;
3337 for (unsigned I = 0, E = NumElements; I < E; ++I) {
3338 HiOps.push_back(Node->getOperand(I));
3339 LoOps.push_back(Node->getOperand(I+NumElements));
3341 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
3342 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
3347 case ISD::BUILD_PAIR:
3348 // Legalize both operands. FIXME: in the future we should handle the case
3349 // where the two elements are not legal.
3350 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3351 Lo = LegalizeOp(Node->getOperand(0));
3352 Hi = LegalizeOp(Node->getOperand(1));
3355 case ISD::SIGN_EXTEND_INREG:
3356 ExpandOp(Node->getOperand(0), Lo, Hi);
3357 // Sign extend the lo-part.
3358 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3359 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3360 TLI.getShiftAmountTy()));
3361 // sext_inreg the low part if needed.
3362 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3366 ExpandOp(Node->getOperand(0), Lo, Hi);
3367 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3368 DAG.getNode(ISD::CTPOP, NVT, Lo),
3369 DAG.getNode(ISD::CTPOP, NVT, Hi));
3370 Hi = DAG.getConstant(0, NVT);
3374 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3375 ExpandOp(Node->getOperand(0), Lo, Hi);
3376 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3377 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3378 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3380 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3381 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3383 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3384 Hi = DAG.getConstant(0, NVT);
3389 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3390 ExpandOp(Node->getOperand(0), Lo, Hi);
3391 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3392 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3393 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3395 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3396 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3398 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3399 Hi = DAG.getConstant(0, NVT);
3404 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3405 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3406 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3408 // Increment the pointer to the other half.
3409 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3410 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3411 getIntPtrConstant(IncrementSize));
3412 //Is this safe? declaring that the two parts of the split load
3413 //are from the same instruction?
3414 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3416 // Build a factor node to remember that this load is independent of the
3418 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3421 // Remember that we legalized the chain.
3422 AddLegalizedOperand(Op.getValue(1), TF);
3423 if (!TLI.isLittleEndian())
3428 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3429 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3430 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3431 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3433 // If we only have two elements, turn into a pair of scalar loads.
3434 // FIXME: handle case where a vector of two elements is fine, such as
3435 // 2 x double on SSE2.
3436 if (NumElements == 2) {
3437 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3438 // Increment the pointer to the other half.
3439 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3440 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3441 getIntPtrConstant(IncrementSize));
3442 //Is this safe? declaring that the two parts of the split load
3443 //are from the same instruction?
3444 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3446 NumElements /= 2; // Split the vector in half
3447 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3448 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3449 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3450 getIntPtrConstant(IncrementSize));
3451 //Is this safe? declaring that the two parts of the split load
3452 //are from the same instruction?
3453 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3456 // Build a factor node to remember that this load is independent of the
3458 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3461 // Remember that we legalized the chain.
3462 AddLegalizedOperand(Op.getValue(1), TF);
3463 if (!TLI.isLittleEndian())
3470 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3471 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3472 SDOperand LL, LH, RL, RH;
3474 ExpandOp(Node->getOperand(0), LL, LH);
3475 ExpandOp(Node->getOperand(1), RL, RH);
3477 // If we only have two elements, turn into a pair of scalar loads.
3478 // FIXME: handle case where a vector of two elements is fine, such as
3479 // 2 x double on SSE2.
3480 if (NumElements == 2) {
3481 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3482 Lo = DAG.getNode(Opc, EVT, LL, RL);
3483 Hi = DAG.getNode(Opc, EVT, LH, RH);
3485 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3487 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3494 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3495 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3497 bool Changed = false;
3498 std::vector<SDOperand> Ops;
3499 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3500 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3501 Changed |= Ops.back() != Node->getOperand(i);
3504 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3505 "Can only expand a call once so far, not i64 -> i16!");
3507 std::vector<MVT::ValueType> RetTyVTs;
3508 RetTyVTs.reserve(3);
3509 RetTyVTs.push_back(NVT);
3510 RetTyVTs.push_back(NVT);
3511 RetTyVTs.push_back(MVT::Other);
3512 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3513 Node->getOpcode() == ISD::TAILCALL);
3514 Lo = SDOperand(NC, 0);
3515 Hi = SDOperand(NC, 1);
3517 // Insert the new chain mapping.
3518 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3523 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3524 SDOperand LL, LH, RL, RH;
3525 ExpandOp(Node->getOperand(0), LL, LH);
3526 ExpandOp(Node->getOperand(1), RL, RH);
3527 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3528 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3532 SDOperand C, LL, LH, RL, RH;
3534 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3535 case Expand: assert(0 && "It's impossible to expand bools");
3537 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3540 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3543 ExpandOp(Node->getOperand(1), LL, LH);
3544 ExpandOp(Node->getOperand(2), RL, RH);
3545 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3546 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3549 case ISD::SELECT_CC: {
3550 SDOperand TL, TH, FL, FH;
3551 ExpandOp(Node->getOperand(2), TL, TH);
3552 ExpandOp(Node->getOperand(3), FL, FH);
3553 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3554 Node->getOperand(1), TL, FL, Node->getOperand(4));
3555 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3556 Node->getOperand(1), TH, FH, Node->getOperand(4));
3557 Lo = LegalizeOp(Lo);
3558 Hi = LegalizeOp(Hi);
3561 case ISD::SEXTLOAD: {
3562 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3563 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3564 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3567 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3569 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3572 // Remember that we legalized the chain.
3573 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3575 // The high part is obtained by SRA'ing all but one of the bits of the lo
3577 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3578 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3579 TLI.getShiftAmountTy()));
3580 Lo = LegalizeOp(Lo);
3581 Hi = LegalizeOp(Hi);
3584 case ISD::ZEXTLOAD: {
3585 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3586 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3587 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3590 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3592 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3595 // Remember that we legalized the chain.
3596 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3598 // The high part is just a zero.
3599 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3600 Lo = LegalizeOp(Lo);
3603 case ISD::EXTLOAD: {
3604 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3605 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3606 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3609 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3611 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3614 // Remember that we legalized the chain.
3615 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3617 // The high part is undefined.
3618 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3619 Lo = LegalizeOp(Lo);
3622 case ISD::ANY_EXTEND: {
3624 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3625 case Expand: assert(0 && "expand-expand not implemented yet!");
3626 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3628 In = PromoteOp(Node->getOperand(0));
3632 // The low part is any extension of the input (which degenerates to a copy).
3633 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3634 // The high part is undefined.
3635 Hi = DAG.getNode(ISD::UNDEF, NVT);
3638 case ISD::SIGN_EXTEND: {
3640 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3641 case Expand: assert(0 && "expand-expand not implemented yet!");
3642 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3644 In = PromoteOp(Node->getOperand(0));
3645 // Emit the appropriate sign_extend_inreg to get the value we want.
3646 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3647 DAG.getValueType(Node->getOperand(0).getValueType()));
3651 // The low part is just a sign extension of the input (which degenerates to
3653 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3655 // The high part is obtained by SRA'ing all but one of the bits of the lo
3657 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3658 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3659 TLI.getShiftAmountTy()));
3662 case ISD::ZERO_EXTEND: {
3664 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3665 case Expand: assert(0 && "expand-expand not implemented yet!");
3666 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3668 In = PromoteOp(Node->getOperand(0));
3669 // Emit the appropriate zero_extend_inreg to get the value we want.
3670 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3674 // The low part is just a zero extension of the input (which degenerates to
3676 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3678 // The high part is just a zero.
3679 Hi = DAG.getConstant(0, NVT);
3683 case ISD::BIT_CONVERT: {
3684 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
3685 Node->getOperand(0));
3686 ExpandOp(Tmp, Lo, Hi);
3690 case ISD::READCYCLECOUNTER: {
3691 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3692 TargetLowering::Custom &&
3693 "Must custom expand ReadCycleCounter");
3694 SDOperand T = TLI.LowerOperation(Op, DAG);
3695 assert(T.Val && "Node must be custom expanded!");
3696 Lo = LegalizeOp(T.getValue(0));
3697 Hi = LegalizeOp(T.getValue(1));
3698 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3699 LegalizeOp(T.getValue(2)));
3703 // These operators cannot be expanded directly, emit them as calls to
3704 // library functions.
3705 case ISD::FP_TO_SINT:
3706 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3708 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3709 case Expand: assert(0 && "cannot expand FP!");
3710 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3711 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3714 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3716 // Now that the custom expander is done, expand the result, which is still
3719 ExpandOp(Op, Lo, Hi);
3724 if (Node->getOperand(0).getValueType() == MVT::f32)
3725 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3727 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3730 case ISD::FP_TO_UINT:
3731 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3732 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3733 LegalizeOp(Node->getOperand(0)));
3734 // Now that the custom expander is done, expand the result, which is still
3736 Op = TLI.LowerOperation(Op, DAG);
3738 ExpandOp(Op, Lo, Hi);
3743 if (Node->getOperand(0).getValueType() == MVT::f32)
3744 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3746 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3750 // If the target wants custom lowering, do so.
3751 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3752 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3753 LegalizeOp(Node->getOperand(1)));
3754 Op = TLI.LowerOperation(Op, DAG);
3756 // Now that the custom expander is done, expand the result, which is
3758 ExpandOp(Op, Lo, Hi);
3763 // If we can emit an efficient shift operation, do so now.
3764 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3767 // If this target supports SHL_PARTS, use it.
3768 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3769 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3774 // Otherwise, emit a libcall.
3775 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3779 // If the target wants custom lowering, do so.
3780 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3781 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3782 LegalizeOp(Node->getOperand(1)));
3783 Op = TLI.LowerOperation(Op, DAG);
3785 // Now that the custom expander is done, expand the result, which is
3787 ExpandOp(Op, Lo, Hi);
3792 // If we can emit an efficient shift operation, do so now.
3793 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3796 // If this target supports SRA_PARTS, use it.
3797 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3798 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3803 // Otherwise, emit a libcall.
3804 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3807 // If the target wants custom lowering, do so.
3808 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3809 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3810 LegalizeOp(Node->getOperand(1)));
3811 Op = TLI.LowerOperation(Op, DAG);
3813 // Now that the custom expander is done, expand the result, which is
3815 ExpandOp(Op, Lo, Hi);
3820 // If we can emit an efficient shift operation, do so now.
3821 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3824 // If this target supports SRL_PARTS, use it.
3825 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3826 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3831 // Otherwise, emit a libcall.
3832 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3836 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3840 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3844 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3845 SDOperand LL, LH, RL, RH;
3846 ExpandOp(Node->getOperand(0), LL, LH);
3847 ExpandOp(Node->getOperand(1), RL, RH);
3848 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3849 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3850 // extended the sign bit of the low half through the upper half, and if so
3851 // emit a MULHS instead of the alternate sequence that is valid for any
3852 // i64 x i64 multiply.
3853 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3854 // is RH an extension of the sign bit of RL?
3855 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3856 RH.getOperand(1).getOpcode() == ISD::Constant &&
3857 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3858 // is LH an extension of the sign bit of LL?
3859 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3860 LH.getOperand(1).getOpcode() == ISD::Constant &&
3861 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3862 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3864 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3865 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3866 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3867 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3868 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3870 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3872 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3876 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3877 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3878 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3879 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3882 // Remember in a map if the values will be reused later.
3883 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3884 std::make_pair(Lo, Hi))).second;
3885 assert(isNew && "Value already expanded?!?");
3887 // Make sure the resultant values have been legalized themselves, unless this
3888 // is a type that requires multi-step expansion.
3889 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
3890 Lo = LegalizeOp(Lo);
3891 Hi = LegalizeOp(Hi);
3896 // SelectionDAG::Legalize - This is the entry point for the file.
3898 void SelectionDAG::Legalize() {
3899 /// run - This is the main entry point to this class.
3901 SelectionDAGLegalize(*this).Run();