1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/SmallPtrSet.h"
36 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
37 cl::desc("Pop up a window to show dags before legalize"));
39 static const bool ViewLegalizeDAGs = 0;
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
59 // Libcall insertion helpers.
61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
62 /// legalized. We use this to ensure that calls are properly serialized
63 /// against each other, including inserted libcalls.
64 SDOperand LastCALLSEQ_END;
66 /// IsLegalizingCall - This member is used *only* for purposes of providing
67 /// helpful assertions that a libcall isn't created while another call is
68 /// being legalized (which could lead to non-serialized call sequences).
69 bool IsLegalizingCall;
72 Legal, // The target natively supports this operation.
73 Promote, // This operation should be executed in a larger type.
74 Expand // Try to expand this to other ops, otherwise use a libcall.
77 /// ValueTypeActions - This is a bitvector that contains two bits for each
78 /// value type, where the two bits correspond to the LegalizeAction enum.
79 /// This can be queried with "getTypeAction(VT)".
80 TargetLowering::ValueTypeActionImpl ValueTypeActions;
82 /// LegalizedNodes - For nodes that are of legal width, and that have more
83 /// than one use, this map indicates what regularized operand to use. This
84 /// allows us to avoid legalizing the same thing more than once.
85 DenseMap<SDOperand, SDOperand> LegalizedNodes;
87 /// PromotedNodes - For nodes that are below legal width, and that have more
88 /// than one use, this map indicates what promoted value to use. This allows
89 /// us to avoid promoting the same thing more than once.
90 DenseMap<SDOperand, SDOperand> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which which operands are the expanded version of the input. This allows
94 /// us to avoid expanding the same node more than once.
95 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
97 /// SplitNodes - For vector nodes that need to be split, this map indicates
98 /// which which operands are the split version of the input. This allows us
99 /// to avoid splitting the same node more than once.
100 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
102 /// ScalarizedNodes - For nodes that need to be converted from vector types to
103 /// scalar types, this contains the mapping of ones we have already
104 /// processed to the result.
105 std::map<SDOperand, SDOperand> ScalarizedNodes;
107 void AddLegalizedOperand(SDOperand From, SDOperand To) {
108 LegalizedNodes.insert(std::make_pair(From, To));
109 // If someone requests legalization of the new node, return itself.
111 LegalizedNodes.insert(std::make_pair(To, To));
113 void AddPromotedOperand(SDOperand From, SDOperand To) {
114 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
115 assert(isNew && "Got into the map somehow?");
116 // If someone requests legalization of the new node, return itself.
117 LegalizedNodes.insert(std::make_pair(To, To));
122 SelectionDAGLegalize(SelectionDAG &DAG);
124 /// getTypeAction - Return how we should legalize values of this type, either
125 /// it is already legal or we need to expand it into multiple registers of
126 /// smaller integer type, or we need to promote it to a larger type.
127 LegalizeAction getTypeAction(MVT::ValueType VT) const {
128 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
131 /// isTypeLegal - Return true if this type is legal on this target.
133 bool isTypeLegal(MVT::ValueType VT) const {
134 return getTypeAction(VT) == Legal;
140 /// HandleOp - Legalize, Promote, or Expand the specified operand as
141 /// appropriate for its type.
142 void HandleOp(SDOperand Op);
144 /// LegalizeOp - We know that the specified value has a legal type.
145 /// Recursively ensure that the operands have legal types, then return the
147 SDOperand LegalizeOp(SDOperand O);
149 /// PromoteOp - Given an operation that produces a value in an invalid type,
150 /// promote it to compute the value into a larger type. The produced value
151 /// will have the correct bits for the low portion of the register, but no
152 /// guarantee is made about the top bits: it may be zero, sign-extended, or
154 SDOperand PromoteOp(SDOperand O);
156 /// ExpandOp - Expand the specified SDOperand into its two component pieces
157 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
158 /// the LegalizeNodes map is filled in for any results that are not expanded,
159 /// the ExpandedNodes map is filled in for any results that are expanded, and
160 /// the Lo/Hi values are returned. This applies to integer types and Vector
162 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// SplitVectorOp - Given an operand of vector type, break it down into
165 /// two smaller values.
166 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
168 /// ScalarizeVectorOp - Given an operand of single-element vector type
169 /// (e.g. v1f32), convert it into the equivalent operation that returns a
170 /// scalar (e.g. f32) value.
171 SDOperand ScalarizeVectorOp(SDOperand O);
173 /// isShuffleLegal - Return true if a vector shuffle is legal with the
174 /// specified mask and type. Targets can specify exactly which masks they
175 /// support and the code generator is tasked with not creating illegal masks.
177 /// Note that this will also return true for shuffles that are promoted to a
180 /// If this is a legal shuffle, this method returns the (possibly promoted)
181 /// build_vector Mask. If it's not a legal shuffle, it returns null.
182 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
184 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
185 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
187 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
189 SDOperand CreateStackTemporary(MVT::ValueType VT);
191 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
193 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
196 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
197 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
198 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
199 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
201 MVT::ValueType DestVT);
202 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
207 SDOperand ExpandBSWAP(SDOperand Op);
208 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
209 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
210 SDOperand &Lo, SDOperand &Hi);
211 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
212 SDOperand &Lo, SDOperand &Hi);
214 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
215 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
217 SDOperand getIntPtrConstant(uint64_t Val) {
218 return DAG.getConstant(Val, TLI.getPointerTy());
223 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
224 /// specified mask and type. Targets can specify exactly which masks they
225 /// support and the code generator is tasked with not creating illegal masks.
227 /// Note that this will also return true for shuffles that are promoted to a
229 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
230 SDOperand Mask) const {
231 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
233 case TargetLowering::Legal:
234 case TargetLowering::Custom:
236 case TargetLowering::Promote: {
237 // If this is promoted to a different type, convert the shuffle mask and
238 // ask if it is legal in the promoted type!
239 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
241 // If we changed # elements, change the shuffle mask.
242 unsigned NumEltsGrowth =
243 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
244 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
245 if (NumEltsGrowth > 1) {
246 // Renumber the elements.
247 SmallVector<SDOperand, 8> Ops;
248 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
249 SDOperand InOp = Mask.getOperand(i);
250 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
251 if (InOp.getOpcode() == ISD::UNDEF)
252 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
254 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
255 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
259 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
265 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
268 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
269 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
270 ValueTypeActions(TLI.getValueTypeActions()) {
271 assert(MVT::LAST_VALUETYPE <= 32 &&
272 "Too many value types for ValueTypeActions to hold!");
275 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
276 /// contains all of a nodes operands before it contains the node.
277 static void ComputeTopDownOrdering(SelectionDAG &DAG,
278 SmallVector<SDNode*, 64> &Order) {
280 DenseMap<SDNode*, unsigned> Visited;
281 std::vector<SDNode*> Worklist;
282 Worklist.reserve(128);
284 // Compute ordering from all of the leaves in the graphs, those (like the
285 // entry node) that have no operands.
286 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
287 E = DAG.allnodes_end(); I != E; ++I) {
288 if (I->getNumOperands() == 0) {
290 Worklist.push_back(I);
294 while (!Worklist.empty()) {
295 SDNode *N = Worklist.back();
298 if (++Visited[N] != N->getNumOperands())
299 continue; // Haven't visited all operands yet
303 // Now that we have N in, add anything that uses it if all of their operands
305 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
307 Worklist.push_back(*UI);
310 assert(Order.size() == Visited.size() &&
312 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
313 "Error: DAG is cyclic!");
317 void SelectionDAGLegalize::LegalizeDAG() {
318 LastCALLSEQ_END = DAG.getEntryNode();
319 IsLegalizingCall = false;
321 // The legalize process is inherently a bottom-up recursive process (users
322 // legalize their uses before themselves). Given infinite stack space, we
323 // could just start legalizing on the root and traverse the whole graph. In
324 // practice however, this causes us to run out of stack space on large basic
325 // blocks. To avoid this problem, compute an ordering of the nodes where each
326 // node is only legalized after all of its operands are legalized.
327 SmallVector<SDNode*, 64> Order;
328 ComputeTopDownOrdering(DAG, Order);
330 for (unsigned i = 0, e = Order.size(); i != e; ++i)
331 HandleOp(SDOperand(Order[i], 0));
333 // Finally, it's possible the root changed. Get the new root.
334 SDOperand OldRoot = DAG.getRoot();
335 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
336 DAG.setRoot(LegalizedNodes[OldRoot]);
338 ExpandedNodes.clear();
339 LegalizedNodes.clear();
340 PromotedNodes.clear();
342 ScalarizedNodes.clear();
344 // Remove dead nodes now.
345 DAG.RemoveDeadNodes();
349 /// FindCallEndFromCallStart - Given a chained node that is part of a call
350 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
351 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
352 if (Node->getOpcode() == ISD::CALLSEQ_END)
354 if (Node->use_empty())
355 return 0; // No CallSeqEnd
357 // The chain is usually at the end.
358 SDOperand TheChain(Node, Node->getNumValues()-1);
359 if (TheChain.getValueType() != MVT::Other) {
360 // Sometimes it's at the beginning.
361 TheChain = SDOperand(Node, 0);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Otherwise, hunt for it.
364 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
365 if (Node->getValueType(i) == MVT::Other) {
366 TheChain = SDOperand(Node, i);
370 // Otherwise, we walked into a node without a chain.
371 if (TheChain.getValueType() != MVT::Other)
376 for (SDNode::use_iterator UI = Node->use_begin(),
377 E = Node->use_end(); UI != E; ++UI) {
379 // Make sure to only follow users of our token chain.
381 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
382 if (User->getOperand(i) == TheChain)
383 if (SDNode *Result = FindCallEndFromCallStart(User))
389 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
390 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
391 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
392 assert(Node && "Didn't find callseq_start for a call??");
393 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
395 assert(Node->getOperand(0).getValueType() == MVT::Other &&
396 "Node doesn't have a token chain argument!");
397 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
400 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
401 /// see if any uses can reach Dest. If no dest operands can get to dest,
402 /// legalize them, legalize ourself, and return false, otherwise, return true.
404 /// Keep track of the nodes we fine that actually do lead to Dest in
405 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
407 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
408 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
409 if (N == Dest) return true; // N certainly leads to Dest :)
411 // If we've already processed this node and it does lead to Dest, there is no
412 // need to reprocess it.
413 if (NodesLeadingTo.count(N)) return true;
415 // If the first result of this node has been already legalized, then it cannot
417 switch (getTypeAction(N->getValueType(0))) {
419 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
422 if (PromotedNodes.count(SDOperand(N, 0))) return false;
425 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
429 // Okay, this node has not already been legalized. Check and legalize all
430 // operands. If none lead to Dest, then we can legalize this node.
431 bool OperandsLeadToDest = false;
432 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
433 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
434 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
436 if (OperandsLeadToDest) {
437 NodesLeadingTo.insert(N);
441 // Okay, this node looks safe, legalize it and return false.
442 HandleOp(SDOperand(N, 0));
446 /// HandleOp - Legalize, Promote, or Expand the specified operand as
447 /// appropriate for its type.
448 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
449 MVT::ValueType VT = Op.getValueType();
450 switch (getTypeAction(VT)) {
451 default: assert(0 && "Bad type action!");
452 case Legal: (void)LegalizeOp(Op); break;
453 case Promote: (void)PromoteOp(Op); break;
455 if (!MVT::isVector(VT)) {
456 // If this is an illegal scalar, expand it into its two component
460 } else if (MVT::getVectorNumElements(VT) == 1) {
461 // If this is an illegal single element vector, convert it to a
463 (void)ScalarizeVectorOp(Op);
465 // Otherwise, this is an illegal multiple element vector.
466 // Split it in half and legalize both parts.
468 SplitVectorOp(Op, X, Y);
474 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
475 /// a load from the constant pool.
476 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
477 SelectionDAG &DAG, TargetLowering &TLI) {
480 // If a FP immediate is precise when represented as a float and if the
481 // target can do an extending load from float to double, we put it into
482 // the constant pool as a float, even if it's is statically typed as a
484 MVT::ValueType VT = CFP->getValueType(0);
485 bool isDouble = VT == MVT::f64;
486 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
487 Type::FloatTy, CFP->getValue());
489 double Val = LLVMC->getValue();
491 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
492 : DAG.getConstant(FloatToBits(Val), MVT::i32);
495 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
496 // Only do this if the target has a native EXTLOAD instruction from f32.
497 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
498 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
503 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
505 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
506 CPIdx, NULL, 0, MVT::f32);
508 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
513 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
516 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
517 SelectionDAG &DAG, TargetLowering &TLI) {
518 MVT::ValueType VT = Node->getValueType(0);
519 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
520 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
521 "fcopysign expansion only supported for f32 and f64");
522 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
524 // First get the sign bit of second operand.
525 SDOperand Mask1 = (SrcVT == MVT::f64)
526 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
527 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
528 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
529 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
530 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
531 // Shift right or sign-extend it if the two operands have different types.
532 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
534 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
535 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
536 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
537 } else if (SizeDiff < 0)
538 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
540 // Clear the sign bit of first operand.
541 SDOperand Mask2 = (VT == MVT::f64)
542 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
543 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
544 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
545 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
546 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
548 // Or the value with the sign bit.
549 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
553 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
555 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
556 TargetLowering &TLI) {
557 assert(MVT::isInteger(ST->getStoredVT()) &&
558 "Non integer unaligned stores not implemented.");
559 int SVOffset = ST->getSrcValueOffset();
560 SDOperand Chain = ST->getChain();
561 SDOperand Ptr = ST->getBasePtr();
562 SDOperand Val = ST->getValue();
563 MVT::ValueType VT = Val.getValueType();
564 // Get the half-size VT
565 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
566 int NumBits = MVT::getSizeInBits(NewStoredVT);
567 int Alignment = ST->getAlignment();
568 int IncrementSize = NumBits / 8;
570 // Divide the stored value in two parts.
571 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
573 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
575 // Store the two parts
576 SDOperand Store1, Store2;
577 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
578 ST->getSrcValue(), SVOffset, NewStoredVT,
579 ST->isVolatile(), Alignment);
580 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
581 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
582 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
583 ST->getSrcValue(), SVOffset + IncrementSize,
584 NewStoredVT, ST->isVolatile(), Alignment);
586 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
589 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
591 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
592 TargetLowering &TLI) {
593 assert(MVT::isInteger(LD->getLoadedVT()) &&
594 "Non integer unaligned loads not implemented.");
595 int SVOffset = LD->getSrcValueOffset();
596 SDOperand Chain = LD->getChain();
597 SDOperand Ptr = LD->getBasePtr();
598 MVT::ValueType VT = LD->getValueType(0);
599 MVT::ValueType NewLoadedVT = LD->getLoadedVT() - 1;
600 int NumBits = MVT::getSizeInBits(NewLoadedVT);
601 int Alignment = LD->getAlignment();
602 int IncrementSize = NumBits / 8;
603 ISD::LoadExtType HiExtType = LD->getExtensionType();
605 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
606 if (HiExtType == ISD::NON_EXTLOAD)
607 HiExtType = ISD::ZEXTLOAD;
609 // Load the value in two parts
611 if (TLI.isLittleEndian()) {
612 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
613 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
614 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
615 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
616 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
617 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
620 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
621 NewLoadedVT,LD->isVolatile(), Alignment);
622 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
623 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
624 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
625 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
629 // aggregate the two parts
630 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
631 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
632 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
634 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
637 SDOperand Ops[] = { Result, TF };
638 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
641 /// LegalizeOp - We know that the specified value has a legal type, and
642 /// that its operands are legal. Now ensure that the operation itself
643 /// is legal, recursively ensuring that the operands' operations remain
645 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
646 assert(isTypeLegal(Op.getValueType()) &&
647 "Caller should expand or promote operands that are not legal!");
648 SDNode *Node = Op.Val;
650 // If this operation defines any values that cannot be represented in a
651 // register on this target, make sure to expand or promote them.
652 if (Node->getNumValues() > 1) {
653 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
654 if (getTypeAction(Node->getValueType(i)) != Legal) {
655 HandleOp(Op.getValue(i));
656 assert(LegalizedNodes.count(Op) &&
657 "Handling didn't add legal operands!");
658 return LegalizedNodes[Op];
662 // Note that LegalizeOp may be reentered even from single-use nodes, which
663 // means that we always must cache transformed nodes.
664 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
665 if (I != LegalizedNodes.end()) return I->second;
667 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
668 SDOperand Result = Op;
669 bool isCustom = false;
671 switch (Node->getOpcode()) {
672 case ISD::FrameIndex:
673 case ISD::EntryToken:
675 case ISD::BasicBlock:
676 case ISD::TargetFrameIndex:
677 case ISD::TargetJumpTable:
678 case ISD::TargetConstant:
679 case ISD::TargetConstantFP:
680 case ISD::TargetConstantPool:
681 case ISD::TargetGlobalAddress:
682 case ISD::TargetGlobalTLSAddress:
683 case ISD::TargetExternalSymbol:
688 // Primitives must all be legal.
689 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
690 "This must be legal!");
693 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
694 // If this is a target node, legalize it by legalizing the operands then
695 // passing it through.
696 SmallVector<SDOperand, 8> Ops;
697 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
698 Ops.push_back(LegalizeOp(Node->getOperand(i)));
700 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
702 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
703 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
704 return Result.getValue(Op.ResNo);
706 // Otherwise this is an unhandled builtin node. splat.
708 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
710 assert(0 && "Do not know how to legalize this operator!");
712 case ISD::GLOBAL_OFFSET_TABLE:
713 case ISD::GlobalAddress:
714 case ISD::GlobalTLSAddress:
715 case ISD::ExternalSymbol:
716 case ISD::ConstantPool:
717 case ISD::JumpTable: // Nothing to do.
718 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
719 default: assert(0 && "This action is not supported yet!");
720 case TargetLowering::Custom:
721 Tmp1 = TLI.LowerOperation(Op, DAG);
722 if (Tmp1.Val) Result = Tmp1;
723 // FALLTHROUGH if the target doesn't want to lower this op after all.
724 case TargetLowering::Legal:
729 case ISD::RETURNADDR:
730 case ISD::FRAME_TO_ARGS_OFFSET:
731 // The only option for these nodes is to custom lower them. If the target
732 // does not custom lower them, then return zero.
733 Tmp1 = TLI.LowerOperation(Op, DAG);
737 Result = DAG.getConstant(0, TLI.getPointerTy());
739 case ISD::EXCEPTIONADDR: {
740 Tmp1 = LegalizeOp(Node->getOperand(0));
741 MVT::ValueType VT = Node->getValueType(0);
742 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
743 default: assert(0 && "This action is not supported yet!");
744 case TargetLowering::Expand: {
745 unsigned Reg = TLI.getExceptionAddressRegister();
746 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
749 case TargetLowering::Custom:
750 Result = TLI.LowerOperation(Op, DAG);
751 if (Result.Val) break;
753 case TargetLowering::Legal: {
754 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
755 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
756 Ops, 2).getValue(Op.ResNo);
762 case ISD::EHSELECTION: {
763 Tmp1 = LegalizeOp(Node->getOperand(0));
764 Tmp2 = LegalizeOp(Node->getOperand(1));
765 MVT::ValueType VT = Node->getValueType(0);
766 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
767 default: assert(0 && "This action is not supported yet!");
768 case TargetLowering::Expand: {
769 unsigned Reg = TLI.getExceptionSelectorRegister();
770 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
773 case TargetLowering::Custom:
774 Result = TLI.LowerOperation(Op, DAG);
775 if (Result.Val) break;
777 case TargetLowering::Legal: {
778 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
779 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
780 Ops, 2).getValue(Op.ResNo);
786 case ISD::EH_RETURN: {
787 MVT::ValueType VT = Node->getValueType(0);
788 // The only "good" option for this node is to custom lower it.
789 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
790 default: assert(0 && "This action is not supported at all!");
791 case TargetLowering::Custom:
792 Result = TLI.LowerOperation(Op, DAG);
793 if (Result.Val) break;
795 case TargetLowering::Legal:
796 // Target does not know, how to lower this, lower to noop
797 Result = LegalizeOp(Node->getOperand(0));
802 case ISD::AssertSext:
803 case ISD::AssertZext:
804 Tmp1 = LegalizeOp(Node->getOperand(0));
805 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
807 case ISD::MERGE_VALUES:
808 // Legalize eliminates MERGE_VALUES nodes.
809 Result = Node->getOperand(Op.ResNo);
811 case ISD::CopyFromReg:
812 Tmp1 = LegalizeOp(Node->getOperand(0));
813 Result = Op.getValue(0);
814 if (Node->getNumValues() == 2) {
815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
817 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
818 if (Node->getNumOperands() == 3) {
819 Tmp2 = LegalizeOp(Node->getOperand(2));
820 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
822 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
824 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
826 // Since CopyFromReg produces two values, make sure to remember that we
827 // legalized both of them.
828 AddLegalizedOperand(Op.getValue(0), Result);
829 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
830 return Result.getValue(Op.ResNo);
832 MVT::ValueType VT = Op.getValueType();
833 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
834 default: assert(0 && "This action is not supported yet!");
835 case TargetLowering::Expand:
836 if (MVT::isInteger(VT))
837 Result = DAG.getConstant(0, VT);
838 else if (MVT::isFloatingPoint(VT))
839 Result = DAG.getConstantFP(0, VT);
841 assert(0 && "Unknown value type!");
843 case TargetLowering::Legal:
849 case ISD::INTRINSIC_W_CHAIN:
850 case ISD::INTRINSIC_WO_CHAIN:
851 case ISD::INTRINSIC_VOID: {
852 SmallVector<SDOperand, 8> Ops;
853 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
854 Ops.push_back(LegalizeOp(Node->getOperand(i)));
855 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
857 // Allow the target to custom lower its intrinsics if it wants to.
858 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
859 TargetLowering::Custom) {
860 Tmp3 = TLI.LowerOperation(Result, DAG);
861 if (Tmp3.Val) Result = Tmp3;
864 if (Result.Val->getNumValues() == 1) break;
866 // Must have return value and chain result.
867 assert(Result.Val->getNumValues() == 2 &&
868 "Cannot return more than two values!");
870 // Since loads produce two values, make sure to remember that we
871 // legalized both of them.
872 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
873 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
874 return Result.getValue(Op.ResNo);
878 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
879 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
881 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
882 case TargetLowering::Promote:
883 default: assert(0 && "This action is not supported yet!");
884 case TargetLowering::Expand: {
885 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
886 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
887 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
889 if (MMI && (useDEBUG_LOC || useLABEL)) {
890 const std::string &FName =
891 cast<StringSDNode>(Node->getOperand(3))->getValue();
892 const std::string &DirName =
893 cast<StringSDNode>(Node->getOperand(4))->getValue();
894 unsigned SrcFile = MMI->RecordSource(DirName, FName);
896 SmallVector<SDOperand, 8> Ops;
897 Ops.push_back(Tmp1); // chain
898 SDOperand LineOp = Node->getOperand(1);
899 SDOperand ColOp = Node->getOperand(2);
902 Ops.push_back(LineOp); // line #
903 Ops.push_back(ColOp); // col #
904 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
905 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
907 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
908 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
909 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
910 Ops.push_back(DAG.getConstant(ID, MVT::i32));
911 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
914 Result = Tmp1; // chain
918 case TargetLowering::Legal:
919 if (Tmp1 != Node->getOperand(0) ||
920 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
921 SmallVector<SDOperand, 8> Ops;
923 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
924 Ops.push_back(Node->getOperand(1)); // line # must be legal.
925 Ops.push_back(Node->getOperand(2)); // col # must be legal.
927 // Otherwise promote them.
928 Ops.push_back(PromoteOp(Node->getOperand(1)));
929 Ops.push_back(PromoteOp(Node->getOperand(2)));
931 Ops.push_back(Node->getOperand(3)); // filename must be legal.
932 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
933 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
940 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
941 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
942 default: assert(0 && "This action is not supported yet!");
943 case TargetLowering::Legal:
944 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
945 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
946 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
947 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
948 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
954 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
955 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
956 default: assert(0 && "This action is not supported yet!");
957 case TargetLowering::Legal:
958 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
959 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
960 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
962 case TargetLowering::Expand:
963 Result = LegalizeOp(Node->getOperand(0));
969 // We know we don't need to expand constants here, constants only have one
970 // value and we check that it is fine above.
972 // FIXME: Maybe we should handle things like targets that don't support full
973 // 32-bit immediates?
975 case ISD::ConstantFP: {
976 // Spill FP immediates to the constant pool if the target cannot directly
977 // codegen them. Targets often have some immediate values that can be
978 // efficiently generated into an FP register without a load. We explicitly
979 // leave these constants as ConstantFP nodes for the target to deal with.
980 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
982 // Check to see if this FP immediate is already legal.
983 bool isLegal = false;
984 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
985 E = TLI.legal_fpimm_end(); I != E; ++I)
986 if (CFP->isExactlyValue(*I)) {
991 // If this is a legal constant, turn it into a TargetConstantFP node.
993 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
997 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
998 default: assert(0 && "This action is not supported yet!");
999 case TargetLowering::Custom:
1000 Tmp3 = TLI.LowerOperation(Result, DAG);
1006 case TargetLowering::Expand:
1007 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1011 case ISD::TokenFactor:
1012 if (Node->getNumOperands() == 2) {
1013 Tmp1 = LegalizeOp(Node->getOperand(0));
1014 Tmp2 = LegalizeOp(Node->getOperand(1));
1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1016 } else if (Node->getNumOperands() == 3) {
1017 Tmp1 = LegalizeOp(Node->getOperand(0));
1018 Tmp2 = LegalizeOp(Node->getOperand(1));
1019 Tmp3 = LegalizeOp(Node->getOperand(2));
1020 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1022 SmallVector<SDOperand, 8> Ops;
1023 // Legalize the operands.
1024 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1025 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1026 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1030 case ISD::FORMAL_ARGUMENTS:
1032 // The only option for this is to custom lower it.
1033 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1034 assert(Tmp3.Val && "Target didn't custom lower this node!");
1035 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1036 "Lowering call/formal_arguments produced unexpected # results!");
1038 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1039 // remember that we legalized all of them, so it doesn't get relegalized.
1040 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1041 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1044 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1047 case ISD::EXTRACT_SUBREG: {
1048 Tmp1 = LegalizeOp(Node->getOperand(0));
1049 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1050 assert(idx && "Operand must be a constant");
1051 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1052 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1055 case ISD::INSERT_SUBREG: {
1056 Tmp1 = LegalizeOp(Node->getOperand(0));
1057 Tmp2 = LegalizeOp(Node->getOperand(1));
1058 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1059 assert(idx && "Operand must be a constant");
1060 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1061 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1064 case ISD::BUILD_VECTOR:
1065 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1066 default: assert(0 && "This action is not supported yet!");
1067 case TargetLowering::Custom:
1068 Tmp3 = TLI.LowerOperation(Result, DAG);
1074 case TargetLowering::Expand:
1075 Result = ExpandBUILD_VECTOR(Result.Val);
1079 case ISD::INSERT_VECTOR_ELT:
1080 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1081 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1082 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1083 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1085 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1086 Node->getValueType(0))) {
1087 default: assert(0 && "This action is not supported yet!");
1088 case TargetLowering::Legal:
1090 case TargetLowering::Custom:
1091 Tmp3 = TLI.LowerOperation(Result, DAG);
1097 case TargetLowering::Expand: {
1098 // If the insert index is a constant, codegen this as a scalar_to_vector,
1099 // then a shuffle that inserts it into the right position in the vector.
1100 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1101 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1102 Tmp1.getValueType(), Tmp2);
1104 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1105 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1106 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1108 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1109 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1111 SmallVector<SDOperand, 8> ShufOps;
1112 for (unsigned i = 0; i != NumElts; ++i) {
1113 if (i != InsertPos->getValue())
1114 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1116 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1118 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1119 &ShufOps[0], ShufOps.size());
1121 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1122 Tmp1, ScVec, ShufMask);
1123 Result = LegalizeOp(Result);
1127 // If the target doesn't support this, we have to spill the input vector
1128 // to a temporary stack slot, update the element, then reload it. This is
1129 // badness. We could also load the value into a vector register (either
1130 // with a "move to register" or "extload into register" instruction, then
1131 // permute it into place, if the idx is a constant and if the idx is
1132 // supported by the target.
1133 MVT::ValueType VT = Tmp1.getValueType();
1134 MVT::ValueType EltVT = Tmp2.getValueType();
1135 MVT::ValueType IdxVT = Tmp3.getValueType();
1136 MVT::ValueType PtrVT = TLI.getPointerTy();
1137 SDOperand StackPtr = CreateStackTemporary(VT);
1138 // Store the vector.
1139 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1141 // Truncate or zero extend offset to target pointer type.
1142 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1143 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1144 // Add the offset to the index.
1145 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1146 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1147 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1148 // Store the scalar value.
1149 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1150 // Load the updated vector.
1151 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1156 case ISD::SCALAR_TO_VECTOR:
1157 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1158 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1162 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1163 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1164 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1165 Node->getValueType(0))) {
1166 default: assert(0 && "This action is not supported yet!");
1167 case TargetLowering::Legal:
1169 case TargetLowering::Custom:
1170 Tmp3 = TLI.LowerOperation(Result, DAG);
1176 case TargetLowering::Expand:
1177 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1181 case ISD::VECTOR_SHUFFLE:
1182 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1183 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1184 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1186 // Allow targets to custom lower the SHUFFLEs they support.
1187 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1188 default: assert(0 && "Unknown operation action!");
1189 case TargetLowering::Legal:
1190 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1191 "vector shuffle should not be created if not legal!");
1193 case TargetLowering::Custom:
1194 Tmp3 = TLI.LowerOperation(Result, DAG);
1200 case TargetLowering::Expand: {
1201 MVT::ValueType VT = Node->getValueType(0);
1202 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1203 MVT::ValueType PtrVT = TLI.getPointerTy();
1204 SDOperand Mask = Node->getOperand(2);
1205 unsigned NumElems = Mask.getNumOperands();
1206 SmallVector<SDOperand,8> Ops;
1207 for (unsigned i = 0; i != NumElems; ++i) {
1208 SDOperand Arg = Mask.getOperand(i);
1209 if (Arg.getOpcode() == ISD::UNDEF) {
1210 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1212 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1213 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1215 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1216 DAG.getConstant(Idx, PtrVT)));
1218 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1219 DAG.getConstant(Idx - NumElems, PtrVT)));
1222 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1225 case TargetLowering::Promote: {
1226 // Change base type to a different vector type.
1227 MVT::ValueType OVT = Node->getValueType(0);
1228 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1230 // Cast the two input vectors.
1231 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1232 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1234 // Convert the shuffle mask to the right # elements.
1235 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1236 assert(Tmp3.Val && "Shuffle not legal?");
1237 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1238 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1244 case ISD::EXTRACT_VECTOR_ELT:
1245 Tmp1 = Node->getOperand(0);
1246 Tmp2 = LegalizeOp(Node->getOperand(1));
1247 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1248 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1251 case ISD::EXTRACT_SUBVECTOR:
1252 Tmp1 = Node->getOperand(0);
1253 Tmp2 = LegalizeOp(Node->getOperand(1));
1254 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1255 Result = ExpandEXTRACT_SUBVECTOR(Result);
1258 case ISD::CALLSEQ_START: {
1259 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1261 // Recursively Legalize all of the inputs of the call end that do not lead
1262 // to this call start. This ensures that any libcalls that need be inserted
1263 // are inserted *before* the CALLSEQ_START.
1264 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1265 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1266 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1270 // Now that we legalized all of the inputs (which may have inserted
1271 // libcalls) create the new CALLSEQ_START node.
1272 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1274 // Merge in the last call, to ensure that this call start after the last
1276 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1277 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1278 Tmp1 = LegalizeOp(Tmp1);
1281 // Do not try to legalize the target-specific arguments (#1+).
1282 if (Tmp1 != Node->getOperand(0)) {
1283 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1285 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1288 // Remember that the CALLSEQ_START is legalized.
1289 AddLegalizedOperand(Op.getValue(0), Result);
1290 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1291 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1293 // Now that the callseq_start and all of the non-call nodes above this call
1294 // sequence have been legalized, legalize the call itself. During this
1295 // process, no libcalls can/will be inserted, guaranteeing that no calls
1297 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1298 SDOperand InCallSEQ = LastCALLSEQ_END;
1299 // Note that we are selecting this call!
1300 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1301 IsLegalizingCall = true;
1303 // Legalize the call, starting from the CALLSEQ_END.
1304 LegalizeOp(LastCALLSEQ_END);
1305 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1308 case ISD::CALLSEQ_END:
1309 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1310 // will cause this node to be legalized as well as handling libcalls right.
1311 if (LastCALLSEQ_END.Val != Node) {
1312 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1313 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1314 assert(I != LegalizedNodes.end() &&
1315 "Legalizing the call start should have legalized this node!");
1319 // Otherwise, the call start has been legalized and everything is going
1320 // according to plan. Just legalize ourselves normally here.
1321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1322 // Do not try to legalize the target-specific arguments (#1+), except for
1323 // an optional flag input.
1324 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1325 if (Tmp1 != Node->getOperand(0)) {
1326 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1328 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1331 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1332 if (Tmp1 != Node->getOperand(0) ||
1333 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1334 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1337 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1340 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1341 // This finishes up call legalization.
1342 IsLegalizingCall = false;
1344 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1345 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1346 if (Node->getNumValues() == 2)
1347 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1348 return Result.getValue(Op.ResNo);
1349 case ISD::DYNAMIC_STACKALLOC: {
1350 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1351 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1352 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1353 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1355 Tmp1 = Result.getValue(0);
1356 Tmp2 = Result.getValue(1);
1357 switch (TLI.getOperationAction(Node->getOpcode(),
1358 Node->getValueType(0))) {
1359 default: assert(0 && "This action is not supported yet!");
1360 case TargetLowering::Expand: {
1361 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1362 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1363 " not tell us which reg is the stack pointer!");
1364 SDOperand Chain = Tmp1.getOperand(0);
1365 SDOperand Size = Tmp2.getOperand(1);
1366 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1367 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1368 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1369 Tmp1 = LegalizeOp(Tmp1);
1370 Tmp2 = LegalizeOp(Tmp2);
1373 case TargetLowering::Custom:
1374 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1376 Tmp1 = LegalizeOp(Tmp3);
1377 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1380 case TargetLowering::Legal:
1383 // Since this op produce two values, make sure to remember that we
1384 // legalized both of them.
1385 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1386 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1387 return Op.ResNo ? Tmp2 : Tmp1;
1389 case ISD::INLINEASM: {
1390 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1391 bool Changed = false;
1392 // Legalize all of the operands of the inline asm, in case they are nodes
1393 // that need to be expanded or something. Note we skip the asm string and
1394 // all of the TargetConstant flags.
1395 SDOperand Op = LegalizeOp(Ops[0]);
1396 Changed = Op != Ops[0];
1399 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1400 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1401 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1402 for (++i; NumVals; ++i, --NumVals) {
1403 SDOperand Op = LegalizeOp(Ops[i]);
1412 Op = LegalizeOp(Ops.back());
1413 Changed |= Op != Ops.back();
1418 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1420 // INLINE asm returns a chain and flag, make sure to add both to the map.
1421 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1422 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1423 return Result.getValue(Op.ResNo);
1426 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1427 // Ensure that libcalls are emitted before a branch.
1428 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1429 Tmp1 = LegalizeOp(Tmp1);
1430 LastCALLSEQ_END = DAG.getEntryNode();
1432 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1435 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1436 // Ensure that libcalls are emitted before a branch.
1437 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1438 Tmp1 = LegalizeOp(Tmp1);
1439 LastCALLSEQ_END = DAG.getEntryNode();
1441 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1442 default: assert(0 && "Indirect target must be legal type (pointer)!");
1444 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1447 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1450 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1451 // Ensure that libcalls are emitted before a branch.
1452 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1453 Tmp1 = LegalizeOp(Tmp1);
1454 LastCALLSEQ_END = DAG.getEntryNode();
1456 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1457 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1459 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1460 default: assert(0 && "This action is not supported yet!");
1461 case TargetLowering::Legal: break;
1462 case TargetLowering::Custom:
1463 Tmp1 = TLI.LowerOperation(Result, DAG);
1464 if (Tmp1.Val) Result = Tmp1;
1466 case TargetLowering::Expand: {
1467 SDOperand Chain = Result.getOperand(0);
1468 SDOperand Table = Result.getOperand(1);
1469 SDOperand Index = Result.getOperand(2);
1471 MVT::ValueType PTy = TLI.getPointerTy();
1472 MachineFunction &MF = DAG.getMachineFunction();
1473 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1474 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1475 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1478 switch (EntrySize) {
1479 default: assert(0 && "Size of jump table not supported yet."); break;
1480 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1481 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1484 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1485 // For PIC, the sequence is:
1486 // BRIND(load(Jumptable + index) + RelocBase)
1487 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1489 if (TLI.usesGlobalOffsetTable())
1490 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1493 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1494 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1495 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1497 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1503 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1504 // Ensure that libcalls are emitted before a return.
1505 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1506 Tmp1 = LegalizeOp(Tmp1);
1507 LastCALLSEQ_END = DAG.getEntryNode();
1509 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1510 case Expand: assert(0 && "It's impossible to expand bools");
1512 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1515 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1517 // The top bits of the promoted condition are not necessarily zero, ensure
1518 // that the value is properly zero extended.
1519 if (!DAG.MaskedValueIsZero(Tmp2,
1520 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1521 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1525 // Basic block destination (Op#2) is always legal.
1526 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1528 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1529 default: assert(0 && "This action is not supported yet!");
1530 case TargetLowering::Legal: break;
1531 case TargetLowering::Custom:
1532 Tmp1 = TLI.LowerOperation(Result, DAG);
1533 if (Tmp1.Val) Result = Tmp1;
1535 case TargetLowering::Expand:
1536 // Expand brcond's setcc into its constituent parts and create a BR_CC
1538 if (Tmp2.getOpcode() == ISD::SETCC) {
1539 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1540 Tmp2.getOperand(0), Tmp2.getOperand(1),
1541 Node->getOperand(2));
1543 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1544 DAG.getCondCode(ISD::SETNE), Tmp2,
1545 DAG.getConstant(0, Tmp2.getValueType()),
1546 Node->getOperand(2));
1552 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1553 // Ensure that libcalls are emitted before a branch.
1554 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1555 Tmp1 = LegalizeOp(Tmp1);
1556 Tmp2 = Node->getOperand(2); // LHS
1557 Tmp3 = Node->getOperand(3); // RHS
1558 Tmp4 = Node->getOperand(1); // CC
1560 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1561 LastCALLSEQ_END = DAG.getEntryNode();
1563 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1564 // the LHS is a legal SETCC itself. In this case, we need to compare
1565 // the result against zero to select between true and false values.
1566 if (Tmp3.Val == 0) {
1567 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1568 Tmp4 = DAG.getCondCode(ISD::SETNE);
1571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1572 Node->getOperand(4));
1574 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1575 default: assert(0 && "Unexpected action for BR_CC!");
1576 case TargetLowering::Legal: break;
1577 case TargetLowering::Custom:
1578 Tmp4 = TLI.LowerOperation(Result, DAG);
1579 if (Tmp4.Val) Result = Tmp4;
1584 LoadSDNode *LD = cast<LoadSDNode>(Node);
1585 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1586 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1588 ISD::LoadExtType ExtType = LD->getExtensionType();
1589 if (ExtType == ISD::NON_EXTLOAD) {
1590 MVT::ValueType VT = Node->getValueType(0);
1591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1592 Tmp3 = Result.getValue(0);
1593 Tmp4 = Result.getValue(1);
1595 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1596 default: assert(0 && "This action is not supported yet!");
1597 case TargetLowering::Legal:
1598 // If this is an unaligned load and the target doesn't support it,
1600 if (!TLI.allowsUnalignedMemoryAccesses()) {
1601 unsigned ABIAlignment = TLI.getTargetData()->
1602 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1603 if (LD->getAlignment() < ABIAlignment){
1604 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1606 Tmp3 = Result.getOperand(0);
1607 Tmp4 = Result.getOperand(1);
1613 case TargetLowering::Custom:
1614 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1616 Tmp3 = LegalizeOp(Tmp1);
1617 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1620 case TargetLowering::Promote: {
1621 // Only promote a load of vector type to another.
1622 assert(MVT::isVector(VT) && "Cannot promote this load!");
1623 // Change base type to a different vector type.
1624 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1626 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1627 LD->getSrcValueOffset(),
1628 LD->isVolatile(), LD->getAlignment());
1629 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1630 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1634 // Since loads produce two values, make sure to remember that we
1635 // legalized both of them.
1636 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1637 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1638 return Op.ResNo ? Tmp4 : Tmp3;
1640 MVT::ValueType SrcVT = LD->getLoadedVT();
1641 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1642 default: assert(0 && "This action is not supported yet!");
1643 case TargetLowering::Promote:
1644 assert(SrcVT == MVT::i1 &&
1645 "Can only promote extending LOAD from i1 -> i8!");
1646 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1647 LD->getSrcValue(), LD->getSrcValueOffset(),
1648 MVT::i8, LD->isVolatile(), LD->getAlignment());
1649 Tmp1 = Result.getValue(0);
1650 Tmp2 = Result.getValue(1);
1652 case TargetLowering::Custom:
1655 case TargetLowering::Legal:
1656 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1657 Tmp1 = Result.getValue(0);
1658 Tmp2 = Result.getValue(1);
1661 Tmp3 = TLI.LowerOperation(Result, DAG);
1663 Tmp1 = LegalizeOp(Tmp3);
1664 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1667 // If this is an unaligned load and the target doesn't support it,
1669 if (!TLI.allowsUnalignedMemoryAccesses()) {
1670 unsigned ABIAlignment = TLI.getTargetData()->
1671 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1672 if (LD->getAlignment() < ABIAlignment){
1673 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1675 Tmp1 = Result.getOperand(0);
1676 Tmp2 = Result.getOperand(1);
1683 case TargetLowering::Expand:
1684 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1685 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1686 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1687 LD->getSrcValueOffset(),
1688 LD->isVolatile(), LD->getAlignment());
1689 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1690 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1691 Tmp2 = LegalizeOp(Load.getValue(1));
1694 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1695 // Turn the unsupported load into an EXTLOAD followed by an explicit
1696 // zero/sign extend inreg.
1697 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1698 Tmp1, Tmp2, LD->getSrcValue(),
1699 LD->getSrcValueOffset(), SrcVT,
1700 LD->isVolatile(), LD->getAlignment());
1702 if (ExtType == ISD::SEXTLOAD)
1703 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1704 Result, DAG.getValueType(SrcVT));
1706 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1707 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1708 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1711 // Since loads produce two values, make sure to remember that we legalized
1713 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1714 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1715 return Op.ResNo ? Tmp2 : Tmp1;
1718 case ISD::EXTRACT_ELEMENT: {
1719 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1720 switch (getTypeAction(OpTy)) {
1721 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1723 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1725 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1726 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1727 TLI.getShiftAmountTy()));
1728 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1731 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1732 Node->getOperand(0));
1736 // Get both the low and high parts.
1737 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1738 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1739 Result = Tmp2; // 1 -> Hi
1741 Result = Tmp1; // 0 -> Lo
1747 case ISD::CopyToReg:
1748 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1750 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1751 "Register type must be legal!");
1752 // Legalize the incoming value (must be a legal type).
1753 Tmp2 = LegalizeOp(Node->getOperand(2));
1754 if (Node->getNumValues() == 1) {
1755 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1757 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1758 if (Node->getNumOperands() == 4) {
1759 Tmp3 = LegalizeOp(Node->getOperand(3));
1760 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1763 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1766 // Since this produces two values, make sure to remember that we legalized
1768 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1769 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1777 // Ensure that libcalls are emitted before a return.
1778 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1779 Tmp1 = LegalizeOp(Tmp1);
1780 LastCALLSEQ_END = DAG.getEntryNode();
1782 switch (Node->getNumOperands()) {
1784 Tmp2 = Node->getOperand(1);
1785 Tmp3 = Node->getOperand(2); // Signness
1786 switch (getTypeAction(Tmp2.getValueType())) {
1788 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1791 if (!MVT::isVector(Tmp2.getValueType())) {
1793 ExpandOp(Tmp2, Lo, Hi);
1795 // Big endian systems want the hi reg first.
1796 if (!TLI.isLittleEndian())
1800 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1802 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1803 Result = LegalizeOp(Result);
1805 SDNode *InVal = Tmp2.Val;
1806 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1807 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1809 // Figure out if there is a simple type corresponding to this Vector
1810 // type. If so, convert to the vector type.
1811 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1812 if (TLI.isTypeLegal(TVT)) {
1813 // Turn this into a return of the vector type.
1814 Tmp2 = LegalizeOp(Tmp2);
1815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1816 } else if (NumElems == 1) {
1817 // Turn this into a return of the scalar type.
1818 Tmp2 = ScalarizeVectorOp(Tmp2);
1819 Tmp2 = LegalizeOp(Tmp2);
1820 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1822 // FIXME: Returns of gcc generic vectors smaller than a legal type
1823 // should be returned in integer registers!
1825 // The scalarized value type may not be legal, e.g. it might require
1826 // promotion or expansion. Relegalize the return.
1827 Result = LegalizeOp(Result);
1829 // FIXME: Returns of gcc generic vectors larger than a legal vector
1830 // type should be returned by reference!
1832 SplitVectorOp(Tmp2, Lo, Hi);
1833 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1834 Result = LegalizeOp(Result);
1839 Tmp2 = PromoteOp(Node->getOperand(1));
1840 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1841 Result = LegalizeOp(Result);
1846 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1848 default: { // ret <values>
1849 SmallVector<SDOperand, 8> NewValues;
1850 NewValues.push_back(Tmp1);
1851 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1852 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1854 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1855 NewValues.push_back(Node->getOperand(i+1));
1859 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1860 "FIXME: TODO: implement returning non-legal vector types!");
1861 ExpandOp(Node->getOperand(i), Lo, Hi);
1862 NewValues.push_back(Lo);
1863 NewValues.push_back(Node->getOperand(i+1));
1865 NewValues.push_back(Hi);
1866 NewValues.push_back(Node->getOperand(i+1));
1871 assert(0 && "Can't promote multiple return value yet!");
1874 if (NewValues.size() == Node->getNumOperands())
1875 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1877 Result = DAG.getNode(ISD::RET, MVT::Other,
1878 &NewValues[0], NewValues.size());
1883 if (Result.getOpcode() == ISD::RET) {
1884 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1885 default: assert(0 && "This action is not supported yet!");
1886 case TargetLowering::Legal: break;
1887 case TargetLowering::Custom:
1888 Tmp1 = TLI.LowerOperation(Result, DAG);
1889 if (Tmp1.Val) Result = Tmp1;
1895 StoreSDNode *ST = cast<StoreSDNode>(Node);
1896 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1897 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1898 int SVOffset = ST->getSrcValueOffset();
1899 unsigned Alignment = ST->getAlignment();
1900 bool isVolatile = ST->isVolatile();
1902 if (!ST->isTruncatingStore()) {
1903 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1904 // FIXME: We shouldn't do this for TargetConstantFP's.
1905 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1906 // to phase ordering between legalized code and the dag combiner. This
1907 // probably means that we need to integrate dag combiner and legalizer
1909 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1910 if (CFP->getValueType(0) == MVT::f32) {
1911 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1913 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1914 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1916 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1917 SVOffset, isVolatile, Alignment);
1921 switch (getTypeAction(ST->getStoredVT())) {
1923 Tmp3 = LegalizeOp(ST->getValue());
1924 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1927 MVT::ValueType VT = Tmp3.getValueType();
1928 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1929 default: assert(0 && "This action is not supported yet!");
1930 case TargetLowering::Legal:
1931 // If this is an unaligned store and the target doesn't support it,
1933 if (!TLI.allowsUnalignedMemoryAccesses()) {
1934 unsigned ABIAlignment = TLI.getTargetData()->
1935 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
1936 if (ST->getAlignment() < ABIAlignment)
1937 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
1941 case TargetLowering::Custom:
1942 Tmp1 = TLI.LowerOperation(Result, DAG);
1943 if (Tmp1.Val) Result = Tmp1;
1945 case TargetLowering::Promote:
1946 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1947 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1948 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1949 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1950 ST->getSrcValue(), SVOffset, isVolatile,
1957 // Truncate the value and store the result.
1958 Tmp3 = PromoteOp(ST->getValue());
1959 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1960 SVOffset, ST->getStoredVT(),
1961 isVolatile, Alignment);
1965 unsigned IncrementSize = 0;
1968 // If this is a vector type, then we have to calculate the increment as
1969 // the product of the element size in bytes, and the number of elements
1970 // in the high half of the vector.
1971 if (MVT::isVector(ST->getValue().getValueType())) {
1972 SDNode *InVal = ST->getValue().Val;
1973 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1974 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1976 // Figure out if there is a simple type corresponding to this Vector
1977 // type. If so, convert to the vector type.
1978 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1979 if (TLI.isTypeLegal(TVT)) {
1980 // Turn this into a normal store of the vector type.
1981 Tmp3 = LegalizeOp(Node->getOperand(1));
1982 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1983 SVOffset, isVolatile, Alignment);
1984 Result = LegalizeOp(Result);
1986 } else if (NumElems == 1) {
1987 // Turn this into a normal store of the scalar type.
1988 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
1989 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1990 SVOffset, isVolatile, Alignment);
1991 // The scalarized value type may not be legal, e.g. it might require
1992 // promotion or expansion. Relegalize the scalar store.
1993 Result = LegalizeOp(Result);
1996 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1997 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2000 ExpandOp(Node->getOperand(1), Lo, Hi);
2001 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2003 if (!TLI.isLittleEndian())
2007 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2008 SVOffset, isVolatile, Alignment);
2010 if (Hi.Val == NULL) {
2011 // Must be int <-> float one-to-one expansion.
2016 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2017 getIntPtrConstant(IncrementSize));
2018 assert(isTypeLegal(Tmp2.getValueType()) &&
2019 "Pointers must be legal!");
2020 SVOffset += IncrementSize;
2021 if (Alignment > IncrementSize)
2022 Alignment = IncrementSize;
2023 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2024 SVOffset, isVolatile, Alignment);
2025 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2030 assert(isTypeLegal(ST->getValue().getValueType()) &&
2031 "Cannot handle illegal TRUNCSTORE yet!");
2032 Tmp3 = LegalizeOp(ST->getValue());
2034 // The only promote case we handle is TRUNCSTORE:i1 X into
2035 // -> TRUNCSTORE:i8 (and X, 1)
2036 if (ST->getStoredVT() == MVT::i1 &&
2037 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2038 // Promote the bool to a mask then store.
2039 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2040 DAG.getConstant(1, Tmp3.getValueType()));
2041 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2043 isVolatile, Alignment);
2044 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2045 Tmp2 != ST->getBasePtr()) {
2046 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2050 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2051 switch (TLI.getStoreXAction(StVT)) {
2052 default: assert(0 && "This action is not supported yet!");
2053 case TargetLowering::Legal:
2054 // If this is an unaligned store and the target doesn't support it,
2056 if (!TLI.allowsUnalignedMemoryAccesses()) {
2057 unsigned ABIAlignment = TLI.getTargetData()->
2058 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2059 if (ST->getAlignment() < ABIAlignment)
2060 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2064 case TargetLowering::Custom:
2065 Tmp1 = TLI.LowerOperation(Result, DAG);
2066 if (Tmp1.Val) Result = Tmp1;
2073 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2074 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2076 case ISD::STACKSAVE:
2077 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2078 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2079 Tmp1 = Result.getValue(0);
2080 Tmp2 = Result.getValue(1);
2082 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2083 default: assert(0 && "This action is not supported yet!");
2084 case TargetLowering::Legal: break;
2085 case TargetLowering::Custom:
2086 Tmp3 = TLI.LowerOperation(Result, DAG);
2088 Tmp1 = LegalizeOp(Tmp3);
2089 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2092 case TargetLowering::Expand:
2093 // Expand to CopyFromReg if the target set
2094 // StackPointerRegisterToSaveRestore.
2095 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2096 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2097 Node->getValueType(0));
2098 Tmp2 = Tmp1.getValue(1);
2100 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2101 Tmp2 = Node->getOperand(0);
2106 // Since stacksave produce two values, make sure to remember that we
2107 // legalized both of them.
2108 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2109 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2110 return Op.ResNo ? Tmp2 : Tmp1;
2112 case ISD::STACKRESTORE:
2113 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2114 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2115 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2117 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2118 default: assert(0 && "This action is not supported yet!");
2119 case TargetLowering::Legal: break;
2120 case TargetLowering::Custom:
2121 Tmp1 = TLI.LowerOperation(Result, DAG);
2122 if (Tmp1.Val) Result = Tmp1;
2124 case TargetLowering::Expand:
2125 // Expand to CopyToReg if the target set
2126 // StackPointerRegisterToSaveRestore.
2127 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2128 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2136 case ISD::READCYCLECOUNTER:
2137 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2138 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2139 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2140 Node->getValueType(0))) {
2141 default: assert(0 && "This action is not supported yet!");
2142 case TargetLowering::Legal:
2143 Tmp1 = Result.getValue(0);
2144 Tmp2 = Result.getValue(1);
2146 case TargetLowering::Custom:
2147 Result = TLI.LowerOperation(Result, DAG);
2148 Tmp1 = LegalizeOp(Result.getValue(0));
2149 Tmp2 = LegalizeOp(Result.getValue(1));
2153 // Since rdcc produce two values, make sure to remember that we legalized
2155 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2156 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2160 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2161 case Expand: assert(0 && "It's impossible to expand bools");
2163 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2166 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2167 // Make sure the condition is either zero or one.
2168 if (!DAG.MaskedValueIsZero(Tmp1,
2169 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2170 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2173 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2174 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2178 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2179 default: assert(0 && "This action is not supported yet!");
2180 case TargetLowering::Legal: break;
2181 case TargetLowering::Custom: {
2182 Tmp1 = TLI.LowerOperation(Result, DAG);
2183 if (Tmp1.Val) Result = Tmp1;
2186 case TargetLowering::Expand:
2187 if (Tmp1.getOpcode() == ISD::SETCC) {
2188 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2190 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2192 Result = DAG.getSelectCC(Tmp1,
2193 DAG.getConstant(0, Tmp1.getValueType()),
2194 Tmp2, Tmp3, ISD::SETNE);
2197 case TargetLowering::Promote: {
2198 MVT::ValueType NVT =
2199 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2200 unsigned ExtOp, TruncOp;
2201 if (MVT::isVector(Tmp2.getValueType())) {
2202 ExtOp = ISD::BIT_CONVERT;
2203 TruncOp = ISD::BIT_CONVERT;
2204 } else if (MVT::isInteger(Tmp2.getValueType())) {
2205 ExtOp = ISD::ANY_EXTEND;
2206 TruncOp = ISD::TRUNCATE;
2208 ExtOp = ISD::FP_EXTEND;
2209 TruncOp = ISD::FP_ROUND;
2211 // Promote each of the values to the new type.
2212 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2213 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2214 // Perform the larger operation, then round down.
2215 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2216 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2221 case ISD::SELECT_CC: {
2222 Tmp1 = Node->getOperand(0); // LHS
2223 Tmp2 = Node->getOperand(1); // RHS
2224 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2225 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2226 SDOperand CC = Node->getOperand(4);
2228 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2230 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2231 // the LHS is a legal SETCC itself. In this case, we need to compare
2232 // the result against zero to select between true and false values.
2233 if (Tmp2.Val == 0) {
2234 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2235 CC = DAG.getCondCode(ISD::SETNE);
2237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2239 // Everything is legal, see if we should expand this op or something.
2240 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2241 default: assert(0 && "This action is not supported yet!");
2242 case TargetLowering::Legal: break;
2243 case TargetLowering::Custom:
2244 Tmp1 = TLI.LowerOperation(Result, DAG);
2245 if (Tmp1.Val) Result = Tmp1;
2251 Tmp1 = Node->getOperand(0);
2252 Tmp2 = Node->getOperand(1);
2253 Tmp3 = Node->getOperand(2);
2254 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2256 // If we had to Expand the SetCC operands into a SELECT node, then it may
2257 // not always be possible to return a true LHS & RHS. In this case, just
2258 // return the value we legalized, returned in the LHS
2259 if (Tmp2.Val == 0) {
2264 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2265 default: assert(0 && "Cannot handle this action for SETCC yet!");
2266 case TargetLowering::Custom:
2269 case TargetLowering::Legal:
2270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2272 Tmp4 = TLI.LowerOperation(Result, DAG);
2273 if (Tmp4.Val) Result = Tmp4;
2276 case TargetLowering::Promote: {
2277 // First step, figure out the appropriate operation to use.
2278 // Allow SETCC to not be supported for all legal data types
2279 // Mostly this targets FP
2280 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2281 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2283 // Scan for the appropriate larger type to use.
2285 NewInTy = (MVT::ValueType)(NewInTy+1);
2287 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2288 "Fell off of the edge of the integer world");
2289 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2290 "Fell off of the edge of the floating point world");
2292 // If the target supports SETCC of this type, use it.
2293 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2296 if (MVT::isInteger(NewInTy))
2297 assert(0 && "Cannot promote Legal Integer SETCC yet");
2299 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2300 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2302 Tmp1 = LegalizeOp(Tmp1);
2303 Tmp2 = LegalizeOp(Tmp2);
2304 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2305 Result = LegalizeOp(Result);
2308 case TargetLowering::Expand:
2309 // Expand a setcc node into a select_cc of the same condition, lhs, and
2310 // rhs that selects between const 1 (true) and const 0 (false).
2311 MVT::ValueType VT = Node->getValueType(0);
2312 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2313 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2320 case ISD::MEMMOVE: {
2321 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2322 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2324 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2325 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2326 case Expand: assert(0 && "Cannot expand a byte!");
2328 Tmp3 = LegalizeOp(Node->getOperand(2));
2331 Tmp3 = PromoteOp(Node->getOperand(2));
2335 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2339 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2341 // Length is too big, just take the lo-part of the length.
2343 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2347 Tmp4 = LegalizeOp(Node->getOperand(3));
2350 Tmp4 = PromoteOp(Node->getOperand(3));
2355 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2356 case Expand: assert(0 && "Cannot expand this yet!");
2358 Tmp5 = LegalizeOp(Node->getOperand(4));
2361 Tmp5 = PromoteOp(Node->getOperand(4));
2365 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2366 default: assert(0 && "This action not implemented for this operation!");
2367 case TargetLowering::Custom:
2370 case TargetLowering::Legal:
2371 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2373 Tmp1 = TLI.LowerOperation(Result, DAG);
2374 if (Tmp1.Val) Result = Tmp1;
2377 case TargetLowering::Expand: {
2378 // Otherwise, the target does not support this operation. Lower the
2379 // operation to an explicit libcall as appropriate.
2380 MVT::ValueType IntPtr = TLI.getPointerTy();
2381 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2382 TargetLowering::ArgListTy Args;
2383 TargetLowering::ArgListEntry Entry;
2385 const char *FnName = 0;
2386 if (Node->getOpcode() == ISD::MEMSET) {
2387 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2388 Args.push_back(Entry);
2389 // Extend the (previously legalized) ubyte argument to be an int value
2391 if (Tmp3.getValueType() > MVT::i32)
2392 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2394 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2395 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2396 Args.push_back(Entry);
2397 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2398 Args.push_back(Entry);
2401 } else if (Node->getOpcode() == ISD::MEMCPY ||
2402 Node->getOpcode() == ISD::MEMMOVE) {
2403 Entry.Ty = IntPtrTy;
2404 Entry.Node = Tmp2; Args.push_back(Entry);
2405 Entry.Node = Tmp3; Args.push_back(Entry);
2406 Entry.Node = Tmp4; Args.push_back(Entry);
2407 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2409 assert(0 && "Unknown op!");
2412 std::pair<SDOperand,SDOperand> CallResult =
2413 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2414 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2415 Result = CallResult.second;
2422 case ISD::SHL_PARTS:
2423 case ISD::SRA_PARTS:
2424 case ISD::SRL_PARTS: {
2425 SmallVector<SDOperand, 8> Ops;
2426 bool Changed = false;
2427 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2428 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2429 Changed |= Ops.back() != Node->getOperand(i);
2432 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2434 switch (TLI.getOperationAction(Node->getOpcode(),
2435 Node->getValueType(0))) {
2436 default: assert(0 && "This action is not supported yet!");
2437 case TargetLowering::Legal: break;
2438 case TargetLowering::Custom:
2439 Tmp1 = TLI.LowerOperation(Result, DAG);
2441 SDOperand Tmp2, RetVal(0, 0);
2442 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2443 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2444 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2448 assert(RetVal.Val && "Illegal result number");
2454 // Since these produce multiple values, make sure to remember that we
2455 // legalized all of them.
2456 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2457 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2458 return Result.getValue(Op.ResNo);
2479 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2480 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2481 case Expand: assert(0 && "Not possible");
2483 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2486 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2490 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2492 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2493 default: assert(0 && "BinOp legalize operation not supported");
2494 case TargetLowering::Legal: break;
2495 case TargetLowering::Custom:
2496 Tmp1 = TLI.LowerOperation(Result, DAG);
2497 if (Tmp1.Val) Result = Tmp1;
2499 case TargetLowering::Expand: {
2500 if (Node->getValueType(0) == MVT::i32) {
2501 switch (Node->getOpcode()) {
2502 default: assert(0 && "Do not know how to expand this integer BinOp!");
2505 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2506 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2508 bool isSigned = Node->getOpcode() == ISD::SDIV;
2509 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2514 assert(MVT::isVector(Node->getValueType(0)) &&
2515 "Cannot expand this binary operator!");
2516 // Expand the operation into a bunch of nasty scalar code.
2517 SmallVector<SDOperand, 8> Ops;
2518 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2519 MVT::ValueType PtrVT = TLI.getPointerTy();
2520 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2522 SDOperand Idx = DAG.getConstant(i, PtrVT);
2523 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2524 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2525 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2527 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2528 &Ops[0], Ops.size());
2531 case TargetLowering::Promote: {
2532 switch (Node->getOpcode()) {
2533 default: assert(0 && "Do not know how to promote this BinOp!");
2537 MVT::ValueType OVT = Node->getValueType(0);
2538 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2539 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2540 // Bit convert each of the values to the new type.
2541 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2542 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2543 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2544 // Bit convert the result back the original type.
2545 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2553 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2554 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2555 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2556 case Expand: assert(0 && "Not possible");
2558 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2561 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2565 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2567 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2568 default: assert(0 && "Operation not supported");
2569 case TargetLowering::Custom:
2570 Tmp1 = TLI.LowerOperation(Result, DAG);
2571 if (Tmp1.Val) Result = Tmp1;
2573 case TargetLowering::Legal: break;
2574 case TargetLowering::Expand: {
2575 // If this target supports fabs/fneg natively and select is cheap,
2576 // do this efficiently.
2577 if (!TLI.isSelectExpensive() &&
2578 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2579 TargetLowering::Legal &&
2580 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2581 TargetLowering::Legal) {
2582 // Get the sign bit of the RHS.
2583 MVT::ValueType IVT =
2584 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2585 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2586 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2587 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2588 // Get the absolute value of the result.
2589 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2590 // Select between the nabs and abs value based on the sign bit of
2592 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2593 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2596 Result = LegalizeOp(Result);
2600 // Otherwise, do bitwise ops!
2601 MVT::ValueType NVT =
2602 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2603 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2604 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2605 Result = LegalizeOp(Result);
2613 Tmp1 = LegalizeOp(Node->getOperand(0));
2614 Tmp2 = LegalizeOp(Node->getOperand(1));
2615 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2616 // Since this produces two values, make sure to remember that we legalized
2618 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2619 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2624 Tmp1 = LegalizeOp(Node->getOperand(0));
2625 Tmp2 = LegalizeOp(Node->getOperand(1));
2626 Tmp3 = LegalizeOp(Node->getOperand(2));
2627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2628 // Since this produces two values, make sure to remember that we legalized
2630 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2631 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2634 case ISD::BUILD_PAIR: {
2635 MVT::ValueType PairTy = Node->getValueType(0);
2636 // TODO: handle the case where the Lo and Hi operands are not of legal type
2637 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2638 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2639 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2640 case TargetLowering::Promote:
2641 case TargetLowering::Custom:
2642 assert(0 && "Cannot promote/custom this yet!");
2643 case TargetLowering::Legal:
2644 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2645 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2647 case TargetLowering::Expand:
2648 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2649 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2650 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2651 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2652 TLI.getShiftAmountTy()));
2653 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2662 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2663 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2665 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2666 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2667 case TargetLowering::Custom:
2670 case TargetLowering::Legal:
2671 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2673 Tmp1 = TLI.LowerOperation(Result, DAG);
2674 if (Tmp1.Val) Result = Tmp1;
2677 case TargetLowering::Expand:
2678 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2679 bool isSigned = DivOpc == ISD::SDIV;
2680 if (MVT::isInteger(Node->getValueType(0))) {
2681 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2682 TargetLowering::Legal) {
2684 MVT::ValueType VT = Node->getValueType(0);
2685 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2686 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2687 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2689 assert(Node->getValueType(0) == MVT::i32 &&
2690 "Cannot expand this binary operator!");
2691 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2692 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2694 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2697 // Floating point mod -> fmod libcall.
2698 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2699 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2701 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2702 false/*sign irrelevant*/, Dummy);
2708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2709 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2711 MVT::ValueType VT = Node->getValueType(0);
2712 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2713 default: assert(0 && "This action is not supported yet!");
2714 case TargetLowering::Custom:
2717 case TargetLowering::Legal:
2718 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2719 Result = Result.getValue(0);
2720 Tmp1 = Result.getValue(1);
2723 Tmp2 = TLI.LowerOperation(Result, DAG);
2725 Result = LegalizeOp(Tmp2);
2726 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2730 case TargetLowering::Expand: {
2731 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2732 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2733 SV->getValue(), SV->getOffset());
2734 // Increment the pointer, VAList, to the next vaarg
2735 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2736 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2737 TLI.getPointerTy()));
2738 // Store the incremented VAList to the legalized pointer
2739 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2741 // Load the actual argument out of the pointer VAList
2742 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2743 Tmp1 = LegalizeOp(Result.getValue(1));
2744 Result = LegalizeOp(Result);
2748 // Since VAARG produces two values, make sure to remember that we
2749 // legalized both of them.
2750 AddLegalizedOperand(SDOperand(Node, 0), Result);
2751 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2752 return Op.ResNo ? Tmp1 : Result;
2756 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2757 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2758 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2760 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2761 default: assert(0 && "This action is not supported yet!");
2762 case TargetLowering::Custom:
2765 case TargetLowering::Legal:
2766 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2767 Node->getOperand(3), Node->getOperand(4));
2769 Tmp1 = TLI.LowerOperation(Result, DAG);
2770 if (Tmp1.Val) Result = Tmp1;
2773 case TargetLowering::Expand:
2774 // This defaults to loading a pointer from the input and storing it to the
2775 // output, returning the chain.
2776 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2777 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2778 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2780 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2787 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2788 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2790 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2791 default: assert(0 && "This action is not supported yet!");
2792 case TargetLowering::Custom:
2795 case TargetLowering::Legal:
2796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2798 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2799 if (Tmp1.Val) Result = Tmp1;
2802 case TargetLowering::Expand:
2803 Result = Tmp1; // Default to a no-op, return the chain
2809 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2810 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2814 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2815 default: assert(0 && "This action is not supported yet!");
2816 case TargetLowering::Legal: break;
2817 case TargetLowering::Custom:
2818 Tmp1 = TLI.LowerOperation(Result, DAG);
2819 if (Tmp1.Val) Result = Tmp1;
2826 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2827 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2828 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2829 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2831 assert(0 && "ROTL/ROTR legalize operation not supported");
2833 case TargetLowering::Legal:
2835 case TargetLowering::Custom:
2836 Tmp1 = TLI.LowerOperation(Result, DAG);
2837 if (Tmp1.Val) Result = Tmp1;
2839 case TargetLowering::Promote:
2840 assert(0 && "Do not know how to promote ROTL/ROTR");
2842 case TargetLowering::Expand:
2843 assert(0 && "Do not know how to expand ROTL/ROTR");
2849 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2850 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2851 case TargetLowering::Custom:
2852 assert(0 && "Cannot custom legalize this yet!");
2853 case TargetLowering::Legal:
2854 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2856 case TargetLowering::Promote: {
2857 MVT::ValueType OVT = Tmp1.getValueType();
2858 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2859 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2861 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2862 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2863 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2864 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2867 case TargetLowering::Expand:
2868 Result = ExpandBSWAP(Tmp1);
2876 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2877 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2878 case TargetLowering::Custom:
2879 case TargetLowering::Legal:
2880 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2881 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
2882 TargetLowering::Custom) {
2883 Tmp1 = TLI.LowerOperation(Result, DAG);
2889 case TargetLowering::Promote: {
2890 MVT::ValueType OVT = Tmp1.getValueType();
2891 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2893 // Zero extend the argument.
2894 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2895 // Perform the larger operation, then subtract if needed.
2896 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2897 switch (Node->getOpcode()) {
2902 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2903 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2904 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2906 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2907 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2910 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2911 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2912 DAG.getConstant(MVT::getSizeInBits(NVT) -
2913 MVT::getSizeInBits(OVT), NVT));
2918 case TargetLowering::Expand:
2919 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2930 Tmp1 = LegalizeOp(Node->getOperand(0));
2931 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2932 case TargetLowering::Promote:
2933 case TargetLowering::Custom:
2936 case TargetLowering::Legal:
2937 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2939 Tmp1 = TLI.LowerOperation(Result, DAG);
2940 if (Tmp1.Val) Result = Tmp1;
2943 case TargetLowering::Expand:
2944 switch (Node->getOpcode()) {
2945 default: assert(0 && "Unreachable!");
2947 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2948 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2949 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2952 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2953 MVT::ValueType VT = Node->getValueType(0);
2954 Tmp2 = DAG.getConstantFP(0.0, VT);
2955 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2956 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2957 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2963 MVT::ValueType VT = Node->getValueType(0);
2964 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2965 switch(Node->getOpcode()) {
2967 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2970 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2973 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2975 default: assert(0 && "Unreachable!");
2978 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2979 false/*sign irrelevant*/, Dummy);
2987 // We always lower FPOWI into a libcall. No target support it yet.
2988 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2989 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2991 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2992 false/*sign irrelevant*/, Dummy);
2995 case ISD::BIT_CONVERT:
2996 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2997 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2998 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
2999 // The input has to be a vector type, we have to either scalarize it, pack
3000 // it, or convert it based on whether the input vector type is legal.
3001 SDNode *InVal = Node->getOperand(0).Val;
3002 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3003 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3005 // Figure out if there is a simple type corresponding to this Vector
3006 // type. If so, convert to the vector type.
3007 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3008 if (TLI.isTypeLegal(TVT)) {
3009 // Turn this into a bit convert of the vector input.
3010 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3011 LegalizeOp(Node->getOperand(0)));
3013 } else if (NumElems == 1) {
3014 // Turn this into a bit convert of the scalar input.
3015 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3016 ScalarizeVectorOp(Node->getOperand(0)));
3019 // FIXME: UNIMP! Store then reload
3020 assert(0 && "Cast from unsupported vector type not implemented yet!");
3023 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3024 Node->getOperand(0).getValueType())) {
3025 default: assert(0 && "Unknown operation action!");
3026 case TargetLowering::Expand:
3027 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3029 case TargetLowering::Legal:
3030 Tmp1 = LegalizeOp(Node->getOperand(0));
3031 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3037 // Conversion operators. The source and destination have different types.
3038 case ISD::SINT_TO_FP:
3039 case ISD::UINT_TO_FP: {
3040 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3041 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3043 switch (TLI.getOperationAction(Node->getOpcode(),
3044 Node->getOperand(0).getValueType())) {
3045 default: assert(0 && "Unknown operation action!");
3046 case TargetLowering::Custom:
3049 case TargetLowering::Legal:
3050 Tmp1 = LegalizeOp(Node->getOperand(0));
3051 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3053 Tmp1 = TLI.LowerOperation(Result, DAG);
3054 if (Tmp1.Val) Result = Tmp1;
3057 case TargetLowering::Expand:
3058 Result = ExpandLegalINT_TO_FP(isSigned,
3059 LegalizeOp(Node->getOperand(0)),
3060 Node->getValueType(0));
3062 case TargetLowering::Promote:
3063 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3064 Node->getValueType(0),
3070 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3071 Node->getValueType(0), Node->getOperand(0));
3074 Tmp1 = PromoteOp(Node->getOperand(0));
3076 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3077 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3079 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3080 Node->getOperand(0).getValueType());
3082 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3083 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3089 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3091 Tmp1 = LegalizeOp(Node->getOperand(0));
3092 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3095 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3097 // Since the result is legal, we should just be able to truncate the low
3098 // part of the source.
3099 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3102 Result = PromoteOp(Node->getOperand(0));
3103 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3108 case ISD::FP_TO_SINT:
3109 case ISD::FP_TO_UINT:
3110 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3112 Tmp1 = LegalizeOp(Node->getOperand(0));
3114 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3115 default: assert(0 && "Unknown operation action!");
3116 case TargetLowering::Custom:
3119 case TargetLowering::Legal:
3120 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3122 Tmp1 = TLI.LowerOperation(Result, DAG);
3123 if (Tmp1.Val) Result = Tmp1;
3126 case TargetLowering::Promote:
3127 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3128 Node->getOpcode() == ISD::FP_TO_SINT);
3130 case TargetLowering::Expand:
3131 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3132 SDOperand True, False;
3133 MVT::ValueType VT = Node->getOperand(0).getValueType();
3134 MVT::ValueType NVT = Node->getValueType(0);
3135 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
3136 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
3137 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3138 Node->getOperand(0), Tmp2, ISD::SETLT);
3139 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3140 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3141 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3143 False = DAG.getNode(ISD::XOR, NVT, False,
3144 DAG.getConstant(1ULL << ShiftAmt, NVT));
3145 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3148 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3154 // Convert f32 / f64 to i32 / i64.
3155 MVT::ValueType VT = Op.getValueType();
3156 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3157 switch (Node->getOpcode()) {
3158 case ISD::FP_TO_SINT:
3159 if (Node->getOperand(0).getValueType() == MVT::f32)
3160 LC = (VT == MVT::i32)
3161 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3163 LC = (VT == MVT::i32)
3164 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3166 case ISD::FP_TO_UINT:
3167 if (Node->getOperand(0).getValueType() == MVT::f32)
3168 LC = (VT == MVT::i32)
3169 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3171 LC = (VT == MVT::i32)
3172 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3174 default: assert(0 && "Unreachable!");
3177 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3178 false/*sign irrelevant*/, Dummy);
3182 Tmp1 = PromoteOp(Node->getOperand(0));
3183 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3184 Result = LegalizeOp(Result);
3190 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3191 TargetLowering::Expand) {
3192 // The only way we can lower this is to turn it into a TRUNCSTORE,
3193 // EXTLOAD pair, targetting a temporary location (a stack slot).
3195 // NOTE: there is a choice here between constantly creating new stack
3196 // slots and always reusing the same one. We currently always create
3197 // new ones, as reuse may inhibit scheduling.
3198 MVT::ValueType VT = Op.getValueType(); // 32
3199 const Type *Ty = MVT::getTypeForValueType(VT);
3200 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3201 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3202 MachineFunction &MF = DAG.getMachineFunction();
3204 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3205 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3206 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3207 StackSlot, NULL, 0, VT);
3208 Result = DAG.getLoad(VT, Result, StackSlot, NULL, 0, VT);
3212 case ISD::ANY_EXTEND:
3213 case ISD::ZERO_EXTEND:
3214 case ISD::SIGN_EXTEND:
3215 case ISD::FP_EXTEND:
3216 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3217 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3219 Tmp1 = LegalizeOp(Node->getOperand(0));
3220 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3223 switch (Node->getOpcode()) {
3224 case ISD::ANY_EXTEND:
3225 Tmp1 = PromoteOp(Node->getOperand(0));
3226 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3228 case ISD::ZERO_EXTEND:
3229 Result = PromoteOp(Node->getOperand(0));
3230 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3231 Result = DAG.getZeroExtendInReg(Result,
3232 Node->getOperand(0).getValueType());
3234 case ISD::SIGN_EXTEND:
3235 Result = PromoteOp(Node->getOperand(0));
3236 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3237 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3239 DAG.getValueType(Node->getOperand(0).getValueType()));
3241 case ISD::FP_EXTEND:
3242 Result = PromoteOp(Node->getOperand(0));
3243 if (Result.getValueType() != Op.getValueType())
3244 // Dynamically dead while we have only 2 FP types.
3245 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3248 Result = PromoteOp(Node->getOperand(0));
3249 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3254 case ISD::FP_ROUND_INREG:
3255 case ISD::SIGN_EXTEND_INREG: {
3256 Tmp1 = LegalizeOp(Node->getOperand(0));
3257 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3259 // If this operation is not supported, convert it to a shl/shr or load/store
3261 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3262 default: assert(0 && "This action not supported for this op yet!");
3263 case TargetLowering::Legal:
3264 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3266 case TargetLowering::Expand:
3267 // If this is an integer extend and shifts are supported, do that.
3268 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3269 // NOTE: we could fall back on load/store here too for targets without
3270 // SAR. However, it is doubtful that any exist.
3271 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3272 MVT::getSizeInBits(ExtraVT);
3273 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3274 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3275 Node->getOperand(0), ShiftCst);
3276 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3278 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3279 // The only way we can lower this is to turn it into a TRUNCSTORE,
3280 // EXTLOAD pair, targetting a temporary location (a stack slot).
3282 // NOTE: there is a choice here between constantly creating new stack
3283 // slots and always reusing the same one. We currently always create
3284 // new ones, as reuse may inhibit scheduling.
3285 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3286 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3287 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3288 MachineFunction &MF = DAG.getMachineFunction();
3290 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3291 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3292 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3293 StackSlot, NULL, 0, ExtraVT);
3294 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3295 Result, StackSlot, NULL, 0, ExtraVT);
3297 assert(0 && "Unknown op");
3303 case ISD::ADJUST_TRAMP: {
3304 Tmp1 = LegalizeOp(Node->getOperand(0));
3305 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3306 default: assert(0 && "This action is not supported yet!");
3307 case TargetLowering::Custom:
3308 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3309 Result = TLI.LowerOperation(Result, DAG);
3310 if (Result.Val) break;
3312 case TargetLowering::Expand:
3318 case ISD::TRAMPOLINE: {
3320 for (unsigned i = 0; i != 6; ++i)
3321 Ops[i] = LegalizeOp(Node->getOperand(i));
3322 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3323 // The only option for this node is to custom lower it.
3324 Result = TLI.LowerOperation(Result, DAG);
3325 assert(Result.Val && "Should always custom lower!");
3330 assert(Result.getValueType() == Op.getValueType() &&
3331 "Bad legalization!");
3333 // Make sure that the generated code is itself legal.
3335 Result = LegalizeOp(Result);
3337 // Note that LegalizeOp may be reentered even from single-use nodes, which
3338 // means that we always must cache transformed nodes.
3339 AddLegalizedOperand(Op, Result);
3343 /// PromoteOp - Given an operation that produces a value in an invalid type,
3344 /// promote it to compute the value into a larger type. The produced value will
3345 /// have the correct bits for the low portion of the register, but no guarantee
3346 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3347 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3348 MVT::ValueType VT = Op.getValueType();
3349 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3350 assert(getTypeAction(VT) == Promote &&
3351 "Caller should expand or legalize operands that are not promotable!");
3352 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3353 "Cannot promote to smaller type!");
3355 SDOperand Tmp1, Tmp2, Tmp3;
3357 SDNode *Node = Op.Val;
3359 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3360 if (I != PromotedNodes.end()) return I->second;
3362 switch (Node->getOpcode()) {
3363 case ISD::CopyFromReg:
3364 assert(0 && "CopyFromReg must be legal!");
3367 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3369 assert(0 && "Do not know how to promote this operator!");
3372 Result = DAG.getNode(ISD::UNDEF, NVT);
3376 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3378 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3379 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3381 case ISD::ConstantFP:
3382 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3383 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3387 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3388 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3389 Node->getOperand(1), Node->getOperand(2));
3393 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3395 Result = LegalizeOp(Node->getOperand(0));
3396 assert(Result.getValueType() >= NVT &&
3397 "This truncation doesn't make sense!");
3398 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3399 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3402 // The truncation is not required, because we don't guarantee anything
3403 // about high bits anyway.
3404 Result = PromoteOp(Node->getOperand(0));
3407 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3408 // Truncate the low part of the expanded value to the result type
3409 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3412 case ISD::SIGN_EXTEND:
3413 case ISD::ZERO_EXTEND:
3414 case ISD::ANY_EXTEND:
3415 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3416 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3418 // Input is legal? Just do extend all the way to the larger type.
3419 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3422 // Promote the reg if it's smaller.
3423 Result = PromoteOp(Node->getOperand(0));
3424 // The high bits are not guaranteed to be anything. Insert an extend.
3425 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3426 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3427 DAG.getValueType(Node->getOperand(0).getValueType()));
3428 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3429 Result = DAG.getZeroExtendInReg(Result,
3430 Node->getOperand(0).getValueType());
3434 case ISD::BIT_CONVERT:
3435 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3436 Result = PromoteOp(Result);
3439 case ISD::FP_EXTEND:
3440 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3442 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3443 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3444 case Promote: assert(0 && "Unreachable with 2 FP types!");
3446 // Input is legal? Do an FP_ROUND_INREG.
3447 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3448 DAG.getValueType(VT));
3453 case ISD::SINT_TO_FP:
3454 case ISD::UINT_TO_FP:
3455 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3457 // No extra round required here.
3458 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3462 Result = PromoteOp(Node->getOperand(0));
3463 if (Node->getOpcode() == ISD::SINT_TO_FP)
3464 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3466 DAG.getValueType(Node->getOperand(0).getValueType()));
3468 Result = DAG.getZeroExtendInReg(Result,
3469 Node->getOperand(0).getValueType());
3470 // No extra round required here.
3471 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3474 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3475 Node->getOperand(0));
3476 // Round if we cannot tolerate excess precision.
3477 if (NoExcessFPPrecision)
3478 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3479 DAG.getValueType(VT));
3484 case ISD::SIGN_EXTEND_INREG:
3485 Result = PromoteOp(Node->getOperand(0));
3486 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3487 Node->getOperand(1));
3489 case ISD::FP_TO_SINT:
3490 case ISD::FP_TO_UINT:
3491 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3494 Tmp1 = Node->getOperand(0);
3497 // The input result is prerounded, so we don't have to do anything
3499 Tmp1 = PromoteOp(Node->getOperand(0));
3502 // If we're promoting a UINT to a larger size, check to see if the new node
3503 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3504 // we can use that instead. This allows us to generate better code for
3505 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3506 // legal, such as PowerPC.
3507 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3508 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3509 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3510 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3511 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3513 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3519 Tmp1 = PromoteOp(Node->getOperand(0));
3520 assert(Tmp1.getValueType() == NVT);
3521 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3522 // NOTE: we do not have to do any extra rounding here for
3523 // NoExcessFPPrecision, because we know the input will have the appropriate
3524 // precision, and these operations don't modify precision at all.
3530 Tmp1 = PromoteOp(Node->getOperand(0));
3531 assert(Tmp1.getValueType() == NVT);
3532 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3533 if (NoExcessFPPrecision)
3534 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3535 DAG.getValueType(VT));
3539 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3540 // directly as well, which may be better.
3541 Tmp1 = PromoteOp(Node->getOperand(0));
3542 assert(Tmp1.getValueType() == NVT);
3543 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3544 if (NoExcessFPPrecision)
3545 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3546 DAG.getValueType(VT));
3556 // The input may have strange things in the top bits of the registers, but
3557 // these operations don't care. They may have weird bits going out, but
3558 // that too is okay if they are integer operations.
3559 Tmp1 = PromoteOp(Node->getOperand(0));
3560 Tmp2 = PromoteOp(Node->getOperand(1));
3561 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3562 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3567 Tmp1 = PromoteOp(Node->getOperand(0));
3568 Tmp2 = PromoteOp(Node->getOperand(1));
3569 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3570 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3572 // Floating point operations will give excess precision that we may not be
3573 // able to tolerate. If we DO allow excess precision, just leave it,
3574 // otherwise excise it.
3575 // FIXME: Why would we need to round FP ops more than integer ones?
3576 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3577 if (NoExcessFPPrecision)
3578 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3579 DAG.getValueType(VT));
3584 // These operators require that their input be sign extended.
3585 Tmp1 = PromoteOp(Node->getOperand(0));
3586 Tmp2 = PromoteOp(Node->getOperand(1));
3587 if (MVT::isInteger(NVT)) {
3588 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3589 DAG.getValueType(VT));
3590 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3591 DAG.getValueType(VT));
3593 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3595 // Perform FP_ROUND: this is probably overly pessimistic.
3596 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3597 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3598 DAG.getValueType(VT));
3602 case ISD::FCOPYSIGN:
3603 // These operators require that their input be fp extended.
3604 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3606 Tmp1 = LegalizeOp(Node->getOperand(0));
3609 Tmp1 = PromoteOp(Node->getOperand(0));
3612 assert(0 && "not implemented");
3614 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3616 Tmp2 = LegalizeOp(Node->getOperand(1));
3619 Tmp2 = PromoteOp(Node->getOperand(1));
3622 assert(0 && "not implemented");
3624 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3626 // Perform FP_ROUND: this is probably overly pessimistic.
3627 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3628 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3629 DAG.getValueType(VT));
3634 // These operators require that their input be zero extended.
3635 Tmp1 = PromoteOp(Node->getOperand(0));
3636 Tmp2 = PromoteOp(Node->getOperand(1));
3637 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3638 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3639 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3640 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3644 Tmp1 = PromoteOp(Node->getOperand(0));
3645 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3648 // The input value must be properly sign extended.
3649 Tmp1 = PromoteOp(Node->getOperand(0));
3650 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3651 DAG.getValueType(VT));
3652 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3655 // The input value must be properly zero extended.
3656 Tmp1 = PromoteOp(Node->getOperand(0));
3657 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3658 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3662 Tmp1 = Node->getOperand(0); // Get the chain.
3663 Tmp2 = Node->getOperand(1); // Get the pointer.
3664 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3665 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3666 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3668 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3669 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3670 SV->getValue(), SV->getOffset());
3671 // Increment the pointer, VAList, to the next vaarg
3672 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3673 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3674 TLI.getPointerTy()));
3675 // Store the incremented VAList to the legalized pointer
3676 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3678 // Load the actual argument out of the pointer VAList
3679 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3681 // Remember that we legalized the chain.
3682 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3686 LoadSDNode *LD = cast<LoadSDNode>(Node);
3687 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3688 ? ISD::EXTLOAD : LD->getExtensionType();
3689 Result = DAG.getExtLoad(ExtType, NVT,
3690 LD->getChain(), LD->getBasePtr(),
3691 LD->getSrcValue(), LD->getSrcValueOffset(),
3694 LD->getAlignment());
3695 // Remember that we legalized the chain.
3696 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3700 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3701 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3702 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3704 case ISD::SELECT_CC:
3705 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3706 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3707 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3708 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3711 Tmp1 = Node->getOperand(0);
3712 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3713 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3714 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3715 DAG.getConstant(MVT::getSizeInBits(NVT) -
3716 MVT::getSizeInBits(VT),
3717 TLI.getShiftAmountTy()));
3722 // Zero extend the argument
3723 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3724 // Perform the larger operation, then subtract if needed.
3725 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3726 switch(Node->getOpcode()) {
3731 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3732 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3733 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3735 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3736 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3739 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3740 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3741 DAG.getConstant(MVT::getSizeInBits(NVT) -
3742 MVT::getSizeInBits(VT), NVT));
3746 case ISD::EXTRACT_SUBVECTOR:
3747 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3749 case ISD::EXTRACT_VECTOR_ELT:
3750 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3754 assert(Result.Val && "Didn't set a result!");
3756 // Make sure the result is itself legal.
3757 Result = LegalizeOp(Result);
3759 // Remember that we promoted this!
3760 AddPromotedOperand(Op, Result);
3764 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3765 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3766 /// based on the vector type. The return type of this matches the element type
3767 /// of the vector, which may not be legal for the target.
3768 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3769 // We know that operand #0 is the Vec vector. If the index is a constant
3770 // or if the invec is a supported hardware type, we can use it. Otherwise,
3771 // lower to a store then an indexed load.
3772 SDOperand Vec = Op.getOperand(0);
3773 SDOperand Idx = Op.getOperand(1);
3775 SDNode *InVal = Vec.Val;
3776 MVT::ValueType TVT = InVal->getValueType(0);
3777 unsigned NumElems = MVT::getVectorNumElements(TVT);
3779 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3780 default: assert(0 && "This action is not supported yet!");
3781 case TargetLowering::Custom: {
3782 Vec = LegalizeOp(Vec);
3783 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3784 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3789 case TargetLowering::Legal:
3790 if (isTypeLegal(TVT)) {
3791 Vec = LegalizeOp(Vec);
3792 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3796 case TargetLowering::Expand:
3800 if (NumElems == 1) {
3801 // This must be an access of the only element. Return it.
3802 Op = ScalarizeVectorOp(Vec);
3803 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3804 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3806 SplitVectorOp(Vec, Lo, Hi);
3807 if (CIdx->getValue() < NumElems/2) {
3811 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3812 Idx.getValueType());
3815 // It's now an extract from the appropriate high or low part. Recurse.
3816 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3817 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3819 // Store the value to a temporary stack slot, then LOAD the scalar
3820 // element back out.
3821 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3822 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3824 // Add the offset to the index.
3825 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3826 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3827 DAG.getConstant(EltSize, Idx.getValueType()));
3828 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3830 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3835 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3836 /// we assume the operation can be split if it is not already legal.
3837 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3838 // We know that operand #0 is the Vec vector. For now we assume the index
3839 // is a constant and that the extracted result is a supported hardware type.
3840 SDOperand Vec = Op.getOperand(0);
3841 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3843 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3845 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3846 // This must be an access of the desired vector length. Return it.
3850 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3852 SplitVectorOp(Vec, Lo, Hi);
3853 if (CIdx->getValue() < NumElems/2) {
3857 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3860 // It's now an extract from the appropriate high or low part. Recurse.
3861 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3862 return ExpandEXTRACT_SUBVECTOR(Op);
3865 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3866 /// with condition CC on the current target. This usually involves legalizing
3867 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3868 /// there may be no choice but to create a new SetCC node to represent the
3869 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3870 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3871 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3874 SDOperand Tmp1, Tmp2, Result;
3876 switch (getTypeAction(LHS.getValueType())) {
3878 Tmp1 = LegalizeOp(LHS); // LHS
3879 Tmp2 = LegalizeOp(RHS); // RHS
3882 Tmp1 = PromoteOp(LHS); // LHS
3883 Tmp2 = PromoteOp(RHS); // RHS
3885 // If this is an FP compare, the operands have already been extended.
3886 if (MVT::isInteger(LHS.getValueType())) {
3887 MVT::ValueType VT = LHS.getValueType();
3888 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3890 // Otherwise, we have to insert explicit sign or zero extends. Note
3891 // that we could insert sign extends for ALL conditions, but zero extend
3892 // is cheaper on many machines (an AND instead of two shifts), so prefer
3894 switch (cast<CondCodeSDNode>(CC)->get()) {
3895 default: assert(0 && "Unknown integer comparison!");
3902 // ALL of these operations will work if we either sign or zero extend
3903 // the operands (including the unsigned comparisons!). Zero extend is
3904 // usually a simpler/cheaper operation, so prefer it.
3905 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3906 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3912 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3913 DAG.getValueType(VT));
3914 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3915 DAG.getValueType(VT));
3921 MVT::ValueType VT = LHS.getValueType();
3922 if (VT == MVT::f32 || VT == MVT::f64) {
3923 // Expand into one or more soft-fp libcall(s).
3924 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3925 switch (cast<CondCodeSDNode>(CC)->get()) {
3928 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3932 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3936 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3940 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3944 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3948 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3951 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3954 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3957 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3958 switch (cast<CondCodeSDNode>(CC)->get()) {
3960 // SETONE = SETOLT | SETOGT
3961 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3964 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3967 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3970 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3973 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3976 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3978 default: assert(0 && "Unsupported FP setcc!");
3983 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3984 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3985 false /*sign irrelevant*/, Dummy);
3986 Tmp2 = DAG.getConstant(0, MVT::i32);
3987 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
3988 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3989 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3990 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3991 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3992 false /*sign irrelevant*/, Dummy);
3993 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3994 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
3995 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4003 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4004 ExpandOp(LHS, LHSLo, LHSHi);
4005 ExpandOp(RHS, RHSLo, RHSHi);
4006 switch (cast<CondCodeSDNode>(CC)->get()) {
4010 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4011 if (RHSCST->isAllOnesValue()) {
4012 // Comparison to -1.
4013 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4018 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4019 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4020 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4021 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4024 // If this is a comparison of the sign bit, just look at the top part.
4026 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4027 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4028 CST->getValue() == 0) || // X < 0
4029 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4030 CST->isAllOnesValue())) { // X > -1
4036 // FIXME: This generated code sucks.
4037 ISD::CondCode LowCC;
4038 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4040 default: assert(0 && "Unknown integer setcc!");
4042 case ISD::SETULT: LowCC = ISD::SETULT; break;
4044 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4046 case ISD::SETULE: LowCC = ISD::SETULE; break;
4048 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4051 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4052 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4053 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4055 // NOTE: on targets without efficient SELECT of bools, we can always use
4056 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4057 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4058 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4059 false, DagCombineInfo);
4061 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4062 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4063 CCCode, false, DagCombineInfo);
4065 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
4067 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4068 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4069 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4070 (Tmp2C && Tmp2C->getValue() == 0 &&
4071 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4072 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4073 (Tmp2C && Tmp2C->getValue() == 1 &&
4074 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4075 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4076 // low part is known false, returns high part.
4077 // For LE / GE, if high part is known false, ignore the low part.
4078 // For LT / GT, if high part is known true, ignore the low part.
4082 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4083 ISD::SETEQ, false, DagCombineInfo);
4085 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4086 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4087 Result, Tmp1, Tmp2));
4098 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4099 /// The resultant code need not be legal. Note that SrcOp is the input operand
4100 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4101 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4103 // Create the stack frame object.
4104 SDOperand FIPtr = CreateStackTemporary(DestVT);
4106 // Emit a store to the stack slot.
4107 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4108 // Result is a load from the stack slot.
4109 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4112 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4113 // Create a vector sized/aligned stack slot, store the value to element #0,
4114 // then load the whole vector back out.
4115 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
4116 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4118 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4122 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4123 /// support the operation, but do support the resultant vector type.
4124 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4126 // If the only non-undef value is the low element, turn this into a
4127 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4128 unsigned NumElems = Node->getNumOperands();
4129 bool isOnlyLowElement = true;
4130 SDOperand SplatValue = Node->getOperand(0);
4131 std::map<SDOperand, std::vector<unsigned> > Values;
4132 Values[SplatValue].push_back(0);
4133 bool isConstant = true;
4134 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4135 SplatValue.getOpcode() != ISD::UNDEF)
4138 for (unsigned i = 1; i < NumElems; ++i) {
4139 SDOperand V = Node->getOperand(i);
4140 Values[V].push_back(i);
4141 if (V.getOpcode() != ISD::UNDEF)
4142 isOnlyLowElement = false;
4143 if (SplatValue != V)
4144 SplatValue = SDOperand(0,0);
4146 // If this isn't a constant element or an undef, we can't use a constant
4148 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4149 V.getOpcode() != ISD::UNDEF)
4153 if (isOnlyLowElement) {
4154 // If the low element is an undef too, then this whole things is an undef.
4155 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4156 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4157 // Otherwise, turn this into a scalar_to_vector node.
4158 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4159 Node->getOperand(0));
4162 // If all elements are constants, create a load from the constant pool.
4164 MVT::ValueType VT = Node->getValueType(0);
4166 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4167 std::vector<Constant*> CV;
4168 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4169 if (ConstantFPSDNode *V =
4170 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4171 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
4172 } else if (ConstantSDNode *V =
4173 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4174 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4176 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4177 CV.push_back(UndefValue::get(OpNTy));
4180 Constant *CP = ConstantVector::get(CV);
4181 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4182 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4185 if (SplatValue.Val) { // Splat of one value?
4186 // Build the shuffle constant vector: <0, 0, 0, 0>
4187 MVT::ValueType MaskVT =
4188 MVT::getIntVectorWithNumElements(NumElems);
4189 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4190 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4191 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4192 &ZeroVec[0], ZeroVec.size());
4194 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4195 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4196 // Get the splatted value into the low element of a vector register.
4197 SDOperand LowValVec =
4198 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4200 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4201 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4202 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4207 // If there are only two unique elements, we may be able to turn this into a
4209 if (Values.size() == 2) {
4210 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4211 MVT::ValueType MaskVT =
4212 MVT::getIntVectorWithNumElements(NumElems);
4213 std::vector<SDOperand> MaskVec(NumElems);
4215 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4216 E = Values.end(); I != E; ++I) {
4217 for (std::vector<unsigned>::iterator II = I->second.begin(),
4218 EE = I->second.end(); II != EE; ++II)
4219 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4222 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4223 &MaskVec[0], MaskVec.size());
4225 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4226 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4227 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4228 SmallVector<SDOperand, 8> Ops;
4229 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4230 E = Values.end(); I != E; ++I) {
4231 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4235 Ops.push_back(ShuffleMask);
4237 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4238 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4239 &Ops[0], Ops.size());
4243 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4244 // aligned object on the stack, store each element into it, then load
4245 // the result as a vector.
4246 MVT::ValueType VT = Node->getValueType(0);
4247 // Create the stack frame object.
4248 SDOperand FIPtr = CreateStackTemporary(VT);
4250 // Emit a store of each element to the stack slot.
4251 SmallVector<SDOperand, 8> Stores;
4252 unsigned TypeByteSize =
4253 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4254 // Store (in the right endianness) the elements to memory.
4255 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4256 // Ignore undef elements.
4257 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4259 unsigned Offset = TypeByteSize*i;
4261 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4262 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4264 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4268 SDOperand StoreChain;
4269 if (!Stores.empty()) // Not all undef elements?
4270 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4271 &Stores[0], Stores.size());
4273 StoreChain = DAG.getEntryNode();
4275 // Result is a load from the stack slot.
4276 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4279 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4280 /// specified value type.
4281 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4282 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4283 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4284 const Type *Ty = MVT::getTypeForValueType(VT);
4285 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4286 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4287 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4290 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4291 SDOperand Op, SDOperand Amt,
4292 SDOperand &Lo, SDOperand &Hi) {
4293 // Expand the subcomponents.
4294 SDOperand LHSL, LHSH;
4295 ExpandOp(Op, LHSL, LHSH);
4297 SDOperand Ops[] = { LHSL, LHSH, Amt };
4298 MVT::ValueType VT = LHSL.getValueType();
4299 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4300 Hi = Lo.getValue(1);
4304 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4305 /// smaller elements. If we can't find a way that is more efficient than a
4306 /// libcall on this target, return false. Otherwise, return true with the
4307 /// low-parts expanded into Lo and Hi.
4308 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4309 SDOperand &Lo, SDOperand &Hi) {
4310 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4311 "This is not a shift!");
4313 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4314 SDOperand ShAmt = LegalizeOp(Amt);
4315 MVT::ValueType ShTy = ShAmt.getValueType();
4316 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4317 unsigned NVTBits = MVT::getSizeInBits(NVT);
4319 // Handle the case when Amt is an immediate. Other cases are currently broken
4320 // and are disabled.
4321 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4322 unsigned Cst = CN->getValue();
4323 // Expand the incoming operand to be shifted, so that we have its parts
4325 ExpandOp(Op, InL, InH);
4329 Lo = DAG.getConstant(0, NVT);
4330 Hi = DAG.getConstant(0, NVT);
4331 } else if (Cst > NVTBits) {
4332 Lo = DAG.getConstant(0, NVT);
4333 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4334 } else if (Cst == NVTBits) {
4335 Lo = DAG.getConstant(0, NVT);
4338 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4339 Hi = DAG.getNode(ISD::OR, NVT,
4340 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4341 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4346 Lo = DAG.getConstant(0, NVT);
4347 Hi = DAG.getConstant(0, NVT);
4348 } else if (Cst > NVTBits) {
4349 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4350 Hi = DAG.getConstant(0, NVT);
4351 } else if (Cst == NVTBits) {
4353 Hi = DAG.getConstant(0, NVT);
4355 Lo = DAG.getNode(ISD::OR, NVT,
4356 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4357 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4358 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4363 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4364 DAG.getConstant(NVTBits-1, ShTy));
4365 } else if (Cst > NVTBits) {
4366 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4367 DAG.getConstant(Cst-NVTBits, ShTy));
4368 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4369 DAG.getConstant(NVTBits-1, ShTy));
4370 } else if (Cst == NVTBits) {
4372 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4373 DAG.getConstant(NVTBits-1, ShTy));
4375 Lo = DAG.getNode(ISD::OR, NVT,
4376 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4377 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4378 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4384 // Okay, the shift amount isn't constant. However, if we can tell that it is
4385 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4386 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4387 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4389 // If we know that the high bit of the shift amount is one, then we can do
4390 // this as a couple of simple shifts.
4391 if (KnownOne & Mask) {
4392 // Mask out the high bit, which we know is set.
4393 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4394 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4396 // Expand the incoming operand to be shifted, so that we have its parts
4398 ExpandOp(Op, InL, InH);
4401 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4402 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4405 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4406 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4409 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4410 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4411 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4416 // If we know that the high bit of the shift amount is zero, then we can do
4417 // this as a couple of simple shifts.
4418 if (KnownZero & Mask) {
4420 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4421 DAG.getConstant(NVTBits, Amt.getValueType()),
4424 // Expand the incoming operand to be shifted, so that we have its parts
4426 ExpandOp(Op, InL, InH);
4429 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4430 Hi = DAG.getNode(ISD::OR, NVT,
4431 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4432 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4435 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4436 Lo = DAG.getNode(ISD::OR, NVT,
4437 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4438 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4441 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4442 Lo = DAG.getNode(ISD::OR, NVT,
4443 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4444 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4453 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4454 // does not fit into a register, return the lo part and set the hi part to the
4455 // by-reg argument. If it does fit into a single register, return the result
4456 // and leave the Hi part unset.
4457 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4458 bool isSigned, SDOperand &Hi) {
4459 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4460 // The input chain to this libcall is the entry node of the function.
4461 // Legalizing the call will automatically add the previous call to the
4463 SDOperand InChain = DAG.getEntryNode();
4465 TargetLowering::ArgListTy Args;
4466 TargetLowering::ArgListEntry Entry;
4467 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4468 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4469 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4470 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4471 Entry.isSExt = isSigned;
4472 Args.push_back(Entry);
4474 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4476 // Splice the libcall in wherever FindInputOutputChains tells us to.
4477 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4478 std::pair<SDOperand,SDOperand> CallInfo =
4479 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4482 // Legalize the call sequence, starting with the chain. This will advance
4483 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4484 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4485 LegalizeOp(CallInfo.second);
4487 switch (getTypeAction(CallInfo.first.getValueType())) {
4488 default: assert(0 && "Unknown thing");
4490 Result = CallInfo.first;
4493 ExpandOp(CallInfo.first, Result, Hi);
4500 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4502 SDOperand SelectionDAGLegalize::
4503 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4504 assert(getTypeAction(Source.getValueType()) == Expand &&
4505 "This is not an expansion!");
4506 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4509 assert(Source.getValueType() == MVT::i64 &&
4510 "This only works for 64-bit -> FP");
4511 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4512 // incoming integer is set. To handle this, we dynamically test to see if
4513 // it is set, and, if so, add a fudge factor.
4515 ExpandOp(Source, Lo, Hi);
4517 // If this is unsigned, and not supported, first perform the conversion to
4518 // signed, then adjust the result if the sign bit is set.
4519 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4520 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4522 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4523 DAG.getConstant(0, Hi.getValueType()),
4525 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4526 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4527 SignSet, Four, Zero);
4528 uint64_t FF = 0x5f800000ULL;
4529 if (TLI.isLittleEndian()) FF <<= 32;
4530 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4532 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4533 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4534 SDOperand FudgeInReg;
4535 if (DestTy == MVT::f32)
4536 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4538 assert(DestTy == MVT::f64 && "Unexpected conversion");
4539 // FIXME: Avoid the extend by construction the right constantpool?
4540 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4541 CPIdx, NULL, 0, MVT::f32);
4543 MVT::ValueType SCVT = SignedConv.getValueType();
4544 if (SCVT != DestTy) {
4545 // Destination type needs to be expanded as well. The FADD now we are
4546 // constructing will be expanded into a libcall.
4547 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4548 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4549 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4550 SignedConv, SignedConv.getValue(1));
4552 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4554 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4557 // Check to see if the target has a custom way to lower this. If so, use it.
4558 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4559 default: assert(0 && "This action not implemented for this operation!");
4560 case TargetLowering::Legal:
4561 case TargetLowering::Expand:
4562 break; // This case is handled below.
4563 case TargetLowering::Custom: {
4564 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4567 return LegalizeOp(NV);
4568 break; // The target decided this was legal after all
4572 // Expand the source, then glue it back together for the call. We must expand
4573 // the source in case it is shared (this pass of legalize must traverse it).
4574 SDOperand SrcLo, SrcHi;
4575 ExpandOp(Source, SrcLo, SrcHi);
4576 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4579 if (DestTy == MVT::f32)
4580 LC = RTLIB::SINTTOFP_I64_F32;
4582 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4583 LC = RTLIB::SINTTOFP_I64_F64;
4586 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4587 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4588 SDOperand UnusedHiPart;
4589 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4593 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4594 /// INT_TO_FP operation of the specified operand when the target requests that
4595 /// we expand it. At this point, we know that the result and operand types are
4596 /// legal for the target.
4597 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4599 MVT::ValueType DestVT) {
4600 if (Op0.getValueType() == MVT::i32) {
4601 // simple 32-bit [signed|unsigned] integer to float/double expansion
4603 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4604 MachineFunction &MF = DAG.getMachineFunction();
4605 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4606 unsigned StackAlign =
4607 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4608 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4609 // get address of 8 byte buffer
4610 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4611 // word offset constant for Hi/Lo address computation
4612 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4613 // set up Hi and Lo (into buffer) address based on endian
4614 SDOperand Hi = StackSlot;
4615 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4616 if (TLI.isLittleEndian())
4619 // if signed map to unsigned space
4620 SDOperand Op0Mapped;
4622 // constant used to invert sign bit (signed to unsigned mapping)
4623 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4624 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4628 // store the lo of the constructed double - based on integer input
4629 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4630 Op0Mapped, Lo, NULL, 0);
4631 // initial hi portion of constructed double
4632 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4633 // store the hi of the constructed double - biased exponent
4634 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4635 // load the constructed double
4636 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4637 // FP constant to bias correct the final result
4638 SDOperand Bias = DAG.getConstantFP(isSigned ?
4639 BitsToDouble(0x4330000080000000ULL)
4640 : BitsToDouble(0x4330000000000000ULL),
4642 // subtract the bias
4643 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4646 // handle final rounding
4647 if (DestVT == MVT::f64) {
4651 // if f32 then cast to f32
4652 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4656 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4657 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4659 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4660 DAG.getConstant(0, Op0.getValueType()),
4662 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4663 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4664 SignSet, Four, Zero);
4666 // If the sign bit of the integer is set, the large number will be treated
4667 // as a negative number. To counteract this, the dynamic code adds an
4668 // offset depending on the data type.
4670 switch (Op0.getValueType()) {
4671 default: assert(0 && "Unsupported integer type!");
4672 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4673 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4674 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4675 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4677 if (TLI.isLittleEndian()) FF <<= 32;
4678 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4680 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4681 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4682 SDOperand FudgeInReg;
4683 if (DestVT == MVT::f32)
4684 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4686 assert(DestVT == MVT::f64 && "Unexpected conversion");
4687 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4688 DAG.getEntryNode(), CPIdx,
4689 NULL, 0, MVT::f32));
4692 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4695 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4696 /// *INT_TO_FP operation of the specified operand when the target requests that
4697 /// we promote it. At this point, we know that the result and operand types are
4698 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4699 /// operation that takes a larger input.
4700 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4701 MVT::ValueType DestVT,
4703 // First step, figure out the appropriate *INT_TO_FP operation to use.
4704 MVT::ValueType NewInTy = LegalOp.getValueType();
4706 unsigned OpToUse = 0;
4708 // Scan for the appropriate larger type to use.
4710 NewInTy = (MVT::ValueType)(NewInTy+1);
4711 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4713 // If the target supports SINT_TO_FP of this type, use it.
4714 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4716 case TargetLowering::Legal:
4717 if (!TLI.isTypeLegal(NewInTy))
4718 break; // Can't use this datatype.
4720 case TargetLowering::Custom:
4721 OpToUse = ISD::SINT_TO_FP;
4725 if (isSigned) continue;
4727 // If the target supports UINT_TO_FP of this type, use it.
4728 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4730 case TargetLowering::Legal:
4731 if (!TLI.isTypeLegal(NewInTy))
4732 break; // Can't use this datatype.
4734 case TargetLowering::Custom:
4735 OpToUse = ISD::UINT_TO_FP;
4740 // Otherwise, try a larger type.
4743 // Okay, we found the operation and type to use. Zero extend our input to the
4744 // desired type then run the operation on it.
4745 return DAG.getNode(OpToUse, DestVT,
4746 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4750 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4751 /// FP_TO_*INT operation of the specified operand when the target requests that
4752 /// we promote it. At this point, we know that the result and operand types are
4753 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4754 /// operation that returns a larger result.
4755 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4756 MVT::ValueType DestVT,
4758 // First step, figure out the appropriate FP_TO*INT operation to use.
4759 MVT::ValueType NewOutTy = DestVT;
4761 unsigned OpToUse = 0;
4763 // Scan for the appropriate larger type to use.
4765 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4766 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4768 // If the target supports FP_TO_SINT returning this type, use it.
4769 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4771 case TargetLowering::Legal:
4772 if (!TLI.isTypeLegal(NewOutTy))
4773 break; // Can't use this datatype.
4775 case TargetLowering::Custom:
4776 OpToUse = ISD::FP_TO_SINT;
4781 // If the target supports FP_TO_UINT of this type, use it.
4782 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4784 case TargetLowering::Legal:
4785 if (!TLI.isTypeLegal(NewOutTy))
4786 break; // Can't use this datatype.
4788 case TargetLowering::Custom:
4789 OpToUse = ISD::FP_TO_UINT;
4794 // Otherwise, try a larger type.
4797 // Okay, we found the operation and type to use. Truncate the result of the
4798 // extended FP_TO_*INT operation to the desired size.
4799 return DAG.getNode(ISD::TRUNCATE, DestVT,
4800 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4803 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4805 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4806 MVT::ValueType VT = Op.getValueType();
4807 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4808 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4810 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4812 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4813 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4814 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4816 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4817 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4818 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4819 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4820 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4821 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4822 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4823 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4824 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4826 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4827 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4828 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4829 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4830 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4831 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4832 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4833 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4834 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4835 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4836 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4837 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4838 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4839 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4840 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4841 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4842 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4843 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4844 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4845 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4846 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4850 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4852 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4854 default: assert(0 && "Cannot expand this yet!");
4856 static const uint64_t mask[6] = {
4857 0x5555555555555555ULL, 0x3333333333333333ULL,
4858 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4859 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4861 MVT::ValueType VT = Op.getValueType();
4862 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4863 unsigned len = MVT::getSizeInBits(VT);
4864 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4865 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4866 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4867 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4868 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4869 DAG.getNode(ISD::AND, VT,
4870 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4875 // for now, we do this:
4876 // x = x | (x >> 1);
4877 // x = x | (x >> 2);
4879 // x = x | (x >>16);
4880 // x = x | (x >>32); // for 64-bit input
4881 // return popcount(~x);
4883 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4884 MVT::ValueType VT = Op.getValueType();
4885 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4886 unsigned len = MVT::getSizeInBits(VT);
4887 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4888 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4889 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4891 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4892 return DAG.getNode(ISD::CTPOP, VT, Op);
4895 // for now, we use: { return popcount(~x & (x - 1)); }
4896 // unless the target has ctlz but not ctpop, in which case we use:
4897 // { return 32 - nlz(~x & (x-1)); }
4898 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4899 MVT::ValueType VT = Op.getValueType();
4900 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4901 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4902 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4903 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4904 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4905 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4906 TLI.isOperationLegal(ISD::CTLZ, VT))
4907 return DAG.getNode(ISD::SUB, VT,
4908 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4909 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4910 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4915 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4916 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4917 /// LegalizeNodes map is filled in for any results that are not expanded, the
4918 /// ExpandedNodes map is filled in for any results that are expanded, and the
4919 /// Lo/Hi values are returned.
4920 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4921 MVT::ValueType VT = Op.getValueType();
4922 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4923 SDNode *Node = Op.Val;
4924 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4925 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4926 MVT::isVector(VT)) &&
4927 "Cannot expand to FP value or to larger int value!");
4929 // See if we already expanded it.
4930 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4931 = ExpandedNodes.find(Op);
4932 if (I != ExpandedNodes.end()) {
4933 Lo = I->second.first;
4934 Hi = I->second.second;
4938 switch (Node->getOpcode()) {
4939 case ISD::CopyFromReg:
4940 assert(0 && "CopyFromReg must be legal!");
4943 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4945 assert(0 && "Do not know how to expand this operator!");
4948 NVT = TLI.getTypeToExpandTo(VT);
4949 Lo = DAG.getNode(ISD::UNDEF, NVT);
4950 Hi = DAG.getNode(ISD::UNDEF, NVT);
4952 case ISD::Constant: {
4953 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4954 Lo = DAG.getConstant(Cst, NVT);
4955 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4958 case ISD::ConstantFP: {
4959 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4960 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4961 if (getTypeAction(Lo.getValueType()) == Expand)
4962 ExpandOp(Lo, Lo, Hi);
4965 case ISD::BUILD_PAIR:
4966 // Return the operands.
4967 Lo = Node->getOperand(0);
4968 Hi = Node->getOperand(1);
4971 case ISD::SIGN_EXTEND_INREG:
4972 ExpandOp(Node->getOperand(0), Lo, Hi);
4973 // sext_inreg the low part if needed.
4974 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4976 // The high part gets the sign extension from the lo-part. This handles
4977 // things like sextinreg V:i64 from i8.
4978 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4979 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4980 TLI.getShiftAmountTy()));
4984 ExpandOp(Node->getOperand(0), Lo, Hi);
4985 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4986 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4992 ExpandOp(Node->getOperand(0), Lo, Hi);
4993 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4994 DAG.getNode(ISD::CTPOP, NVT, Lo),
4995 DAG.getNode(ISD::CTPOP, NVT, Hi));
4996 Hi = DAG.getConstant(0, NVT);
5000 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5001 ExpandOp(Node->getOperand(0), Lo, Hi);
5002 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5003 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5004 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5006 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5007 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5009 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5010 Hi = DAG.getConstant(0, NVT);
5015 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5016 ExpandOp(Node->getOperand(0), Lo, Hi);
5017 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5018 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5019 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5021 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5022 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5024 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5025 Hi = DAG.getConstant(0, NVT);
5030 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5031 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5032 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5033 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5035 // Remember that we legalized the chain.
5036 Hi = LegalizeOp(Hi);
5037 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5038 if (!TLI.isLittleEndian())
5044 LoadSDNode *LD = cast<LoadSDNode>(Node);
5045 SDOperand Ch = LD->getChain(); // Legalize the chain.
5046 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5047 ISD::LoadExtType ExtType = LD->getExtensionType();
5048 int SVOffset = LD->getSrcValueOffset();
5049 unsigned Alignment = LD->getAlignment();
5050 bool isVolatile = LD->isVolatile();
5052 if (ExtType == ISD::NON_EXTLOAD) {
5053 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5054 isVolatile, Alignment);
5055 if (VT == MVT::f32 || VT == MVT::f64) {
5056 // f32->i32 or f64->i64 one to one expansion.
5057 // Remember that we legalized the chain.
5058 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5059 // Recursively expand the new load.
5060 if (getTypeAction(NVT) == Expand)
5061 ExpandOp(Lo, Lo, Hi);
5065 // Increment the pointer to the other half.
5066 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5067 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5068 getIntPtrConstant(IncrementSize));
5069 SVOffset += IncrementSize;
5070 if (Alignment > IncrementSize)
5071 Alignment = IncrementSize;
5072 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5073 isVolatile, Alignment);
5075 // Build a factor node to remember that this load is independent of the
5077 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5080 // Remember that we legalized the chain.
5081 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5082 if (!TLI.isLittleEndian())
5085 MVT::ValueType EVT = LD->getLoadedVT();
5087 if (VT == MVT::f64 && EVT == MVT::f32) {
5088 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5089 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5090 SVOffset, isVolatile, Alignment);
5091 // Remember that we legalized the chain.
5092 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5093 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5098 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5099 SVOffset, isVolatile, Alignment);
5101 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5102 SVOffset, EVT, isVolatile,
5105 // Remember that we legalized the chain.
5106 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5108 if (ExtType == ISD::SEXTLOAD) {
5109 // The high part is obtained by SRA'ing all but one of the bits of the
5111 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5112 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5113 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5114 } else if (ExtType == ISD::ZEXTLOAD) {
5115 // The high part is just a zero.
5116 Hi = DAG.getConstant(0, NVT);
5117 } else /* if (ExtType == ISD::EXTLOAD) */ {
5118 // The high part is undefined.
5119 Hi = DAG.getNode(ISD::UNDEF, NVT);
5126 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5127 SDOperand LL, LH, RL, RH;
5128 ExpandOp(Node->getOperand(0), LL, LH);
5129 ExpandOp(Node->getOperand(1), RL, RH);
5130 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5131 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5135 SDOperand LL, LH, RL, RH;
5136 ExpandOp(Node->getOperand(1), LL, LH);
5137 ExpandOp(Node->getOperand(2), RL, RH);
5138 if (getTypeAction(NVT) == Expand)
5139 NVT = TLI.getTypeToExpandTo(NVT);
5140 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5142 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5145 case ISD::SELECT_CC: {
5146 SDOperand TL, TH, FL, FH;
5147 ExpandOp(Node->getOperand(2), TL, TH);
5148 ExpandOp(Node->getOperand(3), FL, FH);
5149 if (getTypeAction(NVT) == Expand)
5150 NVT = TLI.getTypeToExpandTo(NVT);
5151 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5152 Node->getOperand(1), TL, FL, Node->getOperand(4));
5154 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5155 Node->getOperand(1), TH, FH, Node->getOperand(4));
5158 case ISD::ANY_EXTEND:
5159 // The low part is any extension of the input (which degenerates to a copy).
5160 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5161 // The high part is undefined.
5162 Hi = DAG.getNode(ISD::UNDEF, NVT);
5164 case ISD::SIGN_EXTEND: {
5165 // The low part is just a sign extension of the input (which degenerates to
5167 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5169 // The high part is obtained by SRA'ing all but one of the bits of the lo
5171 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5172 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5173 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5176 case ISD::ZERO_EXTEND:
5177 // The low part is just a zero extension of the input (which degenerates to
5179 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5181 // The high part is just a zero.
5182 Hi = DAG.getConstant(0, NVT);
5185 case ISD::TRUNCATE: {
5186 // The input value must be larger than this value. Expand *it*.
5188 ExpandOp(Node->getOperand(0), NewLo, Hi);
5190 // The low part is now either the right size, or it is closer. If not the
5191 // right size, make an illegal truncate so we recursively expand it.
5192 if (NewLo.getValueType() != Node->getValueType(0))
5193 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5194 ExpandOp(NewLo, Lo, Hi);
5198 case ISD::BIT_CONVERT: {
5200 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5201 // If the target wants to, allow it to lower this itself.
5202 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5203 case Expand: assert(0 && "cannot expand FP!");
5204 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5205 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5207 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5210 // f32 / f64 must be expanded to i32 / i64.
5211 if (VT == MVT::f32 || VT == MVT::f64) {
5212 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5213 if (getTypeAction(NVT) == Expand)
5214 ExpandOp(Lo, Lo, Hi);
5218 // If source operand will be expanded to the same type as VT, i.e.
5219 // i64 <- f64, i32 <- f32, expand the source operand instead.
5220 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5221 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5222 ExpandOp(Node->getOperand(0), Lo, Hi);
5226 // Turn this into a load/store pair by default.
5228 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5230 ExpandOp(Tmp, Lo, Hi);
5234 case ISD::READCYCLECOUNTER:
5235 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5236 TargetLowering::Custom &&
5237 "Must custom expand ReadCycleCounter");
5238 Lo = TLI.LowerOperation(Op, DAG);
5239 assert(Lo.Val && "Node must be custom expanded!");
5240 Hi = Lo.getValue(1);
5241 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5242 LegalizeOp(Lo.getValue(2)));
5245 // These operators cannot be expanded directly, emit them as calls to
5246 // library functions.
5247 case ISD::FP_TO_SINT: {
5248 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5250 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5251 case Expand: assert(0 && "cannot expand FP!");
5252 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5253 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5256 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5258 // Now that the custom expander is done, expand the result, which is still
5261 ExpandOp(Op, Lo, Hi);
5267 if (Node->getOperand(0).getValueType() == MVT::f32)
5268 LC = RTLIB::FPTOSINT_F32_I64;
5270 LC = RTLIB::FPTOSINT_F64_I64;
5271 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5272 false/*sign irrelevant*/, Hi);
5276 case ISD::FP_TO_UINT: {
5277 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5279 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5280 case Expand: assert(0 && "cannot expand FP!");
5281 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5282 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5285 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5287 // Now that the custom expander is done, expand the result.
5289 ExpandOp(Op, Lo, Hi);
5295 if (Node->getOperand(0).getValueType() == MVT::f32)
5296 LC = RTLIB::FPTOUINT_F32_I64;
5298 LC = RTLIB::FPTOUINT_F64_I64;
5299 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5300 false/*sign irrelevant*/, Hi);
5305 // If the target wants custom lowering, do so.
5306 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5307 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5308 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5309 Op = TLI.LowerOperation(Op, DAG);
5311 // Now that the custom expander is done, expand the result, which is
5313 ExpandOp(Op, Lo, Hi);
5318 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5319 // this X << 1 as X+X.
5320 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5321 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5322 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5323 SDOperand LoOps[2], HiOps[3];
5324 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5325 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5326 LoOps[1] = LoOps[0];
5327 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5329 HiOps[1] = HiOps[0];
5330 HiOps[2] = Lo.getValue(1);
5331 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5336 // If we can emit an efficient shift operation, do so now.
5337 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5340 // If this target supports SHL_PARTS, use it.
5341 TargetLowering::LegalizeAction Action =
5342 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5343 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5344 Action == TargetLowering::Custom) {
5345 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5349 // Otherwise, emit a libcall.
5350 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5351 false/*left shift=unsigned*/, Hi);
5356 // If the target wants custom lowering, do so.
5357 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5358 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5359 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5360 Op = TLI.LowerOperation(Op, DAG);
5362 // Now that the custom expander is done, expand the result, which is
5364 ExpandOp(Op, Lo, Hi);
5369 // If we can emit an efficient shift operation, do so now.
5370 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5373 // If this target supports SRA_PARTS, use it.
5374 TargetLowering::LegalizeAction Action =
5375 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5376 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5377 Action == TargetLowering::Custom) {
5378 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5382 // Otherwise, emit a libcall.
5383 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5384 true/*ashr is signed*/, Hi);
5389 // If the target wants custom lowering, do so.
5390 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5391 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5392 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5393 Op = TLI.LowerOperation(Op, DAG);
5395 // Now that the custom expander is done, expand the result, which is
5397 ExpandOp(Op, Lo, Hi);
5402 // If we can emit an efficient shift operation, do so now.
5403 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5406 // If this target supports SRL_PARTS, use it.
5407 TargetLowering::LegalizeAction Action =
5408 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5409 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5410 Action == TargetLowering::Custom) {
5411 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5415 // Otherwise, emit a libcall.
5416 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5417 false/*lshr is unsigned*/, Hi);
5423 // If the target wants to custom expand this, let them.
5424 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5425 TargetLowering::Custom) {
5426 Op = TLI.LowerOperation(Op, DAG);
5428 ExpandOp(Op, Lo, Hi);
5433 // Expand the subcomponents.
5434 SDOperand LHSL, LHSH, RHSL, RHSH;
5435 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5436 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5437 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5438 SDOperand LoOps[2], HiOps[3];
5443 if (Node->getOpcode() == ISD::ADD) {
5444 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5445 HiOps[2] = Lo.getValue(1);
5446 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5448 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5449 HiOps[2] = Lo.getValue(1);
5450 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5457 // Expand the subcomponents.
5458 SDOperand LHSL, LHSH, RHSL, RHSH;
5459 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5460 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5461 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5462 SDOperand LoOps[2] = { LHSL, RHSL };
5463 SDOperand HiOps[3] = { LHSH, RHSH };
5465 if (Node->getOpcode() == ISD::ADDC) {
5466 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5467 HiOps[2] = Lo.getValue(1);
5468 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5470 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5471 HiOps[2] = Lo.getValue(1);
5472 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5474 // Remember that we legalized the flag.
5475 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5480 // Expand the subcomponents.
5481 SDOperand LHSL, LHSH, RHSL, RHSH;
5482 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5483 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5484 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5485 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5486 SDOperand HiOps[3] = { LHSH, RHSH };
5488 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5489 HiOps[2] = Lo.getValue(1);
5490 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5492 // Remember that we legalized the flag.
5493 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5497 // If the target wants to custom expand this, let them.
5498 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5499 SDOperand New = TLI.LowerOperation(Op, DAG);
5501 ExpandOp(New, Lo, Hi);
5506 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5507 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5508 if (HasMULHS || HasMULHU) {
5509 SDOperand LL, LH, RL, RH;
5510 ExpandOp(Node->getOperand(0), LL, LH);
5511 ExpandOp(Node->getOperand(1), RL, RH);
5512 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5513 // FIXME: Move this to the dag combiner.
5514 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5515 // extended the sign bit of the low half through the upper half, and if so
5516 // emit a MULHS instead of the alternate sequence that is valid for any
5517 // i64 x i64 multiply.
5519 // is RH an extension of the sign bit of RL?
5520 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5521 RH.getOperand(1).getOpcode() == ISD::Constant &&
5522 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5523 // is LH an extension of the sign bit of LL?
5524 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5525 LH.getOperand(1).getOpcode() == ISD::Constant &&
5526 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5528 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5530 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5532 } else if (HasMULHU) {
5534 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5537 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5538 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5539 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5540 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5541 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5546 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5547 false/*sign irrelevant*/, Hi);
5551 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5554 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5557 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5560 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5564 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5565 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5569 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5570 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5574 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5575 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5579 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5580 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5583 case ISD::FP_EXTEND:
5584 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5587 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5592 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5593 switch(Node->getOpcode()) {
5595 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5598 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5601 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5603 default: assert(0 && "Unreachable!");
5605 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5609 SDOperand Mask = (VT == MVT::f64)
5610 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5611 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5612 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5613 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5614 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5615 if (getTypeAction(NVT) == Expand)
5616 ExpandOp(Lo, Lo, Hi);
5620 SDOperand Mask = (VT == MVT::f64)
5621 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5622 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5623 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5624 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5625 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5626 if (getTypeAction(NVT) == Expand)
5627 ExpandOp(Lo, Lo, Hi);
5630 case ISD::FCOPYSIGN: {
5631 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5632 if (getTypeAction(NVT) == Expand)
5633 ExpandOp(Lo, Lo, Hi);
5636 case ISD::SINT_TO_FP:
5637 case ISD::UINT_TO_FP: {
5638 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5639 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5641 if (Node->getOperand(0).getValueType() == MVT::i64) {
5643 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5645 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5648 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5650 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5653 // Promote the operand if needed.
5654 if (getTypeAction(SrcVT) == Promote) {
5655 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5657 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5658 DAG.getValueType(SrcVT))
5659 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5660 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5663 const char *LibCall = TLI.getLibcallName(LC);
5665 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5667 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5668 Node->getOperand(0));
5669 if (getTypeAction(Lo.getValueType()) == Expand)
5670 ExpandOp(Lo, Lo, Hi);
5676 // Make sure the resultant values have been legalized themselves, unless this
5677 // is a type that requires multi-step expansion.
5678 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5679 Lo = LegalizeOp(Lo);
5681 // Don't legalize the high part if it is expanded to a single node.
5682 Hi = LegalizeOp(Hi);
5685 // Remember in a map if the values will be reused later.
5686 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5687 assert(isNew && "Value already expanded?!?");
5690 /// SplitVectorOp - Given an operand of vector type, break it down into
5691 /// two smaller values, still of vector type.
5692 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5694 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5695 SDNode *Node = Op.Val;
5696 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5697 assert(NumElements > 1 && "Cannot split a single element vector!");
5698 unsigned NewNumElts = NumElements/2;
5699 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5700 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5702 // See if we already split it.
5703 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5704 = SplitNodes.find(Op);
5705 if (I != SplitNodes.end()) {
5706 Lo = I->second.first;
5707 Hi = I->second.second;
5711 switch (Node->getOpcode()) {
5716 assert(0 && "Unhandled operation in SplitVectorOp!");
5717 case ISD::BUILD_PAIR:
5718 Lo = Node->getOperand(0);
5719 Hi = Node->getOperand(1);
5721 case ISD::BUILD_VECTOR: {
5722 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5723 Node->op_begin()+NewNumElts);
5724 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5726 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5728 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5731 case ISD::CONCAT_VECTORS: {
5732 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5733 if (NewNumSubvectors == 1) {
5734 Lo = Node->getOperand(0);
5735 Hi = Node->getOperand(1);
5737 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5738 Node->op_begin()+NewNumSubvectors);
5739 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5741 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5743 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5759 SDOperand LL, LH, RL, RH;
5760 SplitVectorOp(Node->getOperand(0), LL, LH);
5761 SplitVectorOp(Node->getOperand(1), RL, RH);
5763 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5764 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5768 LoadSDNode *LD = cast<LoadSDNode>(Node);
5769 SDOperand Ch = LD->getChain();
5770 SDOperand Ptr = LD->getBasePtr();
5771 const Value *SV = LD->getSrcValue();
5772 int SVOffset = LD->getSrcValueOffset();
5773 unsigned Alignment = LD->getAlignment();
5774 bool isVolatile = LD->isVolatile();
5776 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5777 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5778 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5779 getIntPtrConstant(IncrementSize));
5780 SVOffset += IncrementSize;
5781 if (Alignment > IncrementSize)
5782 Alignment = IncrementSize;
5783 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5785 // Build a factor node to remember that this load is independent of the
5787 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5790 // Remember that we legalized the chain.
5791 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5794 case ISD::BIT_CONVERT: {
5795 // We know the result is a vector. The input may be either a vector or a
5797 SDOperand InOp = Node->getOperand(0);
5798 if (!MVT::isVector(InOp.getValueType()) ||
5799 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5800 // The input is a scalar or single-element vector.
5801 // Lower to a store/load so that it can be split.
5802 // FIXME: this could be improved probably.
5803 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5805 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5806 InOp, Ptr, NULL, 0);
5807 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5809 // Split the vector and convert each of the pieces now.
5810 SplitVectorOp(InOp, Lo, Hi);
5811 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5812 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5817 // Remember in a map if the values will be reused later.
5819 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5820 assert(isNew && "Value already split?!?");
5824 /// ScalarizeVectorOp - Given an operand of single-element vector type
5825 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5826 /// scalar (e.g. f32) value.
5827 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5828 assert(MVT::isVector(Op.getValueType()) &&
5829 "Bad ScalarizeVectorOp invocation!");
5830 SDNode *Node = Op.Val;
5831 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5832 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5834 // See if we already scalarized it.
5835 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5836 if (I != ScalarizedNodes.end()) return I->second;
5839 switch (Node->getOpcode()) {
5842 Node->dump(&DAG); cerr << "\n";
5844 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5860 Result = DAG.getNode(Node->getOpcode(),
5862 ScalarizeVectorOp(Node->getOperand(0)),
5863 ScalarizeVectorOp(Node->getOperand(1)));
5870 Result = DAG.getNode(Node->getOpcode(),
5872 ScalarizeVectorOp(Node->getOperand(0)));
5875 LoadSDNode *LD = cast<LoadSDNode>(Node);
5876 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5877 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5879 const Value *SV = LD->getSrcValue();
5880 int SVOffset = LD->getSrcValueOffset();
5881 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5882 LD->isVolatile(), LD->getAlignment());
5884 // Remember that we legalized the chain.
5885 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5888 case ISD::BUILD_VECTOR:
5889 Result = Node->getOperand(0);
5891 case ISD::INSERT_VECTOR_ELT:
5892 // Returning the inserted scalar element.
5893 Result = Node->getOperand(1);
5895 case ISD::CONCAT_VECTORS:
5896 assert(Node->getOperand(0).getValueType() == NewVT &&
5897 "Concat of non-legal vectors not yet supported!");
5898 Result = Node->getOperand(0);
5900 case ISD::VECTOR_SHUFFLE: {
5901 // Figure out if the scalar is the LHS or RHS and return it.
5902 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5903 if (cast<ConstantSDNode>(EltNum)->getValue())
5904 Result = ScalarizeVectorOp(Node->getOperand(1));
5906 Result = ScalarizeVectorOp(Node->getOperand(0));
5909 case ISD::EXTRACT_SUBVECTOR:
5910 Result = Node->getOperand(0);
5911 assert(Result.getValueType() == NewVT);
5913 case ISD::BIT_CONVERT:
5914 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5917 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5918 ScalarizeVectorOp(Op.getOperand(1)),
5919 ScalarizeVectorOp(Op.getOperand(2)));
5923 if (TLI.isTypeLegal(NewVT))
5924 Result = LegalizeOp(Result);
5925 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
5926 assert(isNew && "Value already scalarized?");
5931 // SelectionDAG::Legalize - This is the entry point for the file.
5933 void SelectionDAG::Legalize() {
5934 if (ViewLegalizeDAGs) viewGraph();
5936 /// run - This is the main entry point to this class.
5938 SelectionDAGLegalize(*this).LegalizeDAG();