1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// PromoteOp - Given an operation that produces a value in an invalid type,
151 /// promote it to compute the value into a larger type. The produced value
152 /// will have the correct bits for the low portion of the register, but no
153 /// guarantee is made about the top bits: it may be zero, sign-extended, or
155 SDOperand PromoteOp(SDOperand O);
157 /// ExpandOp - Expand the specified SDOperand into its two component pieces
158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
159 /// the LegalizeNodes map is filled in for any results that are not expanded,
160 /// the ExpandedNodes map is filled in for any results that are expanded, and
161 /// the Lo/Hi values are returned. This applies to integer types and Vector
163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// SplitVectorOp - Given an operand of vector type, break it down into
166 /// two smaller values.
167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
169 /// ScalarizeVectorOp - Given an operand of single-element vector type
170 /// (e.g. v1f32), convert it into the equivalent operation that returns a
171 /// scalar (e.g. f32) value.
172 SDOperand ScalarizeVectorOp(SDOperand O);
174 /// isShuffleLegal - Return true if a vector shuffle is legal with the
175 /// specified mask and type. Targets can specify exactly which masks they
176 /// support and the code generator is tasked with not creating illegal masks.
178 /// Note that this will also return true for shuffles that are promoted to a
181 /// If this is a legal shuffle, this method returns the (possibly promoted)
182 /// build_vector Mask. If it's not a legal shuffle, it returns null.
183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
190 SDOperand CreateStackTemporary(MVT::ValueType VT);
192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
198 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
200 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
202 MVT::ValueType DestVT);
203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
208 SDOperand ExpandBSWAP(SDOperand Op);
209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
211 SDOperand &Lo, SDOperand &Hi);
212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
213 SDOperand &Lo, SDOperand &Hi);
215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
218 SDOperand getIntPtrConstant(uint64_t Val) {
219 return DAG.getConstant(Val, TLI.getPointerTy());
224 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
225 /// specified mask and type. Targets can specify exactly which masks they
226 /// support and the code generator is tasked with not creating illegal masks.
228 /// Note that this will also return true for shuffles that are promoted to a
230 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
231 SDOperand Mask) const {
232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
234 case TargetLowering::Legal:
235 case TargetLowering::Custom:
237 case TargetLowering::Promote: {
238 // If this is promoted to a different type, convert the shuffle mask and
239 // ask if it is legal in the promoted type!
240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
242 // If we changed # elements, change the shuffle mask.
243 unsigned NumEltsGrowth =
244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
246 if (NumEltsGrowth > 1) {
247 // Renumber the elements.
248 SmallVector<SDOperand, 8> Ops;
249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
250 SDOperand InOp = Mask.getOperand(i);
251 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
252 if (InOp.getOpcode() == ISD::UNDEF)
253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
269 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
270 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
271 ValueTypeActions(TLI.getValueTypeActions()) {
272 assert(MVT::LAST_VALUETYPE <= 32 &&
273 "Too many value types for ValueTypeActions to hold!");
276 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
277 /// contains all of a nodes operands before it contains the node.
278 static void ComputeTopDownOrdering(SelectionDAG &DAG,
279 SmallVector<SDNode*, 64> &Order) {
281 DenseMap<SDNode*, unsigned> Visited;
282 std::vector<SDNode*> Worklist;
283 Worklist.reserve(128);
285 // Compute ordering from all of the leaves in the graphs, those (like the
286 // entry node) that have no operands.
287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
288 E = DAG.allnodes_end(); I != E; ++I) {
289 if (I->getNumOperands() == 0) {
291 Worklist.push_back(I);
295 while (!Worklist.empty()) {
296 SDNode *N = Worklist.back();
299 if (++Visited[N] != N->getNumOperands())
300 continue; // Haven't visited all operands yet
304 // Now that we have N in, add anything that uses it if all of their operands
306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
308 Worklist.push_back(*UI);
311 assert(Order.size() == Visited.size() &&
313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
314 "Error: DAG is cyclic!");
318 void SelectionDAGLegalize::LegalizeDAG() {
319 LastCALLSEQ_END = DAG.getEntryNode();
320 IsLegalizingCall = false;
322 // The legalize process is inherently a bottom-up recursive process (users
323 // legalize their uses before themselves). Given infinite stack space, we
324 // could just start legalizing on the root and traverse the whole graph. In
325 // practice however, this causes us to run out of stack space on large basic
326 // blocks. To avoid this problem, compute an ordering of the nodes where each
327 // node is only legalized after all of its operands are legalized.
328 SmallVector<SDNode*, 64> Order;
329 ComputeTopDownOrdering(DAG, Order);
331 for (unsigned i = 0, e = Order.size(); i != e; ++i)
332 HandleOp(SDOperand(Order[i], 0));
334 // Finally, it's possible the root changed. Get the new root.
335 SDOperand OldRoot = DAG.getRoot();
336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
337 DAG.setRoot(LegalizedNodes[OldRoot]);
339 ExpandedNodes.clear();
340 LegalizedNodes.clear();
341 PromotedNodes.clear();
343 ScalarizedNodes.clear();
345 // Remove dead nodes now.
346 DAG.RemoveDeadNodes();
350 /// FindCallEndFromCallStart - Given a chained node that is part of a call
351 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
352 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
353 if (Node->getOpcode() == ISD::CALLSEQ_END)
355 if (Node->use_empty())
356 return 0; // No CallSeqEnd
358 // The chain is usually at the end.
359 SDOperand TheChain(Node, Node->getNumValues()-1);
360 if (TheChain.getValueType() != MVT::Other) {
361 // Sometimes it's at the beginning.
362 TheChain = SDOperand(Node, 0);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Otherwise, hunt for it.
365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
366 if (Node->getValueType(i) == MVT::Other) {
367 TheChain = SDOperand(Node, i);
371 // Otherwise, we walked into a node without a chain.
372 if (TheChain.getValueType() != MVT::Other)
377 for (SDNode::use_iterator UI = Node->use_begin(),
378 E = Node->use_end(); UI != E; ++UI) {
380 // Make sure to only follow users of our token chain.
382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
383 if (User->getOperand(i) == TheChain)
384 if (SDNode *Result = FindCallEndFromCallStart(User))
390 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
391 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
392 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
393 assert(Node && "Didn't find callseq_start for a call??");
394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
396 assert(Node->getOperand(0).getValueType() == MVT::Other &&
397 "Node doesn't have a token chain argument!");
398 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
401 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
402 /// see if any uses can reach Dest. If no dest operands can get to dest,
403 /// legalize them, legalize ourself, and return false, otherwise, return true.
405 /// Keep track of the nodes we fine that actually do lead to Dest in
406 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If we've already processed this node and it does lead to Dest, there is no
413 // need to reprocess it.
414 if (NodesLeadingTo.count(N)) return true;
416 // If the first result of this node has been already legalized, then it cannot
418 switch (getTypeAction(N->getValueType(0))) {
420 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
423 if (PromotedNodes.count(SDOperand(N, 0))) return false;
426 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
430 // Okay, this node has not already been legalized. Check and legalize all
431 // operands. If none lead to Dest, then we can legalize this node.
432 bool OperandsLeadToDest = false;
433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
434 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
437 if (OperandsLeadToDest) {
438 NodesLeadingTo.insert(N);
442 // Okay, this node looks safe, legalize it and return false.
443 HandleOp(SDOperand(N, 0));
447 /// HandleOp - Legalize, Promote, or Expand the specified operand as
448 /// appropriate for its type.
449 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
450 MVT::ValueType VT = Op.getValueType();
451 switch (getTypeAction(VT)) {
452 default: assert(0 && "Bad type action!");
453 case Legal: (void)LegalizeOp(Op); break;
454 case Promote: (void)PromoteOp(Op); break;
456 if (!MVT::isVector(VT)) {
457 // If this is an illegal scalar, expand it into its two component
460 if (Op.getOpcode() == ISD::TargetConstant)
461 break; // Allow illegal target nodes.
463 } else if (MVT::getVectorNumElements(VT) == 1) {
464 // If this is an illegal single element vector, convert it to a
466 (void)ScalarizeVectorOp(Op);
468 // Otherwise, this is an illegal multiple element vector.
469 // Split it in half and legalize both parts.
471 SplitVectorOp(Op, X, Y);
477 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
478 /// a load from the constant pool.
479 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
480 SelectionDAG &DAG, TargetLowering &TLI) {
483 // If a FP immediate is precise when represented as a float and if the
484 // target can do an extending load from float to double, we put it into
485 // the constant pool as a float, even if it's is statically typed as a
487 MVT::ValueType VT = CFP->getValueType(0);
488 bool isDouble = VT == MVT::f64;
489 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
490 Type::FloatTy, CFP->getValue());
492 double Val = LLVMC->getValue();
494 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
495 : DAG.getConstant(FloatToBits(Val), MVT::i32);
498 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
499 // Only do this if the target has a native EXTLOAD instruction from f32.
500 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
501 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
506 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
508 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
509 CPIdx, NULL, 0, MVT::f32);
511 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
516 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
519 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
520 SelectionDAG &DAG, TargetLowering &TLI) {
521 MVT::ValueType VT = Node->getValueType(0);
522 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
523 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
524 "fcopysign expansion only supported for f32 and f64");
525 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
527 // First get the sign bit of second operand.
528 SDOperand Mask1 = (SrcVT == MVT::f64)
529 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
530 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
531 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
532 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
533 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
534 // Shift right or sign-extend it if the two operands have different types.
535 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
537 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
538 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
539 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
540 } else if (SizeDiff < 0)
541 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
543 // Clear the sign bit of first operand.
544 SDOperand Mask2 = (VT == MVT::f64)
545 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
546 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
547 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
548 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
549 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
551 // Or the value with the sign bit.
552 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
556 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
558 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
559 TargetLowering &TLI) {
560 assert(MVT::isInteger(ST->getStoredVT()) &&
561 "Non integer unaligned stores not implemented.");
562 int SVOffset = ST->getSrcValueOffset();
563 SDOperand Chain = ST->getChain();
564 SDOperand Ptr = ST->getBasePtr();
565 SDOperand Val = ST->getValue();
566 MVT::ValueType VT = Val.getValueType();
567 // Get the half-size VT
568 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
569 int NumBits = MVT::getSizeInBits(NewStoredVT);
570 int Alignment = ST->getAlignment();
571 int IncrementSize = NumBits / 8;
573 // Divide the stored value in two parts.
574 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
576 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
578 // Store the two parts
579 SDOperand Store1, Store2;
580 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
581 ST->getSrcValue(), SVOffset, NewStoredVT,
582 ST->isVolatile(), Alignment);
583 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
584 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
585 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
586 ST->getSrcValue(), SVOffset + IncrementSize,
587 NewStoredVT, ST->isVolatile(), Alignment);
589 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
592 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
594 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
595 TargetLowering &TLI) {
596 assert(MVT::isInteger(LD->getLoadedVT()) &&
597 "Non integer unaligned loads not implemented.");
598 int SVOffset = LD->getSrcValueOffset();
599 SDOperand Chain = LD->getChain();
600 SDOperand Ptr = LD->getBasePtr();
601 MVT::ValueType VT = LD->getValueType(0);
602 MVT::ValueType NewLoadedVT = LD->getLoadedVT() - 1;
603 int NumBits = MVT::getSizeInBits(NewLoadedVT);
604 int Alignment = LD->getAlignment();
605 int IncrementSize = NumBits / 8;
606 ISD::LoadExtType HiExtType = LD->getExtensionType();
608 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
609 if (HiExtType == ISD::NON_EXTLOAD)
610 HiExtType = ISD::ZEXTLOAD;
612 // Load the value in two parts
614 if (TLI.isLittleEndian()) {
615 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
616 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
617 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
618 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
619 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
623 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
624 NewLoadedVT,LD->isVolatile(), Alignment);
625 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
626 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
627 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
628 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
632 // aggregate the two parts
633 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
634 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
635 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
637 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
640 SDOperand Ops[] = { Result, TF };
641 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
644 /// LegalizeOp - We know that the specified value has a legal type, and
645 /// that its operands are legal. Now ensure that the operation itself
646 /// is legal, recursively ensuring that the operands' operations remain
648 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
649 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
652 assert(isTypeLegal(Op.getValueType()) &&
653 "Caller should expand or promote operands that are not legal!");
654 SDNode *Node = Op.Val;
656 // If this operation defines any values that cannot be represented in a
657 // register on this target, make sure to expand or promote them.
658 if (Node->getNumValues() > 1) {
659 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
660 if (getTypeAction(Node->getValueType(i)) != Legal) {
661 HandleOp(Op.getValue(i));
662 assert(LegalizedNodes.count(Op) &&
663 "Handling didn't add legal operands!");
664 return LegalizedNodes[Op];
668 // Note that LegalizeOp may be reentered even from single-use nodes, which
669 // means that we always must cache transformed nodes.
670 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
671 if (I != LegalizedNodes.end()) return I->second;
673 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
674 SDOperand Result = Op;
675 bool isCustom = false;
677 switch (Node->getOpcode()) {
678 case ISD::FrameIndex:
679 case ISD::EntryToken:
681 case ISD::BasicBlock:
682 case ISD::TargetFrameIndex:
683 case ISD::TargetJumpTable:
684 case ISD::TargetConstant:
685 case ISD::TargetConstantFP:
686 case ISD::TargetConstantPool:
687 case ISD::TargetGlobalAddress:
688 case ISD::TargetGlobalTLSAddress:
689 case ISD::TargetExternalSymbol:
694 // Primitives must all be legal.
695 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
696 "This must be legal!");
699 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
700 // If this is a target node, legalize it by legalizing the operands then
701 // passing it through.
702 SmallVector<SDOperand, 8> Ops;
703 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
704 Ops.push_back(LegalizeOp(Node->getOperand(i)));
706 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
708 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
709 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
710 return Result.getValue(Op.ResNo);
712 // Otherwise this is an unhandled builtin node. splat.
714 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
716 assert(0 && "Do not know how to legalize this operator!");
718 case ISD::GLOBAL_OFFSET_TABLE:
719 case ISD::GlobalAddress:
720 case ISD::GlobalTLSAddress:
721 case ISD::ExternalSymbol:
722 case ISD::ConstantPool:
723 case ISD::JumpTable: // Nothing to do.
724 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
725 default: assert(0 && "This action is not supported yet!");
726 case TargetLowering::Custom:
727 Tmp1 = TLI.LowerOperation(Op, DAG);
728 if (Tmp1.Val) Result = Tmp1;
729 // FALLTHROUGH if the target doesn't want to lower this op after all.
730 case TargetLowering::Legal:
735 case ISD::RETURNADDR:
736 case ISD::FRAME_TO_ARGS_OFFSET:
737 // The only option for these nodes is to custom lower them. If the target
738 // does not custom lower them, then return zero.
739 Tmp1 = TLI.LowerOperation(Op, DAG);
743 Result = DAG.getConstant(0, TLI.getPointerTy());
745 case ISD::EXCEPTIONADDR: {
746 Tmp1 = LegalizeOp(Node->getOperand(0));
747 MVT::ValueType VT = Node->getValueType(0);
748 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
749 default: assert(0 && "This action is not supported yet!");
750 case TargetLowering::Expand: {
751 unsigned Reg = TLI.getExceptionAddressRegister();
752 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
755 case TargetLowering::Custom:
756 Result = TLI.LowerOperation(Op, DAG);
757 if (Result.Val) break;
759 case TargetLowering::Legal: {
760 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
761 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
762 Ops, 2).getValue(Op.ResNo);
768 case ISD::EHSELECTION: {
769 Tmp1 = LegalizeOp(Node->getOperand(0));
770 Tmp2 = LegalizeOp(Node->getOperand(1));
771 MVT::ValueType VT = Node->getValueType(0);
772 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
773 default: assert(0 && "This action is not supported yet!");
774 case TargetLowering::Expand: {
775 unsigned Reg = TLI.getExceptionSelectorRegister();
776 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
779 case TargetLowering::Custom:
780 Result = TLI.LowerOperation(Op, DAG);
781 if (Result.Val) break;
783 case TargetLowering::Legal: {
784 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
785 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
786 Ops, 2).getValue(Op.ResNo);
792 case ISD::EH_RETURN: {
793 MVT::ValueType VT = Node->getValueType(0);
794 // The only "good" option for this node is to custom lower it.
795 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
796 default: assert(0 && "This action is not supported at all!");
797 case TargetLowering::Custom:
798 Result = TLI.LowerOperation(Op, DAG);
799 if (Result.Val) break;
801 case TargetLowering::Legal:
802 // Target does not know, how to lower this, lower to noop
803 Result = LegalizeOp(Node->getOperand(0));
808 case ISD::AssertSext:
809 case ISD::AssertZext:
810 Tmp1 = LegalizeOp(Node->getOperand(0));
811 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
813 case ISD::MERGE_VALUES:
814 // Legalize eliminates MERGE_VALUES nodes.
815 Result = Node->getOperand(Op.ResNo);
817 case ISD::CopyFromReg:
818 Tmp1 = LegalizeOp(Node->getOperand(0));
819 Result = Op.getValue(0);
820 if (Node->getNumValues() == 2) {
821 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
823 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
824 if (Node->getNumOperands() == 3) {
825 Tmp2 = LegalizeOp(Node->getOperand(2));
826 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
828 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
830 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
832 // Since CopyFromReg produces two values, make sure to remember that we
833 // legalized both of them.
834 AddLegalizedOperand(Op.getValue(0), Result);
835 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
836 return Result.getValue(Op.ResNo);
838 MVT::ValueType VT = Op.getValueType();
839 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
840 default: assert(0 && "This action is not supported yet!");
841 case TargetLowering::Expand:
842 if (MVT::isInteger(VT))
843 Result = DAG.getConstant(0, VT);
844 else if (MVT::isFloatingPoint(VT))
845 Result = DAG.getConstantFP(0, VT);
847 assert(0 && "Unknown value type!");
849 case TargetLowering::Legal:
855 case ISD::INTRINSIC_W_CHAIN:
856 case ISD::INTRINSIC_WO_CHAIN:
857 case ISD::INTRINSIC_VOID: {
858 SmallVector<SDOperand, 8> Ops;
859 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
860 Ops.push_back(LegalizeOp(Node->getOperand(i)));
861 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
863 // Allow the target to custom lower its intrinsics if it wants to.
864 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
865 TargetLowering::Custom) {
866 Tmp3 = TLI.LowerOperation(Result, DAG);
867 if (Tmp3.Val) Result = Tmp3;
870 if (Result.Val->getNumValues() == 1) break;
872 // Must have return value and chain result.
873 assert(Result.Val->getNumValues() == 2 &&
874 "Cannot return more than two values!");
876 // Since loads produce two values, make sure to remember that we
877 // legalized both of them.
878 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
879 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
880 return Result.getValue(Op.ResNo);
884 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
885 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
887 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
888 case TargetLowering::Promote:
889 default: assert(0 && "This action is not supported yet!");
890 case TargetLowering::Expand: {
891 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
892 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
893 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
895 if (MMI && (useDEBUG_LOC || useLABEL)) {
896 const std::string &FName =
897 cast<StringSDNode>(Node->getOperand(3))->getValue();
898 const std::string &DirName =
899 cast<StringSDNode>(Node->getOperand(4))->getValue();
900 unsigned SrcFile = MMI->RecordSource(DirName, FName);
902 SmallVector<SDOperand, 8> Ops;
903 Ops.push_back(Tmp1); // chain
904 SDOperand LineOp = Node->getOperand(1);
905 SDOperand ColOp = Node->getOperand(2);
908 Ops.push_back(LineOp); // line #
909 Ops.push_back(ColOp); // col #
910 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
911 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
913 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
914 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
915 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
916 Ops.push_back(DAG.getConstant(ID, MVT::i32));
917 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
920 Result = Tmp1; // chain
924 case TargetLowering::Legal:
925 if (Tmp1 != Node->getOperand(0) ||
926 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
927 SmallVector<SDOperand, 8> Ops;
929 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
930 Ops.push_back(Node->getOperand(1)); // line # must be legal.
931 Ops.push_back(Node->getOperand(2)); // col # must be legal.
933 // Otherwise promote them.
934 Ops.push_back(PromoteOp(Node->getOperand(1)));
935 Ops.push_back(PromoteOp(Node->getOperand(2)));
937 Ops.push_back(Node->getOperand(3)); // filename must be legal.
938 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
939 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
946 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
947 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
948 default: assert(0 && "This action is not supported yet!");
949 case TargetLowering::Legal:
950 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
951 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
952 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
953 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
954 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
960 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
961 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
962 default: assert(0 && "This action is not supported yet!");
963 case TargetLowering::Legal:
964 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
965 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
966 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
968 case TargetLowering::Expand:
969 Result = LegalizeOp(Node->getOperand(0));
974 case ISD::Constant: {
975 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
977 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
979 // We know we don't need to expand constants here, constants only have one
980 // value and we check that it is fine above.
982 if (opAction == TargetLowering::Custom) {
983 Tmp1 = TLI.LowerOperation(Result, DAG);
989 case ISD::ConstantFP: {
990 // Spill FP immediates to the constant pool if the target cannot directly
991 // codegen them. Targets often have some immediate values that can be
992 // efficiently generated into an FP register without a load. We explicitly
993 // leave these constants as ConstantFP nodes for the target to deal with.
994 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
996 // Check to see if this FP immediate is already legal.
997 bool isLegal = false;
998 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
999 E = TLI.legal_fpimm_end(); I != E; ++I)
1000 if (CFP->isExactlyValue(*I)) {
1005 // If this is a legal constant, turn it into a TargetConstantFP node.
1007 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
1011 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1012 default: assert(0 && "This action is not supported yet!");
1013 case TargetLowering::Custom:
1014 Tmp3 = TLI.LowerOperation(Result, DAG);
1020 case TargetLowering::Expand:
1021 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1025 case ISD::TokenFactor:
1026 if (Node->getNumOperands() == 2) {
1027 Tmp1 = LegalizeOp(Node->getOperand(0));
1028 Tmp2 = LegalizeOp(Node->getOperand(1));
1029 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1030 } else if (Node->getNumOperands() == 3) {
1031 Tmp1 = LegalizeOp(Node->getOperand(0));
1032 Tmp2 = LegalizeOp(Node->getOperand(1));
1033 Tmp3 = LegalizeOp(Node->getOperand(2));
1034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1036 SmallVector<SDOperand, 8> Ops;
1037 // Legalize the operands.
1038 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1039 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1040 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1044 case ISD::FORMAL_ARGUMENTS:
1046 // The only option for this is to custom lower it.
1047 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1048 assert(Tmp3.Val && "Target didn't custom lower this node!");
1049 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1050 "Lowering call/formal_arguments produced unexpected # results!");
1052 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1053 // remember that we legalized all of them, so it doesn't get relegalized.
1054 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1055 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1058 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1061 case ISD::EXTRACT_SUBREG: {
1062 Tmp1 = LegalizeOp(Node->getOperand(0));
1063 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1064 assert(idx && "Operand must be a constant");
1065 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1066 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1069 case ISD::INSERT_SUBREG: {
1070 Tmp1 = LegalizeOp(Node->getOperand(0));
1071 Tmp2 = LegalizeOp(Node->getOperand(1));
1072 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1073 assert(idx && "Operand must be a constant");
1074 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1075 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1078 case ISD::BUILD_VECTOR:
1079 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1080 default: assert(0 && "This action is not supported yet!");
1081 case TargetLowering::Custom:
1082 Tmp3 = TLI.LowerOperation(Result, DAG);
1088 case TargetLowering::Expand:
1089 Result = ExpandBUILD_VECTOR(Result.Val);
1093 case ISD::INSERT_VECTOR_ELT:
1094 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1095 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1096 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1099 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1100 Node->getValueType(0))) {
1101 default: assert(0 && "This action is not supported yet!");
1102 case TargetLowering::Legal:
1104 case TargetLowering::Custom:
1105 Tmp3 = TLI.LowerOperation(Result, DAG);
1111 case TargetLowering::Expand: {
1112 // If the insert index is a constant, codegen this as a scalar_to_vector,
1113 // then a shuffle that inserts it into the right position in the vector.
1114 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1115 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1116 Tmp1.getValueType(), Tmp2);
1118 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1119 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1120 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1122 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1123 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1125 SmallVector<SDOperand, 8> ShufOps;
1126 for (unsigned i = 0; i != NumElts; ++i) {
1127 if (i != InsertPos->getValue())
1128 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1130 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1132 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1133 &ShufOps[0], ShufOps.size());
1135 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1136 Tmp1, ScVec, ShufMask);
1137 Result = LegalizeOp(Result);
1141 // If the target doesn't support this, we have to spill the input vector
1142 // to a temporary stack slot, update the element, then reload it. This is
1143 // badness. We could also load the value into a vector register (either
1144 // with a "move to register" or "extload into register" instruction, then
1145 // permute it into place, if the idx is a constant and if the idx is
1146 // supported by the target.
1147 MVT::ValueType VT = Tmp1.getValueType();
1148 MVT::ValueType EltVT = Tmp2.getValueType();
1149 MVT::ValueType IdxVT = Tmp3.getValueType();
1150 MVT::ValueType PtrVT = TLI.getPointerTy();
1151 SDOperand StackPtr = CreateStackTemporary(VT);
1152 // Store the vector.
1153 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1155 // Truncate or zero extend offset to target pointer type.
1156 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1157 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1158 // Add the offset to the index.
1159 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1160 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1161 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1162 // Store the scalar value.
1163 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1164 // Load the updated vector.
1165 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1170 case ISD::SCALAR_TO_VECTOR:
1171 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1172 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1176 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1177 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1178 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1179 Node->getValueType(0))) {
1180 default: assert(0 && "This action is not supported yet!");
1181 case TargetLowering::Legal:
1183 case TargetLowering::Custom:
1184 Tmp3 = TLI.LowerOperation(Result, DAG);
1190 case TargetLowering::Expand:
1191 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1195 case ISD::VECTOR_SHUFFLE:
1196 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1197 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1198 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1200 // Allow targets to custom lower the SHUFFLEs they support.
1201 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1202 default: assert(0 && "Unknown operation action!");
1203 case TargetLowering::Legal:
1204 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1205 "vector shuffle should not be created if not legal!");
1207 case TargetLowering::Custom:
1208 Tmp3 = TLI.LowerOperation(Result, DAG);
1214 case TargetLowering::Expand: {
1215 MVT::ValueType VT = Node->getValueType(0);
1216 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1217 MVT::ValueType PtrVT = TLI.getPointerTy();
1218 SDOperand Mask = Node->getOperand(2);
1219 unsigned NumElems = Mask.getNumOperands();
1220 SmallVector<SDOperand,8> Ops;
1221 for (unsigned i = 0; i != NumElems; ++i) {
1222 SDOperand Arg = Mask.getOperand(i);
1223 if (Arg.getOpcode() == ISD::UNDEF) {
1224 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1226 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1227 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1229 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1230 DAG.getConstant(Idx, PtrVT)));
1232 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1233 DAG.getConstant(Idx - NumElems, PtrVT)));
1236 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1239 case TargetLowering::Promote: {
1240 // Change base type to a different vector type.
1241 MVT::ValueType OVT = Node->getValueType(0);
1242 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1244 // Cast the two input vectors.
1245 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1246 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1248 // Convert the shuffle mask to the right # elements.
1249 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1250 assert(Tmp3.Val && "Shuffle not legal?");
1251 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1252 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1258 case ISD::EXTRACT_VECTOR_ELT:
1259 Tmp1 = Node->getOperand(0);
1260 Tmp2 = LegalizeOp(Node->getOperand(1));
1261 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1262 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1265 case ISD::EXTRACT_SUBVECTOR:
1266 Tmp1 = Node->getOperand(0);
1267 Tmp2 = LegalizeOp(Node->getOperand(1));
1268 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1269 Result = ExpandEXTRACT_SUBVECTOR(Result);
1272 case ISD::CALLSEQ_START: {
1273 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1275 // Recursively Legalize all of the inputs of the call end that do not lead
1276 // to this call start. This ensures that any libcalls that need be inserted
1277 // are inserted *before* the CALLSEQ_START.
1278 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1279 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1280 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1284 // Now that we legalized all of the inputs (which may have inserted
1285 // libcalls) create the new CALLSEQ_START node.
1286 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1288 // Merge in the last call, to ensure that this call start after the last
1290 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1291 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1292 Tmp1 = LegalizeOp(Tmp1);
1295 // Do not try to legalize the target-specific arguments (#1+).
1296 if (Tmp1 != Node->getOperand(0)) {
1297 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1299 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1302 // Remember that the CALLSEQ_START is legalized.
1303 AddLegalizedOperand(Op.getValue(0), Result);
1304 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1305 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1307 // Now that the callseq_start and all of the non-call nodes above this call
1308 // sequence have been legalized, legalize the call itself. During this
1309 // process, no libcalls can/will be inserted, guaranteeing that no calls
1311 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1312 SDOperand InCallSEQ = LastCALLSEQ_END;
1313 // Note that we are selecting this call!
1314 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1315 IsLegalizingCall = true;
1317 // Legalize the call, starting from the CALLSEQ_END.
1318 LegalizeOp(LastCALLSEQ_END);
1319 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1322 case ISD::CALLSEQ_END:
1323 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1324 // will cause this node to be legalized as well as handling libcalls right.
1325 if (LastCALLSEQ_END.Val != Node) {
1326 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1327 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1328 assert(I != LegalizedNodes.end() &&
1329 "Legalizing the call start should have legalized this node!");
1333 // Otherwise, the call start has been legalized and everything is going
1334 // according to plan. Just legalize ourselves normally here.
1335 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1336 // Do not try to legalize the target-specific arguments (#1+), except for
1337 // an optional flag input.
1338 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1339 if (Tmp1 != Node->getOperand(0)) {
1340 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1342 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1345 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1346 if (Tmp1 != Node->getOperand(0) ||
1347 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1348 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1351 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1354 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1355 // This finishes up call legalization.
1356 IsLegalizingCall = false;
1358 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1359 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1360 if (Node->getNumValues() == 2)
1361 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1362 return Result.getValue(Op.ResNo);
1363 case ISD::DYNAMIC_STACKALLOC: {
1364 MVT::ValueType VT = Node->getValueType(0);
1365 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1366 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1367 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1368 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1370 Tmp1 = Result.getValue(0);
1371 Tmp2 = Result.getValue(1);
1372 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1373 default: assert(0 && "This action is not supported yet!");
1374 case TargetLowering::Expand: {
1375 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1376 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1377 " not tell us which reg is the stack pointer!");
1378 SDOperand Chain = Tmp1.getOperand(0);
1379 SDOperand Size = Tmp2.getOperand(1);
1380 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1381 Chain = SP.getValue(1);
1382 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1383 unsigned StackAlign =
1384 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1385 if (Align > StackAlign)
1386 SP = DAG.getNode(ISD::AND, VT, SP,
1387 DAG.getConstant(-(uint64_t)Align, VT));
1388 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1389 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1390 Tmp1 = LegalizeOp(Tmp1);
1391 Tmp2 = LegalizeOp(Tmp2);
1394 case TargetLowering::Custom:
1395 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1397 Tmp1 = LegalizeOp(Tmp3);
1398 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1401 case TargetLowering::Legal:
1404 // Since this op produce two values, make sure to remember that we
1405 // legalized both of them.
1406 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1407 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1408 return Op.ResNo ? Tmp2 : Tmp1;
1410 case ISD::INLINEASM: {
1411 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1412 bool Changed = false;
1413 // Legalize all of the operands of the inline asm, in case they are nodes
1414 // that need to be expanded or something. Note we skip the asm string and
1415 // all of the TargetConstant flags.
1416 SDOperand Op = LegalizeOp(Ops[0]);
1417 Changed = Op != Ops[0];
1420 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1421 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1422 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1423 for (++i; NumVals; ++i, --NumVals) {
1424 SDOperand Op = LegalizeOp(Ops[i]);
1433 Op = LegalizeOp(Ops.back());
1434 Changed |= Op != Ops.back();
1439 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1441 // INLINE asm returns a chain and flag, make sure to add both to the map.
1442 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1443 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1444 return Result.getValue(Op.ResNo);
1447 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1448 // Ensure that libcalls are emitted before a branch.
1449 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1450 Tmp1 = LegalizeOp(Tmp1);
1451 LastCALLSEQ_END = DAG.getEntryNode();
1453 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1456 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1457 // Ensure that libcalls are emitted before a branch.
1458 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1459 Tmp1 = LegalizeOp(Tmp1);
1460 LastCALLSEQ_END = DAG.getEntryNode();
1462 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1463 default: assert(0 && "Indirect target must be legal type (pointer)!");
1465 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1471 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1472 // Ensure that libcalls are emitted before a branch.
1473 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1474 Tmp1 = LegalizeOp(Tmp1);
1475 LastCALLSEQ_END = DAG.getEntryNode();
1477 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1478 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1480 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1481 default: assert(0 && "This action is not supported yet!");
1482 case TargetLowering::Legal: break;
1483 case TargetLowering::Custom:
1484 Tmp1 = TLI.LowerOperation(Result, DAG);
1485 if (Tmp1.Val) Result = Tmp1;
1487 case TargetLowering::Expand: {
1488 SDOperand Chain = Result.getOperand(0);
1489 SDOperand Table = Result.getOperand(1);
1490 SDOperand Index = Result.getOperand(2);
1492 MVT::ValueType PTy = TLI.getPointerTy();
1493 MachineFunction &MF = DAG.getMachineFunction();
1494 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1495 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1496 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1499 switch (EntrySize) {
1500 default: assert(0 && "Size of jump table not supported yet."); break;
1501 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1502 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1505 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1506 // For PIC, the sequence is:
1507 // BRIND(load(Jumptable + index) + RelocBase)
1508 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1510 if (TLI.usesGlobalOffsetTable())
1511 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1514 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1515 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1516 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1518 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1524 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1525 // Ensure that libcalls are emitted before a return.
1526 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1527 Tmp1 = LegalizeOp(Tmp1);
1528 LastCALLSEQ_END = DAG.getEntryNode();
1530 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1531 case Expand: assert(0 && "It's impossible to expand bools");
1533 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1536 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1538 // The top bits of the promoted condition are not necessarily zero, ensure
1539 // that the value is properly zero extended.
1540 if (!DAG.MaskedValueIsZero(Tmp2,
1541 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1542 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1546 // Basic block destination (Op#2) is always legal.
1547 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1549 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1550 default: assert(0 && "This action is not supported yet!");
1551 case TargetLowering::Legal: break;
1552 case TargetLowering::Custom:
1553 Tmp1 = TLI.LowerOperation(Result, DAG);
1554 if (Tmp1.Val) Result = Tmp1;
1556 case TargetLowering::Expand:
1557 // Expand brcond's setcc into its constituent parts and create a BR_CC
1559 if (Tmp2.getOpcode() == ISD::SETCC) {
1560 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1561 Tmp2.getOperand(0), Tmp2.getOperand(1),
1562 Node->getOperand(2));
1564 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1565 DAG.getCondCode(ISD::SETNE), Tmp2,
1566 DAG.getConstant(0, Tmp2.getValueType()),
1567 Node->getOperand(2));
1573 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1574 // Ensure that libcalls are emitted before a branch.
1575 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1576 Tmp1 = LegalizeOp(Tmp1);
1577 Tmp2 = Node->getOperand(2); // LHS
1578 Tmp3 = Node->getOperand(3); // RHS
1579 Tmp4 = Node->getOperand(1); // CC
1581 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1582 LastCALLSEQ_END = DAG.getEntryNode();
1584 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1585 // the LHS is a legal SETCC itself. In this case, we need to compare
1586 // the result against zero to select between true and false values.
1587 if (Tmp3.Val == 0) {
1588 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1589 Tmp4 = DAG.getCondCode(ISD::SETNE);
1592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1593 Node->getOperand(4));
1595 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1596 default: assert(0 && "Unexpected action for BR_CC!");
1597 case TargetLowering::Legal: break;
1598 case TargetLowering::Custom:
1599 Tmp4 = TLI.LowerOperation(Result, DAG);
1600 if (Tmp4.Val) Result = Tmp4;
1605 LoadSDNode *LD = cast<LoadSDNode>(Node);
1606 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1607 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1609 ISD::LoadExtType ExtType = LD->getExtensionType();
1610 if (ExtType == ISD::NON_EXTLOAD) {
1611 MVT::ValueType VT = Node->getValueType(0);
1612 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1613 Tmp3 = Result.getValue(0);
1614 Tmp4 = Result.getValue(1);
1616 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1617 default: assert(0 && "This action is not supported yet!");
1618 case TargetLowering::Legal:
1619 // If this is an unaligned load and the target doesn't support it,
1621 if (!TLI.allowsUnalignedMemoryAccesses()) {
1622 unsigned ABIAlignment = TLI.getTargetData()->
1623 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1624 if (LD->getAlignment() < ABIAlignment){
1625 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1627 Tmp3 = Result.getOperand(0);
1628 Tmp4 = Result.getOperand(1);
1634 case TargetLowering::Custom:
1635 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1637 Tmp3 = LegalizeOp(Tmp1);
1638 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1641 case TargetLowering::Promote: {
1642 // Only promote a load of vector type to another.
1643 assert(MVT::isVector(VT) && "Cannot promote this load!");
1644 // Change base type to a different vector type.
1645 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1647 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1648 LD->getSrcValueOffset(),
1649 LD->isVolatile(), LD->getAlignment());
1650 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1651 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1655 // Since loads produce two values, make sure to remember that we
1656 // legalized both of them.
1657 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1658 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1659 return Op.ResNo ? Tmp4 : Tmp3;
1661 MVT::ValueType SrcVT = LD->getLoadedVT();
1662 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1663 default: assert(0 && "This action is not supported yet!");
1664 case TargetLowering::Promote:
1665 assert(SrcVT == MVT::i1 &&
1666 "Can only promote extending LOAD from i1 -> i8!");
1667 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1668 LD->getSrcValue(), LD->getSrcValueOffset(),
1669 MVT::i8, LD->isVolatile(), LD->getAlignment());
1670 Tmp1 = Result.getValue(0);
1671 Tmp2 = Result.getValue(1);
1673 case TargetLowering::Custom:
1676 case TargetLowering::Legal:
1677 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1678 Tmp1 = Result.getValue(0);
1679 Tmp2 = Result.getValue(1);
1682 Tmp3 = TLI.LowerOperation(Result, DAG);
1684 Tmp1 = LegalizeOp(Tmp3);
1685 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1688 // If this is an unaligned load and the target doesn't support it,
1690 if (!TLI.allowsUnalignedMemoryAccesses()) {
1691 unsigned ABIAlignment = TLI.getTargetData()->
1692 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1693 if (LD->getAlignment() < ABIAlignment){
1694 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1696 Tmp1 = Result.getOperand(0);
1697 Tmp2 = Result.getOperand(1);
1704 case TargetLowering::Expand:
1705 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1706 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1707 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1708 LD->getSrcValueOffset(),
1709 LD->isVolatile(), LD->getAlignment());
1710 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1711 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1712 Tmp2 = LegalizeOp(Load.getValue(1));
1715 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1716 // Turn the unsupported load into an EXTLOAD followed by an explicit
1717 // zero/sign extend inreg.
1718 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1719 Tmp1, Tmp2, LD->getSrcValue(),
1720 LD->getSrcValueOffset(), SrcVT,
1721 LD->isVolatile(), LD->getAlignment());
1723 if (ExtType == ISD::SEXTLOAD)
1724 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1725 Result, DAG.getValueType(SrcVT));
1727 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1728 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1729 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1732 // Since loads produce two values, make sure to remember that we legalized
1734 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1735 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1736 return Op.ResNo ? Tmp2 : Tmp1;
1739 case ISD::EXTRACT_ELEMENT: {
1740 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1741 switch (getTypeAction(OpTy)) {
1742 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1744 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1746 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1747 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1748 TLI.getShiftAmountTy()));
1749 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1752 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1753 Node->getOperand(0));
1757 // Get both the low and high parts.
1758 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1759 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1760 Result = Tmp2; // 1 -> Hi
1762 Result = Tmp1; // 0 -> Lo
1768 case ISD::CopyToReg:
1769 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1771 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1772 "Register type must be legal!");
1773 // Legalize the incoming value (must be a legal type).
1774 Tmp2 = LegalizeOp(Node->getOperand(2));
1775 if (Node->getNumValues() == 1) {
1776 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1778 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1779 if (Node->getNumOperands() == 4) {
1780 Tmp3 = LegalizeOp(Node->getOperand(3));
1781 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1784 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1787 // Since this produces two values, make sure to remember that we legalized
1789 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1790 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1796 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1798 // Ensure that libcalls are emitted before a return.
1799 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1800 Tmp1 = LegalizeOp(Tmp1);
1801 LastCALLSEQ_END = DAG.getEntryNode();
1803 switch (Node->getNumOperands()) {
1805 Tmp2 = Node->getOperand(1);
1806 Tmp3 = Node->getOperand(2); // Signness
1807 switch (getTypeAction(Tmp2.getValueType())) {
1809 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1812 if (!MVT::isVector(Tmp2.getValueType())) {
1814 ExpandOp(Tmp2, Lo, Hi);
1816 // Big endian systems want the hi reg first.
1817 if (!TLI.isLittleEndian())
1821 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1823 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1824 Result = LegalizeOp(Result);
1826 SDNode *InVal = Tmp2.Val;
1827 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1828 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1830 // Figure out if there is a simple type corresponding to this Vector
1831 // type. If so, convert to the vector type.
1832 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1833 if (TLI.isTypeLegal(TVT)) {
1834 // Turn this into a return of the vector type.
1835 Tmp2 = LegalizeOp(Tmp2);
1836 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1837 } else if (NumElems == 1) {
1838 // Turn this into a return of the scalar type.
1839 Tmp2 = ScalarizeVectorOp(Tmp2);
1840 Tmp2 = LegalizeOp(Tmp2);
1841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1843 // FIXME: Returns of gcc generic vectors smaller than a legal type
1844 // should be returned in integer registers!
1846 // The scalarized value type may not be legal, e.g. it might require
1847 // promotion or expansion. Relegalize the return.
1848 Result = LegalizeOp(Result);
1850 // FIXME: Returns of gcc generic vectors larger than a legal vector
1851 // type should be returned by reference!
1853 SplitVectorOp(Tmp2, Lo, Hi);
1854 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1855 Result = LegalizeOp(Result);
1860 Tmp2 = PromoteOp(Node->getOperand(1));
1861 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1862 Result = LegalizeOp(Result);
1867 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1869 default: { // ret <values>
1870 SmallVector<SDOperand, 8> NewValues;
1871 NewValues.push_back(Tmp1);
1872 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1873 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1875 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1876 NewValues.push_back(Node->getOperand(i+1));
1880 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1881 "FIXME: TODO: implement returning non-legal vector types!");
1882 ExpandOp(Node->getOperand(i), Lo, Hi);
1883 NewValues.push_back(Lo);
1884 NewValues.push_back(Node->getOperand(i+1));
1886 NewValues.push_back(Hi);
1887 NewValues.push_back(Node->getOperand(i+1));
1892 assert(0 && "Can't promote multiple return value yet!");
1895 if (NewValues.size() == Node->getNumOperands())
1896 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1898 Result = DAG.getNode(ISD::RET, MVT::Other,
1899 &NewValues[0], NewValues.size());
1904 if (Result.getOpcode() == ISD::RET) {
1905 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1906 default: assert(0 && "This action is not supported yet!");
1907 case TargetLowering::Legal: break;
1908 case TargetLowering::Custom:
1909 Tmp1 = TLI.LowerOperation(Result, DAG);
1910 if (Tmp1.Val) Result = Tmp1;
1916 StoreSDNode *ST = cast<StoreSDNode>(Node);
1917 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1918 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1919 int SVOffset = ST->getSrcValueOffset();
1920 unsigned Alignment = ST->getAlignment();
1921 bool isVolatile = ST->isVolatile();
1923 if (!ST->isTruncatingStore()) {
1924 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1925 // FIXME: We shouldn't do this for TargetConstantFP's.
1926 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1927 // to phase ordering between legalized code and the dag combiner. This
1928 // probably means that we need to integrate dag combiner and legalizer
1930 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1931 if (CFP->getValueType(0) == MVT::f32) {
1932 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1934 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1935 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1937 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1938 SVOffset, isVolatile, Alignment);
1942 switch (getTypeAction(ST->getStoredVT())) {
1944 Tmp3 = LegalizeOp(ST->getValue());
1945 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1948 MVT::ValueType VT = Tmp3.getValueType();
1949 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1950 default: assert(0 && "This action is not supported yet!");
1951 case TargetLowering::Legal:
1952 // If this is an unaligned store and the target doesn't support it,
1954 if (!TLI.allowsUnalignedMemoryAccesses()) {
1955 unsigned ABIAlignment = TLI.getTargetData()->
1956 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
1957 if (ST->getAlignment() < ABIAlignment)
1958 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
1962 case TargetLowering::Custom:
1963 Tmp1 = TLI.LowerOperation(Result, DAG);
1964 if (Tmp1.Val) Result = Tmp1;
1966 case TargetLowering::Promote:
1967 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1968 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1969 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1970 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1971 ST->getSrcValue(), SVOffset, isVolatile,
1978 // Truncate the value and store the result.
1979 Tmp3 = PromoteOp(ST->getValue());
1980 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1981 SVOffset, ST->getStoredVT(),
1982 isVolatile, Alignment);
1986 unsigned IncrementSize = 0;
1989 // If this is a vector type, then we have to calculate the increment as
1990 // the product of the element size in bytes, and the number of elements
1991 // in the high half of the vector.
1992 if (MVT::isVector(ST->getValue().getValueType())) {
1993 SDNode *InVal = ST->getValue().Val;
1994 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1995 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1997 // Figure out if there is a simple type corresponding to this Vector
1998 // type. If so, convert to the vector type.
1999 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2000 if (TLI.isTypeLegal(TVT)) {
2001 // Turn this into a normal store of the vector type.
2002 Tmp3 = LegalizeOp(Node->getOperand(1));
2003 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2004 SVOffset, isVolatile, Alignment);
2005 Result = LegalizeOp(Result);
2007 } else if (NumElems == 1) {
2008 // Turn this into a normal store of the scalar type.
2009 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2010 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2011 SVOffset, isVolatile, Alignment);
2012 // The scalarized value type may not be legal, e.g. it might require
2013 // promotion or expansion. Relegalize the scalar store.
2014 Result = LegalizeOp(Result);
2017 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2018 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2021 ExpandOp(Node->getOperand(1), Lo, Hi);
2022 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2024 if (!TLI.isLittleEndian())
2028 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2029 SVOffset, isVolatile, Alignment);
2031 if (Hi.Val == NULL) {
2032 // Must be int <-> float one-to-one expansion.
2037 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2038 getIntPtrConstant(IncrementSize));
2039 assert(isTypeLegal(Tmp2.getValueType()) &&
2040 "Pointers must be legal!");
2041 SVOffset += IncrementSize;
2042 if (Alignment > IncrementSize)
2043 Alignment = IncrementSize;
2044 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2045 SVOffset, isVolatile, Alignment);
2046 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2051 assert(isTypeLegal(ST->getValue().getValueType()) &&
2052 "Cannot handle illegal TRUNCSTORE yet!");
2053 Tmp3 = LegalizeOp(ST->getValue());
2055 // The only promote case we handle is TRUNCSTORE:i1 X into
2056 // -> TRUNCSTORE:i8 (and X, 1)
2057 if (ST->getStoredVT() == MVT::i1 &&
2058 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2059 // Promote the bool to a mask then store.
2060 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2061 DAG.getConstant(1, Tmp3.getValueType()));
2062 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2064 isVolatile, Alignment);
2065 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2066 Tmp2 != ST->getBasePtr()) {
2067 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2071 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2072 switch (TLI.getStoreXAction(StVT)) {
2073 default: assert(0 && "This action is not supported yet!");
2074 case TargetLowering::Legal:
2075 // If this is an unaligned store and the target doesn't support it,
2077 if (!TLI.allowsUnalignedMemoryAccesses()) {
2078 unsigned ABIAlignment = TLI.getTargetData()->
2079 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2080 if (ST->getAlignment() < ABIAlignment)
2081 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2085 case TargetLowering::Custom:
2086 Tmp1 = TLI.LowerOperation(Result, DAG);
2087 if (Tmp1.Val) Result = Tmp1;
2094 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2095 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2097 case ISD::STACKSAVE:
2098 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2099 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2100 Tmp1 = Result.getValue(0);
2101 Tmp2 = Result.getValue(1);
2103 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2104 default: assert(0 && "This action is not supported yet!");
2105 case TargetLowering::Legal: break;
2106 case TargetLowering::Custom:
2107 Tmp3 = TLI.LowerOperation(Result, DAG);
2109 Tmp1 = LegalizeOp(Tmp3);
2110 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2113 case TargetLowering::Expand:
2114 // Expand to CopyFromReg if the target set
2115 // StackPointerRegisterToSaveRestore.
2116 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2117 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2118 Node->getValueType(0));
2119 Tmp2 = Tmp1.getValue(1);
2121 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2122 Tmp2 = Node->getOperand(0);
2127 // Since stacksave produce two values, make sure to remember that we
2128 // legalized both of them.
2129 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2130 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2131 return Op.ResNo ? Tmp2 : Tmp1;
2133 case ISD::STACKRESTORE:
2134 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2135 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2136 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2138 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2139 default: assert(0 && "This action is not supported yet!");
2140 case TargetLowering::Legal: break;
2141 case TargetLowering::Custom:
2142 Tmp1 = TLI.LowerOperation(Result, DAG);
2143 if (Tmp1.Val) Result = Tmp1;
2145 case TargetLowering::Expand:
2146 // Expand to CopyToReg if the target set
2147 // StackPointerRegisterToSaveRestore.
2148 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2149 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2157 case ISD::READCYCLECOUNTER:
2158 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2159 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2160 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2161 Node->getValueType(0))) {
2162 default: assert(0 && "This action is not supported yet!");
2163 case TargetLowering::Legal:
2164 Tmp1 = Result.getValue(0);
2165 Tmp2 = Result.getValue(1);
2167 case TargetLowering::Custom:
2168 Result = TLI.LowerOperation(Result, DAG);
2169 Tmp1 = LegalizeOp(Result.getValue(0));
2170 Tmp2 = LegalizeOp(Result.getValue(1));
2174 // Since rdcc produce two values, make sure to remember that we legalized
2176 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2177 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2181 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2182 case Expand: assert(0 && "It's impossible to expand bools");
2184 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2187 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2188 // Make sure the condition is either zero or one.
2189 if (!DAG.MaskedValueIsZero(Tmp1,
2190 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2191 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2194 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2195 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2199 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2200 default: assert(0 && "This action is not supported yet!");
2201 case TargetLowering::Legal: break;
2202 case TargetLowering::Custom: {
2203 Tmp1 = TLI.LowerOperation(Result, DAG);
2204 if (Tmp1.Val) Result = Tmp1;
2207 case TargetLowering::Expand:
2208 if (Tmp1.getOpcode() == ISD::SETCC) {
2209 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2211 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2213 Result = DAG.getSelectCC(Tmp1,
2214 DAG.getConstant(0, Tmp1.getValueType()),
2215 Tmp2, Tmp3, ISD::SETNE);
2218 case TargetLowering::Promote: {
2219 MVT::ValueType NVT =
2220 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2221 unsigned ExtOp, TruncOp;
2222 if (MVT::isVector(Tmp2.getValueType())) {
2223 ExtOp = ISD::BIT_CONVERT;
2224 TruncOp = ISD::BIT_CONVERT;
2225 } else if (MVT::isInteger(Tmp2.getValueType())) {
2226 ExtOp = ISD::ANY_EXTEND;
2227 TruncOp = ISD::TRUNCATE;
2229 ExtOp = ISD::FP_EXTEND;
2230 TruncOp = ISD::FP_ROUND;
2232 // Promote each of the values to the new type.
2233 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2234 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2235 // Perform the larger operation, then round down.
2236 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2237 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2242 case ISD::SELECT_CC: {
2243 Tmp1 = Node->getOperand(0); // LHS
2244 Tmp2 = Node->getOperand(1); // RHS
2245 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2246 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2247 SDOperand CC = Node->getOperand(4);
2249 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2251 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2252 // the LHS is a legal SETCC itself. In this case, we need to compare
2253 // the result against zero to select between true and false values.
2254 if (Tmp2.Val == 0) {
2255 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2256 CC = DAG.getCondCode(ISD::SETNE);
2258 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2260 // Everything is legal, see if we should expand this op or something.
2261 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2262 default: assert(0 && "This action is not supported yet!");
2263 case TargetLowering::Legal: break;
2264 case TargetLowering::Custom:
2265 Tmp1 = TLI.LowerOperation(Result, DAG);
2266 if (Tmp1.Val) Result = Tmp1;
2272 Tmp1 = Node->getOperand(0);
2273 Tmp2 = Node->getOperand(1);
2274 Tmp3 = Node->getOperand(2);
2275 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2277 // If we had to Expand the SetCC operands into a SELECT node, then it may
2278 // not always be possible to return a true LHS & RHS. In this case, just
2279 // return the value we legalized, returned in the LHS
2280 if (Tmp2.Val == 0) {
2285 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2286 default: assert(0 && "Cannot handle this action for SETCC yet!");
2287 case TargetLowering::Custom:
2290 case TargetLowering::Legal:
2291 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2293 Tmp4 = TLI.LowerOperation(Result, DAG);
2294 if (Tmp4.Val) Result = Tmp4;
2297 case TargetLowering::Promote: {
2298 // First step, figure out the appropriate operation to use.
2299 // Allow SETCC to not be supported for all legal data types
2300 // Mostly this targets FP
2301 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2302 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2304 // Scan for the appropriate larger type to use.
2306 NewInTy = (MVT::ValueType)(NewInTy+1);
2308 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2309 "Fell off of the edge of the integer world");
2310 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2311 "Fell off of the edge of the floating point world");
2313 // If the target supports SETCC of this type, use it.
2314 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2317 if (MVT::isInteger(NewInTy))
2318 assert(0 && "Cannot promote Legal Integer SETCC yet");
2320 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2321 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2323 Tmp1 = LegalizeOp(Tmp1);
2324 Tmp2 = LegalizeOp(Tmp2);
2325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2326 Result = LegalizeOp(Result);
2329 case TargetLowering::Expand:
2330 // Expand a setcc node into a select_cc of the same condition, lhs, and
2331 // rhs that selects between const 1 (true) and const 0 (false).
2332 MVT::ValueType VT = Node->getValueType(0);
2333 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2334 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2341 case ISD::MEMMOVE: {
2342 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2343 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2345 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2346 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2347 case Expand: assert(0 && "Cannot expand a byte!");
2349 Tmp3 = LegalizeOp(Node->getOperand(2));
2352 Tmp3 = PromoteOp(Node->getOperand(2));
2356 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2360 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2362 // Length is too big, just take the lo-part of the length.
2364 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2368 Tmp4 = LegalizeOp(Node->getOperand(3));
2371 Tmp4 = PromoteOp(Node->getOperand(3));
2376 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2377 case Expand: assert(0 && "Cannot expand this yet!");
2379 Tmp5 = LegalizeOp(Node->getOperand(4));
2382 Tmp5 = PromoteOp(Node->getOperand(4));
2386 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2387 default: assert(0 && "This action not implemented for this operation!");
2388 case TargetLowering::Custom:
2391 case TargetLowering::Legal:
2392 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2394 Tmp1 = TLI.LowerOperation(Result, DAG);
2395 if (Tmp1.Val) Result = Tmp1;
2398 case TargetLowering::Expand: {
2399 // Otherwise, the target does not support this operation. Lower the
2400 // operation to an explicit libcall as appropriate.
2401 MVT::ValueType IntPtr = TLI.getPointerTy();
2402 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2403 TargetLowering::ArgListTy Args;
2404 TargetLowering::ArgListEntry Entry;
2406 const char *FnName = 0;
2407 if (Node->getOpcode() == ISD::MEMSET) {
2408 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2409 Args.push_back(Entry);
2410 // Extend the (previously legalized) ubyte argument to be an int value
2412 if (Tmp3.getValueType() > MVT::i32)
2413 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2415 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2416 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2417 Args.push_back(Entry);
2418 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2419 Args.push_back(Entry);
2422 } else if (Node->getOpcode() == ISD::MEMCPY ||
2423 Node->getOpcode() == ISD::MEMMOVE) {
2424 Entry.Ty = IntPtrTy;
2425 Entry.Node = Tmp2; Args.push_back(Entry);
2426 Entry.Node = Tmp3; Args.push_back(Entry);
2427 Entry.Node = Tmp4; Args.push_back(Entry);
2428 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2430 assert(0 && "Unknown op!");
2433 std::pair<SDOperand,SDOperand> CallResult =
2434 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2435 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2436 Result = CallResult.second;
2443 case ISD::SHL_PARTS:
2444 case ISD::SRA_PARTS:
2445 case ISD::SRL_PARTS: {
2446 SmallVector<SDOperand, 8> Ops;
2447 bool Changed = false;
2448 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2449 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2450 Changed |= Ops.back() != Node->getOperand(i);
2453 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2455 switch (TLI.getOperationAction(Node->getOpcode(),
2456 Node->getValueType(0))) {
2457 default: assert(0 && "This action is not supported yet!");
2458 case TargetLowering::Legal: break;
2459 case TargetLowering::Custom:
2460 Tmp1 = TLI.LowerOperation(Result, DAG);
2462 SDOperand Tmp2, RetVal(0, 0);
2463 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2464 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2465 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2469 assert(RetVal.Val && "Illegal result number");
2475 // Since these produce multiple values, make sure to remember that we
2476 // legalized all of them.
2477 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2478 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2479 return Result.getValue(Op.ResNo);
2500 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2501 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2502 case Expand: assert(0 && "Not possible");
2504 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2507 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2513 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2514 default: assert(0 && "BinOp legalize operation not supported");
2515 case TargetLowering::Legal: break;
2516 case TargetLowering::Custom:
2517 Tmp1 = TLI.LowerOperation(Result, DAG);
2518 if (Tmp1.Val) Result = Tmp1;
2520 case TargetLowering::Expand: {
2521 if (Node->getValueType(0) == MVT::i32) {
2522 switch (Node->getOpcode()) {
2523 default: assert(0 && "Do not know how to expand this integer BinOp!");
2526 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2527 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2529 bool isSigned = Node->getOpcode() == ISD::SDIV;
2530 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2535 assert(MVT::isVector(Node->getValueType(0)) &&
2536 "Cannot expand this binary operator!");
2537 // Expand the operation into a bunch of nasty scalar code.
2538 SmallVector<SDOperand, 8> Ops;
2539 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2540 MVT::ValueType PtrVT = TLI.getPointerTy();
2541 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2543 SDOperand Idx = DAG.getConstant(i, PtrVT);
2544 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2545 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2546 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2548 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2549 &Ops[0], Ops.size());
2552 case TargetLowering::Promote: {
2553 switch (Node->getOpcode()) {
2554 default: assert(0 && "Do not know how to promote this BinOp!");
2558 MVT::ValueType OVT = Node->getValueType(0);
2559 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2560 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2561 // Bit convert each of the values to the new type.
2562 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2563 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2564 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2565 // Bit convert the result back the original type.
2566 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2574 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2575 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2576 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2577 case Expand: assert(0 && "Not possible");
2579 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2582 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2586 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2588 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2589 default: assert(0 && "Operation not supported");
2590 case TargetLowering::Custom:
2591 Tmp1 = TLI.LowerOperation(Result, DAG);
2592 if (Tmp1.Val) Result = Tmp1;
2594 case TargetLowering::Legal: break;
2595 case TargetLowering::Expand: {
2596 // If this target supports fabs/fneg natively and select is cheap,
2597 // do this efficiently.
2598 if (!TLI.isSelectExpensive() &&
2599 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2600 TargetLowering::Legal &&
2601 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2602 TargetLowering::Legal) {
2603 // Get the sign bit of the RHS.
2604 MVT::ValueType IVT =
2605 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2606 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2607 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2608 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2609 // Get the absolute value of the result.
2610 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2611 // Select between the nabs and abs value based on the sign bit of
2613 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2614 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2617 Result = LegalizeOp(Result);
2621 // Otherwise, do bitwise ops!
2622 MVT::ValueType NVT =
2623 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2624 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2625 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2626 Result = LegalizeOp(Result);
2634 Tmp1 = LegalizeOp(Node->getOperand(0));
2635 Tmp2 = LegalizeOp(Node->getOperand(1));
2636 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2637 // Since this produces two values, make sure to remember that we legalized
2639 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2640 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2645 Tmp1 = LegalizeOp(Node->getOperand(0));
2646 Tmp2 = LegalizeOp(Node->getOperand(1));
2647 Tmp3 = LegalizeOp(Node->getOperand(2));
2648 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2649 // Since this produces two values, make sure to remember that we legalized
2651 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2652 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2655 case ISD::BUILD_PAIR: {
2656 MVT::ValueType PairTy = Node->getValueType(0);
2657 // TODO: handle the case where the Lo and Hi operands are not of legal type
2658 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2659 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2660 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2661 case TargetLowering::Promote:
2662 case TargetLowering::Custom:
2663 assert(0 && "Cannot promote/custom this yet!");
2664 case TargetLowering::Legal:
2665 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2666 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2668 case TargetLowering::Expand:
2669 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2670 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2671 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2672 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2673 TLI.getShiftAmountTy()));
2674 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2683 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2684 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2686 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2687 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2688 case TargetLowering::Custom:
2691 case TargetLowering::Legal:
2692 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2694 Tmp1 = TLI.LowerOperation(Result, DAG);
2695 if (Tmp1.Val) Result = Tmp1;
2698 case TargetLowering::Expand:
2699 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2700 bool isSigned = DivOpc == ISD::SDIV;
2701 if (MVT::isInteger(Node->getValueType(0))) {
2702 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2703 TargetLowering::Legal) {
2705 MVT::ValueType VT = Node->getValueType(0);
2706 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2707 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2708 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2710 assert(Node->getValueType(0) == MVT::i32 &&
2711 "Cannot expand this binary operator!");
2712 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2713 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2715 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2718 // Floating point mod -> fmod libcall.
2719 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2720 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2722 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2723 false/*sign irrelevant*/, Dummy);
2729 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2730 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2732 MVT::ValueType VT = Node->getValueType(0);
2733 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2734 default: assert(0 && "This action is not supported yet!");
2735 case TargetLowering::Custom:
2738 case TargetLowering::Legal:
2739 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2740 Result = Result.getValue(0);
2741 Tmp1 = Result.getValue(1);
2744 Tmp2 = TLI.LowerOperation(Result, DAG);
2746 Result = LegalizeOp(Tmp2);
2747 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2751 case TargetLowering::Expand: {
2752 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2753 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2754 SV->getValue(), SV->getOffset());
2755 // Increment the pointer, VAList, to the next vaarg
2756 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2757 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2758 TLI.getPointerTy()));
2759 // Store the incremented VAList to the legalized pointer
2760 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2762 // Load the actual argument out of the pointer VAList
2763 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2764 Tmp1 = LegalizeOp(Result.getValue(1));
2765 Result = LegalizeOp(Result);
2769 // Since VAARG produces two values, make sure to remember that we
2770 // legalized both of them.
2771 AddLegalizedOperand(SDOperand(Node, 0), Result);
2772 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2773 return Op.ResNo ? Tmp1 : Result;
2777 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2778 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2779 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2781 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2782 default: assert(0 && "This action is not supported yet!");
2783 case TargetLowering::Custom:
2786 case TargetLowering::Legal:
2787 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2788 Node->getOperand(3), Node->getOperand(4));
2790 Tmp1 = TLI.LowerOperation(Result, DAG);
2791 if (Tmp1.Val) Result = Tmp1;
2794 case TargetLowering::Expand:
2795 // This defaults to loading a pointer from the input and storing it to the
2796 // output, returning the chain.
2797 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2798 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2799 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2801 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2808 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2809 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2811 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2812 default: assert(0 && "This action is not supported yet!");
2813 case TargetLowering::Custom:
2816 case TargetLowering::Legal:
2817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2819 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2820 if (Tmp1.Val) Result = Tmp1;
2823 case TargetLowering::Expand:
2824 Result = Tmp1; // Default to a no-op, return the chain
2830 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2831 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2833 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2835 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2836 default: assert(0 && "This action is not supported yet!");
2837 case TargetLowering::Legal: break;
2838 case TargetLowering::Custom:
2839 Tmp1 = TLI.LowerOperation(Result, DAG);
2840 if (Tmp1.Val) Result = Tmp1;
2847 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2848 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2849 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2850 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2852 assert(0 && "ROTL/ROTR legalize operation not supported");
2854 case TargetLowering::Legal:
2856 case TargetLowering::Custom:
2857 Tmp1 = TLI.LowerOperation(Result, DAG);
2858 if (Tmp1.Val) Result = Tmp1;
2860 case TargetLowering::Promote:
2861 assert(0 && "Do not know how to promote ROTL/ROTR");
2863 case TargetLowering::Expand:
2864 assert(0 && "Do not know how to expand ROTL/ROTR");
2870 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2871 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2872 case TargetLowering::Custom:
2873 assert(0 && "Cannot custom legalize this yet!");
2874 case TargetLowering::Legal:
2875 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2877 case TargetLowering::Promote: {
2878 MVT::ValueType OVT = Tmp1.getValueType();
2879 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2880 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2882 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2883 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2884 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2885 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2888 case TargetLowering::Expand:
2889 Result = ExpandBSWAP(Tmp1);
2897 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2898 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2899 case TargetLowering::Custom:
2900 case TargetLowering::Legal:
2901 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2902 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
2903 TargetLowering::Custom) {
2904 Tmp1 = TLI.LowerOperation(Result, DAG);
2910 case TargetLowering::Promote: {
2911 MVT::ValueType OVT = Tmp1.getValueType();
2912 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2914 // Zero extend the argument.
2915 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2916 // Perform the larger operation, then subtract if needed.
2917 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2918 switch (Node->getOpcode()) {
2923 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2924 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2925 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2927 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2928 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2931 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2932 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2933 DAG.getConstant(MVT::getSizeInBits(NVT) -
2934 MVT::getSizeInBits(OVT), NVT));
2939 case TargetLowering::Expand:
2940 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2951 Tmp1 = LegalizeOp(Node->getOperand(0));
2952 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2953 case TargetLowering::Promote:
2954 case TargetLowering::Custom:
2957 case TargetLowering::Legal:
2958 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2960 Tmp1 = TLI.LowerOperation(Result, DAG);
2961 if (Tmp1.Val) Result = Tmp1;
2964 case TargetLowering::Expand:
2965 switch (Node->getOpcode()) {
2966 default: assert(0 && "Unreachable!");
2968 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2969 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2970 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2973 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2974 MVT::ValueType VT = Node->getValueType(0);
2975 Tmp2 = DAG.getConstantFP(0.0, VT);
2976 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2977 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2978 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2984 MVT::ValueType VT = Node->getValueType(0);
2985 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2986 switch(Node->getOpcode()) {
2988 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2991 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2994 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2996 default: assert(0 && "Unreachable!");
2999 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3000 false/*sign irrelevant*/, Dummy);
3008 // We always lower FPOWI into a libcall. No target support it yet.
3009 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
3010 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
3012 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3013 false/*sign irrelevant*/, Dummy);
3016 case ISD::BIT_CONVERT:
3017 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3018 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3019 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3020 // The input has to be a vector type, we have to either scalarize it, pack
3021 // it, or convert it based on whether the input vector type is legal.
3022 SDNode *InVal = Node->getOperand(0).Val;
3023 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3024 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3026 // Figure out if there is a simple type corresponding to this Vector
3027 // type. If so, convert to the vector type.
3028 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3029 if (TLI.isTypeLegal(TVT)) {
3030 // Turn this into a bit convert of the vector input.
3031 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3032 LegalizeOp(Node->getOperand(0)));
3034 } else if (NumElems == 1) {
3035 // Turn this into a bit convert of the scalar input.
3036 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3037 ScalarizeVectorOp(Node->getOperand(0)));
3040 // FIXME: UNIMP! Store then reload
3041 assert(0 && "Cast from unsupported vector type not implemented yet!");
3044 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3045 Node->getOperand(0).getValueType())) {
3046 default: assert(0 && "Unknown operation action!");
3047 case TargetLowering::Expand:
3048 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3050 case TargetLowering::Legal:
3051 Tmp1 = LegalizeOp(Node->getOperand(0));
3052 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3058 // Conversion operators. The source and destination have different types.
3059 case ISD::SINT_TO_FP:
3060 case ISD::UINT_TO_FP: {
3061 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3062 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3064 switch (TLI.getOperationAction(Node->getOpcode(),
3065 Node->getOperand(0).getValueType())) {
3066 default: assert(0 && "Unknown operation action!");
3067 case TargetLowering::Custom:
3070 case TargetLowering::Legal:
3071 Tmp1 = LegalizeOp(Node->getOperand(0));
3072 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3074 Tmp1 = TLI.LowerOperation(Result, DAG);
3075 if (Tmp1.Val) Result = Tmp1;
3078 case TargetLowering::Expand:
3079 Result = ExpandLegalINT_TO_FP(isSigned,
3080 LegalizeOp(Node->getOperand(0)),
3081 Node->getValueType(0));
3083 case TargetLowering::Promote:
3084 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3085 Node->getValueType(0),
3091 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3092 Node->getValueType(0), Node->getOperand(0));
3095 Tmp1 = PromoteOp(Node->getOperand(0));
3097 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3098 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3100 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3101 Node->getOperand(0).getValueType());
3103 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3104 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3110 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3112 Tmp1 = LegalizeOp(Node->getOperand(0));
3113 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3116 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3118 // Since the result is legal, we should just be able to truncate the low
3119 // part of the source.
3120 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3123 Result = PromoteOp(Node->getOperand(0));
3124 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3129 case ISD::FP_TO_SINT:
3130 case ISD::FP_TO_UINT:
3131 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3133 Tmp1 = LegalizeOp(Node->getOperand(0));
3135 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3136 default: assert(0 && "Unknown operation action!");
3137 case TargetLowering::Custom:
3140 case TargetLowering::Legal:
3141 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3143 Tmp1 = TLI.LowerOperation(Result, DAG);
3144 if (Tmp1.Val) Result = Tmp1;
3147 case TargetLowering::Promote:
3148 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3149 Node->getOpcode() == ISD::FP_TO_SINT);
3151 case TargetLowering::Expand:
3152 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3153 SDOperand True, False;
3154 MVT::ValueType VT = Node->getOperand(0).getValueType();
3155 MVT::ValueType NVT = Node->getValueType(0);
3156 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
3157 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
3158 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3159 Node->getOperand(0), Tmp2, ISD::SETLT);
3160 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3161 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3162 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3164 False = DAG.getNode(ISD::XOR, NVT, False,
3165 DAG.getConstant(1ULL << ShiftAmt, NVT));
3166 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3169 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3175 // Convert f32 / f64 to i32 / i64.
3176 MVT::ValueType VT = Op.getValueType();
3177 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3178 switch (Node->getOpcode()) {
3179 case ISD::FP_TO_SINT:
3180 if (Node->getOperand(0).getValueType() == MVT::f32)
3181 LC = (VT == MVT::i32)
3182 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3184 LC = (VT == MVT::i32)
3185 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3187 case ISD::FP_TO_UINT:
3188 if (Node->getOperand(0).getValueType() == MVT::f32)
3189 LC = (VT == MVT::i32)
3190 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3192 LC = (VT == MVT::i32)
3193 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3195 default: assert(0 && "Unreachable!");
3198 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3199 false/*sign irrelevant*/, Dummy);
3203 Tmp1 = PromoteOp(Node->getOperand(0));
3204 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3205 Result = LegalizeOp(Result);
3210 case ISD::FP_EXTEND:
3211 case ISD::FP_ROUND: {
3212 MVT::ValueType newVT = Op.getValueType();
3213 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3214 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3215 // The only way we can lower this is to turn it into a STORE,
3216 // LOAD pair, targetting a temporary location (a stack slot).
3218 // NOTE: there is a choice here between constantly creating new stack
3219 // slots and always reusing the same one. We currently always create
3220 // new ones, as reuse may inhibit scheduling.
3221 MVT::ValueType slotVT =
3222 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3223 const Type *Ty = MVT::getTypeForValueType(slotVT);
3224 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3225 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3226 MachineFunction &MF = DAG.getMachineFunction();
3228 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3229 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3230 if (Node->getOpcode() == ISD::FP_EXTEND) {
3231 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3232 StackSlot, NULL, 0);
3233 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3234 Result, StackSlot, NULL, 0, oldVT);
3236 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3237 StackSlot, NULL, 0, newVT);
3238 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
3244 case ISD::ANY_EXTEND:
3245 case ISD::ZERO_EXTEND:
3246 case ISD::SIGN_EXTEND:
3247 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3248 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3250 Tmp1 = LegalizeOp(Node->getOperand(0));
3251 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3254 switch (Node->getOpcode()) {
3255 case ISD::ANY_EXTEND:
3256 Tmp1 = PromoteOp(Node->getOperand(0));
3257 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3259 case ISD::ZERO_EXTEND:
3260 Result = PromoteOp(Node->getOperand(0));
3261 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3262 Result = DAG.getZeroExtendInReg(Result,
3263 Node->getOperand(0).getValueType());
3265 case ISD::SIGN_EXTEND:
3266 Result = PromoteOp(Node->getOperand(0));
3267 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3268 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3270 DAG.getValueType(Node->getOperand(0).getValueType()));
3272 case ISD::FP_EXTEND:
3273 Result = PromoteOp(Node->getOperand(0));
3274 if (Result.getValueType() != Op.getValueType())
3275 // Dynamically dead while we have only 2 FP types.
3276 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3279 Result = PromoteOp(Node->getOperand(0));
3280 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3285 case ISD::FP_ROUND_INREG:
3286 case ISD::SIGN_EXTEND_INREG: {
3287 Tmp1 = LegalizeOp(Node->getOperand(0));
3288 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3290 // If this operation is not supported, convert it to a shl/shr or load/store
3292 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3293 default: assert(0 && "This action not supported for this op yet!");
3294 case TargetLowering::Legal:
3295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3297 case TargetLowering::Expand:
3298 // If this is an integer extend and shifts are supported, do that.
3299 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3300 // NOTE: we could fall back on load/store here too for targets without
3301 // SAR. However, it is doubtful that any exist.
3302 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3303 MVT::getSizeInBits(ExtraVT);
3304 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3305 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3306 Node->getOperand(0), ShiftCst);
3307 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3309 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3310 // The only way we can lower this is to turn it into a TRUNCSTORE,
3311 // EXTLOAD pair, targetting a temporary location (a stack slot).
3313 // NOTE: there is a choice here between constantly creating new stack
3314 // slots and always reusing the same one. We currently always create
3315 // new ones, as reuse may inhibit scheduling.
3316 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3317 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3318 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3319 MachineFunction &MF = DAG.getMachineFunction();
3321 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3322 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3323 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3324 StackSlot, NULL, 0, ExtraVT);
3325 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3326 Result, StackSlot, NULL, 0, ExtraVT);
3328 assert(0 && "Unknown op");
3334 case ISD::ADJUST_TRAMP: {
3335 Tmp1 = LegalizeOp(Node->getOperand(0));
3336 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3337 default: assert(0 && "This action is not supported yet!");
3338 case TargetLowering::Custom:
3339 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3340 Result = TLI.LowerOperation(Result, DAG);
3341 if (Result.Val) break;
3343 case TargetLowering::Expand:
3349 case ISD::TRAMPOLINE: {
3351 for (unsigned i = 0; i != 6; ++i)
3352 Ops[i] = LegalizeOp(Node->getOperand(i));
3353 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3354 // The only option for this node is to custom lower it.
3355 Result = TLI.LowerOperation(Result, DAG);
3356 assert(Result.Val && "Should always custom lower!");
3361 assert(Result.getValueType() == Op.getValueType() &&
3362 "Bad legalization!");
3364 // Make sure that the generated code is itself legal.
3366 Result = LegalizeOp(Result);
3368 // Note that LegalizeOp may be reentered even from single-use nodes, which
3369 // means that we always must cache transformed nodes.
3370 AddLegalizedOperand(Op, Result);
3374 /// PromoteOp - Given an operation that produces a value in an invalid type,
3375 /// promote it to compute the value into a larger type. The produced value will
3376 /// have the correct bits for the low portion of the register, but no guarantee
3377 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3378 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3379 MVT::ValueType VT = Op.getValueType();
3380 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3381 assert(getTypeAction(VT) == Promote &&
3382 "Caller should expand or legalize operands that are not promotable!");
3383 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3384 "Cannot promote to smaller type!");
3386 SDOperand Tmp1, Tmp2, Tmp3;
3388 SDNode *Node = Op.Val;
3390 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3391 if (I != PromotedNodes.end()) return I->second;
3393 switch (Node->getOpcode()) {
3394 case ISD::CopyFromReg:
3395 assert(0 && "CopyFromReg must be legal!");
3398 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3400 assert(0 && "Do not know how to promote this operator!");
3403 Result = DAG.getNode(ISD::UNDEF, NVT);
3407 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3409 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3410 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3412 case ISD::ConstantFP:
3413 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3414 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3418 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3419 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3420 Node->getOperand(1), Node->getOperand(2));
3424 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3426 Result = LegalizeOp(Node->getOperand(0));
3427 assert(Result.getValueType() >= NVT &&
3428 "This truncation doesn't make sense!");
3429 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3430 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3433 // The truncation is not required, because we don't guarantee anything
3434 // about high bits anyway.
3435 Result = PromoteOp(Node->getOperand(0));
3438 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3439 // Truncate the low part of the expanded value to the result type
3440 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3443 case ISD::SIGN_EXTEND:
3444 case ISD::ZERO_EXTEND:
3445 case ISD::ANY_EXTEND:
3446 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3447 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3449 // Input is legal? Just do extend all the way to the larger type.
3450 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3453 // Promote the reg if it's smaller.
3454 Result = PromoteOp(Node->getOperand(0));
3455 // The high bits are not guaranteed to be anything. Insert an extend.
3456 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3457 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3458 DAG.getValueType(Node->getOperand(0).getValueType()));
3459 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3460 Result = DAG.getZeroExtendInReg(Result,
3461 Node->getOperand(0).getValueType());
3465 case ISD::BIT_CONVERT:
3466 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3467 Result = PromoteOp(Result);
3470 case ISD::FP_EXTEND:
3471 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3473 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3474 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3475 case Promote: assert(0 && "Unreachable with 2 FP types!");
3477 // Input is legal? Do an FP_ROUND_INREG.
3478 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3479 DAG.getValueType(VT));
3484 case ISD::SINT_TO_FP:
3485 case ISD::UINT_TO_FP:
3486 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3488 // No extra round required here.
3489 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3493 Result = PromoteOp(Node->getOperand(0));
3494 if (Node->getOpcode() == ISD::SINT_TO_FP)
3495 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3497 DAG.getValueType(Node->getOperand(0).getValueType()));
3499 Result = DAG.getZeroExtendInReg(Result,
3500 Node->getOperand(0).getValueType());
3501 // No extra round required here.
3502 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3505 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3506 Node->getOperand(0));
3507 // Round if we cannot tolerate excess precision.
3508 if (NoExcessFPPrecision)
3509 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3510 DAG.getValueType(VT));
3515 case ISD::SIGN_EXTEND_INREG:
3516 Result = PromoteOp(Node->getOperand(0));
3517 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3518 Node->getOperand(1));
3520 case ISD::FP_TO_SINT:
3521 case ISD::FP_TO_UINT:
3522 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3525 Tmp1 = Node->getOperand(0);
3528 // The input result is prerounded, so we don't have to do anything
3530 Tmp1 = PromoteOp(Node->getOperand(0));
3533 // If we're promoting a UINT to a larger size, check to see if the new node
3534 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3535 // we can use that instead. This allows us to generate better code for
3536 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3537 // legal, such as PowerPC.
3538 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3539 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3540 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3541 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3542 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3544 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3550 Tmp1 = PromoteOp(Node->getOperand(0));
3551 assert(Tmp1.getValueType() == NVT);
3552 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3553 // NOTE: we do not have to do any extra rounding here for
3554 // NoExcessFPPrecision, because we know the input will have the appropriate
3555 // precision, and these operations don't modify precision at all.
3561 Tmp1 = PromoteOp(Node->getOperand(0));
3562 assert(Tmp1.getValueType() == NVT);
3563 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3564 if (NoExcessFPPrecision)
3565 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3566 DAG.getValueType(VT));
3570 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3571 // directly as well, which may be better.
3572 Tmp1 = PromoteOp(Node->getOperand(0));
3573 assert(Tmp1.getValueType() == NVT);
3574 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3575 if (NoExcessFPPrecision)
3576 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3577 DAG.getValueType(VT));
3587 // The input may have strange things in the top bits of the registers, but
3588 // these operations don't care. They may have weird bits going out, but
3589 // that too is okay if they are integer operations.
3590 Tmp1 = PromoteOp(Node->getOperand(0));
3591 Tmp2 = PromoteOp(Node->getOperand(1));
3592 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3593 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3598 Tmp1 = PromoteOp(Node->getOperand(0));
3599 Tmp2 = PromoteOp(Node->getOperand(1));
3600 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3601 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3603 // Floating point operations will give excess precision that we may not be
3604 // able to tolerate. If we DO allow excess precision, just leave it,
3605 // otherwise excise it.
3606 // FIXME: Why would we need to round FP ops more than integer ones?
3607 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3608 if (NoExcessFPPrecision)
3609 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3610 DAG.getValueType(VT));
3615 // These operators require that their input be sign extended.
3616 Tmp1 = PromoteOp(Node->getOperand(0));
3617 Tmp2 = PromoteOp(Node->getOperand(1));
3618 if (MVT::isInteger(NVT)) {
3619 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3620 DAG.getValueType(VT));
3621 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3622 DAG.getValueType(VT));
3624 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3626 // Perform FP_ROUND: this is probably overly pessimistic.
3627 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3628 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3629 DAG.getValueType(VT));
3633 case ISD::FCOPYSIGN:
3634 // These operators require that their input be fp extended.
3635 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3637 Tmp1 = LegalizeOp(Node->getOperand(0));
3640 Tmp1 = PromoteOp(Node->getOperand(0));
3643 assert(0 && "not implemented");
3645 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3647 Tmp2 = LegalizeOp(Node->getOperand(1));
3650 Tmp2 = PromoteOp(Node->getOperand(1));
3653 assert(0 && "not implemented");
3655 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3657 // Perform FP_ROUND: this is probably overly pessimistic.
3658 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3659 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3660 DAG.getValueType(VT));
3665 // These operators require that their input be zero extended.
3666 Tmp1 = PromoteOp(Node->getOperand(0));
3667 Tmp2 = PromoteOp(Node->getOperand(1));
3668 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3669 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3670 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3671 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3675 Tmp1 = PromoteOp(Node->getOperand(0));
3676 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3679 // The input value must be properly sign extended.
3680 Tmp1 = PromoteOp(Node->getOperand(0));
3681 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3682 DAG.getValueType(VT));
3683 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3686 // The input value must be properly zero extended.
3687 Tmp1 = PromoteOp(Node->getOperand(0));
3688 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3689 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3693 Tmp1 = Node->getOperand(0); // Get the chain.
3694 Tmp2 = Node->getOperand(1); // Get the pointer.
3695 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3696 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3697 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3699 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3700 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3701 SV->getValue(), SV->getOffset());
3702 // Increment the pointer, VAList, to the next vaarg
3703 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3704 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3705 TLI.getPointerTy()));
3706 // Store the incremented VAList to the legalized pointer
3707 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3709 // Load the actual argument out of the pointer VAList
3710 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3712 // Remember that we legalized the chain.
3713 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3717 LoadSDNode *LD = cast<LoadSDNode>(Node);
3718 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3719 ? ISD::EXTLOAD : LD->getExtensionType();
3720 Result = DAG.getExtLoad(ExtType, NVT,
3721 LD->getChain(), LD->getBasePtr(),
3722 LD->getSrcValue(), LD->getSrcValueOffset(),
3725 LD->getAlignment());
3726 // Remember that we legalized the chain.
3727 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3731 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3732 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3733 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3735 case ISD::SELECT_CC:
3736 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3737 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3738 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3739 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3742 Tmp1 = Node->getOperand(0);
3743 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3744 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3745 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3746 DAG.getConstant(MVT::getSizeInBits(NVT) -
3747 MVT::getSizeInBits(VT),
3748 TLI.getShiftAmountTy()));
3753 // Zero extend the argument
3754 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3755 // Perform the larger operation, then subtract if needed.
3756 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3757 switch(Node->getOpcode()) {
3762 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3763 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3764 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3766 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3767 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3770 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3771 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3772 DAG.getConstant(MVT::getSizeInBits(NVT) -
3773 MVT::getSizeInBits(VT), NVT));
3777 case ISD::EXTRACT_SUBVECTOR:
3778 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3780 case ISD::EXTRACT_VECTOR_ELT:
3781 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3785 assert(Result.Val && "Didn't set a result!");
3787 // Make sure the result is itself legal.
3788 Result = LegalizeOp(Result);
3790 // Remember that we promoted this!
3791 AddPromotedOperand(Op, Result);
3795 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3796 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3797 /// based on the vector type. The return type of this matches the element type
3798 /// of the vector, which may not be legal for the target.
3799 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3800 // We know that operand #0 is the Vec vector. If the index is a constant
3801 // or if the invec is a supported hardware type, we can use it. Otherwise,
3802 // lower to a store then an indexed load.
3803 SDOperand Vec = Op.getOperand(0);
3804 SDOperand Idx = Op.getOperand(1);
3806 SDNode *InVal = Vec.Val;
3807 MVT::ValueType TVT = InVal->getValueType(0);
3808 unsigned NumElems = MVT::getVectorNumElements(TVT);
3810 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3811 default: assert(0 && "This action is not supported yet!");
3812 case TargetLowering::Custom: {
3813 Vec = LegalizeOp(Vec);
3814 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3815 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3820 case TargetLowering::Legal:
3821 if (isTypeLegal(TVT)) {
3822 Vec = LegalizeOp(Vec);
3823 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3827 case TargetLowering::Expand:
3831 if (NumElems == 1) {
3832 // This must be an access of the only element. Return it.
3833 Op = ScalarizeVectorOp(Vec);
3834 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3835 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3837 SplitVectorOp(Vec, Lo, Hi);
3838 if (CIdx->getValue() < NumElems/2) {
3842 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3843 Idx.getValueType());
3846 // It's now an extract from the appropriate high or low part. Recurse.
3847 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3848 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3850 // Store the value to a temporary stack slot, then LOAD the scalar
3851 // element back out.
3852 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3853 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3855 // Add the offset to the index.
3856 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3857 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3858 DAG.getConstant(EltSize, Idx.getValueType()));
3859 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3861 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3866 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3867 /// we assume the operation can be split if it is not already legal.
3868 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3869 // We know that operand #0 is the Vec vector. For now we assume the index
3870 // is a constant and that the extracted result is a supported hardware type.
3871 SDOperand Vec = Op.getOperand(0);
3872 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3874 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3876 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3877 // This must be an access of the desired vector length. Return it.
3881 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3883 SplitVectorOp(Vec, Lo, Hi);
3884 if (CIdx->getValue() < NumElems/2) {
3888 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3891 // It's now an extract from the appropriate high or low part. Recurse.
3892 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3893 return ExpandEXTRACT_SUBVECTOR(Op);
3896 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3897 /// with condition CC on the current target. This usually involves legalizing
3898 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3899 /// there may be no choice but to create a new SetCC node to represent the
3900 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3901 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3902 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3905 SDOperand Tmp1, Tmp2, Result;
3907 switch (getTypeAction(LHS.getValueType())) {
3909 Tmp1 = LegalizeOp(LHS); // LHS
3910 Tmp2 = LegalizeOp(RHS); // RHS
3913 Tmp1 = PromoteOp(LHS); // LHS
3914 Tmp2 = PromoteOp(RHS); // RHS
3916 // If this is an FP compare, the operands have already been extended.
3917 if (MVT::isInteger(LHS.getValueType())) {
3918 MVT::ValueType VT = LHS.getValueType();
3919 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3921 // Otherwise, we have to insert explicit sign or zero extends. Note
3922 // that we could insert sign extends for ALL conditions, but zero extend
3923 // is cheaper on many machines (an AND instead of two shifts), so prefer
3925 switch (cast<CondCodeSDNode>(CC)->get()) {
3926 default: assert(0 && "Unknown integer comparison!");
3933 // ALL of these operations will work if we either sign or zero extend
3934 // the operands (including the unsigned comparisons!). Zero extend is
3935 // usually a simpler/cheaper operation, so prefer it.
3936 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3937 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3943 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3944 DAG.getValueType(VT));
3945 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3946 DAG.getValueType(VT));
3952 MVT::ValueType VT = LHS.getValueType();
3953 if (VT == MVT::f32 || VT == MVT::f64) {
3954 // Expand into one or more soft-fp libcall(s).
3955 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3956 switch (cast<CondCodeSDNode>(CC)->get()) {
3959 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3963 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3967 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3971 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3975 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3979 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3982 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3985 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3988 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3989 switch (cast<CondCodeSDNode>(CC)->get()) {
3991 // SETONE = SETOLT | SETOGT
3992 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3995 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3998 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4001 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4004 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4007 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4009 default: assert(0 && "Unsupported FP setcc!");
4014 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4015 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4016 false /*sign irrelevant*/, Dummy);
4017 Tmp2 = DAG.getConstant(0, MVT::i32);
4018 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4019 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4020 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4021 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4022 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4023 false /*sign irrelevant*/, Dummy);
4024 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4025 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4026 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4034 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4035 ExpandOp(LHS, LHSLo, LHSHi);
4036 ExpandOp(RHS, RHSLo, RHSHi);
4037 switch (cast<CondCodeSDNode>(CC)->get()) {
4041 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4042 if (RHSCST->isAllOnesValue()) {
4043 // Comparison to -1.
4044 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4049 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4050 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4051 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4052 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4055 // If this is a comparison of the sign bit, just look at the top part.
4057 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4058 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4059 CST->getValue() == 0) || // X < 0
4060 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4061 CST->isAllOnesValue())) { // X > -1
4067 // FIXME: This generated code sucks.
4068 ISD::CondCode LowCC;
4069 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4071 default: assert(0 && "Unknown integer setcc!");
4073 case ISD::SETULT: LowCC = ISD::SETULT; break;
4075 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4077 case ISD::SETULE: LowCC = ISD::SETULE; break;
4079 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4082 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4083 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4084 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4086 // NOTE: on targets without efficient SELECT of bools, we can always use
4087 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4088 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4089 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4090 false, DagCombineInfo);
4092 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4093 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4094 CCCode, false, DagCombineInfo);
4096 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
4098 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4099 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4100 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4101 (Tmp2C && Tmp2C->getValue() == 0 &&
4102 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4103 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4104 (Tmp2C && Tmp2C->getValue() == 1 &&
4105 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4106 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4107 // low part is known false, returns high part.
4108 // For LE / GE, if high part is known false, ignore the low part.
4109 // For LT / GT, if high part is known true, ignore the low part.
4113 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4114 ISD::SETEQ, false, DagCombineInfo);
4116 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4117 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4118 Result, Tmp1, Tmp2));
4129 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4130 /// The resultant code need not be legal. Note that SrcOp is the input operand
4131 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4132 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4134 // Create the stack frame object.
4135 SDOperand FIPtr = CreateStackTemporary(DestVT);
4137 // Emit a store to the stack slot.
4138 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4139 // Result is a load from the stack slot.
4140 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4143 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4144 // Create a vector sized/aligned stack slot, store the value to element #0,
4145 // then load the whole vector back out.
4146 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
4147 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4149 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4153 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4154 /// support the operation, but do support the resultant vector type.
4155 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4157 // If the only non-undef value is the low element, turn this into a
4158 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4159 unsigned NumElems = Node->getNumOperands();
4160 bool isOnlyLowElement = true;
4161 SDOperand SplatValue = Node->getOperand(0);
4162 std::map<SDOperand, std::vector<unsigned> > Values;
4163 Values[SplatValue].push_back(0);
4164 bool isConstant = true;
4165 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4166 SplatValue.getOpcode() != ISD::UNDEF)
4169 for (unsigned i = 1; i < NumElems; ++i) {
4170 SDOperand V = Node->getOperand(i);
4171 Values[V].push_back(i);
4172 if (V.getOpcode() != ISD::UNDEF)
4173 isOnlyLowElement = false;
4174 if (SplatValue != V)
4175 SplatValue = SDOperand(0,0);
4177 // If this isn't a constant element or an undef, we can't use a constant
4179 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4180 V.getOpcode() != ISD::UNDEF)
4184 if (isOnlyLowElement) {
4185 // If the low element is an undef too, then this whole things is an undef.
4186 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4187 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4188 // Otherwise, turn this into a scalar_to_vector node.
4189 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4190 Node->getOperand(0));
4193 // If all elements are constants, create a load from the constant pool.
4195 MVT::ValueType VT = Node->getValueType(0);
4197 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4198 std::vector<Constant*> CV;
4199 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4200 if (ConstantFPSDNode *V =
4201 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4202 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
4203 } else if (ConstantSDNode *V =
4204 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4205 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4207 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4208 CV.push_back(UndefValue::get(OpNTy));
4211 Constant *CP = ConstantVector::get(CV);
4212 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4213 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4216 if (SplatValue.Val) { // Splat of one value?
4217 // Build the shuffle constant vector: <0, 0, 0, 0>
4218 MVT::ValueType MaskVT =
4219 MVT::getIntVectorWithNumElements(NumElems);
4220 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4221 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4222 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4223 &ZeroVec[0], ZeroVec.size());
4225 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4226 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4227 // Get the splatted value into the low element of a vector register.
4228 SDOperand LowValVec =
4229 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4231 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4232 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4233 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4238 // If there are only two unique elements, we may be able to turn this into a
4240 if (Values.size() == 2) {
4241 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4242 MVT::ValueType MaskVT =
4243 MVT::getIntVectorWithNumElements(NumElems);
4244 std::vector<SDOperand> MaskVec(NumElems);
4246 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4247 E = Values.end(); I != E; ++I) {
4248 for (std::vector<unsigned>::iterator II = I->second.begin(),
4249 EE = I->second.end(); II != EE; ++II)
4250 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4253 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4254 &MaskVec[0], MaskVec.size());
4256 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4257 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4258 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4259 SmallVector<SDOperand, 8> Ops;
4260 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4261 E = Values.end(); I != E; ++I) {
4262 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4266 Ops.push_back(ShuffleMask);
4268 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4269 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4270 &Ops[0], Ops.size());
4274 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4275 // aligned object on the stack, store each element into it, then load
4276 // the result as a vector.
4277 MVT::ValueType VT = Node->getValueType(0);
4278 // Create the stack frame object.
4279 SDOperand FIPtr = CreateStackTemporary(VT);
4281 // Emit a store of each element to the stack slot.
4282 SmallVector<SDOperand, 8> Stores;
4283 unsigned TypeByteSize =
4284 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4285 // Store (in the right endianness) the elements to memory.
4286 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4287 // Ignore undef elements.
4288 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4290 unsigned Offset = TypeByteSize*i;
4292 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4293 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4295 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4299 SDOperand StoreChain;
4300 if (!Stores.empty()) // Not all undef elements?
4301 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4302 &Stores[0], Stores.size());
4304 StoreChain = DAG.getEntryNode();
4306 // Result is a load from the stack slot.
4307 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4310 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4311 /// specified value type.
4312 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4313 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4314 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4315 const Type *Ty = MVT::getTypeForValueType(VT);
4316 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4317 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4318 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4321 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4322 SDOperand Op, SDOperand Amt,
4323 SDOperand &Lo, SDOperand &Hi) {
4324 // Expand the subcomponents.
4325 SDOperand LHSL, LHSH;
4326 ExpandOp(Op, LHSL, LHSH);
4328 SDOperand Ops[] = { LHSL, LHSH, Amt };
4329 MVT::ValueType VT = LHSL.getValueType();
4330 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4331 Hi = Lo.getValue(1);
4335 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4336 /// smaller elements. If we can't find a way that is more efficient than a
4337 /// libcall on this target, return false. Otherwise, return true with the
4338 /// low-parts expanded into Lo and Hi.
4339 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4340 SDOperand &Lo, SDOperand &Hi) {
4341 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4342 "This is not a shift!");
4344 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4345 SDOperand ShAmt = LegalizeOp(Amt);
4346 MVT::ValueType ShTy = ShAmt.getValueType();
4347 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4348 unsigned NVTBits = MVT::getSizeInBits(NVT);
4350 // Handle the case when Amt is an immediate. Other cases are currently broken
4351 // and are disabled.
4352 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4353 unsigned Cst = CN->getValue();
4354 // Expand the incoming operand to be shifted, so that we have its parts
4356 ExpandOp(Op, InL, InH);
4360 Lo = DAG.getConstant(0, NVT);
4361 Hi = DAG.getConstant(0, NVT);
4362 } else if (Cst > NVTBits) {
4363 Lo = DAG.getConstant(0, NVT);
4364 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4365 } else if (Cst == NVTBits) {
4366 Lo = DAG.getConstant(0, NVT);
4369 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4370 Hi = DAG.getNode(ISD::OR, NVT,
4371 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4372 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4377 Lo = DAG.getConstant(0, NVT);
4378 Hi = DAG.getConstant(0, NVT);
4379 } else if (Cst > NVTBits) {
4380 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4381 Hi = DAG.getConstant(0, NVT);
4382 } else if (Cst == NVTBits) {
4384 Hi = DAG.getConstant(0, NVT);
4386 Lo = DAG.getNode(ISD::OR, NVT,
4387 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4388 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4389 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4394 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4395 DAG.getConstant(NVTBits-1, ShTy));
4396 } else if (Cst > NVTBits) {
4397 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4398 DAG.getConstant(Cst-NVTBits, ShTy));
4399 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4400 DAG.getConstant(NVTBits-1, ShTy));
4401 } else if (Cst == NVTBits) {
4403 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4404 DAG.getConstant(NVTBits-1, ShTy));
4406 Lo = DAG.getNode(ISD::OR, NVT,
4407 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4408 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4409 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4415 // Okay, the shift amount isn't constant. However, if we can tell that it is
4416 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4417 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4418 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4420 // If we know that the high bit of the shift amount is one, then we can do
4421 // this as a couple of simple shifts.
4422 if (KnownOne & Mask) {
4423 // Mask out the high bit, which we know is set.
4424 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4425 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4427 // Expand the incoming operand to be shifted, so that we have its parts
4429 ExpandOp(Op, InL, InH);
4432 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4433 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4436 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4437 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4440 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4441 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4442 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4447 // If we know that the high bit of the shift amount is zero, then we can do
4448 // this as a couple of simple shifts.
4449 if (KnownZero & Mask) {
4451 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4452 DAG.getConstant(NVTBits, Amt.getValueType()),
4455 // Expand the incoming operand to be shifted, so that we have its parts
4457 ExpandOp(Op, InL, InH);
4460 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4461 Hi = DAG.getNode(ISD::OR, NVT,
4462 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4463 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4466 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4467 Lo = DAG.getNode(ISD::OR, NVT,
4468 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4469 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4472 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4473 Lo = DAG.getNode(ISD::OR, NVT,
4474 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4475 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4484 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4485 // does not fit into a register, return the lo part and set the hi part to the
4486 // by-reg argument. If it does fit into a single register, return the result
4487 // and leave the Hi part unset.
4488 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4489 bool isSigned, SDOperand &Hi) {
4490 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4491 // The input chain to this libcall is the entry node of the function.
4492 // Legalizing the call will automatically add the previous call to the
4494 SDOperand InChain = DAG.getEntryNode();
4496 TargetLowering::ArgListTy Args;
4497 TargetLowering::ArgListEntry Entry;
4498 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4499 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4500 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4501 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4502 Entry.isSExt = isSigned;
4503 Args.push_back(Entry);
4505 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4507 // Splice the libcall in wherever FindInputOutputChains tells us to.
4508 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4509 std::pair<SDOperand,SDOperand> CallInfo =
4510 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4513 // Legalize the call sequence, starting with the chain. This will advance
4514 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4515 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4516 LegalizeOp(CallInfo.second);
4518 switch (getTypeAction(CallInfo.first.getValueType())) {
4519 default: assert(0 && "Unknown thing");
4521 Result = CallInfo.first;
4524 ExpandOp(CallInfo.first, Result, Hi);
4531 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4533 SDOperand SelectionDAGLegalize::
4534 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4535 assert(getTypeAction(Source.getValueType()) == Expand &&
4536 "This is not an expansion!");
4537 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4540 assert(Source.getValueType() == MVT::i64 &&
4541 "This only works for 64-bit -> FP");
4542 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4543 // incoming integer is set. To handle this, we dynamically test to see if
4544 // it is set, and, if so, add a fudge factor.
4546 ExpandOp(Source, Lo, Hi);
4548 // If this is unsigned, and not supported, first perform the conversion to
4549 // signed, then adjust the result if the sign bit is set.
4550 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4551 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4553 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4554 DAG.getConstant(0, Hi.getValueType()),
4556 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4557 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4558 SignSet, Four, Zero);
4559 uint64_t FF = 0x5f800000ULL;
4560 if (TLI.isLittleEndian()) FF <<= 32;
4561 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4563 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4564 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4565 SDOperand FudgeInReg;
4566 if (DestTy == MVT::f32)
4567 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4569 assert(DestTy == MVT::f64 && "Unexpected conversion");
4570 // FIXME: Avoid the extend by construction the right constantpool?
4571 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4572 CPIdx, NULL, 0, MVT::f32);
4574 MVT::ValueType SCVT = SignedConv.getValueType();
4575 if (SCVT != DestTy) {
4576 // Destination type needs to be expanded as well. The FADD now we are
4577 // constructing will be expanded into a libcall.
4578 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4579 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4580 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4581 SignedConv, SignedConv.getValue(1));
4583 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4585 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4588 // Check to see if the target has a custom way to lower this. If so, use it.
4589 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4590 default: assert(0 && "This action not implemented for this operation!");
4591 case TargetLowering::Legal:
4592 case TargetLowering::Expand:
4593 break; // This case is handled below.
4594 case TargetLowering::Custom: {
4595 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4598 return LegalizeOp(NV);
4599 break; // The target decided this was legal after all
4603 // Expand the source, then glue it back together for the call. We must expand
4604 // the source in case it is shared (this pass of legalize must traverse it).
4605 SDOperand SrcLo, SrcHi;
4606 ExpandOp(Source, SrcLo, SrcHi);
4607 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4610 if (DestTy == MVT::f32)
4611 LC = RTLIB::SINTTOFP_I64_F32;
4613 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4614 LC = RTLIB::SINTTOFP_I64_F64;
4617 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4618 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4619 SDOperand UnusedHiPart;
4620 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4624 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4625 /// INT_TO_FP operation of the specified operand when the target requests that
4626 /// we expand it. At this point, we know that the result and operand types are
4627 /// legal for the target.
4628 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4630 MVT::ValueType DestVT) {
4631 if (Op0.getValueType() == MVT::i32) {
4632 // simple 32-bit [signed|unsigned] integer to float/double expansion
4634 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4635 MachineFunction &MF = DAG.getMachineFunction();
4636 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4637 unsigned StackAlign =
4638 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4639 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4640 // get address of 8 byte buffer
4641 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4642 // word offset constant for Hi/Lo address computation
4643 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4644 // set up Hi and Lo (into buffer) address based on endian
4645 SDOperand Hi = StackSlot;
4646 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4647 if (TLI.isLittleEndian())
4650 // if signed map to unsigned space
4651 SDOperand Op0Mapped;
4653 // constant used to invert sign bit (signed to unsigned mapping)
4654 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4655 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4659 // store the lo of the constructed double - based on integer input
4660 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4661 Op0Mapped, Lo, NULL, 0);
4662 // initial hi portion of constructed double
4663 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4664 // store the hi of the constructed double - biased exponent
4665 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4666 // load the constructed double
4667 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4668 // FP constant to bias correct the final result
4669 SDOperand Bias = DAG.getConstantFP(isSigned ?
4670 BitsToDouble(0x4330000080000000ULL)
4671 : BitsToDouble(0x4330000000000000ULL),
4673 // subtract the bias
4674 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4677 // handle final rounding
4678 if (DestVT == MVT::f64) {
4682 // if f32 then cast to f32
4683 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4687 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4688 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4690 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4691 DAG.getConstant(0, Op0.getValueType()),
4693 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4694 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4695 SignSet, Four, Zero);
4697 // If the sign bit of the integer is set, the large number will be treated
4698 // as a negative number. To counteract this, the dynamic code adds an
4699 // offset depending on the data type.
4701 switch (Op0.getValueType()) {
4702 default: assert(0 && "Unsupported integer type!");
4703 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4704 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4705 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4706 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4708 if (TLI.isLittleEndian()) FF <<= 32;
4709 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4711 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4712 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4713 SDOperand FudgeInReg;
4714 if (DestVT == MVT::f32)
4715 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4717 assert(DestVT == MVT::f64 && "Unexpected conversion");
4718 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4719 DAG.getEntryNode(), CPIdx,
4720 NULL, 0, MVT::f32));
4723 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4726 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4727 /// *INT_TO_FP operation of the specified operand when the target requests that
4728 /// we promote it. At this point, we know that the result and operand types are
4729 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4730 /// operation that takes a larger input.
4731 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4732 MVT::ValueType DestVT,
4734 // First step, figure out the appropriate *INT_TO_FP operation to use.
4735 MVT::ValueType NewInTy = LegalOp.getValueType();
4737 unsigned OpToUse = 0;
4739 // Scan for the appropriate larger type to use.
4741 NewInTy = (MVT::ValueType)(NewInTy+1);
4742 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4744 // If the target supports SINT_TO_FP of this type, use it.
4745 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4747 case TargetLowering::Legal:
4748 if (!TLI.isTypeLegal(NewInTy))
4749 break; // Can't use this datatype.
4751 case TargetLowering::Custom:
4752 OpToUse = ISD::SINT_TO_FP;
4756 if (isSigned) continue;
4758 // If the target supports UINT_TO_FP of this type, use it.
4759 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4761 case TargetLowering::Legal:
4762 if (!TLI.isTypeLegal(NewInTy))
4763 break; // Can't use this datatype.
4765 case TargetLowering::Custom:
4766 OpToUse = ISD::UINT_TO_FP;
4771 // Otherwise, try a larger type.
4774 // Okay, we found the operation and type to use. Zero extend our input to the
4775 // desired type then run the operation on it.
4776 return DAG.getNode(OpToUse, DestVT,
4777 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4781 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4782 /// FP_TO_*INT operation of the specified operand when the target requests that
4783 /// we promote it. At this point, we know that the result and operand types are
4784 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4785 /// operation that returns a larger result.
4786 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4787 MVT::ValueType DestVT,
4789 // First step, figure out the appropriate FP_TO*INT operation to use.
4790 MVT::ValueType NewOutTy = DestVT;
4792 unsigned OpToUse = 0;
4794 // Scan for the appropriate larger type to use.
4796 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4797 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4799 // If the target supports FP_TO_SINT returning this type, use it.
4800 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4802 case TargetLowering::Legal:
4803 if (!TLI.isTypeLegal(NewOutTy))
4804 break; // Can't use this datatype.
4806 case TargetLowering::Custom:
4807 OpToUse = ISD::FP_TO_SINT;
4812 // If the target supports FP_TO_UINT of this type, use it.
4813 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4815 case TargetLowering::Legal:
4816 if (!TLI.isTypeLegal(NewOutTy))
4817 break; // Can't use this datatype.
4819 case TargetLowering::Custom:
4820 OpToUse = ISD::FP_TO_UINT;
4825 // Otherwise, try a larger type.
4828 // Okay, we found the operation and type to use. Truncate the result of the
4829 // extended FP_TO_*INT operation to the desired size.
4830 return DAG.getNode(ISD::TRUNCATE, DestVT,
4831 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4834 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4836 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4837 MVT::ValueType VT = Op.getValueType();
4838 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4839 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4841 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4843 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4844 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4845 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4847 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4848 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4849 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4850 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4851 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4852 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4853 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4854 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4855 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4857 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4858 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4859 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4860 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4861 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4862 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4863 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4864 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4865 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4866 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4867 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4868 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4869 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4870 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4871 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4872 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4873 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4874 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4875 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4876 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4877 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4881 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4883 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4885 default: assert(0 && "Cannot expand this yet!");
4887 static const uint64_t mask[6] = {
4888 0x5555555555555555ULL, 0x3333333333333333ULL,
4889 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4890 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4892 MVT::ValueType VT = Op.getValueType();
4893 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4894 unsigned len = MVT::getSizeInBits(VT);
4895 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4896 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4897 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4898 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4899 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4900 DAG.getNode(ISD::AND, VT,
4901 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4906 // for now, we do this:
4907 // x = x | (x >> 1);
4908 // x = x | (x >> 2);
4910 // x = x | (x >>16);
4911 // x = x | (x >>32); // for 64-bit input
4912 // return popcount(~x);
4914 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4915 MVT::ValueType VT = Op.getValueType();
4916 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4917 unsigned len = MVT::getSizeInBits(VT);
4918 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4919 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4920 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4922 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4923 return DAG.getNode(ISD::CTPOP, VT, Op);
4926 // for now, we use: { return popcount(~x & (x - 1)); }
4927 // unless the target has ctlz but not ctpop, in which case we use:
4928 // { return 32 - nlz(~x & (x-1)); }
4929 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4930 MVT::ValueType VT = Op.getValueType();
4931 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4932 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4933 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4934 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4935 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4936 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4937 TLI.isOperationLegal(ISD::CTLZ, VT))
4938 return DAG.getNode(ISD::SUB, VT,
4939 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4940 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4941 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4946 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4947 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4948 /// LegalizeNodes map is filled in for any results that are not expanded, the
4949 /// ExpandedNodes map is filled in for any results that are expanded, and the
4950 /// Lo/Hi values are returned.
4951 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4952 MVT::ValueType VT = Op.getValueType();
4953 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4954 SDNode *Node = Op.Val;
4955 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4956 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4957 MVT::isVector(VT)) &&
4958 "Cannot expand to FP value or to larger int value!");
4960 // See if we already expanded it.
4961 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4962 = ExpandedNodes.find(Op);
4963 if (I != ExpandedNodes.end()) {
4964 Lo = I->second.first;
4965 Hi = I->second.second;
4969 switch (Node->getOpcode()) {
4970 case ISD::CopyFromReg:
4971 assert(0 && "CopyFromReg must be legal!");
4974 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4976 assert(0 && "Do not know how to expand this operator!");
4979 NVT = TLI.getTypeToExpandTo(VT);
4980 Lo = DAG.getNode(ISD::UNDEF, NVT);
4981 Hi = DAG.getNode(ISD::UNDEF, NVT);
4983 case ISD::Constant: {
4984 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4985 Lo = DAG.getConstant(Cst, NVT);
4986 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4989 case ISD::ConstantFP: {
4990 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4991 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4992 if (getTypeAction(Lo.getValueType()) == Expand)
4993 ExpandOp(Lo, Lo, Hi);
4996 case ISD::BUILD_PAIR:
4997 // Return the operands.
4998 Lo = Node->getOperand(0);
4999 Hi = Node->getOperand(1);
5002 case ISD::SIGN_EXTEND_INREG:
5003 ExpandOp(Node->getOperand(0), Lo, Hi);
5004 // sext_inreg the low part if needed.
5005 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5007 // The high part gets the sign extension from the lo-part. This handles
5008 // things like sextinreg V:i64 from i8.
5009 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5010 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5011 TLI.getShiftAmountTy()));
5015 ExpandOp(Node->getOperand(0), Lo, Hi);
5016 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5017 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5023 ExpandOp(Node->getOperand(0), Lo, Hi);
5024 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5025 DAG.getNode(ISD::CTPOP, NVT, Lo),
5026 DAG.getNode(ISD::CTPOP, NVT, Hi));
5027 Hi = DAG.getConstant(0, NVT);
5031 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5032 ExpandOp(Node->getOperand(0), Lo, Hi);
5033 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5034 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5035 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5037 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5038 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5040 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5041 Hi = DAG.getConstant(0, NVT);
5046 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5047 ExpandOp(Node->getOperand(0), Lo, Hi);
5048 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5049 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5050 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5052 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5053 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5055 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5056 Hi = DAG.getConstant(0, NVT);
5061 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5062 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5063 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5064 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5066 // Remember that we legalized the chain.
5067 Hi = LegalizeOp(Hi);
5068 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5069 if (!TLI.isLittleEndian())
5075 LoadSDNode *LD = cast<LoadSDNode>(Node);
5076 SDOperand Ch = LD->getChain(); // Legalize the chain.
5077 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5078 ISD::LoadExtType ExtType = LD->getExtensionType();
5079 int SVOffset = LD->getSrcValueOffset();
5080 unsigned Alignment = LD->getAlignment();
5081 bool isVolatile = LD->isVolatile();
5083 if (ExtType == ISD::NON_EXTLOAD) {
5084 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5085 isVolatile, Alignment);
5086 if (VT == MVT::f32 || VT == MVT::f64) {
5087 // f32->i32 or f64->i64 one to one expansion.
5088 // Remember that we legalized the chain.
5089 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5090 // Recursively expand the new load.
5091 if (getTypeAction(NVT) == Expand)
5092 ExpandOp(Lo, Lo, Hi);
5096 // Increment the pointer to the other half.
5097 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5098 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5099 getIntPtrConstant(IncrementSize));
5100 SVOffset += IncrementSize;
5101 if (Alignment > IncrementSize)
5102 Alignment = IncrementSize;
5103 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5104 isVolatile, Alignment);
5106 // Build a factor node to remember that this load is independent of the
5108 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5111 // Remember that we legalized the chain.
5112 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5113 if (!TLI.isLittleEndian())
5116 MVT::ValueType EVT = LD->getLoadedVT();
5118 if (VT == MVT::f64 && EVT == MVT::f32) {
5119 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5120 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5121 SVOffset, isVolatile, Alignment);
5122 // Remember that we legalized the chain.
5123 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5124 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5129 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5130 SVOffset, isVolatile, Alignment);
5132 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5133 SVOffset, EVT, isVolatile,
5136 // Remember that we legalized the chain.
5137 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5139 if (ExtType == ISD::SEXTLOAD) {
5140 // The high part is obtained by SRA'ing all but one of the bits of the
5142 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5143 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5144 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5145 } else if (ExtType == ISD::ZEXTLOAD) {
5146 // The high part is just a zero.
5147 Hi = DAG.getConstant(0, NVT);
5148 } else /* if (ExtType == ISD::EXTLOAD) */ {
5149 // The high part is undefined.
5150 Hi = DAG.getNode(ISD::UNDEF, NVT);
5157 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5158 SDOperand LL, LH, RL, RH;
5159 ExpandOp(Node->getOperand(0), LL, LH);
5160 ExpandOp(Node->getOperand(1), RL, RH);
5161 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5162 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5166 SDOperand LL, LH, RL, RH;
5167 ExpandOp(Node->getOperand(1), LL, LH);
5168 ExpandOp(Node->getOperand(2), RL, RH);
5169 if (getTypeAction(NVT) == Expand)
5170 NVT = TLI.getTypeToExpandTo(NVT);
5171 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5173 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5176 case ISD::SELECT_CC: {
5177 SDOperand TL, TH, FL, FH;
5178 ExpandOp(Node->getOperand(2), TL, TH);
5179 ExpandOp(Node->getOperand(3), FL, FH);
5180 if (getTypeAction(NVT) == Expand)
5181 NVT = TLI.getTypeToExpandTo(NVT);
5182 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5183 Node->getOperand(1), TL, FL, Node->getOperand(4));
5185 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5186 Node->getOperand(1), TH, FH, Node->getOperand(4));
5189 case ISD::ANY_EXTEND:
5190 // The low part is any extension of the input (which degenerates to a copy).
5191 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5192 // The high part is undefined.
5193 Hi = DAG.getNode(ISD::UNDEF, NVT);
5195 case ISD::SIGN_EXTEND: {
5196 // The low part is just a sign extension of the input (which degenerates to
5198 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5200 // The high part is obtained by SRA'ing all but one of the bits of the lo
5202 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5203 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5204 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5207 case ISD::ZERO_EXTEND:
5208 // The low part is just a zero extension of the input (which degenerates to
5210 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5212 // The high part is just a zero.
5213 Hi = DAG.getConstant(0, NVT);
5216 case ISD::TRUNCATE: {
5217 // The input value must be larger than this value. Expand *it*.
5219 ExpandOp(Node->getOperand(0), NewLo, Hi);
5221 // The low part is now either the right size, or it is closer. If not the
5222 // right size, make an illegal truncate so we recursively expand it.
5223 if (NewLo.getValueType() != Node->getValueType(0))
5224 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5225 ExpandOp(NewLo, Lo, Hi);
5229 case ISD::BIT_CONVERT: {
5231 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5232 // If the target wants to, allow it to lower this itself.
5233 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5234 case Expand: assert(0 && "cannot expand FP!");
5235 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5236 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5238 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5241 // f32 / f64 must be expanded to i32 / i64.
5242 if (VT == MVT::f32 || VT == MVT::f64) {
5243 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5244 if (getTypeAction(NVT) == Expand)
5245 ExpandOp(Lo, Lo, Hi);
5249 // If source operand will be expanded to the same type as VT, i.e.
5250 // i64 <- f64, i32 <- f32, expand the source operand instead.
5251 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5252 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5253 ExpandOp(Node->getOperand(0), Lo, Hi);
5257 // Turn this into a load/store pair by default.
5259 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5261 ExpandOp(Tmp, Lo, Hi);
5265 case ISD::READCYCLECOUNTER:
5266 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5267 TargetLowering::Custom &&
5268 "Must custom expand ReadCycleCounter");
5269 Lo = TLI.LowerOperation(Op, DAG);
5270 assert(Lo.Val && "Node must be custom expanded!");
5271 Hi = Lo.getValue(1);
5272 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5273 LegalizeOp(Lo.getValue(2)));
5276 // These operators cannot be expanded directly, emit them as calls to
5277 // library functions.
5278 case ISD::FP_TO_SINT: {
5279 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5281 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5282 case Expand: assert(0 && "cannot expand FP!");
5283 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5284 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5287 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5289 // Now that the custom expander is done, expand the result, which is still
5292 ExpandOp(Op, Lo, Hi);
5298 if (Node->getOperand(0).getValueType() == MVT::f32)
5299 LC = RTLIB::FPTOSINT_F32_I64;
5301 LC = RTLIB::FPTOSINT_F64_I64;
5302 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5303 false/*sign irrelevant*/, Hi);
5307 case ISD::FP_TO_UINT: {
5308 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5310 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5311 case Expand: assert(0 && "cannot expand FP!");
5312 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5313 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5316 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5318 // Now that the custom expander is done, expand the result.
5320 ExpandOp(Op, Lo, Hi);
5326 if (Node->getOperand(0).getValueType() == MVT::f32)
5327 LC = RTLIB::FPTOUINT_F32_I64;
5329 LC = RTLIB::FPTOUINT_F64_I64;
5330 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5331 false/*sign irrelevant*/, Hi);
5336 // If the target wants custom lowering, do so.
5337 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5338 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5339 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5340 Op = TLI.LowerOperation(Op, DAG);
5342 // Now that the custom expander is done, expand the result, which is
5344 ExpandOp(Op, Lo, Hi);
5349 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5350 // this X << 1 as X+X.
5351 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5352 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5353 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5354 SDOperand LoOps[2], HiOps[3];
5355 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5356 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5357 LoOps[1] = LoOps[0];
5358 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5360 HiOps[1] = HiOps[0];
5361 HiOps[2] = Lo.getValue(1);
5362 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5367 // If we can emit an efficient shift operation, do so now.
5368 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5371 // If this target supports SHL_PARTS, use it.
5372 TargetLowering::LegalizeAction Action =
5373 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5374 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5375 Action == TargetLowering::Custom) {
5376 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5380 // Otherwise, emit a libcall.
5381 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5382 false/*left shift=unsigned*/, Hi);
5387 // If the target wants custom lowering, do so.
5388 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5389 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5390 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5391 Op = TLI.LowerOperation(Op, DAG);
5393 // Now that the custom expander is done, expand the result, which is
5395 ExpandOp(Op, Lo, Hi);
5400 // If we can emit an efficient shift operation, do so now.
5401 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5404 // If this target supports SRA_PARTS, use it.
5405 TargetLowering::LegalizeAction Action =
5406 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5407 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5408 Action == TargetLowering::Custom) {
5409 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5413 // Otherwise, emit a libcall.
5414 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5415 true/*ashr is signed*/, Hi);
5420 // If the target wants custom lowering, do so.
5421 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5422 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5423 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5424 Op = TLI.LowerOperation(Op, DAG);
5426 // Now that the custom expander is done, expand the result, which is
5428 ExpandOp(Op, Lo, Hi);
5433 // If we can emit an efficient shift operation, do so now.
5434 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5437 // If this target supports SRL_PARTS, use it.
5438 TargetLowering::LegalizeAction Action =
5439 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5440 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5441 Action == TargetLowering::Custom) {
5442 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5446 // Otherwise, emit a libcall.
5447 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5448 false/*lshr is unsigned*/, Hi);
5454 // If the target wants to custom expand this, let them.
5455 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5456 TargetLowering::Custom) {
5457 Op = TLI.LowerOperation(Op, DAG);
5459 ExpandOp(Op, Lo, Hi);
5464 // Expand the subcomponents.
5465 SDOperand LHSL, LHSH, RHSL, RHSH;
5466 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5467 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5468 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5469 SDOperand LoOps[2], HiOps[3];
5474 if (Node->getOpcode() == ISD::ADD) {
5475 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5476 HiOps[2] = Lo.getValue(1);
5477 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5479 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5480 HiOps[2] = Lo.getValue(1);
5481 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5488 // Expand the subcomponents.
5489 SDOperand LHSL, LHSH, RHSL, RHSH;
5490 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5491 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5492 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5493 SDOperand LoOps[2] = { LHSL, RHSL };
5494 SDOperand HiOps[3] = { LHSH, RHSH };
5496 if (Node->getOpcode() == ISD::ADDC) {
5497 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5498 HiOps[2] = Lo.getValue(1);
5499 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5501 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5502 HiOps[2] = Lo.getValue(1);
5503 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5505 // Remember that we legalized the flag.
5506 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5511 // Expand the subcomponents.
5512 SDOperand LHSL, LHSH, RHSL, RHSH;
5513 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5514 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5515 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5516 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5517 SDOperand HiOps[3] = { LHSH, RHSH };
5519 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5520 HiOps[2] = Lo.getValue(1);
5521 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5523 // Remember that we legalized the flag.
5524 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5528 // If the target wants to custom expand this, let them.
5529 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5530 SDOperand New = TLI.LowerOperation(Op, DAG);
5532 ExpandOp(New, Lo, Hi);
5537 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5538 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5539 if (HasMULHS || HasMULHU) {
5540 SDOperand LL, LH, RL, RH;
5541 ExpandOp(Node->getOperand(0), LL, LH);
5542 ExpandOp(Node->getOperand(1), RL, RH);
5543 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5544 // FIXME: Move this to the dag combiner.
5545 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5546 // extended the sign bit of the low half through the upper half, and if so
5547 // emit a MULHS instead of the alternate sequence that is valid for any
5548 // i64 x i64 multiply.
5550 // is RH an extension of the sign bit of RL?
5551 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5552 RH.getOperand(1).getOpcode() == ISD::Constant &&
5553 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5554 // is LH an extension of the sign bit of LL?
5555 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5556 LH.getOperand(1).getOpcode() == ISD::Constant &&
5557 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5559 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5561 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5563 } else if (HasMULHU) {
5565 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5568 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5569 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5570 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5571 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5572 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5577 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5578 false/*sign irrelevant*/, Hi);
5582 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5585 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5588 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5591 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5595 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5596 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5600 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5601 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5605 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5606 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5610 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5611 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5614 case ISD::FP_EXTEND:
5615 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5618 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5621 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5622 ? RTLIB::POWI_F32 : RTLIB::POWI_F64),
5628 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5629 switch(Node->getOpcode()) {
5631 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5634 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5637 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5639 default: assert(0 && "Unreachable!");
5641 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5645 SDOperand Mask = (VT == MVT::f64)
5646 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5647 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5648 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5649 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5650 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5651 if (getTypeAction(NVT) == Expand)
5652 ExpandOp(Lo, Lo, Hi);
5656 SDOperand Mask = (VT == MVT::f64)
5657 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5658 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5659 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5660 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5661 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5662 if (getTypeAction(NVT) == Expand)
5663 ExpandOp(Lo, Lo, Hi);
5666 case ISD::FCOPYSIGN: {
5667 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5668 if (getTypeAction(NVT) == Expand)
5669 ExpandOp(Lo, Lo, Hi);
5672 case ISD::SINT_TO_FP:
5673 case ISD::UINT_TO_FP: {
5674 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5675 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5677 if (Node->getOperand(0).getValueType() == MVT::i64) {
5679 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5681 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5684 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5686 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5689 // Promote the operand if needed.
5690 if (getTypeAction(SrcVT) == Promote) {
5691 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5693 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5694 DAG.getValueType(SrcVT))
5695 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5696 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5699 const char *LibCall = TLI.getLibcallName(LC);
5701 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5703 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5704 Node->getOperand(0));
5705 if (getTypeAction(Lo.getValueType()) == Expand)
5706 ExpandOp(Lo, Lo, Hi);
5712 // Make sure the resultant values have been legalized themselves, unless this
5713 // is a type that requires multi-step expansion.
5714 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5715 Lo = LegalizeOp(Lo);
5717 // Don't legalize the high part if it is expanded to a single node.
5718 Hi = LegalizeOp(Hi);
5721 // Remember in a map if the values will be reused later.
5722 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5723 assert(isNew && "Value already expanded?!?");
5726 /// SplitVectorOp - Given an operand of vector type, break it down into
5727 /// two smaller values, still of vector type.
5728 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5730 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5731 SDNode *Node = Op.Val;
5732 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5733 assert(NumElements > 1 && "Cannot split a single element vector!");
5734 unsigned NewNumElts = NumElements/2;
5735 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5736 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5738 // See if we already split it.
5739 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5740 = SplitNodes.find(Op);
5741 if (I != SplitNodes.end()) {
5742 Lo = I->second.first;
5743 Hi = I->second.second;
5747 switch (Node->getOpcode()) {
5752 assert(0 && "Unhandled operation in SplitVectorOp!");
5753 case ISD::BUILD_PAIR:
5754 Lo = Node->getOperand(0);
5755 Hi = Node->getOperand(1);
5757 case ISD::BUILD_VECTOR: {
5758 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5759 Node->op_begin()+NewNumElts);
5760 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5762 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5764 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5767 case ISD::CONCAT_VECTORS: {
5768 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5769 if (NewNumSubvectors == 1) {
5770 Lo = Node->getOperand(0);
5771 Hi = Node->getOperand(1);
5773 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5774 Node->op_begin()+NewNumSubvectors);
5775 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5777 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5779 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5795 SDOperand LL, LH, RL, RH;
5796 SplitVectorOp(Node->getOperand(0), LL, LH);
5797 SplitVectorOp(Node->getOperand(1), RL, RH);
5799 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5800 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5804 LoadSDNode *LD = cast<LoadSDNode>(Node);
5805 SDOperand Ch = LD->getChain();
5806 SDOperand Ptr = LD->getBasePtr();
5807 const Value *SV = LD->getSrcValue();
5808 int SVOffset = LD->getSrcValueOffset();
5809 unsigned Alignment = LD->getAlignment();
5810 bool isVolatile = LD->isVolatile();
5812 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5813 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5814 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5815 getIntPtrConstant(IncrementSize));
5816 SVOffset += IncrementSize;
5817 if (Alignment > IncrementSize)
5818 Alignment = IncrementSize;
5819 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5821 // Build a factor node to remember that this load is independent of the
5823 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5826 // Remember that we legalized the chain.
5827 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5830 case ISD::BIT_CONVERT: {
5831 // We know the result is a vector. The input may be either a vector or a
5833 SDOperand InOp = Node->getOperand(0);
5834 if (!MVT::isVector(InOp.getValueType()) ||
5835 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5836 // The input is a scalar or single-element vector.
5837 // Lower to a store/load so that it can be split.
5838 // FIXME: this could be improved probably.
5839 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5841 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5842 InOp, Ptr, NULL, 0);
5843 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5845 // Split the vector and convert each of the pieces now.
5846 SplitVectorOp(InOp, Lo, Hi);
5847 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5848 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5853 // Remember in a map if the values will be reused later.
5855 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5856 assert(isNew && "Value already split?!?");
5860 /// ScalarizeVectorOp - Given an operand of single-element vector type
5861 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5862 /// scalar (e.g. f32) value.
5863 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5864 assert(MVT::isVector(Op.getValueType()) &&
5865 "Bad ScalarizeVectorOp invocation!");
5866 SDNode *Node = Op.Val;
5867 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5868 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5870 // See if we already scalarized it.
5871 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5872 if (I != ScalarizedNodes.end()) return I->second;
5875 switch (Node->getOpcode()) {
5878 Node->dump(&DAG); cerr << "\n";
5880 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5896 Result = DAG.getNode(Node->getOpcode(),
5898 ScalarizeVectorOp(Node->getOperand(0)),
5899 ScalarizeVectorOp(Node->getOperand(1)));
5906 Result = DAG.getNode(Node->getOpcode(),
5908 ScalarizeVectorOp(Node->getOperand(0)));
5911 LoadSDNode *LD = cast<LoadSDNode>(Node);
5912 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5913 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5915 const Value *SV = LD->getSrcValue();
5916 int SVOffset = LD->getSrcValueOffset();
5917 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5918 LD->isVolatile(), LD->getAlignment());
5920 // Remember that we legalized the chain.
5921 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5924 case ISD::BUILD_VECTOR:
5925 Result = Node->getOperand(0);
5927 case ISD::INSERT_VECTOR_ELT:
5928 // Returning the inserted scalar element.
5929 Result = Node->getOperand(1);
5931 case ISD::CONCAT_VECTORS:
5932 assert(Node->getOperand(0).getValueType() == NewVT &&
5933 "Concat of non-legal vectors not yet supported!");
5934 Result = Node->getOperand(0);
5936 case ISD::VECTOR_SHUFFLE: {
5937 // Figure out if the scalar is the LHS or RHS and return it.
5938 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5939 if (cast<ConstantSDNode>(EltNum)->getValue())
5940 Result = ScalarizeVectorOp(Node->getOperand(1));
5942 Result = ScalarizeVectorOp(Node->getOperand(0));
5945 case ISD::EXTRACT_SUBVECTOR:
5946 Result = Node->getOperand(0);
5947 assert(Result.getValueType() == NewVT);
5949 case ISD::BIT_CONVERT:
5950 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5953 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5954 ScalarizeVectorOp(Op.getOperand(1)),
5955 ScalarizeVectorOp(Op.getOperand(2)));
5959 if (TLI.isTypeLegal(NewVT))
5960 Result = LegalizeOp(Result);
5961 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
5962 assert(isNew && "Value already scalarized?");
5967 // SelectionDAG::Legalize - This is the entry point for the file.
5969 void SelectionDAG::Legalize() {
5970 if (ViewLegalizeDAGs) viewGraph();
5972 /// run - This is the main entry point to this class.
5974 SelectionDAGLegalize(*this).LegalizeDAG();