1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
44 struct FloatSignAsInt;
46 //===----------------------------------------------------------------------===//
47 /// This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
58 class SelectionDAGLegalize {
59 const TargetMachine &TM;
60 const TargetLowering &TLI;
63 /// \brief The set of nodes which have already been legalized. We hold a
64 /// reference to it in order to update as necessary on node deletion.
65 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
67 /// \brief A set of all the nodes updated during legalization.
68 SmallSetVector<SDNode *, 16> *UpdatedNodes;
70 EVT getSetCCResultType(EVT VT) const {
71 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
74 // Libcall insertion helpers.
77 SelectionDAGLegalize(SelectionDAG &DAG,
78 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
79 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
80 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
81 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
83 /// \brief Legalizes the given operation.
84 void LegalizeOp(SDNode *Node);
87 SDValue OptimizeFloatStore(StoreSDNode *ST);
89 void LegalizeLoadOps(SDNode *Node);
90 void LegalizeStoreOps(SDNode *Node);
92 /// Some targets cannot handle a variable
93 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
94 /// is necessary to spill the vector being inserted into to memory, perform
95 /// the insert there, and then read the result back.
96 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
97 SDValue Idx, SDLoc dl);
98 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
99 SDValue Idx, SDLoc dl);
101 /// Return a vector shuffle operation which
102 /// performs the same shuffe in terms of order or result bytes, but on a type
103 /// whose vector element type is narrower than the original shuffle type.
104 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
105 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
106 SDValue N1, SDValue N2,
107 ArrayRef<int> Mask) const;
109 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
110 bool &NeedInvert, SDLoc dl);
112 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
113 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
114 unsigned NumOps, bool isSigned, SDLoc dl);
116 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
117 SDNode *Node, bool isSigned);
118 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
119 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
120 RTLIB::Libcall Call_F128,
121 RTLIB::Libcall Call_PPCF128);
122 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
123 RTLIB::Libcall Call_I8,
124 RTLIB::Libcall Call_I16,
125 RTLIB::Libcall Call_I32,
126 RTLIB::Libcall Call_I64,
127 RTLIB::Libcall Call_I128);
128 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
129 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
131 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
132 SDValue ExpandBUILD_VECTOR(SDNode *Node);
133 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
134 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
135 SmallVectorImpl<SDValue> &Results);
136 void getSignAsIntValue(FloatSignAsInt &State, SDLoc DL, SDValue Value) const;
137 SDValue modifySignAsInt(const FloatSignAsInt &State, SDLoc DL,
138 SDValue NewIntValue) const;
139 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
140 SDValue ExpandFABS(SDNode *Node) const;
141 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
143 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
145 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
148 SDValue ExpandBITREVERSE(SDValue Op, SDLoc dl);
149 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
150 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
152 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
153 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
154 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
156 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
157 SDValue ExpandConstant(ConstantSDNode *CP);
159 // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
160 bool ExpandNode(SDNode *Node);
161 void ConvertNodeToLibcall(SDNode *Node);
162 void PromoteNode(SDNode *Node);
165 // Node replacement helpers
166 void ReplacedNode(SDNode *N) {
167 LegalizedNodes.erase(N);
169 UpdatedNodes->insert(N);
171 void ReplaceNode(SDNode *Old, SDNode *New) {
172 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
173 dbgs() << " with: "; New->dump(&DAG));
175 assert(Old->getNumValues() == New->getNumValues() &&
176 "Replacing one node with another that produces a different number "
178 DAG.ReplaceAllUsesWith(Old, New);
179 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
180 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
182 UpdatedNodes->insert(New);
185 void ReplaceNode(SDValue Old, SDValue New) {
186 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
187 dbgs() << " with: "; New->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 DAG.TransferDbgValues(Old, New);
192 UpdatedNodes->insert(New.getNode());
193 ReplacedNode(Old.getNode());
195 void ReplaceNode(SDNode *Old, const SDValue *New) {
196 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
198 DAG.ReplaceAllUsesWith(Old, New);
199 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
200 DEBUG(dbgs() << (i == 0 ? " with: "
203 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
205 UpdatedNodes->insert(New[i].getNode());
212 /// Return a vector shuffle operation which
213 /// performs the same shuffe in terms of order or result bytes, but on a type
214 /// whose vector element type is narrower than the original shuffle type.
215 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
217 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
218 SDValue N1, SDValue N2,
219 ArrayRef<int> Mask) const {
220 unsigned NumMaskElts = VT.getVectorNumElements();
221 unsigned NumDestElts = NVT.getVectorNumElements();
222 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
224 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
226 if (NumEltsGrowth == 1)
227 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
229 SmallVector<int, 8> NewMask;
230 for (unsigned i = 0; i != NumMaskElts; ++i) {
232 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
234 NewMask.push_back(-1);
236 NewMask.push_back(Idx * NumEltsGrowth + j);
239 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
240 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
241 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
244 /// Expands the ConstantFP node to an integer constant or
245 /// a load from the constant pool.
247 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
251 // If a FP immediate is precise when represented as a float and if the
252 // target can do an extending load from float to double, we put it into
253 // the constant pool as a float, even if it's is statically typed as a
254 // double. This shrinks FP constants and canonicalizes them for targets where
255 // an FP extending load is the same cost as a normal load (such as on the x87
256 // fp stack or PPC FP unit).
257 EVT VT = CFP->getValueType(0);
258 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
260 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
261 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
262 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
267 while (SVT != MVT::f32 && SVT != MVT::f16) {
268 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
269 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
270 // Only do this if the target has a native EXTLOAD instruction from
272 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
273 TLI.ShouldShrinkFPConstant(OrigVT)) {
274 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
275 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
282 DAG.getConstantPool(LLVMC, TLI.getPointerTy(DAG.getDataLayout()));
283 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
285 SDValue Result = DAG.getExtLoad(
286 ISD::EXTLOAD, dl, OrigVT, DAG.getEntryNode(), CPIdx,
287 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), VT,
288 false, false, false, Alignment);
292 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
293 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
294 false, false, false, Alignment);
298 /// Expands the Constant node to a load from the constant pool.
299 SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
301 EVT VT = CP->getValueType(0);
302 SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
303 TLI.getPointerTy(DAG.getDataLayout()));
304 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
306 DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
307 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
308 false, false, false, Alignment);
312 /// Expands an unaligned store to 2 half-size stores.
313 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
314 const TargetLowering &TLI,
315 SelectionDAGLegalize *DAGLegalize) {
316 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
317 "unaligned indexed stores not implemented!");
318 SDValue Chain = ST->getChain();
319 SDValue Ptr = ST->getBasePtr();
320 SDValue Val = ST->getValue();
321 EVT VT = Val.getValueType();
322 int Alignment = ST->getAlignment();
323 unsigned AS = ST->getAddressSpace();
326 if (ST->getMemoryVT().isFloatingPoint() ||
327 ST->getMemoryVT().isVector()) {
328 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
329 if (TLI.isTypeLegal(intVT)) {
330 // Expand to a bitconvert of the value to the integer type of the
331 // same size, then a (misaligned) int store.
332 // FIXME: Does not handle truncating floating point stores!
333 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
334 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
335 ST->isVolatile(), ST->isNonTemporal(), Alignment);
336 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
339 // Do a (aligned) store to a stack slot, then copy from the stack slot
340 // to the final destination using (unaligned) integer loads and stores.
341 EVT StoredVT = ST->getMemoryVT();
343 TLI.getRegisterType(*DAG.getContext(),
344 EVT::getIntegerVT(*DAG.getContext(),
345 StoredVT.getSizeInBits()));
346 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
347 unsigned RegBytes = RegVT.getSizeInBits() / 8;
348 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
350 // Make sure the stack slot is also aligned for the register type.
351 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
353 // Perform the original store, only redirected to the stack slot.
354 SDValue Store = DAG.getTruncStore(Chain, dl,
355 Val, StackPtr, MachinePointerInfo(),
356 StoredVT, false, false, 0);
357 SDValue Increment = DAG.getConstant(
358 RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout(), AS));
359 SmallVector<SDValue, 8> Stores;
362 // Do all but one copies using the full register width.
363 for (unsigned i = 1; i < NumRegs; i++) {
364 // Load one integer register's worth from the stack slot.
365 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
366 MachinePointerInfo(),
367 false, false, false, 0);
368 // Store it to the final location. Remember the store.
369 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
370 ST->getPointerInfo().getWithOffset(Offset),
371 ST->isVolatile(), ST->isNonTemporal(),
372 MinAlign(ST->getAlignment(), Offset)));
373 // Increment the pointers.
375 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
377 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
380 // The last store may be partial. Do a truncating store. On big-endian
381 // machines this requires an extending load from the stack slot to ensure
382 // that the bits are in the right place.
383 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
384 8 * (StoredBytes - Offset));
386 // Load from the stack slot.
387 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
388 MachinePointerInfo(),
389 MemVT, false, false, false, 0);
391 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
393 .getWithOffset(Offset),
394 MemVT, ST->isVolatile(),
396 MinAlign(ST->getAlignment(), Offset),
398 // The order of the stores doesn't matter - say it with a TokenFactor.
399 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
400 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
403 assert(ST->getMemoryVT().isInteger() &&
404 !ST->getMemoryVT().isVector() &&
405 "Unaligned store of unknown type.");
406 // Get the half-size VT
407 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
408 int NumBits = NewStoredVT.getSizeInBits();
409 int IncrementSize = NumBits / 8;
411 // Divide the stored value in two parts.
412 SDValue ShiftAmount =
413 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Val.getValueType(),
414 DAG.getDataLayout()));
416 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
418 // Store the two parts
419 SDValue Store1, Store2;
420 Store1 = DAG.getTruncStore(Chain, dl,
421 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
422 Ptr, ST->getPointerInfo(), NewStoredVT,
423 ST->isVolatile(), ST->isNonTemporal(), Alignment);
425 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
426 DAG.getConstant(IncrementSize, dl,
427 TLI.getPointerTy(DAG.getDataLayout(), AS)));
428 Alignment = MinAlign(Alignment, IncrementSize);
429 Store2 = DAG.getTruncStore(
430 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
431 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT,
432 ST->isVolatile(), ST->isNonTemporal(), Alignment, ST->getAAInfo());
435 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
436 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
439 /// Expands an unaligned load to 2 half-size loads.
441 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
442 const TargetLowering &TLI,
443 SDValue &ValResult, SDValue &ChainResult) {
444 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
445 "unaligned indexed loads not implemented!");
446 SDValue Chain = LD->getChain();
447 SDValue Ptr = LD->getBasePtr();
448 EVT VT = LD->getValueType(0);
449 EVT LoadedVT = LD->getMemoryVT();
451 if (VT.isFloatingPoint() || VT.isVector()) {
452 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
453 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
454 // Expand to a (misaligned) integer load of the same size,
455 // then bitconvert to floating point or vector.
456 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
457 LD->getMemOperand());
458 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
460 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
461 ISD::ANY_EXTEND, dl, VT, Result);
464 ChainResult = newLoad.getValue(1);
468 // Copy the value to a (aligned) stack slot using (unaligned) integer
469 // loads and stores, then do a (aligned) load from the stack slot.
470 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
471 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
472 unsigned RegBytes = RegVT.getSizeInBits() / 8;
473 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
475 // Make sure the stack slot is also aligned for the register type.
476 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
479 DAG.getConstant(RegBytes, dl, TLI.getPointerTy(DAG.getDataLayout()));
480 SmallVector<SDValue, 8> Stores;
481 SDValue StackPtr = StackBase;
484 // Do all but one copies using the full register width.
485 for (unsigned i = 1; i < NumRegs; i++) {
486 // Load one integer register's worth from the original location.
487 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
488 LD->getPointerInfo().getWithOffset(Offset),
489 LD->isVolatile(), LD->isNonTemporal(),
491 MinAlign(LD->getAlignment(), Offset),
493 // Follow the load with a store to the stack slot. Remember the store.
494 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
495 MachinePointerInfo(), false, false, 0));
496 // Increment the pointers.
498 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
499 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
503 // The last copy may be partial. Do an extending load.
504 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
505 8 * (LoadedBytes - Offset));
506 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
507 LD->getPointerInfo().getWithOffset(Offset),
508 MemVT, LD->isVolatile(),
511 MinAlign(LD->getAlignment(), Offset),
513 // Follow the load with a store to the stack slot. Remember the store.
514 // On big-endian machines this requires a truncating store to ensure
515 // that the bits end up in the right place.
516 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
517 MachinePointerInfo(), MemVT,
520 // The order of the stores doesn't matter - say it with a TokenFactor.
521 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
523 // Finally, perform the original load only redirected to the stack slot.
524 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
525 MachinePointerInfo(), LoadedVT, false,false, false,
528 // Callers expect a MERGE_VALUES node.
533 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
534 "Unaligned load of unsupported type.");
536 // Compute the new VT that is half the size of the old one. This is an
538 unsigned NumBits = LoadedVT.getSizeInBits();
540 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
543 unsigned Alignment = LD->getAlignment();
544 unsigned IncrementSize = NumBits / 8;
545 ISD::LoadExtType HiExtType = LD->getExtensionType();
547 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
548 if (HiExtType == ISD::NON_EXTLOAD)
549 HiExtType = ISD::ZEXTLOAD;
551 // Load the value in two parts
553 if (DAG.getDataLayout().isLittleEndian()) {
554 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
555 NewLoadedVT, LD->isVolatile(),
556 LD->isNonTemporal(), LD->isInvariant(), Alignment,
558 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
559 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
560 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
561 LD->getPointerInfo().getWithOffset(IncrementSize),
562 NewLoadedVT, LD->isVolatile(),
563 LD->isNonTemporal(),LD->isInvariant(),
564 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
566 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
567 NewLoadedVT, LD->isVolatile(),
568 LD->isNonTemporal(), LD->isInvariant(), Alignment,
570 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
571 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
572 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
573 LD->getPointerInfo().getWithOffset(IncrementSize),
574 NewLoadedVT, LD->isVolatile(),
575 LD->isNonTemporal(), LD->isInvariant(),
576 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
579 // aggregate the two parts
580 SDValue ShiftAmount =
581 DAG.getConstant(NumBits, dl, TLI.getShiftAmountTy(Hi.getValueType(),
582 DAG.getDataLayout()));
583 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
584 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
586 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
593 /// Some target cannot handle a variable insertion index for the
594 /// INSERT_VECTOR_ELT instruction. In this case, it
595 /// is necessary to spill the vector being inserted into to memory, perform
596 /// the insert there, and then read the result back.
597 SDValue SelectionDAGLegalize::
598 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
604 // If the target doesn't support this, we have to spill the input vector
605 // to a temporary stack slot, update the element, then reload it. This is
606 // badness. We could also load the value into a vector register (either
607 // with a "move to register" or "extload into register" instruction, then
608 // permute it into place, if the idx is a constant and if the idx is
609 // supported by the target.
610 EVT VT = Tmp1.getValueType();
611 EVT EltVT = VT.getVectorElementType();
612 EVT IdxVT = Tmp3.getValueType();
613 EVT PtrVT = TLI.getPointerTy(DAG.getDataLayout());
614 SDValue StackPtr = DAG.CreateStackTemporary(VT);
616 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
619 SDValue Ch = DAG.getStore(
620 DAG.getEntryNode(), dl, Tmp1, StackPtr,
621 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
624 // Truncate or zero extend offset to target pointer type.
625 Tmp3 = DAG.getZExtOrTrunc(Tmp3, dl, PtrVT);
626 // Add the offset to the index.
627 unsigned EltSize = EltVT.getSizeInBits()/8;
628 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
629 DAG.getConstant(EltSize, dl, IdxVT));
630 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
631 // Store the scalar value.
632 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
634 // Load the updated vector.
635 return DAG.getLoad(VT, dl, Ch, StackPtr, MachinePointerInfo::getFixedStack(
636 DAG.getMachineFunction(), SPFI),
637 false, false, false, 0);
641 SDValue SelectionDAGLegalize::
642 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
643 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
644 // SCALAR_TO_VECTOR requires that the type of the value being inserted
645 // match the element type of the vector being created, except for
646 // integers in which case the inserted value can be over width.
647 EVT EltVT = Vec.getValueType().getVectorElementType();
648 if (Val.getValueType() == EltVT ||
649 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
650 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
651 Vec.getValueType(), Val);
653 unsigned NumElts = Vec.getValueType().getVectorNumElements();
654 // We generate a shuffle of InVec and ScVec, so the shuffle mask
655 // should be 0,1,2,3,4,5... with the appropriate element replaced with
657 SmallVector<int, 8> ShufOps;
658 for (unsigned i = 0; i != NumElts; ++i)
659 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
661 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
665 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
668 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
669 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
670 // FIXME: We shouldn't do this for TargetConstantFP's.
671 // FIXME: move this to the DAG Combiner! Note that we can't regress due
672 // to phase ordering between legalized code and the dag combiner. This
673 // probably means that we need to integrate dag combiner and legalizer
675 // We generally can't do this one for long doubles.
676 SDValue Chain = ST->getChain();
677 SDValue Ptr = ST->getBasePtr();
678 unsigned Alignment = ST->getAlignment();
679 bool isVolatile = ST->isVolatile();
680 bool isNonTemporal = ST->isNonTemporal();
681 AAMDNodes AAInfo = ST->getAAInfo();
683 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
684 if (CFP->getValueType(0) == MVT::f32 &&
685 TLI.isTypeLegal(MVT::i32)) {
686 SDValue Con = DAG.getConstant(CFP->getValueAPF().
687 bitcastToAPInt().zextOrTrunc(32),
688 SDLoc(CFP), MVT::i32);
689 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
690 isVolatile, isNonTemporal, Alignment, AAInfo);
693 if (CFP->getValueType(0) == MVT::f64) {
694 // If this target supports 64-bit registers, do a single 64-bit store.
695 if (TLI.isTypeLegal(MVT::i64)) {
696 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
697 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
698 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
699 isVolatile, isNonTemporal, Alignment, AAInfo);
702 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
703 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
704 // stores. If the target supports neither 32- nor 64-bits, this
705 // xform is certainly not worth it.
706 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
707 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
708 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
709 if (DAG.getDataLayout().isBigEndian())
712 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
713 isNonTemporal, Alignment, AAInfo);
714 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
715 DAG.getConstant(4, dl, Ptr.getValueType()));
716 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
717 ST->getPointerInfo().getWithOffset(4),
718 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
721 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
725 return SDValue(nullptr, 0);
728 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
729 StoreSDNode *ST = cast<StoreSDNode>(Node);
730 SDValue Chain = ST->getChain();
731 SDValue Ptr = ST->getBasePtr();
734 unsigned Alignment = ST->getAlignment();
735 bool isVolatile = ST->isVolatile();
736 bool isNonTemporal = ST->isNonTemporal();
737 AAMDNodes AAInfo = ST->getAAInfo();
739 if (!ST->isTruncatingStore()) {
740 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
741 ReplaceNode(ST, OptStore);
746 SDValue Value = ST->getValue();
747 MVT VT = Value.getSimpleValueType();
748 switch (TLI.getOperationAction(ISD::STORE, VT)) {
749 default: llvm_unreachable("This action is not supported yet!");
750 case TargetLowering::Legal: {
751 // If this is an unaligned store and the target doesn't support it,
753 EVT MemVT = ST->getMemoryVT();
754 unsigned AS = ST->getAddressSpace();
755 unsigned Align = ST->getAlignment();
756 const DataLayout &DL = DAG.getDataLayout();
757 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
758 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
761 case TargetLowering::Custom: {
762 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
763 if (Res && Res != SDValue(Node, 0))
764 ReplaceNode(SDValue(Node, 0), Res);
767 case TargetLowering::Promote: {
768 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
769 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
770 "Can only promote stores to same size type");
771 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
773 DAG.getStore(Chain, dl, Value, Ptr,
774 ST->getPointerInfo(), isVolatile,
775 isNonTemporal, Alignment, AAInfo);
776 ReplaceNode(SDValue(Node, 0), Result);
783 SDValue Value = ST->getValue();
785 EVT StVT = ST->getMemoryVT();
786 unsigned StWidth = StVT.getSizeInBits();
787 auto &DL = DAG.getDataLayout();
789 if (StWidth != StVT.getStoreSizeInBits()) {
790 // Promote to a byte-sized store with upper bits zero if not
791 // storing an integral number of bytes. For example, promote
792 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
793 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
794 StVT.getStoreSizeInBits());
795 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
797 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
798 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
799 ReplaceNode(SDValue(Node, 0), Result);
800 } else if (StWidth & (StWidth - 1)) {
801 // If not storing a power-of-2 number of bits, expand as two stores.
802 assert(!StVT.isVector() && "Unsupported truncstore!");
803 unsigned RoundWidth = 1 << Log2_32(StWidth);
804 assert(RoundWidth < StWidth);
805 unsigned ExtraWidth = StWidth - RoundWidth;
806 assert(ExtraWidth < RoundWidth);
807 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
808 "Store size not an integral number of bytes!");
809 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
810 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
812 unsigned IncrementSize;
814 if (DL.isLittleEndian()) {
815 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
816 // Store the bottom RoundWidth bits.
817 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
819 isVolatile, isNonTemporal, Alignment,
822 // Store the remaining ExtraWidth bits.
823 IncrementSize = RoundWidth / 8;
824 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
825 DAG.getConstant(IncrementSize, dl,
826 Ptr.getValueType()));
828 ISD::SRL, dl, Value.getValueType(), Value,
829 DAG.getConstant(RoundWidth, dl,
830 TLI.getShiftAmountTy(Value.getValueType(), DL)));
831 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
832 ST->getPointerInfo().getWithOffset(IncrementSize),
833 ExtraVT, isVolatile, isNonTemporal,
834 MinAlign(Alignment, IncrementSize), AAInfo);
836 // Big endian - avoid unaligned stores.
837 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
838 // Store the top RoundWidth bits.
840 ISD::SRL, dl, Value.getValueType(), Value,
841 DAG.getConstant(ExtraWidth, dl,
842 TLI.getShiftAmountTy(Value.getValueType(), DL)));
843 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
844 RoundVT, isVolatile, isNonTemporal, Alignment,
847 // Store the remaining ExtraWidth bits.
848 IncrementSize = RoundWidth / 8;
849 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
850 DAG.getConstant(IncrementSize, dl,
851 Ptr.getValueType()));
852 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
853 ST->getPointerInfo().getWithOffset(IncrementSize),
854 ExtraVT, isVolatile, isNonTemporal,
855 MinAlign(Alignment, IncrementSize), AAInfo);
858 // The order of the stores doesn't matter.
859 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
860 ReplaceNode(SDValue(Node, 0), Result);
862 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
863 default: llvm_unreachable("This action is not supported yet!");
864 case TargetLowering::Legal: {
865 EVT MemVT = ST->getMemoryVT();
866 unsigned AS = ST->getAddressSpace();
867 unsigned Align = ST->getAlignment();
868 // If this is an unaligned store and the target doesn't support it,
870 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
871 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
874 case TargetLowering::Custom: {
875 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
876 if (Res && Res != SDValue(Node, 0))
877 ReplaceNode(SDValue(Node, 0), Res);
880 case TargetLowering::Expand:
881 assert(!StVT.isVector() &&
882 "Vector Stores are handled in LegalizeVectorOps");
884 // TRUNCSTORE:i16 i32 -> STORE i16
885 assert(TLI.isTypeLegal(StVT) &&
886 "Do not know how to expand this store!");
887 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
889 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
890 isVolatile, isNonTemporal, Alignment, AAInfo);
891 ReplaceNode(SDValue(Node, 0), Result);
898 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
899 LoadSDNode *LD = cast<LoadSDNode>(Node);
900 SDValue Chain = LD->getChain(); // The chain.
901 SDValue Ptr = LD->getBasePtr(); // The base pointer.
902 SDValue Value; // The value returned by the load op.
905 ISD::LoadExtType ExtType = LD->getExtensionType();
906 if (ExtType == ISD::NON_EXTLOAD) {
907 MVT VT = Node->getSimpleValueType(0);
908 SDValue RVal = SDValue(Node, 0);
909 SDValue RChain = SDValue(Node, 1);
911 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
912 default: llvm_unreachable("This action is not supported yet!");
913 case TargetLowering::Legal: {
914 EVT MemVT = LD->getMemoryVT();
915 unsigned AS = LD->getAddressSpace();
916 unsigned Align = LD->getAlignment();
917 const DataLayout &DL = DAG.getDataLayout();
918 // If this is an unaligned load and the target doesn't support it,
920 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
921 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
924 case TargetLowering::Custom: {
925 SDValue Res = TLI.LowerOperation(RVal, DAG);
928 RChain = Res.getValue(1);
932 case TargetLowering::Promote: {
933 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
934 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
935 "Can only promote loads to same size type");
937 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
938 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
939 RChain = Res.getValue(1);
943 if (RChain.getNode() != Node) {
944 assert(RVal.getNode() != Node && "Load must be completely replaced");
945 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
946 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
948 UpdatedNodes->insert(RVal.getNode());
949 UpdatedNodes->insert(RChain.getNode());
956 EVT SrcVT = LD->getMemoryVT();
957 unsigned SrcWidth = SrcVT.getSizeInBits();
958 unsigned Alignment = LD->getAlignment();
959 bool isVolatile = LD->isVolatile();
960 bool isNonTemporal = LD->isNonTemporal();
961 bool isInvariant = LD->isInvariant();
962 AAMDNodes AAInfo = LD->getAAInfo();
964 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
965 // Some targets pretend to have an i1 loading operation, and actually
966 // load an i8. This trick is correct for ZEXTLOAD because the top 7
967 // bits are guaranteed to be zero; it helps the optimizers understand
968 // that these bits are zero. It is also useful for EXTLOAD, since it
969 // tells the optimizers that those bits are undefined. It would be
970 // nice to have an effective generic way of getting these benefits...
971 // Until such a way is found, don't insist on promoting i1 here.
973 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
974 TargetLowering::Promote)) {
975 // Promote to a byte-sized load if not loading an integral number of
976 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
977 unsigned NewWidth = SrcVT.getStoreSizeInBits();
978 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
981 // The extra bits are guaranteed to be zero, since we stored them that
982 // way. A zext load from NVT thus automatically gives zext from SrcVT.
984 ISD::LoadExtType NewExtType =
985 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
988 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
989 Chain, Ptr, LD->getPointerInfo(),
990 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
993 Ch = Result.getValue(1); // The chain.
995 if (ExtType == ISD::SEXTLOAD)
996 // Having the top bits zero doesn't help when sign extending.
997 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
998 Result.getValueType(),
999 Result, DAG.getValueType(SrcVT));
1000 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1001 // All the top bits are guaranteed to be zero - inform the optimizers.
1002 Result = DAG.getNode(ISD::AssertZext, dl,
1003 Result.getValueType(), Result,
1004 DAG.getValueType(SrcVT));
1008 } else if (SrcWidth & (SrcWidth - 1)) {
1009 // If not loading a power-of-2 number of bits, expand as two loads.
1010 assert(!SrcVT.isVector() && "Unsupported extload!");
1011 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1012 assert(RoundWidth < SrcWidth);
1013 unsigned ExtraWidth = SrcWidth - RoundWidth;
1014 assert(ExtraWidth < RoundWidth);
1015 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1016 "Load size not an integral number of bytes!");
1017 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1018 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1020 unsigned IncrementSize;
1021 auto &DL = DAG.getDataLayout();
1023 if (DL.isLittleEndian()) {
1024 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1025 // Load the bottom RoundWidth bits.
1026 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1028 LD->getPointerInfo(), RoundVT, isVolatile,
1029 isNonTemporal, isInvariant, Alignment, AAInfo);
1031 // Load the remaining ExtraWidth bits.
1032 IncrementSize = RoundWidth / 8;
1033 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1034 DAG.getConstant(IncrementSize, dl,
1035 Ptr.getValueType()));
1036 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1037 LD->getPointerInfo().getWithOffset(IncrementSize),
1038 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1039 MinAlign(Alignment, IncrementSize), AAInfo);
1041 // Build a factor node to remember that this load is independent of
1043 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1046 // Move the top bits to the right place.
1048 ISD::SHL, dl, Hi.getValueType(), Hi,
1049 DAG.getConstant(RoundWidth, dl,
1050 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1052 // Join the hi and lo parts.
1053 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1055 // Big endian - avoid unaligned loads.
1056 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1057 // Load the top RoundWidth bits.
1058 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1059 LD->getPointerInfo(), RoundVT, isVolatile,
1060 isNonTemporal, isInvariant, Alignment, AAInfo);
1062 // Load the remaining ExtraWidth bits.
1063 IncrementSize = RoundWidth / 8;
1064 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1065 DAG.getConstant(IncrementSize, dl,
1066 Ptr.getValueType()));
1067 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1068 dl, Node->getValueType(0), Chain, Ptr,
1069 LD->getPointerInfo().getWithOffset(IncrementSize),
1070 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1071 MinAlign(Alignment, IncrementSize), AAInfo);
1073 // Build a factor node to remember that this load is independent of
1075 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1078 // Move the top bits to the right place.
1080 ISD::SHL, dl, Hi.getValueType(), Hi,
1081 DAG.getConstant(ExtraWidth, dl,
1082 TLI.getShiftAmountTy(Hi.getValueType(), DL)));
1084 // Join the hi and lo parts.
1085 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1090 bool isCustom = false;
1091 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1092 SrcVT.getSimpleVT())) {
1093 default: llvm_unreachable("This action is not supported yet!");
1094 case TargetLowering::Custom:
1097 case TargetLowering::Legal: {
1098 Value = SDValue(Node, 0);
1099 Chain = SDValue(Node, 1);
1102 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1103 if (Res.getNode()) {
1105 Chain = Res.getValue(1);
1108 // If this is an unaligned load and the target doesn't support it,
1110 EVT MemVT = LD->getMemoryVT();
1111 unsigned AS = LD->getAddressSpace();
1112 unsigned Align = LD->getAlignment();
1113 const DataLayout &DL = DAG.getDataLayout();
1114 if (!TLI.allowsMemoryAccess(*DAG.getContext(), DL, MemVT, AS, Align))
1115 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1119 case TargetLowering::Expand:
1120 EVT DestVT = Node->getValueType(0);
1121 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, DestVT, SrcVT)) {
1122 // If the source type is not legal, see if there is a legal extload to
1123 // an intermediate type that we can then extend further.
1124 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1125 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1126 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1127 // If we are loading a legal type, this is a non-extload followed by a
1129 ISD::LoadExtType MidExtType =
1130 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1132 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1133 SrcVT, LD->getMemOperand());
1135 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1136 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1137 Chain = Load.getValue(1);
1141 // Handle the special case of fp16 extloads. EXTLOAD doesn't have the
1142 // normal undefined upper bits behavior to allow using an in-reg extend
1143 // with the illegal FP type, so load as an integer and do the
1144 // from-integer conversion.
1145 if (SrcVT.getScalarType() == MVT::f16) {
1146 EVT ISrcVT = SrcVT.changeTypeToInteger();
1147 EVT IDestVT = DestVT.changeTypeToInteger();
1148 EVT LoadVT = TLI.getRegisterType(IDestVT.getSimpleVT());
1150 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, LoadVT,
1152 LD->getMemOperand());
1153 Value = DAG.getNode(ISD::FP16_TO_FP, dl, DestVT, Result);
1154 Chain = Result.getValue(1);
1159 assert(!SrcVT.isVector() &&
1160 "Vector Loads are handled in LegalizeVectorOps");
1162 // FIXME: This does not work for vectors on most targets. Sign-
1163 // and zero-extend operations are currently folded into extending
1164 // loads, whether they are legal or not, and then we end up here
1165 // without any support for legalizing them.
1166 assert(ExtType != ISD::EXTLOAD &&
1167 "EXTLOAD should always be supported!");
1168 // Turn the unsupported load into an EXTLOAD followed by an
1169 // explicit zero/sign extend inreg.
1170 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1171 Node->getValueType(0),
1173 LD->getMemOperand());
1175 if (ExtType == ISD::SEXTLOAD)
1176 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1177 Result.getValueType(),
1178 Result, DAG.getValueType(SrcVT));
1180 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1182 Chain = Result.getValue(1);
1187 // Since loads produce two values, make sure to remember that we legalized
1189 if (Chain.getNode() != Node) {
1190 assert(Value.getNode() != Node && "Load must be completely replaced");
1191 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1192 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1194 UpdatedNodes->insert(Value.getNode());
1195 UpdatedNodes->insert(Chain.getNode());
1201 /// Return a legal replacement for the given operation, with all legal operands.
1202 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1203 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1205 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1209 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1210 assert((TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1211 TargetLowering::TypeLegal ||
1212 TLI.isTypeLegal(Node->getValueType(i))) &&
1213 "Unexpected illegal type!");
1215 for (const SDValue &Op : Node->op_values())
1216 assert((TLI.getTypeAction(*DAG.getContext(), Op.getValueType()) ==
1217 TargetLowering::TypeLegal ||
1218 TLI.isTypeLegal(Op.getValueType()) ||
1219 Op.getOpcode() == ISD::TargetConstant) &&
1220 "Unexpected illegal type!");
1223 // Figure out the correct action; the way to query this varies by opcode
1224 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1225 bool SimpleFinishLegalizing = true;
1226 switch (Node->getOpcode()) {
1227 case ISD::INTRINSIC_W_CHAIN:
1228 case ISD::INTRINSIC_WO_CHAIN:
1229 case ISD::INTRINSIC_VOID:
1230 case ISD::STACKSAVE:
1231 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1233 case ISD::GET_DYNAMIC_AREA_OFFSET:
1234 Action = TLI.getOperationAction(Node->getOpcode(),
1235 Node->getValueType(0));
1238 Action = TLI.getOperationAction(Node->getOpcode(),
1239 Node->getValueType(0));
1240 if (Action != TargetLowering::Promote)
1241 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1243 case ISD::FP_TO_FP16:
1244 case ISD::SINT_TO_FP:
1245 case ISD::UINT_TO_FP:
1246 case ISD::EXTRACT_VECTOR_ELT:
1247 Action = TLI.getOperationAction(Node->getOpcode(),
1248 Node->getOperand(0).getValueType());
1250 case ISD::FP_ROUND_INREG:
1251 case ISD::SIGN_EXTEND_INREG: {
1252 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1253 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1256 case ISD::ATOMIC_STORE: {
1257 Action = TLI.getOperationAction(Node->getOpcode(),
1258 Node->getOperand(2).getValueType());
1261 case ISD::SELECT_CC:
1264 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1265 Node->getOpcode() == ISD::SETCC ? 2 :
1266 Node->getOpcode() == ISD::SETCCE ? 3 : 1;
1267 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1268 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1269 ISD::CondCode CCCode =
1270 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1271 Action = TLI.getCondCodeAction(CCCode, OpVT);
1272 if (Action == TargetLowering::Legal) {
1273 if (Node->getOpcode() == ISD::SELECT_CC)
1274 Action = TLI.getOperationAction(Node->getOpcode(),
1275 Node->getValueType(0));
1277 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1283 // FIXME: Model these properly. LOAD and STORE are complicated, and
1284 // STORE expects the unlegalized operand in some cases.
1285 SimpleFinishLegalizing = false;
1287 case ISD::CALLSEQ_START:
1288 case ISD::CALLSEQ_END:
1289 // FIXME: This shouldn't be necessary. These nodes have special properties
1290 // dealing with the recursive nature of legalization. Removing this
1291 // special case should be done as part of making LegalizeDAG non-recursive.
1292 SimpleFinishLegalizing = false;
1294 case ISD::EXTRACT_ELEMENT:
1295 case ISD::FLT_ROUNDS_:
1297 case ISD::MERGE_VALUES:
1298 case ISD::EH_RETURN:
1299 case ISD::FRAME_TO_ARGS_OFFSET:
1300 case ISD::EH_SJLJ_SETJMP:
1301 case ISD::EH_SJLJ_LONGJMP:
1302 case ISD::EH_SJLJ_SETUP_DISPATCH:
1303 // These operations lie about being legal: when they claim to be legal,
1304 // they should actually be expanded.
1305 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1306 if (Action == TargetLowering::Legal)
1307 Action = TargetLowering::Expand;
1309 case ISD::INIT_TRAMPOLINE:
1310 case ISD::ADJUST_TRAMPOLINE:
1311 case ISD::FRAMEADDR:
1312 case ISD::RETURNADDR:
1313 // These operations lie about being legal: when they claim to be legal,
1314 // they should actually be custom-lowered.
1315 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1316 if (Action == TargetLowering::Legal)
1317 Action = TargetLowering::Custom;
1319 case ISD::READCYCLECOUNTER:
1320 // READCYCLECOUNTER returns an i64, even if type legalization might have
1321 // expanded that to several smaller types.
1322 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64);
1324 case ISD::READ_REGISTER:
1325 case ISD::WRITE_REGISTER:
1326 // Named register is legal in the DAG, but blocked by register name
1327 // selection if not implemented by target (to chose the correct register)
1328 // They'll be converted to Copy(To/From)Reg.
1329 Action = TargetLowering::Legal;
1331 case ISD::DEBUGTRAP:
1332 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1333 if (Action == TargetLowering::Expand) {
1334 // replace ISD::DEBUGTRAP with ISD::TRAP
1336 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1337 Node->getOperand(0));
1338 ReplaceNode(Node, NewVal.getNode());
1339 LegalizeOp(NewVal.getNode());
1345 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1346 Action = TargetLowering::Legal;
1348 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1353 if (SimpleFinishLegalizing) {
1354 SDNode *NewNode = Node;
1355 switch (Node->getOpcode()) {
1362 // Legalizing shifts/rotates requires adjusting the shift amount
1363 // to the appropriate width.
1364 if (!Node->getOperand(1).getValueType().isVector()) {
1366 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1367 Node->getOperand(1));
1368 HandleSDNode Handle(SAO);
1369 LegalizeOp(SAO.getNode());
1370 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1374 case ISD::SRL_PARTS:
1375 case ISD::SRA_PARTS:
1376 case ISD::SHL_PARTS:
1377 // Legalizing shifts/rotates requires adjusting the shift amount
1378 // to the appropriate width.
1379 if (!Node->getOperand(2).getValueType().isVector()) {
1381 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1382 Node->getOperand(2));
1383 HandleSDNode Handle(SAO);
1384 LegalizeOp(SAO.getNode());
1385 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1386 Node->getOperand(1),
1392 if (NewNode != Node) {
1393 ReplaceNode(Node, NewNode);
1397 case TargetLowering::Legal:
1399 case TargetLowering::Custom: {
1400 // FIXME: The handling for custom lowering with multiple results is
1402 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1403 if (Res.getNode()) {
1404 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1407 if (Node->getNumValues() == 1) {
1408 // We can just directly replace this node with the lowered value.
1409 ReplaceNode(SDValue(Node, 0), Res);
1413 SmallVector<SDValue, 8> ResultVals;
1414 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1415 ResultVals.push_back(Res.getValue(i));
1416 ReplaceNode(Node, ResultVals.data());
1421 case TargetLowering::Expand:
1422 if (ExpandNode(Node))
1425 case TargetLowering::LibCall:
1426 ConvertNodeToLibcall(Node);
1428 case TargetLowering::Promote:
1434 switch (Node->getOpcode()) {
1441 llvm_unreachable("Do not know how to legalize this operator!");
1443 case ISD::CALLSEQ_START:
1444 case ISD::CALLSEQ_END:
1447 return LegalizeLoadOps(Node);
1450 return LegalizeStoreOps(Node);
1455 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1456 SDValue Vec = Op.getOperand(0);
1457 SDValue Idx = Op.getOperand(1);
1460 // Before we generate a new store to a temporary stack slot, see if there is
1461 // already one that we can use. There often is because when we scalarize
1462 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1463 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1464 // the vector. If all are expanded here, we don't want one store per vector
1467 // Caches for hasPredecessorHelper
1468 SmallPtrSet<const SDNode *, 32> Visited;
1469 SmallVector<const SDNode *, 16> Worklist;
1471 SDValue StackPtr, Ch;
1472 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1473 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1475 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1476 if (ST->isIndexed() || ST->isTruncatingStore() ||
1477 ST->getValue() != Vec)
1480 // Make sure that nothing else could have stored into the destination of
1482 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1485 // If the index is dependent on the store we will introduce a cycle when
1486 // creating the load (the load uses the index, and by replacing the chain
1487 // we will make the index dependent on the load).
1488 if (Idx.getNode()->hasPredecessorHelper(ST, Visited, Worklist))
1491 StackPtr = ST->getBasePtr();
1492 Ch = SDValue(ST, 0);
1497 if (!Ch.getNode()) {
1498 // Store the value to a temporary stack slot, then LOAD the returned part.
1499 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1500 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1501 MachinePointerInfo(), false, false, 0);
1504 // Add the offset to the index.
1506 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1507 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1508 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1510 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1511 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1515 if (Op.getValueType().isVector())
1516 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1517 MachinePointerInfo(), false, false, false, 0);
1519 NewLoad = DAG.getExtLoad(
1520 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1521 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1523 // Replace the chain going out of the store, by the one out of the load.
1524 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1526 // We introduced a cycle though, so update the loads operands, making sure
1527 // to use the original store's chain as an incoming chain.
1528 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1530 NewLoadOperands[0] = Ch;
1532 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1536 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1537 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1539 SDValue Vec = Op.getOperand(0);
1540 SDValue Part = Op.getOperand(1);
1541 SDValue Idx = Op.getOperand(2);
1544 // Store the value to a temporary stack slot, then LOAD the returned part.
1546 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1547 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1548 MachinePointerInfo PtrInfo =
1549 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1551 // First store the whole vector.
1552 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1555 // Then store the inserted part.
1557 // Add the offset to the index.
1559 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1561 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1562 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1563 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy(DAG.getDataLayout()));
1565 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1568 // Store the subvector.
1569 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1570 MachinePointerInfo(), false, false, 0);
1572 // Finally, load the updated vector.
1573 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1574 false, false, false, 0);
1577 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1578 // We can't handle this case efficiently. Allocate a sufficiently
1579 // aligned object on the stack, store each element into it, then load
1580 // the result as a vector.
1581 // Create the stack frame object.
1582 EVT VT = Node->getValueType(0);
1583 EVT EltVT = VT.getVectorElementType();
1585 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1586 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1587 MachinePointerInfo PtrInfo =
1588 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
1590 // Emit a store of each element to the stack slot.
1591 SmallVector<SDValue, 8> Stores;
1592 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1593 // Store (in the right endianness) the elements to memory.
1594 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1595 // Ignore undef elements.
1596 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1598 unsigned Offset = TypeByteSize*i;
1600 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1601 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1603 // If the destination vector element type is narrower than the source
1604 // element type, only store the bits necessary.
1605 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1606 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1607 Node->getOperand(i), Idx,
1608 PtrInfo.getWithOffset(Offset),
1609 EltVT, false, false, 0));
1611 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1612 Node->getOperand(i), Idx,
1613 PtrInfo.getWithOffset(Offset),
1618 if (!Stores.empty()) // Not all undef elements?
1619 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1621 StoreChain = DAG.getEntryNode();
1623 // Result is a load from the stack slot.
1624 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1625 false, false, false, 0);
1629 /// Keeps track of state when getting the sign of a floating-point value as an
1631 struct FloatSignAsInt {
1636 MachinePointerInfo IntPointerInfo;
1637 MachinePointerInfo FloatPointerInfo;
1644 /// Bitcast a floating-point value to an integer value. Only bitcast the part
1645 /// containing the sign bit if the target has no integer value capable of
1646 /// holding all bits of the floating-point value.
1647 void SelectionDAGLegalize::getSignAsIntValue(FloatSignAsInt &State,
1648 SDLoc DL, SDValue Value) const {
1649 EVT FloatVT = Value.getValueType();
1650 unsigned NumBits = FloatVT.getSizeInBits();
1651 State.FloatVT = FloatVT;
1652 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), NumBits);
1653 // Convert to an integer of the same size.
1654 if (TLI.isTypeLegal(IVT)) {
1655 State.IntValue = DAG.getNode(ISD::BITCAST, DL, IVT, Value);
1656 State.SignMask = APInt::getSignBit(NumBits);
1657 State.SignBit = NumBits - 1;
1661 auto &DataLayout = DAG.getDataLayout();
1662 // Store the float to memory, then load the sign part out as an integer.
1663 MVT LoadTy = TLI.getRegisterType(*DAG.getContext(), MVT::i8);
1664 // First create a temporary that is aligned for both the load and store.
1665 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1666 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1667 // Then store the float to it.
1668 State.FloatPtr = StackPtr;
1669 MachineFunction &MF = DAG.getMachineFunction();
1670 State.FloatPointerInfo = MachinePointerInfo::getFixedStack(MF, FI);
1671 State.Chain = DAG.getStore(DAG.getEntryNode(), DL, Value, State.FloatPtr,
1672 State.FloatPointerInfo, false, false, 0);
1675 if (DataLayout.isBigEndian()) {
1676 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1677 // Load out a legal integer with the same sign bit as the float.
1679 State.IntPointerInfo = State.FloatPointerInfo;
1681 // Advance the pointer so that the loaded byte will contain the sign bit.
1682 unsigned ByteOffset = (FloatVT.getSizeInBits() / 8) - 1;
1683 IntPtr = DAG.getNode(ISD::ADD, DL, StackPtr.getValueType(), StackPtr,
1684 DAG.getConstant(ByteOffset, DL, StackPtr.getValueType()));
1685 State.IntPointerInfo = MachinePointerInfo::getFixedStack(MF, FI,
1689 State.IntPtr = IntPtr;
1690 State.IntValue = DAG.getExtLoad(ISD::EXTLOAD, DL, LoadTy, State.Chain,
1691 IntPtr, State.IntPointerInfo, MVT::i8,
1692 false, false, false, 0);
1693 State.SignMask = APInt::getOneBitSet(LoadTy.getSizeInBits(), 7);
1697 /// Replace the integer value produced by getSignAsIntValue() with a new value
1698 /// and cast the result back to a floating-point type.
1699 SDValue SelectionDAGLegalize::modifySignAsInt(const FloatSignAsInt &State,
1700 SDLoc DL, SDValue NewIntValue) const {
1702 return DAG.getNode(ISD::BITCAST, DL, State.FloatVT, NewIntValue);
1704 // Override the part containing the sign bit in the value stored on the stack.
1705 SDValue Chain = DAG.getTruncStore(State.Chain, DL, NewIntValue, State.IntPtr,
1706 State.IntPointerInfo, MVT::i8, false, false,
1708 return DAG.getLoad(State.FloatVT, DL, Chain, State.FloatPtr,
1709 State.FloatPointerInfo, false, false, false, 0);
1712 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode *Node) const {
1714 SDValue Mag = Node->getOperand(0);
1715 SDValue Sign = Node->getOperand(1);
1717 // Get sign bit into an integer value.
1718 FloatSignAsInt SignAsInt;
1719 getSignAsIntValue(SignAsInt, DL, Sign);
1721 EVT IntVT = SignAsInt.IntValue.getValueType();
1722 SDValue SignMask = DAG.getConstant(SignAsInt.SignMask, DL, IntVT);
1723 SDValue SignBit = DAG.getNode(ISD::AND, DL, IntVT, SignAsInt.IntValue,
1726 // If FABS is legal transform FCOPYSIGN(x, y) => sign(x) ? -FABS(x) : FABS(X)
1727 EVT FloatVT = Mag.getValueType();
1728 if (TLI.isOperationLegalOrCustom(ISD::FABS, FloatVT) &&
1729 TLI.isOperationLegalOrCustom(ISD::FNEG, FloatVT)) {
1730 SDValue AbsValue = DAG.getNode(ISD::FABS, DL, FloatVT, Mag);
1731 SDValue NegValue = DAG.getNode(ISD::FNEG, DL, FloatVT, AbsValue);
1732 SDValue Cond = DAG.getSetCC(DL, getSetCCResultType(IntVT), SignBit,
1733 DAG.getConstant(0, DL, IntVT), ISD::SETNE);
1734 return DAG.getSelect(DL, FloatVT, Cond, NegValue, AbsValue);
1737 // Transform Mag value to integer, and clear the sign bit.
1738 FloatSignAsInt MagAsInt;
1739 getSignAsIntValue(MagAsInt, DL, Mag);
1740 EVT MagVT = MagAsInt.IntValue.getValueType();
1741 SDValue ClearSignMask = DAG.getConstant(~MagAsInt.SignMask, DL, MagVT);
1742 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, MagVT, MagAsInt.IntValue,
1745 // Get the signbit at the right position for MagAsInt.
1746 int ShiftAmount = SignAsInt.SignBit - MagAsInt.SignBit;
1747 if (SignBit.getValueSizeInBits() > ClearedSign.getValueSizeInBits()) {
1748 if (ShiftAmount > 0) {
1749 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, IntVT);
1750 SignBit = DAG.getNode(ISD::SRL, DL, IntVT, SignBit, ShiftCnst);
1751 } else if (ShiftAmount < 0) {
1752 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, IntVT);
1753 SignBit = DAG.getNode(ISD::SHL, DL, IntVT, SignBit, ShiftCnst);
1755 SignBit = DAG.getNode(ISD::TRUNCATE, DL, MagVT, SignBit);
1756 } else if (SignBit.getValueSizeInBits() < ClearedSign.getValueSizeInBits()) {
1757 SignBit = DAG.getNode(ISD::ZERO_EXTEND, DL, MagVT, SignBit);
1758 if (ShiftAmount > 0) {
1759 SDValue ShiftCnst = DAG.getConstant(ShiftAmount, DL, MagVT);
1760 SignBit = DAG.getNode(ISD::SRL, DL, MagVT, SignBit, ShiftCnst);
1761 } else if (ShiftAmount < 0) {
1762 SDValue ShiftCnst = DAG.getConstant(-ShiftAmount, DL, MagVT);
1763 SignBit = DAG.getNode(ISD::SHL, DL, MagVT, SignBit, ShiftCnst);
1767 // Store the part with the modified sign and convert back to float.
1768 SDValue CopiedSign = DAG.getNode(ISD::OR, DL, MagVT, ClearedSign, SignBit);
1769 return modifySignAsInt(MagAsInt, DL, CopiedSign);
1772 SDValue SelectionDAGLegalize::ExpandFABS(SDNode *Node) const {
1774 SDValue Value = Node->getOperand(0);
1776 // Transform FABS(x) => FCOPYSIGN(x, 0.0) if FCOPYSIGN is legal.
1777 EVT FloatVT = Value.getValueType();
1778 if (TLI.isOperationLegalOrCustom(ISD::FCOPYSIGN, FloatVT)) {
1779 SDValue Zero = DAG.getConstantFP(0.0, DL, FloatVT);
1780 return DAG.getNode(ISD::FCOPYSIGN, DL, FloatVT, Value, Zero);
1783 // Transform value to integer, clear the sign bit and transform back.
1784 FloatSignAsInt ValueAsInt;
1785 getSignAsIntValue(ValueAsInt, DL, Value);
1786 EVT IntVT = ValueAsInt.IntValue.getValueType();
1787 SDValue ClearSignMask = DAG.getConstant(~ValueAsInt.SignMask, DL, IntVT);
1788 SDValue ClearedSign = DAG.getNode(ISD::AND, DL, IntVT, ValueAsInt.IntValue,
1790 return modifySignAsInt(ValueAsInt, DL, ClearedSign);
1793 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1794 SmallVectorImpl<SDValue> &Results) {
1795 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1796 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1797 " not tell us which reg is the stack pointer!");
1799 EVT VT = Node->getValueType(0);
1800 SDValue Tmp1 = SDValue(Node, 0);
1801 SDValue Tmp2 = SDValue(Node, 1);
1802 SDValue Tmp3 = Node->getOperand(2);
1803 SDValue Chain = Tmp1.getOperand(0);
1805 // Chain the dynamic stack allocation so that it doesn't modify the stack
1806 // pointer when other instructions are using the stack.
1807 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1809 SDValue Size = Tmp2.getOperand(1);
1810 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1811 Chain = SP.getValue(1);
1812 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1813 unsigned StackAlign =
1814 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1815 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1816 if (Align > StackAlign)
1817 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1818 DAG.getConstant(-(uint64_t)Align, dl, VT));
1819 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1821 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1822 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1824 Results.push_back(Tmp1);
1825 Results.push_back(Tmp2);
1828 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1831 /// If the SETCC has been legalized using AND / OR, then the legalized node
1832 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1833 /// will be set to false.
1835 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1836 /// then the values of LHS and RHS will be swapped, CC will be set to the
1837 /// new condition, and NeedInvert will be set to false.
1839 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1840 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1841 /// will be set to true. The caller must invert the result of the SETCC with
1842 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1843 /// of a true/false result.
1845 /// \returns true if the SetCC has been legalized, false if it hasn't.
1846 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1847 SDValue &LHS, SDValue &RHS,
1851 MVT OpVT = LHS.getSimpleValueType();
1852 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1854 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1855 default: llvm_unreachable("Unknown condition code action!");
1856 case TargetLowering::Legal:
1859 case TargetLowering::Expand: {
1860 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1861 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1862 std::swap(LHS, RHS);
1863 CC = DAG.getCondCode(InvCC);
1866 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1869 default: llvm_unreachable("Don't know how to expand this condition!");
1871 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1872 == TargetLowering::Legal
1873 && "If SETO is expanded, SETOEQ must be legal!");
1874 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1876 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1877 == TargetLowering::Legal
1878 && "If SETUO is expanded, SETUNE must be legal!");
1879 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1892 // If we are floating point, assign and break, otherwise fall through.
1893 if (!OpVT.isInteger()) {
1894 // We can use the 4th bit to tell if we are the unordered
1895 // or ordered version of the opcode.
1896 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1897 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1898 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1901 // Fallthrough if we are unsigned integer.
1906 // We only support using the inverted operation, which is computed above
1907 // and not a different manner of supporting expanding these cases.
1908 llvm_unreachable("Don't know how to expand this condition!");
1911 // Try inverting the result of the inverse condition.
1912 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1913 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1914 CC = DAG.getCondCode(InvCC);
1918 // If inverting the condition didn't work then we have no means to expand
1920 llvm_unreachable("Don't know how to expand this condition!");
1923 SDValue SetCC1, SetCC2;
1924 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1925 // If we aren't the ordered or unorder operation,
1926 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1927 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1928 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1930 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1931 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1932 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1934 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1943 /// Emit a store/load combination to the stack. This stores
1944 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1945 /// a load from the stack slot to DestVT, extending it if needed.
1946 /// The resultant code need not be legal.
1947 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1951 // Create the stack frame object.
1952 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1953 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1954 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1956 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1957 int SPFI = StackPtrFI->getIndex();
1958 MachinePointerInfo PtrInfo =
1959 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI);
1961 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1962 unsigned SlotSize = SlotVT.getSizeInBits();
1963 unsigned DestSize = DestVT.getSizeInBits();
1964 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1965 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1967 // Emit a store to the stack slot. Use a truncstore if the input value is
1968 // later than DestVT.
1971 if (SrcSize > SlotSize)
1972 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1973 PtrInfo, SlotVT, false, false, SrcAlign);
1975 assert(SrcSize == SlotSize && "Invalid store");
1976 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1977 PtrInfo, false, false, SrcAlign);
1980 // Result is a load from the stack slot.
1981 if (SlotSize == DestSize)
1982 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1983 false, false, false, DestAlign);
1985 assert(SlotSize < DestSize && "Unknown extension!");
1986 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1987 PtrInfo, SlotVT, false, false, false, DestAlign);
1990 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1992 // Create a vector sized/aligned stack slot, store the value to element #0,
1993 // then load the whole vector back out.
1994 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1996 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1997 int SPFI = StackPtrFI->getIndex();
1999 SDValue Ch = DAG.getTruncStore(
2000 DAG.getEntryNode(), dl, Node->getOperand(0), StackPtr,
2001 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI),
2002 Node->getValueType(0).getVectorElementType(), false, false, 0);
2004 Node->getValueType(0), dl, Ch, StackPtr,
2005 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), SPFI), false,
2010 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
2011 const TargetLowering &TLI, SDValue &Res) {
2012 unsigned NumElems = Node->getNumOperands();
2014 EVT VT = Node->getValueType(0);
2016 // Try to group the scalars into pairs, shuffle the pairs together, then
2017 // shuffle the pairs of pairs together, etc. until the vector has
2018 // been built. This will work only if all of the necessary shuffle masks
2021 // We do this in two phases; first to check the legality of the shuffles,
2022 // and next, assuming that all shuffles are legal, to create the new nodes.
2023 for (int Phase = 0; Phase < 2; ++Phase) {
2024 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
2026 for (unsigned i = 0; i < NumElems; ++i) {
2027 SDValue V = Node->getOperand(i);
2028 if (V.getOpcode() == ISD::UNDEF)
2033 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
2034 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
2037 while (IntermedVals.size() > 2) {
2038 NewIntermedVals.clear();
2039 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
2040 // This vector and the next vector are shuffled together (simply to
2041 // append the one to the other).
2042 SmallVector<int, 16> ShuffleVec(NumElems, -1);
2044 SmallVector<int, 16> FinalIndices;
2045 FinalIndices.reserve(IntermedVals[i].second.size() +
2046 IntermedVals[i+1].second.size());
2049 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
2052 FinalIndices.push_back(IntermedVals[i].second[j]);
2054 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
2056 ShuffleVec[k] = NumElems + j;
2057 FinalIndices.push_back(IntermedVals[i+1].second[j]);
2062 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
2063 IntermedVals[i+1].first,
2065 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
2067 NewIntermedVals.push_back(
2068 std::make_pair(Shuffle, std::move(FinalIndices)));
2071 // If we had an odd number of defined values, then append the last
2072 // element to the array of new vectors.
2073 if ((IntermedVals.size() & 1) != 0)
2074 NewIntermedVals.push_back(IntermedVals.back());
2076 IntermedVals.swap(NewIntermedVals);
2079 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
2080 "Invalid number of intermediate vectors");
2081 SDValue Vec1 = IntermedVals[0].first;
2083 if (IntermedVals.size() > 1)
2084 Vec2 = IntermedVals[1].first;
2086 Vec2 = DAG.getUNDEF(VT);
2088 SmallVector<int, 16> ShuffleVec(NumElems, -1);
2089 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
2090 ShuffleVec[IntermedVals[0].second[i]] = i;
2091 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
2092 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
2095 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2096 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
2103 /// Expand a BUILD_VECTOR node on targets that don't
2104 /// support the operation, but do support the resultant vector type.
2105 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2106 unsigned NumElems = Node->getNumOperands();
2107 SDValue Value1, Value2;
2109 EVT VT = Node->getValueType(0);
2110 EVT OpVT = Node->getOperand(0).getValueType();
2111 EVT EltVT = VT.getVectorElementType();
2113 // If the only non-undef value is the low element, turn this into a
2114 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
2115 bool isOnlyLowElement = true;
2116 bool MoreThanTwoValues = false;
2117 bool isConstant = true;
2118 for (unsigned i = 0; i < NumElems; ++i) {
2119 SDValue V = Node->getOperand(i);
2120 if (V.getOpcode() == ISD::UNDEF)
2123 isOnlyLowElement = false;
2124 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2127 if (!Value1.getNode()) {
2129 } else if (!Value2.getNode()) {
2132 } else if (V != Value1 && V != Value2) {
2133 MoreThanTwoValues = true;
2137 if (!Value1.getNode())
2138 return DAG.getUNDEF(VT);
2140 if (isOnlyLowElement)
2141 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2143 // If all elements are constants, create a load from the constant pool.
2145 SmallVector<Constant*, 16> CV;
2146 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2147 if (ConstantFPSDNode *V =
2148 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2149 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2150 } else if (ConstantSDNode *V =
2151 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2153 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2155 // If OpVT and EltVT don't match, EltVT is not legal and the
2156 // element values have been promoted/truncated earlier. Undo this;
2157 // we don't want a v16i8 to become a v16i32 for example.
2158 const ConstantInt *CI = V->getConstantIntValue();
2159 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2160 CI->getZExtValue()));
2163 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2164 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2165 CV.push_back(UndefValue::get(OpNTy));
2168 Constant *CP = ConstantVector::get(CV);
2170 DAG.getConstantPool(CP, TLI.getPointerTy(DAG.getDataLayout()));
2171 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2173 VT, dl, DAG.getEntryNode(), CPIdx,
2174 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2175 false, false, Alignment);
2178 SmallSet<SDValue, 16> DefinedValues;
2179 for (unsigned i = 0; i < NumElems; ++i) {
2180 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2182 DefinedValues.insert(Node->getOperand(i));
2185 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2186 if (!MoreThanTwoValues) {
2187 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2188 for (unsigned i = 0; i < NumElems; ++i) {
2189 SDValue V = Node->getOperand(i);
2190 if (V.getOpcode() == ISD::UNDEF)
2192 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2194 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2195 // Get the splatted value into the low element of a vector register.
2196 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2198 if (Value2.getNode())
2199 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2201 Vec2 = DAG.getUNDEF(VT);
2203 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2204 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2208 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2213 // Otherwise, we can't handle this case efficiently.
2214 return ExpandVectorBuildThroughStack(Node);
2217 // Expand a node into a call to a libcall. If the result value
2218 // does not fit into a register, return the lo part and set the hi part to the
2219 // by-reg argument. If it does fit into a single register, return the result
2220 // and leave the Hi part unset.
2221 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2223 TargetLowering::ArgListTy Args;
2224 TargetLowering::ArgListEntry Entry;
2225 for (const SDValue &Op : Node->op_values()) {
2226 EVT ArgVT = Op.getValueType();
2227 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2230 Entry.isSExt = isSigned;
2231 Entry.isZExt = !isSigned;
2232 Args.push_back(Entry);
2234 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2235 TLI.getPointerTy(DAG.getDataLayout()));
2237 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2239 // By default, the input chain to this libcall is the entry node of the
2240 // function. If the libcall is going to be emitted as a tail call then
2241 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2242 // node which is being folded has a non-entry input chain.
2243 SDValue InChain = DAG.getEntryNode();
2245 // isTailCall may be true since the callee does not reference caller stack
2246 // frame. Check if it's in the right position.
2247 SDValue TCChain = InChain;
2248 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2252 TargetLowering::CallLoweringInfo CLI(DAG);
2253 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2254 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2255 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2257 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2259 if (!CallInfo.second.getNode())
2260 // It's a tailcall, return the chain (which is the DAG root).
2261 return DAG.getRoot();
2263 return CallInfo.first;
2266 /// Generate a libcall taking the given operands as arguments
2267 /// and returning a result of type RetVT.
2268 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2269 const SDValue *Ops, unsigned NumOps,
2270 bool isSigned, SDLoc dl) {
2271 TargetLowering::ArgListTy Args;
2272 Args.reserve(NumOps);
2274 TargetLowering::ArgListEntry Entry;
2275 for (unsigned i = 0; i != NumOps; ++i) {
2276 Entry.Node = Ops[i];
2277 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2278 Entry.isSExt = isSigned;
2279 Entry.isZExt = !isSigned;
2280 Args.push_back(Entry);
2282 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2283 TLI.getPointerTy(DAG.getDataLayout()));
2285 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2287 TargetLowering::CallLoweringInfo CLI(DAG);
2288 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2289 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2290 .setSExtResult(isSigned).setZExtResult(!isSigned);
2292 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2294 return CallInfo.first;
2297 // Expand a node into a call to a libcall. Similar to
2298 // ExpandLibCall except that the first operand is the in-chain.
2299 std::pair<SDValue, SDValue>
2300 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2303 SDValue InChain = Node->getOperand(0);
2305 TargetLowering::ArgListTy Args;
2306 TargetLowering::ArgListEntry Entry;
2307 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2308 EVT ArgVT = Node->getOperand(i).getValueType();
2309 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2310 Entry.Node = Node->getOperand(i);
2312 Entry.isSExt = isSigned;
2313 Entry.isZExt = !isSigned;
2314 Args.push_back(Entry);
2316 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2317 TLI.getPointerTy(DAG.getDataLayout()));
2319 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2321 TargetLowering::CallLoweringInfo CLI(DAG);
2322 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2323 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2324 .setSExtResult(isSigned).setZExtResult(!isSigned);
2326 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2331 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2332 RTLIB::Libcall Call_F32,
2333 RTLIB::Libcall Call_F64,
2334 RTLIB::Libcall Call_F80,
2335 RTLIB::Libcall Call_F128,
2336 RTLIB::Libcall Call_PPCF128) {
2338 switch (Node->getSimpleValueType(0).SimpleTy) {
2339 default: llvm_unreachable("Unexpected request for libcall!");
2340 case MVT::f32: LC = Call_F32; break;
2341 case MVT::f64: LC = Call_F64; break;
2342 case MVT::f80: LC = Call_F80; break;
2343 case MVT::f128: LC = Call_F128; break;
2344 case MVT::ppcf128: LC = Call_PPCF128; break;
2346 return ExpandLibCall(LC, Node, false);
2349 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2350 RTLIB::Libcall Call_I8,
2351 RTLIB::Libcall Call_I16,
2352 RTLIB::Libcall Call_I32,
2353 RTLIB::Libcall Call_I64,
2354 RTLIB::Libcall Call_I128) {
2356 switch (Node->getSimpleValueType(0).SimpleTy) {
2357 default: llvm_unreachable("Unexpected request for libcall!");
2358 case MVT::i8: LC = Call_I8; break;
2359 case MVT::i16: LC = Call_I16; break;
2360 case MVT::i32: LC = Call_I32; break;
2361 case MVT::i64: LC = Call_I64; break;
2362 case MVT::i128: LC = Call_I128; break;
2364 return ExpandLibCall(LC, Node, isSigned);
2367 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2369 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2370 SmallVectorImpl<SDValue> &Results) {
2371 unsigned Opcode = Node->getOpcode();
2372 bool isSigned = Opcode == ISD::SDIVREM;
2375 switch (Node->getSimpleValueType(0).SimpleTy) {
2376 default: llvm_unreachable("Unexpected request for libcall!");
2377 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2378 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2379 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2380 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2381 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2384 // The input chain to this libcall is the entry node of the function.
2385 // Legalizing the call will automatically add the previous call to the
2387 SDValue InChain = DAG.getEntryNode();
2389 EVT RetVT = Node->getValueType(0);
2390 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2392 TargetLowering::ArgListTy Args;
2393 TargetLowering::ArgListEntry Entry;
2394 for (const SDValue &Op : Node->op_values()) {
2395 EVT ArgVT = Op.getValueType();
2396 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2399 Entry.isSExt = isSigned;
2400 Entry.isZExt = !isSigned;
2401 Args.push_back(Entry);
2404 // Also pass the return address of the remainder.
2405 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2407 Entry.Ty = RetTy->getPointerTo();
2408 Entry.isSExt = isSigned;
2409 Entry.isZExt = !isSigned;
2410 Args.push_back(Entry);
2412 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2413 TLI.getPointerTy(DAG.getDataLayout()));
2416 TargetLowering::CallLoweringInfo CLI(DAG);
2417 CLI.setDebugLoc(dl).setChain(InChain)
2418 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2419 .setSExtResult(isSigned).setZExtResult(!isSigned);
2421 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2423 // Remainder is loaded back from the stack frame.
2424 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2425 MachinePointerInfo(), false, false, false, 0);
2426 Results.push_back(CallInfo.first);
2427 Results.push_back(Rem);
2430 /// Return true if sincos libcall is available.
2431 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2433 switch (Node->getSimpleValueType(0).SimpleTy) {
2434 default: llvm_unreachable("Unexpected request for libcall!");
2435 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2436 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2437 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2438 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2439 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2441 return TLI.getLibcallName(LC) != nullptr;
2444 /// Return true if sincos libcall is available and can be used to combine sin
2446 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2447 const TargetMachine &TM) {
2448 if (!isSinCosLibcallAvailable(Node, TLI))
2450 // GNU sin/cos functions set errno while sincos does not. Therefore
2451 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2452 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2453 if (isGNU && !TM.Options.UnsafeFPMath)
2458 /// Only issue sincos libcall if both sin and cos are needed.
2459 static bool useSinCos(SDNode *Node) {
2460 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2461 ? ISD::FCOS : ISD::FSIN;
2463 SDValue Op0 = Node->getOperand(0);
2464 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2465 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2469 // The other user might have been turned into sincos already.
2470 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2476 /// Issue libcalls to sincos to compute sin / cos pairs.
2478 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2479 SmallVectorImpl<SDValue> &Results) {
2481 switch (Node->getSimpleValueType(0).SimpleTy) {
2482 default: llvm_unreachable("Unexpected request for libcall!");
2483 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2484 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2485 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2486 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2487 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2490 // The input chain to this libcall is the entry node of the function.
2491 // Legalizing the call will automatically add the previous call to the
2493 SDValue InChain = DAG.getEntryNode();
2495 EVT RetVT = Node->getValueType(0);
2496 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2498 TargetLowering::ArgListTy Args;
2499 TargetLowering::ArgListEntry Entry;
2501 // Pass the argument.
2502 Entry.Node = Node->getOperand(0);
2504 Entry.isSExt = false;
2505 Entry.isZExt = false;
2506 Args.push_back(Entry);
2508 // Pass the return address of sin.
2509 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2510 Entry.Node = SinPtr;
2511 Entry.Ty = RetTy->getPointerTo();
2512 Entry.isSExt = false;
2513 Entry.isZExt = false;
2514 Args.push_back(Entry);
2516 // Also pass the return address of the cos.
2517 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2518 Entry.Node = CosPtr;
2519 Entry.Ty = RetTy->getPointerTo();
2520 Entry.isSExt = false;
2521 Entry.isZExt = false;
2522 Args.push_back(Entry);
2524 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2525 TLI.getPointerTy(DAG.getDataLayout()));
2528 TargetLowering::CallLoweringInfo CLI(DAG);
2529 CLI.setDebugLoc(dl).setChain(InChain)
2530 .setCallee(TLI.getLibcallCallingConv(LC),
2531 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2533 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2535 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2536 MachinePointerInfo(), false, false, false, 0));
2537 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2538 MachinePointerInfo(), false, false, false, 0));
2541 /// This function is responsible for legalizing a
2542 /// INT_TO_FP operation of the specified operand when the target requests that
2543 /// we expand it. At this point, we know that the result and operand types are
2544 /// legal for the target.
2545 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2549 // TODO: Should any fast-math-flags be set for the created nodes?
2551 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2552 // simple 32-bit [signed|unsigned] integer to float/double expansion
2554 // Get the stack frame index of a 8 byte buffer.
2555 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2557 // word offset constant for Hi/Lo address computation
2558 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2559 StackSlot.getValueType());
2560 // set up Hi and Lo (into buffer) address based on endian
2561 SDValue Hi = StackSlot;
2562 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2563 StackSlot, WordOff);
2564 if (DAG.getDataLayout().isLittleEndian())
2567 // if signed map to unsigned space
2570 // constant used to invert sign bit (signed to unsigned mapping)
2571 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2572 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2576 // store the lo of the constructed double - based on integer input
2577 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2578 Op0Mapped, Lo, MachinePointerInfo(),
2580 // initial hi portion of constructed double
2581 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2582 // store the hi of the constructed double - biased exponent
2583 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2584 MachinePointerInfo(),
2586 // load the constructed double
2587 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2588 MachinePointerInfo(), false, false, false, 0);
2589 // FP constant to bias correct the final result
2590 SDValue Bias = DAG.getConstantFP(isSigned ?
2591 BitsToDouble(0x4330000080000000ULL) :
2592 BitsToDouble(0x4330000000000000ULL),
2594 // subtract the bias
2595 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2598 // handle final rounding
2599 if (DestVT == MVT::f64) {
2602 } else if (DestVT.bitsLT(MVT::f64)) {
2603 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2604 DAG.getIntPtrConstant(0, dl));
2605 } else if (DestVT.bitsGT(MVT::f64)) {
2606 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2610 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2611 // Code below here assumes !isSigned without checking again.
2613 // Implementation of unsigned i64 to f64 following the algorithm in
2614 // __floatundidf in compiler_rt. This implementation has the advantage
2615 // of performing rounding correctly, both in the default rounding mode
2616 // and in all alternate rounding modes.
2617 // TODO: Generalize this for use with other types.
2618 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2620 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2621 SDValue TwoP84PlusTwoP52 =
2622 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2625 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2627 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2628 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2629 DAG.getConstant(32, dl, MVT::i64));
2630 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2631 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2632 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2633 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2634 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2636 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2639 // Implementation of unsigned i64 to f32.
2640 // TODO: Generalize this for use with other types.
2641 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2642 // For unsigned conversions, convert them to signed conversions using the
2643 // algorithm from the x86_64 __floatundidf in compiler_rt.
2645 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2647 SDValue ShiftConst = DAG.getConstant(
2648 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
2649 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2650 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2651 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2652 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2654 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2655 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2657 // TODO: This really should be implemented using a branch rather than a
2658 // select. We happen to get lucky and machinesink does the right
2659 // thing most of the time. This would be a good candidate for a
2660 //pseudo-op, or, even better, for whole-function isel.
2661 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2662 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2663 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2666 // Otherwise, implement the fully general conversion.
2668 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2669 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2670 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2671 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2672 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2673 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2674 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2675 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2677 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2678 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2679 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2682 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2683 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType(), DAG.getDataLayout());
2685 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2686 DAG.getConstant(32, dl, SHVT));
2687 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2688 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2690 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2692 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2693 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2694 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2695 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2696 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2697 DAG.getIntPtrConstant(0, dl));
2700 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2702 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2704 DAG.getConstant(0, dl, Op0.getValueType()),
2706 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2707 Four = DAG.getIntPtrConstant(4, dl);
2708 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2709 SignSet, Four, Zero);
2711 // If the sign bit of the integer is set, the large number will be treated
2712 // as a negative number. To counteract this, the dynamic code adds an
2713 // offset depending on the data type.
2715 switch (Op0.getSimpleValueType().SimpleTy) {
2716 default: llvm_unreachable("Unsupported integer type!");
2717 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2718 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2719 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2720 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2722 if (DAG.getDataLayout().isLittleEndian())
2724 Constant *FudgeFactor = ConstantInt::get(
2725 Type::getInt64Ty(*DAG.getContext()), FF);
2728 DAG.getConstantPool(FudgeFactor, TLI.getPointerTy(DAG.getDataLayout()));
2729 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2730 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2731 Alignment = std::min(Alignment, 4u);
2733 if (DestVT == MVT::f32)
2734 FudgeInReg = DAG.getLoad(
2735 MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2736 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2737 false, false, Alignment);
2739 SDValue Load = DAG.getExtLoad(
2740 ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx,
2741 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), MVT::f32,
2742 false, false, false, Alignment);
2743 HandleSDNode Handle(Load);
2744 LegalizeOp(Load.getNode());
2745 FudgeInReg = Handle.getValue();
2748 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2751 /// This function is responsible for legalizing a
2752 /// *INT_TO_FP operation of the specified operand when the target requests that
2753 /// we promote it. At this point, we know that the result and operand types are
2754 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2755 /// operation that takes a larger input.
2756 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2760 // First step, figure out the appropriate *INT_TO_FP operation to use.
2761 EVT NewInTy = LegalOp.getValueType();
2763 unsigned OpToUse = 0;
2765 // Scan for the appropriate larger type to use.
2767 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2768 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2770 // If the target supports SINT_TO_FP of this type, use it.
2771 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2772 OpToUse = ISD::SINT_TO_FP;
2775 if (isSigned) continue;
2777 // If the target supports UINT_TO_FP of this type, use it.
2778 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2779 OpToUse = ISD::UINT_TO_FP;
2783 // Otherwise, try a larger type.
2786 // Okay, we found the operation and type to use. Zero extend our input to the
2787 // desired type then run the operation on it.
2788 return DAG.getNode(OpToUse, dl, DestVT,
2789 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2790 dl, NewInTy, LegalOp));
2793 /// This function is responsible for legalizing a
2794 /// FP_TO_*INT operation of the specified operand when the target requests that
2795 /// we promote it. At this point, we know that the result and operand types are
2796 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2797 /// operation that returns a larger result.
2798 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2802 // First step, figure out the appropriate FP_TO*INT operation to use.
2803 EVT NewOutTy = DestVT;
2805 unsigned OpToUse = 0;
2807 // Scan for the appropriate larger type to use.
2809 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2810 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2812 // A larger signed type can hold all unsigned values of the requested type,
2813 // so using FP_TO_SINT is valid
2814 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2815 OpToUse = ISD::FP_TO_SINT;
2819 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2820 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2821 OpToUse = ISD::FP_TO_UINT;
2825 // Otherwise, try a larger type.
2829 // Okay, we found the operation and type to use.
2830 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2832 // Truncate the result of the extended FP_TO_*INT operation to the desired
2834 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2837 /// Open code the operations for BITREVERSE.
2838 SDValue SelectionDAGLegalize::ExpandBITREVERSE(SDValue Op, SDLoc dl) {
2839 EVT VT = Op.getValueType();
2840 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2841 unsigned Sz = VT.getScalarSizeInBits();
2844 Tmp = DAG.getConstant(0, dl, VT);
2845 for (unsigned I = 0, J = Sz-1; I < Sz; ++I, --J) {
2848 DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(J - I, dl, SHVT));
2851 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
2854 Shift = Shift.shl(J);
2855 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
2856 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
2862 /// Open code the operations for BSWAP of the specified operation.
2863 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2864 EVT VT = Op.getValueType();
2865 EVT SHVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2866 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2867 switch (VT.getSimpleVT().SimpleTy) {
2868 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2870 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2871 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2872 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2874 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2875 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2876 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2877 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2878 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2879 DAG.getConstant(0xFF0000, dl, VT));
2880 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2881 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2882 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2883 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2885 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2886 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2887 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2888 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2889 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2890 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2891 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2892 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2893 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2894 DAG.getConstant(255ULL<<48, dl, VT));
2895 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2896 DAG.getConstant(255ULL<<40, dl, VT));
2897 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2898 DAG.getConstant(255ULL<<32, dl, VT));
2899 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2900 DAG.getConstant(255ULL<<24, dl, VT));
2901 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2902 DAG.getConstant(255ULL<<16, dl, VT));
2903 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2904 DAG.getConstant(255ULL<<8 , dl, VT));
2905 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2906 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2907 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2908 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2909 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2910 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2911 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2915 /// Expand the specified bitcount instruction into operations.
2916 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2919 default: llvm_unreachable("Cannot expand this yet!");
2921 EVT VT = Op.getValueType();
2922 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2923 unsigned Len = VT.getSizeInBits();
2925 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2926 "CTPOP not implemented for this type.");
2928 // This is the "best" algorithm from
2929 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2931 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2933 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2935 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2937 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2940 // v = v - ((v >> 1) & 0x55555555...)
2941 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2942 DAG.getNode(ISD::AND, dl, VT,
2943 DAG.getNode(ISD::SRL, dl, VT, Op,
2944 DAG.getConstant(1, dl, ShVT)),
2946 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2947 Op = DAG.getNode(ISD::ADD, dl, VT,
2948 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2949 DAG.getNode(ISD::AND, dl, VT,
2950 DAG.getNode(ISD::SRL, dl, VT, Op,
2951 DAG.getConstant(2, dl, ShVT)),
2953 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2954 Op = DAG.getNode(ISD::AND, dl, VT,
2955 DAG.getNode(ISD::ADD, dl, VT, Op,
2956 DAG.getNode(ISD::SRL, dl, VT, Op,
2957 DAG.getConstant(4, dl, ShVT))),
2959 // v = (v * 0x01010101...) >> (Len - 8)
2960 Op = DAG.getNode(ISD::SRL, dl, VT,
2961 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2962 DAG.getConstant(Len - 8, dl, ShVT));
2966 case ISD::CTLZ_ZERO_UNDEF:
2967 // This trivially expands to CTLZ.
2968 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2970 EVT VT = Op.getValueType();
2971 unsigned len = VT.getSizeInBits();
2973 if (TLI.isOperationLegalOrCustom(ISD::CTLZ_ZERO_UNDEF, VT)) {
2974 EVT SetCCVT = getSetCCResultType(VT);
2975 SDValue CTLZ = DAG.getNode(ISD::CTLZ_ZERO_UNDEF, dl, VT, Op);
2976 SDValue Zero = DAG.getConstant(0, dl, VT);
2977 SDValue SrcIsZero = DAG.getSetCC(dl, SetCCVT, Op, Zero, ISD::SETEQ);
2978 return DAG.getNode(ISD::SELECT, dl, VT, SrcIsZero,
2979 DAG.getConstant(len, dl, VT), CTLZ);
2982 // for now, we do this:
2983 // x = x | (x >> 1);
2984 // x = x | (x >> 2);
2986 // x = x | (x >>16);
2987 // x = x | (x >>32); // for 64-bit input
2988 // return popcount(~x);
2990 // Ref: "Hacker's Delight" by Henry Warren
2991 EVT ShVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
2992 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2993 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2994 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2995 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2997 Op = DAG.getNOT(dl, Op, VT);
2998 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
3000 case ISD::CTTZ_ZERO_UNDEF:
3001 // This trivially expands to CTTZ.
3002 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
3004 // for now, we use: { return popcount(~x & (x - 1)); }
3005 // unless the target has ctlz but not ctpop, in which case we use:
3006 // { return 32 - nlz(~x & (x-1)); }
3007 // Ref: "Hacker's Delight" by Henry Warren
3008 EVT VT = Op.getValueType();
3009 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
3010 DAG.getNOT(dl, Op, VT),
3011 DAG.getNode(ISD::SUB, dl, VT, Op,
3012 DAG.getConstant(1, dl, VT)));
3013 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
3014 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
3015 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
3016 return DAG.getNode(ISD::SUB, dl, VT,
3017 DAG.getConstant(VT.getSizeInBits(), dl, VT),
3018 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
3019 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
3024 bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
3025 SmallVector<SDValue, 8> Results;
3027 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3029 switch (Node->getOpcode()) {
3032 case ISD::CTLZ_ZERO_UNDEF:
3034 case ISD::CTTZ_ZERO_UNDEF:
3035 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
3036 Results.push_back(Tmp1);
3038 case ISD::BITREVERSE:
3039 Results.push_back(ExpandBITREVERSE(Node->getOperand(0), dl));
3042 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
3044 case ISD::FRAMEADDR:
3045 case ISD::RETURNADDR:
3046 case ISD::FRAME_TO_ARGS_OFFSET:
3047 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3049 case ISD::FLT_ROUNDS_:
3050 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
3052 case ISD::EH_RETURN:
3056 case ISD::EH_SJLJ_LONGJMP:
3057 // If the target didn't expand these, there's nothing to do, so just
3058 // preserve the chain and be done.
3059 Results.push_back(Node->getOperand(0));
3061 case ISD::READCYCLECOUNTER:
3062 // If the target didn't expand this, just return 'zero' and preserve the
3064 Results.append(Node->getNumValues() - 1,
3065 DAG.getConstant(0, dl, Node->getValueType(0)));
3066 Results.push_back(Node->getOperand(0));
3068 case ISD::EH_SJLJ_SETJMP:
3069 // If the target didn't expand this, just return 'zero' and preserve the
3071 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
3072 Results.push_back(Node->getOperand(0));
3074 case ISD::ATOMIC_LOAD: {
3075 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3076 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
3077 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3078 SDValue Swap = DAG.getAtomicCmpSwap(
3079 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3080 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
3081 cast<AtomicSDNode>(Node)->getMemOperand(),
3082 cast<AtomicSDNode>(Node)->getOrdering(),
3083 cast<AtomicSDNode>(Node)->getOrdering(),
3084 cast<AtomicSDNode>(Node)->getSynchScope());
3085 Results.push_back(Swap.getValue(0));
3086 Results.push_back(Swap.getValue(1));
3089 case ISD::ATOMIC_STORE: {
3090 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3091 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3092 cast<AtomicSDNode>(Node)->getMemoryVT(),
3093 Node->getOperand(0),
3094 Node->getOperand(1), Node->getOperand(2),
3095 cast<AtomicSDNode>(Node)->getMemOperand(),
3096 cast<AtomicSDNode>(Node)->getOrdering(),
3097 cast<AtomicSDNode>(Node)->getSynchScope());
3098 Results.push_back(Swap.getValue(1));
3101 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3102 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3103 // splits out the success value as a comparison. Expanding the resulting
3104 // ATOMIC_CMP_SWAP will produce a libcall.
3105 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3106 SDValue Res = DAG.getAtomicCmpSwap(
3107 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3108 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
3109 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
3110 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
3111 cast<AtomicSDNode>(Node)->getFailureOrdering(),
3112 cast<AtomicSDNode>(Node)->getSynchScope());
3114 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
3115 Res, Node->getOperand(2), ISD::SETEQ);
3117 Results.push_back(Res.getValue(0));
3118 Results.push_back(Success);
3119 Results.push_back(Res.getValue(1));
3122 case ISD::DYNAMIC_STACKALLOC:
3123 ExpandDYNAMIC_STACKALLOC(Node, Results);
3125 case ISD::MERGE_VALUES:
3126 for (unsigned i = 0; i < Node->getNumValues(); i++)
3127 Results.push_back(Node->getOperand(i));
3130 EVT VT = Node->getValueType(0);
3132 Results.push_back(DAG.getConstant(0, dl, VT));
3134 assert(VT.isFloatingPoint() && "Unknown value type!");
3135 Results.push_back(DAG.getConstantFP(0, dl, VT));
3141 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3142 Node->getValueType(0), dl);
3143 Results.push_back(Tmp1);
3145 case ISD::FP_EXTEND:
3146 Tmp1 = EmitStackConvert(Node->getOperand(0),
3147 Node->getOperand(0).getValueType(),
3148 Node->getValueType(0), dl);
3149 Results.push_back(Tmp1);
3151 case ISD::SIGN_EXTEND_INREG: {
3152 // NOTE: we could fall back on load/store here too for targets without
3153 // SAR. However, it is doubtful that any exist.
3154 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3155 EVT VT = Node->getValueType(0);
3156 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT, DAG.getDataLayout());
3159 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3160 ExtraVT.getScalarType().getSizeInBits();
3161 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3162 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3163 Node->getOperand(0), ShiftCst);
3164 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3165 Results.push_back(Tmp1);
3168 case ISD::FP_ROUND_INREG: {
3169 // The only way we can lower this is to turn it into a TRUNCSTORE,
3170 // EXTLOAD pair, targeting a temporary location (a stack slot).
3172 // NOTE: there is a choice here between constantly creating new stack
3173 // slots and always reusing the same one. We currently always create
3174 // new ones, as reuse may inhibit scheduling.
3175 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3176 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3177 Node->getValueType(0), dl);
3178 Results.push_back(Tmp1);
3181 case ISD::SINT_TO_FP:
3182 case ISD::UINT_TO_FP:
3183 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3184 Node->getOperand(0), Node->getValueType(0), dl);
3185 Results.push_back(Tmp1);
3187 case ISD::FP_TO_SINT:
3188 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3189 Results.push_back(Tmp1);
3191 case ISD::FP_TO_UINT: {
3192 SDValue True, False;
3193 EVT VT = Node->getOperand(0).getValueType();
3194 EVT NVT = Node->getValueType(0);
3195 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3196 APInt::getNullValue(VT.getSizeInBits()));
3197 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3198 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3199 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3200 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3201 Node->getOperand(0),
3203 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3204 // TODO: Should any fast-math-flags be set for the FSUB?
3205 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3206 DAG.getNode(ISD::FSUB, dl, VT,
3207 Node->getOperand(0), Tmp1));
3208 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3209 DAG.getConstant(x, dl, NVT));
3210 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3211 Results.push_back(Tmp1);
3215 Results.push_back(DAG.expandVAArg(Node));
3216 Results.push_back(Results[0].getValue(1));
3219 Results.push_back(DAG.expandVACopy(Node));
3221 case ISD::EXTRACT_VECTOR_ELT:
3222 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3223 // This must be an access of the only element. Return it.
3224 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3225 Node->getOperand(0));
3227 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3228 Results.push_back(Tmp1);
3230 case ISD::EXTRACT_SUBVECTOR:
3231 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3233 case ISD::INSERT_SUBVECTOR:
3234 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3236 case ISD::CONCAT_VECTORS: {
3237 Results.push_back(ExpandVectorBuildThroughStack(Node));
3240 case ISD::SCALAR_TO_VECTOR:
3241 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3243 case ISD::INSERT_VECTOR_ELT:
3244 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3245 Node->getOperand(1),
3246 Node->getOperand(2), dl));
3248 case ISD::VECTOR_SHUFFLE: {
3249 SmallVector<int, 32> NewMask;
3250 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3252 EVT VT = Node->getValueType(0);
3253 EVT EltVT = VT.getVectorElementType();
3254 SDValue Op0 = Node->getOperand(0);
3255 SDValue Op1 = Node->getOperand(1);
3256 if (!TLI.isTypeLegal(EltVT)) {
3258 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3260 // BUILD_VECTOR operands are allowed to be wider than the element type.
3261 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3263 if (NewEltVT.bitsLT(EltVT)) {
3265 // Convert shuffle node.
3266 // If original node was v4i64 and the new EltVT is i32,
3267 // cast operands to v8i32 and re-build the mask.
3269 // Calculate new VT, the size of the new VT should be equal to original.
3271 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3272 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3273 assert(NewVT.bitsEq(VT));
3275 // cast operands to new VT
3276 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3277 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3279 // Convert the shuffle mask
3280 unsigned int factor =
3281 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3283 // EltVT gets smaller
3286 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3288 for (unsigned fi = 0; fi < factor; ++fi)
3289 NewMask.push_back(Mask[i]);
3292 for (unsigned fi = 0; fi < factor; ++fi)
3293 NewMask.push_back(Mask[i]*factor+fi);
3301 unsigned NumElems = VT.getVectorNumElements();
3302 SmallVector<SDValue, 16> Ops;
3303 for (unsigned i = 0; i != NumElems; ++i) {
3305 Ops.push_back(DAG.getUNDEF(EltVT));
3308 unsigned Idx = Mask[i];
3310 Ops.push_back(DAG.getNode(
3311 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
3312 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout()))));
3314 Ops.push_back(DAG.getNode(
3315 ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op1,
3316 DAG.getConstant(Idx - NumElems, dl,
3317 TLI.getVectorIdxTy(DAG.getDataLayout()))));
3320 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3321 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3322 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3323 Results.push_back(Tmp1);
3326 case ISD::EXTRACT_ELEMENT: {
3327 EVT OpTy = Node->getOperand(0).getValueType();
3328 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3330 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3331 DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
3332 TLI.getShiftAmountTy(
3333 Node->getOperand(0).getValueType(),
3334 DAG.getDataLayout())));
3335 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3338 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3339 Node->getOperand(0));
3341 Results.push_back(Tmp1);
3344 case ISD::STACKSAVE:
3345 // Expand to CopyFromReg if the target set
3346 // StackPointerRegisterToSaveRestore.
3347 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3348 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3349 Node->getValueType(0)));
3350 Results.push_back(Results[0].getValue(1));
3352 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3353 Results.push_back(Node->getOperand(0));
3356 case ISD::STACKRESTORE:
3357 // Expand to CopyToReg if the target set
3358 // StackPointerRegisterToSaveRestore.
3359 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3360 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3361 Node->getOperand(1)));
3363 Results.push_back(Node->getOperand(0));
3366 case ISD::GET_DYNAMIC_AREA_OFFSET:
3367 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
3368 Results.push_back(Results[0].getValue(0));
3370 case ISD::FCOPYSIGN:
3371 Results.push_back(ExpandFCOPYSIGN(Node));
3374 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3375 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3376 // TODO: If FNEG has fast-math-flags, propagate them to the FSUB.
3377 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3378 Node->getOperand(0));
3379 Results.push_back(Tmp1);
3382 Results.push_back(ExpandFABS(Node));
3388 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3390 switch (Node->getOpcode()) {
3391 default: llvm_unreachable("How did we get here?");
3392 case ISD::SMAX: Pred = ISD::SETGT; break;
3393 case ISD::SMIN: Pred = ISD::SETLT; break;
3394 case ISD::UMAX: Pred = ISD::SETUGT; break;
3395 case ISD::UMIN: Pred = ISD::SETULT; break;
3397 Tmp1 = Node->getOperand(0);
3398 Tmp2 = Node->getOperand(1);
3399 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3400 Results.push_back(Tmp1);
3406 EVT VT = Node->getValueType(0);
3407 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3408 // fcos which share the same operand and both are used.
3409 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3410 canCombineSinCosLibcall(Node, TLI, TM))
3411 && useSinCos(Node)) {
3412 SDVTList VTs = DAG.getVTList(VT, VT);
3413 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3414 if (Node->getOpcode() == ISD::FCOS)
3415 Tmp1 = Tmp1.getValue(1);
3416 Results.push_back(Tmp1);
3421 llvm_unreachable("Illegal fmad should never be formed");
3423 case ISD::FP16_TO_FP:
3424 if (Node->getValueType(0) != MVT::f32) {
3425 // We can extend to types bigger than f32 in two steps without changing
3426 // the result. Since "f16 -> f32" is much more commonly available, give
3427 // CodeGen the option of emitting that before resorting to a libcall.
3429 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3431 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3434 case ISD::FP_TO_FP16:
3435 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3436 SDValue Op = Node->getOperand(0);
3437 MVT SVT = Op.getSimpleValueType();
3438 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3439 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3440 // Under fastmath, we can expand this node into a fround followed by
3441 // a float-half conversion.
3442 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3443 DAG.getIntPtrConstant(0, dl));
3445 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3449 case ISD::ConstantFP: {
3450 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3451 // Check to see if this FP immediate is already legal.
3452 // If this is a legal constant, turn it into a TargetConstantFP node.
3453 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3454 Results.push_back(ExpandConstantFP(CFP, true));
3457 case ISD::Constant: {
3458 ConstantSDNode *CP = cast<ConstantSDNode>(Node);
3459 Results.push_back(ExpandConstant(CP));
3463 EVT VT = Node->getValueType(0);
3464 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3465 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3466 const SDNodeFlags *Flags = &cast<BinaryWithFlagsSDNode>(Node)->Flags;
3467 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3468 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1, Flags);
3469 Results.push_back(Tmp1);
3474 EVT VT = Node->getValueType(0);
3475 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3476 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3477 "Don't know how to expand this subtraction!");
3478 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3479 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3481 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3482 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3487 EVT VT = Node->getValueType(0);
3488 bool isSigned = Node->getOpcode() == ISD::SREM;
3489 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3490 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3491 Tmp2 = Node->getOperand(0);
3492 Tmp3 = Node->getOperand(1);
3493 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3494 SDVTList VTs = DAG.getVTList(VT, VT);
3495 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3496 Results.push_back(Tmp1);
3497 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3499 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3500 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3501 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3502 Results.push_back(Tmp1);
3508 bool isSigned = Node->getOpcode() == ISD::SDIV;
3509 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3510 EVT VT = Node->getValueType(0);
3511 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
3512 SDVTList VTs = DAG.getVTList(VT, VT);
3513 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3514 Node->getOperand(1));
3515 Results.push_back(Tmp1);
3521 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3523 EVT VT = Node->getValueType(0);
3524 SDVTList VTs = DAG.getVTList(VT, VT);
3525 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3526 "If this wasn't legal, it shouldn't have been created!");
3527 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3528 Node->getOperand(1));
3529 Results.push_back(Tmp1.getValue(1));
3533 EVT VT = Node->getValueType(0);
3534 SDVTList VTs = DAG.getVTList(VT, VT);
3535 // See if multiply or divide can be lowered using two-result operations.
3536 // We just need the low half of the multiply; try both the signed
3537 // and unsigned forms. If the target supports both SMUL_LOHI and
3538 // UMUL_LOHI, form a preference by checking which forms of plain
3539 // MULH it supports.
3540 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3541 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3542 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3543 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3544 unsigned OpToUse = 0;
3545 if (HasSMUL_LOHI && !HasMULHS) {
3546 OpToUse = ISD::SMUL_LOHI;
3547 } else if (HasUMUL_LOHI && !HasMULHU) {
3548 OpToUse = ISD::UMUL_LOHI;
3549 } else if (HasSMUL_LOHI) {
3550 OpToUse = ISD::SMUL_LOHI;
3551 } else if (HasUMUL_LOHI) {
3552 OpToUse = ISD::UMUL_LOHI;
3555 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3556 Node->getOperand(1)));
3561 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3562 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3563 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3564 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3565 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3566 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3567 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3568 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3570 DAG.getConstant(HalfType.getSizeInBits(), dl,
3571 TLI.getShiftAmountTy(HalfType, DAG.getDataLayout()));
3572 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3573 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3579 SDValue LHS = Node->getOperand(0);
3580 SDValue RHS = Node->getOperand(1);
3581 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3582 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3584 Results.push_back(Sum);
3585 EVT ResultType = Node->getValueType(1);
3586 EVT OType = getSetCCResultType(Node->getValueType(0));
3588 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3590 // LHSSign -> LHS >= 0
3591 // RHSSign -> RHS >= 0
3592 // SumSign -> Sum >= 0
3595 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3597 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3599 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3600 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3601 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3602 Node->getOpcode() == ISD::SADDO ?
3603 ISD::SETEQ : ISD::SETNE);
3605 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3606 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3608 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3609 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3614 SDValue LHS = Node->getOperand(0);
3615 SDValue RHS = Node->getOperand(1);
3616 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3617 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3619 Results.push_back(Sum);
3621 EVT ResultType = Node->getValueType(1);
3622 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3624 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3625 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3627 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3632 EVT VT = Node->getValueType(0);
3633 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3634 SDValue LHS = Node->getOperand(0);
3635 SDValue RHS = Node->getOperand(1);
3638 static const unsigned Ops[2][3] =
3639 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3640 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3641 bool isSigned = Node->getOpcode() == ISD::SMULO;
3642 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3643 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3644 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3645 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3646 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3648 TopHalf = BottomHalf.getValue(1);
3649 } else if (TLI.isTypeLegal(WideVT)) {
3650 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3651 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3652 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3653 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3654 DAG.getIntPtrConstant(0, dl));
3655 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3656 DAG.getIntPtrConstant(1, dl));
3658 // We can fall back to a libcall with an illegal type for the MUL if we
3659 // have a libcall big enough.
3660 // Also, we can fall back to a division in some cases, but that's a big
3661 // performance hit in the general case.
3662 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3663 if (WideVT == MVT::i16)
3664 LC = RTLIB::MUL_I16;
3665 else if (WideVT == MVT::i32)
3666 LC = RTLIB::MUL_I32;
3667 else if (WideVT == MVT::i64)
3668 LC = RTLIB::MUL_I64;
3669 else if (WideVT == MVT::i128)
3670 LC = RTLIB::MUL_I128;
3671 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3673 // The high part is obtained by SRA'ing all but one of the bits of low
3675 unsigned LoSize = VT.getSizeInBits();
3677 DAG.getNode(ISD::SRA, dl, VT, RHS,
3678 DAG.getConstant(LoSize - 1, dl,
3679 TLI.getPointerTy(DAG.getDataLayout())));
3681 DAG.getNode(ISD::SRA, dl, VT, LHS,
3682 DAG.getConstant(LoSize - 1, dl,
3683 TLI.getPointerTy(DAG.getDataLayout())));
3685 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3686 // pre-lowered to the correct types. This all depends upon WideVT not
3687 // being a legal type for the architecture and thus has to be split to
3689 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3690 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3691 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3692 DAG.getIntPtrConstant(0, dl));
3693 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3694 DAG.getIntPtrConstant(1, dl));
3695 // Ret is a node with an illegal type. Because such things are not
3696 // generally permitted during this phase of legalization, make sure the
3697 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3699 assert(Ret->use_empty() &&
3700 "Unexpected uses of illegally type from expanded lib call.");
3704 Tmp1 = DAG.getConstant(
3705 VT.getSizeInBits() - 1, dl,
3706 TLI.getShiftAmountTy(BottomHalf.getValueType(), DAG.getDataLayout()));
3707 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3708 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3711 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3712 DAG.getConstant(0, dl, VT), ISD::SETNE);
3714 Results.push_back(BottomHalf);
3715 Results.push_back(TopHalf);
3718 case ISD::BUILD_PAIR: {
3719 EVT PairTy = Node->getValueType(0);
3720 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3721 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3723 ISD::SHL, dl, PairTy, Tmp2,
3724 DAG.getConstant(PairTy.getSizeInBits() / 2, dl,
3725 TLI.getShiftAmountTy(PairTy, DAG.getDataLayout())));
3726 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3730 Tmp1 = Node->getOperand(0);
3731 Tmp2 = Node->getOperand(1);
3732 Tmp3 = Node->getOperand(2);
3733 if (Tmp1.getOpcode() == ISD::SETCC) {
3734 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3736 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3738 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3739 DAG.getConstant(0, dl, Tmp1.getValueType()),
3740 Tmp2, Tmp3, ISD::SETNE);
3742 Results.push_back(Tmp1);
3745 SDValue Chain = Node->getOperand(0);
3746 SDValue Table = Node->getOperand(1);
3747 SDValue Index = Node->getOperand(2);
3749 EVT PTy = TLI.getPointerTy(DAG.getDataLayout());
3751 const DataLayout &TD = DAG.getDataLayout();
3752 unsigned EntrySize =
3753 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3755 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3756 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3757 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3760 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3761 SDValue LD = DAG.getExtLoad(
3762 ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3763 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT,
3764 false, false, false, 0);
3766 if (TM.getRelocationModel() == Reloc::PIC_) {
3767 // For PIC, the sequence is:
3768 // BRIND(load(Jumptable + index) + RelocBase)
3769 // RelocBase can be JumpTable, GOT or some sort of global base.
3770 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3771 TLI.getPICJumpTableRelocBase(Table, DAG));
3773 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3774 Results.push_back(Tmp1);
3778 // Expand brcond's setcc into its constituent parts and create a BR_CC
3780 Tmp1 = Node->getOperand(0);
3781 Tmp2 = Node->getOperand(1);
3782 if (Tmp2.getOpcode() == ISD::SETCC) {
3783 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3784 Tmp1, Tmp2.getOperand(2),
3785 Tmp2.getOperand(0), Tmp2.getOperand(1),
3786 Node->getOperand(2));
3788 // We test only the i1 bit. Skip the AND if UNDEF.
3789 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3790 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3791 DAG.getConstant(1, dl, Tmp2.getValueType()));
3792 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3793 DAG.getCondCode(ISD::SETNE), Tmp3,
3794 DAG.getConstant(0, dl, Tmp3.getValueType()),
3795 Node->getOperand(2));
3797 Results.push_back(Tmp1);
3800 Tmp1 = Node->getOperand(0);
3801 Tmp2 = Node->getOperand(1);
3802 Tmp3 = Node->getOperand(2);
3803 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3804 Tmp3, NeedInvert, dl);
3807 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3808 // condition code, create a new SETCC node.
3810 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3813 // If we expanded the SETCC by inverting the condition code, then wrap
3814 // the existing SETCC in a NOT to restore the intended condition.
3816 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3818 Results.push_back(Tmp1);
3822 // Otherwise, SETCC for the given comparison type must be completely
3823 // illegal; expand it into a SELECT_CC.
3824 EVT VT = Node->getValueType(0);
3826 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3827 case TargetLowering::ZeroOrOneBooleanContent:
3828 case TargetLowering::UndefinedBooleanContent:
3831 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3835 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3836 DAG.getConstant(TrueValue, dl, VT),
3837 DAG.getConstant(0, dl, VT),
3839 Results.push_back(Tmp1);
3842 case ISD::SELECT_CC: {
3843 Tmp1 = Node->getOperand(0); // LHS
3844 Tmp2 = Node->getOperand(1); // RHS
3845 Tmp3 = Node->getOperand(2); // True
3846 Tmp4 = Node->getOperand(3); // False
3847 EVT VT = Node->getValueType(0);
3848 SDValue CC = Node->getOperand(4);
3849 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3851 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3852 // If the condition code is legal, then we need to expand this
3853 // node using SETCC and SELECT.
3854 EVT CmpVT = Tmp1.getValueType();
3855 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3856 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3859 TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT);
3860 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3861 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3865 // SELECT_CC is legal, so the condition code must not be.
3866 bool Legalized = false;
3867 // Try to legalize by inverting the condition. This is for targets that
3868 // might support an ordered version of a condition, but not the unordered
3869 // version (or vice versa).
3870 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3871 Tmp1.getValueType().isInteger());
3872 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3873 // Use the new condition code and swap true and false
3875 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3877 // If The inverse is not legal, then try to swap the arguments using
3878 // the inverse condition code.
3879 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3880 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3881 // The swapped inverse condition is legal, so swap true and false,
3884 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3889 Legalized = LegalizeSetCCCondCode(
3890 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3893 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3895 // If we expanded the SETCC by inverting the condition code, then swap
3896 // the True/False operands to match.
3898 std::swap(Tmp3, Tmp4);
3900 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3901 // condition code, create a new SELECT_CC node.
3903 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3904 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3906 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3907 CC = DAG.getCondCode(ISD::SETNE);
3908 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3909 Tmp2, Tmp3, Tmp4, CC);
3912 Results.push_back(Tmp1);
3916 Tmp1 = Node->getOperand(0); // Chain
3917 Tmp2 = Node->getOperand(2); // LHS
3918 Tmp3 = Node->getOperand(3); // RHS
3919 Tmp4 = Node->getOperand(1); // CC
3921 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
3922 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
3924 assert(Legalized && "Can't legalize BR_CC with legal condition!");
3926 // If we expanded the SETCC by inverting the condition code, then wrap
3927 // the existing SETCC in a NOT to restore the intended condition.
3929 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
3931 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
3933 if (Tmp4.getNode()) {
3934 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
3935 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
3937 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
3938 Tmp4 = DAG.getCondCode(ISD::SETNE);
3939 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
3940 Tmp2, Tmp3, Node->getOperand(4));
3942 Results.push_back(Tmp1);
3945 case ISD::BUILD_VECTOR:
3946 Results.push_back(ExpandBUILD_VECTOR(Node));
3951 // Scalarize vector SRA/SRL/SHL.
3952 EVT VT = Node->getValueType(0);
3953 assert(VT.isVector() && "Unable to legalize non-vector shift");
3954 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3955 unsigned NumElem = VT.getVectorNumElements();
3957 SmallVector<SDValue, 8> Scalars;
3958 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
3959 SDValue Ex = DAG.getNode(
3960 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(0),
3961 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3962 SDValue Sh = DAG.getNode(
3963 ISD::EXTRACT_VECTOR_ELT, dl, VT.getScalarType(), Node->getOperand(1),
3964 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy(DAG.getDataLayout())));
3965 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
3966 VT.getScalarType(), Ex, Sh));
3969 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
3970 ReplaceNode(SDValue(Node, 0), Result);
3973 case ISD::GLOBAL_OFFSET_TABLE:
3974 case ISD::GlobalAddress:
3975 case ISD::GlobalTLSAddress:
3976 case ISD::ExternalSymbol:
3977 case ISD::ConstantPool:
3978 case ISD::JumpTable:
3979 case ISD::INTRINSIC_W_CHAIN:
3980 case ISD::INTRINSIC_WO_CHAIN:
3981 case ISD::INTRINSIC_VOID:
3982 // FIXME: Custom lowering for these operations shouldn't return null!
3986 // Replace the original node with the legalized result.
3987 if (Results.empty())
3990 ReplaceNode(Node, Results.data());
3994 void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
3995 SmallVector<SDValue, 8> Results;
3997 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3998 unsigned Opc = Node->getOpcode();
4000 case ISD::ATOMIC_FENCE: {
4001 // If the target didn't lower this, lower it to '__sync_synchronize()' call
4002 // FIXME: handle "fence singlethread" more efficiently.
4003 TargetLowering::ArgListTy Args;
4005 TargetLowering::CallLoweringInfo CLI(DAG);
4007 .setChain(Node->getOperand(0))
4008 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
4009 DAG.getExternalSymbol("__sync_synchronize",
4010 TLI.getPointerTy(DAG.getDataLayout())),
4011 std::move(Args), 0);
4013 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4015 Results.push_back(CallResult.second);
4018 // By default, atomic intrinsics are marked Legal and lowered. Targets
4019 // which don't support them directly, however, may want libcalls, in which
4020 // case they mark them Expand, and we get here.
4021 case ISD::ATOMIC_SWAP:
4022 case ISD::ATOMIC_LOAD_ADD:
4023 case ISD::ATOMIC_LOAD_SUB:
4024 case ISD::ATOMIC_LOAD_AND:
4025 case ISD::ATOMIC_LOAD_OR:
4026 case ISD::ATOMIC_LOAD_XOR:
4027 case ISD::ATOMIC_LOAD_NAND:
4028 case ISD::ATOMIC_LOAD_MIN:
4029 case ISD::ATOMIC_LOAD_MAX:
4030 case ISD::ATOMIC_LOAD_UMIN:
4031 case ISD::ATOMIC_LOAD_UMAX:
4032 case ISD::ATOMIC_CMP_SWAP: {
4033 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
4034 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
4035 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
4037 std::pair<SDValue, SDValue> Tmp = ExpandChainLibCall(LC, Node, false);
4038 Results.push_back(Tmp.first);
4039 Results.push_back(Tmp.second);
4043 // If this operation is not supported, lower it to 'abort()' call
4044 TargetLowering::ArgListTy Args;
4045 TargetLowering::CallLoweringInfo CLI(DAG);
4047 .setChain(Node->getOperand(0))
4048 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
4049 DAG.getExternalSymbol("abort",
4050 TLI.getPointerTy(DAG.getDataLayout())),
4051 std::move(Args), 0);
4052 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
4054 Results.push_back(CallResult.second);
4058 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
4059 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
4060 RTLIB::FMIN_PPCF128));
4063 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
4064 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
4065 RTLIB::FMAX_PPCF128));
4068 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
4069 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
4070 RTLIB::SQRT_PPCF128));
4073 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
4074 RTLIB::SIN_F80, RTLIB::SIN_F128,
4075 RTLIB::SIN_PPCF128));
4078 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
4079 RTLIB::COS_F80, RTLIB::COS_F128,
4080 RTLIB::COS_PPCF128));
4083 // Expand into sincos libcall.
4084 ExpandSinCosLibCall(Node, Results);
4087 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
4088 RTLIB::LOG_F80, RTLIB::LOG_F128,
4089 RTLIB::LOG_PPCF128));
4092 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
4093 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
4094 RTLIB::LOG2_PPCF128));
4097 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
4098 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
4099 RTLIB::LOG10_PPCF128));
4102 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
4103 RTLIB::EXP_F80, RTLIB::EXP_F128,
4104 RTLIB::EXP_PPCF128));
4107 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
4108 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
4109 RTLIB::EXP2_PPCF128));
4112 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
4113 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
4114 RTLIB::TRUNC_PPCF128));
4117 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
4118 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
4119 RTLIB::FLOOR_PPCF128));
4122 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
4123 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
4124 RTLIB::CEIL_PPCF128));
4127 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
4128 RTLIB::RINT_F80, RTLIB::RINT_F128,
4129 RTLIB::RINT_PPCF128));
4131 case ISD::FNEARBYINT:
4132 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
4133 RTLIB::NEARBYINT_F64,
4134 RTLIB::NEARBYINT_F80,
4135 RTLIB::NEARBYINT_F128,
4136 RTLIB::NEARBYINT_PPCF128));
4139 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
4143 RTLIB::ROUND_PPCF128));
4146 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
4147 RTLIB::POWI_F80, RTLIB::POWI_F128,
4148 RTLIB::POWI_PPCF128));
4151 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
4152 RTLIB::POW_F80, RTLIB::POW_F128,
4153 RTLIB::POW_PPCF128));
4156 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
4157 RTLIB::DIV_F80, RTLIB::DIV_F128,
4158 RTLIB::DIV_PPCF128));
4161 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
4162 RTLIB::REM_F80, RTLIB::REM_F128,
4163 RTLIB::REM_PPCF128));
4166 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
4167 RTLIB::FMA_F80, RTLIB::FMA_F128,
4168 RTLIB::FMA_PPCF128));
4171 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
4172 RTLIB::ADD_F80, RTLIB::ADD_F128,
4173 RTLIB::ADD_PPCF128));
4176 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
4177 RTLIB::MUL_F80, RTLIB::MUL_F128,
4178 RTLIB::MUL_PPCF128));
4180 case ISD::FP16_TO_FP:
4181 if (Node->getValueType(0) == MVT::f32) {
4182 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
4185 case ISD::FP_TO_FP16: {
4187 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
4188 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
4189 Results.push_back(ExpandLibCall(LC, Node, false));
4193 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
4194 RTLIB::SUB_F80, RTLIB::SUB_F128,
4195 RTLIB::SUB_PPCF128));
4198 Results.push_back(ExpandIntLibCall(Node, true,
4200 RTLIB::SREM_I16, RTLIB::SREM_I32,
4201 RTLIB::SREM_I64, RTLIB::SREM_I128));
4204 Results.push_back(ExpandIntLibCall(Node, false,
4206 RTLIB::UREM_I16, RTLIB::UREM_I32,
4207 RTLIB::UREM_I64, RTLIB::UREM_I128));
4210 Results.push_back(ExpandIntLibCall(Node, true,
4212 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
4213 RTLIB::SDIV_I64, RTLIB::SDIV_I128));
4216 Results.push_back(ExpandIntLibCall(Node, false,
4218 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
4219 RTLIB::UDIV_I64, RTLIB::UDIV_I128));
4223 // Expand into divrem libcall
4224 ExpandDivRemLibCall(Node, Results);
4227 Results.push_back(ExpandIntLibCall(Node, false,
4229 RTLIB::MUL_I16, RTLIB::MUL_I32,
4230 RTLIB::MUL_I64, RTLIB::MUL_I128));
4234 // Replace the original node with the legalized result.
4235 if (!Results.empty())
4236 ReplaceNode(Node, Results.data());
4239 // Determine the vector type to use in place of an original scalar element when
4240 // promoting equally sized vectors.
4241 static MVT getPromotedVectorElementType(const TargetLowering &TLI,
4242 MVT EltVT, MVT NewEltVT) {
4243 unsigned OldEltsPerNewElt = EltVT.getSizeInBits() / NewEltVT.getSizeInBits();
4244 MVT MidVT = MVT::getVectorVT(NewEltVT, OldEltsPerNewElt);
4245 assert(TLI.isTypeLegal(MidVT) && "unexpected");
4249 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4250 SmallVector<SDValue, 8> Results;
4251 MVT OVT = Node->getSimpleValueType(0);
4252 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4253 Node->getOpcode() == ISD::SINT_TO_FP ||
4254 Node->getOpcode() == ISD::SETCC ||
4255 Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
4256 Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
4257 OVT = Node->getOperand(0).getSimpleValueType();
4259 if (Node->getOpcode() == ISD::BR_CC)
4260 OVT = Node->getOperand(2).getSimpleValueType();
4261 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4263 SDValue Tmp1, Tmp2, Tmp3;
4264 switch (Node->getOpcode()) {
4266 case ISD::CTTZ_ZERO_UNDEF:
4268 case ISD::CTLZ_ZERO_UNDEF:
4270 // Zero extend the argument.
4271 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4272 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4273 // already the correct result.
4274 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4275 if (Node->getOpcode() == ISD::CTTZ) {
4276 // FIXME: This should set a bit in the zero extended value instead.
4277 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4278 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4280 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4281 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4282 } else if (Node->getOpcode() == ISD::CTLZ ||
4283 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4284 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4285 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4286 DAG.getConstant(NVT.getSizeInBits() -
4287 OVT.getSizeInBits(), dl, NVT));
4289 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4292 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4293 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4294 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4296 ISD::SRL, dl, NVT, Tmp1,
4297 DAG.getConstant(DiffBits, dl,
4298 TLI.getShiftAmountTy(NVT, DAG.getDataLayout())));
4299 Results.push_back(Tmp1);
4302 case ISD::FP_TO_UINT:
4303 case ISD::FP_TO_SINT:
4304 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4305 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4306 Results.push_back(Tmp1);
4308 case ISD::UINT_TO_FP:
4309 case ISD::SINT_TO_FP:
4310 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4311 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4312 Results.push_back(Tmp1);
4315 SDValue Chain = Node->getOperand(0); // Get the chain.
4316 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4319 if (OVT.isVector()) {
4320 TruncOp = ISD::BITCAST;
4322 assert(OVT.isInteger()
4323 && "VAARG promotion is supported only for vectors or integer types");
4324 TruncOp = ISD::TRUNCATE;
4327 // Perform the larger operation, then convert back
4328 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4329 Node->getConstantOperandVal(3));
4330 Chain = Tmp1.getValue(1);
4332 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4334 // Modified the chain result - switch anything that used the old chain to
4336 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4337 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4339 UpdatedNodes->insert(Tmp2.getNode());
4340 UpdatedNodes->insert(Chain.getNode());
4348 unsigned ExtOp, TruncOp;
4349 if (OVT.isVector()) {
4350 ExtOp = ISD::BITCAST;
4351 TruncOp = ISD::BITCAST;
4353 assert(OVT.isInteger() && "Cannot promote logic operation");
4354 ExtOp = ISD::ANY_EXTEND;
4355 TruncOp = ISD::TRUNCATE;
4357 // Promote each of the values to the new type.
4358 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4359 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4360 // Perform the larger operation, then convert back
4361 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4362 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4366 unsigned ExtOp, TruncOp;
4367 if (Node->getValueType(0).isVector() ||
4368 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4369 ExtOp = ISD::BITCAST;
4370 TruncOp = ISD::BITCAST;
4371 } else if (Node->getValueType(0).isInteger()) {
4372 ExtOp = ISD::ANY_EXTEND;
4373 TruncOp = ISD::TRUNCATE;
4375 ExtOp = ISD::FP_EXTEND;
4376 TruncOp = ISD::FP_ROUND;
4378 Tmp1 = Node->getOperand(0);
4379 // Promote each of the values to the new type.
4380 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4381 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4382 // Perform the larger operation, then round down.
4383 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4384 if (TruncOp != ISD::FP_ROUND)
4385 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4387 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4388 DAG.getIntPtrConstant(0, dl));
4389 Results.push_back(Tmp1);
4392 case ISD::VECTOR_SHUFFLE: {
4393 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4395 // Cast the two input vectors.
4396 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4397 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4399 // Convert the shuffle mask to the right # elements.
4400 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4401 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4402 Results.push_back(Tmp1);
4406 unsigned ExtOp = ISD::FP_EXTEND;
4407 if (NVT.isInteger()) {
4408 ISD::CondCode CCCode =
4409 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4410 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4412 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4413 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4414 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4415 Tmp1, Tmp2, Node->getOperand(2)));
4419 unsigned ExtOp = ISD::FP_EXTEND;
4420 if (NVT.isInteger()) {
4421 ISD::CondCode CCCode =
4422 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4423 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4425 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4426 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4427 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4428 Node->getOperand(0), Node->getOperand(1),
4429 Tmp1, Tmp2, Node->getOperand(4)));
4440 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4441 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4442 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2,
4444 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4445 Tmp3, DAG.getIntPtrConstant(0, dl)));
4449 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4450 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4451 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4453 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4454 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4455 DAG.getIntPtrConstant(0, dl)));
4458 case ISD::FCOPYSIGN:
4460 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4461 Tmp2 = Node->getOperand(1);
4462 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4464 // fcopysign doesn't change anything but the sign bit, so
4465 // (fp_round (fcopysign (fpext a), b))
4467 // (fp_round (fpext a))
4468 // which is a no-op. Mark it as a TRUNCating FP_ROUND.
4469 const bool isTrunc = (Node->getOpcode() == ISD::FCOPYSIGN);
4470 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4471 Tmp3, DAG.getIntPtrConstant(isTrunc, dl)));
4477 case ISD::FNEARBYINT:
4490 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4491 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4492 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4493 Tmp2, DAG.getIntPtrConstant(0, dl)));
4496 case ISD::BUILD_VECTOR: {
4497 MVT EltVT = OVT.getVectorElementType();
4498 MVT NewEltVT = NVT.getVectorElementType();
4500 // Handle bitcasts to a different vector type with the same total bit size
4502 // e.g. v2i64 = build_vector i64:x, i64:y => v4i32
4504 // v4i32 = concat_vectors (v2i32 (bitcast i64:x)), (v2i32 (bitcast i64:y))
4506 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4507 "Invalid promote type for build_vector");
4508 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4510 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4512 SmallVector<SDValue, 8> NewOps;
4513 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) {
4514 SDValue Op = Node->getOperand(I);
4515 NewOps.push_back(DAG.getNode(ISD::BITCAST, SDLoc(Op), MidVT, Op));
4519 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewOps);
4520 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4521 Results.push_back(CvtVec);
4524 case ISD::EXTRACT_VECTOR_ELT: {
4525 MVT EltVT = OVT.getVectorElementType();
4526 MVT NewEltVT = NVT.getVectorElementType();
4528 // Handle bitcasts to a different vector type with the same total bit size.
4530 // e.g. v2i64 = extract_vector_elt x:v2i64, y:i32
4532 // v4i32:castx = bitcast x:v2i64
4535 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
4536 // (i32 (extract_vector_elt castx, (2 * y + 1)))
4539 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4540 "Invalid promote type for extract_vector_elt");
4541 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4543 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4544 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4546 SDValue Idx = Node->getOperand(1);
4547 EVT IdxVT = Idx.getValueType();
4549 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SL, IdxVT);
4550 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4552 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4554 SmallVector<SDValue, 8> NewOps;
4555 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4556 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4557 SDValue TmpIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4559 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4561 NewOps.push_back(Elt);
4564 SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, SL, MidVT, NewOps);
4566 Results.push_back(DAG.getNode(ISD::BITCAST, SL, EltVT, NewVec));
4569 case ISD::INSERT_VECTOR_ELT: {
4570 MVT EltVT = OVT.getVectorElementType();
4571 MVT NewEltVT = NVT.getVectorElementType();
4573 // Handle bitcasts to a different vector type with the same total bit size
4575 // e.g. v2i64 = insert_vector_elt x:v2i64, y:i64, z:i32
4577 // v4i32:castx = bitcast x:v2i64
4578 // v2i32:casty = bitcast y:i64
4581 // (v4i32 insert_vector_elt
4582 // (v4i32 insert_vector_elt v4i32:castx,
4583 // (extract_vector_elt casty, 0), 2 * z),
4584 // (extract_vector_elt casty, 1), (2 * z + 1))
4586 assert(NVT.isVector() && OVT.getSizeInBits() == NVT.getSizeInBits() &&
4587 "Invalid promote type for insert_vector_elt");
4588 assert(NewEltVT.bitsLT(EltVT) && "not handled");
4590 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4591 unsigned NewEltsPerOldElt = MidVT.getVectorNumElements();
4593 SDValue Val = Node->getOperand(1);
4594 SDValue Idx = Node->getOperand(2);
4595 EVT IdxVT = Idx.getValueType();
4598 SDValue Factor = DAG.getConstant(NewEltsPerOldElt, SDLoc(), IdxVT);
4599 SDValue NewBaseIdx = DAG.getNode(ISD::MUL, SL, IdxVT, Idx, Factor);
4601 SDValue CastVec = DAG.getNode(ISD::BITCAST, SL, NVT, Node->getOperand(0));
4602 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4604 SDValue NewVec = CastVec;
4605 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
4606 SDValue IdxOffset = DAG.getConstant(I, SL, IdxVT);
4607 SDValue InEltIdx = DAG.getNode(ISD::ADD, SL, IdxVT, NewBaseIdx, IdxOffset);
4609 SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, NewEltVT,
4610 CastVal, IdxOffset);
4612 NewVec = DAG.getNode(ISD::INSERT_VECTOR_ELT, SL, NVT,
4613 NewVec, Elt, InEltIdx);
4616 Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewVec));
4619 case ISD::SCALAR_TO_VECTOR: {
4620 MVT EltVT = OVT.getVectorElementType();
4621 MVT NewEltVT = NVT.getVectorElementType();
4623 // Handle bitcasts to different vector type with the smae total bit size.
4625 // e.g. v2i64 = scalar_to_vector x:i64
4627 // concat_vectors (v2i32 bitcast x:i64), (v2i32 undef)
4630 MVT MidVT = getPromotedVectorElementType(TLI, EltVT, NewEltVT);
4631 SDValue Val = Node->getOperand(0);
4634 SDValue CastVal = DAG.getNode(ISD::BITCAST, SL, MidVT, Val);
4635 SDValue Undef = DAG.getUNDEF(MidVT);
4637 SmallVector<SDValue, 8> NewElts;
4638 NewElts.push_back(CastVal);
4639 for (unsigned I = 1, NElts = OVT.getVectorNumElements(); I != NElts; ++I)
4640 NewElts.push_back(Undef);
4642 SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SL, NVT, NewElts);
4643 SDValue CvtVec = DAG.getNode(ISD::BITCAST, SL, OVT, Concat);
4644 Results.push_back(CvtVec);
4649 // Replace the original node with the legalized result.
4650 if (!Results.empty())
4651 ReplaceNode(Node, Results.data());
4654 /// This is the entry point for the file.
4655 void SelectionDAG::Legalize() {
4656 AssignTopologicalOrder();
4658 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4659 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4661 // Visit all the nodes. We start in topological order, so that we see
4662 // nodes with their original operands intact. Legalization can produce
4663 // new nodes which may themselves need to be legalized. Iterate until all
4664 // nodes have been legalized.
4666 bool AnyLegalized = false;
4667 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4671 if (N->use_empty() && N != getRoot().getNode()) {
4677 if (LegalizedNodes.insert(N).second) {
4678 AnyLegalized = true;
4679 Legalizer.LegalizeOp(N);
4681 if (N->use_empty() && N != getRoot().getNode()) {
4692 // Remove dead nodes now.
4696 bool SelectionDAG::LegalizeOp(SDNode *N,
4697 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4698 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4699 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4701 // Directly insert the node in question, and legalize it. This will recurse
4702 // as needed through operands.
4703 LegalizedNodes.insert(N);
4704 Legalizer.LegalizeOp(N);
4706 return LegalizedNodes.count(N);