1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
42 //===----------------------------------------------------------------------===//
43 /// This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
60 /// \brief The set of nodes which have already been legalized. We hold a
61 /// reference to it in order to update as necessary on node deletion.
62 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
64 /// \brief A set of all the nodes updated during legalization.
65 SmallSetVector<SDNode *, 16> *UpdatedNodes;
67 EVT getSetCCResultType(EVT VT) const {
68 return TLI.getSetCCResultType(*DAG.getContext(), VT);
71 // Libcall insertion helpers.
74 SelectionDAGLegalize(SelectionDAG &DAG,
75 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
76 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
78 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
80 /// \brief Legalizes the given operation.
81 void LegalizeOp(SDNode *Node);
84 SDValue OptimizeFloatStore(StoreSDNode *ST);
86 void LegalizeLoadOps(SDNode *Node);
87 void LegalizeStoreOps(SDNode *Node);
89 /// Some targets cannot handle a variable
90 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
91 /// is necessary to spill the vector being inserted into to memory, perform
92 /// the insert there, and then read the result back.
93 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
94 SDValue Idx, SDLoc dl);
95 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
96 SDValue Idx, SDLoc dl);
98 /// Return a vector shuffle operation which
99 /// performs the same shuffe in terms of order or result bytes, but on a type
100 /// whose vector element type is narrower than the original shuffle type.
101 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
103 SDValue N1, SDValue N2,
104 ArrayRef<int> Mask) const;
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
107 bool &NeedInvert, SDLoc dl);
109 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
110 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
111 unsigned NumOps, bool isSigned, SDLoc dl);
113 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
114 SDNode *Node, bool isSigned);
115 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
116 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
117 RTLIB::Libcall Call_F128,
118 RTLIB::Libcall Call_PPCF128);
119 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
120 RTLIB::Libcall Call_I8,
121 RTLIB::Libcall Call_I16,
122 RTLIB::Libcall Call_I32,
123 RTLIB::Libcall Call_I64,
124 RTLIB::Libcall Call_I128);
125 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
126 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
129 SDValue ExpandBUILD_VECTOR(SDNode *Node);
130 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
131 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
132 SmallVectorImpl<SDValue> &Results);
133 SDValue ExpandFCOPYSIGN(SDNode *Node);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
141 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
142 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
144 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
145 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
146 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
148 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
150 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
152 void ExpandNode(SDNode *Node);
153 void PromoteNode(SDNode *Node);
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 LegalizedNodes.erase(N);
160 UpdatedNodes->insert(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
164 dbgs() << " with: "; New->dump(&DAG));
166 assert(Old->getNumValues() == New->getNumValues() &&
167 "Replacing one node with another that produces a different number "
169 DAG.ReplaceAllUsesWith(Old, New);
170 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
173 UpdatedNodes->insert(New);
176 void ReplaceNode(SDValue Old, SDValue New) {
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
178 dbgs() << " with: "; New->dump(&DAG));
180 DAG.ReplaceAllUsesWith(Old, New);
181 DAG.TransferDbgValues(Old, New);
183 UpdatedNodes->insert(New.getNode());
184 ReplacedNode(Old.getNode());
186 void ReplaceNode(SDNode *Old, const SDValue *New) {
187 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
191 DEBUG(dbgs() << (i == 0 ? " with: "
194 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
196 UpdatedNodes->insert(New[i].getNode());
203 /// Return a vector shuffle operation which
204 /// performs the same shuffe in terms of order or result bytes, but on a type
205 /// whose vector element type is narrower than the original shuffle type.
206 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
209 SDValue N1, SDValue N2,
210 ArrayRef<int> Mask) const {
211 unsigned NumMaskElts = VT.getVectorNumElements();
212 unsigned NumDestElts = NVT.getVectorNumElements();
213 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
217 if (NumEltsGrowth == 1)
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
220 SmallVector<int, 8> NewMask;
221 for (unsigned i = 0; i != NumMaskElts; ++i) {
223 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
225 NewMask.push_back(-1);
227 NewMask.push_back(Idx * NumEltsGrowth + j);
230 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
231 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
235 /// Expands the ConstantFP node to an integer constant or
236 /// a load from the constant pool.
238 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
242 // If a FP immediate is precise when represented as a float and if the
243 // target can do an extending load from float to double, we put it into
244 // the constant pool as a float, even if it's is statically typed as a
245 // double. This shrinks FP constants and canonicalizes them for targets where
246 // an FP extending load is the same cost as a normal load (such as on the x87
247 // fp stack or PPC FP unit).
248 EVT VT = CFP->getValueType(0);
249 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
252 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), dl,
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
258 while (SVT != MVT::f32 && SVT != MVT::f16) {
259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
260 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261 // Only do this if the target has a native EXTLOAD instruction from
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264 TLI.ShouldShrinkFPConstant(OrigVT)) {
265 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
272 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
273 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
278 CPIdx, MachinePointerInfo::getConstantPool(),
279 VT, false, false, false, Alignment);
283 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
284 MachinePointerInfo::getConstantPool(), false, false, false,
289 /// Expands an unaligned store to 2 half-size stores.
290 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
291 const TargetLowering &TLI,
292 SelectionDAGLegalize *DAGLegalize) {
293 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
294 "unaligned indexed stores not implemented!");
295 SDValue Chain = ST->getChain();
296 SDValue Ptr = ST->getBasePtr();
297 SDValue Val = ST->getValue();
298 EVT VT = Val.getValueType();
299 int Alignment = ST->getAlignment();
300 unsigned AS = ST->getAddressSpace();
303 if (ST->getMemoryVT().isFloatingPoint() ||
304 ST->getMemoryVT().isVector()) {
305 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
306 if (TLI.isTypeLegal(intVT)) {
307 // Expand to a bitconvert of the value to the integer type of the
308 // same size, then a (misaligned) int store.
309 // FIXME: Does not handle truncating floating point stores!
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
311 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
312 ST->isVolatile(), ST->isNonTemporal(), Alignment);
313 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
316 // Do a (aligned) store to a stack slot, then copy from the stack slot
317 // to the final destination using (unaligned) integer loads and stores.
318 EVT StoredVT = ST->getMemoryVT();
320 TLI.getRegisterType(*DAG.getContext(),
321 EVT::getIntegerVT(*DAG.getContext(),
322 StoredVT.getSizeInBits()));
323 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
324 unsigned RegBytes = RegVT.getSizeInBits() / 8;
325 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
327 // Make sure the stack slot is also aligned for the register type.
328 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
330 // Perform the original store, only redirected to the stack slot.
331 SDValue Store = DAG.getTruncStore(Chain, dl,
332 Val, StackPtr, MachinePointerInfo(),
333 StoredVT, false, false, 0);
334 SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy(AS));
335 SmallVector<SDValue, 8> Stores;
338 // Do all but one copies using the full register width.
339 for (unsigned i = 1; i < NumRegs; i++) {
340 // Load one integer register's worth from the stack slot.
341 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
342 MachinePointerInfo(),
343 false, false, false, 0);
344 // Store it to the final location. Remember the store.
345 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
346 ST->getPointerInfo().getWithOffset(Offset),
347 ST->isVolatile(), ST->isNonTemporal(),
348 MinAlign(ST->getAlignment(), Offset)));
349 // Increment the pointers.
351 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
353 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
356 // The last store may be partial. Do a truncating store. On big-endian
357 // machines this requires an extending load from the stack slot to ensure
358 // that the bits are in the right place.
359 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
360 8 * (StoredBytes - Offset));
362 // Load from the stack slot.
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
364 MachinePointerInfo(),
365 MemVT, false, false, false, 0);
367 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
369 .getWithOffset(Offset),
370 MemVT, ST->isVolatile(),
372 MinAlign(ST->getAlignment(), Offset),
374 // The order of the stores doesn't matter - say it with a TokenFactor.
375 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
376 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
379 assert(ST->getMemoryVT().isInteger() &&
380 !ST->getMemoryVT().isVector() &&
381 "Unaligned store of unknown type.");
382 // Get the half-size VT
383 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
384 int NumBits = NewStoredVT.getSizeInBits();
385 int IncrementSize = NumBits / 8;
387 // Divide the stored value in two parts.
388 SDValue ShiftAmount = DAG.getConstant(NumBits, dl,
389 TLI.getShiftAmountTy(Val.getValueType()));
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
393 // Store the two parts
394 SDValue Store1, Store2;
395 Store1 = DAG.getTruncStore(Chain, dl,
396 DAG.getDataLayout().isLittleEndian() ? Lo : Hi,
397 Ptr, ST->getPointerInfo(), NewStoredVT,
398 ST->isVolatile(), ST->isNonTemporal(), Alignment);
400 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
401 DAG.getConstant(IncrementSize, dl, TLI.getPointerTy(AS)));
402 Alignment = MinAlign(Alignment, IncrementSize);
403 Store2 = DAG.getTruncStore(
404 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr,
405 ST->getPointerInfo().getWithOffset(IncrementSize), NewStoredVT,
406 ST->isVolatile(), ST->isNonTemporal(), Alignment, ST->getAAInfo());
409 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
410 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
413 /// Expands an unaligned load to 2 half-size loads.
415 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
416 const TargetLowering &TLI,
417 SDValue &ValResult, SDValue &ChainResult) {
418 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
419 "unaligned indexed loads not implemented!");
420 SDValue Chain = LD->getChain();
421 SDValue Ptr = LD->getBasePtr();
422 EVT VT = LD->getValueType(0);
423 EVT LoadedVT = LD->getMemoryVT();
425 if (VT.isFloatingPoint() || VT.isVector()) {
426 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
427 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
428 // Expand to a (misaligned) integer load of the same size,
429 // then bitconvert to floating point or vector.
430 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
431 LD->getMemOperand());
432 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
434 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
435 ISD::ANY_EXTEND, dl, VT, Result);
442 // Copy the value to a (aligned) stack slot using (unaligned) integer
443 // loads and stores, then do a (aligned) load from the stack slot.
444 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
445 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
446 unsigned RegBytes = RegVT.getSizeInBits() / 8;
447 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
449 // Make sure the stack slot is also aligned for the register type.
450 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
452 SDValue Increment = DAG.getConstant(RegBytes, dl, TLI.getPointerTy());
453 SmallVector<SDValue, 8> Stores;
454 SDValue StackPtr = StackBase;
457 // Do all but one copies using the full register width.
458 for (unsigned i = 1; i < NumRegs; i++) {
459 // Load one integer register's worth from the original location.
460 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
461 LD->getPointerInfo().getWithOffset(Offset),
462 LD->isVolatile(), LD->isNonTemporal(),
464 MinAlign(LD->getAlignment(), Offset),
466 // Follow the load with a store to the stack slot. Remember the store.
467 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
468 MachinePointerInfo(), false, false, 0));
469 // Increment the pointers.
471 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
472 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
476 // The last copy may be partial. Do an extending load.
477 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
478 8 * (LoadedBytes - Offset));
479 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
480 LD->getPointerInfo().getWithOffset(Offset),
481 MemVT, LD->isVolatile(),
484 MinAlign(LD->getAlignment(), Offset),
486 // Follow the load with a store to the stack slot. Remember the store.
487 // On big-endian machines this requires a truncating store to ensure
488 // that the bits end up in the right place.
489 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
490 MachinePointerInfo(), MemVT,
493 // The order of the stores doesn't matter - say it with a TokenFactor.
494 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
496 // Finally, perform the original load only redirected to the stack slot.
497 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
498 MachinePointerInfo(), LoadedVT, false,false, false,
501 // Callers expect a MERGE_VALUES node.
506 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
507 "Unaligned load of unsupported type.");
509 // Compute the new VT that is half the size of the old one. This is an
511 unsigned NumBits = LoadedVT.getSizeInBits();
513 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
516 unsigned Alignment = LD->getAlignment();
517 unsigned IncrementSize = NumBits / 8;
518 ISD::LoadExtType HiExtType = LD->getExtensionType();
520 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
521 if (HiExtType == ISD::NON_EXTLOAD)
522 HiExtType = ISD::ZEXTLOAD;
524 // Load the value in two parts
526 if (DAG.getDataLayout().isLittleEndian()) {
527 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
528 NewLoadedVT, LD->isVolatile(),
529 LD->isNonTemporal(), LD->isInvariant(), Alignment,
531 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
532 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
533 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
534 LD->getPointerInfo().getWithOffset(IncrementSize),
535 NewLoadedVT, LD->isVolatile(),
536 LD->isNonTemporal(),LD->isInvariant(),
537 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
539 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
540 NewLoadedVT, LD->isVolatile(),
541 LD->isNonTemporal(), LD->isInvariant(), Alignment,
543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
544 DAG.getConstant(IncrementSize, dl, Ptr.getValueType()));
545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
546 LD->getPointerInfo().getWithOffset(IncrementSize),
547 NewLoadedVT, LD->isVolatile(),
548 LD->isNonTemporal(), LD->isInvariant(),
549 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
552 // aggregate the two parts
553 SDValue ShiftAmount = DAG.getConstant(NumBits, dl,
554 TLI.getShiftAmountTy(Hi.getValueType()));
555 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
556 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
558 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
565 /// Some target cannot handle a variable insertion index for the
566 /// INSERT_VECTOR_ELT instruction. In this case, it
567 /// is necessary to spill the vector being inserted into to memory, perform
568 /// the insert there, and then read the result back.
569 SDValue SelectionDAGLegalize::
570 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
576 // If the target doesn't support this, we have to spill the input vector
577 // to a temporary stack slot, update the element, then reload it. This is
578 // badness. We could also load the value into a vector register (either
579 // with a "move to register" or "extload into register" instruction, then
580 // permute it into place, if the idx is a constant and if the idx is
581 // supported by the target.
582 EVT VT = Tmp1.getValueType();
583 EVT EltVT = VT.getVectorElementType();
584 EVT IdxVT = Tmp3.getValueType();
585 EVT PtrVT = TLI.getPointerTy();
586 SDValue StackPtr = DAG.CreateStackTemporary(VT);
588 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
591 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
592 MachinePointerInfo::getFixedStack(SPFI),
595 // Truncate or zero extend offset to target pointer type.
596 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
597 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
598 // Add the offset to the index.
599 unsigned EltSize = EltVT.getSizeInBits()/8;
600 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,
601 DAG.getConstant(EltSize, dl, IdxVT));
602 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
603 // Store the scalar value.
604 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
606 // Load the updated vector.
607 return DAG.getLoad(VT, dl, Ch, StackPtr,
608 MachinePointerInfo::getFixedStack(SPFI), false, false,
613 SDValue SelectionDAGLegalize::
614 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
615 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
616 // SCALAR_TO_VECTOR requires that the type of the value being inserted
617 // match the element type of the vector being created, except for
618 // integers in which case the inserted value can be over width.
619 EVT EltVT = Vec.getValueType().getVectorElementType();
620 if (Val.getValueType() == EltVT ||
621 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
622 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
623 Vec.getValueType(), Val);
625 unsigned NumElts = Vec.getValueType().getVectorNumElements();
626 // We generate a shuffle of InVec and ScVec, so the shuffle mask
627 // should be 0,1,2,3,4,5... with the appropriate element replaced with
629 SmallVector<int, 8> ShufOps;
630 for (unsigned i = 0; i != NumElts; ++i)
631 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
633 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
637 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
640 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
641 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
642 // FIXME: We shouldn't do this for TargetConstantFP's.
643 // FIXME: move this to the DAG Combiner! Note that we can't regress due
644 // to phase ordering between legalized code and the dag combiner. This
645 // probably means that we need to integrate dag combiner and legalizer
647 // We generally can't do this one for long doubles.
648 SDValue Chain = ST->getChain();
649 SDValue Ptr = ST->getBasePtr();
650 unsigned Alignment = ST->getAlignment();
651 bool isVolatile = ST->isVolatile();
652 bool isNonTemporal = ST->isNonTemporal();
653 AAMDNodes AAInfo = ST->getAAInfo();
655 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
656 if (CFP->getValueType(0) == MVT::f32 &&
657 TLI.isTypeLegal(MVT::i32)) {
658 SDValue Con = DAG.getConstant(CFP->getValueAPF().
659 bitcastToAPInt().zextOrTrunc(32),
660 SDLoc(CFP), MVT::i32);
661 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
662 isVolatile, isNonTemporal, Alignment, AAInfo);
665 if (CFP->getValueType(0) == MVT::f64) {
666 // If this target supports 64-bit registers, do a single 64-bit store.
667 if (TLI.isTypeLegal(MVT::i64)) {
668 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
669 zextOrTrunc(64), SDLoc(CFP), MVT::i64);
670 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
671 isVolatile, isNonTemporal, Alignment, AAInfo);
674 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
675 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
676 // stores. If the target supports neither 32- nor 64-bits, this
677 // xform is certainly not worth it.
678 const APInt &IntVal = CFP->getValueAPF().bitcastToAPInt();
679 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32);
680 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), dl, MVT::i32);
681 if (DAG.getDataLayout().isBigEndian())
684 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
685 isNonTemporal, Alignment, AAInfo);
686 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
687 DAG.getConstant(4, dl, Ptr.getValueType()));
688 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
689 ST->getPointerInfo().getWithOffset(4),
690 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
693 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
697 return SDValue(nullptr, 0);
700 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
701 StoreSDNode *ST = cast<StoreSDNode>(Node);
702 SDValue Chain = ST->getChain();
703 SDValue Ptr = ST->getBasePtr();
706 unsigned Alignment = ST->getAlignment();
707 bool isVolatile = ST->isVolatile();
708 bool isNonTemporal = ST->isNonTemporal();
709 AAMDNodes AAInfo = ST->getAAInfo();
711 if (!ST->isTruncatingStore()) {
712 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
713 ReplaceNode(ST, OptStore);
718 SDValue Value = ST->getValue();
719 MVT VT = Value.getSimpleValueType();
720 switch (TLI.getOperationAction(ISD::STORE, VT)) {
721 default: llvm_unreachable("This action is not supported yet!");
722 case TargetLowering::Legal: {
723 // If this is an unaligned store and the target doesn't support it,
725 unsigned AS = ST->getAddressSpace();
726 unsigned Align = ST->getAlignment();
727 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
728 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
729 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
730 if (Align < ABIAlignment)
731 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
735 case TargetLowering::Custom: {
736 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
737 if (Res && Res != SDValue(Node, 0))
738 ReplaceNode(SDValue(Node, 0), Res);
741 case TargetLowering::Promote: {
742 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
743 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
744 "Can only promote stores to same size type");
745 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
747 DAG.getStore(Chain, dl, Value, Ptr,
748 ST->getPointerInfo(), isVolatile,
749 isNonTemporal, Alignment, AAInfo);
750 ReplaceNode(SDValue(Node, 0), Result);
757 SDValue Value = ST->getValue();
759 EVT StVT = ST->getMemoryVT();
760 unsigned StWidth = StVT.getSizeInBits();
761 auto &DL = DAG.getDataLayout();
763 if (StWidth != StVT.getStoreSizeInBits()) {
764 // Promote to a byte-sized store with upper bits zero if not
765 // storing an integral number of bytes. For example, promote
766 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
767 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
768 StVT.getStoreSizeInBits());
769 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
771 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
772 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
773 ReplaceNode(SDValue(Node, 0), Result);
774 } else if (StWidth & (StWidth - 1)) {
775 // If not storing a power-of-2 number of bits, expand as two stores.
776 assert(!StVT.isVector() && "Unsupported truncstore!");
777 unsigned RoundWidth = 1 << Log2_32(StWidth);
778 assert(RoundWidth < StWidth);
779 unsigned ExtraWidth = StWidth - RoundWidth;
780 assert(ExtraWidth < RoundWidth);
781 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
782 "Store size not an integral number of bytes!");
783 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
784 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
786 unsigned IncrementSize;
788 if (DL.isLittleEndian()) {
789 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
790 // Store the bottom RoundWidth bits.
791 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
793 isVolatile, isNonTemporal, Alignment,
796 // Store the remaining ExtraWidth bits.
797 IncrementSize = RoundWidth / 8;
798 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
799 DAG.getConstant(IncrementSize, dl,
800 Ptr.getValueType()));
801 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
802 DAG.getConstant(RoundWidth, dl,
803 TLI.getShiftAmountTy(Value.getValueType())));
804 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
805 ST->getPointerInfo().getWithOffset(IncrementSize),
806 ExtraVT, isVolatile, isNonTemporal,
807 MinAlign(Alignment, IncrementSize), AAInfo);
809 // Big endian - avoid unaligned stores.
810 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
811 // Store the top RoundWidth bits.
812 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
813 DAG.getConstant(ExtraWidth, dl,
814 TLI.getShiftAmountTy(Value.getValueType())));
815 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
816 RoundVT, isVolatile, isNonTemporal, Alignment,
819 // Store the remaining ExtraWidth bits.
820 IncrementSize = RoundWidth / 8;
821 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
822 DAG.getConstant(IncrementSize, dl,
823 Ptr.getValueType()));
824 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
825 ST->getPointerInfo().getWithOffset(IncrementSize),
826 ExtraVT, isVolatile, isNonTemporal,
827 MinAlign(Alignment, IncrementSize), AAInfo);
830 // The order of the stores doesn't matter.
831 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
832 ReplaceNode(SDValue(Node, 0), Result);
834 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
835 StVT.getSimpleVT())) {
836 default: llvm_unreachable("This action is not supported yet!");
837 case TargetLowering::Legal: {
838 unsigned AS = ST->getAddressSpace();
839 unsigned Align = ST->getAlignment();
840 // If this is an unaligned store and the target doesn't support it,
842 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
843 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
844 unsigned ABIAlignment = DL.getABITypeAlignment(Ty);
845 if (Align < ABIAlignment)
846 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
850 case TargetLowering::Custom: {
851 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
852 if (Res && Res != SDValue(Node, 0))
853 ReplaceNode(SDValue(Node, 0), Res);
856 case TargetLowering::Expand:
857 assert(!StVT.isVector() &&
858 "Vector Stores are handled in LegalizeVectorOps");
860 // TRUNCSTORE:i16 i32 -> STORE i16
861 assert(TLI.isTypeLegal(StVT) &&
862 "Do not know how to expand this store!");
863 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
865 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
866 isVolatile, isNonTemporal, Alignment, AAInfo);
867 ReplaceNode(SDValue(Node, 0), Result);
874 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
875 LoadSDNode *LD = cast<LoadSDNode>(Node);
876 SDValue Chain = LD->getChain(); // The chain.
877 SDValue Ptr = LD->getBasePtr(); // The base pointer.
878 SDValue Value; // The value returned by the load op.
881 ISD::LoadExtType ExtType = LD->getExtensionType();
882 if (ExtType == ISD::NON_EXTLOAD) {
883 MVT VT = Node->getSimpleValueType(0);
884 SDValue RVal = SDValue(Node, 0);
885 SDValue RChain = SDValue(Node, 1);
887 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
888 default: llvm_unreachable("This action is not supported yet!");
889 case TargetLowering::Legal: {
890 unsigned AS = LD->getAddressSpace();
891 unsigned Align = LD->getAlignment();
892 // If this is an unaligned load and the target doesn't support it,
894 if (!TLI.allowsMisalignedMemoryAccesses(LD->getMemoryVT(), AS, Align)) {
895 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
896 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
897 if (Align < ABIAlignment){
898 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
903 case TargetLowering::Custom: {
904 SDValue Res = TLI.LowerOperation(RVal, DAG);
907 RChain = Res.getValue(1);
911 case TargetLowering::Promote: {
912 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
913 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
914 "Can only promote loads to same size type");
916 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
917 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
918 RChain = Res.getValue(1);
922 if (RChain.getNode() != Node) {
923 assert(RVal.getNode() != Node && "Load must be completely replaced");
924 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
925 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
927 UpdatedNodes->insert(RVal.getNode());
928 UpdatedNodes->insert(RChain.getNode());
935 EVT SrcVT = LD->getMemoryVT();
936 unsigned SrcWidth = SrcVT.getSizeInBits();
937 unsigned Alignment = LD->getAlignment();
938 bool isVolatile = LD->isVolatile();
939 bool isNonTemporal = LD->isNonTemporal();
940 bool isInvariant = LD->isInvariant();
941 AAMDNodes AAInfo = LD->getAAInfo();
943 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
944 // Some targets pretend to have an i1 loading operation, and actually
945 // load an i8. This trick is correct for ZEXTLOAD because the top 7
946 // bits are guaranteed to be zero; it helps the optimizers understand
947 // that these bits are zero. It is also useful for EXTLOAD, since it
948 // tells the optimizers that those bits are undefined. It would be
949 // nice to have an effective generic way of getting these benefits...
950 // Until such a way is found, don't insist on promoting i1 here.
952 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
953 TargetLowering::Promote)) {
954 // Promote to a byte-sized load if not loading an integral number of
955 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
956 unsigned NewWidth = SrcVT.getStoreSizeInBits();
957 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
960 // The extra bits are guaranteed to be zero, since we stored them that
961 // way. A zext load from NVT thus automatically gives zext from SrcVT.
963 ISD::LoadExtType NewExtType =
964 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
967 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
968 Chain, Ptr, LD->getPointerInfo(),
969 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
972 Ch = Result.getValue(1); // The chain.
974 if (ExtType == ISD::SEXTLOAD)
975 // Having the top bits zero doesn't help when sign extending.
976 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
977 Result.getValueType(),
978 Result, DAG.getValueType(SrcVT));
979 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
980 // All the top bits are guaranteed to be zero - inform the optimizers.
981 Result = DAG.getNode(ISD::AssertZext, dl,
982 Result.getValueType(), Result,
983 DAG.getValueType(SrcVT));
987 } else if (SrcWidth & (SrcWidth - 1)) {
988 // If not loading a power-of-2 number of bits, expand as two loads.
989 assert(!SrcVT.isVector() && "Unsupported extload!");
990 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
991 assert(RoundWidth < SrcWidth);
992 unsigned ExtraWidth = SrcWidth - RoundWidth;
993 assert(ExtraWidth < RoundWidth);
994 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
995 "Load size not an integral number of bytes!");
996 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
997 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
999 unsigned IncrementSize;
1000 auto &DL = DAG.getDataLayout();
1002 if (DL.isLittleEndian()) {
1003 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1004 // Load the bottom RoundWidth bits.
1005 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1007 LD->getPointerInfo(), RoundVT, isVolatile,
1008 isNonTemporal, isInvariant, Alignment, AAInfo);
1010 // Load the remaining ExtraWidth bits.
1011 IncrementSize = RoundWidth / 8;
1012 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1013 DAG.getConstant(IncrementSize, dl,
1014 Ptr.getValueType()));
1015 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1016 LD->getPointerInfo().getWithOffset(IncrementSize),
1017 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1018 MinAlign(Alignment, IncrementSize), AAInfo);
1020 // Build a factor node to remember that this load is independent of
1022 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1025 // Move the top bits to the right place.
1026 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1027 DAG.getConstant(RoundWidth, dl,
1028 TLI.getShiftAmountTy(Hi.getValueType())));
1030 // Join the hi and lo parts.
1031 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1033 // Big endian - avoid unaligned loads.
1034 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1035 // Load the top RoundWidth bits.
1036 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1037 LD->getPointerInfo(), RoundVT, isVolatile,
1038 isNonTemporal, isInvariant, Alignment, AAInfo);
1040 // Load the remaining ExtraWidth bits.
1041 IncrementSize = RoundWidth / 8;
1042 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1043 DAG.getConstant(IncrementSize, dl,
1044 Ptr.getValueType()));
1045 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1046 dl, Node->getValueType(0), Chain, Ptr,
1047 LD->getPointerInfo().getWithOffset(IncrementSize),
1048 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1049 MinAlign(Alignment, IncrementSize), AAInfo);
1051 // Build a factor node to remember that this load is independent of
1053 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1056 // Move the top bits to the right place.
1057 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1058 DAG.getConstant(ExtraWidth, dl,
1059 TLI.getShiftAmountTy(Hi.getValueType())));
1061 // Join the hi and lo parts.
1062 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1067 bool isCustom = false;
1068 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1069 SrcVT.getSimpleVT())) {
1070 default: llvm_unreachable("This action is not supported yet!");
1071 case TargetLowering::Custom:
1074 case TargetLowering::Legal: {
1075 Value = SDValue(Node, 0);
1076 Chain = SDValue(Node, 1);
1079 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1080 if (Res.getNode()) {
1082 Chain = Res.getValue(1);
1085 // If this is an unaligned load and the target doesn't support
1087 EVT MemVT = LD->getMemoryVT();
1088 unsigned AS = LD->getAddressSpace();
1089 unsigned Align = LD->getAlignment();
1090 if (!TLI.allowsMisalignedMemoryAccesses(MemVT, AS, Align)) {
1091 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1092 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
1093 if (Align < ABIAlignment){
1094 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1100 case TargetLowering::Expand:
1101 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) {
1102 // If the source type is not legal, see if there is a legal extload to
1103 // an intermediate type that we can then extend further.
1104 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1105 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1106 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1107 // If we are loading a legal type, this is a non-extload followed by a
1109 ISD::LoadExtType MidExtType =
1110 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1112 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1113 SrcVT, LD->getMemOperand());
1115 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1116 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1117 Chain = Load.getValue(1);
1122 assert(!SrcVT.isVector() &&
1123 "Vector Loads are handled in LegalizeVectorOps");
1125 // FIXME: This does not work for vectors on most targets. Sign-
1126 // and zero-extend operations are currently folded into extending
1127 // loads, whether they are legal or not, and then we end up here
1128 // without any support for legalizing them.
1129 assert(ExtType != ISD::EXTLOAD &&
1130 "EXTLOAD should always be supported!");
1131 // Turn the unsupported load into an EXTLOAD followed by an
1132 // explicit zero/sign extend inreg.
1133 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1134 Node->getValueType(0),
1136 LD->getMemOperand());
1138 if (ExtType == ISD::SEXTLOAD)
1139 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1140 Result.getValueType(),
1141 Result, DAG.getValueType(SrcVT));
1143 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1145 Chain = Result.getValue(1);
1150 // Since loads produce two values, make sure to remember that we legalized
1152 if (Chain.getNode() != Node) {
1153 assert(Value.getNode() != Node && "Load must be completely replaced");
1154 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1155 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1157 UpdatedNodes->insert(Value.getNode());
1158 UpdatedNodes->insert(Chain.getNode());
1164 /// Return a legal replacement for the given operation, with all legal operands.
1165 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1166 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1168 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1172 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1173 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1174 TargetLowering::TypeLegal &&
1175 "Unexpected illegal type!");
1177 for (const SDValue &Op : Node->op_values())
1178 assert((TLI.getTypeAction(*DAG.getContext(),
1179 Op.getValueType()) == TargetLowering::TypeLegal ||
1180 Op.getOpcode() == ISD::TargetConstant) &&
1181 "Unexpected illegal type!");
1184 // Figure out the correct action; the way to query this varies by opcode
1185 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1186 bool SimpleFinishLegalizing = true;
1187 switch (Node->getOpcode()) {
1188 case ISD::INTRINSIC_W_CHAIN:
1189 case ISD::INTRINSIC_WO_CHAIN:
1190 case ISD::INTRINSIC_VOID:
1191 case ISD::STACKSAVE:
1192 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1195 Action = TLI.getOperationAction(Node->getOpcode(),
1196 Node->getValueType(0));
1197 if (Action != TargetLowering::Promote)
1198 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1200 case ISD::FP_TO_FP16:
1201 case ISD::SINT_TO_FP:
1202 case ISD::UINT_TO_FP:
1203 case ISD::EXTRACT_VECTOR_ELT:
1204 Action = TLI.getOperationAction(Node->getOpcode(),
1205 Node->getOperand(0).getValueType());
1207 case ISD::FP_ROUND_INREG:
1208 case ISD::SIGN_EXTEND_INREG: {
1209 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1210 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1213 case ISD::ATOMIC_STORE: {
1214 Action = TLI.getOperationAction(Node->getOpcode(),
1215 Node->getOperand(2).getValueType());
1218 case ISD::SELECT_CC:
1221 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1222 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1223 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1224 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1225 ISD::CondCode CCCode =
1226 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1227 Action = TLI.getCondCodeAction(CCCode, OpVT);
1228 if (Action == TargetLowering::Legal) {
1229 if (Node->getOpcode() == ISD::SELECT_CC)
1230 Action = TLI.getOperationAction(Node->getOpcode(),
1231 Node->getValueType(0));
1233 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1239 // FIXME: Model these properly. LOAD and STORE are complicated, and
1240 // STORE expects the unlegalized operand in some cases.
1241 SimpleFinishLegalizing = false;
1243 case ISD::CALLSEQ_START:
1244 case ISD::CALLSEQ_END:
1245 // FIXME: This shouldn't be necessary. These nodes have special properties
1246 // dealing with the recursive nature of legalization. Removing this
1247 // special case should be done as part of making LegalizeDAG non-recursive.
1248 SimpleFinishLegalizing = false;
1250 case ISD::EXTRACT_ELEMENT:
1251 case ISD::FLT_ROUNDS_:
1253 case ISD::MERGE_VALUES:
1254 case ISD::EH_RETURN:
1255 case ISD::FRAME_TO_ARGS_OFFSET:
1256 case ISD::EH_SJLJ_SETJMP:
1257 case ISD::EH_SJLJ_LONGJMP:
1258 // These operations lie about being legal: when they claim to be legal,
1259 // they should actually be expanded.
1260 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1261 if (Action == TargetLowering::Legal)
1262 Action = TargetLowering::Expand;
1264 case ISD::INIT_TRAMPOLINE:
1265 case ISD::ADJUST_TRAMPOLINE:
1266 case ISD::FRAMEADDR:
1267 case ISD::RETURNADDR:
1268 // These operations lie about being legal: when they claim to be legal,
1269 // they should actually be custom-lowered.
1270 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1271 if (Action == TargetLowering::Legal)
1272 Action = TargetLowering::Custom;
1274 case ISD::READ_REGISTER:
1275 case ISD::WRITE_REGISTER:
1276 // Named register is legal in the DAG, but blocked by register name
1277 // selection if not implemented by target (to chose the correct register)
1278 // They'll be converted to Copy(To/From)Reg.
1279 Action = TargetLowering::Legal;
1281 case ISD::DEBUGTRAP:
1282 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1283 if (Action == TargetLowering::Expand) {
1284 // replace ISD::DEBUGTRAP with ISD::TRAP
1286 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1287 Node->getOperand(0));
1288 ReplaceNode(Node, NewVal.getNode());
1289 LegalizeOp(NewVal.getNode());
1295 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1296 Action = TargetLowering::Legal;
1298 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1303 if (SimpleFinishLegalizing) {
1304 SDNode *NewNode = Node;
1305 switch (Node->getOpcode()) {
1312 // Legalizing shifts/rotates requires adjusting the shift amount
1313 // to the appropriate width.
1314 if (!Node->getOperand(1).getValueType().isVector()) {
1316 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1317 Node->getOperand(1));
1318 HandleSDNode Handle(SAO);
1319 LegalizeOp(SAO.getNode());
1320 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1324 case ISD::SRL_PARTS:
1325 case ISD::SRA_PARTS:
1326 case ISD::SHL_PARTS:
1327 // Legalizing shifts/rotates requires adjusting the shift amount
1328 // to the appropriate width.
1329 if (!Node->getOperand(2).getValueType().isVector()) {
1331 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1332 Node->getOperand(2));
1333 HandleSDNode Handle(SAO);
1334 LegalizeOp(SAO.getNode());
1335 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1336 Node->getOperand(1),
1342 if (NewNode != Node) {
1343 ReplaceNode(Node, NewNode);
1347 case TargetLowering::Legal:
1349 case TargetLowering::Custom: {
1350 // FIXME: The handling for custom lowering with multiple results is
1352 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1353 if (Res.getNode()) {
1354 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1357 if (Node->getNumValues() == 1) {
1358 // We can just directly replace this node with the lowered value.
1359 ReplaceNode(SDValue(Node, 0), Res);
1363 SmallVector<SDValue, 8> ResultVals;
1364 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1365 ResultVals.push_back(Res.getValue(i));
1366 ReplaceNode(Node, ResultVals.data());
1371 case TargetLowering::Expand:
1374 case TargetLowering::Promote:
1380 switch (Node->getOpcode()) {
1387 llvm_unreachable("Do not know how to legalize this operator!");
1389 case ISD::CALLSEQ_START:
1390 case ISD::CALLSEQ_END:
1393 return LegalizeLoadOps(Node);
1396 return LegalizeStoreOps(Node);
1401 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1402 SDValue Vec = Op.getOperand(0);
1403 SDValue Idx = Op.getOperand(1);
1406 // Before we generate a new store to a temporary stack slot, see if there is
1407 // already one that we can use. There often is because when we scalarize
1408 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1409 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1410 // the vector. If all are expanded here, we don't want one store per vector
1412 SDValue StackPtr, Ch;
1413 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1414 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1416 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1417 if (ST->isIndexed() || ST->isTruncatingStore() ||
1418 ST->getValue() != Vec)
1421 // Make sure that nothing else could have stored into the destination of
1423 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1426 StackPtr = ST->getBasePtr();
1427 Ch = SDValue(ST, 0);
1432 if (!Ch.getNode()) {
1433 // Store the value to a temporary stack slot, then LOAD the returned part.
1434 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1435 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1436 MachinePointerInfo(), false, false, 0);
1439 // Add the offset to the index.
1441 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1442 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1443 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1445 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1446 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1450 if (Op.getValueType().isVector())
1451 NewLoad = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,
1452 MachinePointerInfo(), false, false, false, 0);
1454 NewLoad = DAG.getExtLoad(
1455 ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, MachinePointerInfo(),
1456 Vec.getValueType().getVectorElementType(), false, false, false, 0);
1458 // Replace the chain going out of the store, by the one out of the load.
1459 DAG.ReplaceAllUsesOfValueWith(Ch, SDValue(NewLoad.getNode(), 1));
1461 // We introduced a cycle though, so update the loads operands, making sure
1462 // to use the original store's chain as an incoming chain.
1463 SmallVector<SDValue, 6> NewLoadOperands(NewLoad->op_begin(),
1465 NewLoadOperands[0] = Ch;
1467 SDValue(DAG.UpdateNodeOperands(NewLoad.getNode(), NewLoadOperands), 0);
1471 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1472 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1474 SDValue Vec = Op.getOperand(0);
1475 SDValue Part = Op.getOperand(1);
1476 SDValue Idx = Op.getOperand(2);
1479 // Store the value to a temporary stack slot, then LOAD the returned part.
1481 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1482 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1483 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1485 // First store the whole vector.
1486 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1489 // Then store the inserted part.
1491 // Add the offset to the index.
1493 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1495 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1496 DAG.getConstant(EltSize, SDLoc(Vec), Idx.getValueType()));
1497 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1499 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1502 // Store the subvector.
1503 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1504 MachinePointerInfo(), false, false, 0);
1506 // Finally, load the updated vector.
1507 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1508 false, false, false, 0);
1511 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1512 // We can't handle this case efficiently. Allocate a sufficiently
1513 // aligned object on the stack, store each element into it, then load
1514 // the result as a vector.
1515 // Create the stack frame object.
1516 EVT VT = Node->getValueType(0);
1517 EVT EltVT = VT.getVectorElementType();
1519 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1520 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1521 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1523 // Emit a store of each element to the stack slot.
1524 SmallVector<SDValue, 8> Stores;
1525 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1526 // Store (in the right endianness) the elements to memory.
1527 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1528 // Ignore undef elements.
1529 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1531 unsigned Offset = TypeByteSize*i;
1533 SDValue Idx = DAG.getConstant(Offset, dl, FIPtr.getValueType());
1534 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1536 // If the destination vector element type is narrower than the source
1537 // element type, only store the bits necessary.
1538 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1539 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1540 Node->getOperand(i), Idx,
1541 PtrInfo.getWithOffset(Offset),
1542 EltVT, false, false, 0));
1544 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1545 Node->getOperand(i), Idx,
1546 PtrInfo.getWithOffset(Offset),
1551 if (!Stores.empty()) // Not all undef elements?
1552 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1554 StoreChain = DAG.getEntryNode();
1556 // Result is a load from the stack slot.
1557 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1558 false, false, false, 0);
1561 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1563 SDValue Tmp1 = Node->getOperand(0);
1564 SDValue Tmp2 = Node->getOperand(1);
1566 // Get the sign bit of the RHS. First obtain a value that has the same
1567 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1569 EVT FloatVT = Tmp2.getValueType();
1570 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1571 if (TLI.isTypeLegal(IVT)) {
1572 // Convert to an integer with the same sign bit.
1573 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1575 auto &DL = DAG.getDataLayout();
1576 // Store the float to memory, then load the sign part out as an integer.
1577 MVT LoadTy = TLI.getPointerTy();
1578 // First create a temporary that is aligned for both the load and store.
1579 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1580 // Then store the float to it.
1582 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1584 if (DL.isBigEndian()) {
1585 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1586 // Load out a legal integer with the same sign bit as the float.
1587 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1588 false, false, false, 0);
1589 } else { // Little endian
1590 SDValue LoadPtr = StackPtr;
1591 // The float may be wider than the integer we are going to load. Advance
1592 // the pointer so that the loaded integer will contain the sign bit.
1593 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1594 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1595 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1596 DAG.getConstant(ByteOffset, dl,
1597 LoadPtr.getValueType()));
1598 // Load a legal integer containing the sign bit.
1599 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1600 false, false, false, 0);
1601 // Move the sign bit to the top bit of the loaded integer.
1602 unsigned BitShift = LoadTy.getSizeInBits() -
1603 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1604 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1606 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1607 DAG.getConstant(BitShift, dl,
1608 TLI.getShiftAmountTy(SignBit.getValueType())));
1611 // Now get the sign bit proper, by seeing whether the value is negative.
1612 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1614 DAG.getConstant(0, dl, SignBit.getValueType()),
1616 // Get the absolute value of the result.
1617 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1618 // Select between the nabs and abs value based on the sign bit of
1620 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1621 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1625 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1626 SmallVectorImpl<SDValue> &Results) {
1627 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1628 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1629 " not tell us which reg is the stack pointer!");
1631 EVT VT = Node->getValueType(0);
1632 SDValue Tmp1 = SDValue(Node, 0);
1633 SDValue Tmp2 = SDValue(Node, 1);
1634 SDValue Tmp3 = Node->getOperand(2);
1635 SDValue Chain = Tmp1.getOperand(0);
1637 // Chain the dynamic stack allocation so that it doesn't modify the stack
1638 // pointer when other instructions are using the stack.
1639 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true), dl);
1641 SDValue Size = Tmp2.getOperand(1);
1642 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1643 Chain = SP.getValue(1);
1644 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1645 unsigned StackAlign =
1646 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1647 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1648 if (Align > StackAlign)
1649 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1650 DAG.getConstant(-(uint64_t)Align, dl, VT));
1651 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1653 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),
1654 DAG.getIntPtrConstant(0, dl, true), SDValue(), dl);
1656 Results.push_back(Tmp1);
1657 Results.push_back(Tmp2);
1660 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1663 /// If the SETCC has been legalized using AND / OR, then the legalized node
1664 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1665 /// will be set to false.
1667 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1668 /// then the values of LHS and RHS will be swapped, CC will be set to the
1669 /// new condition, and NeedInvert will be set to false.
1671 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1672 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1673 /// will be set to true. The caller must invert the result of the SETCC with
1674 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1675 /// of a true/false result.
1677 /// \returns true if the SetCC has been legalized, false if it hasn't.
1678 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1679 SDValue &LHS, SDValue &RHS,
1683 MVT OpVT = LHS.getSimpleValueType();
1684 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1686 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1687 default: llvm_unreachable("Unknown condition code action!");
1688 case TargetLowering::Legal:
1691 case TargetLowering::Expand: {
1692 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1693 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1694 std::swap(LHS, RHS);
1695 CC = DAG.getCondCode(InvCC);
1698 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1701 default: llvm_unreachable("Don't know how to expand this condition!");
1703 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1704 == TargetLowering::Legal
1705 && "If SETO is expanded, SETOEQ must be legal!");
1706 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1708 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1709 == TargetLowering::Legal
1710 && "If SETUO is expanded, SETUNE must be legal!");
1711 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1724 // If we are floating point, assign and break, otherwise fall through.
1725 if (!OpVT.isInteger()) {
1726 // We can use the 4th bit to tell if we are the unordered
1727 // or ordered version of the opcode.
1728 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1729 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1730 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1733 // Fallthrough if we are unsigned integer.
1738 // We only support using the inverted operation, which is computed above
1739 // and not a different manner of supporting expanding these cases.
1740 llvm_unreachable("Don't know how to expand this condition!");
1743 // Try inverting the result of the inverse condition.
1744 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1745 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1746 CC = DAG.getCondCode(InvCC);
1750 // If inverting the condition didn't work then we have no means to expand
1752 llvm_unreachable("Don't know how to expand this condition!");
1755 SDValue SetCC1, SetCC2;
1756 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1757 // If we aren't the ordered or unorder operation,
1758 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1759 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1760 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1762 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1763 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1764 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1766 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1775 /// Emit a store/load combination to the stack. This stores
1776 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1777 /// a load from the stack slot to DestVT, extending it if needed.
1778 /// The resultant code need not be legal.
1779 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1783 // Create the stack frame object.
1784 unsigned SrcAlign = DAG.getDataLayout().getPrefTypeAlignment(
1785 SrcOp.getValueType().getTypeForEVT(*DAG.getContext()));
1786 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1788 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1789 int SPFI = StackPtrFI->getIndex();
1790 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1792 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1793 unsigned SlotSize = SlotVT.getSizeInBits();
1794 unsigned DestSize = DestVT.getSizeInBits();
1795 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1796 unsigned DestAlign = DAG.getDataLayout().getPrefTypeAlignment(DestType);
1798 // Emit a store to the stack slot. Use a truncstore if the input value is
1799 // later than DestVT.
1802 if (SrcSize > SlotSize)
1803 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1804 PtrInfo, SlotVT, false, false, SrcAlign);
1806 assert(SrcSize == SlotSize && "Invalid store");
1807 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1808 PtrInfo, false, false, SrcAlign);
1811 // Result is a load from the stack slot.
1812 if (SlotSize == DestSize)
1813 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1814 false, false, false, DestAlign);
1816 assert(SlotSize < DestSize && "Unknown extension!");
1817 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1818 PtrInfo, SlotVT, false, false, false, DestAlign);
1821 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1823 // Create a vector sized/aligned stack slot, store the value to element #0,
1824 // then load the whole vector back out.
1825 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1827 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1828 int SPFI = StackPtrFI->getIndex();
1830 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1832 MachinePointerInfo::getFixedStack(SPFI),
1833 Node->getValueType(0).getVectorElementType(),
1835 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1836 MachinePointerInfo::getFixedStack(SPFI),
1837 false, false, false, 0);
1841 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1842 const TargetLowering &TLI, SDValue &Res) {
1843 unsigned NumElems = Node->getNumOperands();
1845 EVT VT = Node->getValueType(0);
1847 // Try to group the scalars into pairs, shuffle the pairs together, then
1848 // shuffle the pairs of pairs together, etc. until the vector has
1849 // been built. This will work only if all of the necessary shuffle masks
1852 // We do this in two phases; first to check the legality of the shuffles,
1853 // and next, assuming that all shuffles are legal, to create the new nodes.
1854 for (int Phase = 0; Phase < 2; ++Phase) {
1855 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1857 for (unsigned i = 0; i < NumElems; ++i) {
1858 SDValue V = Node->getOperand(i);
1859 if (V.getOpcode() == ISD::UNDEF)
1864 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1865 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1868 while (IntermedVals.size() > 2) {
1869 NewIntermedVals.clear();
1870 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1871 // This vector and the next vector are shuffled together (simply to
1872 // append the one to the other).
1873 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1875 SmallVector<int, 16> FinalIndices;
1876 FinalIndices.reserve(IntermedVals[i].second.size() +
1877 IntermedVals[i+1].second.size());
1880 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1883 FinalIndices.push_back(IntermedVals[i].second[j]);
1885 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1887 ShuffleVec[k] = NumElems + j;
1888 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1893 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1894 IntermedVals[i+1].first,
1896 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1898 NewIntermedVals.push_back(
1899 std::make_pair(Shuffle, std::move(FinalIndices)));
1902 // If we had an odd number of defined values, then append the last
1903 // element to the array of new vectors.
1904 if ((IntermedVals.size() & 1) != 0)
1905 NewIntermedVals.push_back(IntermedVals.back());
1907 IntermedVals.swap(NewIntermedVals);
1910 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1911 "Invalid number of intermediate vectors");
1912 SDValue Vec1 = IntermedVals[0].first;
1914 if (IntermedVals.size() > 1)
1915 Vec2 = IntermedVals[1].first;
1917 Vec2 = DAG.getUNDEF(VT);
1919 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1920 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1921 ShuffleVec[IntermedVals[0].second[i]] = i;
1922 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1923 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1926 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1927 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1934 /// Expand a BUILD_VECTOR node on targets that don't
1935 /// support the operation, but do support the resultant vector type.
1936 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1937 unsigned NumElems = Node->getNumOperands();
1938 SDValue Value1, Value2;
1940 EVT VT = Node->getValueType(0);
1941 EVT OpVT = Node->getOperand(0).getValueType();
1942 EVT EltVT = VT.getVectorElementType();
1944 // If the only non-undef value is the low element, turn this into a
1945 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1946 bool isOnlyLowElement = true;
1947 bool MoreThanTwoValues = false;
1948 bool isConstant = true;
1949 for (unsigned i = 0; i < NumElems; ++i) {
1950 SDValue V = Node->getOperand(i);
1951 if (V.getOpcode() == ISD::UNDEF)
1954 isOnlyLowElement = false;
1955 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1958 if (!Value1.getNode()) {
1960 } else if (!Value2.getNode()) {
1963 } else if (V != Value1 && V != Value2) {
1964 MoreThanTwoValues = true;
1968 if (!Value1.getNode())
1969 return DAG.getUNDEF(VT);
1971 if (isOnlyLowElement)
1972 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1974 // If all elements are constants, create a load from the constant pool.
1976 SmallVector<Constant*, 16> CV;
1977 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1978 if (ConstantFPSDNode *V =
1979 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1980 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1981 } else if (ConstantSDNode *V =
1982 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1984 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1986 // If OpVT and EltVT don't match, EltVT is not legal and the
1987 // element values have been promoted/truncated earlier. Undo this;
1988 // we don't want a v16i8 to become a v16i32 for example.
1989 const ConstantInt *CI = V->getConstantIntValue();
1990 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1991 CI->getZExtValue()));
1994 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1995 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1996 CV.push_back(UndefValue::get(OpNTy));
1999 Constant *CP = ConstantVector::get(CV);
2000 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
2001 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2002 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2003 MachinePointerInfo::getConstantPool(),
2004 false, false, false, Alignment);
2007 SmallSet<SDValue, 16> DefinedValues;
2008 for (unsigned i = 0; i < NumElems; ++i) {
2009 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
2011 DefinedValues.insert(Node->getOperand(i));
2014 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
2015 if (!MoreThanTwoValues) {
2016 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2017 for (unsigned i = 0; i < NumElems; ++i) {
2018 SDValue V = Node->getOperand(i);
2019 if (V.getOpcode() == ISD::UNDEF)
2021 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2023 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2024 // Get the splatted value into the low element of a vector register.
2025 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2027 if (Value2.getNode())
2028 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2030 Vec2 = DAG.getUNDEF(VT);
2032 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2033 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2037 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2042 // Otherwise, we can't handle this case efficiently.
2043 return ExpandVectorBuildThroughStack(Node);
2046 // Expand a node into a call to a libcall. If the result value
2047 // does not fit into a register, return the lo part and set the hi part to the
2048 // by-reg argument. If it does fit into a single register, return the result
2049 // and leave the Hi part unset.
2050 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2052 TargetLowering::ArgListTy Args;
2053 TargetLowering::ArgListEntry Entry;
2054 for (const SDValue &Op : Node->op_values()) {
2055 EVT ArgVT = Op.getValueType();
2056 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2059 Entry.isSExt = isSigned;
2060 Entry.isZExt = !isSigned;
2061 Args.push_back(Entry);
2063 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2064 TLI.getPointerTy());
2066 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2068 // By default, the input chain to this libcall is the entry node of the
2069 // function. If the libcall is going to be emitted as a tail call then
2070 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2071 // node which is being folded has a non-entry input chain.
2072 SDValue InChain = DAG.getEntryNode();
2074 // isTailCall may be true since the callee does not reference caller stack
2075 // frame. Check if it's in the right position.
2076 SDValue TCChain = InChain;
2077 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2081 TargetLowering::CallLoweringInfo CLI(DAG);
2082 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2083 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2084 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2086 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2088 if (!CallInfo.second.getNode())
2089 // It's a tailcall, return the chain (which is the DAG root).
2090 return DAG.getRoot();
2092 return CallInfo.first;
2095 /// Generate a libcall taking the given operands as arguments
2096 /// and returning a result of type RetVT.
2097 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2098 const SDValue *Ops, unsigned NumOps,
2099 bool isSigned, SDLoc dl) {
2100 TargetLowering::ArgListTy Args;
2101 Args.reserve(NumOps);
2103 TargetLowering::ArgListEntry Entry;
2104 for (unsigned i = 0; i != NumOps; ++i) {
2105 Entry.Node = Ops[i];
2106 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2107 Entry.isSExt = isSigned;
2108 Entry.isZExt = !isSigned;
2109 Args.push_back(Entry);
2111 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2112 TLI.getPointerTy());
2114 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2116 TargetLowering::CallLoweringInfo CLI(DAG);
2117 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2118 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2119 .setSExtResult(isSigned).setZExtResult(!isSigned);
2121 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2123 return CallInfo.first;
2126 // Expand a node into a call to a libcall. Similar to
2127 // ExpandLibCall except that the first operand is the in-chain.
2128 std::pair<SDValue, SDValue>
2129 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2132 SDValue InChain = Node->getOperand(0);
2134 TargetLowering::ArgListTy Args;
2135 TargetLowering::ArgListEntry Entry;
2136 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2137 EVT ArgVT = Node->getOperand(i).getValueType();
2138 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2139 Entry.Node = Node->getOperand(i);
2141 Entry.isSExt = isSigned;
2142 Entry.isZExt = !isSigned;
2143 Args.push_back(Entry);
2145 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2146 TLI.getPointerTy());
2148 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2150 TargetLowering::CallLoweringInfo CLI(DAG);
2151 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2152 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2153 .setSExtResult(isSigned).setZExtResult(!isSigned);
2155 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2160 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2161 RTLIB::Libcall Call_F32,
2162 RTLIB::Libcall Call_F64,
2163 RTLIB::Libcall Call_F80,
2164 RTLIB::Libcall Call_F128,
2165 RTLIB::Libcall Call_PPCF128) {
2167 switch (Node->getSimpleValueType(0).SimpleTy) {
2168 default: llvm_unreachable("Unexpected request for libcall!");
2169 case MVT::f32: LC = Call_F32; break;
2170 case MVT::f64: LC = Call_F64; break;
2171 case MVT::f80: LC = Call_F80; break;
2172 case MVT::f128: LC = Call_F128; break;
2173 case MVT::ppcf128: LC = Call_PPCF128; break;
2175 return ExpandLibCall(LC, Node, false);
2178 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2179 RTLIB::Libcall Call_I8,
2180 RTLIB::Libcall Call_I16,
2181 RTLIB::Libcall Call_I32,
2182 RTLIB::Libcall Call_I64,
2183 RTLIB::Libcall Call_I128) {
2185 switch (Node->getSimpleValueType(0).SimpleTy) {
2186 default: llvm_unreachable("Unexpected request for libcall!");
2187 case MVT::i8: LC = Call_I8; break;
2188 case MVT::i16: LC = Call_I16; break;
2189 case MVT::i32: LC = Call_I32; break;
2190 case MVT::i64: LC = Call_I64; break;
2191 case MVT::i128: LC = Call_I128; break;
2193 return ExpandLibCall(LC, Node, isSigned);
2196 /// Return true if divmod libcall is available.
2197 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2198 const TargetLowering &TLI) {
2200 switch (Node->getSimpleValueType(0).SimpleTy) {
2201 default: llvm_unreachable("Unexpected request for libcall!");
2202 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2203 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2204 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2205 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2206 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2209 return TLI.getLibcallName(LC) != nullptr;
2212 /// Only issue divrem libcall if both quotient and remainder are needed.
2213 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2214 // The other use might have been replaced with a divrem already.
2215 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2216 unsigned OtherOpcode = 0;
2218 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2220 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2222 SDValue Op0 = Node->getOperand(0);
2223 SDValue Op1 = Node->getOperand(1);
2224 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2225 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2229 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2230 User->getOperand(0) == Op0 &&
2231 User->getOperand(1) == Op1)
2237 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2239 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2240 SmallVectorImpl<SDValue> &Results) {
2241 unsigned Opcode = Node->getOpcode();
2242 bool isSigned = Opcode == ISD::SDIVREM;
2245 switch (Node->getSimpleValueType(0).SimpleTy) {
2246 default: llvm_unreachable("Unexpected request for libcall!");
2247 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2248 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2249 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2250 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2251 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2254 // The input chain to this libcall is the entry node of the function.
2255 // Legalizing the call will automatically add the previous call to the
2257 SDValue InChain = DAG.getEntryNode();
2259 EVT RetVT = Node->getValueType(0);
2260 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2262 TargetLowering::ArgListTy Args;
2263 TargetLowering::ArgListEntry Entry;
2264 for (const SDValue &Op : Node->op_values()) {
2265 EVT ArgVT = Op.getValueType();
2266 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2269 Entry.isSExt = isSigned;
2270 Entry.isZExt = !isSigned;
2271 Args.push_back(Entry);
2274 // Also pass the return address of the remainder.
2275 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2277 Entry.Ty = RetTy->getPointerTo();
2278 Entry.isSExt = isSigned;
2279 Entry.isZExt = !isSigned;
2280 Args.push_back(Entry);
2282 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2283 TLI.getPointerTy());
2286 TargetLowering::CallLoweringInfo CLI(DAG);
2287 CLI.setDebugLoc(dl).setChain(InChain)
2288 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2289 .setSExtResult(isSigned).setZExtResult(!isSigned);
2291 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2293 // Remainder is loaded back from the stack frame.
2294 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2295 MachinePointerInfo(), false, false, false, 0);
2296 Results.push_back(CallInfo.first);
2297 Results.push_back(Rem);
2300 /// Return true if sincos libcall is available.
2301 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2303 switch (Node->getSimpleValueType(0).SimpleTy) {
2304 default: llvm_unreachable("Unexpected request for libcall!");
2305 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2306 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2307 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2308 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2309 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2311 return TLI.getLibcallName(LC) != nullptr;
2314 /// Return true if sincos libcall is available and can be used to combine sin
2316 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2317 const TargetMachine &TM) {
2318 if (!isSinCosLibcallAvailable(Node, TLI))
2320 // GNU sin/cos functions set errno while sincos does not. Therefore
2321 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2322 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2323 if (isGNU && !TM.Options.UnsafeFPMath)
2328 /// Only issue sincos libcall if both sin and cos are needed.
2329 static bool useSinCos(SDNode *Node) {
2330 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2331 ? ISD::FCOS : ISD::FSIN;
2333 SDValue Op0 = Node->getOperand(0);
2334 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2335 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2339 // The other user might have been turned into sincos already.
2340 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2346 /// Issue libcalls to sincos to compute sin / cos pairs.
2348 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2349 SmallVectorImpl<SDValue> &Results) {
2351 switch (Node->getSimpleValueType(0).SimpleTy) {
2352 default: llvm_unreachable("Unexpected request for libcall!");
2353 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2354 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2355 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2356 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2357 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2360 // The input chain to this libcall is the entry node of the function.
2361 // Legalizing the call will automatically add the previous call to the
2363 SDValue InChain = DAG.getEntryNode();
2365 EVT RetVT = Node->getValueType(0);
2366 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2368 TargetLowering::ArgListTy Args;
2369 TargetLowering::ArgListEntry Entry;
2371 // Pass the argument.
2372 Entry.Node = Node->getOperand(0);
2374 Entry.isSExt = false;
2375 Entry.isZExt = false;
2376 Args.push_back(Entry);
2378 // Pass the return address of sin.
2379 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2380 Entry.Node = SinPtr;
2381 Entry.Ty = RetTy->getPointerTo();
2382 Entry.isSExt = false;
2383 Entry.isZExt = false;
2384 Args.push_back(Entry);
2386 // Also pass the return address of the cos.
2387 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2388 Entry.Node = CosPtr;
2389 Entry.Ty = RetTy->getPointerTo();
2390 Entry.isSExt = false;
2391 Entry.isZExt = false;
2392 Args.push_back(Entry);
2394 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2395 TLI.getPointerTy());
2398 TargetLowering::CallLoweringInfo CLI(DAG);
2399 CLI.setDebugLoc(dl).setChain(InChain)
2400 .setCallee(TLI.getLibcallCallingConv(LC),
2401 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2403 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2405 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2406 MachinePointerInfo(), false, false, false, 0));
2407 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2408 MachinePointerInfo(), false, false, false, 0));
2411 /// This function is responsible for legalizing a
2412 /// INT_TO_FP operation of the specified operand when the target requests that
2413 /// we expand it. At this point, we know that the result and operand types are
2414 /// legal for the target.
2415 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2419 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2420 // simple 32-bit [signed|unsigned] integer to float/double expansion
2422 // Get the stack frame index of a 8 byte buffer.
2423 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2425 // word offset constant for Hi/Lo address computation
2426 SDValue WordOff = DAG.getConstant(sizeof(int), dl,
2427 StackSlot.getValueType());
2428 // set up Hi and Lo (into buffer) address based on endian
2429 SDValue Hi = StackSlot;
2430 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2431 StackSlot, WordOff);
2432 if (DAG.getDataLayout().isLittleEndian())
2435 // if signed map to unsigned space
2438 // constant used to invert sign bit (signed to unsigned mapping)
2439 SDValue SignBit = DAG.getConstant(0x80000000u, dl, MVT::i32);
2440 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2444 // store the lo of the constructed double - based on integer input
2445 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2446 Op0Mapped, Lo, MachinePointerInfo(),
2448 // initial hi portion of constructed double
2449 SDValue InitialHi = DAG.getConstant(0x43300000u, dl, MVT::i32);
2450 // store the hi of the constructed double - biased exponent
2451 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2452 MachinePointerInfo(),
2454 // load the constructed double
2455 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2456 MachinePointerInfo(), false, false, false, 0);
2457 // FP constant to bias correct the final result
2458 SDValue Bias = DAG.getConstantFP(isSigned ?
2459 BitsToDouble(0x4330000080000000ULL) :
2460 BitsToDouble(0x4330000000000000ULL),
2462 // subtract the bias
2463 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2466 // handle final rounding
2467 if (DestVT == MVT::f64) {
2470 } else if (DestVT.bitsLT(MVT::f64)) {
2471 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2472 DAG.getIntPtrConstant(0, dl));
2473 } else if (DestVT.bitsGT(MVT::f64)) {
2474 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2478 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2479 // Code below here assumes !isSigned without checking again.
2481 // Implementation of unsigned i64 to f64 following the algorithm in
2482 // __floatundidf in compiler_rt. This implementation has the advantage
2483 // of performing rounding correctly, both in the default rounding mode
2484 // and in all alternate rounding modes.
2485 // TODO: Generalize this for use with other types.
2486 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2488 DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
2489 SDValue TwoP84PlusTwoP52 =
2490 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), dl,
2493 DAG.getConstant(UINT64_C(0x4530000000000000), dl, MVT::i64);
2495 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2496 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2497 DAG.getConstant(32, dl, MVT::i64));
2498 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2499 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2500 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2501 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2502 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2504 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2507 // Implementation of unsigned i64 to f32.
2508 // TODO: Generalize this for use with other types.
2509 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2510 // For unsigned conversions, convert them to signed conversions using the
2511 // algorithm from the x86_64 __floatundidf in compiler_rt.
2513 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2515 SDValue ShiftConst =
2516 DAG.getConstant(1, dl, TLI.getShiftAmountTy(Op0.getValueType()));
2517 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2518 SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
2519 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2520 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2522 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2523 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2525 // TODO: This really should be implemented using a branch rather than a
2526 // select. We happen to get lucky and machinesink does the right
2527 // thing most of the time. This would be a good candidate for a
2528 //pseudo-op, or, even better, for whole-function isel.
2529 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2530 Op0, DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);
2531 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2534 // Otherwise, implement the fully general conversion.
2536 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2537 DAG.getConstant(UINT64_C(0xfffffffffffff800), dl, MVT::i64));
2538 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2539 DAG.getConstant(UINT64_C(0x800), dl, MVT::i64));
2540 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2541 DAG.getConstant(UINT64_C(0x7ff), dl, MVT::i64));
2542 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), And2,
2543 DAG.getConstant(UINT64_C(0), dl, MVT::i64),
2545 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2546 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), Op0,
2547 DAG.getConstant(UINT64_C(0x0020000000000000), dl,
2550 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2551 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2553 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2554 DAG.getConstant(32, dl, SHVT));
2555 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2556 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2558 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), dl,
2560 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2561 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2562 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2563 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2564 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2565 DAG.getIntPtrConstant(0, dl));
2568 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2570 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2572 DAG.getConstant(0, dl, Op0.getValueType()),
2574 SDValue Zero = DAG.getIntPtrConstant(0, dl),
2575 Four = DAG.getIntPtrConstant(4, dl);
2576 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2577 SignSet, Four, Zero);
2579 // If the sign bit of the integer is set, the large number will be treated
2580 // as a negative number. To counteract this, the dynamic code adds an
2581 // offset depending on the data type.
2583 switch (Op0.getSimpleValueType().SimpleTy) {
2584 default: llvm_unreachable("Unsupported integer type!");
2585 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2586 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2587 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2588 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2590 if (DAG.getDataLayout().isLittleEndian())
2592 Constant *FudgeFactor = ConstantInt::get(
2593 Type::getInt64Ty(*DAG.getContext()), FF);
2595 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2596 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2597 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2598 Alignment = std::min(Alignment, 4u);
2600 if (DestVT == MVT::f32)
2601 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2602 MachinePointerInfo::getConstantPool(),
2603 false, false, false, Alignment);
2605 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2606 DAG.getEntryNode(), CPIdx,
2607 MachinePointerInfo::getConstantPool(),
2608 MVT::f32, false, false, false, Alignment);
2609 HandleSDNode Handle(Load);
2610 LegalizeOp(Load.getNode());
2611 FudgeInReg = Handle.getValue();
2614 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2617 /// This function is responsible for legalizing a
2618 /// *INT_TO_FP operation of the specified operand when the target requests that
2619 /// we promote it. At this point, we know that the result and operand types are
2620 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2621 /// operation that takes a larger input.
2622 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2626 // First step, figure out the appropriate *INT_TO_FP operation to use.
2627 EVT NewInTy = LegalOp.getValueType();
2629 unsigned OpToUse = 0;
2631 // Scan for the appropriate larger type to use.
2633 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2634 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2636 // If the target supports SINT_TO_FP of this type, use it.
2637 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2638 OpToUse = ISD::SINT_TO_FP;
2641 if (isSigned) continue;
2643 // If the target supports UINT_TO_FP of this type, use it.
2644 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2645 OpToUse = ISD::UINT_TO_FP;
2649 // Otherwise, try a larger type.
2652 // Okay, we found the operation and type to use. Zero extend our input to the
2653 // desired type then run the operation on it.
2654 return DAG.getNode(OpToUse, dl, DestVT,
2655 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2656 dl, NewInTy, LegalOp));
2659 /// This function is responsible for legalizing a
2660 /// FP_TO_*INT operation of the specified operand when the target requests that
2661 /// we promote it. At this point, we know that the result and operand types are
2662 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2663 /// operation that returns a larger result.
2664 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2668 // First step, figure out the appropriate FP_TO*INT operation to use.
2669 EVT NewOutTy = DestVT;
2671 unsigned OpToUse = 0;
2673 // Scan for the appropriate larger type to use.
2675 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2676 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2678 // A larger signed type can hold all unsigned values of the requested type,
2679 // so using FP_TO_SINT is valid
2680 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2681 OpToUse = ISD::FP_TO_SINT;
2685 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2686 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2687 OpToUse = ISD::FP_TO_UINT;
2691 // Otherwise, try a larger type.
2695 // Okay, we found the operation and type to use.
2696 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2698 // Truncate the result of the extended FP_TO_*INT operation to the desired
2700 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2703 /// Open code the operations for BSWAP of the specified operation.
2704 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2705 EVT VT = Op.getValueType();
2706 EVT SHVT = TLI.getShiftAmountTy(VT);
2707 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2708 switch (VT.getSimpleVT().SimpleTy) {
2709 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2711 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2712 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2713 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2715 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2716 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2717 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2718 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2719 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2720 DAG.getConstant(0xFF0000, dl, VT));
2721 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, dl, VT));
2722 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2723 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2724 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2726 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2727 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2728 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2729 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2730 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, dl, SHVT));
2731 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, dl, SHVT));
2732 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, dl, SHVT));
2733 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, dl, SHVT));
2734 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7,
2735 DAG.getConstant(255ULL<<48, dl, VT));
2736 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6,
2737 DAG.getConstant(255ULL<<40, dl, VT));
2738 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5,
2739 DAG.getConstant(255ULL<<32, dl, VT));
2740 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4,
2741 DAG.getConstant(255ULL<<24, dl, VT));
2742 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3,
2743 DAG.getConstant(255ULL<<16, dl, VT));
2744 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2,
2745 DAG.getConstant(255ULL<<8 , dl, VT));
2746 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2747 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2748 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2749 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2750 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2751 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2752 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2756 /// Expand the specified bitcount instruction into operations.
2757 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2760 default: llvm_unreachable("Cannot expand this yet!");
2762 EVT VT = Op.getValueType();
2763 EVT ShVT = TLI.getShiftAmountTy(VT);
2764 unsigned Len = VT.getSizeInBits();
2766 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2767 "CTPOP not implemented for this type.");
2769 // This is the "best" algorithm from
2770 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2772 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)),
2774 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)),
2776 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)),
2778 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)),
2781 // v = v - ((v >> 1) & 0x55555555...)
2782 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2783 DAG.getNode(ISD::AND, dl, VT,
2784 DAG.getNode(ISD::SRL, dl, VT, Op,
2785 DAG.getConstant(1, dl, ShVT)),
2787 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2788 Op = DAG.getNode(ISD::ADD, dl, VT,
2789 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2790 DAG.getNode(ISD::AND, dl, VT,
2791 DAG.getNode(ISD::SRL, dl, VT, Op,
2792 DAG.getConstant(2, dl, ShVT)),
2794 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2795 Op = DAG.getNode(ISD::AND, dl, VT,
2796 DAG.getNode(ISD::ADD, dl, VT, Op,
2797 DAG.getNode(ISD::SRL, dl, VT, Op,
2798 DAG.getConstant(4, dl, ShVT))),
2800 // v = (v * 0x01010101...) >> (Len - 8)
2801 Op = DAG.getNode(ISD::SRL, dl, VT,
2802 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2803 DAG.getConstant(Len - 8, dl, ShVT));
2807 case ISD::CTLZ_ZERO_UNDEF:
2808 // This trivially expands to CTLZ.
2809 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2811 // for now, we do this:
2812 // x = x | (x >> 1);
2813 // x = x | (x >> 2);
2815 // x = x | (x >>16);
2816 // x = x | (x >>32); // for 64-bit input
2817 // return popcount(~x);
2819 // Ref: "Hacker's Delight" by Henry Warren
2820 EVT VT = Op.getValueType();
2821 EVT ShVT = TLI.getShiftAmountTy(VT);
2822 unsigned len = VT.getSizeInBits();
2823 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2824 SDValue Tmp3 = DAG.getConstant(1ULL << i, dl, ShVT);
2825 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2826 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2828 Op = DAG.getNOT(dl, Op, VT);
2829 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2831 case ISD::CTTZ_ZERO_UNDEF:
2832 // This trivially expands to CTTZ.
2833 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2835 // for now, we use: { return popcount(~x & (x - 1)); }
2836 // unless the target has ctlz but not ctpop, in which case we use:
2837 // { return 32 - nlz(~x & (x-1)); }
2838 // Ref: "Hacker's Delight" by Henry Warren
2839 EVT VT = Op.getValueType();
2840 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2841 DAG.getNOT(dl, Op, VT),
2842 DAG.getNode(ISD::SUB, dl, VT, Op,
2843 DAG.getConstant(1, dl, VT)));
2844 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2845 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2846 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2847 return DAG.getNode(ISD::SUB, dl, VT,
2848 DAG.getConstant(VT.getSizeInBits(), dl, VT),
2849 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2850 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2855 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2856 unsigned Opc = Node->getOpcode();
2857 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2858 RTLIB::Libcall LC = RTLIB::getATOMIC(Opc, VT);
2859 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected atomic op or value type!");
2861 return ExpandChainLibCall(LC, Node, false);
2864 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2865 SmallVector<SDValue, 8> Results;
2867 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2869 switch (Node->getOpcode()) {
2872 case ISD::CTLZ_ZERO_UNDEF:
2874 case ISD::CTTZ_ZERO_UNDEF:
2875 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2876 Results.push_back(Tmp1);
2879 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2881 case ISD::FRAMEADDR:
2882 case ISD::RETURNADDR:
2883 case ISD::FRAME_TO_ARGS_OFFSET:
2884 Results.push_back(DAG.getConstant(0, dl, Node->getValueType(0)));
2886 case ISD::FLT_ROUNDS_:
2887 Results.push_back(DAG.getConstant(1, dl, Node->getValueType(0)));
2889 case ISD::EH_RETURN:
2893 case ISD::EH_SJLJ_LONGJMP:
2894 // If the target didn't expand these, there's nothing to do, so just
2895 // preserve the chain and be done.
2896 Results.push_back(Node->getOperand(0));
2898 case ISD::EH_SJLJ_SETJMP:
2899 // If the target didn't expand this, just return 'zero' and preserve the
2901 Results.push_back(DAG.getConstant(0, dl, MVT::i32));
2902 Results.push_back(Node->getOperand(0));
2904 case ISD::ATOMIC_FENCE: {
2905 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2906 // FIXME: handle "fence singlethread" more efficiently.
2907 TargetLowering::ArgListTy Args;
2909 TargetLowering::CallLoweringInfo CLI(DAG);
2910 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
2911 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2912 DAG.getExternalSymbol("__sync_synchronize",
2913 TLI.getPointerTy()), std::move(Args), 0);
2915 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
2917 Results.push_back(CallResult.second);
2920 case ISD::ATOMIC_LOAD: {
2921 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
2922 SDValue Zero = DAG.getConstant(0, dl, Node->getValueType(0));
2923 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2924 SDValue Swap = DAG.getAtomicCmpSwap(
2925 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2926 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
2927 cast<AtomicSDNode>(Node)->getMemOperand(),
2928 cast<AtomicSDNode>(Node)->getOrdering(),
2929 cast<AtomicSDNode>(Node)->getOrdering(),
2930 cast<AtomicSDNode>(Node)->getSynchScope());
2931 Results.push_back(Swap.getValue(0));
2932 Results.push_back(Swap.getValue(1));
2935 case ISD::ATOMIC_STORE: {
2936 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
2937 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
2938 cast<AtomicSDNode>(Node)->getMemoryVT(),
2939 Node->getOperand(0),
2940 Node->getOperand(1), Node->getOperand(2),
2941 cast<AtomicSDNode>(Node)->getMemOperand(),
2942 cast<AtomicSDNode>(Node)->getOrdering(),
2943 cast<AtomicSDNode>(Node)->getSynchScope());
2944 Results.push_back(Swap.getValue(1));
2947 // By default, atomic intrinsics are marked Legal and lowered. Targets
2948 // which don't support them directly, however, may want libcalls, in which
2949 // case they mark them Expand, and we get here.
2950 case ISD::ATOMIC_SWAP:
2951 case ISD::ATOMIC_LOAD_ADD:
2952 case ISD::ATOMIC_LOAD_SUB:
2953 case ISD::ATOMIC_LOAD_AND:
2954 case ISD::ATOMIC_LOAD_OR:
2955 case ISD::ATOMIC_LOAD_XOR:
2956 case ISD::ATOMIC_LOAD_NAND:
2957 case ISD::ATOMIC_LOAD_MIN:
2958 case ISD::ATOMIC_LOAD_MAX:
2959 case ISD::ATOMIC_LOAD_UMIN:
2960 case ISD::ATOMIC_LOAD_UMAX:
2961 case ISD::ATOMIC_CMP_SWAP: {
2962 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
2963 Results.push_back(Tmp.first);
2964 Results.push_back(Tmp.second);
2967 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
2968 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
2969 // splits out the success value as a comparison. Expanding the resulting
2970 // ATOMIC_CMP_SWAP will produce a libcall.
2971 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
2972 SDValue Res = DAG.getAtomicCmpSwap(
2973 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
2974 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
2975 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
2976 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
2977 cast<AtomicSDNode>(Node)->getFailureOrdering(),
2978 cast<AtomicSDNode>(Node)->getSynchScope());
2980 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
2981 Res, Node->getOperand(2), ISD::SETEQ);
2983 Results.push_back(Res.getValue(0));
2984 Results.push_back(Success);
2985 Results.push_back(Res.getValue(1));
2988 case ISD::DYNAMIC_STACKALLOC:
2989 ExpandDYNAMIC_STACKALLOC(Node, Results);
2991 case ISD::MERGE_VALUES:
2992 for (unsigned i = 0; i < Node->getNumValues(); i++)
2993 Results.push_back(Node->getOperand(i));
2996 EVT VT = Node->getValueType(0);
2998 Results.push_back(DAG.getConstant(0, dl, VT));
3000 assert(VT.isFloatingPoint() && "Unknown value type!");
3001 Results.push_back(DAG.getConstantFP(0, dl, VT));
3006 // If this operation is not supported, lower it to 'abort()' call
3007 TargetLowering::ArgListTy Args;
3008 TargetLowering::CallLoweringInfo CLI(DAG);
3009 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3010 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3011 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3012 std::move(Args), 0);
3013 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3015 Results.push_back(CallResult.second);
3020 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3021 Node->getValueType(0), dl);
3022 Results.push_back(Tmp1);
3024 case ISD::FP_EXTEND:
3025 Tmp1 = EmitStackConvert(Node->getOperand(0),
3026 Node->getOperand(0).getValueType(),
3027 Node->getValueType(0), dl);
3028 Results.push_back(Tmp1);
3030 case ISD::SIGN_EXTEND_INREG: {
3031 // NOTE: we could fall back on load/store here too for targets without
3032 // SAR. However, it is doubtful that any exist.
3033 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3034 EVT VT = Node->getValueType(0);
3035 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3038 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3039 ExtraVT.getScalarType().getSizeInBits();
3040 SDValue ShiftCst = DAG.getConstant(BitsDiff, dl, ShiftAmountTy);
3041 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3042 Node->getOperand(0), ShiftCst);
3043 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3044 Results.push_back(Tmp1);
3047 case ISD::FP_ROUND_INREG: {
3048 // The only way we can lower this is to turn it into a TRUNCSTORE,
3049 // EXTLOAD pair, targeting a temporary location (a stack slot).
3051 // NOTE: there is a choice here between constantly creating new stack
3052 // slots and always reusing the same one. We currently always create
3053 // new ones, as reuse may inhibit scheduling.
3054 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3055 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3056 Node->getValueType(0), dl);
3057 Results.push_back(Tmp1);
3060 case ISD::SINT_TO_FP:
3061 case ISD::UINT_TO_FP:
3062 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3063 Node->getOperand(0), Node->getValueType(0), dl);
3064 Results.push_back(Tmp1);
3066 case ISD::FP_TO_SINT:
3067 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3068 Results.push_back(Tmp1);
3070 case ISD::FP_TO_UINT: {
3071 SDValue True, False;
3072 EVT VT = Node->getOperand(0).getValueType();
3073 EVT NVT = Node->getValueType(0);
3074 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3075 APInt::getNullValue(VT.getSizeInBits()));
3076 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3077 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3078 Tmp1 = DAG.getConstantFP(apf, dl, VT);
3079 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3080 Node->getOperand(0),
3082 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3083 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3084 DAG.getNode(ISD::FSUB, dl, VT,
3085 Node->getOperand(0), Tmp1));
3086 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3087 DAG.getConstant(x, dl, NVT));
3088 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3089 Results.push_back(Tmp1);
3093 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3094 EVT VT = Node->getValueType(0);
3095 Tmp1 = Node->getOperand(0);
3096 Tmp2 = Node->getOperand(1);
3097 unsigned Align = Node->getConstantOperandVal(3);
3099 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3100 MachinePointerInfo(V),
3101 false, false, false, 0);
3102 SDValue VAList = VAListLoad;
3104 if (Align > TLI.getMinStackArgumentAlignment()) {
3105 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3107 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3108 DAG.getConstant(Align - 1, dl,
3109 VAList.getValueType()));
3111 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3112 DAG.getConstant(-(int64_t)Align, dl,
3113 VAList.getValueType()));
3116 // Increment the pointer, VAList, to the next vaarg
3117 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3118 DAG.getConstant(DAG.getDataLayout().getTypeAllocSize(
3119 VT.getTypeForEVT(*DAG.getContext())),
3120 dl, VAList.getValueType()));
3121 // Store the incremented VAList to the legalized pointer
3122 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3123 MachinePointerInfo(V), false, false, 0);
3124 // Load the actual argument out of the pointer VAList
3125 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3126 false, false, false, 0));
3127 Results.push_back(Results[0].getValue(1));
3131 // This defaults to loading a pointer from the input and storing it to the
3132 // output, returning the chain.
3133 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3134 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3135 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3136 Node->getOperand(2), MachinePointerInfo(VS),
3137 false, false, false, 0);
3138 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3139 MachinePointerInfo(VD), false, false, 0);
3140 Results.push_back(Tmp1);
3143 case ISD::EXTRACT_VECTOR_ELT:
3144 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3145 // This must be an access of the only element. Return it.
3146 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3147 Node->getOperand(0));
3149 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3150 Results.push_back(Tmp1);
3152 case ISD::EXTRACT_SUBVECTOR:
3153 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3155 case ISD::INSERT_SUBVECTOR:
3156 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3158 case ISD::CONCAT_VECTORS: {
3159 Results.push_back(ExpandVectorBuildThroughStack(Node));
3162 case ISD::SCALAR_TO_VECTOR:
3163 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3165 case ISD::INSERT_VECTOR_ELT:
3166 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3167 Node->getOperand(1),
3168 Node->getOperand(2), dl));
3170 case ISD::VECTOR_SHUFFLE: {
3171 SmallVector<int, 32> NewMask;
3172 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3174 EVT VT = Node->getValueType(0);
3175 EVT EltVT = VT.getVectorElementType();
3176 SDValue Op0 = Node->getOperand(0);
3177 SDValue Op1 = Node->getOperand(1);
3178 if (!TLI.isTypeLegal(EltVT)) {
3180 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3182 // BUILD_VECTOR operands are allowed to be wider than the element type.
3183 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3185 if (NewEltVT.bitsLT(EltVT)) {
3187 // Convert shuffle node.
3188 // If original node was v4i64 and the new EltVT is i32,
3189 // cast operands to v8i32 and re-build the mask.
3191 // Calculate new VT, the size of the new VT should be equal to original.
3193 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3194 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3195 assert(NewVT.bitsEq(VT));
3197 // cast operands to new VT
3198 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3199 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3201 // Convert the shuffle mask
3202 unsigned int factor =
3203 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3205 // EltVT gets smaller
3208 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3210 for (unsigned fi = 0; fi < factor; ++fi)
3211 NewMask.push_back(Mask[i]);
3214 for (unsigned fi = 0; fi < factor; ++fi)
3215 NewMask.push_back(Mask[i]*factor+fi);
3223 unsigned NumElems = VT.getVectorNumElements();
3224 SmallVector<SDValue, 16> Ops;
3225 for (unsigned i = 0; i != NumElems; ++i) {
3227 Ops.push_back(DAG.getUNDEF(EltVT));
3230 unsigned Idx = Mask[i];
3232 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3234 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy())));
3236 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3238 DAG.getConstant(Idx - NumElems, dl,
3239 TLI.getVectorIdxTy())));
3242 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3243 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3244 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3245 Results.push_back(Tmp1);
3248 case ISD::EXTRACT_ELEMENT: {
3249 EVT OpTy = Node->getOperand(0).getValueType();
3250 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3252 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3253 DAG.getConstant(OpTy.getSizeInBits()/2, dl,
3254 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3255 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3258 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3259 Node->getOperand(0));
3261 Results.push_back(Tmp1);
3264 case ISD::STACKSAVE:
3265 // Expand to CopyFromReg if the target set
3266 // StackPointerRegisterToSaveRestore.
3267 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3268 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3269 Node->getValueType(0)));
3270 Results.push_back(Results[0].getValue(1));
3272 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3273 Results.push_back(Node->getOperand(0));
3276 case ISD::STACKRESTORE:
3277 // Expand to CopyToReg if the target set
3278 // StackPointerRegisterToSaveRestore.
3279 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3280 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3281 Node->getOperand(1)));
3283 Results.push_back(Node->getOperand(0));
3286 case ISD::FCOPYSIGN:
3287 Results.push_back(ExpandFCOPYSIGN(Node));
3290 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3291 Tmp1 = DAG.getConstantFP(-0.0, dl, Node->getValueType(0));
3292 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3293 Node->getOperand(0));
3294 Results.push_back(Tmp1);
3297 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3298 EVT VT = Node->getValueType(0);
3299 Tmp1 = Node->getOperand(0);
3300 Tmp2 = DAG.getConstantFP(0.0, dl, VT);
3301 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3302 Tmp1, Tmp2, ISD::SETUGT);
3303 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3304 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3305 Results.push_back(Tmp1);
3312 // Expand Y = MAX(A, B) -> Y = (A > B) ? A : B
3314 switch (Node->getOpcode()) {
3315 default: llvm_unreachable("How did we get here?");
3316 case ISD::SMAX: Pred = ISD::SETGT; break;
3317 case ISD::SMIN: Pred = ISD::SETLT; break;
3318 case ISD::UMAX: Pred = ISD::SETUGT; break;
3319 case ISD::UMIN: Pred = ISD::SETULT; break;
3321 Tmp1 = Node->getOperand(0);
3322 Tmp2 = Node->getOperand(1);
3323 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp1, Tmp2, Pred);
3324 Results.push_back(Tmp1);
3329 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3330 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3331 RTLIB::FMIN_PPCF128));
3334 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3335 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3336 RTLIB::FMAX_PPCF128));
3339 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3340 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3341 RTLIB::SQRT_PPCF128));
3345 EVT VT = Node->getValueType(0);
3346 bool isSIN = Node->getOpcode() == ISD::FSIN;
3347 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3348 // fcos which share the same operand and both are used.
3349 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3350 canCombineSinCosLibcall(Node, TLI, TM))
3351 && useSinCos(Node)) {
3352 SDVTList VTs = DAG.getVTList(VT, VT);
3353 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3355 Tmp1 = Tmp1.getValue(1);
3356 Results.push_back(Tmp1);
3358 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3359 RTLIB::SIN_F80, RTLIB::SIN_F128,
3360 RTLIB::SIN_PPCF128));
3362 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3363 RTLIB::COS_F80, RTLIB::COS_F128,
3364 RTLIB::COS_PPCF128));
3369 // Expand into sincos libcall.
3370 ExpandSinCosLibCall(Node, Results);
3373 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3374 RTLIB::LOG_F80, RTLIB::LOG_F128,
3375 RTLIB::LOG_PPCF128));
3378 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3379 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3380 RTLIB::LOG2_PPCF128));
3383 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3384 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3385 RTLIB::LOG10_PPCF128));
3388 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3389 RTLIB::EXP_F80, RTLIB::EXP_F128,
3390 RTLIB::EXP_PPCF128));
3393 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3394 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3395 RTLIB::EXP2_PPCF128));
3398 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3399 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3400 RTLIB::TRUNC_PPCF128));
3403 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3404 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3405 RTLIB::FLOOR_PPCF128));
3408 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3409 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3410 RTLIB::CEIL_PPCF128));
3413 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3414 RTLIB::RINT_F80, RTLIB::RINT_F128,
3415 RTLIB::RINT_PPCF128));
3417 case ISD::FNEARBYINT:
3418 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3419 RTLIB::NEARBYINT_F64,
3420 RTLIB::NEARBYINT_F80,
3421 RTLIB::NEARBYINT_F128,
3422 RTLIB::NEARBYINT_PPCF128));
3425 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3429 RTLIB::ROUND_PPCF128));
3432 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3433 RTLIB::POWI_F80, RTLIB::POWI_F128,
3434 RTLIB::POWI_PPCF128));
3437 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3438 RTLIB::POW_F80, RTLIB::POW_F128,
3439 RTLIB::POW_PPCF128));
3442 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3443 RTLIB::DIV_F80, RTLIB::DIV_F128,
3444 RTLIB::DIV_PPCF128));
3447 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3448 RTLIB::REM_F80, RTLIB::REM_F128,
3449 RTLIB::REM_PPCF128));
3452 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3453 RTLIB::FMA_F80, RTLIB::FMA_F128,
3454 RTLIB::FMA_PPCF128));
3457 llvm_unreachable("Illegal fmad should never be formed");
3460 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3461 RTLIB::ADD_F80, RTLIB::ADD_F128,
3462 RTLIB::ADD_PPCF128));
3465 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3466 RTLIB::MUL_F80, RTLIB::MUL_F128,
3467 RTLIB::MUL_PPCF128));
3469 case ISD::FP16_TO_FP: {
3470 if (Node->getValueType(0) == MVT::f32) {
3471 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3475 // We can extend to types bigger than f32 in two steps without changing the
3476 // result. Since "f16 -> f32" is much more commonly available, give CodeGen
3477 // the option of emitting that before resorting to a libcall.
3479 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3481 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3484 case ISD::FP_TO_FP16: {
3485 if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {
3486 SDValue Op = Node->getOperand(0);
3487 MVT SVT = Op.getSimpleValueType();
3488 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3489 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3490 // Under fastmath, we can expand this node into a fround followed by
3491 // a float-half conversion.
3492 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3493 DAG.getIntPtrConstant(0, dl));
3495 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3501 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
3502 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3503 Results.push_back(ExpandLibCall(LC, Node, false));
3506 case ISD::ConstantFP: {
3507 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3508 // Check to see if this FP immediate is already legal.
3509 // If this is a legal constant, turn it into a TargetConstantFP node.
3510 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3511 Results.push_back(ExpandConstantFP(CFP, true));
3515 EVT VT = Node->getValueType(0);
3516 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3517 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3518 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3519 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3520 Results.push_back(Tmp1);
3522 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3523 RTLIB::SUB_F80, RTLIB::SUB_F128,
3524 RTLIB::SUB_PPCF128));
3529 EVT VT = Node->getValueType(0);
3530 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3531 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3532 "Don't know how to expand this subtraction!");
3533 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3534 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
3536 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, dl, VT));
3537 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3542 EVT VT = Node->getValueType(0);
3543 bool isSigned = Node->getOpcode() == ISD::SREM;
3544 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3545 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3546 Tmp2 = Node->getOperand(0);
3547 Tmp3 = Node->getOperand(1);
3548 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3549 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3550 // If div is legal, it's better to do the normal expansion
3551 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3552 useDivRem(Node, isSigned, false))) {
3553 SDVTList VTs = DAG.getVTList(VT, VT);
3554 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3555 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3557 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3558 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3559 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3560 } else if (isSigned)
3561 Tmp1 = ExpandIntLibCall(Node, true,
3563 RTLIB::SREM_I16, RTLIB::SREM_I32,
3564 RTLIB::SREM_I64, RTLIB::SREM_I128);
3566 Tmp1 = ExpandIntLibCall(Node, false,
3568 RTLIB::UREM_I16, RTLIB::UREM_I32,
3569 RTLIB::UREM_I64, RTLIB::UREM_I128);
3570 Results.push_back(Tmp1);
3575 bool isSigned = Node->getOpcode() == ISD::SDIV;
3576 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3577 EVT VT = Node->getValueType(0);
3578 SDVTList VTs = DAG.getVTList(VT, VT);
3579 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3580 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3581 useDivRem(Node, isSigned, true)))
3582 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3583 Node->getOperand(1));
3585 Tmp1 = ExpandIntLibCall(Node, true,
3587 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3588 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3590 Tmp1 = ExpandIntLibCall(Node, false,
3592 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3593 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3594 Results.push_back(Tmp1);
3599 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3601 EVT VT = Node->getValueType(0);
3602 SDVTList VTs = DAG.getVTList(VT, VT);
3603 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3604 "If this wasn't legal, it shouldn't have been created!");
3605 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3606 Node->getOperand(1));
3607 Results.push_back(Tmp1.getValue(1));
3612 // Expand into divrem libcall
3613 ExpandDivRemLibCall(Node, Results);
3616 EVT VT = Node->getValueType(0);
3617 SDVTList VTs = DAG.getVTList(VT, VT);
3618 // See if multiply or divide can be lowered using two-result operations.
3619 // We just need the low half of the multiply; try both the signed
3620 // and unsigned forms. If the target supports both SMUL_LOHI and
3621 // UMUL_LOHI, form a preference by checking which forms of plain
3622 // MULH it supports.
3623 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3624 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3625 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3626 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3627 unsigned OpToUse = 0;
3628 if (HasSMUL_LOHI && !HasMULHS) {
3629 OpToUse = ISD::SMUL_LOHI;
3630 } else if (HasUMUL_LOHI && !HasMULHU) {
3631 OpToUse = ISD::UMUL_LOHI;
3632 } else if (HasSMUL_LOHI) {
3633 OpToUse = ISD::SMUL_LOHI;
3634 } else if (HasUMUL_LOHI) {
3635 OpToUse = ISD::UMUL_LOHI;
3638 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3639 Node->getOperand(1)));
3644 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3645 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3646 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3647 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3648 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3649 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3650 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3651 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3652 SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(), dl,
3653 TLI.getShiftAmountTy(HalfType));
3654 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3655 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3659 Tmp1 = ExpandIntLibCall(Node, false,
3661 RTLIB::MUL_I16, RTLIB::MUL_I32,
3662 RTLIB::MUL_I64, RTLIB::MUL_I128);
3663 Results.push_back(Tmp1);
3668 SDValue LHS = Node->getOperand(0);
3669 SDValue RHS = Node->getOperand(1);
3670 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3671 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3673 Results.push_back(Sum);
3674 EVT ResultType = Node->getValueType(1);
3675 EVT OType = getSetCCResultType(Node->getValueType(0));
3677 SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
3679 // LHSSign -> LHS >= 0
3680 // RHSSign -> RHS >= 0
3681 // SumSign -> Sum >= 0
3684 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3686 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3688 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3689 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3690 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3691 Node->getOpcode() == ISD::SADDO ?
3692 ISD::SETEQ : ISD::SETNE);
3694 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3695 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3697 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3698 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3703 SDValue LHS = Node->getOperand(0);
3704 SDValue RHS = Node->getOperand(1);
3705 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3706 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3708 Results.push_back(Sum);
3710 EVT ResultType = Node->getValueType(1);
3711 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3713 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3714 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3716 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3721 EVT VT = Node->getValueType(0);
3722 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3723 SDValue LHS = Node->getOperand(0);
3724 SDValue RHS = Node->getOperand(1);
3727 static const unsigned Ops[2][3] =
3728 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3729 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3730 bool isSigned = Node->getOpcode() == ISD::SMULO;
3731 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3732 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3733 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3734 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3735 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3737 TopHalf = BottomHalf.getValue(1);
3738 } else if (TLI.isTypeLegal(WideVT)) {
3739 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3740 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3741 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3742 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3743 DAG.getIntPtrConstant(0, dl));
3744 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3745 DAG.getIntPtrConstant(1, dl));
3747 // We can fall back to a libcall with an illegal type for the MUL if we
3748 // have a libcall big enough.
3749 // Also, we can fall back to a division in some cases, but that's a big
3750 // performance hit in the general case.
3751 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3752 if (WideVT == MVT::i16)
3753 LC = RTLIB::MUL_I16;
3754 else if (WideVT == MVT::i32)
3755 LC = RTLIB::MUL_I32;
3756 else if (WideVT == MVT::i64)
3757 LC = RTLIB::MUL_I64;
3758 else if (WideVT == MVT::i128)
3759 LC = RTLIB::MUL_I128;
3760 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3762 // The high part is obtained by SRA'ing all but one of the bits of low
3764 unsigned LoSize = VT.getSizeInBits();
3765 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3766 DAG.getConstant(LoSize - 1, dl,
3767 TLI.getPointerTy()));
3768 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3769 DAG.getConstant(LoSize - 1, dl,
3770 TLI.getPointerTy()));
3772 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3773 // pre-lowered to the correct types. This all depends upon WideVT not
3774 // being a legal type for the architecture and thus has to be split to
3776 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3777 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3778 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3779 DAG.getIntPtrConstant(0, dl));
3780 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3781 DAG.getIntPtrConstant(1, dl));
3782 // Ret is a node with an illegal type. Because such things are not
3783 // generally permitted during this phase of legalization, make sure the
3784 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3786 assert(Ret->use_empty() &&
3787 "Unexpected uses of illegally type from expanded lib call.");
3791 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, dl,
3792 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3793 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3794 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3797 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3798 DAG.getConstant(0, dl, VT), ISD::SETNE);
3800 Results.push_back(BottomHalf);
3801 Results.push_back(TopHalf);
3804 case ISD::BUILD_PAIR: {
3805 EVT PairTy = Node->getValueType(0);
3806 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3807 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3808 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3809 DAG.getConstant(PairTy.getSizeInBits()/2, dl,
3810 TLI.getShiftAmountTy(PairTy)));
3811 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3815 Tmp1 = Node->getOperand(0);
3816 Tmp2 = Node->getOperand(1);
3817 Tmp3 = Node->getOperand(2);
3818 if (Tmp1.getOpcode() == ISD::SETCC) {
3819 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3821 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3823 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3824 DAG.getConstant(0, dl, Tmp1.getValueType()),
3825 Tmp2, Tmp3, ISD::SETNE);
3827 Results.push_back(Tmp1);
3830 SDValue Chain = Node->getOperand(0);
3831 SDValue Table = Node->getOperand(1);
3832 SDValue Index = Node->getOperand(2);
3834 EVT PTy = TLI.getPointerTy();
3836 const DataLayout &TD = DAG.getDataLayout();
3837 unsigned EntrySize =
3838 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3840 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(), Index,
3841 DAG.getConstant(EntrySize, dl, Index.getValueType()));
3842 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3845 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3846 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3847 MachinePointerInfo::getJumpTable(), MemVT,
3848 false, false, false, 0);
3850 if (TM.getRelocationModel() == Reloc::PIC_) {
3851 // For PIC, the sequence is:
3852 // BRIND(load(Jumptable + index) + RelocBase)
3853 // RelocBase can be JumpTable, GOT or some sort of global base.
3854 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3855 TLI.getPICJumpTableRelocBase(Table, DAG));
3857 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3858 Results.push_back(Tmp1);
3862 // Expand brcond's setcc into its constituent parts and create a BR_CC
3864 Tmp1 = Node->getOperand(0);
3865 Tmp2 = Node->getOperand(1);
3866 if (Tmp2.getOpcode() == ISD::SETCC) {
3867 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3868 Tmp1, Tmp2.getOperand(2),
3869 Tmp2.getOperand(0), Tmp2.getOperand(1),
3870 Node->getOperand(2));
3872 // We test only the i1 bit. Skip the AND if UNDEF.
3873 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3874 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3875 DAG.getConstant(1, dl, Tmp2.getValueType()));
3876 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3877 DAG.getCondCode(ISD::SETNE), Tmp3,
3878 DAG.getConstant(0, dl, Tmp3.getValueType()),
3879 Node->getOperand(2));
3881 Results.push_back(Tmp1);
3884 Tmp1 = Node->getOperand(0);
3885 Tmp2 = Node->getOperand(1);
3886 Tmp3 = Node->getOperand(2);
3887 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3888 Tmp3, NeedInvert, dl);
3891 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3892 // condition code, create a new SETCC node.
3894 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3897 // If we expanded the SETCC by inverting the condition code, then wrap
3898 // the existing SETCC in a NOT to restore the intended condition.
3900 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3902 Results.push_back(Tmp1);
3906 // Otherwise, SETCC for the given comparison type must be completely
3907 // illegal; expand it into a SELECT_CC.
3908 EVT VT = Node->getValueType(0);
3910 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3911 case TargetLowering::ZeroOrOneBooleanContent:
3912 case TargetLowering::UndefinedBooleanContent:
3915 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3919 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3920 DAG.getConstant(TrueValue, dl, VT),
3921 DAG.getConstant(0, dl, VT),
3923 Results.push_back(Tmp1);
3926 case ISD::SELECT_CC: {
3927 Tmp1 = Node->getOperand(0); // LHS
3928 Tmp2 = Node->getOperand(1); // RHS
3929 Tmp3 = Node->getOperand(2); // True
3930 Tmp4 = Node->getOperand(3); // False
3931 EVT VT = Node->getValueType(0);
3932 SDValue CC = Node->getOperand(4);
3933 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3935 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3936 // If the condition code is legal, then we need to expand this
3937 // node using SETCC and SELECT.
3938 EVT CmpVT = Tmp1.getValueType();
3939 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
3940 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
3942 EVT CCVT = TLI.getSetCCResultType(*DAG.getContext(), CmpVT);
3943 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
3944 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
3948 // SELECT_CC is legal, so the condition code must not be.
3949 bool Legalized = false;
3950 // Try to legalize by inverting the condition. This is for targets that
3951 // might support an ordered version of a condition, but not the unordered
3952 // version (or vice versa).
3953 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
3954 Tmp1.getValueType().isInteger());
3955 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
3956 // Use the new condition code and swap true and false
3958 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
3960 // If The inverse is not legal, then try to swap the arguments using
3961 // the inverse condition code.
3962 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
3963 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
3964 // The swapped inverse condition is legal, so swap true and false,
3967 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
3972 Legalized = LegalizeSetCCCondCode(
3973 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
3976 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
3978 // If we expanded the SETCC by inverting the condition code, then swap
3979 // the True/False operands to match.
3981 std::swap(Tmp3, Tmp4);
3983 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3984 // condition code, create a new SELECT_CC node.
3986 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
3987 Tmp1, Tmp2, Tmp3, Tmp4, CC);
3989 Tmp2 = DAG.getConstant(0, dl, Tmp1.getValueType());
3990 CC = DAG.getCondCode(ISD::SETNE);
3991 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
3992 Tmp2, Tmp3, Tmp4, CC);
3995 Results.push_back(Tmp1);
3999 Tmp1 = Node->getOperand(0); // Chain
4000 Tmp2 = Node->getOperand(2); // LHS
4001 Tmp3 = Node->getOperand(3); // RHS
4002 Tmp4 = Node->getOperand(1); // CC
4004 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
4005 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
4007 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4009 // If we expanded the SETCC by inverting the condition code, then wrap
4010 // the existing SETCC in a NOT to restore the intended condition.
4012 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
4014 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4016 if (Tmp4.getNode()) {
4017 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4018 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4020 Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType());
4021 Tmp4 = DAG.getCondCode(ISD::SETNE);
4022 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4023 Tmp2, Tmp3, Node->getOperand(4));
4025 Results.push_back(Tmp1);
4028 case ISD::BUILD_VECTOR:
4029 Results.push_back(ExpandBUILD_VECTOR(Node));
4034 // Scalarize vector SRA/SRL/SHL.
4035 EVT VT = Node->getValueType(0);
4036 assert(VT.isVector() && "Unable to legalize non-vector shift");
4037 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4038 unsigned NumElem = VT.getVectorNumElements();
4040 SmallVector<SDValue, 8> Scalars;
4041 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4042 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4044 Node->getOperand(0),
4045 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
4046 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4048 Node->getOperand(1),
4049 DAG.getConstant(Idx, dl, TLI.getVectorIdxTy()));
4050 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4051 VT.getScalarType(), Ex, Sh));
4054 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4055 ReplaceNode(SDValue(Node, 0), Result);
4058 case ISD::GLOBAL_OFFSET_TABLE:
4059 case ISD::GlobalAddress:
4060 case ISD::GlobalTLSAddress:
4061 case ISD::ExternalSymbol:
4062 case ISD::ConstantPool:
4063 case ISD::JumpTable:
4064 case ISD::INTRINSIC_W_CHAIN:
4065 case ISD::INTRINSIC_WO_CHAIN:
4066 case ISD::INTRINSIC_VOID:
4067 // FIXME: Custom lowering for these operations shouldn't return null!
4071 // Replace the original node with the legalized result.
4072 if (!Results.empty())
4073 ReplaceNode(Node, Results.data());
4076 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4077 SmallVector<SDValue, 8> Results;
4078 MVT OVT = Node->getSimpleValueType(0);
4079 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4080 Node->getOpcode() == ISD::SINT_TO_FP ||
4081 Node->getOpcode() == ISD::SETCC) {
4082 OVT = Node->getOperand(0).getSimpleValueType();
4084 if (Node->getOpcode() == ISD::BR_CC)
4085 OVT = Node->getOperand(2).getSimpleValueType();
4086 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4088 SDValue Tmp1, Tmp2, Tmp3;
4089 switch (Node->getOpcode()) {
4091 case ISD::CTTZ_ZERO_UNDEF:
4093 case ISD::CTLZ_ZERO_UNDEF:
4095 // Zero extend the argument.
4096 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4097 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4098 // already the correct result.
4099 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4100 if (Node->getOpcode() == ISD::CTTZ) {
4101 // FIXME: This should set a bit in the zero extended value instead.
4102 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4103 Tmp1, DAG.getConstant(NVT.getSizeInBits(), dl, NVT),
4105 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4106 DAG.getConstant(OVT.getSizeInBits(), dl, NVT), Tmp1);
4107 } else if (Node->getOpcode() == ISD::CTLZ ||
4108 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4109 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4110 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4111 DAG.getConstant(NVT.getSizeInBits() -
4112 OVT.getSizeInBits(), dl, NVT));
4114 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4117 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4118 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4119 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4120 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4121 DAG.getConstant(DiffBits, dl,
4122 TLI.getShiftAmountTy(NVT)));
4123 Results.push_back(Tmp1);
4126 case ISD::FP_TO_UINT:
4127 case ISD::FP_TO_SINT:
4128 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4129 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4130 Results.push_back(Tmp1);
4132 case ISD::UINT_TO_FP:
4133 case ISD::SINT_TO_FP:
4134 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4135 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4136 Results.push_back(Tmp1);
4139 SDValue Chain = Node->getOperand(0); // Get the chain.
4140 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4143 if (OVT.isVector()) {
4144 TruncOp = ISD::BITCAST;
4146 assert(OVT.isInteger()
4147 && "VAARG promotion is supported only for vectors or integer types");
4148 TruncOp = ISD::TRUNCATE;
4151 // Perform the larger operation, then convert back
4152 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4153 Node->getConstantOperandVal(3));
4154 Chain = Tmp1.getValue(1);
4156 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4158 // Modified the chain result - switch anything that used the old chain to
4160 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4161 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4163 UpdatedNodes->insert(Tmp2.getNode());
4164 UpdatedNodes->insert(Chain.getNode());
4172 unsigned ExtOp, TruncOp;
4173 if (OVT.isVector()) {
4174 ExtOp = ISD::BITCAST;
4175 TruncOp = ISD::BITCAST;
4177 assert(OVT.isInteger() && "Cannot promote logic operation");
4178 ExtOp = ISD::ANY_EXTEND;
4179 TruncOp = ISD::TRUNCATE;
4181 // Promote each of the values to the new type.
4182 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4183 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4184 // Perform the larger operation, then convert back
4185 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4186 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4190 unsigned ExtOp, TruncOp;
4191 if (Node->getValueType(0).isVector() ||
4192 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4193 ExtOp = ISD::BITCAST;
4194 TruncOp = ISD::BITCAST;
4195 } else if (Node->getValueType(0).isInteger()) {
4196 ExtOp = ISD::ANY_EXTEND;
4197 TruncOp = ISD::TRUNCATE;
4199 ExtOp = ISD::FP_EXTEND;
4200 TruncOp = ISD::FP_ROUND;
4202 Tmp1 = Node->getOperand(0);
4203 // Promote each of the values to the new type.
4204 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4205 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4206 // Perform the larger operation, then round down.
4207 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4208 if (TruncOp != ISD::FP_ROUND)
4209 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4211 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4212 DAG.getIntPtrConstant(0, dl));
4213 Results.push_back(Tmp1);
4216 case ISD::VECTOR_SHUFFLE: {
4217 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4219 // Cast the two input vectors.
4220 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4221 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4223 // Convert the shuffle mask to the right # elements.
4224 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4225 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4226 Results.push_back(Tmp1);
4230 unsigned ExtOp = ISD::FP_EXTEND;
4231 if (NVT.isInteger()) {
4232 ISD::CondCode CCCode =
4233 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4234 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4236 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4237 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4238 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4239 Tmp1, Tmp2, Node->getOperand(2)));
4243 unsigned ExtOp = ISD::FP_EXTEND;
4244 if (NVT.isInteger()) {
4245 ISD::CondCode CCCode =
4246 cast<CondCodeSDNode>(Node->getOperand(1))->get();
4247 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4249 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4250 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(3));
4251 Results.push_back(DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0),
4252 Node->getOperand(0), Node->getOperand(1),
4253 Tmp1, Tmp2, Node->getOperand(4)));
4263 case ISD::FCOPYSIGN:
4265 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4266 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4267 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4268 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4269 Tmp3, DAG.getIntPtrConstant(0, dl)));
4273 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4274 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4275 Tmp3 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(2));
4277 DAG.getNode(ISD::FP_ROUND, dl, OVT,
4278 DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2, Tmp3),
4279 DAG.getIntPtrConstant(0, dl)));
4283 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4284 Tmp2 = Node->getOperand(1);
4285 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4286 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4287 Tmp3, DAG.getIntPtrConstant(0, dl)));
4293 case ISD::FNEARBYINT:
4306 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4307 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4308 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4309 Tmp2, DAG.getIntPtrConstant(0, dl)));
4314 // Replace the original node with the legalized result.
4315 if (!Results.empty())
4316 ReplaceNode(Node, Results.data());
4319 /// This is the entry point for the file.
4320 void SelectionDAG::Legalize() {
4321 AssignTopologicalOrder();
4323 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4324 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4326 // Visit all the nodes. We start in topological order, so that we see
4327 // nodes with their original operands intact. Legalization can produce
4328 // new nodes which may themselves need to be legalized. Iterate until all
4329 // nodes have been legalized.
4331 bool AnyLegalized = false;
4332 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4336 if (N->use_empty() && N != getRoot().getNode()) {
4342 if (LegalizedNodes.insert(N).second) {
4343 AnyLegalized = true;
4344 Legalizer.LegalizeOp(N);
4346 if (N->use_empty() && N != getRoot().getNode()) {
4357 // Remove dead nodes now.
4361 bool SelectionDAG::LegalizeOp(SDNode *N,
4362 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4363 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4364 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4366 // Directly insert the node in question, and legalize it. This will recurse
4367 // as needed through operands.
4368 LegalizedNodes.insert(N);
4369 Legalizer.LegalizeOp(N);
4371 return LegalizedNodes.count(N);