1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Compiler.h"
26 #include "llvm/ADT/SmallVector.h"
32 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
33 cl::desc("Pop up a window to show dags before legalize"));
35 static const bool ViewLegalizeDAGs = 0;
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDOperand LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 std::map<SDOperand, SDOperand> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 std::map<SDOperand, SDOperand> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
98 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
99 /// concrete packed types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDOperand, SDOperand> PackedNodes;
103 void AddLegalizedOperand(SDOperand From, SDOperand To) {
104 LegalizedNodes.insert(std::make_pair(From, To));
105 // If someone requests legalization of the new node, return itself.
107 LegalizedNodes.insert(std::make_pair(To, To));
109 void AddPromotedOperand(SDOperand From, SDOperand To) {
110 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
111 assert(isNew && "Got into the map somehow?");
112 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
118 SelectionDAGLegalize(SelectionDAG &DAG);
120 /// getTypeAction - Return how we should legalize values of this type, either
121 /// it is already legal or we need to expand it into multiple registers of
122 /// smaller integer type, or we need to promote it to a larger type.
123 LegalizeAction getTypeAction(MVT::ValueType VT) const {
124 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
127 /// isTypeLegal - Return true if this type is legal on this target.
129 bool isTypeLegal(MVT::ValueType VT) const {
130 return getTypeAction(VT) == Legal;
136 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
137 /// appropriate for its type.
138 void HandleOp(SDOperand Op);
140 /// LegalizeOp - We know that the specified value has a legal type.
141 /// Recursively ensure that the operands have legal types, then return the
143 SDOperand LegalizeOp(SDOperand O);
145 /// PromoteOp - Given an operation that produces a value in an invalid type,
146 /// promote it to compute the value into a larger type. The produced value
147 /// will have the correct bits for the low portion of the register, but no
148 /// guarantee is made about the top bits: it may be zero, sign-extended, or
150 SDOperand PromoteOp(SDOperand O);
152 /// ExpandOp - Expand the specified SDOperand into its two component pieces
153 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
154 /// the LegalizeNodes map is filled in for any results that are not expanded,
155 /// the ExpandedNodes map is filled in for any results that are expanded, and
156 /// the Lo/Hi values are returned. This applies to integer types and Vector
158 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
160 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
161 /// two smaller values of MVT::Vector type.
162 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
165 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
166 /// this is called, we know that PackedVT is the right type for the result and
167 /// we know that this type is legal for the target.
168 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
170 /// isShuffleLegal - Return true if a vector shuffle is legal with the
171 /// specified mask and type. Targets can specify exactly which masks they
172 /// support and the code generator is tasked with not creating illegal masks.
174 /// Note that this will also return true for shuffles that are promoted to a
177 /// If this is a legal shuffle, this method returns the (possibly promoted)
178 /// build_vector Mask. If it's not a legal shuffle, it returns null.
179 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
181 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
182 std::set<SDNode*> &NodesLeadingTo);
184 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
186 SDOperand CreateStackTemporary(MVT::ValueType VT);
188 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
190 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
193 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
194 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
195 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
196 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
198 MVT::ValueType DestVT);
199 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand ExpandBSWAP(SDOperand Op);
205 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
206 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
207 SDOperand &Lo, SDOperand &Hi);
208 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
209 SDOperand &Lo, SDOperand &Hi);
211 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
212 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
214 SDOperand getIntPtrConstant(uint64_t Val) {
215 return DAG.getConstant(Val, TLI.getPointerTy());
220 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
221 /// specified mask and type. Targets can specify exactly which masks they
222 /// support and the code generator is tasked with not creating illegal masks.
224 /// Note that this will also return true for shuffles that are promoted to a
226 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
227 SDOperand Mask) const {
228 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
230 case TargetLowering::Legal:
231 case TargetLowering::Custom:
233 case TargetLowering::Promote: {
234 // If this is promoted to a different type, convert the shuffle mask and
235 // ask if it is legal in the promoted type!
236 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
238 // If we changed # elements, change the shuffle mask.
239 unsigned NumEltsGrowth =
240 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
241 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
242 if (NumEltsGrowth > 1) {
243 // Renumber the elements.
244 SmallVector<SDOperand, 8> Ops;
245 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
246 SDOperand InOp = Mask.getOperand(i);
247 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
248 if (InOp.getOpcode() == ISD::UNDEF)
249 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
251 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
252 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
256 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
262 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
265 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
266 /// specified vector opcode.
267 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
269 default: assert(0 && "Don't know how to scalarize this opcode!");
270 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
271 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
272 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
273 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
274 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
275 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
276 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
277 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
281 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
282 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
283 ValueTypeActions(TLI.getValueTypeActions()) {
284 assert(MVT::LAST_VALUETYPE <= 32 &&
285 "Too many value types for ValueTypeActions to hold!");
288 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
289 /// not been visited yet and if all of its operands have already been visited.
290 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
291 std::map<SDNode*, unsigned> &Visited) {
292 if (++Visited[N] != N->getNumOperands())
293 return; // Haven't visited all operands yet
297 if (N->hasOneUse()) { // Tail recurse in common case.
298 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
302 // Now that we have N in, add anything that uses it if all of their operands
304 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
305 ComputeTopDownOrdering(*UI, Order, Visited);
309 void SelectionDAGLegalize::LegalizeDAG() {
310 LastCALLSEQ_END = DAG.getEntryNode();
311 IsLegalizingCall = false;
313 // The legalize process is inherently a bottom-up recursive process (users
314 // legalize their uses before themselves). Given infinite stack space, we
315 // could just start legalizing on the root and traverse the whole graph. In
316 // practice however, this causes us to run out of stack space on large basic
317 // blocks. To avoid this problem, compute an ordering of the nodes where each
318 // node is only legalized after all of its operands are legalized.
319 std::map<SDNode*, unsigned> Visited;
320 std::vector<SDNode*> Order;
322 // Compute ordering from all of the leaves in the graphs, those (like the
323 // entry node) that have no operands.
324 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
325 E = DAG.allnodes_end(); I != E; ++I) {
326 if (I->getNumOperands() == 0) {
328 ComputeTopDownOrdering(I, Order, Visited);
332 assert(Order.size() == Visited.size() &&
334 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
335 "Error: DAG is cyclic!");
338 for (unsigned i = 0, e = Order.size(); i != e; ++i)
339 HandleOp(SDOperand(Order[i], 0));
341 // Finally, it's possible the root changed. Get the new root.
342 SDOperand OldRoot = DAG.getRoot();
343 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
344 DAG.setRoot(LegalizedNodes[OldRoot]);
346 ExpandedNodes.clear();
347 LegalizedNodes.clear();
348 PromotedNodes.clear();
352 // Remove dead nodes now.
353 DAG.RemoveDeadNodes();
357 /// FindCallEndFromCallStart - Given a chained node that is part of a call
358 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
359 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
360 if (Node->getOpcode() == ISD::CALLSEQ_END)
362 if (Node->use_empty())
363 return 0; // No CallSeqEnd
365 // The chain is usually at the end.
366 SDOperand TheChain(Node, Node->getNumValues()-1);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Sometimes it's at the beginning.
369 TheChain = SDOperand(Node, 0);
370 if (TheChain.getValueType() != MVT::Other) {
371 // Otherwise, hunt for it.
372 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
373 if (Node->getValueType(i) == MVT::Other) {
374 TheChain = SDOperand(Node, i);
378 // Otherwise, we walked into a node without a chain.
379 if (TheChain.getValueType() != MVT::Other)
384 for (SDNode::use_iterator UI = Node->use_begin(),
385 E = Node->use_end(); UI != E; ++UI) {
387 // Make sure to only follow users of our token chain.
389 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
390 if (User->getOperand(i) == TheChain)
391 if (SDNode *Result = FindCallEndFromCallStart(User))
397 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
398 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
399 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
400 assert(Node && "Didn't find callseq_start for a call??");
401 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
403 assert(Node->getOperand(0).getValueType() == MVT::Other &&
404 "Node doesn't have a token chain argument!");
405 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
408 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
409 /// see if any uses can reach Dest. If no dest operands can get to dest,
410 /// legalize them, legalize ourself, and return false, otherwise, return true.
412 /// Keep track of the nodes we fine that actually do lead to Dest in
413 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
415 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
416 std::set<SDNode*> &NodesLeadingTo) {
417 if (N == Dest) return true; // N certainly leads to Dest :)
419 // If we've already processed this node and it does lead to Dest, there is no
420 // need to reprocess it.
421 if (NodesLeadingTo.count(N)) return true;
423 // If the first result of this node has been already legalized, then it cannot
425 switch (getTypeAction(N->getValueType(0))) {
427 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
430 if (PromotedNodes.count(SDOperand(N, 0))) return false;
433 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
437 // Okay, this node has not already been legalized. Check and legalize all
438 // operands. If none lead to Dest, then we can legalize this node.
439 bool OperandsLeadToDest = false;
440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
441 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
442 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
444 if (OperandsLeadToDest) {
445 NodesLeadingTo.insert(N);
449 // Okay, this node looks safe, legalize it and return false.
450 HandleOp(SDOperand(N, 0));
454 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
455 /// appropriate for its type.
456 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
457 switch (getTypeAction(Op.getValueType())) {
458 default: assert(0 && "Bad type action!");
459 case Legal: LegalizeOp(Op); break;
460 case Promote: PromoteOp(Op); break;
462 if (Op.getValueType() != MVT::Vector) {
467 unsigned NumOps = N->getNumOperands();
468 unsigned NumElements =
469 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
470 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
471 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
472 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
473 // In the common case, this is a legal vector type, convert it to the
474 // packed operation and type now.
475 PackVectorOp(Op, PackedVT);
476 } else if (NumElements == 1) {
477 // Otherwise, if this is a single element vector, convert it to a
479 PackVectorOp(Op, EVT);
481 // Otherwise, this is a multiple element vector that isn't supported.
482 // Split it in half and legalize both parts.
484 SplitVectorOp(Op, X, Y);
492 /// LegalizeOp - We know that the specified value has a legal type.
493 /// Recursively ensure that the operands have legal types, then return the
495 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
496 assert(isTypeLegal(Op.getValueType()) &&
497 "Caller should expand or promote operands that are not legal!");
498 SDNode *Node = Op.Val;
500 // If this operation defines any values that cannot be represented in a
501 // register on this target, make sure to expand or promote them.
502 if (Node->getNumValues() > 1) {
503 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
504 if (getTypeAction(Node->getValueType(i)) != Legal) {
505 HandleOp(Op.getValue(i));
506 assert(LegalizedNodes.count(Op) &&
507 "Handling didn't add legal operands!");
508 return LegalizedNodes[Op];
512 // Note that LegalizeOp may be reentered even from single-use nodes, which
513 // means that we always must cache transformed nodes.
514 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
515 if (I != LegalizedNodes.end()) return I->second;
517 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
518 SDOperand Result = Op;
519 bool isCustom = false;
521 switch (Node->getOpcode()) {
522 case ISD::FrameIndex:
523 case ISD::EntryToken:
525 case ISD::BasicBlock:
526 case ISD::TargetFrameIndex:
527 case ISD::TargetJumpTable:
528 case ISD::TargetConstant:
529 case ISD::TargetConstantFP:
530 case ISD::TargetConstantPool:
531 case ISD::TargetGlobalAddress:
532 case ISD::TargetExternalSymbol:
537 case ISD::GLOBAL_OFFSET_TABLE:
538 // Primitives must all be legal.
539 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
540 "This must be legal!");
543 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
544 // If this is a target node, legalize it by legalizing the operands then
545 // passing it through.
546 SmallVector<SDOperand, 8> Ops;
547 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
548 Ops.push_back(LegalizeOp(Node->getOperand(i)));
550 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
552 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
553 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
554 return Result.getValue(Op.ResNo);
556 // Otherwise this is an unhandled builtin node. splat.
558 cerr << "NODE: "; Node->dump(); cerr << "\n";
560 assert(0 && "Do not know how to legalize this operator!");
562 case ISD::GlobalAddress:
563 case ISD::ExternalSymbol:
564 case ISD::ConstantPool:
565 case ISD::JumpTable: // Nothing to do.
566 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
567 default: assert(0 && "This action is not supported yet!");
568 case TargetLowering::Custom:
569 Tmp1 = TLI.LowerOperation(Op, DAG);
570 if (Tmp1.Val) Result = Tmp1;
571 // FALLTHROUGH if the target doesn't want to lower this op after all.
572 case TargetLowering::Legal:
576 case ISD::AssertSext:
577 case ISD::AssertZext:
578 Tmp1 = LegalizeOp(Node->getOperand(0));
579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
581 case ISD::MERGE_VALUES:
582 // Legalize eliminates MERGE_VALUES nodes.
583 Result = Node->getOperand(Op.ResNo);
585 case ISD::CopyFromReg:
586 Tmp1 = LegalizeOp(Node->getOperand(0));
587 Result = Op.getValue(0);
588 if (Node->getNumValues() == 2) {
589 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
591 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
592 if (Node->getNumOperands() == 3) {
593 Tmp2 = LegalizeOp(Node->getOperand(2));
594 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
596 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
598 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
600 // Since CopyFromReg produces two values, make sure to remember that we
601 // legalized both of them.
602 AddLegalizedOperand(Op.getValue(0), Result);
603 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
604 return Result.getValue(Op.ResNo);
606 MVT::ValueType VT = Op.getValueType();
607 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
608 default: assert(0 && "This action is not supported yet!");
609 case TargetLowering::Expand:
610 if (MVT::isInteger(VT))
611 Result = DAG.getConstant(0, VT);
612 else if (MVT::isFloatingPoint(VT))
613 Result = DAG.getConstantFP(0, VT);
615 assert(0 && "Unknown value type!");
617 case TargetLowering::Legal:
623 case ISD::INTRINSIC_W_CHAIN:
624 case ISD::INTRINSIC_WO_CHAIN:
625 case ISD::INTRINSIC_VOID: {
626 SmallVector<SDOperand, 8> Ops;
627 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
628 Ops.push_back(LegalizeOp(Node->getOperand(i)));
629 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
631 // Allow the target to custom lower its intrinsics if it wants to.
632 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
633 TargetLowering::Custom) {
634 Tmp3 = TLI.LowerOperation(Result, DAG);
635 if (Tmp3.Val) Result = Tmp3;
638 if (Result.Val->getNumValues() == 1) break;
640 // Must have return value and chain result.
641 assert(Result.Val->getNumValues() == 2 &&
642 "Cannot return more than two values!");
644 // Since loads produce two values, make sure to remember that we
645 // legalized both of them.
646 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
647 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
648 return Result.getValue(Op.ResNo);
652 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
655 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
656 case TargetLowering::Promote:
657 default: assert(0 && "This action is not supported yet!");
658 case TargetLowering::Expand: {
659 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
660 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
661 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
663 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
664 const std::string &FName =
665 cast<StringSDNode>(Node->getOperand(3))->getValue();
666 const std::string &DirName =
667 cast<StringSDNode>(Node->getOperand(4))->getValue();
668 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
670 SmallVector<SDOperand, 8> Ops;
671 Ops.push_back(Tmp1); // chain
672 SDOperand LineOp = Node->getOperand(1);
673 SDOperand ColOp = Node->getOperand(2);
676 Ops.push_back(LineOp); // line #
677 Ops.push_back(ColOp); // col #
678 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
679 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
681 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
682 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
683 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
684 Ops.push_back(DAG.getConstant(ID, MVT::i32));
685 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other,&Ops[0],Ops.size());
688 Result = Tmp1; // chain
692 case TargetLowering::Legal:
693 if (Tmp1 != Node->getOperand(0) ||
694 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
695 SmallVector<SDOperand, 8> Ops;
697 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
698 Ops.push_back(Node->getOperand(1)); // line # must be legal.
699 Ops.push_back(Node->getOperand(2)); // col # must be legal.
701 // Otherwise promote them.
702 Ops.push_back(PromoteOp(Node->getOperand(1)));
703 Ops.push_back(PromoteOp(Node->getOperand(2)));
705 Ops.push_back(Node->getOperand(3)); // filename must be legal.
706 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
707 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
714 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
715 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
716 default: assert(0 && "This action is not supported yet!");
717 case TargetLowering::Legal:
718 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
719 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
720 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
721 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
722 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
727 case ISD::DEBUG_LABEL:
728 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
729 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
730 default: assert(0 && "This action is not supported yet!");
731 case TargetLowering::Legal:
732 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
733 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
734 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
740 // We know we don't need to expand constants here, constants only have one
741 // value and we check that it is fine above.
743 // FIXME: Maybe we should handle things like targets that don't support full
744 // 32-bit immediates?
746 case ISD::ConstantFP: {
747 // Spill FP immediates to the constant pool if the target cannot directly
748 // codegen them. Targets often have some immediate values that can be
749 // efficiently generated into an FP register without a load. We explicitly
750 // leave these constants as ConstantFP nodes for the target to deal with.
751 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
753 // Check to see if this FP immediate is already legal.
754 bool isLegal = false;
755 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
756 E = TLI.legal_fpimm_end(); I != E; ++I)
757 if (CFP->isExactlyValue(*I)) {
762 // If this is a legal constant, turn it into a TargetConstantFP node.
764 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
768 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
769 default: assert(0 && "This action is not supported yet!");
770 case TargetLowering::Custom:
771 Tmp3 = TLI.LowerOperation(Result, DAG);
777 case TargetLowering::Expand:
778 // Otherwise we need to spill the constant to memory.
781 // If a FP immediate is precise when represented as a float and if the
782 // target can do an extending load from float to double, we put it into
783 // the constant pool as a float, even if it's is statically typed as a
785 MVT::ValueType VT = CFP->getValueType(0);
786 bool isDouble = VT == MVT::f64;
787 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
788 Type::FloatTy, CFP->getValue());
789 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
790 // Only do this if the target has a native EXTLOAD instruction from
792 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
793 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
798 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
800 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
801 CPIdx, NULL, 0, MVT::f32);
803 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
808 case ISD::TokenFactor:
809 if (Node->getNumOperands() == 2) {
810 Tmp1 = LegalizeOp(Node->getOperand(0));
811 Tmp2 = LegalizeOp(Node->getOperand(1));
812 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
813 } else if (Node->getNumOperands() == 3) {
814 Tmp1 = LegalizeOp(Node->getOperand(0));
815 Tmp2 = LegalizeOp(Node->getOperand(1));
816 Tmp3 = LegalizeOp(Node->getOperand(2));
817 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
819 SmallVector<SDOperand, 8> Ops;
820 // Legalize the operands.
821 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
822 Ops.push_back(LegalizeOp(Node->getOperand(i)));
823 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
827 case ISD::FORMAL_ARGUMENTS:
829 // The only option for this is to custom lower it.
830 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
831 assert(Tmp3.Val && "Target didn't custom lower this node!");
832 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
833 "Lowering call/formal_arguments produced unexpected # results!");
835 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
836 // remember that we legalized all of them, so it doesn't get relegalized.
837 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
838 Tmp1 = LegalizeOp(Tmp3.getValue(i));
841 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
845 case ISD::BUILD_VECTOR:
846 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
847 default: assert(0 && "This action is not supported yet!");
848 case TargetLowering::Custom:
849 Tmp3 = TLI.LowerOperation(Result, DAG);
855 case TargetLowering::Expand:
856 Result = ExpandBUILD_VECTOR(Result.Val);
860 case ISD::INSERT_VECTOR_ELT:
861 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
862 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
863 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
864 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
866 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
867 Node->getValueType(0))) {
868 default: assert(0 && "This action is not supported yet!");
869 case TargetLowering::Legal:
871 case TargetLowering::Custom:
872 Tmp3 = TLI.LowerOperation(Result, DAG);
878 case TargetLowering::Expand: {
879 // If the insert index is a constant, codegen this as a scalar_to_vector,
880 // then a shuffle that inserts it into the right position in the vector.
881 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
882 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
883 Tmp1.getValueType(), Tmp2);
885 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
886 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
887 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
889 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
890 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
892 SmallVector<SDOperand, 8> ShufOps;
893 for (unsigned i = 0; i != NumElts; ++i) {
894 if (i != InsertPos->getValue())
895 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
897 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
899 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
900 &ShufOps[0], ShufOps.size());
902 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
903 Tmp1, ScVec, ShufMask);
904 Result = LegalizeOp(Result);
908 // If the target doesn't support this, we have to spill the input vector
909 // to a temporary stack slot, update the element, then reload it. This is
910 // badness. We could also load the value into a vector register (either
911 // with a "move to register" or "extload into register" instruction, then
912 // permute it into place, if the idx is a constant and if the idx is
913 // supported by the target.
914 MVT::ValueType VT = Tmp1.getValueType();
915 MVT::ValueType EltVT = Tmp2.getValueType();
916 MVT::ValueType IdxVT = Tmp3.getValueType();
917 MVT::ValueType PtrVT = TLI.getPointerTy();
918 SDOperand StackPtr = CreateStackTemporary(VT);
920 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
922 // Truncate or zero extend offset to target pointer type.
923 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
924 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
925 // Add the offset to the index.
926 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
927 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
928 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
929 // Store the scalar value.
930 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
931 // Load the updated vector.
932 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
937 case ISD::SCALAR_TO_VECTOR:
938 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
939 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
943 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
944 Result = DAG.UpdateNodeOperands(Result, Tmp1);
945 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
946 Node->getValueType(0))) {
947 default: assert(0 && "This action is not supported yet!");
948 case TargetLowering::Legal:
950 case TargetLowering::Custom:
951 Tmp3 = TLI.LowerOperation(Result, DAG);
957 case TargetLowering::Expand:
958 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
962 case ISD::VECTOR_SHUFFLE:
963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
964 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
967 // Allow targets to custom lower the SHUFFLEs they support.
968 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
969 default: assert(0 && "Unknown operation action!");
970 case TargetLowering::Legal:
971 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
972 "vector shuffle should not be created if not legal!");
974 case TargetLowering::Custom:
975 Tmp3 = TLI.LowerOperation(Result, DAG);
981 case TargetLowering::Expand: {
982 MVT::ValueType VT = Node->getValueType(0);
983 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
984 MVT::ValueType PtrVT = TLI.getPointerTy();
985 SDOperand Mask = Node->getOperand(2);
986 unsigned NumElems = Mask.getNumOperands();
987 SmallVector<SDOperand,8> Ops;
988 for (unsigned i = 0; i != NumElems; ++i) {
989 SDOperand Arg = Mask.getOperand(i);
990 if (Arg.getOpcode() == ISD::UNDEF) {
991 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
993 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
994 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
996 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
997 DAG.getConstant(Idx, PtrVT)));
999 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1000 DAG.getConstant(Idx - NumElems, PtrVT)));
1003 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1006 case TargetLowering::Promote: {
1007 // Change base type to a different vector type.
1008 MVT::ValueType OVT = Node->getValueType(0);
1009 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1011 // Cast the two input vectors.
1012 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1013 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1015 // Convert the shuffle mask to the right # elements.
1016 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1017 assert(Tmp3.Val && "Shuffle not legal?");
1018 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1019 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1025 case ISD::EXTRACT_VECTOR_ELT:
1026 Tmp1 = LegalizeOp(Node->getOperand(0));
1027 Tmp2 = LegalizeOp(Node->getOperand(1));
1028 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1030 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1031 Tmp1.getValueType())) {
1032 default: assert(0 && "This action is not supported yet!");
1033 case TargetLowering::Legal:
1035 case TargetLowering::Custom:
1036 Tmp3 = TLI.LowerOperation(Result, DAG);
1042 case TargetLowering::Expand:
1043 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1048 case ISD::VEXTRACT_VECTOR_ELT:
1049 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1052 case ISD::CALLSEQ_START: {
1053 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1055 // Recursively Legalize all of the inputs of the call end that do not lead
1056 // to this call start. This ensures that any libcalls that need be inserted
1057 // are inserted *before* the CALLSEQ_START.
1058 {std::set<SDNode*> NodesLeadingTo;
1059 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1060 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1064 // Now that we legalized all of the inputs (which may have inserted
1065 // libcalls) create the new CALLSEQ_START node.
1066 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1068 // Merge in the last call, to ensure that this call start after the last
1070 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1071 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1072 Tmp1 = LegalizeOp(Tmp1);
1075 // Do not try to legalize the target-specific arguments (#1+).
1076 if (Tmp1 != Node->getOperand(0)) {
1077 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1079 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1082 // Remember that the CALLSEQ_START is legalized.
1083 AddLegalizedOperand(Op.getValue(0), Result);
1084 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1085 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1087 // Now that the callseq_start and all of the non-call nodes above this call
1088 // sequence have been legalized, legalize the call itself. During this
1089 // process, no libcalls can/will be inserted, guaranteeing that no calls
1091 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1092 SDOperand InCallSEQ = LastCALLSEQ_END;
1093 // Note that we are selecting this call!
1094 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1095 IsLegalizingCall = true;
1097 // Legalize the call, starting from the CALLSEQ_END.
1098 LegalizeOp(LastCALLSEQ_END);
1099 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1102 case ISD::CALLSEQ_END:
1103 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1104 // will cause this node to be legalized as well as handling libcalls right.
1105 if (LastCALLSEQ_END.Val != Node) {
1106 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1107 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1108 assert(I != LegalizedNodes.end() &&
1109 "Legalizing the call start should have legalized this node!");
1113 // Otherwise, the call start has been legalized and everything is going
1114 // according to plan. Just legalize ourselves normally here.
1115 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1116 // Do not try to legalize the target-specific arguments (#1+), except for
1117 // an optional flag input.
1118 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1119 if (Tmp1 != Node->getOperand(0)) {
1120 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1122 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1125 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1126 if (Tmp1 != Node->getOperand(0) ||
1127 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1128 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1131 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1134 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1135 // This finishes up call legalization.
1136 IsLegalizingCall = false;
1138 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1139 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1140 if (Node->getNumValues() == 2)
1141 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1142 return Result.getValue(Op.ResNo);
1143 case ISD::DYNAMIC_STACKALLOC: {
1144 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1145 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1146 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1149 Tmp1 = Result.getValue(0);
1150 Tmp2 = Result.getValue(1);
1151 switch (TLI.getOperationAction(Node->getOpcode(),
1152 Node->getValueType(0))) {
1153 default: assert(0 && "This action is not supported yet!");
1154 case TargetLowering::Expand: {
1155 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1156 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1157 " not tell us which reg is the stack pointer!");
1158 SDOperand Chain = Tmp1.getOperand(0);
1159 SDOperand Size = Tmp2.getOperand(1);
1160 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1161 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1162 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1163 Tmp1 = LegalizeOp(Tmp1);
1164 Tmp2 = LegalizeOp(Tmp2);
1167 case TargetLowering::Custom:
1168 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1170 Tmp1 = LegalizeOp(Tmp3);
1171 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1174 case TargetLowering::Legal:
1177 // Since this op produce two values, make sure to remember that we
1178 // legalized both of them.
1179 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1180 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1181 return Op.ResNo ? Tmp2 : Tmp1;
1183 case ISD::INLINEASM: {
1184 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1185 bool Changed = false;
1186 // Legalize all of the operands of the inline asm, in case they are nodes
1187 // that need to be expanded or something. Note we skip the asm string and
1188 // all of the TargetConstant flags.
1189 SDOperand Op = LegalizeOp(Ops[0]);
1190 Changed = Op != Ops[0];
1193 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1194 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1195 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1196 for (++i; NumVals; ++i, --NumVals) {
1197 SDOperand Op = LegalizeOp(Ops[i]);
1206 Op = LegalizeOp(Ops.back());
1207 Changed |= Op != Ops.back();
1212 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1214 // INLINE asm returns a chain and flag, make sure to add both to the map.
1215 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1216 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1217 return Result.getValue(Op.ResNo);
1220 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1221 // Ensure that libcalls are emitted before a branch.
1222 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1223 Tmp1 = LegalizeOp(Tmp1);
1224 LastCALLSEQ_END = DAG.getEntryNode();
1226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1229 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1230 // Ensure that libcalls are emitted before a branch.
1231 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1232 Tmp1 = LegalizeOp(Tmp1);
1233 LastCALLSEQ_END = DAG.getEntryNode();
1235 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1236 default: assert(0 && "Indirect target must be legal type (pointer)!");
1238 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1241 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1245 // Ensure that libcalls are emitted before a branch.
1246 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1247 Tmp1 = LegalizeOp(Tmp1);
1248 LastCALLSEQ_END = DAG.getEntryNode();
1250 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1251 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1253 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1254 default: assert(0 && "This action is not supported yet!");
1255 case TargetLowering::Legal: break;
1256 case TargetLowering::Custom:
1257 Tmp1 = TLI.LowerOperation(Result, DAG);
1258 if (Tmp1.Val) Result = Tmp1;
1260 case TargetLowering::Expand: {
1261 SDOperand Chain = Result.getOperand(0);
1262 SDOperand Table = Result.getOperand(1);
1263 SDOperand Index = Result.getOperand(2);
1265 MVT::ValueType PTy = TLI.getPointerTy();
1266 bool isPIC = TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_;
1267 // PIC jump table entries are 32-bit values.
1268 unsigned EntrySize = isPIC ? 4 : MVT::getSizeInBits(PTy)/8;
1269 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1270 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1271 SDOperand LD = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0);
1273 // For PIC, the sequence is:
1274 // BRIND(load(Jumptable + index) + RelocBase)
1275 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1277 if (TLI.usesGlobalOffsetTable())
1278 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1281 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1282 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1283 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1285 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1292 // Ensure that libcalls are emitted before a return.
1293 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1294 Tmp1 = LegalizeOp(Tmp1);
1295 LastCALLSEQ_END = DAG.getEntryNode();
1297 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1298 case Expand: assert(0 && "It's impossible to expand bools");
1300 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1303 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1305 // The top bits of the promoted condition are not necessarily zero, ensure
1306 // that the value is properly zero extended.
1307 if (!TLI.MaskedValueIsZero(Tmp2,
1308 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1309 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1313 // Basic block destination (Op#2) is always legal.
1314 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1316 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1317 default: assert(0 && "This action is not supported yet!");
1318 case TargetLowering::Legal: break;
1319 case TargetLowering::Custom:
1320 Tmp1 = TLI.LowerOperation(Result, DAG);
1321 if (Tmp1.Val) Result = Tmp1;
1323 case TargetLowering::Expand:
1324 // Expand brcond's setcc into its constituent parts and create a BR_CC
1326 if (Tmp2.getOpcode() == ISD::SETCC) {
1327 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1328 Tmp2.getOperand(0), Tmp2.getOperand(1),
1329 Node->getOperand(2));
1331 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1332 DAG.getCondCode(ISD::SETNE), Tmp2,
1333 DAG.getConstant(0, Tmp2.getValueType()),
1334 Node->getOperand(2));
1340 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1341 // Ensure that libcalls are emitted before a branch.
1342 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1343 Tmp1 = LegalizeOp(Tmp1);
1344 LastCALLSEQ_END = DAG.getEntryNode();
1346 Tmp2 = Node->getOperand(2); // LHS
1347 Tmp3 = Node->getOperand(3); // RHS
1348 Tmp4 = Node->getOperand(1); // CC
1350 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1352 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1353 // the LHS is a legal SETCC itself. In this case, we need to compare
1354 // the result against zero to select between true and false values.
1355 if (Tmp3.Val == 0) {
1356 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1357 Tmp4 = DAG.getCondCode(ISD::SETNE);
1360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1361 Node->getOperand(4));
1363 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1364 default: assert(0 && "Unexpected action for BR_CC!");
1365 case TargetLowering::Legal: break;
1366 case TargetLowering::Custom:
1367 Tmp4 = TLI.LowerOperation(Result, DAG);
1368 if (Tmp4.Val) Result = Tmp4;
1373 LoadSDNode *LD = cast<LoadSDNode>(Node);
1374 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1375 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1377 ISD::LoadExtType ExtType = LD->getExtensionType();
1378 if (ExtType == ISD::NON_EXTLOAD) {
1379 MVT::ValueType VT = Node->getValueType(0);
1380 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1381 Tmp3 = Result.getValue(0);
1382 Tmp4 = Result.getValue(1);
1384 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1385 default: assert(0 && "This action is not supported yet!");
1386 case TargetLowering::Legal: break;
1387 case TargetLowering::Custom:
1388 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1390 Tmp3 = LegalizeOp(Tmp1);
1391 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1394 case TargetLowering::Promote: {
1395 // Only promote a load of vector type to another.
1396 assert(MVT::isVector(VT) && "Cannot promote this load!");
1397 // Change base type to a different vector type.
1398 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1400 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1401 LD->getSrcValueOffset());
1402 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1403 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1407 // Since loads produce two values, make sure to remember that we
1408 // legalized both of them.
1409 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1410 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1411 return Op.ResNo ? Tmp4 : Tmp3;
1413 MVT::ValueType SrcVT = LD->getLoadedVT();
1414 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1415 default: assert(0 && "This action is not supported yet!");
1416 case TargetLowering::Promote:
1417 assert(SrcVT == MVT::i1 &&
1418 "Can only promote extending LOAD from i1 -> i8!");
1419 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1420 LD->getSrcValue(), LD->getSrcValueOffset(),
1422 Tmp1 = Result.getValue(0);
1423 Tmp2 = Result.getValue(1);
1425 case TargetLowering::Custom:
1428 case TargetLowering::Legal:
1429 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1430 Tmp1 = Result.getValue(0);
1431 Tmp2 = Result.getValue(1);
1434 Tmp3 = TLI.LowerOperation(Result, DAG);
1436 Tmp1 = LegalizeOp(Tmp3);
1437 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1441 case TargetLowering::Expand:
1442 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1443 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1444 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1445 LD->getSrcValueOffset());
1446 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1447 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1448 Tmp2 = LegalizeOp(Load.getValue(1));
1451 assert(ExtType != ISD::EXTLOAD && "EXTLOAD should always be supported!");
1452 // Turn the unsupported load into an EXTLOAD followed by an explicit
1453 // zero/sign extend inreg.
1454 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1455 Tmp1, Tmp2, LD->getSrcValue(),
1456 LD->getSrcValueOffset(), SrcVT);
1458 if (ExtType == ISD::SEXTLOAD)
1459 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1460 Result, DAG.getValueType(SrcVT));
1462 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1463 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1464 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1467 // Since loads produce two values, make sure to remember that we legalized
1469 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1470 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1471 return Op.ResNo ? Tmp2 : Tmp1;
1474 case ISD::EXTRACT_ELEMENT: {
1475 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1476 switch (getTypeAction(OpTy)) {
1477 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1479 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1481 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1482 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1483 TLI.getShiftAmountTy()));
1484 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1487 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1488 Node->getOperand(0));
1492 // Get both the low and high parts.
1493 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1494 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1495 Result = Tmp2; // 1 -> Hi
1497 Result = Tmp1; // 0 -> Lo
1503 case ISD::CopyToReg:
1504 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1506 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1507 "Register type must be legal!");
1508 // Legalize the incoming value (must be a legal type).
1509 Tmp2 = LegalizeOp(Node->getOperand(2));
1510 if (Node->getNumValues() == 1) {
1511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1513 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1514 if (Node->getNumOperands() == 4) {
1515 Tmp3 = LegalizeOp(Node->getOperand(3));
1516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1519 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1522 // Since this produces two values, make sure to remember that we legalized
1524 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1525 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1531 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1533 // Ensure that libcalls are emitted before a return.
1534 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1535 Tmp1 = LegalizeOp(Tmp1);
1536 LastCALLSEQ_END = DAG.getEntryNode();
1538 switch (Node->getNumOperands()) {
1540 Tmp2 = Node->getOperand(1);
1541 Tmp3 = Node->getOperand(2); // Signness
1542 switch (getTypeAction(Tmp2.getValueType())) {
1544 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1547 if (Tmp2.getValueType() != MVT::Vector) {
1549 ExpandOp(Tmp2, Lo, Hi);
1551 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1553 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1554 Result = LegalizeOp(Result);
1556 SDNode *InVal = Tmp2.Val;
1558 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1559 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1561 // Figure out if there is a Packed type corresponding to this Vector
1562 // type. If so, convert to the packed type.
1563 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1564 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1565 // Turn this into a return of the packed type.
1566 Tmp2 = PackVectorOp(Tmp2, TVT);
1567 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1568 } else if (NumElems == 1) {
1569 // Turn this into a return of the scalar type.
1570 Tmp2 = PackVectorOp(Tmp2, EVT);
1571 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1573 // FIXME: Returns of gcc generic vectors smaller than a legal type
1574 // should be returned in integer registers!
1576 // The scalarized value type may not be legal, e.g. it might require
1577 // promotion or expansion. Relegalize the return.
1578 Result = LegalizeOp(Result);
1580 // FIXME: Returns of gcc generic vectors larger than a legal vector
1581 // type should be returned by reference!
1583 SplitVectorOp(Tmp2, Lo, Hi);
1584 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi, Tmp3);
1585 Result = LegalizeOp(Result);
1590 Tmp2 = PromoteOp(Node->getOperand(1));
1591 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1592 Result = LegalizeOp(Result);
1597 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1599 default: { // ret <values>
1600 SmallVector<SDOperand, 8> NewValues;
1601 NewValues.push_back(Tmp1);
1602 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1603 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1605 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1606 NewValues.push_back(Node->getOperand(i+1));
1610 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1611 "FIXME: TODO: implement returning non-legal vector types!");
1612 ExpandOp(Node->getOperand(i), Lo, Hi);
1613 NewValues.push_back(Lo);
1614 NewValues.push_back(Node->getOperand(i+1));
1616 NewValues.push_back(Hi);
1617 NewValues.push_back(Node->getOperand(i+1));
1622 assert(0 && "Can't promote multiple return value yet!");
1625 if (NewValues.size() == Node->getNumOperands())
1626 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1628 Result = DAG.getNode(ISD::RET, MVT::Other,
1629 &NewValues[0], NewValues.size());
1634 if (Result.getOpcode() == ISD::RET) {
1635 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1636 default: assert(0 && "This action is not supported yet!");
1637 case TargetLowering::Legal: break;
1638 case TargetLowering::Custom:
1639 Tmp1 = TLI.LowerOperation(Result, DAG);
1640 if (Tmp1.Val) Result = Tmp1;
1646 StoreSDNode *ST = cast<StoreSDNode>(Node);
1647 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1648 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1650 if (!ST->isTruncatingStore()) {
1651 switch (getTypeAction(ST->getStoredVT())) {
1653 Tmp3 = LegalizeOp(ST->getValue());
1654 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1657 MVT::ValueType VT = Tmp3.getValueType();
1658 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1659 default: assert(0 && "This action is not supported yet!");
1660 case TargetLowering::Legal: break;
1661 case TargetLowering::Custom:
1662 Tmp1 = TLI.LowerOperation(Result, DAG);
1663 if (Tmp1.Val) Result = Tmp1;
1665 case TargetLowering::Promote:
1666 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1667 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1668 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1669 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1670 ST->getSrcValue(), ST->getSrcValueOffset());
1676 // Truncate the value and store the result.
1677 Tmp3 = PromoteOp(ST->getValue());
1678 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1679 ST->getSrcValueOffset(), ST->getStoredVT());
1683 unsigned IncrementSize = 0;
1686 // If this is a vector type, then we have to calculate the increment as
1687 // the product of the element size in bytes, and the number of elements
1688 // in the high half of the vector.
1689 if (ST->getValue().getValueType() == MVT::Vector) {
1690 SDNode *InVal = ST->getValue().Val;
1692 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1693 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1695 // Figure out if there is a Packed type corresponding to this Vector
1696 // type. If so, convert to the packed type.
1697 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1698 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1699 // Turn this into a normal store of the packed type.
1700 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1701 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1702 ST->getSrcValueOffset());
1703 Result = LegalizeOp(Result);
1705 } else if (NumElems == 1) {
1706 // Turn this into a normal store of the scalar type.
1707 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1708 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1709 ST->getSrcValueOffset());
1710 // The scalarized value type may not be legal, e.g. it might require
1711 // promotion or expansion. Relegalize the scalar store.
1712 Result = LegalizeOp(Result);
1715 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1716 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1719 ExpandOp(Node->getOperand(1), Lo, Hi);
1720 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1722 if (!TLI.isLittleEndian())
1726 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1727 ST->getSrcValueOffset());
1728 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1729 getIntPtrConstant(IncrementSize));
1730 assert(isTypeLegal(Tmp2.getValueType()) &&
1731 "Pointers must be legal!");
1732 // FIXME: This sets the srcvalue of both halves to be the same, which is
1734 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1735 ST->getSrcValueOffset());
1736 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1741 assert(isTypeLegal(ST->getValue().getValueType()) &&
1742 "Cannot handle illegal TRUNCSTORE yet!");
1743 Tmp3 = LegalizeOp(ST->getValue());
1745 // The only promote case we handle is TRUNCSTORE:i1 X into
1746 // -> TRUNCSTORE:i8 (and X, 1)
1747 if (ST->getStoredVT() == MVT::i1 &&
1748 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1749 // Promote the bool to a mask then store.
1750 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1751 DAG.getConstant(1, Tmp3.getValueType()));
1752 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1753 ST->getSrcValueOffset(), MVT::i8);
1754 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1755 Tmp2 != ST->getBasePtr()) {
1756 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1760 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1761 switch (TLI.getStoreXAction(StVT)) {
1762 default: assert(0 && "This action is not supported yet!");
1763 case TargetLowering::Legal: break;
1764 case TargetLowering::Custom:
1765 Tmp1 = TLI.LowerOperation(Result, DAG);
1766 if (Tmp1.Val) Result = Tmp1;
1773 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1774 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1776 case ISD::STACKSAVE:
1777 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1778 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1779 Tmp1 = Result.getValue(0);
1780 Tmp2 = Result.getValue(1);
1782 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1783 default: assert(0 && "This action is not supported yet!");
1784 case TargetLowering::Legal: break;
1785 case TargetLowering::Custom:
1786 Tmp3 = TLI.LowerOperation(Result, DAG);
1788 Tmp1 = LegalizeOp(Tmp3);
1789 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1792 case TargetLowering::Expand:
1793 // Expand to CopyFromReg if the target set
1794 // StackPointerRegisterToSaveRestore.
1795 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1796 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1797 Node->getValueType(0));
1798 Tmp2 = Tmp1.getValue(1);
1800 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1801 Tmp2 = Node->getOperand(0);
1806 // Since stacksave produce two values, make sure to remember that we
1807 // legalized both of them.
1808 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1809 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1810 return Op.ResNo ? Tmp2 : Tmp1;
1812 case ISD::STACKRESTORE:
1813 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1814 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1815 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1817 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1818 default: assert(0 && "This action is not supported yet!");
1819 case TargetLowering::Legal: break;
1820 case TargetLowering::Custom:
1821 Tmp1 = TLI.LowerOperation(Result, DAG);
1822 if (Tmp1.Val) Result = Tmp1;
1824 case TargetLowering::Expand:
1825 // Expand to CopyToReg if the target set
1826 // StackPointerRegisterToSaveRestore.
1827 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1828 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1836 case ISD::READCYCLECOUNTER:
1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1838 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1839 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1840 Node->getValueType(0))) {
1841 default: assert(0 && "This action is not supported yet!");
1842 case TargetLowering::Legal:
1843 Tmp1 = Result.getValue(0);
1844 Tmp2 = Result.getValue(1);
1846 case TargetLowering::Custom:
1847 Result = TLI.LowerOperation(Result, DAG);
1848 Tmp1 = LegalizeOp(Result.getValue(0));
1849 Tmp2 = LegalizeOp(Result.getValue(1));
1853 // Since rdcc produce two values, make sure to remember that we legalized
1855 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1856 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1860 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1861 case Expand: assert(0 && "It's impossible to expand bools");
1863 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1866 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1867 // Make sure the condition is either zero or one.
1868 if (!TLI.MaskedValueIsZero(Tmp1,
1869 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
1870 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1873 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1874 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1876 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1878 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1879 default: assert(0 && "This action is not supported yet!");
1880 case TargetLowering::Legal: break;
1881 case TargetLowering::Custom: {
1882 Tmp1 = TLI.LowerOperation(Result, DAG);
1883 if (Tmp1.Val) Result = Tmp1;
1886 case TargetLowering::Expand:
1887 if (Tmp1.getOpcode() == ISD::SETCC) {
1888 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1890 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1892 Result = DAG.getSelectCC(Tmp1,
1893 DAG.getConstant(0, Tmp1.getValueType()),
1894 Tmp2, Tmp3, ISD::SETNE);
1897 case TargetLowering::Promote: {
1898 MVT::ValueType NVT =
1899 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1900 unsigned ExtOp, TruncOp;
1901 if (MVT::isVector(Tmp2.getValueType())) {
1902 ExtOp = ISD::BIT_CONVERT;
1903 TruncOp = ISD::BIT_CONVERT;
1904 } else if (MVT::isInteger(Tmp2.getValueType())) {
1905 ExtOp = ISD::ANY_EXTEND;
1906 TruncOp = ISD::TRUNCATE;
1908 ExtOp = ISD::FP_EXTEND;
1909 TruncOp = ISD::FP_ROUND;
1911 // Promote each of the values to the new type.
1912 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1913 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1914 // Perform the larger operation, then round down.
1915 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1916 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1921 case ISD::SELECT_CC: {
1922 Tmp1 = Node->getOperand(0); // LHS
1923 Tmp2 = Node->getOperand(1); // RHS
1924 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1925 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1926 SDOperand CC = Node->getOperand(4);
1928 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1930 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1931 // the LHS is a legal SETCC itself. In this case, we need to compare
1932 // the result against zero to select between true and false values.
1933 if (Tmp2.Val == 0) {
1934 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1935 CC = DAG.getCondCode(ISD::SETNE);
1937 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1939 // Everything is legal, see if we should expand this op or something.
1940 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1941 default: assert(0 && "This action is not supported yet!");
1942 case TargetLowering::Legal: break;
1943 case TargetLowering::Custom:
1944 Tmp1 = TLI.LowerOperation(Result, DAG);
1945 if (Tmp1.Val) Result = Tmp1;
1951 Tmp1 = Node->getOperand(0);
1952 Tmp2 = Node->getOperand(1);
1953 Tmp3 = Node->getOperand(2);
1954 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1956 // If we had to Expand the SetCC operands into a SELECT node, then it may
1957 // not always be possible to return a true LHS & RHS. In this case, just
1958 // return the value we legalized, returned in the LHS
1959 if (Tmp2.Val == 0) {
1964 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1965 default: assert(0 && "Cannot handle this action for SETCC yet!");
1966 case TargetLowering::Custom:
1969 case TargetLowering::Legal:
1970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1972 Tmp3 = TLI.LowerOperation(Result, DAG);
1973 if (Tmp3.Val) Result = Tmp3;
1976 case TargetLowering::Promote: {
1977 // First step, figure out the appropriate operation to use.
1978 // Allow SETCC to not be supported for all legal data types
1979 // Mostly this targets FP
1980 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1981 MVT::ValueType OldVT = NewInTy;
1983 // Scan for the appropriate larger type to use.
1985 NewInTy = (MVT::ValueType)(NewInTy+1);
1987 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1988 "Fell off of the edge of the integer world");
1989 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1990 "Fell off of the edge of the floating point world");
1992 // If the target supports SETCC of this type, use it.
1993 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1996 if (MVT::isInteger(NewInTy))
1997 assert(0 && "Cannot promote Legal Integer SETCC yet");
1999 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2000 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2002 Tmp1 = LegalizeOp(Tmp1);
2003 Tmp2 = LegalizeOp(Tmp2);
2004 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2005 Result = LegalizeOp(Result);
2008 case TargetLowering::Expand:
2009 // Expand a setcc node into a select_cc of the same condition, lhs, and
2010 // rhs that selects between const 1 (true) and const 0 (false).
2011 MVT::ValueType VT = Node->getValueType(0);
2012 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2013 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2014 Node->getOperand(2));
2020 case ISD::MEMMOVE: {
2021 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2022 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2024 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2025 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2026 case Expand: assert(0 && "Cannot expand a byte!");
2028 Tmp3 = LegalizeOp(Node->getOperand(2));
2031 Tmp3 = PromoteOp(Node->getOperand(2));
2035 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2039 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2041 // Length is too big, just take the lo-part of the length.
2043 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2047 Tmp4 = LegalizeOp(Node->getOperand(3));
2050 Tmp4 = PromoteOp(Node->getOperand(3));
2055 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2056 case Expand: assert(0 && "Cannot expand this yet!");
2058 Tmp5 = LegalizeOp(Node->getOperand(4));
2061 Tmp5 = PromoteOp(Node->getOperand(4));
2065 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2066 default: assert(0 && "This action not implemented for this operation!");
2067 case TargetLowering::Custom:
2070 case TargetLowering::Legal:
2071 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2073 Tmp1 = TLI.LowerOperation(Result, DAG);
2074 if (Tmp1.Val) Result = Tmp1;
2077 case TargetLowering::Expand: {
2078 // Otherwise, the target does not support this operation. Lower the
2079 // operation to an explicit libcall as appropriate.
2080 MVT::ValueType IntPtr = TLI.getPointerTy();
2081 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2082 std::vector<std::pair<SDOperand, const Type*> > Args;
2084 const char *FnName = 0;
2085 if (Node->getOpcode() == ISD::MEMSET) {
2086 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2087 // Extend the (previously legalized) ubyte argument to be an int value
2089 if (Tmp3.getValueType() > MVT::i32)
2090 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2092 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2093 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2094 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2097 } else if (Node->getOpcode() == ISD::MEMCPY ||
2098 Node->getOpcode() == ISD::MEMMOVE) {
2099 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2100 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2101 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2102 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2104 assert(0 && "Unknown op!");
2107 std::pair<SDOperand,SDOperand> CallResult =
2108 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2109 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2110 Result = CallResult.second;
2117 case ISD::SHL_PARTS:
2118 case ISD::SRA_PARTS:
2119 case ISD::SRL_PARTS: {
2120 SmallVector<SDOperand, 8> Ops;
2121 bool Changed = false;
2122 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2123 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2124 Changed |= Ops.back() != Node->getOperand(i);
2127 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2129 switch (TLI.getOperationAction(Node->getOpcode(),
2130 Node->getValueType(0))) {
2131 default: assert(0 && "This action is not supported yet!");
2132 case TargetLowering::Legal: break;
2133 case TargetLowering::Custom:
2134 Tmp1 = TLI.LowerOperation(Result, DAG);
2136 SDOperand Tmp2, RetVal(0, 0);
2137 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2138 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2139 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2143 assert(RetVal.Val && "Illegal result number");
2149 // Since these produce multiple values, make sure to remember that we
2150 // legalized all of them.
2151 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2152 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2153 return Result.getValue(Op.ResNo);
2174 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2175 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2176 case Expand: assert(0 && "Not possible");
2178 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2181 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2185 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2187 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2188 default: assert(0 && "BinOp legalize operation not supported");
2189 case TargetLowering::Legal: break;
2190 case TargetLowering::Custom:
2191 Tmp1 = TLI.LowerOperation(Result, DAG);
2192 if (Tmp1.Val) Result = Tmp1;
2194 case TargetLowering::Expand: {
2195 if (Node->getValueType(0) == MVT::i32) {
2196 switch (Node->getOpcode()) {
2197 default: assert(0 && "Do not know how to expand this integer BinOp!");
2200 const char *FnName = Node->getOpcode() == ISD::UDIV
2201 ? "__udivsi3" : "__divsi3";
2203 Result = ExpandLibCall(FnName, Node, Dummy);
2208 assert(MVT::isVector(Node->getValueType(0)) &&
2209 "Cannot expand this binary operator!");
2210 // Expand the operation into a bunch of nasty scalar code.
2211 SmallVector<SDOperand, 8> Ops;
2212 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2213 MVT::ValueType PtrVT = TLI.getPointerTy();
2214 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2216 SDOperand Idx = DAG.getConstant(i, PtrVT);
2217 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2218 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2219 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2221 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2222 &Ops[0], Ops.size());
2225 case TargetLowering::Promote: {
2226 switch (Node->getOpcode()) {
2227 default: assert(0 && "Do not know how to promote this BinOp!");
2231 MVT::ValueType OVT = Node->getValueType(0);
2232 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2233 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2234 // Bit convert each of the values to the new type.
2235 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2236 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2237 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2238 // Bit convert the result back the original type.
2239 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2247 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2248 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2249 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2250 case Expand: assert(0 && "Not possible");
2252 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2255 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2259 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2261 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2262 default: assert(0 && "Operation not supported");
2263 case TargetLowering::Custom:
2264 Tmp1 = TLI.LowerOperation(Result, DAG);
2265 if (Tmp1.Val) Result = Tmp1;
2267 case TargetLowering::Legal: break;
2268 case TargetLowering::Expand:
2269 // If this target supports fabs/fneg natively, do this efficiently.
2270 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2271 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2272 // Get the sign bit of the RHS.
2273 MVT::ValueType IVT =
2274 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2275 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2276 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2277 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2278 // Get the absolute value of the result.
2279 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2280 // Select between the nabs and abs value based on the sign bit of
2282 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2283 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2286 Result = LegalizeOp(Result);
2290 // Otherwise, do bitwise ops!
2292 // copysign -> copysignf/copysign libcall.
2294 if (Node->getValueType(0) == MVT::f32) {
2295 FnName = "copysignf";
2296 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2297 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2298 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2300 FnName = "copysign";
2301 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2302 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2303 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2306 Result = ExpandLibCall(FnName, Node, Dummy);
2313 Tmp1 = LegalizeOp(Node->getOperand(0));
2314 Tmp2 = LegalizeOp(Node->getOperand(1));
2315 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2316 // Since this produces two values, make sure to remember that we legalized
2318 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2319 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2324 Tmp1 = LegalizeOp(Node->getOperand(0));
2325 Tmp2 = LegalizeOp(Node->getOperand(1));
2326 Tmp3 = LegalizeOp(Node->getOperand(2));
2327 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2328 // Since this produces two values, make sure to remember that we legalized
2330 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2331 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2334 case ISD::BUILD_PAIR: {
2335 MVT::ValueType PairTy = Node->getValueType(0);
2336 // TODO: handle the case where the Lo and Hi operands are not of legal type
2337 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2338 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2339 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2340 case TargetLowering::Promote:
2341 case TargetLowering::Custom:
2342 assert(0 && "Cannot promote/custom this yet!");
2343 case TargetLowering::Legal:
2344 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2345 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2347 case TargetLowering::Expand:
2348 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2349 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2350 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2351 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2352 TLI.getShiftAmountTy()));
2353 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2362 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2363 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2365 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2366 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2367 case TargetLowering::Custom:
2370 case TargetLowering::Legal:
2371 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2373 Tmp1 = TLI.LowerOperation(Result, DAG);
2374 if (Tmp1.Val) Result = Tmp1;
2377 case TargetLowering::Expand:
2378 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2379 if (MVT::isInteger(Node->getValueType(0))) {
2380 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2381 TargetLowering::Legal) {
2383 MVT::ValueType VT = Node->getValueType(0);
2384 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2385 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2386 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2388 assert(Node->getValueType(0) == MVT::i32 &&
2389 "Cannot expand this binary operator!");
2390 const char *FnName = Node->getOpcode() == ISD::UREM
2391 ? "__umodsi3" : "__modsi3";
2393 Result = ExpandLibCall(FnName, Node, Dummy);
2396 // Floating point mod -> fmod libcall.
2397 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2399 Result = ExpandLibCall(FnName, Node, Dummy);
2405 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2406 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2408 MVT::ValueType VT = Node->getValueType(0);
2409 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2410 default: assert(0 && "This action is not supported yet!");
2411 case TargetLowering::Custom:
2414 case TargetLowering::Legal:
2415 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2416 Result = Result.getValue(0);
2417 Tmp1 = Result.getValue(1);
2420 Tmp2 = TLI.LowerOperation(Result, DAG);
2422 Result = LegalizeOp(Tmp2);
2423 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2427 case TargetLowering::Expand: {
2428 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2429 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2430 SV->getValue(), SV->getOffset());
2431 // Increment the pointer, VAList, to the next vaarg
2432 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2433 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2434 TLI.getPointerTy()));
2435 // Store the incremented VAList to the legalized pointer
2436 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2438 // Load the actual argument out of the pointer VAList
2439 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2440 Tmp1 = LegalizeOp(Result.getValue(1));
2441 Result = LegalizeOp(Result);
2445 // Since VAARG produces two values, make sure to remember that we
2446 // legalized both of them.
2447 AddLegalizedOperand(SDOperand(Node, 0), Result);
2448 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2449 return Op.ResNo ? Tmp1 : Result;
2453 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2454 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2455 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2457 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2458 default: assert(0 && "This action is not supported yet!");
2459 case TargetLowering::Custom:
2462 case TargetLowering::Legal:
2463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2464 Node->getOperand(3), Node->getOperand(4));
2466 Tmp1 = TLI.LowerOperation(Result, DAG);
2467 if (Tmp1.Val) Result = Tmp1;
2470 case TargetLowering::Expand:
2471 // This defaults to loading a pointer from the input and storing it to the
2472 // output, returning the chain.
2473 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2474 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2475 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2477 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2484 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2485 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2487 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2488 default: assert(0 && "This action is not supported yet!");
2489 case TargetLowering::Custom:
2492 case TargetLowering::Legal:
2493 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2495 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2496 if (Tmp1.Val) Result = Tmp1;
2499 case TargetLowering::Expand:
2500 Result = Tmp1; // Default to a no-op, return the chain
2506 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2507 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2509 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2511 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2512 default: assert(0 && "This action is not supported yet!");
2513 case TargetLowering::Legal: break;
2514 case TargetLowering::Custom:
2515 Tmp1 = TLI.LowerOperation(Result, DAG);
2516 if (Tmp1.Val) Result = Tmp1;
2523 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2524 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2526 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2527 "Cannot handle this yet!");
2528 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2532 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2533 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2534 case TargetLowering::Custom:
2535 assert(0 && "Cannot custom legalize this yet!");
2536 case TargetLowering::Legal:
2537 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2539 case TargetLowering::Promote: {
2540 MVT::ValueType OVT = Tmp1.getValueType();
2541 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2542 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2544 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2545 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2546 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2547 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2550 case TargetLowering::Expand:
2551 Result = ExpandBSWAP(Tmp1);
2559 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2560 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2561 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2562 case TargetLowering::Legal:
2563 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2565 case TargetLowering::Promote: {
2566 MVT::ValueType OVT = Tmp1.getValueType();
2567 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2569 // Zero extend the argument.
2570 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2571 // Perform the larger operation, then subtract if needed.
2572 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2573 switch (Node->getOpcode()) {
2578 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2579 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2580 DAG.getConstant(getSizeInBits(NVT), NVT),
2582 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2583 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2586 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2587 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2588 DAG.getConstant(getSizeInBits(NVT) -
2589 getSizeInBits(OVT), NVT));
2594 case TargetLowering::Expand:
2595 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2606 Tmp1 = LegalizeOp(Node->getOperand(0));
2607 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2608 case TargetLowering::Promote:
2609 case TargetLowering::Custom:
2612 case TargetLowering::Legal:
2613 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2615 Tmp1 = TLI.LowerOperation(Result, DAG);
2616 if (Tmp1.Val) Result = Tmp1;
2619 case TargetLowering::Expand:
2620 switch (Node->getOpcode()) {
2621 default: assert(0 && "Unreachable!");
2623 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2624 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2625 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2628 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2629 MVT::ValueType VT = Node->getValueType(0);
2630 Tmp2 = DAG.getConstantFP(0.0, VT);
2631 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2632 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2633 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2639 MVT::ValueType VT = Node->getValueType(0);
2640 const char *FnName = 0;
2641 switch(Node->getOpcode()) {
2642 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2643 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2644 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2645 default: assert(0 && "Unreachable!");
2648 Result = ExpandLibCall(FnName, Node, Dummy);
2656 // We always lower FPOWI into a libcall. No target support it yet.
2657 const char *FnName = Node->getValueType(0) == MVT::f32
2658 ? "__powisf2" : "__powidf2";
2660 Result = ExpandLibCall(FnName, Node, Dummy);
2663 case ISD::BIT_CONVERT:
2664 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2665 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2667 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2668 Node->getOperand(0).getValueType())) {
2669 default: assert(0 && "Unknown operation action!");
2670 case TargetLowering::Expand:
2671 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2673 case TargetLowering::Legal:
2674 Tmp1 = LegalizeOp(Node->getOperand(0));
2675 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2680 case ISD::VBIT_CONVERT: {
2681 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2682 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2684 // The input has to be a vector type, we have to either scalarize it, pack
2685 // it, or convert it based on whether the input vector type is legal.
2686 SDNode *InVal = Node->getOperand(0).Val;
2688 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2689 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2691 // Figure out if there is a Packed type corresponding to this Vector
2692 // type. If so, convert to the packed type.
2693 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2694 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2695 // Turn this into a bit convert of the packed input.
2696 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2697 PackVectorOp(Node->getOperand(0), TVT));
2699 } else if (NumElems == 1) {
2700 // Turn this into a bit convert of the scalar input.
2701 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2702 PackVectorOp(Node->getOperand(0), EVT));
2705 // FIXME: UNIMP! Store then reload
2706 assert(0 && "Cast from unsupported vector type not implemented yet!");
2710 // Conversion operators. The source and destination have different types.
2711 case ISD::SINT_TO_FP:
2712 case ISD::UINT_TO_FP: {
2713 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2714 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2716 switch (TLI.getOperationAction(Node->getOpcode(),
2717 Node->getOperand(0).getValueType())) {
2718 default: assert(0 && "Unknown operation action!");
2719 case TargetLowering::Custom:
2722 case TargetLowering::Legal:
2723 Tmp1 = LegalizeOp(Node->getOperand(0));
2724 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2726 Tmp1 = TLI.LowerOperation(Result, DAG);
2727 if (Tmp1.Val) Result = Tmp1;
2730 case TargetLowering::Expand:
2731 Result = ExpandLegalINT_TO_FP(isSigned,
2732 LegalizeOp(Node->getOperand(0)),
2733 Node->getValueType(0));
2735 case TargetLowering::Promote:
2736 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2737 Node->getValueType(0),
2743 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2744 Node->getValueType(0), Node->getOperand(0));
2747 Tmp1 = PromoteOp(Node->getOperand(0));
2749 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2750 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2752 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2753 Node->getOperand(0).getValueType());
2755 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2756 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2762 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2764 Tmp1 = LegalizeOp(Node->getOperand(0));
2765 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2768 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2770 // Since the result is legal, we should just be able to truncate the low
2771 // part of the source.
2772 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2775 Result = PromoteOp(Node->getOperand(0));
2776 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2781 case ISD::FP_TO_SINT:
2782 case ISD::FP_TO_UINT:
2783 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2785 Tmp1 = LegalizeOp(Node->getOperand(0));
2787 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2788 default: assert(0 && "Unknown operation action!");
2789 case TargetLowering::Custom:
2792 case TargetLowering::Legal:
2793 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2795 Tmp1 = TLI.LowerOperation(Result, DAG);
2796 if (Tmp1.Val) Result = Tmp1;
2799 case TargetLowering::Promote:
2800 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2801 Node->getOpcode() == ISD::FP_TO_SINT);
2803 case TargetLowering::Expand:
2804 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2805 SDOperand True, False;
2806 MVT::ValueType VT = Node->getOperand(0).getValueType();
2807 MVT::ValueType NVT = Node->getValueType(0);
2808 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2809 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2810 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2811 Node->getOperand(0), Tmp2, ISD::SETLT);
2812 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2813 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2814 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2816 False = DAG.getNode(ISD::XOR, NVT, False,
2817 DAG.getConstant(1ULL << ShiftAmt, NVT));
2818 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2821 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2827 assert(0 && "Shouldn't need to expand other operators here!");
2829 Tmp1 = PromoteOp(Node->getOperand(0));
2830 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2831 Result = LegalizeOp(Result);
2836 case ISD::ANY_EXTEND:
2837 case ISD::ZERO_EXTEND:
2838 case ISD::SIGN_EXTEND:
2839 case ISD::FP_EXTEND:
2841 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2842 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2844 Tmp1 = LegalizeOp(Node->getOperand(0));
2845 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2848 switch (Node->getOpcode()) {
2849 case ISD::ANY_EXTEND:
2850 Tmp1 = PromoteOp(Node->getOperand(0));
2851 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2853 case ISD::ZERO_EXTEND:
2854 Result = PromoteOp(Node->getOperand(0));
2855 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2856 Result = DAG.getZeroExtendInReg(Result,
2857 Node->getOperand(0).getValueType());
2859 case ISD::SIGN_EXTEND:
2860 Result = PromoteOp(Node->getOperand(0));
2861 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2862 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2864 DAG.getValueType(Node->getOperand(0).getValueType()));
2866 case ISD::FP_EXTEND:
2867 Result = PromoteOp(Node->getOperand(0));
2868 if (Result.getValueType() != Op.getValueType())
2869 // Dynamically dead while we have only 2 FP types.
2870 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2873 Result = PromoteOp(Node->getOperand(0));
2874 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2879 case ISD::FP_ROUND_INREG:
2880 case ISD::SIGN_EXTEND_INREG: {
2881 Tmp1 = LegalizeOp(Node->getOperand(0));
2882 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2884 // If this operation is not supported, convert it to a shl/shr or load/store
2886 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2887 default: assert(0 && "This action not supported for this op yet!");
2888 case TargetLowering::Legal:
2889 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2891 case TargetLowering::Expand:
2892 // If this is an integer extend and shifts are supported, do that.
2893 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2894 // NOTE: we could fall back on load/store here too for targets without
2895 // SAR. However, it is doubtful that any exist.
2896 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2897 MVT::getSizeInBits(ExtraVT);
2898 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2899 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2900 Node->getOperand(0), ShiftCst);
2901 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2903 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2904 // The only way we can lower this is to turn it into a TRUNCSTORE,
2905 // EXTLOAD pair, targetting a temporary location (a stack slot).
2907 // NOTE: there is a choice here between constantly creating new stack
2908 // slots and always reusing the same one. We currently always create
2909 // new ones, as reuse may inhibit scheduling.
2910 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2911 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2912 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2913 MachineFunction &MF = DAG.getMachineFunction();
2915 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2916 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2917 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
2918 StackSlot, NULL, 0, ExtraVT);
2919 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2920 Result, StackSlot, NULL, 0, ExtraVT);
2922 assert(0 && "Unknown op");
2930 assert(Result.getValueType() == Op.getValueType() &&
2931 "Bad legalization!");
2933 // Make sure that the generated code is itself legal.
2935 Result = LegalizeOp(Result);
2937 // Note that LegalizeOp may be reentered even from single-use nodes, which
2938 // means that we always must cache transformed nodes.
2939 AddLegalizedOperand(Op, Result);
2943 /// PromoteOp - Given an operation that produces a value in an invalid type,
2944 /// promote it to compute the value into a larger type. The produced value will
2945 /// have the correct bits for the low portion of the register, but no guarantee
2946 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2947 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2948 MVT::ValueType VT = Op.getValueType();
2949 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2950 assert(getTypeAction(VT) == Promote &&
2951 "Caller should expand or legalize operands that are not promotable!");
2952 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2953 "Cannot promote to smaller type!");
2955 SDOperand Tmp1, Tmp2, Tmp3;
2957 SDNode *Node = Op.Val;
2959 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2960 if (I != PromotedNodes.end()) return I->second;
2962 switch (Node->getOpcode()) {
2963 case ISD::CopyFromReg:
2964 assert(0 && "CopyFromReg must be legal!");
2967 cerr << "NODE: "; Node->dump(); cerr << "\n";
2969 assert(0 && "Do not know how to promote this operator!");
2972 Result = DAG.getNode(ISD::UNDEF, NVT);
2976 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2978 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2979 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2981 case ISD::ConstantFP:
2982 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2983 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2987 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2988 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2989 Node->getOperand(1), Node->getOperand(2));
2993 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2995 Result = LegalizeOp(Node->getOperand(0));
2996 assert(Result.getValueType() >= NVT &&
2997 "This truncation doesn't make sense!");
2998 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2999 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3002 // The truncation is not required, because we don't guarantee anything
3003 // about high bits anyway.
3004 Result = PromoteOp(Node->getOperand(0));
3007 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3008 // Truncate the low part of the expanded value to the result type
3009 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3012 case ISD::SIGN_EXTEND:
3013 case ISD::ZERO_EXTEND:
3014 case ISD::ANY_EXTEND:
3015 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3016 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3018 // Input is legal? Just do extend all the way to the larger type.
3019 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3022 // Promote the reg if it's smaller.
3023 Result = PromoteOp(Node->getOperand(0));
3024 // The high bits are not guaranteed to be anything. Insert an extend.
3025 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3026 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3027 DAG.getValueType(Node->getOperand(0).getValueType()));
3028 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3029 Result = DAG.getZeroExtendInReg(Result,
3030 Node->getOperand(0).getValueType());
3034 case ISD::BIT_CONVERT:
3035 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3036 Result = PromoteOp(Result);
3039 case ISD::FP_EXTEND:
3040 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3042 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3043 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3044 case Promote: assert(0 && "Unreachable with 2 FP types!");
3046 // Input is legal? Do an FP_ROUND_INREG.
3047 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3048 DAG.getValueType(VT));
3053 case ISD::SINT_TO_FP:
3054 case ISD::UINT_TO_FP:
3055 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3057 // No extra round required here.
3058 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3062 Result = PromoteOp(Node->getOperand(0));
3063 if (Node->getOpcode() == ISD::SINT_TO_FP)
3064 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3066 DAG.getValueType(Node->getOperand(0).getValueType()));
3068 Result = DAG.getZeroExtendInReg(Result,
3069 Node->getOperand(0).getValueType());
3070 // No extra round required here.
3071 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3074 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3075 Node->getOperand(0));
3076 // Round if we cannot tolerate excess precision.
3077 if (NoExcessFPPrecision)
3078 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3079 DAG.getValueType(VT));
3084 case ISD::SIGN_EXTEND_INREG:
3085 Result = PromoteOp(Node->getOperand(0));
3086 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3087 Node->getOperand(1));
3089 case ISD::FP_TO_SINT:
3090 case ISD::FP_TO_UINT:
3091 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3093 Tmp1 = Node->getOperand(0);
3096 // The input result is prerounded, so we don't have to do anything
3098 Tmp1 = PromoteOp(Node->getOperand(0));
3101 assert(0 && "not implemented");
3103 // If we're promoting a UINT to a larger size, check to see if the new node
3104 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3105 // we can use that instead. This allows us to generate better code for
3106 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3107 // legal, such as PowerPC.
3108 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3109 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3110 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3111 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3112 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3114 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3120 Tmp1 = PromoteOp(Node->getOperand(0));
3121 assert(Tmp1.getValueType() == NVT);
3122 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3123 // NOTE: we do not have to do any extra rounding here for
3124 // NoExcessFPPrecision, because we know the input will have the appropriate
3125 // precision, and these operations don't modify precision at all.
3131 Tmp1 = PromoteOp(Node->getOperand(0));
3132 assert(Tmp1.getValueType() == NVT);
3133 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3134 if (NoExcessFPPrecision)
3135 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3136 DAG.getValueType(VT));
3145 // The input may have strange things in the top bits of the registers, but
3146 // these operations don't care. They may have weird bits going out, but
3147 // that too is okay if they are integer operations.
3148 Tmp1 = PromoteOp(Node->getOperand(0));
3149 Tmp2 = PromoteOp(Node->getOperand(1));
3150 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3151 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3156 Tmp1 = PromoteOp(Node->getOperand(0));
3157 Tmp2 = PromoteOp(Node->getOperand(1));
3158 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3159 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3161 // Floating point operations will give excess precision that we may not be
3162 // able to tolerate. If we DO allow excess precision, just leave it,
3163 // otherwise excise it.
3164 // FIXME: Why would we need to round FP ops more than integer ones?
3165 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3166 if (NoExcessFPPrecision)
3167 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3168 DAG.getValueType(VT));
3173 // These operators require that their input be sign extended.
3174 Tmp1 = PromoteOp(Node->getOperand(0));
3175 Tmp2 = PromoteOp(Node->getOperand(1));
3176 if (MVT::isInteger(NVT)) {
3177 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3178 DAG.getValueType(VT));
3179 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3180 DAG.getValueType(VT));
3182 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3184 // Perform FP_ROUND: this is probably overly pessimistic.
3185 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3186 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3187 DAG.getValueType(VT));
3191 case ISD::FCOPYSIGN:
3192 // These operators require that their input be fp extended.
3193 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3195 Tmp1 = LegalizeOp(Node->getOperand(0));
3198 Tmp1 = PromoteOp(Node->getOperand(0));
3201 assert(0 && "not implemented");
3203 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3205 Tmp2 = LegalizeOp(Node->getOperand(1));
3208 Tmp2 = PromoteOp(Node->getOperand(1));
3211 assert(0 && "not implemented");
3213 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3215 // Perform FP_ROUND: this is probably overly pessimistic.
3216 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3217 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3218 DAG.getValueType(VT));
3223 // These operators require that their input be zero extended.
3224 Tmp1 = PromoteOp(Node->getOperand(0));
3225 Tmp2 = PromoteOp(Node->getOperand(1));
3226 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3227 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3228 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3229 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3233 Tmp1 = PromoteOp(Node->getOperand(0));
3234 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3237 // The input value must be properly sign extended.
3238 Tmp1 = PromoteOp(Node->getOperand(0));
3239 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3240 DAG.getValueType(VT));
3241 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3244 // The input value must be properly zero extended.
3245 Tmp1 = PromoteOp(Node->getOperand(0));
3246 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3247 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3251 Tmp1 = Node->getOperand(0); // Get the chain.
3252 Tmp2 = Node->getOperand(1); // Get the pointer.
3253 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3254 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3255 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3257 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3258 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3259 SV->getValue(), SV->getOffset());
3260 // Increment the pointer, VAList, to the next vaarg
3261 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3262 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3263 TLI.getPointerTy()));
3264 // Store the incremented VAList to the legalized pointer
3265 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3267 // Load the actual argument out of the pointer VAList
3268 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3270 // Remember that we legalized the chain.
3271 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3275 LoadSDNode *LD = cast<LoadSDNode>(Node);
3276 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3277 ? ISD::EXTLOAD : LD->getExtensionType();
3278 Result = DAG.getExtLoad(ExtType, NVT,
3279 LD->getChain(), LD->getBasePtr(),
3280 LD->getSrcValue(), LD->getSrcValueOffset(),
3282 // Remember that we legalized the chain.
3283 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3287 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3288 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3289 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3291 case ISD::SELECT_CC:
3292 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3293 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3294 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3295 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3298 Tmp1 = Node->getOperand(0);
3299 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3300 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3301 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3302 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3303 TLI.getShiftAmountTy()));
3308 // Zero extend the argument
3309 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3310 // Perform the larger operation, then subtract if needed.
3311 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3312 switch(Node->getOpcode()) {
3317 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3318 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3319 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3320 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3321 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3324 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3325 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3326 DAG.getConstant(getSizeInBits(NVT) -
3327 getSizeInBits(VT), NVT));
3331 case ISD::VEXTRACT_VECTOR_ELT:
3332 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3334 case ISD::EXTRACT_VECTOR_ELT:
3335 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3339 assert(Result.Val && "Didn't set a result!");
3341 // Make sure the result is itself legal.
3342 Result = LegalizeOp(Result);
3344 // Remember that we promoted this!
3345 AddPromotedOperand(Op, Result);
3349 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3350 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3351 /// on the vector type. The return type of this matches the element type of the
3352 /// vector, which may not be legal for the target.
3353 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3354 // We know that operand #0 is the Vec vector. If the index is a constant
3355 // or if the invec is a supported hardware type, we can use it. Otherwise,
3356 // lower to a store then an indexed load.
3357 SDOperand Vec = Op.getOperand(0);
3358 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3360 SDNode *InVal = Vec.Val;
3361 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3362 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3364 // Figure out if there is a Packed type corresponding to this Vector
3365 // type. If so, convert to the packed type.
3366 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3367 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3368 // Turn this into a packed extract_vector_elt operation.
3369 Vec = PackVectorOp(Vec, TVT);
3370 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3371 } else if (NumElems == 1) {
3372 // This must be an access of the only element. Return it.
3373 return PackVectorOp(Vec, EVT);
3374 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3376 SplitVectorOp(Vec, Lo, Hi);
3377 if (CIdx->getValue() < NumElems/2) {
3381 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3384 // It's now an extract from the appropriate high or low part. Recurse.
3385 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3386 return LowerVEXTRACT_VECTOR_ELT(Op);
3388 // Variable index case for extract element.
3389 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3390 assert(0 && "unimp!");
3395 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3397 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3398 SDOperand Vector = Op.getOperand(0);
3399 SDOperand Idx = Op.getOperand(1);
3401 // If the target doesn't support this, store the value to a temporary
3402 // stack slot, then LOAD the scalar element back out.
3403 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3404 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vector, StackPtr, NULL, 0);
3406 // Add the offset to the index.
3407 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3408 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3409 DAG.getConstant(EltSize, Idx.getValueType()));
3410 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3412 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3416 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3417 /// with condition CC on the current target. This usually involves legalizing
3418 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3419 /// there may be no choice but to create a new SetCC node to represent the
3420 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3421 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3422 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3425 SDOperand Tmp1, Tmp2, Result;
3427 switch (getTypeAction(LHS.getValueType())) {
3429 Tmp1 = LegalizeOp(LHS); // LHS
3430 Tmp2 = LegalizeOp(RHS); // RHS
3433 Tmp1 = PromoteOp(LHS); // LHS
3434 Tmp2 = PromoteOp(RHS); // RHS
3436 // If this is an FP compare, the operands have already been extended.
3437 if (MVT::isInteger(LHS.getValueType())) {
3438 MVT::ValueType VT = LHS.getValueType();
3439 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3441 // Otherwise, we have to insert explicit sign or zero extends. Note
3442 // that we could insert sign extends for ALL conditions, but zero extend
3443 // is cheaper on many machines (an AND instead of two shifts), so prefer
3445 switch (cast<CondCodeSDNode>(CC)->get()) {
3446 default: assert(0 && "Unknown integer comparison!");
3453 // ALL of these operations will work if we either sign or zero extend
3454 // the operands (including the unsigned comparisons!). Zero extend is
3455 // usually a simpler/cheaper operation, so prefer it.
3456 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3457 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3463 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3464 DAG.getValueType(VT));
3465 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3466 DAG.getValueType(VT));
3472 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3473 ExpandOp(LHS, LHSLo, LHSHi);
3474 ExpandOp(RHS, RHSLo, RHSHi);
3475 switch (cast<CondCodeSDNode>(CC)->get()) {
3479 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3480 if (RHSCST->isAllOnesValue()) {
3481 // Comparison to -1.
3482 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3487 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3488 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3489 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3490 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3493 // If this is a comparison of the sign bit, just look at the top part.
3495 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3496 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3497 CST->getValue() == 0) || // X < 0
3498 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3499 CST->isAllOnesValue())) { // X > -1
3505 // FIXME: This generated code sucks.
3506 ISD::CondCode LowCC;
3507 switch (cast<CondCodeSDNode>(CC)->get()) {
3508 default: assert(0 && "Unknown integer setcc!");
3510 case ISD::SETULT: LowCC = ISD::SETULT; break;
3512 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3514 case ISD::SETULE: LowCC = ISD::SETULE; break;
3516 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3519 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3520 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3521 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3523 // NOTE: on targets without efficient SELECT of bools, we can always use
3524 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3525 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3526 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3527 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3528 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3529 Result, Tmp1, Tmp2));
3538 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3539 /// The resultant code need not be legal. Note that SrcOp is the input operand
3540 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3541 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3543 // Create the stack frame object.
3544 SDOperand FIPtr = CreateStackTemporary(DestVT);
3546 // Emit a store to the stack slot.
3547 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3548 // Result is a load from the stack slot.
3549 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3552 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3553 // Create a vector sized/aligned stack slot, store the value to element #0,
3554 // then load the whole vector back out.
3555 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3556 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3558 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3562 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3563 /// support the operation, but do support the resultant packed vector type.
3564 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3566 // If the only non-undef value is the low element, turn this into a
3567 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3568 unsigned NumElems = Node->getNumOperands();
3569 bool isOnlyLowElement = true;
3570 SDOperand SplatValue = Node->getOperand(0);
3571 std::map<SDOperand, std::vector<unsigned> > Values;
3572 Values[SplatValue].push_back(0);
3573 bool isConstant = true;
3574 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3575 SplatValue.getOpcode() != ISD::UNDEF)
3578 for (unsigned i = 1; i < NumElems; ++i) {
3579 SDOperand V = Node->getOperand(i);
3580 Values[V].push_back(i);
3581 if (V.getOpcode() != ISD::UNDEF)
3582 isOnlyLowElement = false;
3583 if (SplatValue != V)
3584 SplatValue = SDOperand(0,0);
3586 // If this isn't a constant element or an undef, we can't use a constant
3588 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3589 V.getOpcode() != ISD::UNDEF)
3593 if (isOnlyLowElement) {
3594 // If the low element is an undef too, then this whole things is an undef.
3595 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3596 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3597 // Otherwise, turn this into a scalar_to_vector node.
3598 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3599 Node->getOperand(0));
3602 // If all elements are constants, create a load from the constant pool.
3604 MVT::ValueType VT = Node->getValueType(0);
3606 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3607 std::vector<Constant*> CV;
3608 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3609 if (ConstantFPSDNode *V =
3610 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3611 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3612 } else if (ConstantSDNode *V =
3613 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3614 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3616 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3617 CV.push_back(UndefValue::get(OpNTy));
3620 Constant *CP = ConstantPacked::get(CV);
3621 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3622 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
3625 if (SplatValue.Val) { // Splat of one value?
3626 // Build the shuffle constant vector: <0, 0, 0, 0>
3627 MVT::ValueType MaskVT =
3628 MVT::getIntVectorWithNumElements(NumElems);
3629 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3630 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3631 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3632 &ZeroVec[0], ZeroVec.size());
3634 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3635 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3636 // Get the splatted value into the low element of a vector register.
3637 SDOperand LowValVec =
3638 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3640 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3641 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3642 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3647 // If there are only two unique elements, we may be able to turn this into a
3649 if (Values.size() == 2) {
3650 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3651 MVT::ValueType MaskVT =
3652 MVT::getIntVectorWithNumElements(NumElems);
3653 std::vector<SDOperand> MaskVec(NumElems);
3655 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3656 E = Values.end(); I != E; ++I) {
3657 for (std::vector<unsigned>::iterator II = I->second.begin(),
3658 EE = I->second.end(); II != EE; ++II)
3659 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3662 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
3663 &MaskVec[0], MaskVec.size());
3665 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3666 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3667 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3668 SmallVector<SDOperand, 8> Ops;
3669 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3670 E = Values.end(); I != E; ++I) {
3671 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3675 Ops.push_back(ShuffleMask);
3677 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3678 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
3679 &Ops[0], Ops.size());
3683 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3684 // aligned object on the stack, store each element into it, then load
3685 // the result as a vector.
3686 MVT::ValueType VT = Node->getValueType(0);
3687 // Create the stack frame object.
3688 SDOperand FIPtr = CreateStackTemporary(VT);
3690 // Emit a store of each element to the stack slot.
3691 SmallVector<SDOperand, 8> Stores;
3692 unsigned TypeByteSize =
3693 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3694 // Store (in the right endianness) the elements to memory.
3695 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3696 // Ignore undef elements.
3697 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3699 unsigned Offset = TypeByteSize*i;
3701 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3702 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3704 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
3708 SDOperand StoreChain;
3709 if (!Stores.empty()) // Not all undef elements?
3710 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
3711 &Stores[0], Stores.size());
3713 StoreChain = DAG.getEntryNode();
3715 // Result is a load from the stack slot.
3716 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
3719 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3720 /// specified value type.
3721 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3722 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3723 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3724 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3725 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3728 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3729 SDOperand Op, SDOperand Amt,
3730 SDOperand &Lo, SDOperand &Hi) {
3731 // Expand the subcomponents.
3732 SDOperand LHSL, LHSH;
3733 ExpandOp(Op, LHSL, LHSH);
3735 SDOperand Ops[] = { LHSL, LHSH, Amt };
3736 MVT::ValueType VT = LHSL.getValueType();
3737 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
3738 Hi = Lo.getValue(1);
3742 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3743 /// smaller elements. If we can't find a way that is more efficient than a
3744 /// libcall on this target, return false. Otherwise, return true with the
3745 /// low-parts expanded into Lo and Hi.
3746 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3747 SDOperand &Lo, SDOperand &Hi) {
3748 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3749 "This is not a shift!");
3751 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3752 SDOperand ShAmt = LegalizeOp(Amt);
3753 MVT::ValueType ShTy = ShAmt.getValueType();
3754 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3755 unsigned NVTBits = MVT::getSizeInBits(NVT);
3757 // Handle the case when Amt is an immediate. Other cases are currently broken
3758 // and are disabled.
3759 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3760 unsigned Cst = CN->getValue();
3761 // Expand the incoming operand to be shifted, so that we have its parts
3763 ExpandOp(Op, InL, InH);
3767 Lo = DAG.getConstant(0, NVT);
3768 Hi = DAG.getConstant(0, NVT);
3769 } else if (Cst > NVTBits) {
3770 Lo = DAG.getConstant(0, NVT);
3771 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3772 } else if (Cst == NVTBits) {
3773 Lo = DAG.getConstant(0, NVT);
3776 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3777 Hi = DAG.getNode(ISD::OR, NVT,
3778 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3779 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3784 Lo = DAG.getConstant(0, NVT);
3785 Hi = DAG.getConstant(0, NVT);
3786 } else if (Cst > NVTBits) {
3787 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3788 Hi = DAG.getConstant(0, NVT);
3789 } else if (Cst == NVTBits) {
3791 Hi = DAG.getConstant(0, NVT);
3793 Lo = DAG.getNode(ISD::OR, NVT,
3794 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3795 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3796 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3801 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3802 DAG.getConstant(NVTBits-1, ShTy));
3803 } else if (Cst > NVTBits) {
3804 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3805 DAG.getConstant(Cst-NVTBits, ShTy));
3806 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3807 DAG.getConstant(NVTBits-1, ShTy));
3808 } else if (Cst == NVTBits) {
3810 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3811 DAG.getConstant(NVTBits-1, ShTy));
3813 Lo = DAG.getNode(ISD::OR, NVT,
3814 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3815 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3816 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3822 // Okay, the shift amount isn't constant. However, if we can tell that it is
3823 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
3824 uint64_t Mask = NVTBits, KnownZero, KnownOne;
3825 TLI.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
3827 // If we know that the high bit of the shift amount is one, then we can do
3828 // this as a couple of simple shifts.
3829 if (KnownOne & Mask) {
3830 // Mask out the high bit, which we know is set.
3831 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
3832 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3834 // Expand the incoming operand to be shifted, so that we have its parts
3836 ExpandOp(Op, InL, InH);
3839 Lo = DAG.getConstant(0, NVT); // Low part is zero.
3840 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
3843 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
3844 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
3847 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
3848 DAG.getConstant(NVTBits-1, Amt.getValueType()));
3849 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
3854 // If we know that the high bit of the shift amount is zero, then we can do
3855 // this as a couple of simple shifts.
3856 if (KnownZero & Mask) {
3858 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
3859 DAG.getConstant(NVTBits, Amt.getValueType()),
3862 // Expand the incoming operand to be shifted, so that we have its parts
3864 ExpandOp(Op, InL, InH);
3867 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
3868 Hi = DAG.getNode(ISD::OR, NVT,
3869 DAG.getNode(ISD::SHL, NVT, InH, Amt),
3870 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
3873 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
3874 Lo = DAG.getNode(ISD::OR, NVT,
3875 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3876 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3879 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
3880 Lo = DAG.getNode(ISD::OR, NVT,
3881 DAG.getNode(ISD::SRL, NVT, InL, Amt),
3882 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
3891 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3892 // does not fit into a register, return the lo part and set the hi part to the
3893 // by-reg argument. If it does fit into a single register, return the result
3894 // and leave the Hi part unset.
3895 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3897 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3898 // The input chain to this libcall is the entry node of the function.
3899 // Legalizing the call will automatically add the previous call to the
3901 SDOperand InChain = DAG.getEntryNode();
3903 TargetLowering::ArgListTy Args;
3904 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3905 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3906 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3907 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3909 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3911 // Splice the libcall in wherever FindInputOutputChains tells us to.
3912 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3913 std::pair<SDOperand,SDOperand> CallInfo =
3914 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3917 // Legalize the call sequence, starting with the chain. This will advance
3918 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3919 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3920 LegalizeOp(CallInfo.second);
3922 switch (getTypeAction(CallInfo.first.getValueType())) {
3923 default: assert(0 && "Unknown thing");
3925 Result = CallInfo.first;
3928 ExpandOp(CallInfo.first, Result, Hi);
3935 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3936 /// destination type is legal.
3937 SDOperand SelectionDAGLegalize::
3938 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3939 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3940 assert(getTypeAction(Source.getValueType()) == Expand &&
3941 "This is not an expansion!");
3942 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3945 assert(Source.getValueType() == MVT::i64 &&
3946 "This only works for 64-bit -> FP");
3947 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3948 // incoming integer is set. To handle this, we dynamically test to see if
3949 // it is set, and, if so, add a fudge factor.
3951 ExpandOp(Source, Lo, Hi);
3953 // If this is unsigned, and not supported, first perform the conversion to
3954 // signed, then adjust the result if the sign bit is set.
3955 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3956 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3958 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3959 DAG.getConstant(0, Hi.getValueType()),
3961 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3962 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3963 SignSet, Four, Zero);
3964 uint64_t FF = 0x5f800000ULL;
3965 if (TLI.isLittleEndian()) FF <<= 32;
3966 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
3968 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3969 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3970 SDOperand FudgeInReg;
3971 if (DestTy == MVT::f32)
3972 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
3974 assert(DestTy == MVT::f64 && "Unexpected conversion");
3975 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3976 CPIdx, NULL, 0, MVT::f32);
3978 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3981 // Check to see if the target has a custom way to lower this. If so, use it.
3982 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3983 default: assert(0 && "This action not implemented for this operation!");
3984 case TargetLowering::Legal:
3985 case TargetLowering::Expand:
3986 break; // This case is handled below.
3987 case TargetLowering::Custom: {
3988 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3991 return LegalizeOp(NV);
3992 break; // The target decided this was legal after all
3996 // Expand the source, then glue it back together for the call. We must expand
3997 // the source in case it is shared (this pass of legalize must traverse it).
3998 SDOperand SrcLo, SrcHi;
3999 ExpandOp(Source, SrcLo, SrcHi);
4000 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4002 const char *FnName = 0;
4003 if (DestTy == MVT::f32)
4004 FnName = "__floatdisf";
4006 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4007 FnName = "__floatdidf";
4010 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4011 SDOperand UnusedHiPart;
4012 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
4015 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4016 /// INT_TO_FP operation of the specified operand when the target requests that
4017 /// we expand it. At this point, we know that the result and operand types are
4018 /// legal for the target.
4019 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4021 MVT::ValueType DestVT) {
4022 if (Op0.getValueType() == MVT::i32) {
4023 // simple 32-bit [signed|unsigned] integer to float/double expansion
4025 // get the stack frame index of a 8 byte buffer
4026 MachineFunction &MF = DAG.getMachineFunction();
4027 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
4028 // get address of 8 byte buffer
4029 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4030 // word offset constant for Hi/Lo address computation
4031 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4032 // set up Hi and Lo (into buffer) address based on endian
4033 SDOperand Hi = StackSlot;
4034 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4035 if (TLI.isLittleEndian())
4038 // if signed map to unsigned space
4039 SDOperand Op0Mapped;
4041 // constant used to invert sign bit (signed to unsigned mapping)
4042 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4043 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4047 // store the lo of the constructed double - based on integer input
4048 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4049 Op0Mapped, Lo, NULL, 0);
4050 // initial hi portion of constructed double
4051 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4052 // store the hi of the constructed double - biased exponent
4053 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4054 // load the constructed double
4055 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4056 // FP constant to bias correct the final result
4057 SDOperand Bias = DAG.getConstantFP(isSigned ?
4058 BitsToDouble(0x4330000080000000ULL)
4059 : BitsToDouble(0x4330000000000000ULL),
4061 // subtract the bias
4062 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4065 // handle final rounding
4066 if (DestVT == MVT::f64) {
4070 // if f32 then cast to f32
4071 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4075 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4076 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4078 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4079 DAG.getConstant(0, Op0.getValueType()),
4081 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4082 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4083 SignSet, Four, Zero);
4085 // If the sign bit of the integer is set, the large number will be treated
4086 // as a negative number. To counteract this, the dynamic code adds an
4087 // offset depending on the data type.
4089 switch (Op0.getValueType()) {
4090 default: assert(0 && "Unsupported integer type!");
4091 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4092 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4093 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4094 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4096 if (TLI.isLittleEndian()) FF <<= 32;
4097 static Constant *FudgeFactor = ConstantInt::get(Type::ULongTy, FF);
4099 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4100 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4101 SDOperand FudgeInReg;
4102 if (DestVT == MVT::f32)
4103 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4105 assert(DestVT == MVT::f64 && "Unexpected conversion");
4106 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4107 DAG.getEntryNode(), CPIdx,
4108 NULL, 0, MVT::f32));
4111 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4114 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4115 /// *INT_TO_FP operation of the specified operand when the target requests that
4116 /// we promote it. At this point, we know that the result and operand types are
4117 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4118 /// operation that takes a larger input.
4119 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4120 MVT::ValueType DestVT,
4122 // First step, figure out the appropriate *INT_TO_FP operation to use.
4123 MVT::ValueType NewInTy = LegalOp.getValueType();
4125 unsigned OpToUse = 0;
4127 // Scan for the appropriate larger type to use.
4129 NewInTy = (MVT::ValueType)(NewInTy+1);
4130 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4132 // If the target supports SINT_TO_FP of this type, use it.
4133 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4135 case TargetLowering::Legal:
4136 if (!TLI.isTypeLegal(NewInTy))
4137 break; // Can't use this datatype.
4139 case TargetLowering::Custom:
4140 OpToUse = ISD::SINT_TO_FP;
4144 if (isSigned) continue;
4146 // If the target supports UINT_TO_FP of this type, use it.
4147 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4149 case TargetLowering::Legal:
4150 if (!TLI.isTypeLegal(NewInTy))
4151 break; // Can't use this datatype.
4153 case TargetLowering::Custom:
4154 OpToUse = ISD::UINT_TO_FP;
4159 // Otherwise, try a larger type.
4162 // Okay, we found the operation and type to use. Zero extend our input to the
4163 // desired type then run the operation on it.
4164 return DAG.getNode(OpToUse, DestVT,
4165 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4169 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4170 /// FP_TO_*INT operation of the specified operand when the target requests that
4171 /// we promote it. At this point, we know that the result and operand types are
4172 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4173 /// operation that returns a larger result.
4174 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4175 MVT::ValueType DestVT,
4177 // First step, figure out the appropriate FP_TO*INT operation to use.
4178 MVT::ValueType NewOutTy = DestVT;
4180 unsigned OpToUse = 0;
4182 // Scan for the appropriate larger type to use.
4184 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4185 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4187 // If the target supports FP_TO_SINT returning this type, use it.
4188 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4190 case TargetLowering::Legal:
4191 if (!TLI.isTypeLegal(NewOutTy))
4192 break; // Can't use this datatype.
4194 case TargetLowering::Custom:
4195 OpToUse = ISD::FP_TO_SINT;
4200 // If the target supports FP_TO_UINT of this type, use it.
4201 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4203 case TargetLowering::Legal:
4204 if (!TLI.isTypeLegal(NewOutTy))
4205 break; // Can't use this datatype.
4207 case TargetLowering::Custom:
4208 OpToUse = ISD::FP_TO_UINT;
4213 // Otherwise, try a larger type.
4216 // Okay, we found the operation and type to use. Truncate the result of the
4217 // extended FP_TO_*INT operation to the desired size.
4218 return DAG.getNode(ISD::TRUNCATE, DestVT,
4219 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4222 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4224 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4225 MVT::ValueType VT = Op.getValueType();
4226 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4227 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4229 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4231 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4232 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4233 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4235 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4236 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4237 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4238 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4239 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4240 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4241 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4242 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4243 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4245 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4246 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4247 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4248 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4249 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4250 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4251 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4252 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4253 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4254 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4255 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4256 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4257 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4258 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4259 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4260 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4261 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4262 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4263 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4264 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4265 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4269 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4271 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4273 default: assert(0 && "Cannot expand this yet!");
4275 static const uint64_t mask[6] = {
4276 0x5555555555555555ULL, 0x3333333333333333ULL,
4277 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4278 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4280 MVT::ValueType VT = Op.getValueType();
4281 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4282 unsigned len = getSizeInBits(VT);
4283 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4284 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4285 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4286 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4287 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4288 DAG.getNode(ISD::AND, VT,
4289 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4294 // for now, we do this:
4295 // x = x | (x >> 1);
4296 // x = x | (x >> 2);
4298 // x = x | (x >>16);
4299 // x = x | (x >>32); // for 64-bit input
4300 // return popcount(~x);
4302 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4303 MVT::ValueType VT = Op.getValueType();
4304 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4305 unsigned len = getSizeInBits(VT);
4306 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4307 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4308 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4310 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4311 return DAG.getNode(ISD::CTPOP, VT, Op);
4314 // for now, we use: { return popcount(~x & (x - 1)); }
4315 // unless the target has ctlz but not ctpop, in which case we use:
4316 // { return 32 - nlz(~x & (x-1)); }
4317 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4318 MVT::ValueType VT = Op.getValueType();
4319 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4320 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4321 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4322 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4323 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4324 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4325 TLI.isOperationLegal(ISD::CTLZ, VT))
4326 return DAG.getNode(ISD::SUB, VT,
4327 DAG.getConstant(getSizeInBits(VT), VT),
4328 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4329 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4334 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4335 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4336 /// LegalizeNodes map is filled in for any results that are not expanded, the
4337 /// ExpandedNodes map is filled in for any results that are expanded, and the
4338 /// Lo/Hi values are returned.
4339 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4340 MVT::ValueType VT = Op.getValueType();
4341 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4342 SDNode *Node = Op.Val;
4343 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4344 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4345 VT == MVT::Vector) &&
4346 "Cannot expand to FP value or to larger int value!");
4348 // See if we already expanded it.
4349 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4350 = ExpandedNodes.find(Op);
4351 if (I != ExpandedNodes.end()) {
4352 Lo = I->second.first;
4353 Hi = I->second.second;
4357 switch (Node->getOpcode()) {
4358 case ISD::CopyFromReg:
4359 assert(0 && "CopyFromReg must be legal!");
4362 cerr << "NODE: "; Node->dump(); cerr << "\n";
4364 assert(0 && "Do not know how to expand this operator!");
4367 Lo = DAG.getNode(ISD::UNDEF, NVT);
4368 Hi = DAG.getNode(ISD::UNDEF, NVT);
4370 case ISD::Constant: {
4371 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4372 Lo = DAG.getConstant(Cst, NVT);
4373 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4376 case ISD::BUILD_PAIR:
4377 // Return the operands.
4378 Lo = Node->getOperand(0);
4379 Hi = Node->getOperand(1);
4382 case ISD::SIGN_EXTEND_INREG:
4383 ExpandOp(Node->getOperand(0), Lo, Hi);
4384 // sext_inreg the low part if needed.
4385 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4387 // The high part gets the sign extension from the lo-part. This handles
4388 // things like sextinreg V:i64 from i8.
4389 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4390 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4391 TLI.getShiftAmountTy()));
4395 ExpandOp(Node->getOperand(0), Lo, Hi);
4396 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4397 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4403 ExpandOp(Node->getOperand(0), Lo, Hi);
4404 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4405 DAG.getNode(ISD::CTPOP, NVT, Lo),
4406 DAG.getNode(ISD::CTPOP, NVT, Hi));
4407 Hi = DAG.getConstant(0, NVT);
4411 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4412 ExpandOp(Node->getOperand(0), Lo, Hi);
4413 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4414 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4415 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4417 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4418 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4420 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4421 Hi = DAG.getConstant(0, NVT);
4426 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4427 ExpandOp(Node->getOperand(0), Lo, Hi);
4428 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4429 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4430 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4432 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4433 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4435 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4436 Hi = DAG.getConstant(0, NVT);
4441 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4442 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4443 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4444 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4446 // Remember that we legalized the chain.
4447 Hi = LegalizeOp(Hi);
4448 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4449 if (!TLI.isLittleEndian())
4455 LoadSDNode *LD = cast<LoadSDNode>(Node);
4456 SDOperand Ch = LD->getChain(); // Legalize the chain.
4457 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4458 ISD::LoadExtType ExtType = LD->getExtensionType();
4460 if (ExtType == ISD::NON_EXTLOAD) {
4461 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4463 // Increment the pointer to the other half.
4464 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4465 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4466 getIntPtrConstant(IncrementSize));
4467 // FIXME: This creates a bogus srcvalue!
4468 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), LD->getSrcValueOffset());
4470 // Build a factor node to remember that this load is independent of the
4472 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4475 // Remember that we legalized the chain.
4476 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4477 if (!TLI.isLittleEndian())
4480 MVT::ValueType EVT = LD->getLoadedVT();
4483 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4484 LD->getSrcValueOffset());
4486 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4487 LD->getSrcValueOffset(), EVT);
4489 // Remember that we legalized the chain.
4490 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4492 if (ExtType == ISD::SEXTLOAD) {
4493 // The high part is obtained by SRA'ing all but one of the bits of the
4495 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4496 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4497 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4498 } else if (ExtType == ISD::ZEXTLOAD) {
4499 // The high part is just a zero.
4500 Hi = DAG.getConstant(0, NVT);
4501 } else /* if (ExtType == ISD::EXTLOAD) */ {
4502 // The high part is undefined.
4503 Hi = DAG.getNode(ISD::UNDEF, NVT);
4510 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4511 SDOperand LL, LH, RL, RH;
4512 ExpandOp(Node->getOperand(0), LL, LH);
4513 ExpandOp(Node->getOperand(1), RL, RH);
4514 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4515 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4519 SDOperand LL, LH, RL, RH;
4520 ExpandOp(Node->getOperand(1), LL, LH);
4521 ExpandOp(Node->getOperand(2), RL, RH);
4522 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4523 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4526 case ISD::SELECT_CC: {
4527 SDOperand TL, TH, FL, FH;
4528 ExpandOp(Node->getOperand(2), TL, TH);
4529 ExpandOp(Node->getOperand(3), FL, FH);
4530 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4531 Node->getOperand(1), TL, FL, Node->getOperand(4));
4532 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4533 Node->getOperand(1), TH, FH, Node->getOperand(4));
4536 case ISD::ANY_EXTEND:
4537 // The low part is any extension of the input (which degenerates to a copy).
4538 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4539 // The high part is undefined.
4540 Hi = DAG.getNode(ISD::UNDEF, NVT);
4542 case ISD::SIGN_EXTEND: {
4543 // The low part is just a sign extension of the input (which degenerates to
4545 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4547 // The high part is obtained by SRA'ing all but one of the bits of the lo
4549 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4550 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4551 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4554 case ISD::ZERO_EXTEND:
4555 // The low part is just a zero extension of the input (which degenerates to
4557 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4559 // The high part is just a zero.
4560 Hi = DAG.getConstant(0, NVT);
4563 case ISD::BIT_CONVERT: {
4565 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
4566 // If the target wants to, allow it to lower this itself.
4567 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4568 case Expand: assert(0 && "cannot expand FP!");
4569 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
4570 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
4572 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
4575 // f32 / f64 must be expanded to i32 / i64.
4576 if (VT == MVT::f32 || VT == MVT::f64) {
4577 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
4582 // Turn this into a load/store pair by default.
4584 Tmp = ExpandBIT_CONVERT(NVT, Node->getOperand(0));
4586 ExpandOp(Tmp, Lo, Hi);
4590 case ISD::READCYCLECOUNTER:
4591 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4592 TargetLowering::Custom &&
4593 "Must custom expand ReadCycleCounter");
4594 Lo = TLI.LowerOperation(Op, DAG);
4595 assert(Lo.Val && "Node must be custom expanded!");
4596 Hi = Lo.getValue(1);
4597 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4598 LegalizeOp(Lo.getValue(2)));
4601 // These operators cannot be expanded directly, emit them as calls to
4602 // library functions.
4603 case ISD::FP_TO_SINT:
4604 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4606 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4607 case Expand: assert(0 && "cannot expand FP!");
4608 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4609 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4612 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4614 // Now that the custom expander is done, expand the result, which is still
4617 ExpandOp(Op, Lo, Hi);
4622 if (Node->getOperand(0).getValueType() == MVT::f32)
4623 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4625 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4628 case ISD::FP_TO_UINT:
4629 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4631 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4632 case Expand: assert(0 && "cannot expand FP!");
4633 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4634 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4637 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4639 // Now that the custom expander is done, expand the result.
4641 ExpandOp(Op, Lo, Hi);
4646 if (Node->getOperand(0).getValueType() == MVT::f32)
4647 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4649 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4653 // If the target wants custom lowering, do so.
4654 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4655 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4656 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4657 Op = TLI.LowerOperation(Op, DAG);
4659 // Now that the custom expander is done, expand the result, which is
4661 ExpandOp(Op, Lo, Hi);
4666 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
4667 // this X << 1 as X+X.
4668 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
4669 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
4670 TLI.isOperationLegal(ISD::ADDE, NVT)) {
4671 SDOperand LoOps[2], HiOps[3];
4672 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
4673 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
4674 LoOps[1] = LoOps[0];
4675 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4677 HiOps[1] = HiOps[0];
4678 HiOps[2] = Lo.getValue(1);
4679 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4684 // If we can emit an efficient shift operation, do so now.
4685 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4688 // If this target supports SHL_PARTS, use it.
4689 TargetLowering::LegalizeAction Action =
4690 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4691 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4692 Action == TargetLowering::Custom) {
4693 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4697 // Otherwise, emit a libcall.
4698 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4703 // If the target wants custom lowering, do so.
4704 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4705 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4706 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4707 Op = TLI.LowerOperation(Op, DAG);
4709 // Now that the custom expander is done, expand the result, which is
4711 ExpandOp(Op, Lo, Hi);
4716 // If we can emit an efficient shift operation, do so now.
4717 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4720 // If this target supports SRA_PARTS, use it.
4721 TargetLowering::LegalizeAction Action =
4722 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4723 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4724 Action == TargetLowering::Custom) {
4725 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4729 // Otherwise, emit a libcall.
4730 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4735 // If the target wants custom lowering, do so.
4736 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4737 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4738 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4739 Op = TLI.LowerOperation(Op, DAG);
4741 // Now that the custom expander is done, expand the result, which is
4743 ExpandOp(Op, Lo, Hi);
4748 // If we can emit an efficient shift operation, do so now.
4749 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4752 // If this target supports SRL_PARTS, use it.
4753 TargetLowering::LegalizeAction Action =
4754 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4755 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4756 Action == TargetLowering::Custom) {
4757 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4761 // Otherwise, emit a libcall.
4762 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4768 // If the target wants to custom expand this, let them.
4769 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4770 TargetLowering::Custom) {
4771 Op = TLI.LowerOperation(Op, DAG);
4773 ExpandOp(Op, Lo, Hi);
4778 // Expand the subcomponents.
4779 SDOperand LHSL, LHSH, RHSL, RHSH;
4780 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4781 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4782 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
4783 SDOperand LoOps[2], HiOps[3];
4788 if (Node->getOpcode() == ISD::ADD) {
4789 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
4790 HiOps[2] = Lo.getValue(1);
4791 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
4793 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
4794 HiOps[2] = Lo.getValue(1);
4795 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
4800 // If the target wants to custom expand this, let them.
4801 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
4802 SDOperand New = TLI.LowerOperation(Op, DAG);
4804 ExpandOp(New, Lo, Hi);
4809 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
4810 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
4811 if (HasMULHS || HasMULHU) {
4812 SDOperand LL, LH, RL, RH;
4813 ExpandOp(Node->getOperand(0), LL, LH);
4814 ExpandOp(Node->getOperand(1), RL, RH);
4815 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4816 // FIXME: Move this to the dag combiner.
4817 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4818 // extended the sign bit of the low half through the upper half, and if so
4819 // emit a MULHS instead of the alternate sequence that is valid for any
4820 // i64 x i64 multiply.
4822 // is RH an extension of the sign bit of RL?
4823 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4824 RH.getOperand(1).getOpcode() == ISD::Constant &&
4825 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4826 // is LH an extension of the sign bit of LL?
4827 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4828 LH.getOperand(1).getOpcode() == ISD::Constant &&
4829 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4831 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4833 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4835 } else if (HasMULHU) {
4837 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4840 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4841 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4842 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4843 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4844 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4849 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4852 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4853 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4854 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4855 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4858 Lo = ExpandLibCall(((VT == MVT::f32) ? "__addsf3" : "__adddf3"), Node, Hi);
4861 Lo = ExpandLibCall(((VT == MVT::f32) ? "__subsf3" : "__subdf3"), Node, Hi);
4864 Lo = ExpandLibCall(((VT == MVT::f32) ? "__mulsf3" : "__muldf3"), Node, Hi);
4867 Lo = ExpandLibCall(((VT == MVT::f32) ? "__divsf3" : "__divdf3"), Node, Hi);
4869 case ISD::FP_EXTEND:
4870 Lo = ExpandLibCall("__extendsfdf2", Node, Hi);
4873 Lo = ExpandLibCall("__truncdfsf2", Node, Hi);
4877 // Make sure the resultant values have been legalized themselves, unless this
4878 // is a type that requires multi-step expansion.
4879 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4880 Lo = LegalizeOp(Lo);
4882 // Don't legalize the high part if it is expanded to a single node.
4883 Hi = LegalizeOp(Hi);
4886 // Remember in a map if the values will be reused later.
4888 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4889 assert(isNew && "Value already expanded?!?");
4892 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4893 /// two smaller values of MVT::Vector type.
4894 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4896 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4897 SDNode *Node = Op.Val;
4898 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4899 assert(NumElements > 1 && "Cannot split a single element vector!");
4900 unsigned NewNumElts = NumElements/2;
4901 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4902 SDOperand TypeNode = *(Node->op_end()-1);
4904 // See if we already split it.
4905 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4906 = SplitNodes.find(Op);
4907 if (I != SplitNodes.end()) {
4908 Lo = I->second.first;
4909 Hi = I->second.second;
4913 switch (Node->getOpcode()) {
4918 assert(0 && "Unhandled operation in SplitVectorOp!");
4919 case ISD::VBUILD_VECTOR: {
4920 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
4921 Node->op_begin()+NewNumElts);
4922 LoOps.push_back(NewNumEltsNode);
4923 LoOps.push_back(TypeNode);
4924 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &LoOps[0], LoOps.size());
4926 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
4928 HiOps.push_back(NewNumEltsNode);
4929 HiOps.push_back(TypeNode);
4930 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &HiOps[0], HiOps.size());
4941 SDOperand LL, LH, RL, RH;
4942 SplitVectorOp(Node->getOperand(0), LL, LH);
4943 SplitVectorOp(Node->getOperand(1), RL, RH);
4945 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4946 NewNumEltsNode, TypeNode);
4947 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4948 NewNumEltsNode, TypeNode);
4952 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4953 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4954 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4956 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4957 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4958 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4959 getIntPtrConstant(IncrementSize));
4960 // FIXME: This creates a bogus srcvalue!
4961 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4963 // Build a factor node to remember that this load is independent of the
4965 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4968 // Remember that we legalized the chain.
4969 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4972 case ISD::VBIT_CONVERT: {
4973 // We know the result is a vector. The input may be either a vector or a
4975 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4976 // Lower to a store/load. FIXME: this could be improved probably.
4977 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4979 SDOperand St = DAG.getStore(DAG.getEntryNode(),
4980 Op.getOperand(0), Ptr, NULL, 0);
4981 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4982 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4983 SplitVectorOp(St, Lo, Hi);
4985 // If the input is a vector type, we have to either scalarize it, pack it
4986 // or convert it based on whether the input vector type is legal.
4987 SDNode *InVal = Node->getOperand(0).Val;
4989 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4990 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4992 // If the input is from a single element vector, scalarize the vector,
4993 // then treat like a scalar.
4994 if (NumElems == 1) {
4995 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4996 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4997 Op.getOperand(1), Op.getOperand(2));
4998 SplitVectorOp(Scalar, Lo, Hi);
5000 // Split the input vector.
5001 SplitVectorOp(Op.getOperand(0), Lo, Hi);
5003 // Convert each of the pieces now.
5004 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
5005 NewNumEltsNode, TypeNode);
5006 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
5007 NewNumEltsNode, TypeNode);
5014 // Remember in a map if the values will be reused later.
5016 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5017 assert(isNew && "Value already expanded?!?");
5021 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
5022 /// equivalent operation that returns a scalar (e.g. F32) or packed value
5023 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
5024 /// type for the result.
5025 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
5026 MVT::ValueType NewVT) {
5027 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
5028 SDNode *Node = Op.Val;
5030 // See if we already packed it.
5031 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
5032 if (I != PackedNodes.end()) return I->second;
5035 switch (Node->getOpcode()) {
5038 Node->dump(); cerr << "\n";
5040 assert(0 && "Unknown vector operation in PackVectorOp!");
5049 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
5051 PackVectorOp(Node->getOperand(0), NewVT),
5052 PackVectorOp(Node->getOperand(1), NewVT));
5055 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
5056 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
5058 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
5059 Result = DAG.getLoad(NewVT, Ch, Ptr, SV->getValue(), SV->getOffset());
5061 // Remember that we legalized the chain.
5062 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5065 case ISD::VBUILD_VECTOR:
5066 if (Node->getOperand(0).getValueType() == NewVT) {
5067 // Returning a scalar?
5068 Result = Node->getOperand(0);
5070 // Returning a BUILD_VECTOR?
5072 // If all elements of the build_vector are undefs, return an undef.
5073 bool AllUndef = true;
5074 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
5075 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
5080 Result = DAG.getNode(ISD::UNDEF, NewVT);
5082 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Node->op_begin(),
5083 Node->getNumOperands()-2);
5087 case ISD::VINSERT_VECTOR_ELT:
5088 if (!MVT::isVector(NewVT)) {
5089 // Returning a scalar? Must be the inserted element.
5090 Result = Node->getOperand(1);
5092 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
5093 PackVectorOp(Node->getOperand(0), NewVT),
5094 Node->getOperand(1), Node->getOperand(2));
5097 case ISD::VVECTOR_SHUFFLE:
5098 if (!MVT::isVector(NewVT)) {
5099 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
5100 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5101 if (cast<ConstantSDNode>(EltNum)->getValue())
5102 Result = PackVectorOp(Node->getOperand(1), NewVT);
5104 Result = PackVectorOp(Node->getOperand(0), NewVT);
5106 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
5107 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
5108 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
5109 Node->getOperand(2).Val->op_end()-2);
5110 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
5111 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT,
5112 Node->getOperand(2).Val->op_begin(),
5113 Node->getOperand(2).Val->getNumOperands()-2);
5115 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
5116 PackVectorOp(Node->getOperand(0), NewVT),
5117 PackVectorOp(Node->getOperand(1), NewVT), BV);
5120 case ISD::VBIT_CONVERT:
5121 if (Op.getOperand(0).getValueType() != MVT::Vector)
5122 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5124 // If the input is a vector type, we have to either scalarize it, pack it
5125 // or convert it based on whether the input vector type is legal.
5126 SDNode *InVal = Node->getOperand(0).Val;
5128 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
5129 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
5131 // Figure out if there is a Packed type corresponding to this Vector
5132 // type. If so, convert to the packed type.
5133 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
5134 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
5135 // Turn this into a bit convert of the packed input.
5136 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5137 PackVectorOp(Node->getOperand(0), TVT));
5139 } else if (NumElems == 1) {
5140 // Turn this into a bit convert of the scalar input.
5141 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
5142 PackVectorOp(Node->getOperand(0), EVT));
5146 assert(0 && "Cast from unsupported vector type not implemented yet!");
5151 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5152 PackVectorOp(Op.getOperand(1), NewVT),
5153 PackVectorOp(Op.getOperand(2), NewVT));
5157 if (TLI.isTypeLegal(NewVT))
5158 Result = LegalizeOp(Result);
5159 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
5160 assert(isNew && "Value already packed?");
5165 // SelectionDAG::Legalize - This is the entry point for the file.
5167 void SelectionDAG::Legalize() {
5168 if (ViewLegalizeDAGs) viewGraph();
5170 /// run - This is the main entry point to this class.
5172 SelectionDAGLegalize(*this).LegalizeDAG();