1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
55 // Libcall insertion helpers.
57 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
58 /// legalized. We use this to ensure that calls are properly serialized
59 /// against each other, including inserted libcalls.
60 SDValue LastCALLSEQ_END;
62 /// IsLegalizingCall - This member is used *only* for purposes of providing
63 /// helpful assertions that a libcall isn't created while another call is
64 /// being legalized (which could lead to non-serialized call sequences).
65 bool IsLegalizingCall;
68 Legal, // The target natively supports this operation.
69 Promote, // This operation should be executed in a larger type.
70 Expand // Try to expand this to other ops, otherwise use a libcall.
73 /// ValueTypeActions - This is a bitvector that contains two bits for each
74 /// value type, where the two bits correspond to the LegalizeAction enum.
75 /// This can be queried with "getTypeAction(VT)".
76 TargetLowering::ValueTypeActionImpl ValueTypeActions;
78 /// LegalizedNodes - For nodes that are of legal width, and that have more
79 /// than one use, this map indicates what regularized operand to use. This
80 /// allows us to avoid legalizing the same thing more than once.
81 DenseMap<SDValue, SDValue> LegalizedNodes;
83 /// PromotedNodes - For nodes that are below legal width, and that have more
84 /// than one use, this map indicates what promoted value to use. This allows
85 /// us to avoid promoting the same thing more than once.
86 DenseMap<SDValue, SDValue> PromotedNodes;
88 /// ExpandedNodes - For nodes that need to be expanded this map indicates
89 /// which operands are the expanded version of the input. This allows
90 /// us to avoid expanding the same node more than once.
91 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
93 /// SplitNodes - For vector nodes that need to be split, this map indicates
94 /// which operands are the split version of the input. This allows us
95 /// to avoid splitting the same node more than once.
96 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
98 /// ScalarizedNodes - For nodes that need to be converted from vector types to
99 /// scalar types, this contains the mapping of ones we have already
100 /// processed to the result.
101 std::map<SDValue, SDValue> ScalarizedNodes;
103 /// WidenNodes - For nodes that need to be widened from one vector type to
104 /// another, this contains the mapping of those that we have already widen.
105 /// This allows us to avoid widening more than once.
106 std::map<SDValue, SDValue> WidenNodes;
108 void AddLegalizedOperand(SDValue From, SDValue To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDValue From, SDValue To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
116 assert(isNew && "Got into the map somehow?");
118 // If someone requests legalization of the new node, return itself.
119 LegalizedNodes.insert(std::make_pair(To, To));
121 void AddWidenedOperand(SDValue From, SDValue To) {
122 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
123 assert(isNew && "Got into the map somehow?");
125 // If someone requests legalization of the new node, return itself.
126 LegalizedNodes.insert(std::make_pair(To, To));
130 explicit SelectionDAGLegalize(SelectionDAG &DAG);
132 /// getTypeAction - Return how we should legalize values of this type, either
133 /// it is already legal or we need to expand it into multiple registers of
134 /// smaller integer type, or we need to promote it to a larger type.
135 LegalizeAction getTypeAction(MVT VT) const {
136 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
139 /// isTypeLegal - Return true if this type is legal on this target.
141 bool isTypeLegal(MVT VT) const {
142 return getTypeAction(VT) == Legal;
148 /// HandleOp - Legalize, Promote, or Expand the specified operand as
149 /// appropriate for its type.
150 void HandleOp(SDValue Op);
152 /// LegalizeOp - We know that the specified value has a legal type.
153 /// Recursively ensure that the operands have legal types, then return the
155 SDValue LegalizeOp(SDValue O);
157 /// UnrollVectorOp - We know that the given vector has a legal type, however
158 /// the operation it performs is not legal and is an operation that we have
159 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
160 /// operating on each element individually.
161 SDValue UnrollVectorOp(SDValue O);
163 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
164 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
165 /// is necessary to spill the vector being inserted into to memory, perform
166 /// the insert there, and then read the result back.
167 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
170 /// PromoteOp - Given an operation that produces a value in an invalid type,
171 /// promote it to compute the value into a larger type. The produced value
172 /// will have the correct bits for the low portion of the register, but no
173 /// guarantee is made about the top bits: it may be zero, sign-extended, or
175 SDValue PromoteOp(SDValue O);
177 /// ExpandOp - Expand the specified SDValue into its two component pieces
178 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
179 /// the LegalizedNodes map is filled in for any results that are not expanded,
180 /// the ExpandedNodes map is filled in for any results that are expanded, and
181 /// the Lo/Hi values are returned. This applies to integer types and Vector
183 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
185 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
186 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
187 /// for the existing elements but no guarantee is made about the new elements
188 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
189 /// when we have an instruction operating on an illegal vector type and we
190 /// want to widen it to do the computation on a legal wider vector type.
191 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
193 /// SplitVectorOp - Given an operand of vector type, break it down into
194 /// two smaller values.
195 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
197 /// ScalarizeVectorOp - Given an operand of single-element vector type
198 /// (e.g. v1f32), convert it into the equivalent operation that returns a
199 /// scalar (e.g. f32) value.
200 SDValue ScalarizeVectorOp(SDValue O);
202 /// Useful 16 element vector type that is used to pass operands for widening.
203 typedef SmallVector<SDValue, 16> SDValueVector;
205 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
206 /// the LdChain contains a single load and false if it contains a token
207 /// factor for multiple loads. It takes
208 /// Result: location to return the result
209 /// LdChain: location to return the load chain
210 /// Op: load operation to widen
211 /// NVT: widen vector result type we want for the load
212 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
213 SDValue Op, MVT NVT);
215 /// Helper genWidenVectorLoads - Helper function to generate a set of
216 /// loads to load a vector with a resulting wider type. It takes
217 /// LdChain: list of chains for the load we have generated
218 /// Chain: incoming chain for the ld vector
219 /// BasePtr: base pointer to load from
220 /// SV: memory disambiguation source value
221 /// SVOffset: memory disambiugation offset
222 /// Alignment: alignment of the memory
223 /// isVolatile: volatile load
224 /// LdWidth: width of memory that we want to load
225 /// ResType: the wider result result type for the resulting loaded vector
226 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
227 SDValue BasePtr, const Value *SV,
228 int SVOffset, unsigned Alignment,
229 bool isVolatile, unsigned LdWidth,
232 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
233 /// location. It takes
234 /// ST: store node that we want to replace
235 /// Chain: incoming store chain
236 /// BasePtr: base address of where we want to store into
237 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
240 /// Helper genWidenVectorStores - Helper function to generate a set of
241 /// stores to store a widen vector into non widen memory
243 // StChain: list of chains for the stores we have generated
244 // Chain: incoming chain for the ld vector
245 // BasePtr: base pointer to load from
246 // SV: memory disambiguation source value
247 // SVOffset: memory disambiugation offset
248 // Alignment: alignment of the memory
249 // isVolatile: volatile lod
250 // ValOp: value to store
251 // StWidth: width of memory that we want to store
252 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
253 SDValue BasePtr, const Value *SV,
254 int SVOffset, unsigned Alignment,
255 bool isVolatile, SDValue ValOp,
258 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
259 /// specified mask and type. Targets can specify exactly which masks they
260 /// support and the code generator is tasked with not creating illegal masks.
262 /// Note that this will also return true for shuffles that are promoted to a
265 /// If this is a legal shuffle, this method returns the (possibly promoted)
266 /// build_vector Mask. If it's not a legal shuffle, it returns null.
267 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
269 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
270 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
272 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
273 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
274 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
275 LegalizeSetCCOperands(LHS, RHS, CC);
276 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
279 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
281 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
283 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
284 SDValue ExpandBUILD_VECTOR(SDNode *Node);
285 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
286 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
287 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
288 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
289 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
291 SDValue ExpandBSWAP(SDValue Op);
292 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
293 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
294 SDValue &Lo, SDValue &Hi);
295 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
296 SDValue &Lo, SDValue &Hi);
298 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
299 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
303 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
304 /// specified mask and type. Targets can specify exactly which masks they
305 /// support and the code generator is tasked with not creating illegal masks.
307 /// Note that this will also return true for shuffles that are promoted to a
309 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
310 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
312 case TargetLowering::Legal:
313 case TargetLowering::Custom:
315 case TargetLowering::Promote: {
316 // If this is promoted to a different type, convert the shuffle mask and
317 // ask if it is legal in the promoted type!
318 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
319 MVT EltVT = NVT.getVectorElementType();
321 // If we changed # elements, change the shuffle mask.
322 unsigned NumEltsGrowth =
323 NVT.getVectorNumElements() / VT.getVectorNumElements();
324 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
325 if (NumEltsGrowth > 1) {
326 // Renumber the elements.
327 SmallVector<SDValue, 8> Ops;
328 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
329 SDValue InOp = Mask.getOperand(i);
330 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
331 if (InOp.getOpcode() == ISD::UNDEF)
332 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
334 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
335 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
339 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
345 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
348 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
349 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
350 ValueTypeActions(TLI.getValueTypeActions()) {
351 assert(MVT::LAST_VALUETYPE <= 32 &&
352 "Too many value types for ValueTypeActions to hold!");
355 void SelectionDAGLegalize::LegalizeDAG() {
356 LastCALLSEQ_END = DAG.getEntryNode();
357 IsLegalizingCall = false;
359 // The legalize process is inherently a bottom-up recursive process (users
360 // legalize their uses before themselves). Given infinite stack space, we
361 // could just start legalizing on the root and traverse the whole graph. In
362 // practice however, this causes us to run out of stack space on large basic
363 // blocks. To avoid this problem, compute an ordering of the nodes where each
364 // node is only legalized after all of its operands are legalized.
365 DAG.AssignTopologicalOrder();
366 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
367 E = prior(DAG.allnodes_end()); I != next(E); ++I)
368 HandleOp(SDValue(I, 0));
370 // Finally, it's possible the root changed. Get the new root.
371 SDValue OldRoot = DAG.getRoot();
372 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
373 DAG.setRoot(LegalizedNodes[OldRoot]);
375 ExpandedNodes.clear();
376 LegalizedNodes.clear();
377 PromotedNodes.clear();
379 ScalarizedNodes.clear();
382 // Remove dead nodes now.
383 DAG.RemoveDeadNodes();
387 /// FindCallEndFromCallStart - Given a chained node that is part of a call
388 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
389 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
390 if (Node->getOpcode() == ISD::CALLSEQ_END)
392 if (Node->use_empty())
393 return 0; // No CallSeqEnd
395 // The chain is usually at the end.
396 SDValue TheChain(Node, Node->getNumValues()-1);
397 if (TheChain.getValueType() != MVT::Other) {
398 // Sometimes it's at the beginning.
399 TheChain = SDValue(Node, 0);
400 if (TheChain.getValueType() != MVT::Other) {
401 // Otherwise, hunt for it.
402 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
403 if (Node->getValueType(i) == MVT::Other) {
404 TheChain = SDValue(Node, i);
408 // Otherwise, we walked into a node without a chain.
409 if (TheChain.getValueType() != MVT::Other)
414 for (SDNode::use_iterator UI = Node->use_begin(),
415 E = Node->use_end(); UI != E; ++UI) {
417 // Make sure to only follow users of our token chain.
419 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
420 if (User->getOperand(i) == TheChain)
421 if (SDNode *Result = FindCallEndFromCallStart(User))
427 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
428 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
429 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
430 assert(Node && "Didn't find callseq_start for a call??");
431 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
433 assert(Node->getOperand(0).getValueType() == MVT::Other &&
434 "Node doesn't have a token chain argument!");
435 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
438 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
439 /// see if any uses can reach Dest. If no dest operands can get to dest,
440 /// legalize them, legalize ourself, and return false, otherwise, return true.
442 /// Keep track of the nodes we fine that actually do lead to Dest in
443 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
445 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
446 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
447 if (N == Dest) return true; // N certainly leads to Dest :)
449 // If we've already processed this node and it does lead to Dest, there is no
450 // need to reprocess it.
451 if (NodesLeadingTo.count(N)) return true;
453 // If the first result of this node has been already legalized, then it cannot
455 switch (getTypeAction(N->getValueType(0))) {
457 if (LegalizedNodes.count(SDValue(N, 0))) return false;
460 if (PromotedNodes.count(SDValue(N, 0))) return false;
463 if (ExpandedNodes.count(SDValue(N, 0))) return false;
467 // Okay, this node has not already been legalized. Check and legalize all
468 // operands. If none lead to Dest, then we can legalize this node.
469 bool OperandsLeadToDest = false;
470 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
471 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
472 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
474 if (OperandsLeadToDest) {
475 NodesLeadingTo.insert(N);
479 // Okay, this node looks safe, legalize it and return false.
480 HandleOp(SDValue(N, 0));
484 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
485 /// appropriate for its type.
486 void SelectionDAGLegalize::HandleOp(SDValue Op) {
487 MVT VT = Op.getValueType();
488 switch (getTypeAction(VT)) {
489 default: assert(0 && "Bad type action!");
490 case Legal: (void)LegalizeOp(Op); break;
492 if (!VT.isVector()) {
497 // See if we can widen otherwise use Expand to either scalarize or split
498 MVT WidenVT = TLI.getWidenVectorType(VT);
499 if (WidenVT != MVT::Other) {
500 (void) WidenVectorOp(Op, WidenVT);
503 // else fall thru to expand since we can't widen the vector
506 if (!VT.isVector()) {
507 // If this is an illegal scalar, expand it into its two component
510 if (Op.getOpcode() == ISD::TargetConstant)
511 break; // Allow illegal target nodes.
513 } else if (VT.getVectorNumElements() == 1) {
514 // If this is an illegal single element vector, convert it to a
516 (void)ScalarizeVectorOp(Op);
518 // This is an illegal multiple element vector.
519 // Split it in half and legalize both parts.
521 SplitVectorOp(Op, X, Y);
527 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
528 /// a load from the constant pool.
529 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
530 SelectionDAG &DAG, TargetLowering &TLI) {
533 // If a FP immediate is precise when represented as a float and if the
534 // target can do an extending load from float to double, we put it into
535 // the constant pool as a float, even if it's is statically typed as a
536 // double. This shrinks FP constants and canonicalizes them for targets where
537 // an FP extending load is the same cost as a normal load (such as on the x87
538 // fp stack or PPC FP unit).
539 MVT VT = CFP->getValueType(0);
540 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
542 if (VT!=MVT::f64 && VT!=MVT::f32)
543 assert(0 && "Invalid type expansion");
544 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
545 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
550 while (SVT != MVT::f32) {
551 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
552 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
553 // Only do this if the target has a native EXTLOAD instruction from
555 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
556 TLI.ShouldShrinkFPConstant(OrigVT)) {
557 const Type *SType = SVT.getTypeForMVT();
558 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
564 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
565 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
567 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
568 CPIdx, PseudoSourceValue::getConstantPool(),
569 0, VT, false, Alignment);
570 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
571 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
575 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
578 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
579 SelectionDAG &DAG, TargetLowering &TLI) {
580 MVT VT = Node->getValueType(0);
581 MVT SrcVT = Node->getOperand(1).getValueType();
582 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
583 "fcopysign expansion only supported for f32 and f64");
584 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
586 // First get the sign bit of second operand.
587 SDValue Mask1 = (SrcVT == MVT::f64)
588 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
589 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
590 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
591 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
592 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
593 // Shift right or sign-extend it if the two operands have different types.
594 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
596 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
597 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
598 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
599 } else if (SizeDiff < 0) {
600 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
601 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
602 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
605 // Clear the sign bit of first operand.
606 SDValue Mask2 = (VT == MVT::f64)
607 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
608 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
609 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
610 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
611 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
613 // Or the value with the sign bit.
614 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
618 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
620 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
621 TargetLowering &TLI) {
622 SDValue Chain = ST->getChain();
623 SDValue Ptr = ST->getBasePtr();
624 SDValue Val = ST->getValue();
625 MVT VT = Val.getValueType();
626 int Alignment = ST->getAlignment();
627 int SVOffset = ST->getSrcValueOffset();
628 if (ST->getMemoryVT().isFloatingPoint() ||
629 ST->getMemoryVT().isVector()) {
630 // Expand to a bitconvert of the value to the integer type of the
631 // same size, then a (misaligned) int store.
633 if (VT.is128BitVector() || VT == MVT::ppcf128 || VT == MVT::f128)
635 else if (VT.is64BitVector() || VT==MVT::f64)
637 else if (VT==MVT::f32)
640 assert(0 && "Unaligned store of unsupported type");
642 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
643 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
644 SVOffset, ST->isVolatile(), Alignment);
646 assert(ST->getMemoryVT().isInteger() &&
647 !ST->getMemoryVT().isVector() &&
648 "Unaligned store of unknown type.");
649 // Get the half-size VT
651 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
652 int NumBits = NewStoredVT.getSizeInBits();
653 int IncrementSize = NumBits / 8;
655 // Divide the stored value in two parts.
656 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
658 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
660 // Store the two parts
661 SDValue Store1, Store2;
662 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
663 ST->getSrcValue(), SVOffset, NewStoredVT,
664 ST->isVolatile(), Alignment);
665 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
666 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
667 Alignment = MinAlign(Alignment, IncrementSize);
668 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
669 ST->getSrcValue(), SVOffset + IncrementSize,
670 NewStoredVT, ST->isVolatile(), Alignment);
672 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
675 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
677 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
678 TargetLowering &TLI) {
679 int SVOffset = LD->getSrcValueOffset();
680 SDValue Chain = LD->getChain();
681 SDValue Ptr = LD->getBasePtr();
682 MVT VT = LD->getValueType(0);
683 MVT LoadedVT = LD->getMemoryVT();
684 if (VT.isFloatingPoint() || VT.isVector()) {
685 // Expand to a (misaligned) integer load of the same size,
686 // then bitconvert to floating point or vector.
688 if (LoadedVT.is128BitVector() ||
689 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
691 else if (LoadedVT.is64BitVector() || LoadedVT == MVT::f64)
693 else if (LoadedVT == MVT::f32)
696 assert(0 && "Unaligned load of unsupported type");
698 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
699 SVOffset, LD->isVolatile(),
701 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
702 if (VT.isFloatingPoint() && LoadedVT != VT)
703 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
705 SDValue Ops[] = { Result, Chain };
706 return DAG.getMergeValues(Ops, 2);
708 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
709 "Unaligned load of unsupported type.");
711 // Compute the new VT that is half the size of the old one. This is an
713 unsigned NumBits = LoadedVT.getSizeInBits();
715 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
718 unsigned Alignment = LD->getAlignment();
719 unsigned IncrementSize = NumBits / 8;
720 ISD::LoadExtType HiExtType = LD->getExtensionType();
722 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
723 if (HiExtType == ISD::NON_EXTLOAD)
724 HiExtType = ISD::ZEXTLOAD;
726 // Load the value in two parts
728 if (TLI.isLittleEndian()) {
729 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
730 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
731 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
732 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
733 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
734 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
735 MinAlign(Alignment, IncrementSize));
737 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
738 NewLoadedVT,LD->isVolatile(), Alignment);
739 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
740 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
741 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
742 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
743 MinAlign(Alignment, IncrementSize));
746 // aggregate the two parts
747 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
748 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
749 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
751 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
754 SDValue Ops[] = { Result, TF };
755 return DAG.getMergeValues(Ops, 2);
758 /// UnrollVectorOp - We know that the given vector has a legal type, however
759 /// the operation it performs is not legal and is an operation that we have
760 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
761 /// operating on each element individually.
762 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
763 MVT VT = Op.getValueType();
764 assert(isTypeLegal(VT) &&
765 "Caller should expand or promote operands that are not legal!");
766 assert(Op.getNode()->getNumValues() == 1 &&
767 "Can't unroll a vector with multiple results!");
768 unsigned NE = VT.getVectorNumElements();
769 MVT EltVT = VT.getVectorElementType();
771 SmallVector<SDValue, 8> Scalars;
772 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
773 for (unsigned i = 0; i != NE; ++i) {
774 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
775 SDValue Operand = Op.getOperand(j);
776 MVT OperandVT = Operand.getValueType();
777 if (OperandVT.isVector()) {
778 // A vector operand; extract a single element.
779 MVT OperandEltVT = OperandVT.getVectorElementType();
780 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
783 DAG.getConstant(i, MVT::i32));
785 // A scalar operand; just use it as is.
786 Operands[j] = Operand;
789 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
790 &Operands[0], Operands.size()));
793 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
796 /// GetFPLibCall - Return the right libcall for the given floating point type.
797 static RTLIB::Libcall GetFPLibCall(MVT VT,
798 RTLIB::Libcall Call_F32,
799 RTLIB::Libcall Call_F64,
800 RTLIB::Libcall Call_F80,
801 RTLIB::Libcall Call_PPCF128) {
803 VT == MVT::f32 ? Call_F32 :
804 VT == MVT::f64 ? Call_F64 :
805 VT == MVT::f80 ? Call_F80 :
806 VT == MVT::ppcf128 ? Call_PPCF128 :
807 RTLIB::UNKNOWN_LIBCALL;
810 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
811 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
812 /// is necessary to spill the vector being inserted into to memory, perform
813 /// the insert there, and then read the result back.
814 SDValue SelectionDAGLegalize::
815 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
820 // If the target doesn't support this, we have to spill the input vector
821 // to a temporary stack slot, update the element, then reload it. This is
822 // badness. We could also load the value into a vector register (either
823 // with a "move to register" or "extload into register" instruction, then
824 // permute it into place, if the idx is a constant and if the idx is
825 // supported by the target.
826 MVT VT = Tmp1.getValueType();
827 MVT EltVT = VT.getVectorElementType();
828 MVT IdxVT = Tmp3.getValueType();
829 MVT PtrVT = TLI.getPointerTy();
830 SDValue StackPtr = DAG.CreateStackTemporary(VT);
832 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
835 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
836 PseudoSourceValue::getFixedStack(SPFI), 0);
838 // Truncate or zero extend offset to target pointer type.
839 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
840 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
841 // Add the offset to the index.
842 unsigned EltSize = EltVT.getSizeInBits()/8;
843 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
844 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
845 // Store the scalar value.
846 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
847 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
848 // Load the updated vector.
849 return DAG.getLoad(VT, Ch, StackPtr,
850 PseudoSourceValue::getFixedStack(SPFI), 0);
853 /// LegalizeOp - We know that the specified value has a legal type, and
854 /// that its operands are legal. Now ensure that the operation itself
855 /// is legal, recursively ensuring that the operands' operations remain
857 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
858 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
861 assert(isTypeLegal(Op.getValueType()) &&
862 "Caller should expand or promote operands that are not legal!");
863 SDNode *Node = Op.getNode();
865 // If this operation defines any values that cannot be represented in a
866 // register on this target, make sure to expand or promote them.
867 if (Node->getNumValues() > 1) {
868 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
869 if (getTypeAction(Node->getValueType(i)) != Legal) {
870 HandleOp(Op.getValue(i));
871 assert(LegalizedNodes.count(Op) &&
872 "Handling didn't add legal operands!");
873 return LegalizedNodes[Op];
877 // Note that LegalizeOp may be reentered even from single-use nodes, which
878 // means that we always must cache transformed nodes.
879 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
880 if (I != LegalizedNodes.end()) return I->second;
882 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
884 bool isCustom = false;
886 switch (Node->getOpcode()) {
887 case ISD::FrameIndex:
888 case ISD::EntryToken:
890 case ISD::BasicBlock:
891 case ISD::TargetFrameIndex:
892 case ISD::TargetJumpTable:
893 case ISD::TargetConstant:
894 case ISD::TargetConstantFP:
895 case ISD::TargetConstantPool:
896 case ISD::TargetGlobalAddress:
897 case ISD::TargetGlobalTLSAddress:
898 case ISD::TargetExternalSymbol:
901 case ISD::MEMOPERAND:
904 // Primitives must all be legal.
905 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
906 "This must be legal!");
909 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
910 // If this is a target node, legalize it by legalizing the operands then
911 // passing it through.
912 SmallVector<SDValue, 8> Ops;
913 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
914 Ops.push_back(LegalizeOp(Node->getOperand(i)));
916 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
918 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
919 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
920 return Result.getValue(Op.getResNo());
922 // Otherwise this is an unhandled builtin node. splat.
924 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
926 assert(0 && "Do not know how to legalize this operator!");
928 case ISD::GLOBAL_OFFSET_TABLE:
929 case ISD::GlobalAddress:
930 case ISD::GlobalTLSAddress:
931 case ISD::ExternalSymbol:
932 case ISD::ConstantPool:
933 case ISD::JumpTable: // Nothing to do.
934 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
935 default: assert(0 && "This action is not supported yet!");
936 case TargetLowering::Custom:
937 Tmp1 = TLI.LowerOperation(Op, DAG);
938 if (Tmp1.getNode()) Result = Tmp1;
939 // FALLTHROUGH if the target doesn't want to lower this op after all.
940 case TargetLowering::Legal:
945 case ISD::RETURNADDR:
946 // The only option for these nodes is to custom lower them. If the target
947 // does not custom lower them, then return zero.
948 Tmp1 = TLI.LowerOperation(Op, DAG);
952 Result = DAG.getConstant(0, TLI.getPointerTy());
954 case ISD::FRAME_TO_ARGS_OFFSET: {
955 MVT VT = Node->getValueType(0);
956 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
957 default: assert(0 && "This action is not supported yet!");
958 case TargetLowering::Custom:
959 Result = TLI.LowerOperation(Op, DAG);
960 if (Result.getNode()) break;
962 case TargetLowering::Legal:
963 Result = DAG.getConstant(0, VT);
968 case ISD::EXCEPTIONADDR: {
969 Tmp1 = LegalizeOp(Node->getOperand(0));
970 MVT VT = Node->getValueType(0);
971 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
972 default: assert(0 && "This action is not supported yet!");
973 case TargetLowering::Expand: {
974 unsigned Reg = TLI.getExceptionAddressRegister();
975 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
978 case TargetLowering::Custom:
979 Result = TLI.LowerOperation(Op, DAG);
980 if (Result.getNode()) break;
982 case TargetLowering::Legal: {
983 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
984 Result = DAG.getMergeValues(Ops, 2);
989 if (Result.getNode()->getNumValues() == 1) break;
991 assert(Result.getNode()->getNumValues() == 2 &&
992 "Cannot return more than two values!");
994 // Since we produced two values, make sure to remember that we
995 // legalized both of them.
996 Tmp1 = LegalizeOp(Result);
997 Tmp2 = LegalizeOp(Result.getValue(1));
998 AddLegalizedOperand(Op.getValue(0), Tmp1);
999 AddLegalizedOperand(Op.getValue(1), Tmp2);
1000 return Op.getResNo() ? Tmp2 : Tmp1;
1001 case ISD::EHSELECTION: {
1002 Tmp1 = LegalizeOp(Node->getOperand(0));
1003 Tmp2 = LegalizeOp(Node->getOperand(1));
1004 MVT VT = Node->getValueType(0);
1005 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1006 default: assert(0 && "This action is not supported yet!");
1007 case TargetLowering::Expand: {
1008 unsigned Reg = TLI.getExceptionSelectorRegister();
1009 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1012 case TargetLowering::Custom:
1013 Result = TLI.LowerOperation(Op, DAG);
1014 if (Result.getNode()) break;
1016 case TargetLowering::Legal: {
1017 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1018 Result = DAG.getMergeValues(Ops, 2);
1023 if (Result.getNode()->getNumValues() == 1) break;
1025 assert(Result.getNode()->getNumValues() == 2 &&
1026 "Cannot return more than two values!");
1028 // Since we produced two values, make sure to remember that we
1029 // legalized both of them.
1030 Tmp1 = LegalizeOp(Result);
1031 Tmp2 = LegalizeOp(Result.getValue(1));
1032 AddLegalizedOperand(Op.getValue(0), Tmp1);
1033 AddLegalizedOperand(Op.getValue(1), Tmp2);
1034 return Op.getResNo() ? Tmp2 : Tmp1;
1035 case ISD::EH_RETURN: {
1036 MVT VT = Node->getValueType(0);
1037 // The only "good" option for this node is to custom lower it.
1038 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1039 default: assert(0 && "This action is not supported at all!");
1040 case TargetLowering::Custom:
1041 Result = TLI.LowerOperation(Op, DAG);
1042 if (Result.getNode()) break;
1044 case TargetLowering::Legal:
1045 // Target does not know, how to lower this, lower to noop
1046 Result = LegalizeOp(Node->getOperand(0));
1051 case ISD::AssertSext:
1052 case ISD::AssertZext:
1053 Tmp1 = LegalizeOp(Node->getOperand(0));
1054 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1056 case ISD::MERGE_VALUES:
1057 // Legalize eliminates MERGE_VALUES nodes.
1058 Result = Node->getOperand(Op.getResNo());
1060 case ISD::CopyFromReg:
1061 Tmp1 = LegalizeOp(Node->getOperand(0));
1062 Result = Op.getValue(0);
1063 if (Node->getNumValues() == 2) {
1064 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1066 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1067 if (Node->getNumOperands() == 3) {
1068 Tmp2 = LegalizeOp(Node->getOperand(2));
1069 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1071 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1073 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1075 // Since CopyFromReg produces two values, make sure to remember that we
1076 // legalized both of them.
1077 AddLegalizedOperand(Op.getValue(0), Result);
1078 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1079 return Result.getValue(Op.getResNo());
1081 MVT VT = Op.getValueType();
1082 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1083 default: assert(0 && "This action is not supported yet!");
1084 case TargetLowering::Expand:
1086 Result = DAG.getConstant(0, VT);
1087 else if (VT.isFloatingPoint())
1088 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1091 assert(0 && "Unknown value type!");
1093 case TargetLowering::Legal:
1099 case ISD::INTRINSIC_W_CHAIN:
1100 case ISD::INTRINSIC_WO_CHAIN:
1101 case ISD::INTRINSIC_VOID: {
1102 SmallVector<SDValue, 8> Ops;
1103 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1104 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1105 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1107 // Allow the target to custom lower its intrinsics if it wants to.
1108 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1109 TargetLowering::Custom) {
1110 Tmp3 = TLI.LowerOperation(Result, DAG);
1111 if (Tmp3.getNode()) Result = Tmp3;
1114 if (Result.getNode()->getNumValues() == 1) break;
1116 // Must have return value and chain result.
1117 assert(Result.getNode()->getNumValues() == 2 &&
1118 "Cannot return more than two values!");
1120 // Since loads produce two values, make sure to remember that we
1121 // legalized both of them.
1122 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1123 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1124 return Result.getValue(Op.getResNo());
1127 case ISD::DBG_STOPPOINT:
1128 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1129 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1131 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1132 case TargetLowering::Promote:
1133 default: assert(0 && "This action is not supported yet!");
1134 case TargetLowering::Expand: {
1135 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1136 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1137 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1139 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1140 if (MMI && (useDEBUG_LOC || useLABEL)) {
1141 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1142 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1144 unsigned Line = DSP->getLine();
1145 unsigned Col = DSP->getColumn();
1148 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1149 DAG.getConstant(Col, MVT::i32),
1150 DAG.getConstant(SrcFile, MVT::i32) };
1151 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1153 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1154 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1157 Result = Tmp1; // chain
1161 case TargetLowering::Legal: {
1162 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1163 if (Action == Legal && Tmp1 == Node->getOperand(0))
1166 SmallVector<SDValue, 8> Ops;
1167 Ops.push_back(Tmp1);
1168 if (Action == Legal) {
1169 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1170 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1172 // Otherwise promote them.
1173 Ops.push_back(PromoteOp(Node->getOperand(1)));
1174 Ops.push_back(PromoteOp(Node->getOperand(2)));
1176 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1177 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1178 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1185 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1186 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1187 default: assert(0 && "This action is not supported yet!");
1188 case TargetLowering::Legal:
1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1190 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1191 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1192 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1194 case TargetLowering::Expand:
1195 Result = LegalizeOp(Node->getOperand(0));
1200 case ISD::DEBUG_LOC:
1201 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1202 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1203 default: assert(0 && "This action is not supported yet!");
1204 case TargetLowering::Legal: {
1205 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1206 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1207 if (Action == Legal && Tmp1 == Node->getOperand(0))
1209 if (Action == Legal) {
1210 Tmp2 = Node->getOperand(1);
1211 Tmp3 = Node->getOperand(2);
1212 Tmp4 = Node->getOperand(3);
1214 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1215 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1216 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1224 case ISD::DBG_LABEL:
1226 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1227 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1228 default: assert(0 && "This action is not supported yet!");
1229 case TargetLowering::Legal:
1230 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1231 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1233 case TargetLowering::Expand:
1234 Result = LegalizeOp(Node->getOperand(0));
1240 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1241 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1242 default: assert(0 && "This action is not supported yet!");
1243 case TargetLowering::Legal:
1244 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1245 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1246 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1247 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1248 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1250 case TargetLowering::Expand:
1252 Result = LegalizeOp(Node->getOperand(0));
1257 case ISD::MEMBARRIER: {
1258 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1259 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1260 default: assert(0 && "This action is not supported yet!");
1261 case TargetLowering::Legal: {
1263 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1264 for (int x = 1; x < 6; ++x) {
1265 Ops[x] = Node->getOperand(x);
1266 if (!isTypeLegal(Ops[x].getValueType()))
1267 Ops[x] = PromoteOp(Ops[x]);
1269 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1272 case TargetLowering::Expand:
1273 //There is no libgcc call for this op
1274 Result = Node->getOperand(0); // Noop
1280 case ISD::ATOMIC_CMP_SWAP_8:
1281 case ISD::ATOMIC_CMP_SWAP_16:
1282 case ISD::ATOMIC_CMP_SWAP_32:
1283 case ISD::ATOMIC_CMP_SWAP_64: {
1284 unsigned int num_operands = 4;
1285 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1287 for (unsigned int x = 0; x < num_operands; ++x)
1288 Ops[x] = LegalizeOp(Node->getOperand(x));
1289 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1291 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1292 default: assert(0 && "This action is not supported yet!");
1293 case TargetLowering::Custom:
1294 Result = TLI.LowerOperation(Result, DAG);
1296 case TargetLowering::Legal:
1299 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1300 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1301 return Result.getValue(Op.getResNo());
1303 case ISD::ATOMIC_LOAD_ADD_8:
1304 case ISD::ATOMIC_LOAD_SUB_8:
1305 case ISD::ATOMIC_LOAD_AND_8:
1306 case ISD::ATOMIC_LOAD_OR_8:
1307 case ISD::ATOMIC_LOAD_XOR_8:
1308 case ISD::ATOMIC_LOAD_NAND_8:
1309 case ISD::ATOMIC_LOAD_MIN_8:
1310 case ISD::ATOMIC_LOAD_MAX_8:
1311 case ISD::ATOMIC_LOAD_UMIN_8:
1312 case ISD::ATOMIC_LOAD_UMAX_8:
1313 case ISD::ATOMIC_SWAP_8:
1314 case ISD::ATOMIC_LOAD_ADD_16:
1315 case ISD::ATOMIC_LOAD_SUB_16:
1316 case ISD::ATOMIC_LOAD_AND_16:
1317 case ISD::ATOMIC_LOAD_OR_16:
1318 case ISD::ATOMIC_LOAD_XOR_16:
1319 case ISD::ATOMIC_LOAD_NAND_16:
1320 case ISD::ATOMIC_LOAD_MIN_16:
1321 case ISD::ATOMIC_LOAD_MAX_16:
1322 case ISD::ATOMIC_LOAD_UMIN_16:
1323 case ISD::ATOMIC_LOAD_UMAX_16:
1324 case ISD::ATOMIC_SWAP_16:
1325 case ISD::ATOMIC_LOAD_ADD_32:
1326 case ISD::ATOMIC_LOAD_SUB_32:
1327 case ISD::ATOMIC_LOAD_AND_32:
1328 case ISD::ATOMIC_LOAD_OR_32:
1329 case ISD::ATOMIC_LOAD_XOR_32:
1330 case ISD::ATOMIC_LOAD_NAND_32:
1331 case ISD::ATOMIC_LOAD_MIN_32:
1332 case ISD::ATOMIC_LOAD_MAX_32:
1333 case ISD::ATOMIC_LOAD_UMIN_32:
1334 case ISD::ATOMIC_LOAD_UMAX_32:
1335 case ISD::ATOMIC_SWAP_32:
1336 case ISD::ATOMIC_LOAD_ADD_64:
1337 case ISD::ATOMIC_LOAD_SUB_64:
1338 case ISD::ATOMIC_LOAD_AND_64:
1339 case ISD::ATOMIC_LOAD_OR_64:
1340 case ISD::ATOMIC_LOAD_XOR_64:
1341 case ISD::ATOMIC_LOAD_NAND_64:
1342 case ISD::ATOMIC_LOAD_MIN_64:
1343 case ISD::ATOMIC_LOAD_MAX_64:
1344 case ISD::ATOMIC_LOAD_UMIN_64:
1345 case ISD::ATOMIC_LOAD_UMAX_64:
1346 case ISD::ATOMIC_SWAP_64: {
1347 unsigned int num_operands = 3;
1348 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1350 for (unsigned int x = 0; x < num_operands; ++x)
1351 Ops[x] = LegalizeOp(Node->getOperand(x));
1352 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1354 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1355 default: assert(0 && "This action is not supported yet!");
1356 case TargetLowering::Custom:
1357 Result = TLI.LowerOperation(Result, DAG);
1359 case TargetLowering::Legal:
1362 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1363 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1364 return Result.getValue(Op.getResNo());
1366 case ISD::Constant: {
1367 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1369 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1371 // We know we don't need to expand constants here, constants only have one
1372 // value and we check that it is fine above.
1374 if (opAction == TargetLowering::Custom) {
1375 Tmp1 = TLI.LowerOperation(Result, DAG);
1381 case ISD::ConstantFP: {
1382 // Spill FP immediates to the constant pool if the target cannot directly
1383 // codegen them. Targets often have some immediate values that can be
1384 // efficiently generated into an FP register without a load. We explicitly
1385 // leave these constants as ConstantFP nodes for the target to deal with.
1386 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1388 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1389 default: assert(0 && "This action is not supported yet!");
1390 case TargetLowering::Legal:
1392 case TargetLowering::Custom:
1393 Tmp3 = TLI.LowerOperation(Result, DAG);
1394 if (Tmp3.getNode()) {
1399 case TargetLowering::Expand: {
1400 // Check to see if this FP immediate is already legal.
1401 bool isLegal = false;
1402 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1403 E = TLI.legal_fpimm_end(); I != E; ++I) {
1404 if (CFP->isExactlyValue(*I)) {
1409 // If this is a legal constant, turn it into a TargetConstantFP node.
1412 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1417 case ISD::TokenFactor:
1418 if (Node->getNumOperands() == 2) {
1419 Tmp1 = LegalizeOp(Node->getOperand(0));
1420 Tmp2 = LegalizeOp(Node->getOperand(1));
1421 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1422 } else if (Node->getNumOperands() == 3) {
1423 Tmp1 = LegalizeOp(Node->getOperand(0));
1424 Tmp2 = LegalizeOp(Node->getOperand(1));
1425 Tmp3 = LegalizeOp(Node->getOperand(2));
1426 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1428 SmallVector<SDValue, 8> Ops;
1429 // Legalize the operands.
1430 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1431 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1432 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1436 case ISD::FORMAL_ARGUMENTS:
1438 // The only option for this is to custom lower it.
1439 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1440 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1441 // A call within a calling sequence must be legalized to something
1442 // other than the normal CALLSEQ_END. Violating this gets Legalize
1443 // into an infinite loop.
1444 assert ((!IsLegalizingCall ||
1445 Node->getOpcode() != ISD::CALL ||
1446 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1447 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1449 // The number of incoming and outgoing values should match; unless the final
1450 // outgoing value is a flag.
1451 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1452 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1453 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1455 "Lowering call/formal_arguments produced unexpected # results!");
1457 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1458 // remember that we legalized all of them, so it doesn't get relegalized.
1459 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1460 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1462 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1463 if (Op.getResNo() == i)
1465 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1468 case ISD::EXTRACT_SUBREG: {
1469 Tmp1 = LegalizeOp(Node->getOperand(0));
1470 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1471 assert(idx && "Operand must be a constant");
1472 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1473 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1476 case ISD::INSERT_SUBREG: {
1477 Tmp1 = LegalizeOp(Node->getOperand(0));
1478 Tmp2 = LegalizeOp(Node->getOperand(1));
1479 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1480 assert(idx && "Operand must be a constant");
1481 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1482 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1485 case ISD::BUILD_VECTOR:
1486 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1487 default: assert(0 && "This action is not supported yet!");
1488 case TargetLowering::Custom:
1489 Tmp3 = TLI.LowerOperation(Result, DAG);
1490 if (Tmp3.getNode()) {
1495 case TargetLowering::Expand:
1496 Result = ExpandBUILD_VECTOR(Result.getNode());
1500 case ISD::INSERT_VECTOR_ELT:
1501 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1502 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1504 // The type of the value to insert may not be legal, even though the vector
1505 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1507 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1508 default: assert(0 && "Cannot expand insert element operand");
1509 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1510 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1512 // FIXME: An alternative would be to check to see if the target is not
1513 // going to custom lower this operation, we could bitcast to half elt
1514 // width and perform two inserts at that width, if that is legal.
1515 Tmp2 = Node->getOperand(1);
1518 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1520 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1521 Node->getValueType(0))) {
1522 default: assert(0 && "This action is not supported yet!");
1523 case TargetLowering::Legal:
1525 case TargetLowering::Custom:
1526 Tmp4 = TLI.LowerOperation(Result, DAG);
1527 if (Tmp4.getNode()) {
1532 case TargetLowering::Promote:
1533 // Fall thru for vector case
1534 case TargetLowering::Expand: {
1535 // If the insert index is a constant, codegen this as a scalar_to_vector,
1536 // then a shuffle that inserts it into the right position in the vector.
1537 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1538 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1539 // match the element type of the vector being created.
1540 if (Tmp2.getValueType() ==
1541 Op.getValueType().getVectorElementType()) {
1542 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1543 Tmp1.getValueType(), Tmp2);
1545 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1547 MVT::getIntVectorWithNumElements(NumElts);
1548 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1550 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1551 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1552 // elt 0 of the RHS.
1553 SmallVector<SDValue, 8> ShufOps;
1554 for (unsigned i = 0; i != NumElts; ++i) {
1555 if (i != InsertPos->getZExtValue())
1556 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1558 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1560 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1561 &ShufOps[0], ShufOps.size());
1563 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1564 Tmp1, ScVec, ShufMask);
1565 Result = LegalizeOp(Result);
1569 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1574 case ISD::SCALAR_TO_VECTOR:
1575 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1576 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1580 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1581 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1582 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1583 Node->getValueType(0))) {
1584 default: assert(0 && "This action is not supported yet!");
1585 case TargetLowering::Legal:
1587 case TargetLowering::Custom:
1588 Tmp3 = TLI.LowerOperation(Result, DAG);
1589 if (Tmp3.getNode()) {
1594 case TargetLowering::Expand:
1595 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1599 case ISD::VECTOR_SHUFFLE:
1600 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1601 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1602 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1604 // Allow targets to custom lower the SHUFFLEs they support.
1605 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1606 default: assert(0 && "Unknown operation action!");
1607 case TargetLowering::Legal:
1608 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1609 "vector shuffle should not be created if not legal!");
1611 case TargetLowering::Custom:
1612 Tmp3 = TLI.LowerOperation(Result, DAG);
1613 if (Tmp3.getNode()) {
1618 case TargetLowering::Expand: {
1619 MVT VT = Node->getValueType(0);
1620 MVT EltVT = VT.getVectorElementType();
1621 MVT PtrVT = TLI.getPointerTy();
1622 SDValue Mask = Node->getOperand(2);
1623 unsigned NumElems = Mask.getNumOperands();
1624 SmallVector<SDValue,8> Ops;
1625 for (unsigned i = 0; i != NumElems; ++i) {
1626 SDValue Arg = Mask.getOperand(i);
1627 if (Arg.getOpcode() == ISD::UNDEF) {
1628 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1630 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1631 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1633 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1634 DAG.getConstant(Idx, PtrVT)));
1636 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1637 DAG.getConstant(Idx - NumElems, PtrVT)));
1640 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1643 case TargetLowering::Promote: {
1644 // Change base type to a different vector type.
1645 MVT OVT = Node->getValueType(0);
1646 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1648 // Cast the two input vectors.
1649 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1650 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1652 // Convert the shuffle mask to the right # elements.
1653 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1654 assert(Tmp3.getNode() && "Shuffle not legal?");
1655 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1656 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1662 case ISD::EXTRACT_VECTOR_ELT:
1663 Tmp1 = Node->getOperand(0);
1664 Tmp2 = LegalizeOp(Node->getOperand(1));
1665 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1666 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1669 case ISD::EXTRACT_SUBVECTOR:
1670 Tmp1 = Node->getOperand(0);
1671 Tmp2 = LegalizeOp(Node->getOperand(1));
1672 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1673 Result = ExpandEXTRACT_SUBVECTOR(Result);
1676 case ISD::CONCAT_VECTORS: {
1677 // Use extract/insert/build vector for now. We might try to be
1678 // more clever later.
1679 MVT PtrVT = TLI.getPointerTy();
1680 SmallVector<SDValue, 8> Ops;
1681 unsigned NumOperands = Node->getNumOperands();
1682 for (unsigned i=0; i < NumOperands; ++i) {
1683 SDValue SubOp = Node->getOperand(i);
1684 MVT VVT = SubOp.getNode()->getValueType(0);
1685 MVT EltVT = VVT.getVectorElementType();
1686 unsigned NumSubElem = VVT.getVectorNumElements();
1687 for (unsigned j=0; j < NumSubElem; ++j) {
1688 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1689 DAG.getConstant(j, PtrVT)));
1692 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1693 &Ops[0], Ops.size()));
1696 case ISD::CALLSEQ_START: {
1697 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1699 // Recursively Legalize all of the inputs of the call end that do not lead
1700 // to this call start. This ensures that any libcalls that need be inserted
1701 // are inserted *before* the CALLSEQ_START.
1702 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1703 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1704 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1708 // Now that we legalized all of the inputs (which may have inserted
1709 // libcalls) create the new CALLSEQ_START node.
1710 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1712 // Merge in the last call, to ensure that this call start after the last
1714 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1715 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1716 Tmp1 = LegalizeOp(Tmp1);
1719 // Do not try to legalize the target-specific arguments (#1+).
1720 if (Tmp1 != Node->getOperand(0)) {
1721 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1723 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1726 // Remember that the CALLSEQ_START is legalized.
1727 AddLegalizedOperand(Op.getValue(0), Result);
1728 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1729 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1731 // Now that the callseq_start and all of the non-call nodes above this call
1732 // sequence have been legalized, legalize the call itself. During this
1733 // process, no libcalls can/will be inserted, guaranteeing that no calls
1735 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1736 // Note that we are selecting this call!
1737 LastCALLSEQ_END = SDValue(CallEnd, 0);
1738 IsLegalizingCall = true;
1740 // Legalize the call, starting from the CALLSEQ_END.
1741 LegalizeOp(LastCALLSEQ_END);
1742 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1745 case ISD::CALLSEQ_END:
1746 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1747 // will cause this node to be legalized as well as handling libcalls right.
1748 if (LastCALLSEQ_END.getNode() != Node) {
1749 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1750 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1751 assert(I != LegalizedNodes.end() &&
1752 "Legalizing the call start should have legalized this node!");
1756 // Otherwise, the call start has been legalized and everything is going
1757 // according to plan. Just legalize ourselves normally here.
1758 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1759 // Do not try to legalize the target-specific arguments (#1+), except for
1760 // an optional flag input.
1761 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1762 if (Tmp1 != Node->getOperand(0)) {
1763 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1765 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1768 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1769 if (Tmp1 != Node->getOperand(0) ||
1770 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1771 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1774 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1777 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1778 // This finishes up call legalization.
1779 IsLegalizingCall = false;
1781 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1782 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1783 if (Node->getNumValues() == 2)
1784 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1785 return Result.getValue(Op.getResNo());
1786 case ISD::DYNAMIC_STACKALLOC: {
1787 MVT VT = Node->getValueType(0);
1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1789 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1790 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1793 Tmp1 = Result.getValue(0);
1794 Tmp2 = Result.getValue(1);
1795 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1796 default: assert(0 && "This action is not supported yet!");
1797 case TargetLowering::Expand: {
1798 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1799 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1800 " not tell us which reg is the stack pointer!");
1801 SDValue Chain = Tmp1.getOperand(0);
1803 // Chain the dynamic stack allocation so that it doesn't modify the stack
1804 // pointer when other instructions are using the stack.
1805 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1807 SDValue Size = Tmp2.getOperand(1);
1808 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1809 Chain = SP.getValue(1);
1810 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1811 unsigned StackAlign =
1812 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1813 if (Align > StackAlign)
1814 SP = DAG.getNode(ISD::AND, VT, SP,
1815 DAG.getConstant(-(uint64_t)Align, VT));
1816 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1817 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1819 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1820 DAG.getIntPtrConstant(0, true), SDValue());
1822 Tmp1 = LegalizeOp(Tmp1);
1823 Tmp2 = LegalizeOp(Tmp2);
1826 case TargetLowering::Custom:
1827 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1828 if (Tmp3.getNode()) {
1829 Tmp1 = LegalizeOp(Tmp3);
1830 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1833 case TargetLowering::Legal:
1836 // Since this op produce two values, make sure to remember that we
1837 // legalized both of them.
1838 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1839 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1840 return Op.getResNo() ? Tmp2 : Tmp1;
1842 case ISD::INLINEASM: {
1843 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1844 bool Changed = false;
1845 // Legalize all of the operands of the inline asm, in case they are nodes
1846 // that need to be expanded or something. Note we skip the asm string and
1847 // all of the TargetConstant flags.
1848 SDValue Op = LegalizeOp(Ops[0]);
1849 Changed = Op != Ops[0];
1852 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1853 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1854 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1855 for (++i; NumVals; ++i, --NumVals) {
1856 SDValue Op = LegalizeOp(Ops[i]);
1865 Op = LegalizeOp(Ops.back());
1866 Changed |= Op != Ops.back();
1871 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1873 // INLINE asm returns a chain and flag, make sure to add both to the map.
1874 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1875 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1876 return Result.getValue(Op.getResNo());
1879 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1880 // Ensure that libcalls are emitted before a branch.
1881 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1882 Tmp1 = LegalizeOp(Tmp1);
1883 LastCALLSEQ_END = DAG.getEntryNode();
1885 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1889 // Ensure that libcalls are emitted before a branch.
1890 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1891 Tmp1 = LegalizeOp(Tmp1);
1892 LastCALLSEQ_END = DAG.getEntryNode();
1894 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1895 default: assert(0 && "Indirect target must be legal type (pointer)!");
1897 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1900 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1903 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1904 // Ensure that libcalls are emitted before a branch.
1905 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1906 Tmp1 = LegalizeOp(Tmp1);
1907 LastCALLSEQ_END = DAG.getEntryNode();
1909 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1910 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1912 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1913 default: assert(0 && "This action is not supported yet!");
1914 case TargetLowering::Legal: break;
1915 case TargetLowering::Custom:
1916 Tmp1 = TLI.LowerOperation(Result, DAG);
1917 if (Tmp1.getNode()) Result = Tmp1;
1919 case TargetLowering::Expand: {
1920 SDValue Chain = Result.getOperand(0);
1921 SDValue Table = Result.getOperand(1);
1922 SDValue Index = Result.getOperand(2);
1924 MVT PTy = TLI.getPointerTy();
1925 MachineFunction &MF = DAG.getMachineFunction();
1926 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1927 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1928 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1931 switch (EntrySize) {
1932 default: assert(0 && "Size of jump table not supported yet."); break;
1933 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1934 PseudoSourceValue::getJumpTable(), 0); break;
1935 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1936 PseudoSourceValue::getJumpTable(), 0); break;
1940 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1941 // For PIC, the sequence is:
1942 // BRIND(load(Jumptable + index) + RelocBase)
1943 // RelocBase can be JumpTable, GOT or some sort of global base.
1944 if (PTy != MVT::i32)
1945 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1946 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1947 TLI.getPICJumpTableRelocBase(Table, DAG));
1949 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1954 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1955 // Ensure that libcalls are emitted before a return.
1956 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1957 Tmp1 = LegalizeOp(Tmp1);
1958 LastCALLSEQ_END = DAG.getEntryNode();
1960 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1961 case Expand: assert(0 && "It's impossible to expand bools");
1963 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1966 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1968 // The top bits of the promoted condition are not necessarily zero, ensure
1969 // that the value is properly zero extended.
1970 unsigned BitWidth = Tmp2.getValueSizeInBits();
1971 if (!DAG.MaskedValueIsZero(Tmp2,
1972 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1973 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1978 // Basic block destination (Op#2) is always legal.
1979 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1981 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1982 default: assert(0 && "This action is not supported yet!");
1983 case TargetLowering::Legal: break;
1984 case TargetLowering::Custom:
1985 Tmp1 = TLI.LowerOperation(Result, DAG);
1986 if (Tmp1.getNode()) Result = Tmp1;
1988 case TargetLowering::Expand:
1989 // Expand brcond's setcc into its constituent parts and create a BR_CC
1991 if (Tmp2.getOpcode() == ISD::SETCC) {
1992 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1993 Tmp2.getOperand(0), Tmp2.getOperand(1),
1994 Node->getOperand(2));
1996 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1997 DAG.getCondCode(ISD::SETNE), Tmp2,
1998 DAG.getConstant(0, Tmp2.getValueType()),
1999 Node->getOperand(2));
2005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2006 // Ensure that libcalls are emitted before a branch.
2007 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2008 Tmp1 = LegalizeOp(Tmp1);
2009 Tmp2 = Node->getOperand(2); // LHS
2010 Tmp3 = Node->getOperand(3); // RHS
2011 Tmp4 = Node->getOperand(1); // CC
2013 LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
2014 LastCALLSEQ_END = DAG.getEntryNode();
2016 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2017 // the LHS is a legal SETCC itself. In this case, we need to compare
2018 // the result against zero to select between true and false values.
2019 if (Tmp3.getNode() == 0) {
2020 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2021 Tmp4 = DAG.getCondCode(ISD::SETNE);
2024 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2025 Node->getOperand(4));
2027 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2028 default: assert(0 && "Unexpected action for BR_CC!");
2029 case TargetLowering::Legal: break;
2030 case TargetLowering::Custom:
2031 Tmp4 = TLI.LowerOperation(Result, DAG);
2032 if (Tmp4.getNode()) Result = Tmp4;
2037 LoadSDNode *LD = cast<LoadSDNode>(Node);
2038 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2039 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2041 ISD::LoadExtType ExtType = LD->getExtensionType();
2042 if (ExtType == ISD::NON_EXTLOAD) {
2043 MVT VT = Node->getValueType(0);
2044 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2045 Tmp3 = Result.getValue(0);
2046 Tmp4 = Result.getValue(1);
2048 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2049 default: assert(0 && "This action is not supported yet!");
2050 case TargetLowering::Legal:
2051 // If this is an unaligned load and the target doesn't support it,
2053 if (!TLI.allowsUnalignedMemoryAccesses()) {
2054 unsigned ABIAlignment = TLI.getTargetData()->
2055 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2056 if (LD->getAlignment() < ABIAlignment){
2057 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2059 Tmp3 = Result.getOperand(0);
2060 Tmp4 = Result.getOperand(1);
2061 Tmp3 = LegalizeOp(Tmp3);
2062 Tmp4 = LegalizeOp(Tmp4);
2066 case TargetLowering::Custom:
2067 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2068 if (Tmp1.getNode()) {
2069 Tmp3 = LegalizeOp(Tmp1);
2070 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2073 case TargetLowering::Promote: {
2074 // Only promote a load of vector type to another.
2075 assert(VT.isVector() && "Cannot promote this load!");
2076 // Change base type to a different vector type.
2077 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2079 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2080 LD->getSrcValueOffset(),
2081 LD->isVolatile(), LD->getAlignment());
2082 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2083 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2087 // Since loads produce two values, make sure to remember that we
2088 // legalized both of them.
2089 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2090 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2091 return Op.getResNo() ? Tmp4 : Tmp3;
2093 MVT SrcVT = LD->getMemoryVT();
2094 unsigned SrcWidth = SrcVT.getSizeInBits();
2095 int SVOffset = LD->getSrcValueOffset();
2096 unsigned Alignment = LD->getAlignment();
2097 bool isVolatile = LD->isVolatile();
2099 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2100 // Some targets pretend to have an i1 loading operation, and actually
2101 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2102 // bits are guaranteed to be zero; it helps the optimizers understand
2103 // that these bits are zero. It is also useful for EXTLOAD, since it
2104 // tells the optimizers that those bits are undefined. It would be
2105 // nice to have an effective generic way of getting these benefits...
2106 // Until such a way is found, don't insist on promoting i1 here.
2107 (SrcVT != MVT::i1 ||
2108 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2109 // Promote to a byte-sized load if not loading an integral number of
2110 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2111 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2112 MVT NVT = MVT::getIntegerVT(NewWidth);
2115 // The extra bits are guaranteed to be zero, since we stored them that
2116 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2118 ISD::LoadExtType NewExtType =
2119 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2121 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2122 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2123 NVT, isVolatile, Alignment);
2125 Ch = Result.getValue(1); // The chain.
2127 if (ExtType == ISD::SEXTLOAD)
2128 // Having the top bits zero doesn't help when sign extending.
2129 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2130 Result, DAG.getValueType(SrcVT));
2131 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2132 // All the top bits are guaranteed to be zero - inform the optimizers.
2133 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2134 DAG.getValueType(SrcVT));
2136 Tmp1 = LegalizeOp(Result);
2137 Tmp2 = LegalizeOp(Ch);
2138 } else if (SrcWidth & (SrcWidth - 1)) {
2139 // If not loading a power-of-2 number of bits, expand as two loads.
2140 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2141 "Unsupported extload!");
2142 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2143 assert(RoundWidth < SrcWidth);
2144 unsigned ExtraWidth = SrcWidth - RoundWidth;
2145 assert(ExtraWidth < RoundWidth);
2146 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2147 "Load size not an integral number of bytes!");
2148 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2149 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2151 unsigned IncrementSize;
2153 if (TLI.isLittleEndian()) {
2154 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2155 // Load the bottom RoundWidth bits.
2156 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2157 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2160 // Load the remaining ExtraWidth bits.
2161 IncrementSize = RoundWidth / 8;
2162 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2163 DAG.getIntPtrConstant(IncrementSize));
2164 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2165 LD->getSrcValue(), SVOffset + IncrementSize,
2166 ExtraVT, isVolatile,
2167 MinAlign(Alignment, IncrementSize));
2169 // Build a factor node to remember that this load is independent of the
2171 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2174 // Move the top bits to the right place.
2175 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2176 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2178 // Join the hi and lo parts.
2179 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2181 // Big endian - avoid unaligned loads.
2182 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2183 // Load the top RoundWidth bits.
2184 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2185 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2188 // Load the remaining ExtraWidth bits.
2189 IncrementSize = RoundWidth / 8;
2190 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2191 DAG.getIntPtrConstant(IncrementSize));
2192 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2193 LD->getSrcValue(), SVOffset + IncrementSize,
2194 ExtraVT, isVolatile,
2195 MinAlign(Alignment, IncrementSize));
2197 // Build a factor node to remember that this load is independent of the
2199 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2202 // Move the top bits to the right place.
2203 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2204 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2206 // Join the hi and lo parts.
2207 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2210 Tmp1 = LegalizeOp(Result);
2211 Tmp2 = LegalizeOp(Ch);
2213 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2214 default: assert(0 && "This action is not supported yet!");
2215 case TargetLowering::Custom:
2218 case TargetLowering::Legal:
2219 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2220 Tmp1 = Result.getValue(0);
2221 Tmp2 = Result.getValue(1);
2224 Tmp3 = TLI.LowerOperation(Result, DAG);
2225 if (Tmp3.getNode()) {
2226 Tmp1 = LegalizeOp(Tmp3);
2227 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2230 // If this is an unaligned load and the target doesn't support it,
2232 if (!TLI.allowsUnalignedMemoryAccesses()) {
2233 unsigned ABIAlignment = TLI.getTargetData()->
2234 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2235 if (LD->getAlignment() < ABIAlignment){
2236 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2238 Tmp1 = Result.getOperand(0);
2239 Tmp2 = Result.getOperand(1);
2240 Tmp1 = LegalizeOp(Tmp1);
2241 Tmp2 = LegalizeOp(Tmp2);
2246 case TargetLowering::Expand:
2247 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2248 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2249 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2250 LD->getSrcValueOffset(),
2251 LD->isVolatile(), LD->getAlignment());
2252 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2253 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2254 Tmp2 = LegalizeOp(Load.getValue(1));
2257 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2258 // Turn the unsupported load into an EXTLOAD followed by an explicit
2259 // zero/sign extend inreg.
2260 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2261 Tmp1, Tmp2, LD->getSrcValue(),
2262 LD->getSrcValueOffset(), SrcVT,
2263 LD->isVolatile(), LD->getAlignment());
2265 if (ExtType == ISD::SEXTLOAD)
2266 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2267 Result, DAG.getValueType(SrcVT));
2269 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2270 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2271 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2276 // Since loads produce two values, make sure to remember that we legalized
2278 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2279 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2280 return Op.getResNo() ? Tmp2 : Tmp1;
2283 case ISD::EXTRACT_ELEMENT: {
2284 MVT OpTy = Node->getOperand(0).getValueType();
2285 switch (getTypeAction(OpTy)) {
2286 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2288 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2290 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2291 DAG.getConstant(OpTy.getSizeInBits()/2,
2292 TLI.getShiftAmountTy()));
2293 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2296 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2297 Node->getOperand(0));
2301 // Get both the low and high parts.
2302 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2303 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2304 Result = Tmp2; // 1 -> Hi
2306 Result = Tmp1; // 0 -> Lo
2312 case ISD::CopyToReg:
2313 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2315 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2316 "Register type must be legal!");
2317 // Legalize the incoming value (must be a legal type).
2318 Tmp2 = LegalizeOp(Node->getOperand(2));
2319 if (Node->getNumValues() == 1) {
2320 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2322 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2323 if (Node->getNumOperands() == 4) {
2324 Tmp3 = LegalizeOp(Node->getOperand(3));
2325 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2331 // Since this produces two values, make sure to remember that we legalized
2333 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2334 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2340 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2342 // Ensure that libcalls are emitted before a return.
2343 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2344 Tmp1 = LegalizeOp(Tmp1);
2345 LastCALLSEQ_END = DAG.getEntryNode();
2347 switch (Node->getNumOperands()) {
2349 Tmp2 = Node->getOperand(1);
2350 Tmp3 = Node->getOperand(2); // Signness
2351 switch (getTypeAction(Tmp2.getValueType())) {
2353 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2356 if (!Tmp2.getValueType().isVector()) {
2358 ExpandOp(Tmp2, Lo, Hi);
2360 // Big endian systems want the hi reg first.
2361 if (TLI.isBigEndian())
2365 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2367 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2368 Result = LegalizeOp(Result);
2370 SDNode *InVal = Tmp2.getNode();
2371 int InIx = Tmp2.getResNo();
2372 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2373 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2375 // Figure out if there is a simple type corresponding to this Vector
2376 // type. If so, convert to the vector type.
2377 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2378 if (TLI.isTypeLegal(TVT)) {
2379 // Turn this into a return of the vector type.
2380 Tmp2 = LegalizeOp(Tmp2);
2381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2382 } else if (NumElems == 1) {
2383 // Turn this into a return of the scalar type.
2384 Tmp2 = ScalarizeVectorOp(Tmp2);
2385 Tmp2 = LegalizeOp(Tmp2);
2386 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2388 // FIXME: Returns of gcc generic vectors smaller than a legal type
2389 // should be returned in integer registers!
2391 // The scalarized value type may not be legal, e.g. it might require
2392 // promotion or expansion. Relegalize the return.
2393 Result = LegalizeOp(Result);
2395 // FIXME: Returns of gcc generic vectors larger than a legal vector
2396 // type should be returned by reference!
2398 SplitVectorOp(Tmp2, Lo, Hi);
2399 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2400 Result = LegalizeOp(Result);
2405 Tmp2 = PromoteOp(Node->getOperand(1));
2406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2407 Result = LegalizeOp(Result);
2412 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2414 default: { // ret <values>
2415 SmallVector<SDValue, 8> NewValues;
2416 NewValues.push_back(Tmp1);
2417 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2418 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2420 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2421 NewValues.push_back(Node->getOperand(i+1));
2425 assert(!Node->getOperand(i).getValueType().isExtended() &&
2426 "FIXME: TODO: implement returning non-legal vector types!");
2427 ExpandOp(Node->getOperand(i), Lo, Hi);
2428 NewValues.push_back(Lo);
2429 NewValues.push_back(Node->getOperand(i+1));
2431 NewValues.push_back(Hi);
2432 NewValues.push_back(Node->getOperand(i+1));
2437 assert(0 && "Can't promote multiple return value yet!");
2440 if (NewValues.size() == Node->getNumOperands())
2441 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2443 Result = DAG.getNode(ISD::RET, MVT::Other,
2444 &NewValues[0], NewValues.size());
2449 if (Result.getOpcode() == ISD::RET) {
2450 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2451 default: assert(0 && "This action is not supported yet!");
2452 case TargetLowering::Legal: break;
2453 case TargetLowering::Custom:
2454 Tmp1 = TLI.LowerOperation(Result, DAG);
2455 if (Tmp1.getNode()) Result = Tmp1;
2461 StoreSDNode *ST = cast<StoreSDNode>(Node);
2462 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2463 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2464 int SVOffset = ST->getSrcValueOffset();
2465 unsigned Alignment = ST->getAlignment();
2466 bool isVolatile = ST->isVolatile();
2468 if (!ST->isTruncatingStore()) {
2469 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2470 // FIXME: We shouldn't do this for TargetConstantFP's.
2471 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2472 // to phase ordering between legalized code and the dag combiner. This
2473 // probably means that we need to integrate dag combiner and legalizer
2475 // We generally can't do this one for long doubles.
2476 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2477 if (CFP->getValueType(0) == MVT::f32 &&
2478 getTypeAction(MVT::i32) == Legal) {
2479 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2480 bitcastToAPInt().zextOrTrunc(32),
2482 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2483 SVOffset, isVolatile, Alignment);
2485 } else if (CFP->getValueType(0) == MVT::f64) {
2486 // If this target supports 64-bit registers, do a single 64-bit store.
2487 if (getTypeAction(MVT::i64) == Legal) {
2488 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2489 zextOrTrunc(64), MVT::i64);
2490 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2491 SVOffset, isVolatile, Alignment);
2493 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2494 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2495 // stores. If the target supports neither 32- nor 64-bits, this
2496 // xform is certainly not worth it.
2497 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2498 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2499 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2500 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2502 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2503 SVOffset, isVolatile, Alignment);
2504 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2505 DAG.getIntPtrConstant(4));
2506 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2507 isVolatile, MinAlign(Alignment, 4U));
2509 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2515 switch (getTypeAction(ST->getMemoryVT())) {
2517 Tmp3 = LegalizeOp(ST->getValue());
2518 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2521 MVT VT = Tmp3.getValueType();
2522 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2523 default: assert(0 && "This action is not supported yet!");
2524 case TargetLowering::Legal:
2525 // If this is an unaligned store and the target doesn't support it,
2527 if (!TLI.allowsUnalignedMemoryAccesses()) {
2528 unsigned ABIAlignment = TLI.getTargetData()->
2529 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2530 if (ST->getAlignment() < ABIAlignment)
2531 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2535 case TargetLowering::Custom:
2536 Tmp1 = TLI.LowerOperation(Result, DAG);
2537 if (Tmp1.getNode()) Result = Tmp1;
2539 case TargetLowering::Promote:
2540 assert(VT.isVector() && "Unknown legal promote case!");
2541 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2542 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2543 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2544 ST->getSrcValue(), SVOffset, isVolatile,
2551 if (!ST->getMemoryVT().isVector()) {
2552 // Truncate the value and store the result.
2553 Tmp3 = PromoteOp(ST->getValue());
2554 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2555 SVOffset, ST->getMemoryVT(),
2556 isVolatile, Alignment);
2559 // Fall thru to expand for vector
2561 unsigned IncrementSize = 0;
2564 // If this is a vector type, then we have to calculate the increment as
2565 // the product of the element size in bytes, and the number of elements
2566 // in the high half of the vector.
2567 if (ST->getValue().getValueType().isVector()) {
2568 SDNode *InVal = ST->getValue().getNode();
2569 int InIx = ST->getValue().getResNo();
2570 MVT InVT = InVal->getValueType(InIx);
2571 unsigned NumElems = InVT.getVectorNumElements();
2572 MVT EVT = InVT.getVectorElementType();
2574 // Figure out if there is a simple type corresponding to this Vector
2575 // type. If so, convert to the vector type.
2576 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2577 if (TLI.isTypeLegal(TVT)) {
2578 // Turn this into a normal store of the vector type.
2579 Tmp3 = LegalizeOp(ST->getValue());
2580 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2581 SVOffset, isVolatile, Alignment);
2582 Result = LegalizeOp(Result);
2584 } else if (NumElems == 1) {
2585 // Turn this into a normal store of the scalar type.
2586 Tmp3 = ScalarizeVectorOp(ST->getValue());
2587 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2588 SVOffset, isVolatile, Alignment);
2589 // The scalarized value type may not be legal, e.g. it might require
2590 // promotion or expansion. Relegalize the scalar store.
2591 Result = LegalizeOp(Result);
2594 // Check if we have widen this node with another value
2595 std::map<SDValue, SDValue>::iterator I =
2596 WidenNodes.find(ST->getValue());
2597 if (I != WidenNodes.end()) {
2598 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2602 SplitVectorOp(ST->getValue(), Lo, Hi);
2603 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2604 EVT.getSizeInBits()/8;
2608 ExpandOp(ST->getValue(), Lo, Hi);
2609 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2611 if (Hi.getNode() && TLI.isBigEndian())
2615 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2616 SVOffset, isVolatile, Alignment);
2618 if (Hi.getNode() == NULL) {
2619 // Must be int <-> float one-to-one expansion.
2624 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2625 DAG.getIntPtrConstant(IncrementSize));
2626 assert(isTypeLegal(Tmp2.getValueType()) &&
2627 "Pointers must be legal!");
2628 SVOffset += IncrementSize;
2629 Alignment = MinAlign(Alignment, IncrementSize);
2630 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2631 SVOffset, isVolatile, Alignment);
2632 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2637 switch (getTypeAction(ST->getValue().getValueType())) {
2639 Tmp3 = LegalizeOp(ST->getValue());
2642 if (!ST->getValue().getValueType().isVector()) {
2643 // We can promote the value, the truncstore will still take care of it.
2644 Tmp3 = PromoteOp(ST->getValue());
2647 // Vector case falls through to expand
2649 // Just store the low part. This may become a non-trunc store, so make
2650 // sure to use getTruncStore, not UpdateNodeOperands below.
2651 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2652 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2653 SVOffset, MVT::i8, isVolatile, Alignment);
2656 MVT StVT = ST->getMemoryVT();
2657 unsigned StWidth = StVT.getSizeInBits();
2659 if (StWidth != StVT.getStoreSizeInBits()) {
2660 // Promote to a byte-sized store with upper bits zero if not
2661 // storing an integral number of bytes. For example, promote
2662 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2663 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2664 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2665 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2666 SVOffset, NVT, isVolatile, Alignment);
2667 } else if (StWidth & (StWidth - 1)) {
2668 // If not storing a power-of-2 number of bits, expand as two stores.
2669 assert(StVT.isExtended() && !StVT.isVector() &&
2670 "Unsupported truncstore!");
2671 unsigned RoundWidth = 1 << Log2_32(StWidth);
2672 assert(RoundWidth < StWidth);
2673 unsigned ExtraWidth = StWidth - RoundWidth;
2674 assert(ExtraWidth < RoundWidth);
2675 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2676 "Store size not an integral number of bytes!");
2677 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2678 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2680 unsigned IncrementSize;
2682 if (TLI.isLittleEndian()) {
2683 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2684 // Store the bottom RoundWidth bits.
2685 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2687 isVolatile, Alignment);
2689 // Store the remaining ExtraWidth bits.
2690 IncrementSize = RoundWidth / 8;
2691 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2692 DAG.getIntPtrConstant(IncrementSize));
2693 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2694 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2695 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2696 SVOffset + IncrementSize, ExtraVT, isVolatile,
2697 MinAlign(Alignment, IncrementSize));
2699 // Big endian - avoid unaligned stores.
2700 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2701 // Store the top RoundWidth bits.
2702 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2703 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2704 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2705 RoundVT, isVolatile, Alignment);
2707 // Store the remaining ExtraWidth bits.
2708 IncrementSize = RoundWidth / 8;
2709 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2710 DAG.getIntPtrConstant(IncrementSize));
2711 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2712 SVOffset + IncrementSize, ExtraVT, isVolatile,
2713 MinAlign(Alignment, IncrementSize));
2716 // The order of the stores doesn't matter.
2717 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2719 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2720 Tmp2 != ST->getBasePtr())
2721 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2724 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2725 default: assert(0 && "This action is not supported yet!");
2726 case TargetLowering::Legal:
2727 // If this is an unaligned store and the target doesn't support it,
2729 if (!TLI.allowsUnalignedMemoryAccesses()) {
2730 unsigned ABIAlignment = TLI.getTargetData()->
2731 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2732 if (ST->getAlignment() < ABIAlignment)
2733 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2737 case TargetLowering::Custom:
2738 Result = TLI.LowerOperation(Result, DAG);
2741 // TRUNCSTORE:i16 i32 -> STORE i16
2742 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2743 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2744 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2745 isVolatile, Alignment);
2753 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2754 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2756 case ISD::STACKSAVE:
2757 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2758 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2759 Tmp1 = Result.getValue(0);
2760 Tmp2 = Result.getValue(1);
2762 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2763 default: assert(0 && "This action is not supported yet!");
2764 case TargetLowering::Legal: break;
2765 case TargetLowering::Custom:
2766 Tmp3 = TLI.LowerOperation(Result, DAG);
2767 if (Tmp3.getNode()) {
2768 Tmp1 = LegalizeOp(Tmp3);
2769 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2772 case TargetLowering::Expand:
2773 // Expand to CopyFromReg if the target set
2774 // StackPointerRegisterToSaveRestore.
2775 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2776 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2777 Node->getValueType(0));
2778 Tmp2 = Tmp1.getValue(1);
2780 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2781 Tmp2 = Node->getOperand(0);
2786 // Since stacksave produce two values, make sure to remember that we
2787 // legalized both of them.
2788 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2789 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2790 return Op.getResNo() ? Tmp2 : Tmp1;
2792 case ISD::STACKRESTORE:
2793 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2794 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2795 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2797 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2798 default: assert(0 && "This action is not supported yet!");
2799 case TargetLowering::Legal: break;
2800 case TargetLowering::Custom:
2801 Tmp1 = TLI.LowerOperation(Result, DAG);
2802 if (Tmp1.getNode()) Result = Tmp1;
2804 case TargetLowering::Expand:
2805 // Expand to CopyToReg if the target set
2806 // StackPointerRegisterToSaveRestore.
2807 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2808 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2816 case ISD::READCYCLECOUNTER:
2817 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2818 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2819 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2820 Node->getValueType(0))) {
2821 default: assert(0 && "This action is not supported yet!");
2822 case TargetLowering::Legal:
2823 Tmp1 = Result.getValue(0);
2824 Tmp2 = Result.getValue(1);
2826 case TargetLowering::Custom:
2827 Result = TLI.LowerOperation(Result, DAG);
2828 Tmp1 = LegalizeOp(Result.getValue(0));
2829 Tmp2 = LegalizeOp(Result.getValue(1));
2833 // Since rdcc produce two values, make sure to remember that we legalized
2835 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2836 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2840 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2841 case Expand: assert(0 && "It's impossible to expand bools");
2843 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2846 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2847 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2848 // Make sure the condition is either zero or one.
2849 unsigned BitWidth = Tmp1.getValueSizeInBits();
2850 if (!DAG.MaskedValueIsZero(Tmp1,
2851 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2852 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2856 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2857 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2859 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2861 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2862 default: assert(0 && "This action is not supported yet!");
2863 case TargetLowering::Legal: break;
2864 case TargetLowering::Custom: {
2865 Tmp1 = TLI.LowerOperation(Result, DAG);
2866 if (Tmp1.getNode()) Result = Tmp1;
2869 case TargetLowering::Expand:
2870 if (Tmp1.getOpcode() == ISD::SETCC) {
2871 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2873 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2875 Result = DAG.getSelectCC(Tmp1,
2876 DAG.getConstant(0, Tmp1.getValueType()),
2877 Tmp2, Tmp3, ISD::SETNE);
2880 case TargetLowering::Promote: {
2882 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2883 unsigned ExtOp, TruncOp;
2884 if (Tmp2.getValueType().isVector()) {
2885 ExtOp = ISD::BIT_CONVERT;
2886 TruncOp = ISD::BIT_CONVERT;
2887 } else if (Tmp2.getValueType().isInteger()) {
2888 ExtOp = ISD::ANY_EXTEND;
2889 TruncOp = ISD::TRUNCATE;
2891 ExtOp = ISD::FP_EXTEND;
2892 TruncOp = ISD::FP_ROUND;
2894 // Promote each of the values to the new type.
2895 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2896 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2897 // Perform the larger operation, then round down.
2898 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2899 if (TruncOp != ISD::FP_ROUND)
2900 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2902 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2903 DAG.getIntPtrConstant(0));
2908 case ISD::SELECT_CC: {
2909 Tmp1 = Node->getOperand(0); // LHS
2910 Tmp2 = Node->getOperand(1); // RHS
2911 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2912 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2913 SDValue CC = Node->getOperand(4);
2915 LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
2917 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2918 // the LHS is a legal SETCC itself. In this case, we need to compare
2919 // the result against zero to select between true and false values.
2920 if (Tmp2.getNode() == 0) {
2921 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2922 CC = DAG.getCondCode(ISD::SETNE);
2924 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2926 // Everything is legal, see if we should expand this op or something.
2927 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2928 default: assert(0 && "This action is not supported yet!");
2929 case TargetLowering::Legal: break;
2930 case TargetLowering::Custom:
2931 Tmp1 = TLI.LowerOperation(Result, DAG);
2932 if (Tmp1.getNode()) Result = Tmp1;
2938 Tmp1 = Node->getOperand(0);
2939 Tmp2 = Node->getOperand(1);
2940 Tmp3 = Node->getOperand(2);
2941 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
2943 // If we had to Expand the SetCC operands into a SELECT node, then it may
2944 // not always be possible to return a true LHS & RHS. In this case, just
2945 // return the value we legalized, returned in the LHS
2946 if (Tmp2.getNode() == 0) {
2951 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2952 default: assert(0 && "Cannot handle this action for SETCC yet!");
2953 case TargetLowering::Custom:
2956 case TargetLowering::Legal:
2957 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2959 Tmp4 = TLI.LowerOperation(Result, DAG);
2960 if (Tmp4.getNode()) Result = Tmp4;
2963 case TargetLowering::Promote: {
2964 // First step, figure out the appropriate operation to use.
2965 // Allow SETCC to not be supported for all legal data types
2966 // Mostly this targets FP
2967 MVT NewInTy = Node->getOperand(0).getValueType();
2968 MVT OldVT = NewInTy; OldVT = OldVT;
2970 // Scan for the appropriate larger type to use.
2972 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2974 assert(NewInTy.isInteger() == OldVT.isInteger() &&
2975 "Fell off of the edge of the integer world");
2976 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
2977 "Fell off of the edge of the floating point world");
2979 // If the target supports SETCC of this type, use it.
2980 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2983 if (NewInTy.isInteger())
2984 assert(0 && "Cannot promote Legal Integer SETCC yet");
2986 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2987 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2989 Tmp1 = LegalizeOp(Tmp1);
2990 Tmp2 = LegalizeOp(Tmp2);
2991 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2992 Result = LegalizeOp(Result);
2995 case TargetLowering::Expand:
2996 // Expand a setcc node into a select_cc of the same condition, lhs, and
2997 // rhs that selects between const 1 (true) and const 0 (false).
2998 MVT VT = Node->getValueType(0);
2999 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3000 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3006 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3007 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3008 SDValue CC = Node->getOperand(2);
3010 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3012 // Everything is legal, see if we should expand this op or something.
3013 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3014 default: assert(0 && "This action is not supported yet!");
3015 case TargetLowering::Legal: break;
3016 case TargetLowering::Custom:
3017 Tmp1 = TLI.LowerOperation(Result, DAG);
3018 if (Tmp1.getNode()) Result = Tmp1;
3024 case ISD::SHL_PARTS:
3025 case ISD::SRA_PARTS:
3026 case ISD::SRL_PARTS: {
3027 SmallVector<SDValue, 8> Ops;
3028 bool Changed = false;
3029 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3030 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3031 Changed |= Ops.back() != Node->getOperand(i);
3034 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3036 switch (TLI.getOperationAction(Node->getOpcode(),
3037 Node->getValueType(0))) {
3038 default: assert(0 && "This action is not supported yet!");
3039 case TargetLowering::Legal: break;
3040 case TargetLowering::Custom:
3041 Tmp1 = TLI.LowerOperation(Result, DAG);
3042 if (Tmp1.getNode()) {
3043 SDValue Tmp2, RetVal(0, 0);
3044 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3045 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3046 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3047 if (i == Op.getResNo())
3050 assert(RetVal.getNode() && "Illegal result number");
3056 // Since these produce multiple values, make sure to remember that we
3057 // legalized all of them.
3058 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3059 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3060 return Result.getValue(Op.getResNo());
3082 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3083 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3084 case Expand: assert(0 && "Not possible");
3086 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3089 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3093 if ((Node->getOpcode() == ISD::SHL ||
3094 Node->getOpcode() == ISD::SRL ||
3095 Node->getOpcode() == ISD::SRA) &&
3096 !Node->getValueType(0).isVector()) {
3097 if (TLI.getShiftAmountTy().bitsLT(Tmp2.getValueType()))
3098 Tmp2 = DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), Tmp2);
3099 else if (TLI.getShiftAmountTy().bitsGT(Tmp2.getValueType()))
3100 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), Tmp2);
3103 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3105 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3106 default: assert(0 && "BinOp legalize operation not supported");
3107 case TargetLowering::Legal: break;
3108 case TargetLowering::Custom:
3109 Tmp1 = TLI.LowerOperation(Result, DAG);
3110 if (Tmp1.getNode()) {
3114 // Fall through if the custom lower can't deal with the operation
3115 case TargetLowering::Expand: {
3116 MVT VT = Op.getValueType();
3118 // See if multiply or divide can be lowered using two-result operations.
3119 SDVTList VTs = DAG.getVTList(VT, VT);
3120 if (Node->getOpcode() == ISD::MUL) {
3121 // We just need the low half of the multiply; try both the signed
3122 // and unsigned forms. If the target supports both SMUL_LOHI and
3123 // UMUL_LOHI, form a preference by checking which forms of plain
3124 // MULH it supports.
3125 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3126 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3127 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3128 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3129 unsigned OpToUse = 0;
3130 if (HasSMUL_LOHI && !HasMULHS) {
3131 OpToUse = ISD::SMUL_LOHI;
3132 } else if (HasUMUL_LOHI && !HasMULHU) {
3133 OpToUse = ISD::UMUL_LOHI;
3134 } else if (HasSMUL_LOHI) {
3135 OpToUse = ISD::SMUL_LOHI;
3136 } else if (HasUMUL_LOHI) {
3137 OpToUse = ISD::UMUL_LOHI;
3140 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3144 if (Node->getOpcode() == ISD::MULHS &&
3145 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3146 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3150 if (Node->getOpcode() == ISD::MULHU &&
3151 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3152 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3156 if (Node->getOpcode() == ISD::SDIV &&
3157 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3158 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3162 if (Node->getOpcode() == ISD::UDIV &&
3163 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3164 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3169 // Check to see if we have a libcall for this operator.
3170 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3171 bool isSigned = false;
3172 switch (Node->getOpcode()) {
3175 if (VT == MVT::i32) {
3176 LC = Node->getOpcode() == ISD::UDIV
3177 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3178 isSigned = Node->getOpcode() == ISD::SDIV;
3183 LC = RTLIB::MUL_I32;
3186 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3187 RTLIB::POW_PPCF128);
3191 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3193 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3197 assert(Node->getValueType(0).isVector() &&
3198 "Cannot expand this binary operator!");
3199 // Expand the operation into a bunch of nasty scalar code.
3200 Result = LegalizeOp(UnrollVectorOp(Op));
3203 case TargetLowering::Promote: {
3204 switch (Node->getOpcode()) {
3205 default: assert(0 && "Do not know how to promote this BinOp!");
3209 MVT OVT = Node->getValueType(0);
3210 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3211 assert(OVT.isVector() && "Cannot promote this BinOp!");
3212 // Bit convert each of the values to the new type.
3213 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3214 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3215 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3216 // Bit convert the result back the original type.
3217 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3225 case ISD::SMUL_LOHI:
3226 case ISD::UMUL_LOHI:
3229 // These nodes will only be produced by target-specific lowering, so
3230 // they shouldn't be here if they aren't legal.
3231 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3232 "This must be legal!");
3234 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3235 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3236 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3239 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3240 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3241 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3242 case Expand: assert(0 && "Not possible");
3244 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3247 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3251 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3253 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3254 default: assert(0 && "Operation not supported");
3255 case TargetLowering::Custom:
3256 Tmp1 = TLI.LowerOperation(Result, DAG);
3257 if (Tmp1.getNode()) Result = Tmp1;
3259 case TargetLowering::Legal: break;
3260 case TargetLowering::Expand: {
3261 // If this target supports fabs/fneg natively and select is cheap,
3262 // do this efficiently.
3263 if (!TLI.isSelectExpensive() &&
3264 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3265 TargetLowering::Legal &&
3266 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3267 TargetLowering::Legal) {
3268 // Get the sign bit of the RHS.
3270 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3271 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3272 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3273 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3274 // Get the absolute value of the result.
3275 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3276 // Select between the nabs and abs value based on the sign bit of
3278 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3279 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3282 Result = LegalizeOp(Result);
3286 // Otherwise, do bitwise ops!
3288 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3289 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3290 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3291 Result = LegalizeOp(Result);
3299 Tmp1 = LegalizeOp(Node->getOperand(0));
3300 Tmp2 = LegalizeOp(Node->getOperand(1));
3301 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3302 Tmp3 = Result.getValue(0);
3303 Tmp4 = Result.getValue(1);
3305 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3306 default: assert(0 && "This action is not supported yet!");
3307 case TargetLowering::Legal:
3309 case TargetLowering::Custom:
3310 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3311 if (Tmp1.getNode() != NULL) {
3312 Tmp3 = LegalizeOp(Tmp1);
3313 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3317 // Since this produces two values, make sure to remember that we legalized
3319 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3320 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3321 return Op.getResNo() ? Tmp4 : Tmp3;
3325 Tmp1 = LegalizeOp(Node->getOperand(0));
3326 Tmp2 = LegalizeOp(Node->getOperand(1));
3327 Tmp3 = LegalizeOp(Node->getOperand(2));
3328 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3329 Tmp3 = Result.getValue(0);
3330 Tmp4 = Result.getValue(1);
3332 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3333 default: assert(0 && "This action is not supported yet!");
3334 case TargetLowering::Legal:
3336 case TargetLowering::Custom:
3337 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3338 if (Tmp1.getNode() != NULL) {
3339 Tmp3 = LegalizeOp(Tmp1);
3340 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3344 // Since this produces two values, make sure to remember that we legalized
3346 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3347 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3348 return Op.getResNo() ? Tmp4 : Tmp3;
3350 case ISD::BUILD_PAIR: {
3351 MVT PairTy = Node->getValueType(0);
3352 // TODO: handle the case where the Lo and Hi operands are not of legal type
3353 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3354 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3355 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3356 case TargetLowering::Promote:
3357 case TargetLowering::Custom:
3358 assert(0 && "Cannot promote/custom this yet!");
3359 case TargetLowering::Legal:
3360 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3361 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3363 case TargetLowering::Expand:
3364 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3365 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3366 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3367 DAG.getConstant(PairTy.getSizeInBits()/2,
3368 TLI.getShiftAmountTy()));
3369 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3378 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3379 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3381 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3382 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3383 case TargetLowering::Custom:
3386 case TargetLowering::Legal:
3387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3389 Tmp1 = TLI.LowerOperation(Result, DAG);
3390 if (Tmp1.getNode()) Result = Tmp1;
3393 case TargetLowering::Expand: {
3394 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3395 bool isSigned = DivOpc == ISD::SDIV;
3396 MVT VT = Node->getValueType(0);
3398 // See if remainder can be lowered using two-result operations.
3399 SDVTList VTs = DAG.getVTList(VT, VT);
3400 if (Node->getOpcode() == ISD::SREM &&
3401 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3402 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3405 if (Node->getOpcode() == ISD::UREM &&
3406 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3407 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3411 if (VT.isInteger()) {
3412 if (TLI.getOperationAction(DivOpc, VT) ==
3413 TargetLowering::Legal) {
3415 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3416 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3417 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3418 } else if (VT.isVector()) {
3419 Result = LegalizeOp(UnrollVectorOp(Op));
3421 assert(VT == MVT::i32 &&
3422 "Cannot expand this binary operator!");
3423 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3424 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3426 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3429 assert(VT.isFloatingPoint() &&
3430 "remainder op must have integer or floating-point type");
3431 if (VT.isVector()) {
3432 Result = LegalizeOp(UnrollVectorOp(Op));
3434 // Floating point mod -> fmod libcall.
3435 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3436 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3438 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3446 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3447 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3449 MVT VT = Node->getValueType(0);
3450 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3451 default: assert(0 && "This action is not supported yet!");
3452 case TargetLowering::Custom:
3455 case TargetLowering::Legal:
3456 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3457 Result = Result.getValue(0);
3458 Tmp1 = Result.getValue(1);
3461 Tmp2 = TLI.LowerOperation(Result, DAG);
3462 if (Tmp2.getNode()) {
3463 Result = LegalizeOp(Tmp2);
3464 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3468 case TargetLowering::Expand: {
3469 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3470 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3471 // Increment the pointer, VAList, to the next vaarg
3472 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3473 DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()),
3474 TLI.getPointerTy()));
3475 // Store the incremented VAList to the legalized pointer
3476 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3477 // Load the actual argument out of the pointer VAList
3478 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3479 Tmp1 = LegalizeOp(Result.getValue(1));
3480 Result = LegalizeOp(Result);
3484 // Since VAARG produces two values, make sure to remember that we
3485 // legalized both of them.
3486 AddLegalizedOperand(SDValue(Node, 0), Result);
3487 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3488 return Op.getResNo() ? Tmp1 : Result;
3492 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3493 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3494 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3496 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3497 default: assert(0 && "This action is not supported yet!");
3498 case TargetLowering::Custom:
3501 case TargetLowering::Legal:
3502 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3503 Node->getOperand(3), Node->getOperand(4));
3505 Tmp1 = TLI.LowerOperation(Result, DAG);
3506 if (Tmp1.getNode()) Result = Tmp1;
3509 case TargetLowering::Expand:
3510 // This defaults to loading a pointer from the input and storing it to the
3511 // output, returning the chain.
3512 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3513 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3514 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3515 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3521 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3522 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3524 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3525 default: assert(0 && "This action is not supported yet!");
3526 case TargetLowering::Custom:
3529 case TargetLowering::Legal:
3530 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3532 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3533 if (Tmp1.getNode()) Result = Tmp1;
3536 case TargetLowering::Expand:
3537 Result = Tmp1; // Default to a no-op, return the chain
3543 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3544 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3546 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3548 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3549 default: assert(0 && "This action is not supported yet!");
3550 case TargetLowering::Legal: break;
3551 case TargetLowering::Custom:
3552 Tmp1 = TLI.LowerOperation(Result, DAG);
3553 if (Tmp1.getNode()) Result = Tmp1;
3560 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3561 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3562 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3563 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3565 assert(0 && "ROTL/ROTR legalize operation not supported");
3567 case TargetLowering::Legal:
3569 case TargetLowering::Custom:
3570 Tmp1 = TLI.LowerOperation(Result, DAG);
3571 if (Tmp1.getNode()) Result = Tmp1;
3573 case TargetLowering::Promote:
3574 assert(0 && "Do not know how to promote ROTL/ROTR");
3576 case TargetLowering::Expand:
3577 assert(0 && "Do not know how to expand ROTL/ROTR");
3583 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3584 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3585 case TargetLowering::Custom:
3586 assert(0 && "Cannot custom legalize this yet!");
3587 case TargetLowering::Legal:
3588 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3590 case TargetLowering::Promote: {
3591 MVT OVT = Tmp1.getValueType();
3592 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3593 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3595 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3596 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3597 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3598 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3601 case TargetLowering::Expand:
3602 Result = ExpandBSWAP(Tmp1);
3610 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3611 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3612 case TargetLowering::Custom:
3613 case TargetLowering::Legal:
3614 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3615 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3616 TargetLowering::Custom) {
3617 Tmp1 = TLI.LowerOperation(Result, DAG);
3618 if (Tmp1.getNode()) {
3623 case TargetLowering::Promote: {
3624 MVT OVT = Tmp1.getValueType();
3625 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3627 // Zero extend the argument.
3628 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3629 // Perform the larger operation, then subtract if needed.
3630 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3631 switch (Node->getOpcode()) {
3636 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3637 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3638 DAG.getConstant(NVT.getSizeInBits(), NVT),
3640 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3641 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3644 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3645 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3646 DAG.getConstant(NVT.getSizeInBits() -
3647 OVT.getSizeInBits(), NVT));
3652 case TargetLowering::Expand:
3653 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3673 case ISD::FNEARBYINT:
3674 Tmp1 = LegalizeOp(Node->getOperand(0));
3675 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3676 case TargetLowering::Promote:
3677 case TargetLowering::Custom:
3680 case TargetLowering::Legal:
3681 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3683 Tmp1 = TLI.LowerOperation(Result, DAG);
3684 if (Tmp1.getNode()) Result = Tmp1;
3687 case TargetLowering::Expand:
3688 switch (Node->getOpcode()) {
3689 default: assert(0 && "Unreachable!");
3691 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3692 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3693 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3696 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3697 MVT VT = Node->getValueType(0);
3698 Tmp2 = DAG.getConstantFP(0.0, VT);
3699 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3701 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3702 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3717 case ISD::FNEARBYINT: {
3718 MVT VT = Node->getValueType(0);
3720 // Expand unsupported unary vector operators by unrolling them.
3721 if (VT.isVector()) {
3722 Result = LegalizeOp(UnrollVectorOp(Op));
3726 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3727 switch(Node->getOpcode()) {
3729 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3730 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3733 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3734 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3737 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3738 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3741 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3742 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3745 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3746 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3749 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3750 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3753 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3754 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3757 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3758 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3761 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3762 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3765 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3766 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3769 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3770 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3773 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3774 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3776 case ISD::FNEARBYINT:
3777 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3778 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3781 default: assert(0 && "Unreachable!");
3784 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3792 MVT VT = Node->getValueType(0);
3794 // Expand unsupported unary vector operators by unrolling them.
3795 if (VT.isVector()) {
3796 Result = LegalizeOp(UnrollVectorOp(Op));
3800 // We always lower FPOWI into a libcall. No target support for it yet.
3801 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3802 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3804 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3807 case ISD::BIT_CONVERT:
3808 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3809 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3810 Node->getValueType(0));
3811 } else if (Op.getOperand(0).getValueType().isVector()) {
3812 // The input has to be a vector type, we have to either scalarize it, pack
3813 // it, or convert it based on whether the input vector type is legal.
3814 SDNode *InVal = Node->getOperand(0).getNode();
3815 int InIx = Node->getOperand(0).getResNo();
3816 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3817 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3819 // Figure out if there is a simple type corresponding to this Vector
3820 // type. If so, convert to the vector type.
3821 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3822 if (TLI.isTypeLegal(TVT)) {
3823 // Turn this into a bit convert of the vector input.
3824 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3825 LegalizeOp(Node->getOperand(0)));
3827 } else if (NumElems == 1) {
3828 // Turn this into a bit convert of the scalar input.
3829 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3830 ScalarizeVectorOp(Node->getOperand(0)));
3833 // FIXME: UNIMP! Store then reload
3834 assert(0 && "Cast from unsupported vector type not implemented yet!");
3837 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3838 Node->getOperand(0).getValueType())) {
3839 default: assert(0 && "Unknown operation action!");
3840 case TargetLowering::Expand:
3841 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3842 Node->getValueType(0));
3844 case TargetLowering::Legal:
3845 Tmp1 = LegalizeOp(Node->getOperand(0));
3846 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3851 case ISD::CONVERT_RNDSAT: {
3852 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3854 default: assert(0 && "Unknown cvt code!");
3865 SDValue DTyOp = Node->getOperand(1);
3866 SDValue STyOp = Node->getOperand(2);
3867 SDValue RndOp = Node->getOperand(3);
3868 SDValue SatOp = Node->getOperand(4);
3869 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3870 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3872 Tmp1 = LegalizeOp(Node->getOperand(0));
3873 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3875 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3876 TargetLowering::Custom) {
3877 Tmp1 = TLI.LowerOperation(Result, DAG);
3878 if (Tmp1.getNode()) Result = Tmp1;
3882 Result = PromoteOp(Node->getOperand(0));
3883 // For FP, make Op1 a i32
3885 Result = DAG.getConvertRndSat(Result.getValueType(), Result,
3886 DTyOp, STyOp, RndOp, SatOp, CvtCode);
3891 } // end switch CvtCode
3894 // Conversion operators. The source and destination have different types.
3895 case ISD::SINT_TO_FP:
3896 case ISD::UINT_TO_FP: {
3897 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3898 Result = LegalizeINT_TO_FP(Result, isSigned,
3899 Node->getValueType(0), Node->getOperand(0));
3903 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3905 Tmp1 = LegalizeOp(Node->getOperand(0));
3906 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3907 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
3908 case TargetLowering::Custom:
3911 case TargetLowering::Legal:
3912 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3914 Tmp1 = TLI.LowerOperation(Result, DAG);
3915 if (Tmp1.getNode()) Result = Tmp1;
3921 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3923 // Since the result is legal, we should just be able to truncate the low
3924 // part of the source.
3925 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3928 Result = PromoteOp(Node->getOperand(0));
3929 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3934 case ISD::FP_TO_SINT:
3935 case ISD::FP_TO_UINT:
3936 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3938 Tmp1 = LegalizeOp(Node->getOperand(0));
3940 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3941 default: assert(0 && "Unknown operation action!");
3942 case TargetLowering::Custom:
3945 case TargetLowering::Legal:
3946 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3948 Tmp1 = TLI.LowerOperation(Result, DAG);
3949 if (Tmp1.getNode()) Result = Tmp1;
3952 case TargetLowering::Promote:
3953 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3954 Node->getOpcode() == ISD::FP_TO_SINT);
3956 case TargetLowering::Expand:
3957 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3958 SDValue True, False;
3959 MVT VT = Node->getOperand(0).getValueType();
3960 MVT NVT = Node->getValueType(0);
3961 const uint64_t zero[] = {0, 0};
3962 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
3963 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3964 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3965 Tmp2 = DAG.getConstantFP(apf, VT);
3966 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3967 Node->getOperand(0), Tmp2, ISD::SETLT);
3968 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3969 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3970 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3972 False = DAG.getNode(ISD::XOR, NVT, False,
3973 DAG.getConstant(x, NVT));
3974 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3977 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3983 MVT VT = Op.getValueType();
3984 MVT OVT = Node->getOperand(0).getValueType();
3985 // Convert ppcf128 to i32
3986 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3987 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3988 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3989 Node->getOperand(0), DAG.getValueType(MVT::f64));
3990 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3991 DAG.getIntPtrConstant(1));
3992 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3994 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3995 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3996 Tmp2 = DAG.getConstantFP(apf, OVT);
3997 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3998 // FIXME: generated code sucks.
3999 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
4000 DAG.getNode(ISD::ADD, MVT::i32,
4001 DAG.getNode(ISD::FP_TO_SINT, VT,
4002 DAG.getNode(ISD::FSUB, OVT,
4003 Node->getOperand(0), Tmp2)),
4004 DAG.getConstant(0x80000000, MVT::i32)),
4005 DAG.getNode(ISD::FP_TO_SINT, VT,
4006 Node->getOperand(0)),
4007 DAG.getCondCode(ISD::SETGE));
4011 // Convert f32 / f64 to i32 / i64 / i128.
4012 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4013 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4014 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4016 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4020 Tmp1 = PromoteOp(Node->getOperand(0));
4021 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4022 Result = LegalizeOp(Result);
4027 case ISD::FP_EXTEND: {
4028 MVT DstVT = Op.getValueType();
4029 MVT SrcVT = Op.getOperand(0).getValueType();
4030 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4031 // The only other way we can lower this is to turn it into a STORE,
4032 // LOAD pair, targetting a temporary location (a stack slot).
4033 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
4036 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4037 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4039 Tmp1 = LegalizeOp(Node->getOperand(0));
4040 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4043 Tmp1 = PromoteOp(Node->getOperand(0));
4044 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4049 case ISD::FP_ROUND: {
4050 MVT DstVT = Op.getValueType();
4051 MVT SrcVT = Op.getOperand(0).getValueType();
4052 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4053 if (SrcVT == MVT::ppcf128) {
4055 ExpandOp(Node->getOperand(0), Lo, Result);
4056 // Round it the rest of the way (e.g. to f32) if needed.
4057 if (DstVT!=MVT::f64)
4058 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4061 // The only other way we can lower this is to turn it into a STORE,
4062 // LOAD pair, targetting a temporary location (a stack slot).
4063 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4066 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4067 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4069 Tmp1 = LegalizeOp(Node->getOperand(0));
4070 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4073 Tmp1 = PromoteOp(Node->getOperand(0));
4074 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4075 Node->getOperand(1));
4080 case ISD::ANY_EXTEND:
4081 case ISD::ZERO_EXTEND:
4082 case ISD::SIGN_EXTEND:
4083 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4084 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4086 Tmp1 = LegalizeOp(Node->getOperand(0));
4087 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4088 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4089 TargetLowering::Custom) {
4090 Tmp1 = TLI.LowerOperation(Result, DAG);
4091 if (Tmp1.getNode()) Result = Tmp1;
4095 switch (Node->getOpcode()) {
4096 case ISD::ANY_EXTEND:
4097 Tmp1 = PromoteOp(Node->getOperand(0));
4098 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4100 case ISD::ZERO_EXTEND:
4101 Result = PromoteOp(Node->getOperand(0));
4102 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4103 Result = DAG.getZeroExtendInReg(Result,
4104 Node->getOperand(0).getValueType());
4106 case ISD::SIGN_EXTEND:
4107 Result = PromoteOp(Node->getOperand(0));
4108 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4109 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4111 DAG.getValueType(Node->getOperand(0).getValueType()));
4116 case ISD::FP_ROUND_INREG:
4117 case ISD::SIGN_EXTEND_INREG: {
4118 Tmp1 = LegalizeOp(Node->getOperand(0));
4119 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4121 // If this operation is not supported, convert it to a shl/shr or load/store
4123 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4124 default: assert(0 && "This action not supported for this op yet!");
4125 case TargetLowering::Legal:
4126 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4128 case TargetLowering::Expand:
4129 // If this is an integer extend and shifts are supported, do that.
4130 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4131 // NOTE: we could fall back on load/store here too for targets without
4132 // SAR. However, it is doubtful that any exist.
4133 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4134 ExtraVT.getSizeInBits();
4135 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4136 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4137 Node->getOperand(0), ShiftCst);
4138 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4140 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4141 // The only way we can lower this is to turn it into a TRUNCSTORE,
4142 // EXTLOAD pair, targetting a temporary location (a stack slot).
4144 // NOTE: there is a choice here between constantly creating new stack
4145 // slots and always reusing the same one. We currently always create
4146 // new ones, as reuse may inhibit scheduling.
4147 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4148 Node->getValueType(0));
4150 assert(0 && "Unknown op");
4156 case ISD::TRAMPOLINE: {
4158 for (unsigned i = 0; i != 6; ++i)
4159 Ops[i] = LegalizeOp(Node->getOperand(i));
4160 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4161 // The only option for this node is to custom lower it.
4162 Result = TLI.LowerOperation(Result, DAG);
4163 assert(Result.getNode() && "Should always custom lower!");
4165 // Since trampoline produces two values, make sure to remember that we
4166 // legalized both of them.
4167 Tmp1 = LegalizeOp(Result.getValue(1));
4168 Result = LegalizeOp(Result);
4169 AddLegalizedOperand(SDValue(Node, 0), Result);
4170 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4171 return Op.getResNo() ? Tmp1 : Result;
4173 case ISD::FLT_ROUNDS_: {
4174 MVT VT = Node->getValueType(0);
4175 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4176 default: assert(0 && "This action not supported for this op yet!");
4177 case TargetLowering::Custom:
4178 Result = TLI.LowerOperation(Op, DAG);
4179 if (Result.getNode()) break;
4181 case TargetLowering::Legal:
4182 // If this operation is not supported, lower it to constant 1
4183 Result = DAG.getConstant(1, VT);
4189 MVT VT = Node->getValueType(0);
4190 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4191 default: assert(0 && "This action not supported for this op yet!");
4192 case TargetLowering::Legal:
4193 Tmp1 = LegalizeOp(Node->getOperand(0));
4194 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4196 case TargetLowering::Custom:
4197 Result = TLI.LowerOperation(Op, DAG);
4198 if (Result.getNode()) break;
4200 case TargetLowering::Expand:
4201 // If this operation is not supported, lower it to 'abort()' call
4202 Tmp1 = LegalizeOp(Node->getOperand(0));
4203 TargetLowering::ArgListTy Args;
4204 std::pair<SDValue,SDValue> CallResult =
4205 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4206 false, false, false, false, CallingConv::C, false,
4207 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4209 Result = CallResult.second;
4216 MVT VT = Node->getValueType(0);
4217 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4218 default: assert(0 && "This action not supported for this op yet!");
4219 case TargetLowering::Custom:
4220 Result = TLI.LowerOperation(Op, DAG);
4221 if (Result.getNode()) break;
4223 case TargetLowering::Legal: {
4224 SDValue LHS = LegalizeOp(Node->getOperand(0));
4225 SDValue RHS = LegalizeOp(Node->getOperand(1));
4227 SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
4228 MVT OType = Node->getValueType(1);
4230 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4232 // LHSSign -> LHS >= 0
4233 // RHSSign -> RHS >= 0
4234 // SumSign -> Sum >= 0
4236 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4238 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4239 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4240 SDValue SignsEq = DAG.getSetCC(OType, LHSSign, RHSSign, ISD::SETEQ);
4242 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4243 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4245 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsEq, SumSignNE);
4247 MVT ValueVTs[] = { LHS.getValueType(), OType };
4248 SDValue Ops[] = { Sum, Cmp };
4250 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4252 SDNode *RNode = Result.getNode();
4253 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4254 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4262 MVT VT = Node->getValueType(0);
4263 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4264 default: assert(0 && "This action not supported for this op yet!");
4265 case TargetLowering::Custom:
4266 Result = TLI.LowerOperation(Op, DAG);
4267 if (Result.getNode()) break;
4269 case TargetLowering::Legal: {
4270 SDValue LHS = LegalizeOp(Node->getOperand(0));
4271 SDValue RHS = LegalizeOp(Node->getOperand(1));
4273 SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
4274 MVT OType = Node->getValueType(1);
4275 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS, ISD::SETULT);
4277 MVT ValueVTs[] = { LHS.getValueType(), OType };
4278 SDValue Ops[] = { Sum, Cmp };
4280 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4282 SDNode *RNode = Result.getNode();
4283 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4284 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4293 assert(Result.getValueType() == Op.getValueType() &&
4294 "Bad legalization!");
4296 // Make sure that the generated code is itself legal.
4298 Result = LegalizeOp(Result);
4300 // Note that LegalizeOp may be reentered even from single-use nodes, which
4301 // means that we always must cache transformed nodes.
4302 AddLegalizedOperand(Op, Result);
4306 /// PromoteOp - Given an operation that produces a value in an invalid type,
4307 /// promote it to compute the value into a larger type. The produced value will
4308 /// have the correct bits for the low portion of the register, but no guarantee
4309 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4310 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4311 MVT VT = Op.getValueType();
4312 MVT NVT = TLI.getTypeToTransformTo(VT);
4313 assert(getTypeAction(VT) == Promote &&
4314 "Caller should expand or legalize operands that are not promotable!");
4315 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4316 "Cannot promote to smaller type!");
4318 SDValue Tmp1, Tmp2, Tmp3;
4320 SDNode *Node = Op.getNode();
4322 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4323 if (I != PromotedNodes.end()) return I->second;
4325 switch (Node->getOpcode()) {
4326 case ISD::CopyFromReg:
4327 assert(0 && "CopyFromReg must be legal!");
4330 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4332 assert(0 && "Do not know how to promote this operator!");
4335 Result = DAG.getNode(ISD::UNDEF, NVT);
4339 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4341 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4342 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4344 case ISD::ConstantFP:
4345 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4346 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4350 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4351 && "SetCC type is not legal??");
4352 Result = DAG.getNode(ISD::SETCC,
4353 TLI.getSetCCResultType(Node->getOperand(0)),
4354 Node->getOperand(0), Node->getOperand(1),
4355 Node->getOperand(2));
4359 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4361 Result = LegalizeOp(Node->getOperand(0));
4362 assert(Result.getValueType().bitsGE(NVT) &&
4363 "This truncation doesn't make sense!");
4364 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4365 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4368 // The truncation is not required, because we don't guarantee anything
4369 // about high bits anyway.
4370 Result = PromoteOp(Node->getOperand(0));
4373 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4374 // Truncate the low part of the expanded value to the result type
4375 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4378 case ISD::SIGN_EXTEND:
4379 case ISD::ZERO_EXTEND:
4380 case ISD::ANY_EXTEND:
4381 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4382 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4384 // Input is legal? Just do extend all the way to the larger type.
4385 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4388 // Promote the reg if it's smaller.
4389 Result = PromoteOp(Node->getOperand(0));
4390 // The high bits are not guaranteed to be anything. Insert an extend.
4391 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4392 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4393 DAG.getValueType(Node->getOperand(0).getValueType()));
4394 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4395 Result = DAG.getZeroExtendInReg(Result,
4396 Node->getOperand(0).getValueType());
4400 case ISD::CONVERT_RNDSAT: {
4401 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4402 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4403 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4404 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4405 "can only promote integers");
4406 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4407 Node->getOperand(1), Node->getOperand(2),
4408 Node->getOperand(3), Node->getOperand(4),
4413 case ISD::BIT_CONVERT:
4414 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4415 Node->getValueType(0));
4416 Result = PromoteOp(Result);
4419 case ISD::FP_EXTEND:
4420 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4422 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4423 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4424 case Promote: assert(0 && "Unreachable with 2 FP types!");
4426 if (Node->getConstantOperandVal(1) == 0) {
4427 // Input is legal? Do an FP_ROUND_INREG.
4428 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4429 DAG.getValueType(VT));
4431 // Just remove the truncate, it isn't affecting the value.
4432 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4433 Node->getOperand(1));
4438 case ISD::SINT_TO_FP:
4439 case ISD::UINT_TO_FP:
4440 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4442 // No extra round required here.
4443 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4447 Result = PromoteOp(Node->getOperand(0));
4448 if (Node->getOpcode() == ISD::SINT_TO_FP)
4449 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4451 DAG.getValueType(Node->getOperand(0).getValueType()));
4453 Result = DAG.getZeroExtendInReg(Result,
4454 Node->getOperand(0).getValueType());
4455 // No extra round required here.
4456 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4459 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4460 Node->getOperand(0));
4461 // Round if we cannot tolerate excess precision.
4462 if (NoExcessFPPrecision)
4463 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4464 DAG.getValueType(VT));
4469 case ISD::SIGN_EXTEND_INREG:
4470 Result = PromoteOp(Node->getOperand(0));
4471 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4472 Node->getOperand(1));
4474 case ISD::FP_TO_SINT:
4475 case ISD::FP_TO_UINT:
4476 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4479 Tmp1 = Node->getOperand(0);
4482 // The input result is prerounded, so we don't have to do anything
4484 Tmp1 = PromoteOp(Node->getOperand(0));
4487 // If we're promoting a UINT to a larger size, check to see if the new node
4488 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4489 // we can use that instead. This allows us to generate better code for
4490 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4491 // legal, such as PowerPC.
4492 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4493 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4494 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4495 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4496 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4498 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4504 Tmp1 = PromoteOp(Node->getOperand(0));
4505 assert(Tmp1.getValueType() == NVT);
4506 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4507 // NOTE: we do not have to do any extra rounding here for
4508 // NoExcessFPPrecision, because we know the input will have the appropriate
4509 // precision, and these operations don't modify precision at all.
4524 case ISD::FNEARBYINT:
4525 Tmp1 = PromoteOp(Node->getOperand(0));
4526 assert(Tmp1.getValueType() == NVT);
4527 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4528 if (NoExcessFPPrecision)
4529 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4530 DAG.getValueType(VT));
4535 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4536 // directly as well, which may be better.
4537 Tmp1 = PromoteOp(Node->getOperand(0));
4538 Tmp2 = Node->getOperand(1);
4539 if (Node->getOpcode() == ISD::FPOW)
4540 Tmp2 = PromoteOp(Tmp2);
4541 assert(Tmp1.getValueType() == NVT);
4542 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4543 if (NoExcessFPPrecision)
4544 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4545 DAG.getValueType(VT));
4549 case ISD::ATOMIC_CMP_SWAP_8:
4550 case ISD::ATOMIC_CMP_SWAP_16:
4551 case ISD::ATOMIC_CMP_SWAP_32:
4552 case ISD::ATOMIC_CMP_SWAP_64: {
4553 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4554 Tmp2 = PromoteOp(Node->getOperand(2));
4555 Tmp3 = PromoteOp(Node->getOperand(3));
4556 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4557 AtomNode->getBasePtr(), Tmp2, Tmp3,
4558 AtomNode->getSrcValue(),
4559 AtomNode->getAlignment());
4560 // Remember that we legalized the chain.
4561 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4564 case ISD::ATOMIC_LOAD_ADD_8:
4565 case ISD::ATOMIC_LOAD_SUB_8:
4566 case ISD::ATOMIC_LOAD_AND_8:
4567 case ISD::ATOMIC_LOAD_OR_8:
4568 case ISD::ATOMIC_LOAD_XOR_8:
4569 case ISD::ATOMIC_LOAD_NAND_8:
4570 case ISD::ATOMIC_LOAD_MIN_8:
4571 case ISD::ATOMIC_LOAD_MAX_8:
4572 case ISD::ATOMIC_LOAD_UMIN_8:
4573 case ISD::ATOMIC_LOAD_UMAX_8:
4574 case ISD::ATOMIC_SWAP_8:
4575 case ISD::ATOMIC_LOAD_ADD_16:
4576 case ISD::ATOMIC_LOAD_SUB_16:
4577 case ISD::ATOMIC_LOAD_AND_16:
4578 case ISD::ATOMIC_LOAD_OR_16:
4579 case ISD::ATOMIC_LOAD_XOR_16:
4580 case ISD::ATOMIC_LOAD_NAND_16:
4581 case ISD::ATOMIC_LOAD_MIN_16:
4582 case ISD::ATOMIC_LOAD_MAX_16:
4583 case ISD::ATOMIC_LOAD_UMIN_16:
4584 case ISD::ATOMIC_LOAD_UMAX_16:
4585 case ISD::ATOMIC_SWAP_16:
4586 case ISD::ATOMIC_LOAD_ADD_32:
4587 case ISD::ATOMIC_LOAD_SUB_32:
4588 case ISD::ATOMIC_LOAD_AND_32:
4589 case ISD::ATOMIC_LOAD_OR_32:
4590 case ISD::ATOMIC_LOAD_XOR_32:
4591 case ISD::ATOMIC_LOAD_NAND_32:
4592 case ISD::ATOMIC_LOAD_MIN_32:
4593 case ISD::ATOMIC_LOAD_MAX_32:
4594 case ISD::ATOMIC_LOAD_UMIN_32:
4595 case ISD::ATOMIC_LOAD_UMAX_32:
4596 case ISD::ATOMIC_SWAP_32:
4597 case ISD::ATOMIC_LOAD_ADD_64:
4598 case ISD::ATOMIC_LOAD_SUB_64:
4599 case ISD::ATOMIC_LOAD_AND_64:
4600 case ISD::ATOMIC_LOAD_OR_64:
4601 case ISD::ATOMIC_LOAD_XOR_64:
4602 case ISD::ATOMIC_LOAD_NAND_64:
4603 case ISD::ATOMIC_LOAD_MIN_64:
4604 case ISD::ATOMIC_LOAD_MAX_64:
4605 case ISD::ATOMIC_LOAD_UMIN_64:
4606 case ISD::ATOMIC_LOAD_UMAX_64:
4607 case ISD::ATOMIC_SWAP_64: {
4608 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4609 Tmp2 = PromoteOp(Node->getOperand(2));
4610 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4611 AtomNode->getBasePtr(), Tmp2,
4612 AtomNode->getSrcValue(),
4613 AtomNode->getAlignment());
4614 // Remember that we legalized the chain.
4615 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4625 // The input may have strange things in the top bits of the registers, but
4626 // these operations don't care. They may have weird bits going out, but
4627 // that too is okay if they are integer operations.
4628 Tmp1 = PromoteOp(Node->getOperand(0));
4629 Tmp2 = PromoteOp(Node->getOperand(1));
4630 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4631 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4636 Tmp1 = PromoteOp(Node->getOperand(0));
4637 Tmp2 = PromoteOp(Node->getOperand(1));
4638 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4639 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4641 // Floating point operations will give excess precision that we may not be
4642 // able to tolerate. If we DO allow excess precision, just leave it,
4643 // otherwise excise it.
4644 // FIXME: Why would we need to round FP ops more than integer ones?
4645 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4646 if (NoExcessFPPrecision)
4647 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4648 DAG.getValueType(VT));
4653 // These operators require that their input be sign extended.
4654 Tmp1 = PromoteOp(Node->getOperand(0));
4655 Tmp2 = PromoteOp(Node->getOperand(1));
4656 if (NVT.isInteger()) {
4657 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4658 DAG.getValueType(VT));
4659 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4660 DAG.getValueType(VT));
4662 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4664 // Perform FP_ROUND: this is probably overly pessimistic.
4665 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4666 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4667 DAG.getValueType(VT));
4671 case ISD::FCOPYSIGN:
4672 // These operators require that their input be fp extended.
4673 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4674 case Expand: assert(0 && "not implemented");
4675 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4676 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4678 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4679 case Expand: assert(0 && "not implemented");
4680 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4681 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4683 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4685 // Perform FP_ROUND: this is probably overly pessimistic.
4686 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4687 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4688 DAG.getValueType(VT));
4693 // These operators require that their input be zero extended.
4694 Tmp1 = PromoteOp(Node->getOperand(0));
4695 Tmp2 = PromoteOp(Node->getOperand(1));
4696 assert(NVT.isInteger() && "Operators don't apply to FP!");
4697 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4698 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4699 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4703 Tmp1 = PromoteOp(Node->getOperand(0));
4704 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4707 // The input value must be properly sign extended.
4708 Tmp1 = PromoteOp(Node->getOperand(0));
4709 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4710 DAG.getValueType(VT));
4711 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4714 // The input value must be properly zero extended.
4715 Tmp1 = PromoteOp(Node->getOperand(0));
4716 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4717 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4721 Tmp1 = Node->getOperand(0); // Get the chain.
4722 Tmp2 = Node->getOperand(1); // Get the pointer.
4723 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4724 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4725 Result = TLI.LowerOperation(Tmp3, DAG);
4727 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4728 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4729 // Increment the pointer, VAList, to the next vaarg
4730 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4731 DAG.getConstant(VT.getSizeInBits()/8,
4732 TLI.getPointerTy()));
4733 // Store the incremented VAList to the legalized pointer
4734 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4735 // Load the actual argument out of the pointer VAList
4736 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4738 // Remember that we legalized the chain.
4739 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4743 LoadSDNode *LD = cast<LoadSDNode>(Node);
4744 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4745 ? ISD::EXTLOAD : LD->getExtensionType();
4746 Result = DAG.getExtLoad(ExtType, NVT,
4747 LD->getChain(), LD->getBasePtr(),
4748 LD->getSrcValue(), LD->getSrcValueOffset(),
4751 LD->getAlignment());
4752 // Remember that we legalized the chain.
4753 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4757 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4758 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4760 MVT VT2 = Tmp2.getValueType();
4761 assert(VT2 == Tmp3.getValueType()
4762 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4763 // Ensure that the resulting node is at least the same size as the operands'
4764 // value types, because we cannot assume that TLI.getSetCCValueType() is
4766 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4769 case ISD::SELECT_CC:
4770 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4771 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4772 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4773 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4776 Tmp1 = Node->getOperand(0);
4777 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4778 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4779 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4780 DAG.getConstant(NVT.getSizeInBits() -
4782 TLI.getShiftAmountTy()));
4787 // Zero extend the argument
4788 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4789 // Perform the larger operation, then subtract if needed.
4790 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4791 switch(Node->getOpcode()) {
4796 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4797 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4798 DAG.getConstant(NVT.getSizeInBits(), NVT),
4800 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4801 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4804 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4805 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4806 DAG.getConstant(NVT.getSizeInBits() -
4807 VT.getSizeInBits(), NVT));
4811 case ISD::EXTRACT_SUBVECTOR:
4812 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4814 case ISD::EXTRACT_VECTOR_ELT:
4815 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4819 assert(Result.getNode() && "Didn't set a result!");
4821 // Make sure the result is itself legal.
4822 Result = LegalizeOp(Result);
4824 // Remember that we promoted this!
4825 AddPromotedOperand(Op, Result);
4829 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4830 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4831 /// based on the vector type. The return type of this matches the element type
4832 /// of the vector, which may not be legal for the target.
4833 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4834 // We know that operand #0 is the Vec vector. If the index is a constant
4835 // or if the invec is a supported hardware type, we can use it. Otherwise,
4836 // lower to a store then an indexed load.
4837 SDValue Vec = Op.getOperand(0);
4838 SDValue Idx = Op.getOperand(1);
4840 MVT TVT = Vec.getValueType();
4841 unsigned NumElems = TVT.getVectorNumElements();
4843 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4844 default: assert(0 && "This action is not supported yet!");
4845 case TargetLowering::Custom: {
4846 Vec = LegalizeOp(Vec);
4847 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4848 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4853 case TargetLowering::Legal:
4854 if (isTypeLegal(TVT)) {
4855 Vec = LegalizeOp(Vec);
4856 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4860 case TargetLowering::Promote:
4861 assert(TVT.isVector() && "not vector type");
4862 // fall thru to expand since vectors are by default are promote
4863 case TargetLowering::Expand:
4867 if (NumElems == 1) {
4868 // This must be an access of the only element. Return it.
4869 Op = ScalarizeVectorOp(Vec);
4870 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4871 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4872 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4874 SplitVectorOp(Vec, Lo, Hi);
4875 if (CIdx->getZExtValue() < NumLoElts) {
4879 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
4880 Idx.getValueType());
4883 // It's now an extract from the appropriate high or low part. Recurse.
4884 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4885 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4887 // Store the value to a temporary stack slot, then LOAD the scalar
4888 // element back out.
4889 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4890 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4892 // Add the offset to the index.
4893 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
4894 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4895 DAG.getConstant(EltSize, Idx.getValueType()));
4897 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
4898 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4900 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4902 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4904 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4909 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4910 /// we assume the operation can be split if it is not already legal.
4911 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
4912 // We know that operand #0 is the Vec vector. For now we assume the index
4913 // is a constant and that the extracted result is a supported hardware type.
4914 SDValue Vec = Op.getOperand(0);
4915 SDValue Idx = LegalizeOp(Op.getOperand(1));
4917 unsigned NumElems = Vec.getValueType().getVectorNumElements();
4919 if (NumElems == Op.getValueType().getVectorNumElements()) {
4920 // This must be an access of the desired vector length. Return it.
4924 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4926 SplitVectorOp(Vec, Lo, Hi);
4927 if (CIdx->getZExtValue() < NumElems/2) {
4931 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
4932 Idx.getValueType());
4935 // It's now an extract from the appropriate high or low part. Recurse.
4936 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4937 return ExpandEXTRACT_SUBVECTOR(Op);
4940 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4941 /// with condition CC on the current target. This usually involves legalizing
4942 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4943 /// there may be no choice but to create a new SetCC node to represent the
4944 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4945 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
4946 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
4949 SDValue Tmp1, Tmp2, Tmp3, Result;
4951 switch (getTypeAction(LHS.getValueType())) {
4953 Tmp1 = LegalizeOp(LHS); // LHS
4954 Tmp2 = LegalizeOp(RHS); // RHS
4957 Tmp1 = PromoteOp(LHS); // LHS
4958 Tmp2 = PromoteOp(RHS); // RHS
4960 // If this is an FP compare, the operands have already been extended.
4961 if (LHS.getValueType().isInteger()) {
4962 MVT VT = LHS.getValueType();
4963 MVT NVT = TLI.getTypeToTransformTo(VT);
4965 // Otherwise, we have to insert explicit sign or zero extends. Note
4966 // that we could insert sign extends for ALL conditions, but zero extend
4967 // is cheaper on many machines (an AND instead of two shifts), so prefer
4969 switch (cast<CondCodeSDNode>(CC)->get()) {
4970 default: assert(0 && "Unknown integer comparison!");
4977 // ALL of these operations will work if we either sign or zero extend
4978 // the operands (including the unsigned comparisons!). Zero extend is
4979 // usually a simpler/cheaper operation, so prefer it.
4980 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4981 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4987 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4988 DAG.getValueType(VT));
4989 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4990 DAG.getValueType(VT));
4991 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
4992 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
4998 MVT VT = LHS.getValueType();
4999 if (VT == MVT::f32 || VT == MVT::f64) {
5000 // Expand into one or more soft-fp libcall(s).
5001 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5002 switch (cast<CondCodeSDNode>(CC)->get()) {
5005 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5009 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5013 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5017 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5021 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5025 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5028 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5031 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5034 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5035 switch (cast<CondCodeSDNode>(CC)->get()) {
5037 // SETONE = SETOLT | SETOGT
5038 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5041 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5044 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5047 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5050 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5053 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5055 default: assert(0 && "Unsupported FP setcc!");
5060 SDValue Ops[2] = { LHS, RHS };
5061 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
5062 false /*sign irrelevant*/, Dummy);
5063 Tmp2 = DAG.getConstant(0, MVT::i32);
5064 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5065 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5066 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
5068 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
5069 false /*sign irrelevant*/, Dummy);
5070 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
5071 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5072 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5075 LHS = LegalizeOp(Tmp1);
5080 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5081 ExpandOp(LHS, LHSLo, LHSHi);
5082 ExpandOp(RHS, RHSLo, RHSHi);
5083 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5085 if (VT==MVT::ppcf128) {
5086 // FIXME: This generated code sucks. We want to generate
5087 // FCMPU crN, hi1, hi2
5089 // FCMPU crN, lo1, lo2
5090 // The following can be improved, but not that much.
5091 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5093 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
5094 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5095 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5097 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
5098 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5099 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
5108 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5109 if (RHSCST->isAllOnesValue()) {
5110 // Comparison to -1.
5111 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
5116 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
5117 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
5118 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5119 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5122 // If this is a comparison of the sign bit, just look at the top part.
5124 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5125 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5126 CST->isNullValue()) || // X < 0
5127 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5128 CST->isAllOnesValue())) { // X > -1
5134 // FIXME: This generated code sucks.
5135 ISD::CondCode LowCC;
5137 default: assert(0 && "Unknown integer setcc!");
5139 case ISD::SETULT: LowCC = ISD::SETULT; break;
5141 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5143 case ISD::SETULE: LowCC = ISD::SETULE; break;
5145 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5148 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5149 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5150 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5152 // NOTE: on targets without efficient SELECT of bools, we can always use
5153 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5154 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5155 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
5156 LowCC, false, DagCombineInfo);
5157 if (!Tmp1.getNode())
5158 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
5159 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5160 CCCode, false, DagCombineInfo);
5161 if (!Tmp2.getNode())
5162 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
5165 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5166 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5167 if ((Tmp1C && Tmp1C->isNullValue()) ||
5168 (Tmp2C && Tmp2C->isNullValue() &&
5169 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5170 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5171 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5172 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5173 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5174 // low part is known false, returns high part.
5175 // For LE / GE, if high part is known false, ignore the low part.
5176 // For LT / GT, if high part is known true, ignore the low part.
5180 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5181 ISD::SETEQ, false, DagCombineInfo);
5182 if (!Result.getNode())
5183 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5185 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5186 Result, Tmp1, Tmp2));
5197 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5198 /// condition code CC on the current target. This routine assumes LHS and rHS
5199 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5200 /// illegal condition code into AND / OR of multiple SETCC values.
5201 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5202 SDValue &LHS, SDValue &RHS,
5204 MVT OpVT = LHS.getValueType();
5205 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5206 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5207 default: assert(0 && "Unknown condition code action!");
5208 case TargetLowering::Legal:
5211 case TargetLowering::Expand: {
5212 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5215 default: assert(0 && "Don't know how to expand this condition!"); abort();
5216 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5217 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5218 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5219 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5220 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5221 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5222 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5223 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5224 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5225 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5226 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5227 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5228 // FIXME: Implement more expansions.
5231 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5232 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5233 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5241 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5242 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5243 /// a load from the stack slot to DestVT, extending it if needed.
5244 /// The resultant code need not be legal.
5245 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5248 // Create the stack frame object.
5249 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5250 SrcOp.getValueType().getTypeForMVT());
5251 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5253 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5254 int SPFI = StackPtrFI->getIndex();
5256 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5257 unsigned SlotSize = SlotVT.getSizeInBits();
5258 unsigned DestSize = DestVT.getSizeInBits();
5259 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5260 DestVT.getTypeForMVT());
5262 // Emit a store to the stack slot. Use a truncstore if the input value is
5263 // later than DestVT.
5266 if (SrcSize > SlotSize)
5267 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5268 PseudoSourceValue::getFixedStack(SPFI), 0,
5269 SlotVT, false, SrcAlign);
5271 assert(SrcSize == SlotSize && "Invalid store");
5272 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5273 PseudoSourceValue::getFixedStack(SPFI), 0,
5277 // Result is a load from the stack slot.
5278 if (SlotSize == DestSize)
5279 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5281 assert(SlotSize < DestSize && "Unknown extension!");
5282 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5286 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5287 // Create a vector sized/aligned stack slot, store the value to element #0,
5288 // then load the whole vector back out.
5289 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5291 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5292 int SPFI = StackPtrFI->getIndex();
5294 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5295 PseudoSourceValue::getFixedStack(SPFI), 0);
5296 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5297 PseudoSourceValue::getFixedStack(SPFI), 0);
5301 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5302 /// support the operation, but do support the resultant vector type.
5303 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5305 // If the only non-undef value is the low element, turn this into a
5306 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5307 unsigned NumElems = Node->getNumOperands();
5308 bool isOnlyLowElement = true;
5309 SDValue SplatValue = Node->getOperand(0);
5311 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5312 // and use a bitmask instead of a list of elements.
5313 std::map<SDValue, std::vector<unsigned> > Values;
5314 Values[SplatValue].push_back(0);
5315 bool isConstant = true;
5316 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5317 SplatValue.getOpcode() != ISD::UNDEF)
5320 for (unsigned i = 1; i < NumElems; ++i) {
5321 SDValue V = Node->getOperand(i);
5322 Values[V].push_back(i);
5323 if (V.getOpcode() != ISD::UNDEF)
5324 isOnlyLowElement = false;
5325 if (SplatValue != V)
5326 SplatValue = SDValue(0,0);
5328 // If this isn't a constant element or an undef, we can't use a constant
5330 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5331 V.getOpcode() != ISD::UNDEF)
5335 if (isOnlyLowElement) {
5336 // If the low element is an undef too, then this whole things is an undef.
5337 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5338 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5339 // Otherwise, turn this into a scalar_to_vector node.
5340 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5341 Node->getOperand(0));
5344 // If all elements are constants, create a load from the constant pool.
5346 MVT VT = Node->getValueType(0);
5347 std::vector<Constant*> CV;
5348 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5349 if (ConstantFPSDNode *V =
5350 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5351 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5352 } else if (ConstantSDNode *V =
5353 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5354 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5356 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5358 Node->getOperand(0).getValueType().getTypeForMVT();
5359 CV.push_back(UndefValue::get(OpNTy));
5362 Constant *CP = ConstantVector::get(CV);
5363 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5364 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5365 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5366 PseudoSourceValue::getConstantPool(), 0,
5370 if (SplatValue.getNode()) { // Splat of one value?
5371 // Build the shuffle constant vector: <0, 0, 0, 0>
5372 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5373 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5374 std::vector<SDValue> ZeroVec(NumElems, Zero);
5375 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5376 &ZeroVec[0], ZeroVec.size());
5378 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5379 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5380 // Get the splatted value into the low element of a vector register.
5382 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5384 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5385 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5386 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5391 // If there are only two unique elements, we may be able to turn this into a
5393 if (Values.size() == 2) {
5394 // Get the two values in deterministic order.
5395 SDValue Val1 = Node->getOperand(1);
5397 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5398 if (MI->first != Val1)
5401 Val2 = (++MI)->first;
5403 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5404 // vector shuffle has the undef vector on the RHS.
5405 if (Val1.getOpcode() == ISD::UNDEF)
5406 std::swap(Val1, Val2);
5408 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5409 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5410 MVT MaskEltVT = MaskVT.getVectorElementType();
5411 std::vector<SDValue> MaskVec(NumElems);
5413 // Set elements of the shuffle mask for Val1.
5414 std::vector<unsigned> &Val1Elts = Values[Val1];
5415 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5416 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5418 // Set elements of the shuffle mask for Val2.
5419 std::vector<unsigned> &Val2Elts = Values[Val2];
5420 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5421 if (Val2.getOpcode() != ISD::UNDEF)
5422 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5424 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5426 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5427 &MaskVec[0], MaskVec.size());
5429 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5430 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5431 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5432 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5433 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5434 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5436 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5437 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5441 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5442 // aligned object on the stack, store each element into it, then load
5443 // the result as a vector.
5444 MVT VT = Node->getValueType(0);
5445 // Create the stack frame object.
5446 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5448 // Emit a store of each element to the stack slot.
5449 SmallVector<SDValue, 8> Stores;
5450 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5451 // Store (in the right endianness) the elements to memory.
5452 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5453 // Ignore undef elements.
5454 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5456 unsigned Offset = TypeByteSize*i;
5458 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5459 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5461 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5466 if (!Stores.empty()) // Not all undef elements?
5467 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5468 &Stores[0], Stores.size());
5470 StoreChain = DAG.getEntryNode();
5472 // Result is a load from the stack slot.
5473 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5476 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5477 SDValue Op, SDValue Amt,
5478 SDValue &Lo, SDValue &Hi) {
5479 // Expand the subcomponents.
5481 ExpandOp(Op, LHSL, LHSH);
5483 SDValue Ops[] = { LHSL, LHSH, Amt };
5484 MVT VT = LHSL.getValueType();
5485 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5486 Hi = Lo.getValue(1);
5490 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5491 /// smaller elements. If we can't find a way that is more efficient than a
5492 /// libcall on this target, return false. Otherwise, return true with the
5493 /// low-parts expanded into Lo and Hi.
5494 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5495 SDValue &Lo, SDValue &Hi) {
5496 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5497 "This is not a shift!");
5499 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5500 SDValue ShAmt = LegalizeOp(Amt);
5501 MVT ShTy = ShAmt.getValueType();
5502 unsigned ShBits = ShTy.getSizeInBits();
5503 unsigned VTBits = Op.getValueType().getSizeInBits();
5504 unsigned NVTBits = NVT.getSizeInBits();
5506 // Handle the case when Amt is an immediate.
5507 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5508 unsigned Cst = CN->getZExtValue();
5509 // Expand the incoming operand to be shifted, so that we have its parts
5511 ExpandOp(Op, InL, InH);
5515 Lo = DAG.getConstant(0, NVT);
5516 Hi = DAG.getConstant(0, NVT);
5517 } else if (Cst > NVTBits) {
5518 Lo = DAG.getConstant(0, NVT);
5519 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5520 } else if (Cst == NVTBits) {
5521 Lo = DAG.getConstant(0, NVT);
5524 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5525 Hi = DAG.getNode(ISD::OR, NVT,
5526 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5527 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5532 Lo = DAG.getConstant(0, NVT);
5533 Hi = DAG.getConstant(0, NVT);
5534 } else if (Cst > NVTBits) {
5535 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5536 Hi = DAG.getConstant(0, NVT);
5537 } else if (Cst == NVTBits) {
5539 Hi = DAG.getConstant(0, NVT);
5541 Lo = DAG.getNode(ISD::OR, NVT,
5542 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5543 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5544 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5549 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5550 DAG.getConstant(NVTBits-1, ShTy));
5551 } else if (Cst > NVTBits) {
5552 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5553 DAG.getConstant(Cst-NVTBits, ShTy));
5554 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5555 DAG.getConstant(NVTBits-1, ShTy));
5556 } else if (Cst == NVTBits) {
5558 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5559 DAG.getConstant(NVTBits-1, ShTy));
5561 Lo = DAG.getNode(ISD::OR, NVT,
5562 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5563 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5564 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5570 // Okay, the shift amount isn't constant. However, if we can tell that it is
5571 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5572 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5573 APInt KnownZero, KnownOne;
5574 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5576 // If we know that if any of the high bits of the shift amount are one, then
5577 // we can do this as a couple of simple shifts.
5578 if (KnownOne.intersects(Mask)) {
5579 // Mask out the high bit, which we know is set.
5580 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5581 DAG.getConstant(~Mask, Amt.getValueType()));
5583 // Expand the incoming operand to be shifted, so that we have its parts
5585 ExpandOp(Op, InL, InH);
5588 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5589 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5592 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5593 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5596 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5597 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5598 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5603 // If we know that the high bits of the shift amount are all zero, then we can
5604 // do this as a couple of simple shifts.
5605 if ((KnownZero & Mask) == Mask) {
5607 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5608 DAG.getConstant(NVTBits, Amt.getValueType()),
5611 // Expand the incoming operand to be shifted, so that we have its parts
5613 ExpandOp(Op, InL, InH);
5616 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5617 Hi = DAG.getNode(ISD::OR, NVT,
5618 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5619 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5622 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5623 Lo = DAG.getNode(ISD::OR, NVT,
5624 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5625 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5628 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5629 Lo = DAG.getNode(ISD::OR, NVT,
5630 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5631 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5640 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5641 // does not fit into a register, return the lo part and set the hi part to the
5642 // by-reg argument. If it does fit into a single register, return the result
5643 // and leave the Hi part unset.
5644 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5645 bool isSigned, SDValue &Hi) {
5646 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5647 // The input chain to this libcall is the entry node of the function.
5648 // Legalizing the call will automatically add the previous call to the
5650 SDValue InChain = DAG.getEntryNode();
5652 TargetLowering::ArgListTy Args;
5653 TargetLowering::ArgListEntry Entry;
5654 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5655 MVT ArgVT = Node->getOperand(i).getValueType();
5656 const Type *ArgTy = ArgVT.getTypeForMVT();
5657 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5658 Entry.isSExt = isSigned;
5659 Entry.isZExt = !isSigned;
5660 Args.push_back(Entry);
5662 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5663 TLI.getPointerTy());
5665 // Splice the libcall in wherever FindInputOutputChains tells us to.
5666 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5667 std::pair<SDValue,SDValue> CallInfo =
5668 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5669 CallingConv::C, false, Callee, Args, DAG);
5671 // Legalize the call sequence, starting with the chain. This will advance
5672 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5673 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5674 LegalizeOp(CallInfo.second);
5676 switch (getTypeAction(CallInfo.first.getValueType())) {
5677 default: assert(0 && "Unknown thing");
5679 Result = CallInfo.first;
5682 ExpandOp(CallInfo.first, Result, Hi);
5688 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5690 SDValue SelectionDAGLegalize::
5691 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5692 bool isCustom = false;
5694 switch (getTypeAction(Op.getValueType())) {
5696 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5697 Op.getValueType())) {
5698 default: assert(0 && "Unknown operation action!");
5699 case TargetLowering::Custom:
5702 case TargetLowering::Legal:
5703 Tmp1 = LegalizeOp(Op);
5704 if (Result.getNode())
5705 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5707 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5710 Tmp1 = TLI.LowerOperation(Result, DAG);
5711 if (Tmp1.getNode()) Result = Tmp1;
5714 case TargetLowering::Expand:
5715 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5717 case TargetLowering::Promote:
5718 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5723 Result = ExpandIntToFP(isSigned, DestTy, Op);
5726 Tmp1 = PromoteOp(Op);
5728 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5729 Tmp1, DAG.getValueType(Op.getValueType()));
5731 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5734 if (Result.getNode())
5735 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5737 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5739 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5745 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5747 SDValue SelectionDAGLegalize::
5748 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5749 MVT SourceVT = Source.getValueType();
5750 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5752 // Expand unsupported int-to-fp vector casts by unrolling them.
5753 if (DestTy.isVector()) {
5755 return LegalizeOp(UnrollVectorOp(Source));
5756 MVT DestEltTy = DestTy.getVectorElementType();
5757 if (DestTy.getVectorNumElements() == 1) {
5758 SDValue Scalar = ScalarizeVectorOp(Source);
5759 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5761 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5764 SplitVectorOp(Source, Lo, Hi);
5765 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5766 DestTy.getVectorNumElements() / 2);
5767 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5768 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5769 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5773 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5774 if (!isSigned && SourceVT != MVT::i32) {
5775 // The integer value loaded will be incorrectly if the 'sign bit' of the
5776 // incoming integer is set. To handle this, we dynamically test to see if
5777 // it is set, and, if so, add a fudge factor.
5781 ExpandOp(Source, Lo, Hi);
5782 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5784 // The comparison for the sign bit will use the entire operand.
5788 // Check to see if the target has a custom way to lower this. If so, use
5789 // it. (Note we've already expanded the operand in this case.)
5790 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5791 default: assert(0 && "This action not implemented for this operation!");
5792 case TargetLowering::Legal:
5793 case TargetLowering::Expand:
5794 break; // This case is handled below.
5795 case TargetLowering::Custom: {
5796 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5799 return LegalizeOp(NV);
5800 break; // The target decided this was legal after all
5804 // If this is unsigned, and not supported, first perform the conversion to
5805 // signed, then adjust the result if the sign bit is set.
5806 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5808 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5809 DAG.getConstant(0, Hi.getValueType()),
5811 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5812 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5813 SignSet, Four, Zero);
5814 uint64_t FF = 0x5f800000ULL;
5815 if (TLI.isLittleEndian()) FF <<= 32;
5816 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5818 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5819 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5820 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5821 Alignment = std::min(Alignment, 4u);
5823 if (DestTy == MVT::f32)
5824 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5825 PseudoSourceValue::getConstantPool(), 0,
5827 else if (DestTy.bitsGT(MVT::f32))
5828 // FIXME: Avoid the extend by construction the right constantpool?
5829 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5831 PseudoSourceValue::getConstantPool(), 0,
5832 MVT::f32, false, Alignment);
5834 assert(0 && "Unexpected conversion");
5836 MVT SCVT = SignedConv.getValueType();
5837 if (SCVT != DestTy) {
5838 // Destination type needs to be expanded as well. The FADD now we are
5839 // constructing will be expanded into a libcall.
5840 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5841 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5842 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5843 SignedConv, SignedConv.getValue(1));
5845 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5847 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5850 // Check to see if the target has a custom way to lower this. If so, use it.
5851 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5852 default: assert(0 && "This action not implemented for this operation!");
5853 case TargetLowering::Legal:
5854 case TargetLowering::Expand:
5855 break; // This case is handled below.
5856 case TargetLowering::Custom: {
5857 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5860 return LegalizeOp(NV);
5861 break; // The target decided this was legal after all
5865 // Expand the source, then glue it back together for the call. We must expand
5866 // the source in case it is shared (this pass of legalize must traverse it).
5868 SDValue SrcLo, SrcHi;
5869 ExpandOp(Source, SrcLo, SrcHi);
5870 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5873 RTLIB::Libcall LC = isSigned ?
5874 RTLIB::getSINTTOFP(SourceVT, DestTy) :
5875 RTLIB::getUINTTOFP(SourceVT, DestTy);
5876 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
5878 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5880 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
5881 if (Result.getValueType() != DestTy && HiPart.getNode())
5882 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5886 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5887 /// INT_TO_FP operation of the specified operand when the target requests that
5888 /// we expand it. At this point, we know that the result and operand types are
5889 /// legal for the target.
5890 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5893 if (Op0.getValueType() == MVT::i32) {
5894 // simple 32-bit [signed|unsigned] integer to float/double expansion
5896 // Get the stack frame index of a 8 byte buffer.
5897 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
5899 // word offset constant for Hi/Lo address computation
5900 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5901 // set up Hi and Lo (into buffer) address based on endian
5902 SDValue Hi = StackSlot;
5903 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5904 if (TLI.isLittleEndian())
5907 // if signed map to unsigned space
5910 // constant used to invert sign bit (signed to unsigned mapping)
5911 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5912 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5916 // store the lo of the constructed double - based on integer input
5917 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
5918 Op0Mapped, Lo, NULL, 0);
5919 // initial hi portion of constructed double
5920 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5921 // store the hi of the constructed double - biased exponent
5922 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5923 // load the constructed double
5924 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5925 // FP constant to bias correct the final result
5926 SDValue Bias = DAG.getConstantFP(isSigned ?
5927 BitsToDouble(0x4330000080000000ULL)
5928 : BitsToDouble(0x4330000000000000ULL),
5930 // subtract the bias
5931 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5934 // handle final rounding
5935 if (DestVT == MVT::f64) {
5938 } else if (DestVT.bitsLT(MVT::f64)) {
5939 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5940 DAG.getIntPtrConstant(0));
5941 } else if (DestVT.bitsGT(MVT::f64)) {
5942 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5946 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5947 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5949 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5950 DAG.getConstant(0, Op0.getValueType()),
5952 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5953 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5954 SignSet, Four, Zero);
5956 // If the sign bit of the integer is set, the large number will be treated
5957 // as a negative number. To counteract this, the dynamic code adds an
5958 // offset depending on the data type.
5960 switch (Op0.getValueType().getSimpleVT()) {
5961 default: assert(0 && "Unsupported integer type!");
5962 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5963 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5964 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5965 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5967 if (TLI.isLittleEndian()) FF <<= 32;
5968 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5970 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5971 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5972 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5973 Alignment = std::min(Alignment, 4u);
5975 if (DestVT == MVT::f32)
5976 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5977 PseudoSourceValue::getConstantPool(), 0,
5981 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5982 DAG.getEntryNode(), CPIdx,
5983 PseudoSourceValue::getConstantPool(), 0,
5984 MVT::f32, false, Alignment));
5987 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5990 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5991 /// *INT_TO_FP operation of the specified operand when the target requests that
5992 /// we promote it. At this point, we know that the result and operand types are
5993 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5994 /// operation that takes a larger input.
5995 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
5998 // First step, figure out the appropriate *INT_TO_FP operation to use.
5999 MVT NewInTy = LegalOp.getValueType();
6001 unsigned OpToUse = 0;
6003 // Scan for the appropriate larger type to use.
6005 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6006 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6008 // If the target supports SINT_TO_FP of this type, use it.
6009 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6011 case TargetLowering::Legal:
6012 if (!TLI.isTypeLegal(NewInTy))
6013 break; // Can't use this datatype.
6015 case TargetLowering::Custom:
6016 OpToUse = ISD::SINT_TO_FP;
6020 if (isSigned) continue;
6022 // If the target supports UINT_TO_FP of this type, use it.
6023 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6025 case TargetLowering::Legal:
6026 if (!TLI.isTypeLegal(NewInTy))
6027 break; // Can't use this datatype.
6029 case TargetLowering::Custom:
6030 OpToUse = ISD::UINT_TO_FP;
6035 // Otherwise, try a larger type.
6038 // Okay, we found the operation and type to use. Zero extend our input to the
6039 // desired type then run the operation on it.
6040 return DAG.getNode(OpToUse, DestVT,
6041 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6045 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6046 /// FP_TO_*INT operation of the specified operand when the target requests that
6047 /// we promote it. At this point, we know that the result and operand types are
6048 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6049 /// operation that returns a larger result.
6050 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6053 // First step, figure out the appropriate FP_TO*INT operation to use.
6054 MVT NewOutTy = DestVT;
6056 unsigned OpToUse = 0;
6058 // Scan for the appropriate larger type to use.
6060 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6061 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6063 // If the target supports FP_TO_SINT returning this type, use it.
6064 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6066 case TargetLowering::Legal:
6067 if (!TLI.isTypeLegal(NewOutTy))
6068 break; // Can't use this datatype.
6070 case TargetLowering::Custom:
6071 OpToUse = ISD::FP_TO_SINT;
6076 // If the target supports FP_TO_UINT of this type, use it.
6077 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6079 case TargetLowering::Legal:
6080 if (!TLI.isTypeLegal(NewOutTy))
6081 break; // Can't use this datatype.
6083 case TargetLowering::Custom:
6084 OpToUse = ISD::FP_TO_UINT;
6089 // Otherwise, try a larger type.
6093 // Okay, we found the operation and type to use.
6094 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
6096 // If the operation produces an invalid type, it must be custom lowered. Use
6097 // the target lowering hooks to expand it. Just keep the low part of the
6098 // expanded operation, we know that we're truncating anyway.
6099 if (getTypeAction(NewOutTy) == Expand) {
6100 SmallVector<SDValue, 2> Results;
6101 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6102 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6103 Operation = Results[0];
6106 // Truncate the result of the extended FP_TO_*INT operation to the desired
6108 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
6111 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6113 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
6114 MVT VT = Op.getValueType();
6115 MVT SHVT = TLI.getShiftAmountTy();
6116 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6117 switch (VT.getSimpleVT()) {
6118 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6120 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6121 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6122 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6124 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6125 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6126 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6127 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6128 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6129 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6130 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6131 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6132 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6134 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6135 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6136 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6137 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6138 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6139 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6140 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6141 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6142 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6143 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6144 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6145 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6146 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6147 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6148 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6149 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6150 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6151 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6152 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6153 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6154 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6158 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6160 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6162 default: assert(0 && "Cannot expand this yet!");
6164 static const uint64_t mask[6] = {
6165 0x5555555555555555ULL, 0x3333333333333333ULL,
6166 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6167 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6169 MVT VT = Op.getValueType();
6170 MVT ShVT = TLI.getShiftAmountTy();
6171 unsigned len = VT.getSizeInBits();
6172 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6173 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6174 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
6175 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6176 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6177 DAG.getNode(ISD::AND, VT,
6178 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6183 // for now, we do this:
6184 // x = x | (x >> 1);
6185 // x = x | (x >> 2);
6187 // x = x | (x >>16);
6188 // x = x | (x >>32); // for 64-bit input
6189 // return popcount(~x);
6191 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6192 MVT VT = Op.getValueType();
6193 MVT ShVT = TLI.getShiftAmountTy();
6194 unsigned len = VT.getSizeInBits();
6195 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6196 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6197 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6199 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
6200 return DAG.getNode(ISD::CTPOP, VT, Op);
6203 // for now, we use: { return popcount(~x & (x - 1)); }
6204 // unless the target has ctlz but not ctpop, in which case we use:
6205 // { return 32 - nlz(~x & (x-1)); }
6206 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6207 MVT VT = Op.getValueType();
6208 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
6209 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6210 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
6211 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6212 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6213 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6214 TLI.isOperationLegal(ISD::CTLZ, VT))
6215 return DAG.getNode(ISD::SUB, VT,
6216 DAG.getConstant(VT.getSizeInBits(), VT),
6217 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6218 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6223 /// ExpandOp - Expand the specified SDValue into its two component pieces
6224 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6225 /// LegalizedNodes map is filled in for any results that are not expanded, the
6226 /// ExpandedNodes map is filled in for any results that are expanded, and the
6227 /// Lo/Hi values are returned.
6228 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6229 MVT VT = Op.getValueType();
6230 MVT NVT = TLI.getTypeToTransformTo(VT);
6231 SDNode *Node = Op.getNode();
6232 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6233 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6234 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6236 // See if we already expanded it.
6237 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6238 = ExpandedNodes.find(Op);
6239 if (I != ExpandedNodes.end()) {
6240 Lo = I->second.first;
6241 Hi = I->second.second;
6245 switch (Node->getOpcode()) {
6246 case ISD::CopyFromReg:
6247 assert(0 && "CopyFromReg must be legal!");
6248 case ISD::FP_ROUND_INREG:
6249 if (VT == MVT::ppcf128 &&
6250 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6251 TargetLowering::Custom) {
6252 SDValue SrcLo, SrcHi, Src;
6253 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6254 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6255 SDValue Result = TLI.LowerOperation(
6256 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6257 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6258 Lo = Result.getNode()->getOperand(0);
6259 Hi = Result.getNode()->getOperand(1);
6265 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6267 assert(0 && "Do not know how to expand this operator!");
6269 case ISD::EXTRACT_ELEMENT:
6270 ExpandOp(Node->getOperand(0), Lo, Hi);
6271 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6272 return ExpandOp(Hi, Lo, Hi);
6273 return ExpandOp(Lo, Lo, Hi);
6274 case ISD::EXTRACT_VECTOR_ELT:
6275 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6276 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6277 return ExpandOp(Lo, Lo, Hi);
6279 Lo = DAG.getNode(ISD::UNDEF, NVT);
6280 Hi = DAG.getNode(ISD::UNDEF, NVT);
6282 case ISD::Constant: {
6283 unsigned NVTBits = NVT.getSizeInBits();
6284 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6285 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6286 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6289 case ISD::ConstantFP: {
6290 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6291 if (CFP->getValueType(0) == MVT::ppcf128) {
6292 APInt api = CFP->getValueAPF().bitcastToAPInt();
6293 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6295 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6299 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6300 if (getTypeAction(Lo.getValueType()) == Expand)
6301 ExpandOp(Lo, Lo, Hi);
6304 case ISD::BUILD_PAIR:
6305 // Return the operands.
6306 Lo = Node->getOperand(0);
6307 Hi = Node->getOperand(1);
6310 case ISD::MERGE_VALUES:
6311 if (Node->getNumValues() == 1) {
6312 ExpandOp(Op.getOperand(0), Lo, Hi);
6315 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6316 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6317 Op.getValue(1).getValueType() == MVT::Other &&
6318 "unhandled MERGE_VALUES");
6319 ExpandOp(Op.getOperand(0), Lo, Hi);
6320 // Remember that we legalized the chain.
6321 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6324 case ISD::SIGN_EXTEND_INREG:
6325 ExpandOp(Node->getOperand(0), Lo, Hi);
6326 // sext_inreg the low part if needed.
6327 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6329 // The high part gets the sign extension from the lo-part. This handles
6330 // things like sextinreg V:i64 from i8.
6331 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6332 DAG.getConstant(NVT.getSizeInBits()-1,
6333 TLI.getShiftAmountTy()));
6337 ExpandOp(Node->getOperand(0), Lo, Hi);
6338 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6339 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6345 ExpandOp(Node->getOperand(0), Lo, Hi);
6346 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6347 DAG.getNode(ISD::CTPOP, NVT, Lo),
6348 DAG.getNode(ISD::CTPOP, NVT, Hi));
6349 Hi = DAG.getConstant(0, NVT);
6353 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6354 ExpandOp(Node->getOperand(0), Lo, Hi);
6355 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6356 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6357 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
6359 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6360 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6362 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6363 Hi = DAG.getConstant(0, NVT);
6368 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6369 ExpandOp(Node->getOperand(0), Lo, Hi);
6370 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6371 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6372 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
6374 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6375 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6377 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6378 Hi = DAG.getConstant(0, NVT);
6383 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6384 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6385 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6386 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6388 // Remember that we legalized the chain.
6389 Hi = LegalizeOp(Hi);
6390 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6391 if (TLI.isBigEndian())
6397 LoadSDNode *LD = cast<LoadSDNode>(Node);
6398 SDValue Ch = LD->getChain(); // Legalize the chain.
6399 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6400 ISD::LoadExtType ExtType = LD->getExtensionType();
6401 const Value *SV = LD->getSrcValue();
6402 int SVOffset = LD->getSrcValueOffset();
6403 unsigned Alignment = LD->getAlignment();
6404 bool isVolatile = LD->isVolatile();
6406 if (ExtType == ISD::NON_EXTLOAD) {
6407 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6408 isVolatile, Alignment);
6409 if (VT == MVT::f32 || VT == MVT::f64) {
6410 // f32->i32 or f64->i64 one to one expansion.
6411 // Remember that we legalized the chain.
6412 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6413 // Recursively expand the new load.
6414 if (getTypeAction(NVT) == Expand)
6415 ExpandOp(Lo, Lo, Hi);
6419 // Increment the pointer to the other half.
6420 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6421 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6422 DAG.getIntPtrConstant(IncrementSize));
6423 SVOffset += IncrementSize;
6424 Alignment = MinAlign(Alignment, IncrementSize);
6425 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6426 isVolatile, Alignment);
6428 // Build a factor node to remember that this load is independent of the
6430 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6433 // Remember that we legalized the chain.
6434 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6435 if (TLI.isBigEndian())
6438 MVT EVT = LD->getMemoryVT();
6440 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6441 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6442 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6443 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6444 SVOffset, isVolatile, Alignment);
6445 // Remember that we legalized the chain.
6446 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6447 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6452 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6453 SVOffset, isVolatile, Alignment);
6455 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6456 SVOffset, EVT, isVolatile,
6459 // Remember that we legalized the chain.
6460 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6462 if (ExtType == ISD::SEXTLOAD) {
6463 // The high part is obtained by SRA'ing all but one of the bits of the
6465 unsigned LoSize = Lo.getValueType().getSizeInBits();
6466 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6467 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6468 } else if (ExtType == ISD::ZEXTLOAD) {
6469 // The high part is just a zero.
6470 Hi = DAG.getConstant(0, NVT);
6471 } else /* if (ExtType == ISD::EXTLOAD) */ {
6472 // The high part is undefined.
6473 Hi = DAG.getNode(ISD::UNDEF, NVT);
6480 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6481 SDValue LL, LH, RL, RH;
6482 ExpandOp(Node->getOperand(0), LL, LH);
6483 ExpandOp(Node->getOperand(1), RL, RH);
6484 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6485 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6489 SDValue LL, LH, RL, RH;
6490 ExpandOp(Node->getOperand(1), LL, LH);
6491 ExpandOp(Node->getOperand(2), RL, RH);
6492 if (getTypeAction(NVT) == Expand)
6493 NVT = TLI.getTypeToExpandTo(NVT);
6494 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6496 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6499 case ISD::SELECT_CC: {
6500 SDValue TL, TH, FL, FH;
6501 ExpandOp(Node->getOperand(2), TL, TH);
6502 ExpandOp(Node->getOperand(3), FL, FH);
6503 if (getTypeAction(NVT) == Expand)
6504 NVT = TLI.getTypeToExpandTo(NVT);
6505 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6506 Node->getOperand(1), TL, FL, Node->getOperand(4));
6508 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6509 Node->getOperand(1), TH, FH, Node->getOperand(4));
6512 case ISD::ANY_EXTEND:
6513 // The low part is any extension of the input (which degenerates to a copy).
6514 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6515 // The high part is undefined.
6516 Hi = DAG.getNode(ISD::UNDEF, NVT);
6518 case ISD::SIGN_EXTEND: {
6519 // The low part is just a sign extension of the input (which degenerates to
6521 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6523 // The high part is obtained by SRA'ing all but one of the bits of the lo
6525 unsigned LoSize = Lo.getValueType().getSizeInBits();
6526 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6527 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6530 case ISD::ZERO_EXTEND:
6531 // The low part is just a zero extension of the input (which degenerates to
6533 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6535 // The high part is just a zero.
6536 Hi = DAG.getConstant(0, NVT);
6539 case ISD::TRUNCATE: {
6540 // The input value must be larger than this value. Expand *it*.
6542 ExpandOp(Node->getOperand(0), NewLo, Hi);
6544 // The low part is now either the right size, or it is closer. If not the
6545 // right size, make an illegal truncate so we recursively expand it.
6546 if (NewLo.getValueType() != Node->getValueType(0))
6547 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6548 ExpandOp(NewLo, Lo, Hi);
6552 case ISD::BIT_CONVERT: {
6554 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6555 // If the target wants to, allow it to lower this itself.
6556 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6557 case Expand: assert(0 && "cannot expand FP!");
6558 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6559 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6561 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6564 // f32 / f64 must be expanded to i32 / i64.
6565 if (VT == MVT::f32 || VT == MVT::f64) {
6566 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6567 if (getTypeAction(NVT) == Expand)
6568 ExpandOp(Lo, Lo, Hi);
6572 // If source operand will be expanded to the same type as VT, i.e.
6573 // i64 <- f64, i32 <- f32, expand the source operand instead.
6574 MVT VT0 = Node->getOperand(0).getValueType();
6575 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6576 ExpandOp(Node->getOperand(0), Lo, Hi);
6580 // Turn this into a load/store pair by default.
6581 if (Tmp.getNode() == 0)
6582 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6584 ExpandOp(Tmp, Lo, Hi);
6588 case ISD::READCYCLECOUNTER: {
6589 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6590 TargetLowering::Custom &&
6591 "Must custom expand ReadCycleCounter");
6592 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6593 assert(Tmp.getNode() && "Node must be custom expanded!");
6594 ExpandOp(Tmp.getValue(0), Lo, Hi);
6595 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6596 LegalizeOp(Tmp.getValue(1)));
6600 case ISD::ATOMIC_CMP_SWAP_64: {
6601 // This operation does not need a loop.
6602 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6603 assert(Tmp.getNode() && "Node must be custom expanded!");
6604 ExpandOp(Tmp.getValue(0), Lo, Hi);
6605 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6606 LegalizeOp(Tmp.getValue(1)));
6610 case ISD::ATOMIC_LOAD_ADD_64:
6611 case ISD::ATOMIC_LOAD_SUB_64:
6612 case ISD::ATOMIC_LOAD_AND_64:
6613 case ISD::ATOMIC_LOAD_OR_64:
6614 case ISD::ATOMIC_LOAD_XOR_64:
6615 case ISD::ATOMIC_LOAD_NAND_64:
6616 case ISD::ATOMIC_SWAP_64: {
6617 // These operations require a loop to be generated. We can't do that yet,
6618 // so substitute a target-dependent pseudo and expand that later.
6619 SDValue In2Lo, In2Hi, In2;
6620 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6621 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6622 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6624 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6625 Anode->getSrcValue(), Anode->getAlignment());
6626 SDValue Result = TLI.LowerOperation(Replace, DAG);
6627 ExpandOp(Result.getValue(0), Lo, Hi);
6628 // Remember that we legalized the chain.
6629 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6633 // These operators cannot be expanded directly, emit them as calls to
6634 // library functions.
6635 case ISD::FP_TO_SINT: {
6636 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6638 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6639 case Expand: assert(0 && "cannot expand FP!");
6640 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6641 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6644 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6646 // Now that the custom expander is done, expand the result, which is still
6649 ExpandOp(Op, Lo, Hi);
6654 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6656 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6657 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6661 case ISD::FP_TO_UINT: {
6662 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6664 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6665 case Expand: assert(0 && "cannot expand FP!");
6666 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6667 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6670 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6672 // Now that the custom expander is done, expand the result.
6674 ExpandOp(Op, Lo, Hi);
6679 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6681 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6682 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6687 // If the target wants custom lowering, do so.
6688 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6689 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6690 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6691 Op = TLI.LowerOperation(Op, DAG);
6693 // Now that the custom expander is done, expand the result, which is
6695 ExpandOp(Op, Lo, Hi);
6700 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6701 // this X << 1 as X+X.
6702 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6703 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6704 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6705 SDValue LoOps[2], HiOps[3];
6706 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6707 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6708 LoOps[1] = LoOps[0];
6709 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6711 HiOps[1] = HiOps[0];
6712 HiOps[2] = Lo.getValue(1);
6713 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6718 // If we can emit an efficient shift operation, do so now.
6719 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6722 // If this target supports SHL_PARTS, use it.
6723 TargetLowering::LegalizeAction Action =
6724 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6725 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6726 Action == TargetLowering::Custom) {
6727 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6731 // Otherwise, emit a libcall.
6732 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6737 // If the target wants custom lowering, do so.
6738 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6739 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6740 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6741 Op = TLI.LowerOperation(Op, DAG);
6743 // Now that the custom expander is done, expand the result, which is
6745 ExpandOp(Op, Lo, Hi);
6750 // If we can emit an efficient shift operation, do so now.
6751 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6754 // If this target supports SRA_PARTS, use it.
6755 TargetLowering::LegalizeAction Action =
6756 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6757 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6758 Action == TargetLowering::Custom) {
6759 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6763 // Otherwise, emit a libcall.
6764 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6769 // If the target wants custom lowering, do so.
6770 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6771 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6772 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6773 Op = TLI.LowerOperation(Op, DAG);
6775 // Now that the custom expander is done, expand the result, which is
6777 ExpandOp(Op, Lo, Hi);
6782 // If we can emit an efficient shift operation, do so now.
6783 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6786 // If this target supports SRL_PARTS, use it.
6787 TargetLowering::LegalizeAction Action =
6788 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6789 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6790 Action == TargetLowering::Custom) {
6791 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6795 // Otherwise, emit a libcall.
6796 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6802 // If the target wants to custom expand this, let them.
6803 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6804 TargetLowering::Custom) {
6805 SDValue Result = TLI.LowerOperation(Op, DAG);
6806 if (Result.getNode()) {
6807 ExpandOp(Result, Lo, Hi);
6811 // Expand the subcomponents.
6812 SDValue LHSL, LHSH, RHSL, RHSH;
6813 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6814 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6815 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6816 SDValue LoOps[2], HiOps[3];
6822 //cascaded check to see if any smaller size has a a carry flag.
6823 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6824 bool hasCarry = false;
6825 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6826 MVT AVT = MVT::getIntegerVT(BitSize);
6827 if (TLI.isOperationLegal(OpV, AVT)) {
6834 if (Node->getOpcode() == ISD::ADD) {
6835 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6836 HiOps[2] = Lo.getValue(1);
6837 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6839 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6840 HiOps[2] = Lo.getValue(1);
6841 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6845 if (Node->getOpcode() == ISD::ADD) {
6846 Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
6847 Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
6848 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6849 Lo, LoOps[0], ISD::SETULT);
6850 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
6851 DAG.getConstant(1, NVT),
6852 DAG.getConstant(0, NVT));
6853 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
6854 Lo, LoOps[1], ISD::SETULT);
6855 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
6856 DAG.getConstant(1, NVT),
6858 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
6860 Lo = DAG.getNode(ISD::SUB, VTList, LoOps, 2);
6861 Hi = DAG.getNode(ISD::SUB, VTList, HiOps, 2);
6862 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
6863 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
6864 DAG.getConstant(1, NVT),
6865 DAG.getConstant(0, NVT));
6866 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
6874 // Expand the subcomponents.
6875 SDValue LHSL, LHSH, RHSL, RHSH;
6876 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6877 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6878 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6879 SDValue LoOps[2] = { LHSL, RHSL };
6880 SDValue HiOps[3] = { LHSH, RHSH };
6882 if (Node->getOpcode() == ISD::ADDC) {
6883 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6884 HiOps[2] = Lo.getValue(1);
6885 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6887 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6888 HiOps[2] = Lo.getValue(1);
6889 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6891 // Remember that we legalized the flag.
6892 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6897 // Expand the subcomponents.
6898 SDValue LHSL, LHSH, RHSL, RHSH;
6899 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6900 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6901 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6902 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6903 SDValue HiOps[3] = { LHSH, RHSH };
6905 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6906 HiOps[2] = Lo.getValue(1);
6907 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6909 // Remember that we legalized the flag.
6910 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6914 // If the target wants to custom expand this, let them.
6915 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6916 SDValue New = TLI.LowerOperation(Op, DAG);
6917 if (New.getNode()) {
6918 ExpandOp(New, Lo, Hi);
6923 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6924 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6925 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6926 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6927 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6928 SDValue LL, LH, RL, RH;
6929 ExpandOp(Node->getOperand(0), LL, LH);
6930 ExpandOp(Node->getOperand(1), RL, RH);
6931 unsigned OuterBitSize = Op.getValueSizeInBits();
6932 unsigned InnerBitSize = RH.getValueSizeInBits();
6933 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6934 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6935 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6936 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6937 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6938 // The inputs are both zero-extended.
6940 // We can emit a umul_lohi.
6941 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6942 Hi = SDValue(Lo.getNode(), 1);
6946 // We can emit a mulhu+mul.
6947 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6948 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6952 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6953 // The input values are both sign-extended.
6955 // We can emit a smul_lohi.
6956 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6957 Hi = SDValue(Lo.getNode(), 1);
6961 // We can emit a mulhs+mul.
6962 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6963 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6968 // Lo,Hi = umul LHS, RHS.
6969 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6970 DAG.getVTList(NVT, NVT), LL, RL);
6972 Hi = UMulLOHI.getValue(1);
6973 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6974 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6975 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6976 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6980 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6981 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6982 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6983 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6984 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6985 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6990 // If nothing else, we can make a libcall.
6991 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6995 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6998 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7001 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7004 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7008 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7011 RTLIB::ADD_PPCF128),
7015 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7018 RTLIB::SUB_PPCF128),
7022 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7025 RTLIB::MUL_PPCF128),
7029 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7032 RTLIB::DIV_PPCF128),
7035 case ISD::FP_EXTEND: {
7036 if (VT == MVT::ppcf128) {
7037 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7038 Node->getOperand(0).getValueType()==MVT::f64);
7039 const uint64_t zero = 0;
7040 if (Node->getOperand(0).getValueType()==MVT::f32)
7041 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
7043 Hi = Node->getOperand(0);
7044 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7047 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7048 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7049 Lo = ExpandLibCall(LC, Node, true, Hi);
7052 case ISD::FP_ROUND: {
7053 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7055 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7056 Lo = ExpandLibCall(LC, Node, true, Hi);
7071 case ISD::FNEARBYINT:
7074 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7075 switch(Node->getOpcode()) {
7077 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7078 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7081 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7082 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7085 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7086 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7089 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7090 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7093 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7094 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7097 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7098 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7101 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7102 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7105 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7106 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7109 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7110 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7113 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7114 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7117 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7118 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7121 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7122 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7124 case ISD::FNEARBYINT:
7125 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7126 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7129 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7130 RTLIB::POW_PPCF128);
7133 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7134 RTLIB::POWI_PPCF128);
7136 default: assert(0 && "Unreachable!");
7138 Lo = ExpandLibCall(LC, Node, false, Hi);
7142 if (VT == MVT::ppcf128) {
7144 ExpandOp(Node->getOperand(0), Lo, Tmp);
7145 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7146 // lo = hi==fabs(hi) ? lo : -lo;
7147 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7148 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7149 DAG.getCondCode(ISD::SETEQ));
7152 SDValue Mask = (VT == MVT::f64)
7153 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7154 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7155 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7156 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7157 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7158 if (getTypeAction(NVT) == Expand)
7159 ExpandOp(Lo, Lo, Hi);
7163 if (VT == MVT::ppcf128) {
7164 ExpandOp(Node->getOperand(0), Lo, Hi);
7165 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7166 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7169 SDValue Mask = (VT == MVT::f64)
7170 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7171 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7172 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7173 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7174 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7175 if (getTypeAction(NVT) == Expand)
7176 ExpandOp(Lo, Lo, Hi);
7179 case ISD::FCOPYSIGN: {
7180 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7181 if (getTypeAction(NVT) == Expand)
7182 ExpandOp(Lo, Lo, Hi);
7185 case ISD::SINT_TO_FP:
7186 case ISD::UINT_TO_FP: {
7187 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7188 MVT SrcVT = Node->getOperand(0).getValueType();
7190 // Promote the operand if needed. Do this before checking for
7191 // ppcf128 so conversions of i16 and i8 work.
7192 if (getTypeAction(SrcVT) == Promote) {
7193 SDValue Tmp = PromoteOp(Node->getOperand(0));
7195 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7196 DAG.getValueType(SrcVT))
7197 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7198 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7199 SrcVT = Node->getOperand(0).getValueType();
7202 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7203 static const uint64_t zero = 0;
7205 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7206 Node->getOperand(0)));
7207 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7209 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7210 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7211 Node->getOperand(0)));
7212 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7213 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7214 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7215 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7216 DAG.getConstant(0, MVT::i32),
7217 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7219 APFloat(APInt(128, 2, TwoE32)),
7222 DAG.getCondCode(ISD::SETLT)),
7227 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7228 // si64->ppcf128 done by libcall, below
7229 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7230 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7232 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7233 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7234 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7235 DAG.getConstant(0, MVT::i64),
7236 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7238 APFloat(APInt(128, 2, TwoE64)),
7241 DAG.getCondCode(ISD::SETLT)),
7246 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7247 Node->getOperand(0));
7248 if (getTypeAction(Lo.getValueType()) == Expand)
7249 // float to i32 etc. can be 'expanded' to a single node.
7250 ExpandOp(Lo, Lo, Hi);
7255 // Make sure the resultant values have been legalized themselves, unless this
7256 // is a type that requires multi-step expansion.
7257 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7258 Lo = LegalizeOp(Lo);
7260 // Don't legalize the high part if it is expanded to a single node.
7261 Hi = LegalizeOp(Hi);
7264 // Remember in a map if the values will be reused later.
7266 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7267 assert(isNew && "Value already expanded?!?");
7271 /// SplitVectorOp - Given an operand of vector type, break it down into
7272 /// two smaller values, still of vector type.
7273 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7275 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7276 SDNode *Node = Op.getNode();
7277 unsigned NumElements = Op.getValueType().getVectorNumElements();
7278 assert(NumElements > 1 && "Cannot split a single element vector!");
7280 MVT NewEltVT = Op.getValueType().getVectorElementType();
7282 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7283 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7285 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7286 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7288 // See if we already split it.
7289 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7290 = SplitNodes.find(Op);
7291 if (I != SplitNodes.end()) {
7292 Lo = I->second.first;
7293 Hi = I->second.second;
7297 switch (Node->getOpcode()) {
7302 assert(0 && "Unhandled operation in SplitVectorOp!");
7304 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7305 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7307 case ISD::BUILD_PAIR:
7308 Lo = Node->getOperand(0);
7309 Hi = Node->getOperand(1);
7311 case ISD::INSERT_VECTOR_ELT: {
7312 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7313 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7314 unsigned Index = Idx->getZExtValue();
7315 SDValue ScalarOp = Node->getOperand(1);
7316 if (Index < NewNumElts_Lo)
7317 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7318 DAG.getIntPtrConstant(Index));
7320 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7321 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7324 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7325 Node->getOperand(1),
7326 Node->getOperand(2));
7327 SplitVectorOp(Tmp, Lo, Hi);
7330 case ISD::VECTOR_SHUFFLE: {
7331 // Build the low part.
7332 SDValue Mask = Node->getOperand(2);
7333 SmallVector<SDValue, 8> Ops;
7334 MVT PtrVT = TLI.getPointerTy();
7336 // Insert all of the elements from the input that are needed. We use
7337 // buildvector of extractelement here because the input vectors will have
7338 // to be legalized, so this makes the code simpler.
7339 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7340 SDValue IdxNode = Mask.getOperand(i);
7341 if (IdxNode.getOpcode() == ISD::UNDEF) {
7342 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7345 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7346 SDValue InVec = Node->getOperand(0);
7347 if (Idx >= NumElements) {
7348 InVec = Node->getOperand(1);
7351 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7352 DAG.getConstant(Idx, PtrVT)));
7354 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7357 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7358 SDValue IdxNode = Mask.getOperand(i);
7359 if (IdxNode.getOpcode() == ISD::UNDEF) {
7360 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7363 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7364 SDValue InVec = Node->getOperand(0);
7365 if (Idx >= NumElements) {
7366 InVec = Node->getOperand(1);
7369 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7370 DAG.getConstant(Idx, PtrVT)));
7372 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7375 case ISD::BUILD_VECTOR: {
7376 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7377 Node->op_begin()+NewNumElts_Lo);
7378 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7380 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7382 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7385 case ISD::CONCAT_VECTORS: {
7386 // FIXME: Handle non-power-of-two vectors?
7387 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7388 if (NewNumSubvectors == 1) {
7389 Lo = Node->getOperand(0);
7390 Hi = Node->getOperand(1);
7392 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7393 Node->op_begin()+NewNumSubvectors);
7394 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7396 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7398 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7402 case ISD::EXTRACT_SUBVECTOR: {
7403 SDValue Vec = Op.getOperand(0);
7404 SDValue Idx = Op.getOperand(1);
7405 MVT IdxVT = Idx.getValueType();
7407 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7408 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7410 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7411 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7414 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7415 DAG.getConstant(NewNumElts_Lo, IdxVT));
7416 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7421 SDValue Cond = Node->getOperand(0);
7423 SDValue LL, LH, RL, RH;
7424 SplitVectorOp(Node->getOperand(1), LL, LH);
7425 SplitVectorOp(Node->getOperand(2), RL, RH);
7427 if (Cond.getValueType().isVector()) {
7428 // Handle a vector merge.
7430 SplitVectorOp(Cond, CL, CH);
7431 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7432 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7434 // Handle a simple select with vector operands.
7435 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7436 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7440 case ISD::SELECT_CC: {
7441 SDValue CondLHS = Node->getOperand(0);
7442 SDValue CondRHS = Node->getOperand(1);
7443 SDValue CondCode = Node->getOperand(4);
7445 SDValue LL, LH, RL, RH;
7446 SplitVectorOp(Node->getOperand(2), LL, LH);
7447 SplitVectorOp(Node->getOperand(3), RL, RH);
7449 // Handle a simple select with vector operands.
7450 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7452 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7457 SDValue LL, LH, RL, RH;
7458 SplitVectorOp(Node->getOperand(0), LL, LH);
7459 SplitVectorOp(Node->getOperand(1), RL, RH);
7460 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7461 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7480 SDValue LL, LH, RL, RH;
7481 SplitVectorOp(Node->getOperand(0), LL, LH);
7482 SplitVectorOp(Node->getOperand(1), RL, RH);
7484 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7485 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7491 SplitVectorOp(Node->getOperand(0), L, H);
7493 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7494 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7510 case ISD::FP_TO_SINT:
7511 case ISD::FP_TO_UINT:
7512 case ISD::SINT_TO_FP:
7513 case ISD::UINT_TO_FP:
7515 case ISD::ANY_EXTEND:
7516 case ISD::SIGN_EXTEND:
7517 case ISD::ZERO_EXTEND:
7518 case ISD::FP_EXTEND: {
7520 SplitVectorOp(Node->getOperand(0), L, H);
7522 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7523 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7526 case ISD::CONVERT_RNDSAT: {
7527 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7529 SplitVectorOp(Node->getOperand(0), L, H);
7530 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7531 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7532 SDValue STyOpL = DAG.getValueType(L.getValueType());
7533 SDValue STyOpH = DAG.getValueType(H.getValueType());
7535 SDValue RndOp = Node->getOperand(3);
7536 SDValue SatOp = Node->getOperand(4);
7538 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7539 RndOp, SatOp, CvtCode);
7540 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7541 RndOp, SatOp, CvtCode);
7545 LoadSDNode *LD = cast<LoadSDNode>(Node);
7546 SDValue Ch = LD->getChain();
7547 SDValue Ptr = LD->getBasePtr();
7548 ISD::LoadExtType ExtType = LD->getExtensionType();
7549 const Value *SV = LD->getSrcValue();
7550 int SVOffset = LD->getSrcValueOffset();
7551 MVT MemoryVT = LD->getMemoryVT();
7552 unsigned Alignment = LD->getAlignment();
7553 bool isVolatile = LD->isVolatile();
7555 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7556 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7558 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7559 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7560 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7562 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7563 NewVT_Lo, Ch, Ptr, Offset,
7564 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7565 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7566 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7567 DAG.getIntPtrConstant(IncrementSize));
7568 SVOffset += IncrementSize;
7569 Alignment = MinAlign(Alignment, IncrementSize);
7570 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7571 NewVT_Hi, Ch, Ptr, Offset,
7572 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7574 // Build a factor node to remember that this load is independent of the
7576 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7579 // Remember that we legalized the chain.
7580 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7583 case ISD::BIT_CONVERT: {
7584 // We know the result is a vector. The input may be either a vector or a
7586 SDValue InOp = Node->getOperand(0);
7587 if (!InOp.getValueType().isVector() ||
7588 InOp.getValueType().getVectorNumElements() == 1) {
7589 // The input is a scalar or single-element vector.
7590 // Lower to a store/load so that it can be split.
7591 // FIXME: this could be improved probably.
7592 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7593 Op.getValueType().getTypeForMVT());
7594 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7595 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7597 SDValue St = DAG.getStore(DAG.getEntryNode(),
7599 PseudoSourceValue::getFixedStack(FI), 0);
7600 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7601 PseudoSourceValue::getFixedStack(FI), 0);
7603 // Split the vector and convert each of the pieces now.
7604 SplitVectorOp(InOp, Lo, Hi);
7605 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7606 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7611 // Remember in a map if the values will be reused later.
7613 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7614 assert(isNew && "Value already split?!?");
7619 /// ScalarizeVectorOp - Given an operand of single-element vector type
7620 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7621 /// scalar (e.g. f32) value.
7622 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7623 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7624 SDNode *Node = Op.getNode();
7625 MVT NewVT = Op.getValueType().getVectorElementType();
7626 assert(Op.getValueType().getVectorNumElements() == 1);
7628 // See if we already scalarized it.
7629 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7630 if (I != ScalarizedNodes.end()) return I->second;
7633 switch (Node->getOpcode()) {
7636 Node->dump(&DAG); cerr << "\n";
7638 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7655 Result = DAG.getNode(Node->getOpcode(),
7657 ScalarizeVectorOp(Node->getOperand(0)),
7658 ScalarizeVectorOp(Node->getOperand(1)));
7670 case ISD::FP_TO_SINT:
7671 case ISD::FP_TO_UINT:
7672 case ISD::SINT_TO_FP:
7673 case ISD::UINT_TO_FP:
7674 case ISD::SIGN_EXTEND:
7675 case ISD::ZERO_EXTEND:
7676 case ISD::ANY_EXTEND:
7678 case ISD::FP_EXTEND:
7679 Result = DAG.getNode(Node->getOpcode(),
7681 ScalarizeVectorOp(Node->getOperand(0)));
7683 case ISD::CONVERT_RNDSAT: {
7684 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7685 Result = DAG.getConvertRndSat(NewVT, Op0,
7686 DAG.getValueType(NewVT),
7687 DAG.getValueType(Op0.getValueType()),
7688 Node->getOperand(3),
7689 Node->getOperand(4),
7690 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7695 Result = DAG.getNode(Node->getOpcode(),
7697 ScalarizeVectorOp(Node->getOperand(0)),
7698 Node->getOperand(1));
7701 LoadSDNode *LD = cast<LoadSDNode>(Node);
7702 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7703 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7704 ISD::LoadExtType ExtType = LD->getExtensionType();
7705 const Value *SV = LD->getSrcValue();
7706 int SVOffset = LD->getSrcValueOffset();
7707 MVT MemoryVT = LD->getMemoryVT();
7708 unsigned Alignment = LD->getAlignment();
7709 bool isVolatile = LD->isVolatile();
7711 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7712 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7714 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7715 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7716 MemoryVT.getVectorElementType(),
7717 isVolatile, Alignment);
7719 // Remember that we legalized the chain.
7720 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7723 case ISD::BUILD_VECTOR:
7724 Result = Node->getOperand(0);
7726 case ISD::INSERT_VECTOR_ELT:
7727 // Returning the inserted scalar element.
7728 Result = Node->getOperand(1);
7730 case ISD::CONCAT_VECTORS:
7731 assert(Node->getOperand(0).getValueType() == NewVT &&
7732 "Concat of non-legal vectors not yet supported!");
7733 Result = Node->getOperand(0);
7735 case ISD::VECTOR_SHUFFLE: {
7736 // Figure out if the scalar is the LHS or RHS and return it.
7737 SDValue EltNum = Node->getOperand(2).getOperand(0);
7738 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7739 Result = ScalarizeVectorOp(Node->getOperand(1));
7741 Result = ScalarizeVectorOp(Node->getOperand(0));
7744 case ISD::EXTRACT_SUBVECTOR:
7745 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7746 Node->getOperand(1));
7748 case ISD::BIT_CONVERT: {
7749 SDValue Op0 = Op.getOperand(0);
7750 if (Op0.getValueType().getVectorNumElements() == 1)
7751 Op0 = ScalarizeVectorOp(Op0);
7752 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7756 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7757 ScalarizeVectorOp(Op.getOperand(1)),
7758 ScalarizeVectorOp(Op.getOperand(2)));
7760 case ISD::SELECT_CC:
7761 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7762 Node->getOperand(1),
7763 ScalarizeVectorOp(Op.getOperand(2)),
7764 ScalarizeVectorOp(Op.getOperand(3)),
7765 Node->getOperand(4));
7768 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7769 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7770 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7772 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7773 DAG.getConstant(-1ULL, NewVT),
7774 DAG.getConstant(0ULL, NewVT));
7779 if (TLI.isTypeLegal(NewVT))
7780 Result = LegalizeOp(Result);
7781 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7782 assert(isNew && "Value already scalarized?");
7788 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7789 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7790 if (I != WidenNodes.end()) return I->second;
7792 MVT VT = Op.getValueType();
7793 assert(VT.isVector() && "Cannot widen non-vector type!");
7796 SDNode *Node = Op.getNode();
7797 MVT EVT = VT.getVectorElementType();
7799 unsigned NumElts = VT.getVectorNumElements();
7800 unsigned NewNumElts = WidenVT.getVectorNumElements();
7801 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7802 assert(NewNumElts < 17);
7804 // When widen is called, it is assumed that it is more efficient to use a
7805 // wide type. The default action is to widen to operation to a wider legal
7806 // vector type and then do the operation if it is legal by calling LegalizeOp
7807 // again. If there is no vector equivalent, we will unroll the operation, do
7808 // it, and rebuild the vector. If most of the operations are vectorizible to
7809 // the legal type, the resulting code will be more efficient. If this is not
7810 // the case, the resulting code will preform badly as we end up generating
7811 // code to pack/unpack the results. It is the function that calls widen
7812 // that is responsible for seeing this doesn't happen.
7813 switch (Node->getOpcode()) {
7818 assert(0 && "Unexpected operation in WidenVectorOp!");
7820 case ISD::CopyFromReg:
7821 assert(0 && "CopyFromReg doesn't need widening!");
7823 case ISD::ConstantFP:
7824 // To build a vector of these elements, clients should call BuildVector
7825 // and with each element instead of creating a node with a vector type
7826 assert(0 && "Unexpected operation in WidenVectorOp!");
7828 // Variable Arguments with vector types doesn't make any sense to me
7829 assert(0 && "Unexpected operation in WidenVectorOp!");
7832 Result = DAG.getNode(ISD::UNDEF, WidenVT);
7834 case ISD::BUILD_VECTOR: {
7835 // Build a vector with undefined for the new nodes
7836 SDValueVector NewOps(Node->op_begin(), Node->op_end());
7837 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7838 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
7840 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
7843 case ISD::INSERT_VECTOR_ELT: {
7844 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7845 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
7846 Node->getOperand(1), Node->getOperand(2));
7849 case ISD::VECTOR_SHUFFLE: {
7850 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7851 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
7852 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
7853 // used as permutation array. We build the vector here instead of widening
7854 // because we don't want to legalize and have it turned to something else.
7855 SDValue PermOp = Node->getOperand(2);
7856 SDValueVector NewOps;
7857 MVT PVT = PermOp.getValueType().getVectorElementType();
7858 for (unsigned i = 0; i < NumElts; ++i) {
7859 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
7860 NewOps.push_back(PermOp.getOperand(i));
7863 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
7864 if (Idx < NumElts) {
7865 NewOps.push_back(PermOp.getOperand(i));
7868 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
7869 PermOp.getOperand(i).getValueType()));
7873 for (unsigned i = NumElts; i < NewNumElts; ++i) {
7874 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
7877 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
7878 MVT::getVectorVT(PVT, NewOps.size()),
7879 &NewOps[0], NewOps.size());
7881 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
7885 // If the load widen returns true, we can use a single load for the
7886 // vector. Otherwise, it is returning a token factor for multiple
7889 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
7890 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
7892 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
7896 case ISD::BIT_CONVERT: {
7897 SDValue Tmp1 = Node->getOperand(0);
7898 // Converts between two different types so we need to determine
7899 // the correct widen type for the input operand.
7900 MVT TVT = Tmp1.getValueType();
7901 assert(TVT.isVector() && "can not widen non vector type");
7902 MVT TEVT = TVT.getVectorElementType();
7903 assert(WidenVT.getSizeInBits() % EVT.getSizeInBits() == 0 &&
7904 "can not widen bit bit convert that are not multiple of element type");
7905 MVT TWidenVT = MVT::getVectorVT(TEVT,
7906 WidenVT.getSizeInBits()/EVT.getSizeInBits());
7907 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7908 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
7909 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7911 TargetLowering::LegalizeAction action =
7912 TLI.getOperationAction(Node->getOpcode(), WidenVT);
7914 default: assert(0 && "action not supported");
7915 case TargetLowering::Legal:
7917 case TargetLowering::Promote:
7918 // We defer the promotion to when we legalize the op
7920 case TargetLowering::Expand:
7921 // Expand the operation into a bunch of nasty scalar code.
7922 Result = LegalizeOp(UnrollVectorOp(Result));
7928 case ISD::SINT_TO_FP:
7929 case ISD::UINT_TO_FP:
7930 case ISD::FP_TO_SINT:
7931 case ISD::FP_TO_UINT: {
7932 SDValue Tmp1 = Node->getOperand(0);
7933 // Converts between two different types so we need to determine
7934 // the correct widen type for the input operand.
7935 MVT TVT = Tmp1.getValueType();
7936 assert(TVT.isVector() && "can not widen non vector type");
7937 MVT TEVT = TVT.getVectorElementType();
7938 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
7939 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
7940 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
7941 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7945 case ISD::FP_EXTEND:
7946 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
7948 case ISD::SIGN_EXTEND:
7949 case ISD::ZERO_EXTEND:
7950 case ISD::ANY_EXTEND:
7952 case ISD::SIGN_EXTEND_INREG:
7961 // Unary op widening
7963 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
7964 assert(Tmp1.getValueType() == WidenVT);
7965 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
7968 case ISD::CONVERT_RNDSAT: {
7969 SDValue RndOp = Node->getOperand(3);
7970 SDValue SatOp = Node->getOperand(4);
7971 SDValue SrcOp = Node->getOperand(0);
7973 // Converts between two different types so we need to determine
7974 // the correct widen type for the input operand.
7975 MVT SVT = SrcOp.getValueType();
7976 assert(SVT.isVector() && "can not widen non vector type");
7977 MVT SEVT = SVT.getVectorElementType();
7978 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
7980 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
7981 assert(SrcOp.getValueType() == WidenVT);
7982 SDValue DTyOp = DAG.getValueType(WidenVT);
7983 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
7984 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7986 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
7987 RndOp, SatOp, CvtCode);
8007 case ISD::FCOPYSIGN:
8011 // Binary op widening
8012 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8013 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8014 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8015 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
8022 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8023 assert(Tmp1.getValueType() == WidenVT);
8024 SDValue ShOp = Node->getOperand(1);
8025 MVT ShVT = ShOp.getValueType();
8026 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8027 WidenVT.getVectorNumElements());
8028 ShOp = WidenVectorOp(ShOp, NewShVT);
8029 assert(ShOp.getValueType() == NewShVT);
8030 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp);
8034 case ISD::EXTRACT_VECTOR_ELT: {
8035 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8036 assert(Tmp1.getValueType() == WidenVT);
8037 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
8040 case ISD::CONCAT_VECTORS: {
8041 // We concurrently support only widen on a multiple of the incoming vector.
8042 // We could widen on a multiple of the incoming operand if necessary.
8043 unsigned NumConcat = NewNumElts / NumElts;
8044 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8045 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8046 SmallVector<SDValue, 8> MOps;
8048 for (unsigned i = 1; i != NumConcat; ++i) {
8049 MOps.push_back(UndefVal);
8051 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8052 &MOps[0], MOps.size()));
8055 case ISD::EXTRACT_SUBVECTOR: {
8056 SDValue Tmp1 = Node->getOperand(0);
8057 SDValue Idx = Node->getOperand(1);
8058 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8059 if (CIdx && CIdx->getZExtValue() == 0) {
8060 // Since we are access the start of the vector, the incoming
8061 // vector type might be the proper.
8062 MVT Tmp1VT = Tmp1.getValueType();
8063 if (Tmp1VT == WidenVT)
8066 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8067 if (Tmp1VTNumElts < NewNumElts)
8068 Result = WidenVectorOp(Tmp1, WidenVT);
8070 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8072 } else if (NewNumElts % NumElts == 0) {
8073 // Widen the extracted subvector.
8074 unsigned NumConcat = NewNumElts / NumElts;
8075 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8076 SmallVector<SDValue, 8> MOps;
8078 for (unsigned i = 1; i != NumConcat; ++i) {
8079 MOps.push_back(UndefVal);
8081 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8082 &MOps[0], MOps.size()));
8084 assert(0 && "can not widen extract subvector");
8085 // This could be implemented using insert and build vector but I would
8086 // like to see when this happens.
8092 // Determine new condition widen type and widen
8093 SDValue Cond1 = Node->getOperand(0);
8094 MVT CondVT = Cond1.getValueType();
8095 assert(CondVT.isVector() && "can not widen non vector type");
8096 MVT CondEVT = CondVT.getVectorElementType();
8097 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8098 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8099 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8101 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8102 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8103 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8104 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8108 case ISD::SELECT_CC: {
8109 // Determine new condition widen type and widen
8110 SDValue Cond1 = Node->getOperand(0);
8111 SDValue Cond2 = Node->getOperand(1);
8112 MVT CondVT = Cond1.getValueType();
8113 assert(CondVT.isVector() && "can not widen non vector type");
8114 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8115 MVT CondEVT = CondVT.getVectorElementType();
8116 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8117 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8118 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8119 assert(Cond1.getValueType() == CondWidenVT &&
8120 Cond2.getValueType() == CondWidenVT && "condition not widen");
8122 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8123 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8124 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8125 "operands not widen");
8126 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8127 Tmp2, Node->getOperand(4));
8131 // Determine widen for the operand
8132 SDValue Tmp1 = Node->getOperand(0);
8133 MVT TmpVT = Tmp1.getValueType();
8134 assert(TmpVT.isVector() && "can not widen non vector type");
8135 MVT TmpEVT = TmpVT.getVectorElementType();
8136 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8137 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8138 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8139 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8140 Node->getOperand(2));
8143 case ISD::ATOMIC_CMP_SWAP_8:
8144 case ISD::ATOMIC_CMP_SWAP_16:
8145 case ISD::ATOMIC_CMP_SWAP_32:
8146 case ISD::ATOMIC_CMP_SWAP_64:
8147 case ISD::ATOMIC_LOAD_ADD_8:
8148 case ISD::ATOMIC_LOAD_SUB_8:
8149 case ISD::ATOMIC_LOAD_AND_8:
8150 case ISD::ATOMIC_LOAD_OR_8:
8151 case ISD::ATOMIC_LOAD_XOR_8:
8152 case ISD::ATOMIC_LOAD_NAND_8:
8153 case ISD::ATOMIC_LOAD_MIN_8:
8154 case ISD::ATOMIC_LOAD_MAX_8:
8155 case ISD::ATOMIC_LOAD_UMIN_8:
8156 case ISD::ATOMIC_LOAD_UMAX_8:
8157 case ISD::ATOMIC_SWAP_8:
8158 case ISD::ATOMIC_LOAD_ADD_16:
8159 case ISD::ATOMIC_LOAD_SUB_16:
8160 case ISD::ATOMIC_LOAD_AND_16:
8161 case ISD::ATOMIC_LOAD_OR_16:
8162 case ISD::ATOMIC_LOAD_XOR_16:
8163 case ISD::ATOMIC_LOAD_NAND_16:
8164 case ISD::ATOMIC_LOAD_MIN_16:
8165 case ISD::ATOMIC_LOAD_MAX_16:
8166 case ISD::ATOMIC_LOAD_UMIN_16:
8167 case ISD::ATOMIC_LOAD_UMAX_16:
8168 case ISD::ATOMIC_SWAP_16:
8169 case ISD::ATOMIC_LOAD_ADD_32:
8170 case ISD::ATOMIC_LOAD_SUB_32:
8171 case ISD::ATOMIC_LOAD_AND_32:
8172 case ISD::ATOMIC_LOAD_OR_32:
8173 case ISD::ATOMIC_LOAD_XOR_32:
8174 case ISD::ATOMIC_LOAD_NAND_32:
8175 case ISD::ATOMIC_LOAD_MIN_32:
8176 case ISD::ATOMIC_LOAD_MAX_32:
8177 case ISD::ATOMIC_LOAD_UMIN_32:
8178 case ISD::ATOMIC_LOAD_UMAX_32:
8179 case ISD::ATOMIC_SWAP_32:
8180 case ISD::ATOMIC_LOAD_ADD_64:
8181 case ISD::ATOMIC_LOAD_SUB_64:
8182 case ISD::ATOMIC_LOAD_AND_64:
8183 case ISD::ATOMIC_LOAD_OR_64:
8184 case ISD::ATOMIC_LOAD_XOR_64:
8185 case ISD::ATOMIC_LOAD_NAND_64:
8186 case ISD::ATOMIC_LOAD_MIN_64:
8187 case ISD::ATOMIC_LOAD_MAX_64:
8188 case ISD::ATOMIC_LOAD_UMIN_64:
8189 case ISD::ATOMIC_LOAD_UMAX_64:
8190 case ISD::ATOMIC_SWAP_64: {
8191 // For now, we assume that using vectors for these operations don't make
8192 // much sense so we just split it. We return an empty result
8194 SplitVectorOp(Op, X, Y);
8199 } // end switch (Node->getOpcode())
8201 assert(Result.getNode() && "Didn't set a result!");
8203 Result = LegalizeOp(Result);
8205 AddWidenedOperand(Op, Result);
8209 // Utility function to find a legal vector type and its associated element
8210 // type from a preferred width and whose vector type must be the same size
8212 // TLI: Target lowering used to determine legal types
8213 // Width: Preferred width of element type
8214 // VVT: Vector value type whose size we must match.
8215 // Returns VecEVT and EVT - the vector type and its associated element type
8216 static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
8217 MVT& EVT, MVT& VecEVT) {
8218 // We start with the preferred width, make it a power of 2 and see if
8219 // we can find a vector type of that width. If not, we reduce it by
8220 // another power of 2. If we have widen the type, a vector of bytes should
8222 assert(TLI.isTypeLegal(VVT));
8223 unsigned EWidth = Width + 1;
8226 EWidth = (1 << Log2_32(EWidth-1));
8227 EVT = MVT::getIntegerVT(EWidth);
8228 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8229 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8230 } while (!TLI.isTypeLegal(VecEVT) ||
8231 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8234 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8243 // We assume that we have good rules to handle loading power of two loads so
8244 // we break down the operations to power of 2 loads. The strategy is to
8245 // load the largest power of 2 that we can easily transform to a legal vector
8246 // and then insert into that vector, and the cast the result into the legal
8247 // vector that we want. This avoids unnecessary stack converts.
8248 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8249 // the load is nonvolatile, we an use a wider load for the value.
8250 // Find a vector length we can load a large chunk
8253 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8254 EVTWidth = EVT.getSizeInBits();
8256 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8257 isVolatile, Alignment);
8258 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8259 LdChain.push_back(LdOp.getValue(1));
8261 // Check if we can load the element with one instruction
8262 if (LdWidth == EVTWidth) {
8263 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8266 // The vector element order is endianness dependent.
8268 LdWidth -= EVTWidth;
8269 unsigned Offset = 0;
8271 while (LdWidth > 0) {
8272 unsigned Increment = EVTWidth / 8;
8273 Offset += Increment;
8274 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8275 DAG.getIntPtrConstant(Increment));
8277 if (LdWidth < EVTWidth) {
8278 // Our current type we are using is too large, use a smaller size by
8279 // using a smaller power of 2
8280 unsigned oEVTWidth = EVTWidth;
8281 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8282 EVTWidth = EVT.getSizeInBits();
8283 // Readjust position and vector position based on new load type
8284 Idx = Idx * (oEVTWidth/EVTWidth);
8285 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8288 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8289 SVOffset+Offset, isVolatile,
8290 MinAlign(Alignment, Offset));
8291 LdChain.push_back(LdOp.getValue(1));
8292 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8293 DAG.getIntPtrConstant(Idx++));
8295 LdWidth -= EVTWidth;
8298 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8301 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8305 // TODO: Add support for ConcatVec and the ability to load many vector
8306 // types (e.g., v4i8). This will not work when a vector register
8307 // to memory mapping is strange (e.g., vector elements are not
8308 // stored in some sequential order).
8310 // It must be true that the widen vector type is bigger than where
8311 // we need to load from.
8312 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8313 MVT LdVT = LD->getMemoryVT();
8314 assert(LdVT.isVector() && NVT.isVector());
8315 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8318 SDValue Chain = LD->getChain();
8319 SDValue BasePtr = LD->getBasePtr();
8320 int SVOffset = LD->getSrcValueOffset();
8321 unsigned Alignment = LD->getAlignment();
8322 bool isVolatile = LD->isVolatile();
8323 const Value *SV = LD->getSrcValue();
8324 unsigned int LdWidth = LdVT.getSizeInBits();
8326 // Load value as a large register
8327 SDValueVector LdChain;
8328 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8329 Alignment, isVolatile, LdWidth, NVT);
8331 if (LdChain.size() == 1) {
8336 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8342 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8351 // Breaks the stores into a series of power of 2 width stores. For any
8352 // width, we convert the vector to the vector of element size that we
8353 // want to store. This avoids requiring a stack convert.
8355 // Find a width of the element type we can store with
8356 MVT VVT = ValOp.getValueType();
8359 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8360 EVTWidth = EVT.getSizeInBits();
8362 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8363 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8364 DAG.getIntPtrConstant(0));
8365 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8366 isVolatile, Alignment);
8367 StChain.push_back(StOp);
8369 // Check if we are done
8370 if (StWidth == EVTWidth) {
8375 StWidth -= EVTWidth;
8376 unsigned Offset = 0;
8378 while (StWidth > 0) {
8379 unsigned Increment = EVTWidth / 8;
8380 Offset += Increment;
8381 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8382 DAG.getIntPtrConstant(Increment));
8384 if (StWidth < EVTWidth) {
8385 // Our current type we are using is too large, use a smaller size by
8386 // using a smaller power of 2
8387 unsigned oEVTWidth = EVTWidth;
8388 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8389 EVTWidth = EVT.getSizeInBits();
8390 // Readjust position and vector position based on new load type
8391 Idx = Idx * (oEVTWidth/EVTWidth);
8392 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8395 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8396 DAG.getIntPtrConstant(Idx++));
8397 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8398 SVOffset + Offset, isVolatile,
8399 MinAlign(Alignment, Offset)));
8400 StWidth -= EVTWidth;
8405 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8408 // TODO: It might be cleaner if we can use SplitVector and have more legal
8409 // vector types that can be stored into memory (e.g., v4xi8 can
8410 // be stored as a word). This will not work when a vector register
8411 // to memory mapping is strange (e.g., vector elements are not
8412 // stored in some sequential order).
8414 MVT StVT = ST->getMemoryVT();
8415 SDValue ValOp = ST->getValue();
8417 // Check if we have widen this node with another value
8418 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8419 if (I != WidenNodes.end())
8422 MVT VVT = ValOp.getValueType();
8424 // It must be true that we the widen vector type is bigger than where
8425 // we need to store.
8426 assert(StVT.isVector() && VVT.isVector());
8427 assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8428 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8431 SDValueVector StChain;
8432 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8433 ST->getSrcValueOffset(), ST->getAlignment(),
8434 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8435 if (StChain.size() == 1)
8438 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8442 // SelectionDAG::Legalize - This is the entry point for the file.
8444 void SelectionDAG::Legalize() {
8445 /// run - This is the main entry point to this class.
8447 SelectionDAGLegalize(*this).LegalizeDAG();