1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetLowering.h"
20 #include "llvm/Target/TargetData.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Compiler.h"
29 #include "llvm/ADT/DenseMap.h"
30 #include "llvm/ADT/SmallVector.h"
31 #include "llvm/ADT/SmallPtrSet.h"
37 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
38 cl::desc("Pop up a window to show dags before legalize"));
40 static const bool ViewLegalizeDAGs = 0;
43 //===----------------------------------------------------------------------===//
44 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
45 /// hacks on it until the target machine can handle it. This involves
46 /// eliminating value sizes the machine cannot handle (promoting small sizes to
47 /// large sizes or splitting up large values into small values) as well as
48 /// eliminating operations the machine cannot handle.
50 /// This code also does a small amount of optimization and recognition of idioms
51 /// as part of its processing. For example, if a target does not support a
52 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
53 /// will attempt merge setcc and brc instructions into brcc's.
56 class VISIBILITY_HIDDEN SelectionDAGLegalize {
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDOperand LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDOperand, SDOperand> LegalizedNodes;
88 /// PromotedNodes - For nodes that are below legal width, and that have more
89 /// than one use, this map indicates what promoted value to use. This allows
90 /// us to avoid promoting the same thing more than once.
91 DenseMap<SDOperand, SDOperand> PromotedNodes;
93 /// ExpandedNodes - For nodes that need to be expanded this map indicates
94 /// which which operands are the expanded version of the input. This allows
95 /// us to avoid expanding the same node more than once.
96 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
98 /// SplitNodes - For vector nodes that need to be split, this map indicates
99 /// which which operands are the split version of the input. This allows us
100 /// to avoid splitting the same node more than once.
101 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
103 /// ScalarizedNodes - For nodes that need to be converted from vector types to
104 /// scalar types, this contains the mapping of ones we have already
105 /// processed to the result.
106 std::map<SDOperand, SDOperand> ScalarizedNodes;
108 void AddLegalizedOperand(SDOperand From, SDOperand To) {
109 LegalizedNodes.insert(std::make_pair(From, To));
110 // If someone requests legalization of the new node, return itself.
112 LegalizedNodes.insert(std::make_pair(To, To));
114 void AddPromotedOperand(SDOperand From, SDOperand To) {
115 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
116 assert(isNew && "Got into the map somehow?");
117 // If someone requests legalization of the new node, return itself.
118 LegalizedNodes.insert(std::make_pair(To, To));
123 SelectionDAGLegalize(SelectionDAG &DAG);
125 /// getTypeAction - Return how we should legalize values of this type, either
126 /// it is already legal or we need to expand it into multiple registers of
127 /// smaller integer type, or we need to promote it to a larger type.
128 LegalizeAction getTypeAction(MVT::ValueType VT) const {
129 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
132 /// isTypeLegal - Return true if this type is legal on this target.
134 bool isTypeLegal(MVT::ValueType VT) const {
135 return getTypeAction(VT) == Legal;
141 /// HandleOp - Legalize, Promote, or Expand the specified operand as
142 /// appropriate for its type.
143 void HandleOp(SDOperand Op);
145 /// LegalizeOp - We know that the specified value has a legal type.
146 /// Recursively ensure that the operands have legal types, then return the
148 SDOperand LegalizeOp(SDOperand O);
150 /// PromoteOp - Given an operation that produces a value in an invalid type,
151 /// promote it to compute the value into a larger type. The produced value
152 /// will have the correct bits for the low portion of the register, but no
153 /// guarantee is made about the top bits: it may be zero, sign-extended, or
155 SDOperand PromoteOp(SDOperand O);
157 /// ExpandOp - Expand the specified SDOperand into its two component pieces
158 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
159 /// the LegalizeNodes map is filled in for any results that are not expanded,
160 /// the ExpandedNodes map is filled in for any results that are expanded, and
161 /// the Lo/Hi values are returned. This applies to integer types and Vector
163 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
165 /// SplitVectorOp - Given an operand of vector type, break it down into
166 /// two smaller values.
167 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
169 /// ScalarizeVectorOp - Given an operand of single-element vector type
170 /// (e.g. v1f32), convert it into the equivalent operation that returns a
171 /// scalar (e.g. f32) value.
172 SDOperand ScalarizeVectorOp(SDOperand O);
174 /// isShuffleLegal - Return true if a vector shuffle is legal with the
175 /// specified mask and type. Targets can specify exactly which masks they
176 /// support and the code generator is tasked with not creating illegal masks.
178 /// Note that this will also return true for shuffles that are promoted to a
181 /// If this is a legal shuffle, this method returns the (possibly promoted)
182 /// build_vector Mask. If it's not a legal shuffle, it returns null.
183 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
185 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
186 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
188 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
190 SDOperand CreateStackTemporary(MVT::ValueType VT);
192 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
194 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
197 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
198 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
199 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
200 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
202 MVT::ValueType DestVT);
203 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
205 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
208 SDOperand ExpandBSWAP(SDOperand Op);
209 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
210 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
211 SDOperand &Lo, SDOperand &Hi);
212 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
213 SDOperand &Lo, SDOperand &Hi);
215 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
216 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
218 SDOperand getIntPtrConstant(uint64_t Val) {
219 return DAG.getConstant(Val, TLI.getPointerTy());
224 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
225 /// specified mask and type. Targets can specify exactly which masks they
226 /// support and the code generator is tasked with not creating illegal masks.
228 /// Note that this will also return true for shuffles that are promoted to a
230 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
231 SDOperand Mask) const {
232 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
234 case TargetLowering::Legal:
235 case TargetLowering::Custom:
237 case TargetLowering::Promote: {
238 // If this is promoted to a different type, convert the shuffle mask and
239 // ask if it is legal in the promoted type!
240 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
242 // If we changed # elements, change the shuffle mask.
243 unsigned NumEltsGrowth =
244 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
245 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
246 if (NumEltsGrowth > 1) {
247 // Renumber the elements.
248 SmallVector<SDOperand, 8> Ops;
249 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
250 SDOperand InOp = Mask.getOperand(i);
251 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
252 if (InOp.getOpcode() == ISD::UNDEF)
253 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
255 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
256 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
260 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
266 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
269 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
270 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
271 ValueTypeActions(TLI.getValueTypeActions()) {
272 assert(MVT::LAST_VALUETYPE <= 32 &&
273 "Too many value types for ValueTypeActions to hold!");
276 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
277 /// contains all of a nodes operands before it contains the node.
278 static void ComputeTopDownOrdering(SelectionDAG &DAG,
279 SmallVector<SDNode*, 64> &Order) {
281 DenseMap<SDNode*, unsigned> Visited;
282 std::vector<SDNode*> Worklist;
283 Worklist.reserve(128);
285 // Compute ordering from all of the leaves in the graphs, those (like the
286 // entry node) that have no operands.
287 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
288 E = DAG.allnodes_end(); I != E; ++I) {
289 if (I->getNumOperands() == 0) {
291 Worklist.push_back(I);
295 while (!Worklist.empty()) {
296 SDNode *N = Worklist.back();
299 if (++Visited[N] != N->getNumOperands())
300 continue; // Haven't visited all operands yet
304 // Now that we have N in, add anything that uses it if all of their operands
306 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
308 Worklist.push_back(*UI);
311 assert(Order.size() == Visited.size() &&
313 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
314 "Error: DAG is cyclic!");
318 void SelectionDAGLegalize::LegalizeDAG() {
319 LastCALLSEQ_END = DAG.getEntryNode();
320 IsLegalizingCall = false;
322 // The legalize process is inherently a bottom-up recursive process (users
323 // legalize their uses before themselves). Given infinite stack space, we
324 // could just start legalizing on the root and traverse the whole graph. In
325 // practice however, this causes us to run out of stack space on large basic
326 // blocks. To avoid this problem, compute an ordering of the nodes where each
327 // node is only legalized after all of its operands are legalized.
328 SmallVector<SDNode*, 64> Order;
329 ComputeTopDownOrdering(DAG, Order);
331 for (unsigned i = 0, e = Order.size(); i != e; ++i)
332 HandleOp(SDOperand(Order[i], 0));
334 // Finally, it's possible the root changed. Get the new root.
335 SDOperand OldRoot = DAG.getRoot();
336 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
337 DAG.setRoot(LegalizedNodes[OldRoot]);
339 ExpandedNodes.clear();
340 LegalizedNodes.clear();
341 PromotedNodes.clear();
343 ScalarizedNodes.clear();
345 // Remove dead nodes now.
346 DAG.RemoveDeadNodes();
350 /// FindCallEndFromCallStart - Given a chained node that is part of a call
351 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
352 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
353 if (Node->getOpcode() == ISD::CALLSEQ_END)
355 if (Node->use_empty())
356 return 0; // No CallSeqEnd
358 // The chain is usually at the end.
359 SDOperand TheChain(Node, Node->getNumValues()-1);
360 if (TheChain.getValueType() != MVT::Other) {
361 // Sometimes it's at the beginning.
362 TheChain = SDOperand(Node, 0);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Otherwise, hunt for it.
365 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
366 if (Node->getValueType(i) == MVT::Other) {
367 TheChain = SDOperand(Node, i);
371 // Otherwise, we walked into a node without a chain.
372 if (TheChain.getValueType() != MVT::Other)
377 for (SDNode::use_iterator UI = Node->use_begin(),
378 E = Node->use_end(); UI != E; ++UI) {
380 // Make sure to only follow users of our token chain.
382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
383 if (User->getOperand(i) == TheChain)
384 if (SDNode *Result = FindCallEndFromCallStart(User))
390 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
391 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
392 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
393 assert(Node && "Didn't find callseq_start for a call??");
394 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
396 assert(Node->getOperand(0).getValueType() == MVT::Other &&
397 "Node doesn't have a token chain argument!");
398 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
401 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
402 /// see if any uses can reach Dest. If no dest operands can get to dest,
403 /// legalize them, legalize ourself, and return false, otherwise, return true.
405 /// Keep track of the nodes we fine that actually do lead to Dest in
406 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
409 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If we've already processed this node and it does lead to Dest, there is no
413 // need to reprocess it.
414 if (NodesLeadingTo.count(N)) return true;
416 // If the first result of this node has been already legalized, then it cannot
418 switch (getTypeAction(N->getValueType(0))) {
420 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
423 if (PromotedNodes.count(SDOperand(N, 0))) return false;
426 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
430 // Okay, this node has not already been legalized. Check and legalize all
431 // operands. If none lead to Dest, then we can legalize this node.
432 bool OperandsLeadToDest = false;
433 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
434 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
435 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
437 if (OperandsLeadToDest) {
438 NodesLeadingTo.insert(N);
442 // Okay, this node looks safe, legalize it and return false.
443 HandleOp(SDOperand(N, 0));
447 /// HandleOp - Legalize, Promote, or Expand the specified operand as
448 /// appropriate for its type.
449 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
450 MVT::ValueType VT = Op.getValueType();
451 switch (getTypeAction(VT)) {
452 default: assert(0 && "Bad type action!");
453 case Legal: (void)LegalizeOp(Op); break;
454 case Promote: (void)PromoteOp(Op); break;
456 if (!MVT::isVector(VT)) {
457 // If this is an illegal scalar, expand it into its two component
460 if (Op.getOpcode() == ISD::TargetConstant)
461 break; // Allow illegal target nodes.
463 } else if (MVT::getVectorNumElements(VT) == 1) {
464 // If this is an illegal single element vector, convert it to a
466 (void)ScalarizeVectorOp(Op);
468 // Otherwise, this is an illegal multiple element vector.
469 // Split it in half and legalize both parts.
471 SplitVectorOp(Op, X, Y);
477 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
478 /// a load from the constant pool.
479 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
480 SelectionDAG &DAG, TargetLowering &TLI) {
483 // If a FP immediate is precise when represented as a float and if the
484 // target can do an extending load from float to double, we put it into
485 // the constant pool as a float, even if it's is statically typed as a
487 MVT::ValueType VT = CFP->getValueType(0);
488 bool isDouble = VT == MVT::f64;
489 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
490 Type::FloatTy, CFP->getValue());
492 double Val = LLVMC->getValue();
494 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
495 : DAG.getConstant(FloatToBits(Val), MVT::i32);
498 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
499 // Only do this if the target has a native EXTLOAD instruction from f32.
500 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
501 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
506 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
508 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
509 CPIdx, NULL, 0, MVT::f32);
511 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
516 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
519 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
520 SelectionDAG &DAG, TargetLowering &TLI) {
521 MVT::ValueType VT = Node->getValueType(0);
522 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
523 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
524 "fcopysign expansion only supported for f32 and f64");
525 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
527 // First get the sign bit of second operand.
528 SDOperand Mask1 = (SrcVT == MVT::f64)
529 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
530 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
531 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
532 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
533 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
534 // Shift right or sign-extend it if the two operands have different types.
535 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
537 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
538 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
539 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
540 } else if (SizeDiff < 0)
541 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
543 // Clear the sign bit of first operand.
544 SDOperand Mask2 = (VT == MVT::f64)
545 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
546 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
547 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
548 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
549 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
551 // Or the value with the sign bit.
552 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
556 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
558 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
559 TargetLowering &TLI) {
560 assert(MVT::isInteger(ST->getStoredVT()) &&
561 "Non integer unaligned stores not implemented.");
562 int SVOffset = ST->getSrcValueOffset();
563 SDOperand Chain = ST->getChain();
564 SDOperand Ptr = ST->getBasePtr();
565 SDOperand Val = ST->getValue();
566 MVT::ValueType VT = Val.getValueType();
567 // Get the half-size VT
568 MVT::ValueType NewStoredVT = ST->getStoredVT() - 1;
569 int NumBits = MVT::getSizeInBits(NewStoredVT);
570 int Alignment = ST->getAlignment();
571 int IncrementSize = NumBits / 8;
573 // Divide the stored value in two parts.
574 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
576 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
578 // Store the two parts
579 SDOperand Store1, Store2;
580 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
581 ST->getSrcValue(), SVOffset, NewStoredVT,
582 ST->isVolatile(), Alignment);
583 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
584 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
585 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
586 ST->getSrcValue(), SVOffset + IncrementSize,
587 NewStoredVT, ST->isVolatile(), Alignment);
589 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
592 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
594 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
595 TargetLowering &TLI) {
596 assert(MVT::isInteger(LD->getLoadedVT()) &&
597 "Non integer unaligned loads not implemented.");
598 int SVOffset = LD->getSrcValueOffset();
599 SDOperand Chain = LD->getChain();
600 SDOperand Ptr = LD->getBasePtr();
601 MVT::ValueType VT = LD->getValueType(0);
602 MVT::ValueType NewLoadedVT = LD->getLoadedVT() - 1;
603 int NumBits = MVT::getSizeInBits(NewLoadedVT);
604 int Alignment = LD->getAlignment();
605 int IncrementSize = NumBits / 8;
606 ISD::LoadExtType HiExtType = LD->getExtensionType();
608 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
609 if (HiExtType == ISD::NON_EXTLOAD)
610 HiExtType = ISD::ZEXTLOAD;
612 // Load the value in two parts
614 if (TLI.isLittleEndian()) {
615 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
616 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
617 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
618 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
619 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
620 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
623 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
624 NewLoadedVT,LD->isVolatile(), Alignment);
625 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
626 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
627 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
628 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
632 // aggregate the two parts
633 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
634 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
635 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
637 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
640 SDOperand Ops[] = { Result, TF };
641 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
644 /// LegalizeOp - We know that the specified value has a legal type, and
645 /// that its operands are legal. Now ensure that the operation itself
646 /// is legal, recursively ensuring that the operands' operations remain
648 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
649 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
652 assert(isTypeLegal(Op.getValueType()) &&
653 "Caller should expand or promote operands that are not legal!");
654 SDNode *Node = Op.Val;
656 // If this operation defines any values that cannot be represented in a
657 // register on this target, make sure to expand or promote them.
658 if (Node->getNumValues() > 1) {
659 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
660 if (getTypeAction(Node->getValueType(i)) != Legal) {
661 HandleOp(Op.getValue(i));
662 assert(LegalizedNodes.count(Op) &&
663 "Handling didn't add legal operands!");
664 return LegalizedNodes[Op];
668 // Note that LegalizeOp may be reentered even from single-use nodes, which
669 // means that we always must cache transformed nodes.
670 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
671 if (I != LegalizedNodes.end()) return I->second;
673 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
674 SDOperand Result = Op;
675 bool isCustom = false;
677 switch (Node->getOpcode()) {
678 case ISD::FrameIndex:
679 case ISD::EntryToken:
681 case ISD::BasicBlock:
682 case ISD::TargetFrameIndex:
683 case ISD::TargetJumpTable:
684 case ISD::TargetConstant:
685 case ISD::TargetConstantFP:
686 case ISD::TargetConstantPool:
687 case ISD::TargetGlobalAddress:
688 case ISD::TargetGlobalTLSAddress:
689 case ISD::TargetExternalSymbol:
694 // Primitives must all be legal.
695 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
696 "This must be legal!");
699 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
700 // If this is a target node, legalize it by legalizing the operands then
701 // passing it through.
702 SmallVector<SDOperand, 8> Ops;
703 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
704 Ops.push_back(LegalizeOp(Node->getOperand(i)));
706 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
708 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
709 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
710 return Result.getValue(Op.ResNo);
712 // Otherwise this is an unhandled builtin node. splat.
714 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
716 assert(0 && "Do not know how to legalize this operator!");
718 case ISD::GLOBAL_OFFSET_TABLE:
719 case ISD::GlobalAddress:
720 case ISD::GlobalTLSAddress:
721 case ISD::ExternalSymbol:
722 case ISD::ConstantPool:
723 case ISD::JumpTable: // Nothing to do.
724 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
725 default: assert(0 && "This action is not supported yet!");
726 case TargetLowering::Custom:
727 Tmp1 = TLI.LowerOperation(Op, DAG);
728 if (Tmp1.Val) Result = Tmp1;
729 // FALLTHROUGH if the target doesn't want to lower this op after all.
730 case TargetLowering::Legal:
735 case ISD::RETURNADDR:
736 // The only option for these nodes is to custom lower them. If the target
737 // does not custom lower them, then return zero.
738 Tmp1 = TLI.LowerOperation(Op, DAG);
742 Result = DAG.getConstant(0, TLI.getPointerTy());
744 case ISD::FRAME_TO_ARGS_OFFSET: {
745 MVT::ValueType VT = Node->getValueType(0);
746 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
747 default: assert(0 && "This action is not supported yet!");
748 case TargetLowering::Custom:
749 Result = TLI.LowerOperation(Op, DAG);
750 if (Result.Val) break;
752 case TargetLowering::Legal:
753 Result = DAG.getConstant(0, VT);
758 case ISD::EXCEPTIONADDR: {
759 Tmp1 = LegalizeOp(Node->getOperand(0));
760 MVT::ValueType VT = Node->getValueType(0);
761 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
762 default: assert(0 && "This action is not supported yet!");
763 case TargetLowering::Expand: {
764 unsigned Reg = TLI.getExceptionAddressRegister();
765 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
768 case TargetLowering::Custom:
769 Result = TLI.LowerOperation(Op, DAG);
770 if (Result.Val) break;
772 case TargetLowering::Legal: {
773 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
774 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
775 Ops, 2).getValue(Op.ResNo);
781 case ISD::EHSELECTION: {
782 Tmp1 = LegalizeOp(Node->getOperand(0));
783 Tmp2 = LegalizeOp(Node->getOperand(1));
784 MVT::ValueType VT = Node->getValueType(0);
785 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
786 default: assert(0 && "This action is not supported yet!");
787 case TargetLowering::Expand: {
788 unsigned Reg = TLI.getExceptionSelectorRegister();
789 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
792 case TargetLowering::Custom:
793 Result = TLI.LowerOperation(Op, DAG);
794 if (Result.Val) break;
796 case TargetLowering::Legal: {
797 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
798 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
799 Ops, 2).getValue(Op.ResNo);
805 case ISD::EH_RETURN: {
806 MVT::ValueType VT = Node->getValueType(0);
807 // The only "good" option for this node is to custom lower it.
808 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
809 default: assert(0 && "This action is not supported at all!");
810 case TargetLowering::Custom:
811 Result = TLI.LowerOperation(Op, DAG);
812 if (Result.Val) break;
814 case TargetLowering::Legal:
815 // Target does not know, how to lower this, lower to noop
816 Result = LegalizeOp(Node->getOperand(0));
821 case ISD::AssertSext:
822 case ISD::AssertZext:
823 Tmp1 = LegalizeOp(Node->getOperand(0));
824 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
826 case ISD::MERGE_VALUES:
827 // Legalize eliminates MERGE_VALUES nodes.
828 Result = Node->getOperand(Op.ResNo);
830 case ISD::CopyFromReg:
831 Tmp1 = LegalizeOp(Node->getOperand(0));
832 Result = Op.getValue(0);
833 if (Node->getNumValues() == 2) {
834 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
836 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
837 if (Node->getNumOperands() == 3) {
838 Tmp2 = LegalizeOp(Node->getOperand(2));
839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
843 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
845 // Since CopyFromReg produces two values, make sure to remember that we
846 // legalized both of them.
847 AddLegalizedOperand(Op.getValue(0), Result);
848 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
849 return Result.getValue(Op.ResNo);
851 MVT::ValueType VT = Op.getValueType();
852 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
853 default: assert(0 && "This action is not supported yet!");
854 case TargetLowering::Expand:
855 if (MVT::isInteger(VT))
856 Result = DAG.getConstant(0, VT);
857 else if (MVT::isFloatingPoint(VT))
858 Result = DAG.getConstantFP(0, VT);
860 assert(0 && "Unknown value type!");
862 case TargetLowering::Legal:
868 case ISD::INTRINSIC_W_CHAIN:
869 case ISD::INTRINSIC_WO_CHAIN:
870 case ISD::INTRINSIC_VOID: {
871 SmallVector<SDOperand, 8> Ops;
872 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
873 Ops.push_back(LegalizeOp(Node->getOperand(i)));
874 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
876 // Allow the target to custom lower its intrinsics if it wants to.
877 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
878 TargetLowering::Custom) {
879 Tmp3 = TLI.LowerOperation(Result, DAG);
880 if (Tmp3.Val) Result = Tmp3;
883 if (Result.Val->getNumValues() == 1) break;
885 // Must have return value and chain result.
886 assert(Result.Val->getNumValues() == 2 &&
887 "Cannot return more than two values!");
889 // Since loads produce two values, make sure to remember that we
890 // legalized both of them.
891 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
892 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
893 return Result.getValue(Op.ResNo);
897 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
898 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
900 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
901 case TargetLowering::Promote:
902 default: assert(0 && "This action is not supported yet!");
903 case TargetLowering::Expand: {
904 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
905 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
906 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
908 if (MMI && (useDEBUG_LOC || useLABEL)) {
909 const std::string &FName =
910 cast<StringSDNode>(Node->getOperand(3))->getValue();
911 const std::string &DirName =
912 cast<StringSDNode>(Node->getOperand(4))->getValue();
913 unsigned SrcFile = MMI->RecordSource(DirName, FName);
915 SmallVector<SDOperand, 8> Ops;
916 Ops.push_back(Tmp1); // chain
917 SDOperand LineOp = Node->getOperand(1);
918 SDOperand ColOp = Node->getOperand(2);
921 Ops.push_back(LineOp); // line #
922 Ops.push_back(ColOp); // col #
923 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
924 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
926 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
927 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
928 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
929 Ops.push_back(DAG.getConstant(ID, MVT::i32));
930 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
933 Result = Tmp1; // chain
937 case TargetLowering::Legal:
938 if (Tmp1 != Node->getOperand(0) ||
939 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
940 SmallVector<SDOperand, 8> Ops;
942 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
943 Ops.push_back(Node->getOperand(1)); // line # must be legal.
944 Ops.push_back(Node->getOperand(2)); // col # must be legal.
946 // Otherwise promote them.
947 Ops.push_back(PromoteOp(Node->getOperand(1)));
948 Ops.push_back(PromoteOp(Node->getOperand(2)));
950 Ops.push_back(Node->getOperand(3)); // filename must be legal.
951 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
952 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
959 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
960 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
961 default: assert(0 && "This action is not supported yet!");
962 case TargetLowering::Legal:
963 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
964 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
965 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
966 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
967 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
973 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
974 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
975 default: assert(0 && "This action is not supported yet!");
976 case TargetLowering::Legal:
977 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
978 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
979 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
981 case TargetLowering::Expand:
982 Result = LegalizeOp(Node->getOperand(0));
987 case ISD::Constant: {
988 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
990 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
992 // We know we don't need to expand constants here, constants only have one
993 // value and we check that it is fine above.
995 if (opAction == TargetLowering::Custom) {
996 Tmp1 = TLI.LowerOperation(Result, DAG);
1002 case ISD::ConstantFP: {
1003 // Spill FP immediates to the constant pool if the target cannot directly
1004 // codegen them. Targets often have some immediate values that can be
1005 // efficiently generated into an FP register without a load. We explicitly
1006 // leave these constants as ConstantFP nodes for the target to deal with.
1007 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1009 // Check to see if this FP immediate is already legal.
1010 bool isLegal = false;
1011 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1012 E = TLI.legal_fpimm_end(); I != E; ++I)
1013 if (CFP->isExactlyValue(*I)) {
1018 // If this is a legal constant, turn it into a TargetConstantFP node.
1020 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
1024 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1025 default: assert(0 && "This action is not supported yet!");
1026 case TargetLowering::Custom:
1027 Tmp3 = TLI.LowerOperation(Result, DAG);
1033 case TargetLowering::Expand:
1034 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1038 case ISD::TokenFactor:
1039 if (Node->getNumOperands() == 2) {
1040 Tmp1 = LegalizeOp(Node->getOperand(0));
1041 Tmp2 = LegalizeOp(Node->getOperand(1));
1042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1043 } else if (Node->getNumOperands() == 3) {
1044 Tmp1 = LegalizeOp(Node->getOperand(0));
1045 Tmp2 = LegalizeOp(Node->getOperand(1));
1046 Tmp3 = LegalizeOp(Node->getOperand(2));
1047 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1049 SmallVector<SDOperand, 8> Ops;
1050 // Legalize the operands.
1051 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1052 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1053 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1057 case ISD::FORMAL_ARGUMENTS:
1059 // The only option for this is to custom lower it.
1060 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1061 assert(Tmp3.Val && "Target didn't custom lower this node!");
1062 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
1063 "Lowering call/formal_arguments produced unexpected # results!");
1065 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1066 // remember that we legalized all of them, so it doesn't get relegalized.
1067 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1068 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1071 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1074 case ISD::EXTRACT_SUBREG: {
1075 Tmp1 = LegalizeOp(Node->getOperand(0));
1076 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1077 assert(idx && "Operand must be a constant");
1078 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1079 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1082 case ISD::INSERT_SUBREG: {
1083 Tmp1 = LegalizeOp(Node->getOperand(0));
1084 Tmp2 = LegalizeOp(Node->getOperand(1));
1085 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1086 assert(idx && "Operand must be a constant");
1087 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1088 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1091 case ISD::BUILD_VECTOR:
1092 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1093 default: assert(0 && "This action is not supported yet!");
1094 case TargetLowering::Custom:
1095 Tmp3 = TLI.LowerOperation(Result, DAG);
1101 case TargetLowering::Expand:
1102 Result = ExpandBUILD_VECTOR(Result.Val);
1106 case ISD::INSERT_VECTOR_ELT:
1107 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1108 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
1109 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1110 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1112 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1113 Node->getValueType(0))) {
1114 default: assert(0 && "This action is not supported yet!");
1115 case TargetLowering::Legal:
1117 case TargetLowering::Custom:
1118 Tmp3 = TLI.LowerOperation(Result, DAG);
1124 case TargetLowering::Expand: {
1125 // If the insert index is a constant, codegen this as a scalar_to_vector,
1126 // then a shuffle that inserts it into the right position in the vector.
1127 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1128 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1129 Tmp1.getValueType(), Tmp2);
1131 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1132 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1133 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1135 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1136 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1138 SmallVector<SDOperand, 8> ShufOps;
1139 for (unsigned i = 0; i != NumElts; ++i) {
1140 if (i != InsertPos->getValue())
1141 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1143 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1145 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1146 &ShufOps[0], ShufOps.size());
1148 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1149 Tmp1, ScVec, ShufMask);
1150 Result = LegalizeOp(Result);
1154 // If the target doesn't support this, we have to spill the input vector
1155 // to a temporary stack slot, update the element, then reload it. This is
1156 // badness. We could also load the value into a vector register (either
1157 // with a "move to register" or "extload into register" instruction, then
1158 // permute it into place, if the idx is a constant and if the idx is
1159 // supported by the target.
1160 MVT::ValueType VT = Tmp1.getValueType();
1161 MVT::ValueType EltVT = Tmp2.getValueType();
1162 MVT::ValueType IdxVT = Tmp3.getValueType();
1163 MVT::ValueType PtrVT = TLI.getPointerTy();
1164 SDOperand StackPtr = CreateStackTemporary(VT);
1165 // Store the vector.
1166 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1168 // Truncate or zero extend offset to target pointer type.
1169 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1170 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1171 // Add the offset to the index.
1172 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1173 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1174 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1175 // Store the scalar value.
1176 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1177 // Load the updated vector.
1178 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1183 case ISD::SCALAR_TO_VECTOR:
1184 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1185 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1189 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1191 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1192 Node->getValueType(0))) {
1193 default: assert(0 && "This action is not supported yet!");
1194 case TargetLowering::Legal:
1196 case TargetLowering::Custom:
1197 Tmp3 = TLI.LowerOperation(Result, DAG);
1203 case TargetLowering::Expand:
1204 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1208 case ISD::VECTOR_SHUFFLE:
1209 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1210 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1213 // Allow targets to custom lower the SHUFFLEs they support.
1214 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1215 default: assert(0 && "Unknown operation action!");
1216 case TargetLowering::Legal:
1217 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1218 "vector shuffle should not be created if not legal!");
1220 case TargetLowering::Custom:
1221 Tmp3 = TLI.LowerOperation(Result, DAG);
1227 case TargetLowering::Expand: {
1228 MVT::ValueType VT = Node->getValueType(0);
1229 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1230 MVT::ValueType PtrVT = TLI.getPointerTy();
1231 SDOperand Mask = Node->getOperand(2);
1232 unsigned NumElems = Mask.getNumOperands();
1233 SmallVector<SDOperand,8> Ops;
1234 for (unsigned i = 0; i != NumElems; ++i) {
1235 SDOperand Arg = Mask.getOperand(i);
1236 if (Arg.getOpcode() == ISD::UNDEF) {
1237 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1239 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1240 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1242 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1243 DAG.getConstant(Idx, PtrVT)));
1245 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1246 DAG.getConstant(Idx - NumElems, PtrVT)));
1249 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1252 case TargetLowering::Promote: {
1253 // Change base type to a different vector type.
1254 MVT::ValueType OVT = Node->getValueType(0);
1255 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1257 // Cast the two input vectors.
1258 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1259 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1261 // Convert the shuffle mask to the right # elements.
1262 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1263 assert(Tmp3.Val && "Shuffle not legal?");
1264 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1265 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1271 case ISD::EXTRACT_VECTOR_ELT:
1272 Tmp1 = Node->getOperand(0);
1273 Tmp2 = LegalizeOp(Node->getOperand(1));
1274 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1275 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1278 case ISD::EXTRACT_SUBVECTOR:
1279 Tmp1 = Node->getOperand(0);
1280 Tmp2 = LegalizeOp(Node->getOperand(1));
1281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1282 Result = ExpandEXTRACT_SUBVECTOR(Result);
1285 case ISD::CALLSEQ_START: {
1286 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1288 // Recursively Legalize all of the inputs of the call end that do not lead
1289 // to this call start. This ensures that any libcalls that need be inserted
1290 // are inserted *before* the CALLSEQ_START.
1291 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1292 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1293 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1297 // Now that we legalized all of the inputs (which may have inserted
1298 // libcalls) create the new CALLSEQ_START node.
1299 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1301 // Merge in the last call, to ensure that this call start after the last
1303 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1304 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1305 Tmp1 = LegalizeOp(Tmp1);
1308 // Do not try to legalize the target-specific arguments (#1+).
1309 if (Tmp1 != Node->getOperand(0)) {
1310 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1312 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1315 // Remember that the CALLSEQ_START is legalized.
1316 AddLegalizedOperand(Op.getValue(0), Result);
1317 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1318 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1320 // Now that the callseq_start and all of the non-call nodes above this call
1321 // sequence have been legalized, legalize the call itself. During this
1322 // process, no libcalls can/will be inserted, guaranteeing that no calls
1324 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1325 SDOperand InCallSEQ = LastCALLSEQ_END;
1326 // Note that we are selecting this call!
1327 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1328 IsLegalizingCall = true;
1330 // Legalize the call, starting from the CALLSEQ_END.
1331 LegalizeOp(LastCALLSEQ_END);
1332 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1335 case ISD::CALLSEQ_END:
1336 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1337 // will cause this node to be legalized as well as handling libcalls right.
1338 if (LastCALLSEQ_END.Val != Node) {
1339 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1340 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1341 assert(I != LegalizedNodes.end() &&
1342 "Legalizing the call start should have legalized this node!");
1346 // Otherwise, the call start has been legalized and everything is going
1347 // according to plan. Just legalize ourselves normally here.
1348 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1349 // Do not try to legalize the target-specific arguments (#1+), except for
1350 // an optional flag input.
1351 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1352 if (Tmp1 != Node->getOperand(0)) {
1353 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1355 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1358 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1359 if (Tmp1 != Node->getOperand(0) ||
1360 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1361 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1364 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1367 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1368 // This finishes up call legalization.
1369 IsLegalizingCall = false;
1371 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1372 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1373 if (Node->getNumValues() == 2)
1374 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1375 return Result.getValue(Op.ResNo);
1376 case ISD::DYNAMIC_STACKALLOC: {
1377 MVT::ValueType VT = Node->getValueType(0);
1378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1379 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1380 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1381 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1383 Tmp1 = Result.getValue(0);
1384 Tmp2 = Result.getValue(1);
1385 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1386 default: assert(0 && "This action is not supported yet!");
1387 case TargetLowering::Expand: {
1388 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1389 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1390 " not tell us which reg is the stack pointer!");
1391 SDOperand Chain = Tmp1.getOperand(0);
1392 SDOperand Size = Tmp2.getOperand(1);
1393 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1394 Chain = SP.getValue(1);
1395 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1396 unsigned StackAlign =
1397 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1398 if (Align > StackAlign)
1399 SP = DAG.getNode(ISD::AND, VT, SP,
1400 DAG.getConstant(-(uint64_t)Align, VT));
1401 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1402 Tmp2 = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1403 Tmp1 = LegalizeOp(Tmp1);
1404 Tmp2 = LegalizeOp(Tmp2);
1407 case TargetLowering::Custom:
1408 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1410 Tmp1 = LegalizeOp(Tmp3);
1411 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1414 case TargetLowering::Legal:
1417 // Since this op produce two values, make sure to remember that we
1418 // legalized both of them.
1419 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1420 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1421 return Op.ResNo ? Tmp2 : Tmp1;
1423 case ISD::INLINEASM: {
1424 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1425 bool Changed = false;
1426 // Legalize all of the operands of the inline asm, in case they are nodes
1427 // that need to be expanded or something. Note we skip the asm string and
1428 // all of the TargetConstant flags.
1429 SDOperand Op = LegalizeOp(Ops[0]);
1430 Changed = Op != Ops[0];
1433 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1434 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1435 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1436 for (++i; NumVals; ++i, --NumVals) {
1437 SDOperand Op = LegalizeOp(Ops[i]);
1446 Op = LegalizeOp(Ops.back());
1447 Changed |= Op != Ops.back();
1452 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1454 // INLINE asm returns a chain and flag, make sure to add both to the map.
1455 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1456 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1457 return Result.getValue(Op.ResNo);
1460 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1461 // Ensure that libcalls are emitted before a branch.
1462 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1463 Tmp1 = LegalizeOp(Tmp1);
1464 LastCALLSEQ_END = DAG.getEntryNode();
1466 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1469 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1470 // Ensure that libcalls are emitted before a branch.
1471 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1472 Tmp1 = LegalizeOp(Tmp1);
1473 LastCALLSEQ_END = DAG.getEntryNode();
1475 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1476 default: assert(0 && "Indirect target must be legal type (pointer)!");
1478 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1481 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1484 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1485 // Ensure that libcalls are emitted before a branch.
1486 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1487 Tmp1 = LegalizeOp(Tmp1);
1488 LastCALLSEQ_END = DAG.getEntryNode();
1490 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1491 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1493 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1494 default: assert(0 && "This action is not supported yet!");
1495 case TargetLowering::Legal: break;
1496 case TargetLowering::Custom:
1497 Tmp1 = TLI.LowerOperation(Result, DAG);
1498 if (Tmp1.Val) Result = Tmp1;
1500 case TargetLowering::Expand: {
1501 SDOperand Chain = Result.getOperand(0);
1502 SDOperand Table = Result.getOperand(1);
1503 SDOperand Index = Result.getOperand(2);
1505 MVT::ValueType PTy = TLI.getPointerTy();
1506 MachineFunction &MF = DAG.getMachineFunction();
1507 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1508 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1509 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1512 switch (EntrySize) {
1513 default: assert(0 && "Size of jump table not supported yet."); break;
1514 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1515 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1518 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1519 // For PIC, the sequence is:
1520 // BRIND(load(Jumptable + index) + RelocBase)
1521 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1523 if (TLI.usesGlobalOffsetTable())
1524 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1527 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1528 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1529 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1531 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1537 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1538 // Ensure that libcalls are emitted before a return.
1539 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1540 Tmp1 = LegalizeOp(Tmp1);
1541 LastCALLSEQ_END = DAG.getEntryNode();
1543 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1544 case Expand: assert(0 && "It's impossible to expand bools");
1546 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1549 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1551 // The top bits of the promoted condition are not necessarily zero, ensure
1552 // that the value is properly zero extended.
1553 if (!DAG.MaskedValueIsZero(Tmp2,
1554 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1555 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1559 // Basic block destination (Op#2) is always legal.
1560 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1562 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1563 default: assert(0 && "This action is not supported yet!");
1564 case TargetLowering::Legal: break;
1565 case TargetLowering::Custom:
1566 Tmp1 = TLI.LowerOperation(Result, DAG);
1567 if (Tmp1.Val) Result = Tmp1;
1569 case TargetLowering::Expand:
1570 // Expand brcond's setcc into its constituent parts and create a BR_CC
1572 if (Tmp2.getOpcode() == ISD::SETCC) {
1573 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1574 Tmp2.getOperand(0), Tmp2.getOperand(1),
1575 Node->getOperand(2));
1577 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1578 DAG.getCondCode(ISD::SETNE), Tmp2,
1579 DAG.getConstant(0, Tmp2.getValueType()),
1580 Node->getOperand(2));
1586 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1587 // Ensure that libcalls are emitted before a branch.
1588 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1589 Tmp1 = LegalizeOp(Tmp1);
1590 Tmp2 = Node->getOperand(2); // LHS
1591 Tmp3 = Node->getOperand(3); // RHS
1592 Tmp4 = Node->getOperand(1); // CC
1594 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1595 LastCALLSEQ_END = DAG.getEntryNode();
1597 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1598 // the LHS is a legal SETCC itself. In this case, we need to compare
1599 // the result against zero to select between true and false values.
1600 if (Tmp3.Val == 0) {
1601 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1602 Tmp4 = DAG.getCondCode(ISD::SETNE);
1605 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1606 Node->getOperand(4));
1608 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1609 default: assert(0 && "Unexpected action for BR_CC!");
1610 case TargetLowering::Legal: break;
1611 case TargetLowering::Custom:
1612 Tmp4 = TLI.LowerOperation(Result, DAG);
1613 if (Tmp4.Val) Result = Tmp4;
1618 LoadSDNode *LD = cast<LoadSDNode>(Node);
1619 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1620 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1622 ISD::LoadExtType ExtType = LD->getExtensionType();
1623 if (ExtType == ISD::NON_EXTLOAD) {
1624 MVT::ValueType VT = Node->getValueType(0);
1625 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1626 Tmp3 = Result.getValue(0);
1627 Tmp4 = Result.getValue(1);
1629 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1630 default: assert(0 && "This action is not supported yet!");
1631 case TargetLowering::Legal:
1632 // If this is an unaligned load and the target doesn't support it,
1634 if (!TLI.allowsUnalignedMemoryAccesses()) {
1635 unsigned ABIAlignment = TLI.getTargetData()->
1636 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1637 if (LD->getAlignment() < ABIAlignment){
1638 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1640 Tmp3 = Result.getOperand(0);
1641 Tmp4 = Result.getOperand(1);
1647 case TargetLowering::Custom:
1648 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1650 Tmp3 = LegalizeOp(Tmp1);
1651 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1654 case TargetLowering::Promote: {
1655 // Only promote a load of vector type to another.
1656 assert(MVT::isVector(VT) && "Cannot promote this load!");
1657 // Change base type to a different vector type.
1658 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1660 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1661 LD->getSrcValueOffset(),
1662 LD->isVolatile(), LD->getAlignment());
1663 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1664 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1668 // Since loads produce two values, make sure to remember that we
1669 // legalized both of them.
1670 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1671 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1672 return Op.ResNo ? Tmp4 : Tmp3;
1674 MVT::ValueType SrcVT = LD->getLoadedVT();
1675 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1676 default: assert(0 && "This action is not supported yet!");
1677 case TargetLowering::Promote:
1678 assert(SrcVT == MVT::i1 &&
1679 "Can only promote extending LOAD from i1 -> i8!");
1680 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1681 LD->getSrcValue(), LD->getSrcValueOffset(),
1682 MVT::i8, LD->isVolatile(), LD->getAlignment());
1683 Tmp1 = Result.getValue(0);
1684 Tmp2 = Result.getValue(1);
1686 case TargetLowering::Custom:
1689 case TargetLowering::Legal:
1690 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1691 Tmp1 = Result.getValue(0);
1692 Tmp2 = Result.getValue(1);
1695 Tmp3 = TLI.LowerOperation(Result, DAG);
1697 Tmp1 = LegalizeOp(Tmp3);
1698 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1701 // If this is an unaligned load and the target doesn't support it,
1703 if (!TLI.allowsUnalignedMemoryAccesses()) {
1704 unsigned ABIAlignment = TLI.getTargetData()->
1705 getABITypeAlignment(MVT::getTypeForValueType(LD->getLoadedVT()));
1706 if (LD->getAlignment() < ABIAlignment){
1707 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1709 Tmp1 = Result.getOperand(0);
1710 Tmp2 = Result.getOperand(1);
1717 case TargetLowering::Expand:
1718 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1719 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1720 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1721 LD->getSrcValueOffset(),
1722 LD->isVolatile(), LD->getAlignment());
1723 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1724 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1725 Tmp2 = LegalizeOp(Load.getValue(1));
1728 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1729 // Turn the unsupported load into an EXTLOAD followed by an explicit
1730 // zero/sign extend inreg.
1731 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1732 Tmp1, Tmp2, LD->getSrcValue(),
1733 LD->getSrcValueOffset(), SrcVT,
1734 LD->isVolatile(), LD->getAlignment());
1736 if (ExtType == ISD::SEXTLOAD)
1737 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1738 Result, DAG.getValueType(SrcVT));
1740 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1741 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1742 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1745 // Since loads produce two values, make sure to remember that we legalized
1747 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1748 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1749 return Op.ResNo ? Tmp2 : Tmp1;
1752 case ISD::EXTRACT_ELEMENT: {
1753 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1754 switch (getTypeAction(OpTy)) {
1755 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1757 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1759 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1760 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1761 TLI.getShiftAmountTy()));
1762 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1765 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1766 Node->getOperand(0));
1770 // Get both the low and high parts.
1771 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1772 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1773 Result = Tmp2; // 1 -> Hi
1775 Result = Tmp1; // 0 -> Lo
1781 case ISD::CopyToReg:
1782 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1784 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1785 "Register type must be legal!");
1786 // Legalize the incoming value (must be a legal type).
1787 Tmp2 = LegalizeOp(Node->getOperand(2));
1788 if (Node->getNumValues() == 1) {
1789 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1791 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1792 if (Node->getNumOperands() == 4) {
1793 Tmp3 = LegalizeOp(Node->getOperand(3));
1794 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1797 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1800 // Since this produces two values, make sure to remember that we legalized
1802 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1803 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1809 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1811 // Ensure that libcalls are emitted before a return.
1812 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1813 Tmp1 = LegalizeOp(Tmp1);
1814 LastCALLSEQ_END = DAG.getEntryNode();
1816 switch (Node->getNumOperands()) {
1818 Tmp2 = Node->getOperand(1);
1819 Tmp3 = Node->getOperand(2); // Signness
1820 switch (getTypeAction(Tmp2.getValueType())) {
1822 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1825 if (!MVT::isVector(Tmp2.getValueType())) {
1827 ExpandOp(Tmp2, Lo, Hi);
1829 // Big endian systems want the hi reg first.
1830 if (!TLI.isLittleEndian())
1834 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1836 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1837 Result = LegalizeOp(Result);
1839 SDNode *InVal = Tmp2.Val;
1840 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1841 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1843 // Figure out if there is a simple type corresponding to this Vector
1844 // type. If so, convert to the vector type.
1845 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1846 if (TLI.isTypeLegal(TVT)) {
1847 // Turn this into a return of the vector type.
1848 Tmp2 = LegalizeOp(Tmp2);
1849 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1850 } else if (NumElems == 1) {
1851 // Turn this into a return of the scalar type.
1852 Tmp2 = ScalarizeVectorOp(Tmp2);
1853 Tmp2 = LegalizeOp(Tmp2);
1854 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1856 // FIXME: Returns of gcc generic vectors smaller than a legal type
1857 // should be returned in integer registers!
1859 // The scalarized value type may not be legal, e.g. it might require
1860 // promotion or expansion. Relegalize the return.
1861 Result = LegalizeOp(Result);
1863 // FIXME: Returns of gcc generic vectors larger than a legal vector
1864 // type should be returned by reference!
1866 SplitVectorOp(Tmp2, Lo, Hi);
1867 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1868 Result = LegalizeOp(Result);
1873 Tmp2 = PromoteOp(Node->getOperand(1));
1874 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1875 Result = LegalizeOp(Result);
1880 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1882 default: { // ret <values>
1883 SmallVector<SDOperand, 8> NewValues;
1884 NewValues.push_back(Tmp1);
1885 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1886 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1888 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1889 NewValues.push_back(Node->getOperand(i+1));
1893 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1894 "FIXME: TODO: implement returning non-legal vector types!");
1895 ExpandOp(Node->getOperand(i), Lo, Hi);
1896 NewValues.push_back(Lo);
1897 NewValues.push_back(Node->getOperand(i+1));
1899 NewValues.push_back(Hi);
1900 NewValues.push_back(Node->getOperand(i+1));
1905 assert(0 && "Can't promote multiple return value yet!");
1908 if (NewValues.size() == Node->getNumOperands())
1909 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1911 Result = DAG.getNode(ISD::RET, MVT::Other,
1912 &NewValues[0], NewValues.size());
1917 if (Result.getOpcode() == ISD::RET) {
1918 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1919 default: assert(0 && "This action is not supported yet!");
1920 case TargetLowering::Legal: break;
1921 case TargetLowering::Custom:
1922 Tmp1 = TLI.LowerOperation(Result, DAG);
1923 if (Tmp1.Val) Result = Tmp1;
1929 StoreSDNode *ST = cast<StoreSDNode>(Node);
1930 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1931 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1932 int SVOffset = ST->getSrcValueOffset();
1933 unsigned Alignment = ST->getAlignment();
1934 bool isVolatile = ST->isVolatile();
1936 if (!ST->isTruncatingStore()) {
1937 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1938 // FIXME: We shouldn't do this for TargetConstantFP's.
1939 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1940 // to phase ordering between legalized code and the dag combiner. This
1941 // probably means that we need to integrate dag combiner and legalizer
1943 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1944 if (CFP->getValueType(0) == MVT::f32) {
1945 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1947 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1948 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1950 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1951 SVOffset, isVolatile, Alignment);
1955 switch (getTypeAction(ST->getStoredVT())) {
1957 Tmp3 = LegalizeOp(ST->getValue());
1958 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1961 MVT::ValueType VT = Tmp3.getValueType();
1962 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1963 default: assert(0 && "This action is not supported yet!");
1964 case TargetLowering::Legal:
1965 // If this is an unaligned store and the target doesn't support it,
1967 if (!TLI.allowsUnalignedMemoryAccesses()) {
1968 unsigned ABIAlignment = TLI.getTargetData()->
1969 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
1970 if (ST->getAlignment() < ABIAlignment)
1971 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
1975 case TargetLowering::Custom:
1976 Tmp1 = TLI.LowerOperation(Result, DAG);
1977 if (Tmp1.Val) Result = Tmp1;
1979 case TargetLowering::Promote:
1980 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1981 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1982 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1983 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1984 ST->getSrcValue(), SVOffset, isVolatile,
1991 // Truncate the value and store the result.
1992 Tmp3 = PromoteOp(ST->getValue());
1993 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1994 SVOffset, ST->getStoredVT(),
1995 isVolatile, Alignment);
1999 unsigned IncrementSize = 0;
2002 // If this is a vector type, then we have to calculate the increment as
2003 // the product of the element size in bytes, and the number of elements
2004 // in the high half of the vector.
2005 if (MVT::isVector(ST->getValue().getValueType())) {
2006 SDNode *InVal = ST->getValue().Val;
2007 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2008 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2010 // Figure out if there is a simple type corresponding to this Vector
2011 // type. If so, convert to the vector type.
2012 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2013 if (TLI.isTypeLegal(TVT)) {
2014 // Turn this into a normal store of the vector type.
2015 Tmp3 = LegalizeOp(Node->getOperand(1));
2016 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2017 SVOffset, isVolatile, Alignment);
2018 Result = LegalizeOp(Result);
2020 } else if (NumElems == 1) {
2021 // Turn this into a normal store of the scalar type.
2022 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
2023 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2024 SVOffset, isVolatile, Alignment);
2025 // The scalarized value type may not be legal, e.g. it might require
2026 // promotion or expansion. Relegalize the scalar store.
2027 Result = LegalizeOp(Result);
2030 SplitVectorOp(Node->getOperand(1), Lo, Hi);
2031 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
2034 ExpandOp(Node->getOperand(1), Lo, Hi);
2035 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2037 if (!TLI.isLittleEndian())
2041 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2042 SVOffset, isVolatile, Alignment);
2044 if (Hi.Val == NULL) {
2045 // Must be int <-> float one-to-one expansion.
2050 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2051 getIntPtrConstant(IncrementSize));
2052 assert(isTypeLegal(Tmp2.getValueType()) &&
2053 "Pointers must be legal!");
2054 SVOffset += IncrementSize;
2055 if (Alignment > IncrementSize)
2056 Alignment = IncrementSize;
2057 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2058 SVOffset, isVolatile, Alignment);
2059 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2064 assert(isTypeLegal(ST->getValue().getValueType()) &&
2065 "Cannot handle illegal TRUNCSTORE yet!");
2066 Tmp3 = LegalizeOp(ST->getValue());
2068 // The only promote case we handle is TRUNCSTORE:i1 X into
2069 // -> TRUNCSTORE:i8 (and X, 1)
2070 if (ST->getStoredVT() == MVT::i1 &&
2071 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
2072 // Promote the bool to a mask then store.
2073 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
2074 DAG.getConstant(1, Tmp3.getValueType()));
2075 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2077 isVolatile, Alignment);
2078 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2079 Tmp2 != ST->getBasePtr()) {
2080 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2084 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
2085 switch (TLI.getStoreXAction(StVT)) {
2086 default: assert(0 && "This action is not supported yet!");
2087 case TargetLowering::Legal:
2088 // If this is an unaligned store and the target doesn't support it,
2090 if (!TLI.allowsUnalignedMemoryAccesses()) {
2091 unsigned ABIAlignment = TLI.getTargetData()->
2092 getABITypeAlignment(MVT::getTypeForValueType(ST->getStoredVT()));
2093 if (ST->getAlignment() < ABIAlignment)
2094 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2098 case TargetLowering::Custom:
2099 Tmp1 = TLI.LowerOperation(Result, DAG);
2100 if (Tmp1.Val) Result = Tmp1;
2107 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2108 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2110 case ISD::STACKSAVE:
2111 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2112 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2113 Tmp1 = Result.getValue(0);
2114 Tmp2 = Result.getValue(1);
2116 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2117 default: assert(0 && "This action is not supported yet!");
2118 case TargetLowering::Legal: break;
2119 case TargetLowering::Custom:
2120 Tmp3 = TLI.LowerOperation(Result, DAG);
2122 Tmp1 = LegalizeOp(Tmp3);
2123 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2126 case TargetLowering::Expand:
2127 // Expand to CopyFromReg if the target set
2128 // StackPointerRegisterToSaveRestore.
2129 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2130 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2131 Node->getValueType(0));
2132 Tmp2 = Tmp1.getValue(1);
2134 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2135 Tmp2 = Node->getOperand(0);
2140 // Since stacksave produce two values, make sure to remember that we
2141 // legalized both of them.
2142 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2143 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2144 return Op.ResNo ? Tmp2 : Tmp1;
2146 case ISD::STACKRESTORE:
2147 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2148 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2149 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2151 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2152 default: assert(0 && "This action is not supported yet!");
2153 case TargetLowering::Legal: break;
2154 case TargetLowering::Custom:
2155 Tmp1 = TLI.LowerOperation(Result, DAG);
2156 if (Tmp1.Val) Result = Tmp1;
2158 case TargetLowering::Expand:
2159 // Expand to CopyToReg if the target set
2160 // StackPointerRegisterToSaveRestore.
2161 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2162 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2170 case ISD::READCYCLECOUNTER:
2171 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2172 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2173 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2174 Node->getValueType(0))) {
2175 default: assert(0 && "This action is not supported yet!");
2176 case TargetLowering::Legal:
2177 Tmp1 = Result.getValue(0);
2178 Tmp2 = Result.getValue(1);
2180 case TargetLowering::Custom:
2181 Result = TLI.LowerOperation(Result, DAG);
2182 Tmp1 = LegalizeOp(Result.getValue(0));
2183 Tmp2 = LegalizeOp(Result.getValue(1));
2187 // Since rdcc produce two values, make sure to remember that we legalized
2189 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2190 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2194 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2195 case Expand: assert(0 && "It's impossible to expand bools");
2197 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2200 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2201 // Make sure the condition is either zero or one.
2202 if (!DAG.MaskedValueIsZero(Tmp1,
2203 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2204 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2207 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2208 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2212 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2213 default: assert(0 && "This action is not supported yet!");
2214 case TargetLowering::Legal: break;
2215 case TargetLowering::Custom: {
2216 Tmp1 = TLI.LowerOperation(Result, DAG);
2217 if (Tmp1.Val) Result = Tmp1;
2220 case TargetLowering::Expand:
2221 if (Tmp1.getOpcode() == ISD::SETCC) {
2222 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2224 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2226 Result = DAG.getSelectCC(Tmp1,
2227 DAG.getConstant(0, Tmp1.getValueType()),
2228 Tmp2, Tmp3, ISD::SETNE);
2231 case TargetLowering::Promote: {
2232 MVT::ValueType NVT =
2233 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2234 unsigned ExtOp, TruncOp;
2235 if (MVT::isVector(Tmp2.getValueType())) {
2236 ExtOp = ISD::BIT_CONVERT;
2237 TruncOp = ISD::BIT_CONVERT;
2238 } else if (MVT::isInteger(Tmp2.getValueType())) {
2239 ExtOp = ISD::ANY_EXTEND;
2240 TruncOp = ISD::TRUNCATE;
2242 ExtOp = ISD::FP_EXTEND;
2243 TruncOp = ISD::FP_ROUND;
2245 // Promote each of the values to the new type.
2246 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2247 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2248 // Perform the larger operation, then round down.
2249 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2250 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2255 case ISD::SELECT_CC: {
2256 Tmp1 = Node->getOperand(0); // LHS
2257 Tmp2 = Node->getOperand(1); // RHS
2258 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2259 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2260 SDOperand CC = Node->getOperand(4);
2262 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2264 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2265 // the LHS is a legal SETCC itself. In this case, we need to compare
2266 // the result against zero to select between true and false values.
2267 if (Tmp2.Val == 0) {
2268 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2269 CC = DAG.getCondCode(ISD::SETNE);
2271 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2273 // Everything is legal, see if we should expand this op or something.
2274 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2275 default: assert(0 && "This action is not supported yet!");
2276 case TargetLowering::Legal: break;
2277 case TargetLowering::Custom:
2278 Tmp1 = TLI.LowerOperation(Result, DAG);
2279 if (Tmp1.Val) Result = Tmp1;
2285 Tmp1 = Node->getOperand(0);
2286 Tmp2 = Node->getOperand(1);
2287 Tmp3 = Node->getOperand(2);
2288 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2290 // If we had to Expand the SetCC operands into a SELECT node, then it may
2291 // not always be possible to return a true LHS & RHS. In this case, just
2292 // return the value we legalized, returned in the LHS
2293 if (Tmp2.Val == 0) {
2298 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2299 default: assert(0 && "Cannot handle this action for SETCC yet!");
2300 case TargetLowering::Custom:
2303 case TargetLowering::Legal:
2304 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2306 Tmp4 = TLI.LowerOperation(Result, DAG);
2307 if (Tmp4.Val) Result = Tmp4;
2310 case TargetLowering::Promote: {
2311 // First step, figure out the appropriate operation to use.
2312 // Allow SETCC to not be supported for all legal data types
2313 // Mostly this targets FP
2314 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2315 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2317 // Scan for the appropriate larger type to use.
2319 NewInTy = (MVT::ValueType)(NewInTy+1);
2321 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2322 "Fell off of the edge of the integer world");
2323 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2324 "Fell off of the edge of the floating point world");
2326 // If the target supports SETCC of this type, use it.
2327 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2330 if (MVT::isInteger(NewInTy))
2331 assert(0 && "Cannot promote Legal Integer SETCC yet");
2333 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2334 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2336 Tmp1 = LegalizeOp(Tmp1);
2337 Tmp2 = LegalizeOp(Tmp2);
2338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2339 Result = LegalizeOp(Result);
2342 case TargetLowering::Expand:
2343 // Expand a setcc node into a select_cc of the same condition, lhs, and
2344 // rhs that selects between const 1 (true) and const 0 (false).
2345 MVT::ValueType VT = Node->getValueType(0);
2346 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2347 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2354 case ISD::MEMMOVE: {
2355 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2356 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2358 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2359 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2360 case Expand: assert(0 && "Cannot expand a byte!");
2362 Tmp3 = LegalizeOp(Node->getOperand(2));
2365 Tmp3 = PromoteOp(Node->getOperand(2));
2369 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2373 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2375 // Length is too big, just take the lo-part of the length.
2377 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2381 Tmp4 = LegalizeOp(Node->getOperand(3));
2384 Tmp4 = PromoteOp(Node->getOperand(3));
2389 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2390 case Expand: assert(0 && "Cannot expand this yet!");
2392 Tmp5 = LegalizeOp(Node->getOperand(4));
2395 Tmp5 = PromoteOp(Node->getOperand(4));
2399 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2400 default: assert(0 && "This action not implemented for this operation!");
2401 case TargetLowering::Custom:
2404 case TargetLowering::Legal:
2405 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2407 Tmp1 = TLI.LowerOperation(Result, DAG);
2408 if (Tmp1.Val) Result = Tmp1;
2411 case TargetLowering::Expand: {
2412 // Otherwise, the target does not support this operation. Lower the
2413 // operation to an explicit libcall as appropriate.
2414 MVT::ValueType IntPtr = TLI.getPointerTy();
2415 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2416 TargetLowering::ArgListTy Args;
2417 TargetLowering::ArgListEntry Entry;
2419 const char *FnName = 0;
2420 if (Node->getOpcode() == ISD::MEMSET) {
2421 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2422 Args.push_back(Entry);
2423 // Extend the (previously legalized) ubyte argument to be an int value
2425 if (Tmp3.getValueType() > MVT::i32)
2426 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2428 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2429 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2430 Args.push_back(Entry);
2431 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2432 Args.push_back(Entry);
2435 } else if (Node->getOpcode() == ISD::MEMCPY ||
2436 Node->getOpcode() == ISD::MEMMOVE) {
2437 Entry.Ty = IntPtrTy;
2438 Entry.Node = Tmp2; Args.push_back(Entry);
2439 Entry.Node = Tmp3; Args.push_back(Entry);
2440 Entry.Node = Tmp4; Args.push_back(Entry);
2441 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2443 assert(0 && "Unknown op!");
2446 std::pair<SDOperand,SDOperand> CallResult =
2447 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2448 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2449 Result = CallResult.second;
2456 case ISD::SHL_PARTS:
2457 case ISD::SRA_PARTS:
2458 case ISD::SRL_PARTS: {
2459 SmallVector<SDOperand, 8> Ops;
2460 bool Changed = false;
2461 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2462 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2463 Changed |= Ops.back() != Node->getOperand(i);
2466 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2468 switch (TLI.getOperationAction(Node->getOpcode(),
2469 Node->getValueType(0))) {
2470 default: assert(0 && "This action is not supported yet!");
2471 case TargetLowering::Legal: break;
2472 case TargetLowering::Custom:
2473 Tmp1 = TLI.LowerOperation(Result, DAG);
2475 SDOperand Tmp2, RetVal(0, 0);
2476 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2477 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2478 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2482 assert(RetVal.Val && "Illegal result number");
2488 // Since these produce multiple values, make sure to remember that we
2489 // legalized all of them.
2490 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2491 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2492 return Result.getValue(Op.ResNo);
2513 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2514 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2515 case Expand: assert(0 && "Not possible");
2517 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2520 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2526 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2527 default: assert(0 && "BinOp legalize operation not supported");
2528 case TargetLowering::Legal: break;
2529 case TargetLowering::Custom:
2530 Tmp1 = TLI.LowerOperation(Result, DAG);
2531 if (Tmp1.Val) Result = Tmp1;
2533 case TargetLowering::Expand: {
2534 if (Node->getValueType(0) == MVT::i32) {
2535 switch (Node->getOpcode()) {
2536 default: assert(0 && "Do not know how to expand this integer BinOp!");
2539 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2540 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2542 bool isSigned = Node->getOpcode() == ISD::SDIV;
2543 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2548 assert(MVT::isVector(Node->getValueType(0)) &&
2549 "Cannot expand this binary operator!");
2550 // Expand the operation into a bunch of nasty scalar code.
2551 SmallVector<SDOperand, 8> Ops;
2552 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2553 MVT::ValueType PtrVT = TLI.getPointerTy();
2554 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2556 SDOperand Idx = DAG.getConstant(i, PtrVT);
2557 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2558 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2559 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2561 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2562 &Ops[0], Ops.size());
2565 case TargetLowering::Promote: {
2566 switch (Node->getOpcode()) {
2567 default: assert(0 && "Do not know how to promote this BinOp!");
2571 MVT::ValueType OVT = Node->getValueType(0);
2572 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2573 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2574 // Bit convert each of the values to the new type.
2575 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2576 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2577 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2578 // Bit convert the result back the original type.
2579 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2587 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2588 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2589 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2590 case Expand: assert(0 && "Not possible");
2592 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2595 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2601 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2602 default: assert(0 && "Operation not supported");
2603 case TargetLowering::Custom:
2604 Tmp1 = TLI.LowerOperation(Result, DAG);
2605 if (Tmp1.Val) Result = Tmp1;
2607 case TargetLowering::Legal: break;
2608 case TargetLowering::Expand: {
2609 // If this target supports fabs/fneg natively and select is cheap,
2610 // do this efficiently.
2611 if (!TLI.isSelectExpensive() &&
2612 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2613 TargetLowering::Legal &&
2614 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2615 TargetLowering::Legal) {
2616 // Get the sign bit of the RHS.
2617 MVT::ValueType IVT =
2618 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2619 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2620 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2621 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2622 // Get the absolute value of the result.
2623 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2624 // Select between the nabs and abs value based on the sign bit of
2626 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2627 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2630 Result = LegalizeOp(Result);
2634 // Otherwise, do bitwise ops!
2635 MVT::ValueType NVT =
2636 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2637 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2638 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2639 Result = LegalizeOp(Result);
2647 Tmp1 = LegalizeOp(Node->getOperand(0));
2648 Tmp2 = LegalizeOp(Node->getOperand(1));
2649 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2650 // Since this produces two values, make sure to remember that we legalized
2652 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2653 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2658 Tmp1 = LegalizeOp(Node->getOperand(0));
2659 Tmp2 = LegalizeOp(Node->getOperand(1));
2660 Tmp3 = LegalizeOp(Node->getOperand(2));
2661 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2662 // Since this produces two values, make sure to remember that we legalized
2664 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2665 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2668 case ISD::BUILD_PAIR: {
2669 MVT::ValueType PairTy = Node->getValueType(0);
2670 // TODO: handle the case where the Lo and Hi operands are not of legal type
2671 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2672 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2673 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2674 case TargetLowering::Promote:
2675 case TargetLowering::Custom:
2676 assert(0 && "Cannot promote/custom this yet!");
2677 case TargetLowering::Legal:
2678 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2679 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2681 case TargetLowering::Expand:
2682 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2683 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2684 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2685 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2686 TLI.getShiftAmountTy()));
2687 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2696 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2697 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2699 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2700 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2701 case TargetLowering::Custom:
2704 case TargetLowering::Legal:
2705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2707 Tmp1 = TLI.LowerOperation(Result, DAG);
2708 if (Tmp1.Val) Result = Tmp1;
2711 case TargetLowering::Expand:
2712 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2713 bool isSigned = DivOpc == ISD::SDIV;
2714 if (MVT::isInteger(Node->getValueType(0))) {
2715 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2716 TargetLowering::Legal) {
2718 MVT::ValueType VT = Node->getValueType(0);
2719 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2720 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2721 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2723 assert(Node->getValueType(0) == MVT::i32 &&
2724 "Cannot expand this binary operator!");
2725 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2726 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2728 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2731 // Floating point mod -> fmod libcall.
2732 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2733 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2735 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2736 false/*sign irrelevant*/, Dummy);
2742 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2743 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2745 MVT::ValueType VT = Node->getValueType(0);
2746 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2747 default: assert(0 && "This action is not supported yet!");
2748 case TargetLowering::Custom:
2751 case TargetLowering::Legal:
2752 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2753 Result = Result.getValue(0);
2754 Tmp1 = Result.getValue(1);
2757 Tmp2 = TLI.LowerOperation(Result, DAG);
2759 Result = LegalizeOp(Tmp2);
2760 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2764 case TargetLowering::Expand: {
2765 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2766 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2767 SV->getValue(), SV->getOffset());
2768 // Increment the pointer, VAList, to the next vaarg
2769 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2770 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2771 TLI.getPointerTy()));
2772 // Store the incremented VAList to the legalized pointer
2773 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2775 // Load the actual argument out of the pointer VAList
2776 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2777 Tmp1 = LegalizeOp(Result.getValue(1));
2778 Result = LegalizeOp(Result);
2782 // Since VAARG produces two values, make sure to remember that we
2783 // legalized both of them.
2784 AddLegalizedOperand(SDOperand(Node, 0), Result);
2785 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2786 return Op.ResNo ? Tmp1 : Result;
2790 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2791 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2792 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2794 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2795 default: assert(0 && "This action is not supported yet!");
2796 case TargetLowering::Custom:
2799 case TargetLowering::Legal:
2800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2801 Node->getOperand(3), Node->getOperand(4));
2803 Tmp1 = TLI.LowerOperation(Result, DAG);
2804 if (Tmp1.Val) Result = Tmp1;
2807 case TargetLowering::Expand:
2808 // This defaults to loading a pointer from the input and storing it to the
2809 // output, returning the chain.
2810 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2811 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2812 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2814 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2821 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2822 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2824 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2825 default: assert(0 && "This action is not supported yet!");
2826 case TargetLowering::Custom:
2829 case TargetLowering::Legal:
2830 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2832 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2833 if (Tmp1.Val) Result = Tmp1;
2836 case TargetLowering::Expand:
2837 Result = Tmp1; // Default to a no-op, return the chain
2843 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2844 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2846 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2848 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2849 default: assert(0 && "This action is not supported yet!");
2850 case TargetLowering::Legal: break;
2851 case TargetLowering::Custom:
2852 Tmp1 = TLI.LowerOperation(Result, DAG);
2853 if (Tmp1.Val) Result = Tmp1;
2860 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2861 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2862 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2863 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2865 assert(0 && "ROTL/ROTR legalize operation not supported");
2867 case TargetLowering::Legal:
2869 case TargetLowering::Custom:
2870 Tmp1 = TLI.LowerOperation(Result, DAG);
2871 if (Tmp1.Val) Result = Tmp1;
2873 case TargetLowering::Promote:
2874 assert(0 && "Do not know how to promote ROTL/ROTR");
2876 case TargetLowering::Expand:
2877 assert(0 && "Do not know how to expand ROTL/ROTR");
2883 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2884 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2885 case TargetLowering::Custom:
2886 assert(0 && "Cannot custom legalize this yet!");
2887 case TargetLowering::Legal:
2888 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2890 case TargetLowering::Promote: {
2891 MVT::ValueType OVT = Tmp1.getValueType();
2892 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2893 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2895 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2896 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2897 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2898 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2901 case TargetLowering::Expand:
2902 Result = ExpandBSWAP(Tmp1);
2910 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2911 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2912 case TargetLowering::Custom:
2913 case TargetLowering::Legal:
2914 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2915 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
2916 TargetLowering::Custom) {
2917 Tmp1 = TLI.LowerOperation(Result, DAG);
2923 case TargetLowering::Promote: {
2924 MVT::ValueType OVT = Tmp1.getValueType();
2925 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2927 // Zero extend the argument.
2928 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2929 // Perform the larger operation, then subtract if needed.
2930 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2931 switch (Node->getOpcode()) {
2936 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2937 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2938 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2940 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2941 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2944 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2945 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2946 DAG.getConstant(MVT::getSizeInBits(NVT) -
2947 MVT::getSizeInBits(OVT), NVT));
2952 case TargetLowering::Expand:
2953 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2964 Tmp1 = LegalizeOp(Node->getOperand(0));
2965 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2966 case TargetLowering::Promote:
2967 case TargetLowering::Custom:
2970 case TargetLowering::Legal:
2971 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2973 Tmp1 = TLI.LowerOperation(Result, DAG);
2974 if (Tmp1.Val) Result = Tmp1;
2977 case TargetLowering::Expand:
2978 switch (Node->getOpcode()) {
2979 default: assert(0 && "Unreachable!");
2981 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2982 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2983 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2986 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2987 MVT::ValueType VT = Node->getValueType(0);
2988 Tmp2 = DAG.getConstantFP(0.0, VT);
2989 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2990 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2991 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2997 MVT::ValueType VT = Node->getValueType(0);
2998 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2999 switch(Node->getOpcode()) {
3001 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
3004 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
3007 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
3009 default: assert(0 && "Unreachable!");
3012 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3013 false/*sign irrelevant*/, Dummy);
3021 // We always lower FPOWI into a libcall. No target support it yet.
3022 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
3023 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
3025 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3026 false/*sign irrelevant*/, Dummy);
3029 case ISD::BIT_CONVERT:
3030 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3031 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3032 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3033 // The input has to be a vector type, we have to either scalarize it, pack
3034 // it, or convert it based on whether the input vector type is legal.
3035 SDNode *InVal = Node->getOperand(0).Val;
3036 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
3037 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
3039 // Figure out if there is a simple type corresponding to this Vector
3040 // type. If so, convert to the vector type.
3041 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3042 if (TLI.isTypeLegal(TVT)) {
3043 // Turn this into a bit convert of the vector input.
3044 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3045 LegalizeOp(Node->getOperand(0)));
3047 } else if (NumElems == 1) {
3048 // Turn this into a bit convert of the scalar input.
3049 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3050 ScalarizeVectorOp(Node->getOperand(0)));
3053 // FIXME: UNIMP! Store then reload
3054 assert(0 && "Cast from unsupported vector type not implemented yet!");
3057 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3058 Node->getOperand(0).getValueType())) {
3059 default: assert(0 && "Unknown operation action!");
3060 case TargetLowering::Expand:
3061 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3063 case TargetLowering::Legal:
3064 Tmp1 = LegalizeOp(Node->getOperand(0));
3065 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3071 // Conversion operators. The source and destination have different types.
3072 case ISD::SINT_TO_FP:
3073 case ISD::UINT_TO_FP: {
3074 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3075 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3077 switch (TLI.getOperationAction(Node->getOpcode(),
3078 Node->getOperand(0).getValueType())) {
3079 default: assert(0 && "Unknown operation action!");
3080 case TargetLowering::Custom:
3083 case TargetLowering::Legal:
3084 Tmp1 = LegalizeOp(Node->getOperand(0));
3085 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3087 Tmp1 = TLI.LowerOperation(Result, DAG);
3088 if (Tmp1.Val) Result = Tmp1;
3091 case TargetLowering::Expand:
3092 Result = ExpandLegalINT_TO_FP(isSigned,
3093 LegalizeOp(Node->getOperand(0)),
3094 Node->getValueType(0));
3096 case TargetLowering::Promote:
3097 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3098 Node->getValueType(0),
3104 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3105 Node->getValueType(0), Node->getOperand(0));
3108 Tmp1 = PromoteOp(Node->getOperand(0));
3110 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3111 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3113 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3114 Node->getOperand(0).getValueType());
3116 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3117 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3123 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3125 Tmp1 = LegalizeOp(Node->getOperand(0));
3126 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3129 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3131 // Since the result is legal, we should just be able to truncate the low
3132 // part of the source.
3133 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3136 Result = PromoteOp(Node->getOperand(0));
3137 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3142 case ISD::FP_TO_SINT:
3143 case ISD::FP_TO_UINT:
3144 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3146 Tmp1 = LegalizeOp(Node->getOperand(0));
3148 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3149 default: assert(0 && "Unknown operation action!");
3150 case TargetLowering::Custom:
3153 case TargetLowering::Legal:
3154 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3156 Tmp1 = TLI.LowerOperation(Result, DAG);
3157 if (Tmp1.Val) Result = Tmp1;
3160 case TargetLowering::Promote:
3161 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3162 Node->getOpcode() == ISD::FP_TO_SINT);
3164 case TargetLowering::Expand:
3165 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3166 SDOperand True, False;
3167 MVT::ValueType VT = Node->getOperand(0).getValueType();
3168 MVT::ValueType NVT = Node->getValueType(0);
3169 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
3170 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
3171 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3172 Node->getOperand(0), Tmp2, ISD::SETLT);
3173 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3174 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3175 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3177 False = DAG.getNode(ISD::XOR, NVT, False,
3178 DAG.getConstant(1ULL << ShiftAmt, NVT));
3179 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3182 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3188 // Convert f32 / f64 to i32 / i64.
3189 MVT::ValueType VT = Op.getValueType();
3190 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3191 switch (Node->getOpcode()) {
3192 case ISD::FP_TO_SINT:
3193 if (Node->getOperand(0).getValueType() == MVT::f32)
3194 LC = (VT == MVT::i32)
3195 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3197 LC = (VT == MVT::i32)
3198 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3200 case ISD::FP_TO_UINT:
3201 if (Node->getOperand(0).getValueType() == MVT::f32)
3202 LC = (VT == MVT::i32)
3203 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3205 LC = (VT == MVT::i32)
3206 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3208 default: assert(0 && "Unreachable!");
3211 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3212 false/*sign irrelevant*/, Dummy);
3216 Tmp1 = PromoteOp(Node->getOperand(0));
3217 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3218 Result = LegalizeOp(Result);
3223 case ISD::FP_EXTEND:
3224 case ISD::FP_ROUND: {
3225 MVT::ValueType newVT = Op.getValueType();
3226 MVT::ValueType oldVT = Op.getOperand(0).getValueType();
3227 if (TLI.getConvertAction(oldVT, newVT) == TargetLowering::Expand) {
3228 // The only way we can lower this is to turn it into a STORE,
3229 // LOAD pair, targetting a temporary location (a stack slot).
3231 // NOTE: there is a choice here between constantly creating new stack
3232 // slots and always reusing the same one. We currently always create
3233 // new ones, as reuse may inhibit scheduling.
3234 MVT::ValueType slotVT =
3235 (Node->getOpcode() == ISD::FP_EXTEND) ? oldVT : newVT;
3236 const Type *Ty = MVT::getTypeForValueType(slotVT);
3237 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3238 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3239 MachineFunction &MF = DAG.getMachineFunction();
3241 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3242 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3243 if (Node->getOpcode() == ISD::FP_EXTEND) {
3244 Result = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0),
3245 StackSlot, NULL, 0);
3246 Result = DAG.getExtLoad(ISD::EXTLOAD, newVT,
3247 Result, StackSlot, NULL, 0, oldVT);
3249 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3250 StackSlot, NULL, 0, newVT);
3251 Result = DAG.getLoad(newVT, Result, StackSlot, NULL, 0, newVT);
3257 case ISD::ANY_EXTEND:
3258 case ISD::ZERO_EXTEND:
3259 case ISD::SIGN_EXTEND:
3260 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3261 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3263 Tmp1 = LegalizeOp(Node->getOperand(0));
3264 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3267 switch (Node->getOpcode()) {
3268 case ISD::ANY_EXTEND:
3269 Tmp1 = PromoteOp(Node->getOperand(0));
3270 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3272 case ISD::ZERO_EXTEND:
3273 Result = PromoteOp(Node->getOperand(0));
3274 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3275 Result = DAG.getZeroExtendInReg(Result,
3276 Node->getOperand(0).getValueType());
3278 case ISD::SIGN_EXTEND:
3279 Result = PromoteOp(Node->getOperand(0));
3280 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3281 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3283 DAG.getValueType(Node->getOperand(0).getValueType()));
3285 case ISD::FP_EXTEND:
3286 Result = PromoteOp(Node->getOperand(0));
3287 if (Result.getValueType() != Op.getValueType())
3288 // Dynamically dead while we have only 2 FP types.
3289 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3292 Result = PromoteOp(Node->getOperand(0));
3293 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3298 case ISD::FP_ROUND_INREG:
3299 case ISD::SIGN_EXTEND_INREG: {
3300 Tmp1 = LegalizeOp(Node->getOperand(0));
3301 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3303 // If this operation is not supported, convert it to a shl/shr or load/store
3305 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3306 default: assert(0 && "This action not supported for this op yet!");
3307 case TargetLowering::Legal:
3308 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3310 case TargetLowering::Expand:
3311 // If this is an integer extend and shifts are supported, do that.
3312 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3313 // NOTE: we could fall back on load/store here too for targets without
3314 // SAR. However, it is doubtful that any exist.
3315 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3316 MVT::getSizeInBits(ExtraVT);
3317 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3318 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3319 Node->getOperand(0), ShiftCst);
3320 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3322 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3323 // The only way we can lower this is to turn it into a TRUNCSTORE,
3324 // EXTLOAD pair, targetting a temporary location (a stack slot).
3326 // NOTE: there is a choice here between constantly creating new stack
3327 // slots and always reusing the same one. We currently always create
3328 // new ones, as reuse may inhibit scheduling.
3329 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3330 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3331 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3332 MachineFunction &MF = DAG.getMachineFunction();
3334 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3335 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3336 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3337 StackSlot, NULL, 0, ExtraVT);
3338 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3339 Result, StackSlot, NULL, 0, ExtraVT);
3341 assert(0 && "Unknown op");
3347 case ISD::ADJUST_TRAMP: {
3348 Tmp1 = LegalizeOp(Node->getOperand(0));
3349 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3350 default: assert(0 && "This action is not supported yet!");
3351 case TargetLowering::Custom:
3352 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3353 Result = TLI.LowerOperation(Result, DAG);
3354 if (Result.Val) break;
3356 case TargetLowering::Expand:
3362 case ISD::TRAMPOLINE: {
3364 for (unsigned i = 0; i != 6; ++i)
3365 Ops[i] = LegalizeOp(Node->getOperand(i));
3366 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3367 // The only option for this node is to custom lower it.
3368 Result = TLI.LowerOperation(Result, DAG);
3369 assert(Result.Val && "Should always custom lower!");
3374 assert(Result.getValueType() == Op.getValueType() &&
3375 "Bad legalization!");
3377 // Make sure that the generated code is itself legal.
3379 Result = LegalizeOp(Result);
3381 // Note that LegalizeOp may be reentered even from single-use nodes, which
3382 // means that we always must cache transformed nodes.
3383 AddLegalizedOperand(Op, Result);
3387 /// PromoteOp - Given an operation that produces a value in an invalid type,
3388 /// promote it to compute the value into a larger type. The produced value will
3389 /// have the correct bits for the low portion of the register, but no guarantee
3390 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3391 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3392 MVT::ValueType VT = Op.getValueType();
3393 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3394 assert(getTypeAction(VT) == Promote &&
3395 "Caller should expand or legalize operands that are not promotable!");
3396 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3397 "Cannot promote to smaller type!");
3399 SDOperand Tmp1, Tmp2, Tmp3;
3401 SDNode *Node = Op.Val;
3403 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3404 if (I != PromotedNodes.end()) return I->second;
3406 switch (Node->getOpcode()) {
3407 case ISD::CopyFromReg:
3408 assert(0 && "CopyFromReg must be legal!");
3411 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3413 assert(0 && "Do not know how to promote this operator!");
3416 Result = DAG.getNode(ISD::UNDEF, NVT);
3420 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3422 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3423 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3425 case ISD::ConstantFP:
3426 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3427 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3431 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3432 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3433 Node->getOperand(1), Node->getOperand(2));
3437 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3439 Result = LegalizeOp(Node->getOperand(0));
3440 assert(Result.getValueType() >= NVT &&
3441 "This truncation doesn't make sense!");
3442 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3443 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3446 // The truncation is not required, because we don't guarantee anything
3447 // about high bits anyway.
3448 Result = PromoteOp(Node->getOperand(0));
3451 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3452 // Truncate the low part of the expanded value to the result type
3453 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3456 case ISD::SIGN_EXTEND:
3457 case ISD::ZERO_EXTEND:
3458 case ISD::ANY_EXTEND:
3459 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3460 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3462 // Input is legal? Just do extend all the way to the larger type.
3463 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3466 // Promote the reg if it's smaller.
3467 Result = PromoteOp(Node->getOperand(0));
3468 // The high bits are not guaranteed to be anything. Insert an extend.
3469 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3470 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3471 DAG.getValueType(Node->getOperand(0).getValueType()));
3472 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3473 Result = DAG.getZeroExtendInReg(Result,
3474 Node->getOperand(0).getValueType());
3478 case ISD::BIT_CONVERT:
3479 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3480 Result = PromoteOp(Result);
3483 case ISD::FP_EXTEND:
3484 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3486 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3487 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3488 case Promote: assert(0 && "Unreachable with 2 FP types!");
3490 // Input is legal? Do an FP_ROUND_INREG.
3491 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3492 DAG.getValueType(VT));
3497 case ISD::SINT_TO_FP:
3498 case ISD::UINT_TO_FP:
3499 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3501 // No extra round required here.
3502 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3506 Result = PromoteOp(Node->getOperand(0));
3507 if (Node->getOpcode() == ISD::SINT_TO_FP)
3508 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3510 DAG.getValueType(Node->getOperand(0).getValueType()));
3512 Result = DAG.getZeroExtendInReg(Result,
3513 Node->getOperand(0).getValueType());
3514 // No extra round required here.
3515 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3518 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3519 Node->getOperand(0));
3520 // Round if we cannot tolerate excess precision.
3521 if (NoExcessFPPrecision)
3522 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3523 DAG.getValueType(VT));
3528 case ISD::SIGN_EXTEND_INREG:
3529 Result = PromoteOp(Node->getOperand(0));
3530 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3531 Node->getOperand(1));
3533 case ISD::FP_TO_SINT:
3534 case ISD::FP_TO_UINT:
3535 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3538 Tmp1 = Node->getOperand(0);
3541 // The input result is prerounded, so we don't have to do anything
3543 Tmp1 = PromoteOp(Node->getOperand(0));
3546 // If we're promoting a UINT to a larger size, check to see if the new node
3547 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3548 // we can use that instead. This allows us to generate better code for
3549 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3550 // legal, such as PowerPC.
3551 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3552 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3553 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3554 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3555 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3557 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3563 Tmp1 = PromoteOp(Node->getOperand(0));
3564 assert(Tmp1.getValueType() == NVT);
3565 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3566 // NOTE: we do not have to do any extra rounding here for
3567 // NoExcessFPPrecision, because we know the input will have the appropriate
3568 // precision, and these operations don't modify precision at all.
3574 Tmp1 = PromoteOp(Node->getOperand(0));
3575 assert(Tmp1.getValueType() == NVT);
3576 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3577 if (NoExcessFPPrecision)
3578 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3579 DAG.getValueType(VT));
3583 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3584 // directly as well, which may be better.
3585 Tmp1 = PromoteOp(Node->getOperand(0));
3586 assert(Tmp1.getValueType() == NVT);
3587 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3588 if (NoExcessFPPrecision)
3589 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3590 DAG.getValueType(VT));
3600 // The input may have strange things in the top bits of the registers, but
3601 // these operations don't care. They may have weird bits going out, but
3602 // that too is okay if they are integer operations.
3603 Tmp1 = PromoteOp(Node->getOperand(0));
3604 Tmp2 = PromoteOp(Node->getOperand(1));
3605 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3606 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3611 Tmp1 = PromoteOp(Node->getOperand(0));
3612 Tmp2 = PromoteOp(Node->getOperand(1));
3613 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3614 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3616 // Floating point operations will give excess precision that we may not be
3617 // able to tolerate. If we DO allow excess precision, just leave it,
3618 // otherwise excise it.
3619 // FIXME: Why would we need to round FP ops more than integer ones?
3620 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3621 if (NoExcessFPPrecision)
3622 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3623 DAG.getValueType(VT));
3628 // These operators require that their input be sign extended.
3629 Tmp1 = PromoteOp(Node->getOperand(0));
3630 Tmp2 = PromoteOp(Node->getOperand(1));
3631 if (MVT::isInteger(NVT)) {
3632 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3633 DAG.getValueType(VT));
3634 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3635 DAG.getValueType(VT));
3637 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3639 // Perform FP_ROUND: this is probably overly pessimistic.
3640 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3641 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3642 DAG.getValueType(VT));
3646 case ISD::FCOPYSIGN:
3647 // These operators require that their input be fp extended.
3648 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3650 Tmp1 = LegalizeOp(Node->getOperand(0));
3653 Tmp1 = PromoteOp(Node->getOperand(0));
3656 assert(0 && "not implemented");
3658 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3660 Tmp2 = LegalizeOp(Node->getOperand(1));
3663 Tmp2 = PromoteOp(Node->getOperand(1));
3666 assert(0 && "not implemented");
3668 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3670 // Perform FP_ROUND: this is probably overly pessimistic.
3671 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3672 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3673 DAG.getValueType(VT));
3678 // These operators require that their input be zero extended.
3679 Tmp1 = PromoteOp(Node->getOperand(0));
3680 Tmp2 = PromoteOp(Node->getOperand(1));
3681 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3682 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3683 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3684 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3688 Tmp1 = PromoteOp(Node->getOperand(0));
3689 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3692 // The input value must be properly sign extended.
3693 Tmp1 = PromoteOp(Node->getOperand(0));
3694 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3695 DAG.getValueType(VT));
3696 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3699 // The input value must be properly zero extended.
3700 Tmp1 = PromoteOp(Node->getOperand(0));
3701 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3702 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3706 Tmp1 = Node->getOperand(0); // Get the chain.
3707 Tmp2 = Node->getOperand(1); // Get the pointer.
3708 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3709 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3710 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3712 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3713 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3714 SV->getValue(), SV->getOffset());
3715 // Increment the pointer, VAList, to the next vaarg
3716 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3717 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3718 TLI.getPointerTy()));
3719 // Store the incremented VAList to the legalized pointer
3720 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3722 // Load the actual argument out of the pointer VAList
3723 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3725 // Remember that we legalized the chain.
3726 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3730 LoadSDNode *LD = cast<LoadSDNode>(Node);
3731 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3732 ? ISD::EXTLOAD : LD->getExtensionType();
3733 Result = DAG.getExtLoad(ExtType, NVT,
3734 LD->getChain(), LD->getBasePtr(),
3735 LD->getSrcValue(), LD->getSrcValueOffset(),
3738 LD->getAlignment());
3739 // Remember that we legalized the chain.
3740 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3744 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3745 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3746 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3748 case ISD::SELECT_CC:
3749 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3750 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3751 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3752 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3755 Tmp1 = Node->getOperand(0);
3756 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3757 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3758 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3759 DAG.getConstant(MVT::getSizeInBits(NVT) -
3760 MVT::getSizeInBits(VT),
3761 TLI.getShiftAmountTy()));
3766 // Zero extend the argument
3767 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3768 // Perform the larger operation, then subtract if needed.
3769 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3770 switch(Node->getOpcode()) {
3775 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3776 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3777 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3779 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3780 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3783 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3784 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3785 DAG.getConstant(MVT::getSizeInBits(NVT) -
3786 MVT::getSizeInBits(VT), NVT));
3790 case ISD::EXTRACT_SUBVECTOR:
3791 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3793 case ISD::EXTRACT_VECTOR_ELT:
3794 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3798 assert(Result.Val && "Didn't set a result!");
3800 // Make sure the result is itself legal.
3801 Result = LegalizeOp(Result);
3803 // Remember that we promoted this!
3804 AddPromotedOperand(Op, Result);
3808 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3809 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3810 /// based on the vector type. The return type of this matches the element type
3811 /// of the vector, which may not be legal for the target.
3812 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3813 // We know that operand #0 is the Vec vector. If the index is a constant
3814 // or if the invec is a supported hardware type, we can use it. Otherwise,
3815 // lower to a store then an indexed load.
3816 SDOperand Vec = Op.getOperand(0);
3817 SDOperand Idx = Op.getOperand(1);
3819 SDNode *InVal = Vec.Val;
3820 MVT::ValueType TVT = InVal->getValueType(0);
3821 unsigned NumElems = MVT::getVectorNumElements(TVT);
3823 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3824 default: assert(0 && "This action is not supported yet!");
3825 case TargetLowering::Custom: {
3826 Vec = LegalizeOp(Vec);
3827 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3828 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3833 case TargetLowering::Legal:
3834 if (isTypeLegal(TVT)) {
3835 Vec = LegalizeOp(Vec);
3836 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3840 case TargetLowering::Expand:
3844 if (NumElems == 1) {
3845 // This must be an access of the only element. Return it.
3846 Op = ScalarizeVectorOp(Vec);
3847 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3848 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3850 SplitVectorOp(Vec, Lo, Hi);
3851 if (CIdx->getValue() < NumElems/2) {
3855 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3856 Idx.getValueType());
3859 // It's now an extract from the appropriate high or low part. Recurse.
3860 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3861 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3863 // Store the value to a temporary stack slot, then LOAD the scalar
3864 // element back out.
3865 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3866 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3868 // Add the offset to the index.
3869 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3870 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3871 DAG.getConstant(EltSize, Idx.getValueType()));
3872 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3874 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3879 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3880 /// we assume the operation can be split if it is not already legal.
3881 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3882 // We know that operand #0 is the Vec vector. For now we assume the index
3883 // is a constant and that the extracted result is a supported hardware type.
3884 SDOperand Vec = Op.getOperand(0);
3885 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3887 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3889 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3890 // This must be an access of the desired vector length. Return it.
3894 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3896 SplitVectorOp(Vec, Lo, Hi);
3897 if (CIdx->getValue() < NumElems/2) {
3901 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3904 // It's now an extract from the appropriate high or low part. Recurse.
3905 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3906 return ExpandEXTRACT_SUBVECTOR(Op);
3909 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3910 /// with condition CC on the current target. This usually involves legalizing
3911 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3912 /// there may be no choice but to create a new SetCC node to represent the
3913 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3914 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3915 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3918 SDOperand Tmp1, Tmp2, Result;
3920 switch (getTypeAction(LHS.getValueType())) {
3922 Tmp1 = LegalizeOp(LHS); // LHS
3923 Tmp2 = LegalizeOp(RHS); // RHS
3926 Tmp1 = PromoteOp(LHS); // LHS
3927 Tmp2 = PromoteOp(RHS); // RHS
3929 // If this is an FP compare, the operands have already been extended.
3930 if (MVT::isInteger(LHS.getValueType())) {
3931 MVT::ValueType VT = LHS.getValueType();
3932 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3934 // Otherwise, we have to insert explicit sign or zero extends. Note
3935 // that we could insert sign extends for ALL conditions, but zero extend
3936 // is cheaper on many machines (an AND instead of two shifts), so prefer
3938 switch (cast<CondCodeSDNode>(CC)->get()) {
3939 default: assert(0 && "Unknown integer comparison!");
3946 // ALL of these operations will work if we either sign or zero extend
3947 // the operands (including the unsigned comparisons!). Zero extend is
3948 // usually a simpler/cheaper operation, so prefer it.
3949 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3950 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3956 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3957 DAG.getValueType(VT));
3958 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3959 DAG.getValueType(VT));
3965 MVT::ValueType VT = LHS.getValueType();
3966 if (VT == MVT::f32 || VT == MVT::f64) {
3967 // Expand into one or more soft-fp libcall(s).
3968 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3969 switch (cast<CondCodeSDNode>(CC)->get()) {
3972 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3976 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3980 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3984 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3988 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3992 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3995 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3998 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4001 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4002 switch (cast<CondCodeSDNode>(CC)->get()) {
4004 // SETONE = SETOLT | SETOGT
4005 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4008 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4011 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4014 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4017 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4020 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4022 default: assert(0 && "Unsupported FP setcc!");
4027 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4028 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4029 false /*sign irrelevant*/, Dummy);
4030 Tmp2 = DAG.getConstant(0, MVT::i32);
4031 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4032 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4033 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4034 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4035 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4036 false /*sign irrelevant*/, Dummy);
4037 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4038 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4039 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4047 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4048 ExpandOp(LHS, LHSLo, LHSHi);
4049 ExpandOp(RHS, RHSLo, RHSHi);
4050 switch (cast<CondCodeSDNode>(CC)->get()) {
4054 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4055 if (RHSCST->isAllOnesValue()) {
4056 // Comparison to -1.
4057 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4062 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4063 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4064 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4065 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4068 // If this is a comparison of the sign bit, just look at the top part.
4070 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4071 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4072 CST->getValue() == 0) || // X < 0
4073 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4074 CST->isAllOnesValue())) { // X > -1
4080 // FIXME: This generated code sucks.
4081 ISD::CondCode LowCC;
4082 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4084 default: assert(0 && "Unknown integer setcc!");
4086 case ISD::SETULT: LowCC = ISD::SETULT; break;
4088 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4090 case ISD::SETULE: LowCC = ISD::SETULE; break;
4092 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4095 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4096 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4097 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4099 // NOTE: on targets without efficient SELECT of bools, we can always use
4100 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4101 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4102 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4103 false, DagCombineInfo);
4105 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4106 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4107 CCCode, false, DagCombineInfo);
4109 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
4111 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4112 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4113 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4114 (Tmp2C && Tmp2C->getValue() == 0 &&
4115 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4116 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4117 (Tmp2C && Tmp2C->getValue() == 1 &&
4118 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4119 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4120 // low part is known false, returns high part.
4121 // For LE / GE, if high part is known false, ignore the low part.
4122 // For LT / GT, if high part is known true, ignore the low part.
4126 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4127 ISD::SETEQ, false, DagCombineInfo);
4129 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4130 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4131 Result, Tmp1, Tmp2));
4142 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
4143 /// The resultant code need not be legal. Note that SrcOp is the input operand
4144 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
4145 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
4147 // Create the stack frame object.
4148 SDOperand FIPtr = CreateStackTemporary(DestVT);
4150 // Emit a store to the stack slot.
4151 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
4152 // Result is a load from the stack slot.
4153 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4156 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4157 // Create a vector sized/aligned stack slot, store the value to element #0,
4158 // then load the whole vector back out.
4159 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
4160 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4162 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
4166 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4167 /// support the operation, but do support the resultant vector type.
4168 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4170 // If the only non-undef value is the low element, turn this into a
4171 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4172 unsigned NumElems = Node->getNumOperands();
4173 bool isOnlyLowElement = true;
4174 SDOperand SplatValue = Node->getOperand(0);
4175 std::map<SDOperand, std::vector<unsigned> > Values;
4176 Values[SplatValue].push_back(0);
4177 bool isConstant = true;
4178 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4179 SplatValue.getOpcode() != ISD::UNDEF)
4182 for (unsigned i = 1; i < NumElems; ++i) {
4183 SDOperand V = Node->getOperand(i);
4184 Values[V].push_back(i);
4185 if (V.getOpcode() != ISD::UNDEF)
4186 isOnlyLowElement = false;
4187 if (SplatValue != V)
4188 SplatValue = SDOperand(0,0);
4190 // If this isn't a constant element or an undef, we can't use a constant
4192 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4193 V.getOpcode() != ISD::UNDEF)
4197 if (isOnlyLowElement) {
4198 // If the low element is an undef too, then this whole things is an undef.
4199 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4200 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4201 // Otherwise, turn this into a scalar_to_vector node.
4202 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4203 Node->getOperand(0));
4206 // If all elements are constants, create a load from the constant pool.
4208 MVT::ValueType VT = Node->getValueType(0);
4210 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4211 std::vector<Constant*> CV;
4212 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4213 if (ConstantFPSDNode *V =
4214 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4215 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
4216 } else if (ConstantSDNode *V =
4217 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4218 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4220 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4221 CV.push_back(UndefValue::get(OpNTy));
4224 Constant *CP = ConstantVector::get(CV);
4225 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4226 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4229 if (SplatValue.Val) { // Splat of one value?
4230 // Build the shuffle constant vector: <0, 0, 0, 0>
4231 MVT::ValueType MaskVT =
4232 MVT::getIntVectorWithNumElements(NumElems);
4233 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4234 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4235 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4236 &ZeroVec[0], ZeroVec.size());
4238 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4239 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4240 // Get the splatted value into the low element of a vector register.
4241 SDOperand LowValVec =
4242 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4244 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4245 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4246 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4251 // If there are only two unique elements, we may be able to turn this into a
4253 if (Values.size() == 2) {
4254 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4255 MVT::ValueType MaskVT =
4256 MVT::getIntVectorWithNumElements(NumElems);
4257 std::vector<SDOperand> MaskVec(NumElems);
4259 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4260 E = Values.end(); I != E; ++I) {
4261 for (std::vector<unsigned>::iterator II = I->second.begin(),
4262 EE = I->second.end(); II != EE; ++II)
4263 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4266 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4267 &MaskVec[0], MaskVec.size());
4269 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4270 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4271 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4272 SmallVector<SDOperand, 8> Ops;
4273 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4274 E = Values.end(); I != E; ++I) {
4275 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4279 Ops.push_back(ShuffleMask);
4281 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4282 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4283 &Ops[0], Ops.size());
4287 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4288 // aligned object on the stack, store each element into it, then load
4289 // the result as a vector.
4290 MVT::ValueType VT = Node->getValueType(0);
4291 // Create the stack frame object.
4292 SDOperand FIPtr = CreateStackTemporary(VT);
4294 // Emit a store of each element to the stack slot.
4295 SmallVector<SDOperand, 8> Stores;
4296 unsigned TypeByteSize =
4297 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4298 // Store (in the right endianness) the elements to memory.
4299 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4300 // Ignore undef elements.
4301 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4303 unsigned Offset = TypeByteSize*i;
4305 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4306 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4308 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4312 SDOperand StoreChain;
4313 if (!Stores.empty()) // Not all undef elements?
4314 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4315 &Stores[0], Stores.size());
4317 StoreChain = DAG.getEntryNode();
4319 // Result is a load from the stack slot.
4320 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4323 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4324 /// specified value type.
4325 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4326 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4327 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4328 const Type *Ty = MVT::getTypeForValueType(VT);
4329 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4330 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4331 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4334 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4335 SDOperand Op, SDOperand Amt,
4336 SDOperand &Lo, SDOperand &Hi) {
4337 // Expand the subcomponents.
4338 SDOperand LHSL, LHSH;
4339 ExpandOp(Op, LHSL, LHSH);
4341 SDOperand Ops[] = { LHSL, LHSH, Amt };
4342 MVT::ValueType VT = LHSL.getValueType();
4343 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4344 Hi = Lo.getValue(1);
4348 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4349 /// smaller elements. If we can't find a way that is more efficient than a
4350 /// libcall on this target, return false. Otherwise, return true with the
4351 /// low-parts expanded into Lo and Hi.
4352 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4353 SDOperand &Lo, SDOperand &Hi) {
4354 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4355 "This is not a shift!");
4357 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4358 SDOperand ShAmt = LegalizeOp(Amt);
4359 MVT::ValueType ShTy = ShAmt.getValueType();
4360 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4361 unsigned NVTBits = MVT::getSizeInBits(NVT);
4363 // Handle the case when Amt is an immediate. Other cases are currently broken
4364 // and are disabled.
4365 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4366 unsigned Cst = CN->getValue();
4367 // Expand the incoming operand to be shifted, so that we have its parts
4369 ExpandOp(Op, InL, InH);
4373 Lo = DAG.getConstant(0, NVT);
4374 Hi = DAG.getConstant(0, NVT);
4375 } else if (Cst > NVTBits) {
4376 Lo = DAG.getConstant(0, NVT);
4377 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4378 } else if (Cst == NVTBits) {
4379 Lo = DAG.getConstant(0, NVT);
4382 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4383 Hi = DAG.getNode(ISD::OR, NVT,
4384 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4385 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4390 Lo = DAG.getConstant(0, NVT);
4391 Hi = DAG.getConstant(0, NVT);
4392 } else if (Cst > NVTBits) {
4393 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4394 Hi = DAG.getConstant(0, NVT);
4395 } else if (Cst == NVTBits) {
4397 Hi = DAG.getConstant(0, NVT);
4399 Lo = DAG.getNode(ISD::OR, NVT,
4400 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4401 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4402 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4407 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4408 DAG.getConstant(NVTBits-1, ShTy));
4409 } else if (Cst > NVTBits) {
4410 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4411 DAG.getConstant(Cst-NVTBits, ShTy));
4412 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4413 DAG.getConstant(NVTBits-1, ShTy));
4414 } else if (Cst == NVTBits) {
4416 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4417 DAG.getConstant(NVTBits-1, ShTy));
4419 Lo = DAG.getNode(ISD::OR, NVT,
4420 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4421 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4422 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4428 // Okay, the shift amount isn't constant. However, if we can tell that it is
4429 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4430 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4431 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4433 // If we know that the high bit of the shift amount is one, then we can do
4434 // this as a couple of simple shifts.
4435 if (KnownOne & Mask) {
4436 // Mask out the high bit, which we know is set.
4437 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4438 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4440 // Expand the incoming operand to be shifted, so that we have its parts
4442 ExpandOp(Op, InL, InH);
4445 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4446 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4449 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4450 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4453 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4454 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4455 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4460 // If we know that the high bit of the shift amount is zero, then we can do
4461 // this as a couple of simple shifts.
4462 if (KnownZero & Mask) {
4464 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4465 DAG.getConstant(NVTBits, Amt.getValueType()),
4468 // Expand the incoming operand to be shifted, so that we have its parts
4470 ExpandOp(Op, InL, InH);
4473 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4474 Hi = DAG.getNode(ISD::OR, NVT,
4475 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4476 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4479 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4480 Lo = DAG.getNode(ISD::OR, NVT,
4481 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4482 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4485 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4486 Lo = DAG.getNode(ISD::OR, NVT,
4487 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4488 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4497 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4498 // does not fit into a register, return the lo part and set the hi part to the
4499 // by-reg argument. If it does fit into a single register, return the result
4500 // and leave the Hi part unset.
4501 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4502 bool isSigned, SDOperand &Hi) {
4503 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4504 // The input chain to this libcall is the entry node of the function.
4505 // Legalizing the call will automatically add the previous call to the
4507 SDOperand InChain = DAG.getEntryNode();
4509 TargetLowering::ArgListTy Args;
4510 TargetLowering::ArgListEntry Entry;
4511 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4512 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4513 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4514 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4515 Entry.isSExt = isSigned;
4516 Args.push_back(Entry);
4518 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4520 // Splice the libcall in wherever FindInputOutputChains tells us to.
4521 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4522 std::pair<SDOperand,SDOperand> CallInfo =
4523 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4526 // Legalize the call sequence, starting with the chain. This will advance
4527 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4528 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4529 LegalizeOp(CallInfo.second);
4531 switch (getTypeAction(CallInfo.first.getValueType())) {
4532 default: assert(0 && "Unknown thing");
4534 Result = CallInfo.first;
4537 ExpandOp(CallInfo.first, Result, Hi);
4544 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4546 SDOperand SelectionDAGLegalize::
4547 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4548 assert(getTypeAction(Source.getValueType()) == Expand &&
4549 "This is not an expansion!");
4550 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4553 assert(Source.getValueType() == MVT::i64 &&
4554 "This only works for 64-bit -> FP");
4555 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4556 // incoming integer is set. To handle this, we dynamically test to see if
4557 // it is set, and, if so, add a fudge factor.
4559 ExpandOp(Source, Lo, Hi);
4561 // If this is unsigned, and not supported, first perform the conversion to
4562 // signed, then adjust the result if the sign bit is set.
4563 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4564 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4566 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4567 DAG.getConstant(0, Hi.getValueType()),
4569 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4570 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4571 SignSet, Four, Zero);
4572 uint64_t FF = 0x5f800000ULL;
4573 if (TLI.isLittleEndian()) FF <<= 32;
4574 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4576 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4577 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4578 SDOperand FudgeInReg;
4579 if (DestTy == MVT::f32)
4580 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4582 assert(DestTy == MVT::f64 && "Unexpected conversion");
4583 // FIXME: Avoid the extend by construction the right constantpool?
4584 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4585 CPIdx, NULL, 0, MVT::f32);
4587 MVT::ValueType SCVT = SignedConv.getValueType();
4588 if (SCVT != DestTy) {
4589 // Destination type needs to be expanded as well. The FADD now we are
4590 // constructing will be expanded into a libcall.
4591 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4592 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4593 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4594 SignedConv, SignedConv.getValue(1));
4596 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4598 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4601 // Check to see if the target has a custom way to lower this. If so, use it.
4602 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4603 default: assert(0 && "This action not implemented for this operation!");
4604 case TargetLowering::Legal:
4605 case TargetLowering::Expand:
4606 break; // This case is handled below.
4607 case TargetLowering::Custom: {
4608 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4611 return LegalizeOp(NV);
4612 break; // The target decided this was legal after all
4616 // Expand the source, then glue it back together for the call. We must expand
4617 // the source in case it is shared (this pass of legalize must traverse it).
4618 SDOperand SrcLo, SrcHi;
4619 ExpandOp(Source, SrcLo, SrcHi);
4620 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4623 if (DestTy == MVT::f32)
4624 LC = RTLIB::SINTTOFP_I64_F32;
4626 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4627 LC = RTLIB::SINTTOFP_I64_F64;
4630 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4631 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4632 SDOperand UnusedHiPart;
4633 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4637 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4638 /// INT_TO_FP operation of the specified operand when the target requests that
4639 /// we expand it. At this point, we know that the result and operand types are
4640 /// legal for the target.
4641 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4643 MVT::ValueType DestVT) {
4644 if (Op0.getValueType() == MVT::i32) {
4645 // simple 32-bit [signed|unsigned] integer to float/double expansion
4647 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4648 MachineFunction &MF = DAG.getMachineFunction();
4649 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4650 unsigned StackAlign =
4651 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4652 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4653 // get address of 8 byte buffer
4654 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4655 // word offset constant for Hi/Lo address computation
4656 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4657 // set up Hi and Lo (into buffer) address based on endian
4658 SDOperand Hi = StackSlot;
4659 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4660 if (TLI.isLittleEndian())
4663 // if signed map to unsigned space
4664 SDOperand Op0Mapped;
4666 // constant used to invert sign bit (signed to unsigned mapping)
4667 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4668 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4672 // store the lo of the constructed double - based on integer input
4673 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4674 Op0Mapped, Lo, NULL, 0);
4675 // initial hi portion of constructed double
4676 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4677 // store the hi of the constructed double - biased exponent
4678 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4679 // load the constructed double
4680 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4681 // FP constant to bias correct the final result
4682 SDOperand Bias = DAG.getConstantFP(isSigned ?
4683 BitsToDouble(0x4330000080000000ULL)
4684 : BitsToDouble(0x4330000000000000ULL),
4686 // subtract the bias
4687 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4690 // handle final rounding
4691 if (DestVT == MVT::f64) {
4695 // if f32 then cast to f32
4696 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4700 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4701 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4703 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4704 DAG.getConstant(0, Op0.getValueType()),
4706 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4707 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4708 SignSet, Four, Zero);
4710 // If the sign bit of the integer is set, the large number will be treated
4711 // as a negative number. To counteract this, the dynamic code adds an
4712 // offset depending on the data type.
4714 switch (Op0.getValueType()) {
4715 default: assert(0 && "Unsupported integer type!");
4716 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4717 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4718 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4719 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4721 if (TLI.isLittleEndian()) FF <<= 32;
4722 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4724 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4725 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4726 SDOperand FudgeInReg;
4727 if (DestVT == MVT::f32)
4728 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4730 assert(DestVT == MVT::f64 && "Unexpected conversion");
4731 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4732 DAG.getEntryNode(), CPIdx,
4733 NULL, 0, MVT::f32));
4736 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4739 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4740 /// *INT_TO_FP operation of the specified operand when the target requests that
4741 /// we promote it. At this point, we know that the result and operand types are
4742 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4743 /// operation that takes a larger input.
4744 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4745 MVT::ValueType DestVT,
4747 // First step, figure out the appropriate *INT_TO_FP operation to use.
4748 MVT::ValueType NewInTy = LegalOp.getValueType();
4750 unsigned OpToUse = 0;
4752 // Scan for the appropriate larger type to use.
4754 NewInTy = (MVT::ValueType)(NewInTy+1);
4755 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4757 // If the target supports SINT_TO_FP of this type, use it.
4758 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4760 case TargetLowering::Legal:
4761 if (!TLI.isTypeLegal(NewInTy))
4762 break; // Can't use this datatype.
4764 case TargetLowering::Custom:
4765 OpToUse = ISD::SINT_TO_FP;
4769 if (isSigned) continue;
4771 // If the target supports UINT_TO_FP of this type, use it.
4772 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4774 case TargetLowering::Legal:
4775 if (!TLI.isTypeLegal(NewInTy))
4776 break; // Can't use this datatype.
4778 case TargetLowering::Custom:
4779 OpToUse = ISD::UINT_TO_FP;
4784 // Otherwise, try a larger type.
4787 // Okay, we found the operation and type to use. Zero extend our input to the
4788 // desired type then run the operation on it.
4789 return DAG.getNode(OpToUse, DestVT,
4790 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4794 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4795 /// FP_TO_*INT operation of the specified operand when the target requests that
4796 /// we promote it. At this point, we know that the result and operand types are
4797 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4798 /// operation that returns a larger result.
4799 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4800 MVT::ValueType DestVT,
4802 // First step, figure out the appropriate FP_TO*INT operation to use.
4803 MVT::ValueType NewOutTy = DestVT;
4805 unsigned OpToUse = 0;
4807 // Scan for the appropriate larger type to use.
4809 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4810 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4812 // If the target supports FP_TO_SINT returning this type, use it.
4813 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4815 case TargetLowering::Legal:
4816 if (!TLI.isTypeLegal(NewOutTy))
4817 break; // Can't use this datatype.
4819 case TargetLowering::Custom:
4820 OpToUse = ISD::FP_TO_SINT;
4825 // If the target supports FP_TO_UINT of this type, use it.
4826 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4828 case TargetLowering::Legal:
4829 if (!TLI.isTypeLegal(NewOutTy))
4830 break; // Can't use this datatype.
4832 case TargetLowering::Custom:
4833 OpToUse = ISD::FP_TO_UINT;
4838 // Otherwise, try a larger type.
4841 // Okay, we found the operation and type to use. Truncate the result of the
4842 // extended FP_TO_*INT operation to the desired size.
4843 return DAG.getNode(ISD::TRUNCATE, DestVT,
4844 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4847 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4849 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4850 MVT::ValueType VT = Op.getValueType();
4851 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4852 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4854 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4856 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4857 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4858 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4860 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4861 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4862 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4863 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4864 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4865 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4866 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4867 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4868 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4870 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4871 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4872 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4873 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4874 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4875 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4876 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4877 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4878 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4879 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4880 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4881 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4882 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4883 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4884 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4885 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4886 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4887 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4888 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4889 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4890 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4894 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4896 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4898 default: assert(0 && "Cannot expand this yet!");
4900 static const uint64_t mask[6] = {
4901 0x5555555555555555ULL, 0x3333333333333333ULL,
4902 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4903 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4905 MVT::ValueType VT = Op.getValueType();
4906 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4907 unsigned len = MVT::getSizeInBits(VT);
4908 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4909 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4910 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4911 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4912 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4913 DAG.getNode(ISD::AND, VT,
4914 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4919 // for now, we do this:
4920 // x = x | (x >> 1);
4921 // x = x | (x >> 2);
4923 // x = x | (x >>16);
4924 // x = x | (x >>32); // for 64-bit input
4925 // return popcount(~x);
4927 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4928 MVT::ValueType VT = Op.getValueType();
4929 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4930 unsigned len = MVT::getSizeInBits(VT);
4931 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4932 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4933 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4935 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4936 return DAG.getNode(ISD::CTPOP, VT, Op);
4939 // for now, we use: { return popcount(~x & (x - 1)); }
4940 // unless the target has ctlz but not ctpop, in which case we use:
4941 // { return 32 - nlz(~x & (x-1)); }
4942 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4943 MVT::ValueType VT = Op.getValueType();
4944 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4945 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4946 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4947 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4948 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4949 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4950 TLI.isOperationLegal(ISD::CTLZ, VT))
4951 return DAG.getNode(ISD::SUB, VT,
4952 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4953 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4954 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4959 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4960 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4961 /// LegalizeNodes map is filled in for any results that are not expanded, the
4962 /// ExpandedNodes map is filled in for any results that are expanded, and the
4963 /// Lo/Hi values are returned.
4964 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4965 MVT::ValueType VT = Op.getValueType();
4966 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4967 SDNode *Node = Op.Val;
4968 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4969 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4970 MVT::isVector(VT)) &&
4971 "Cannot expand to FP value or to larger int value!");
4973 // See if we already expanded it.
4974 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4975 = ExpandedNodes.find(Op);
4976 if (I != ExpandedNodes.end()) {
4977 Lo = I->second.first;
4978 Hi = I->second.second;
4982 switch (Node->getOpcode()) {
4983 case ISD::CopyFromReg:
4984 assert(0 && "CopyFromReg must be legal!");
4987 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4989 assert(0 && "Do not know how to expand this operator!");
4992 NVT = TLI.getTypeToExpandTo(VT);
4993 Lo = DAG.getNode(ISD::UNDEF, NVT);
4994 Hi = DAG.getNode(ISD::UNDEF, NVT);
4996 case ISD::Constant: {
4997 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4998 Lo = DAG.getConstant(Cst, NVT);
4999 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
5002 case ISD::ConstantFP: {
5003 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5004 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5005 if (getTypeAction(Lo.getValueType()) == Expand)
5006 ExpandOp(Lo, Lo, Hi);
5009 case ISD::BUILD_PAIR:
5010 // Return the operands.
5011 Lo = Node->getOperand(0);
5012 Hi = Node->getOperand(1);
5015 case ISD::SIGN_EXTEND_INREG:
5016 ExpandOp(Node->getOperand(0), Lo, Hi);
5017 // sext_inreg the low part if needed.
5018 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5020 // The high part gets the sign extension from the lo-part. This handles
5021 // things like sextinreg V:i64 from i8.
5022 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5023 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5024 TLI.getShiftAmountTy()));
5028 ExpandOp(Node->getOperand(0), Lo, Hi);
5029 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5030 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5036 ExpandOp(Node->getOperand(0), Lo, Hi);
5037 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5038 DAG.getNode(ISD::CTPOP, NVT, Lo),
5039 DAG.getNode(ISD::CTPOP, NVT, Hi));
5040 Hi = DAG.getConstant(0, NVT);
5044 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5045 ExpandOp(Node->getOperand(0), Lo, Hi);
5046 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5047 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5048 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5050 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5051 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5053 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5054 Hi = DAG.getConstant(0, NVT);
5059 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5060 ExpandOp(Node->getOperand(0), Lo, Hi);
5061 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5062 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5063 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5065 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5066 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5068 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5069 Hi = DAG.getConstant(0, NVT);
5074 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5075 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5076 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5077 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5079 // Remember that we legalized the chain.
5080 Hi = LegalizeOp(Hi);
5081 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5082 if (!TLI.isLittleEndian())
5088 LoadSDNode *LD = cast<LoadSDNode>(Node);
5089 SDOperand Ch = LD->getChain(); // Legalize the chain.
5090 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5091 ISD::LoadExtType ExtType = LD->getExtensionType();
5092 int SVOffset = LD->getSrcValueOffset();
5093 unsigned Alignment = LD->getAlignment();
5094 bool isVolatile = LD->isVolatile();
5096 if (ExtType == ISD::NON_EXTLOAD) {
5097 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5098 isVolatile, Alignment);
5099 if (VT == MVT::f32 || VT == MVT::f64) {
5100 // f32->i32 or f64->i64 one to one expansion.
5101 // Remember that we legalized the chain.
5102 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5103 // Recursively expand the new load.
5104 if (getTypeAction(NVT) == Expand)
5105 ExpandOp(Lo, Lo, Hi);
5109 // Increment the pointer to the other half.
5110 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5111 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5112 getIntPtrConstant(IncrementSize));
5113 SVOffset += IncrementSize;
5114 if (Alignment > IncrementSize)
5115 Alignment = IncrementSize;
5116 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5117 isVolatile, Alignment);
5119 // Build a factor node to remember that this load is independent of the
5121 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5124 // Remember that we legalized the chain.
5125 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5126 if (!TLI.isLittleEndian())
5129 MVT::ValueType EVT = LD->getLoadedVT();
5131 if (VT == MVT::f64 && EVT == MVT::f32) {
5132 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5133 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5134 SVOffset, isVolatile, Alignment);
5135 // Remember that we legalized the chain.
5136 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5137 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5142 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5143 SVOffset, isVolatile, Alignment);
5145 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5146 SVOffset, EVT, isVolatile,
5149 // Remember that we legalized the chain.
5150 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5152 if (ExtType == ISD::SEXTLOAD) {
5153 // The high part is obtained by SRA'ing all but one of the bits of the
5155 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5156 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5157 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5158 } else if (ExtType == ISD::ZEXTLOAD) {
5159 // The high part is just a zero.
5160 Hi = DAG.getConstant(0, NVT);
5161 } else /* if (ExtType == ISD::EXTLOAD) */ {
5162 // The high part is undefined.
5163 Hi = DAG.getNode(ISD::UNDEF, NVT);
5170 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5171 SDOperand LL, LH, RL, RH;
5172 ExpandOp(Node->getOperand(0), LL, LH);
5173 ExpandOp(Node->getOperand(1), RL, RH);
5174 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5175 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5179 SDOperand LL, LH, RL, RH;
5180 ExpandOp(Node->getOperand(1), LL, LH);
5181 ExpandOp(Node->getOperand(2), RL, RH);
5182 if (getTypeAction(NVT) == Expand)
5183 NVT = TLI.getTypeToExpandTo(NVT);
5184 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5186 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5189 case ISD::SELECT_CC: {
5190 SDOperand TL, TH, FL, FH;
5191 ExpandOp(Node->getOperand(2), TL, TH);
5192 ExpandOp(Node->getOperand(3), FL, FH);
5193 if (getTypeAction(NVT) == Expand)
5194 NVT = TLI.getTypeToExpandTo(NVT);
5195 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5196 Node->getOperand(1), TL, FL, Node->getOperand(4));
5198 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
5199 Node->getOperand(1), TH, FH, Node->getOperand(4));
5202 case ISD::ANY_EXTEND:
5203 // The low part is any extension of the input (which degenerates to a copy).
5204 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
5205 // The high part is undefined.
5206 Hi = DAG.getNode(ISD::UNDEF, NVT);
5208 case ISD::SIGN_EXTEND: {
5209 // The low part is just a sign extension of the input (which degenerates to
5211 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
5213 // The high part is obtained by SRA'ing all but one of the bits of the lo
5215 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5216 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5217 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5220 case ISD::ZERO_EXTEND:
5221 // The low part is just a zero extension of the input (which degenerates to
5223 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
5225 // The high part is just a zero.
5226 Hi = DAG.getConstant(0, NVT);
5229 case ISD::TRUNCATE: {
5230 // The input value must be larger than this value. Expand *it*.
5232 ExpandOp(Node->getOperand(0), NewLo, Hi);
5234 // The low part is now either the right size, or it is closer. If not the
5235 // right size, make an illegal truncate so we recursively expand it.
5236 if (NewLo.getValueType() != Node->getValueType(0))
5237 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5238 ExpandOp(NewLo, Lo, Hi);
5242 case ISD::BIT_CONVERT: {
5244 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5245 // If the target wants to, allow it to lower this itself.
5246 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5247 case Expand: assert(0 && "cannot expand FP!");
5248 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5249 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5251 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5254 // f32 / f64 must be expanded to i32 / i64.
5255 if (VT == MVT::f32 || VT == MVT::f64) {
5256 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5257 if (getTypeAction(NVT) == Expand)
5258 ExpandOp(Lo, Lo, Hi);
5262 // If source operand will be expanded to the same type as VT, i.e.
5263 // i64 <- f64, i32 <- f32, expand the source operand instead.
5264 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5265 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5266 ExpandOp(Node->getOperand(0), Lo, Hi);
5270 // Turn this into a load/store pair by default.
5272 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5274 ExpandOp(Tmp, Lo, Hi);
5278 case ISD::READCYCLECOUNTER:
5279 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5280 TargetLowering::Custom &&
5281 "Must custom expand ReadCycleCounter");
5282 Lo = TLI.LowerOperation(Op, DAG);
5283 assert(Lo.Val && "Node must be custom expanded!");
5284 Hi = Lo.getValue(1);
5285 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5286 LegalizeOp(Lo.getValue(2)));
5289 // These operators cannot be expanded directly, emit them as calls to
5290 // library functions.
5291 case ISD::FP_TO_SINT: {
5292 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5294 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5295 case Expand: assert(0 && "cannot expand FP!");
5296 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5297 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5300 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5302 // Now that the custom expander is done, expand the result, which is still
5305 ExpandOp(Op, Lo, Hi);
5311 if (Node->getOperand(0).getValueType() == MVT::f32)
5312 LC = RTLIB::FPTOSINT_F32_I64;
5314 LC = RTLIB::FPTOSINT_F64_I64;
5315 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5316 false/*sign irrelevant*/, Hi);
5320 case ISD::FP_TO_UINT: {
5321 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5323 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5324 case Expand: assert(0 && "cannot expand FP!");
5325 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5326 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5329 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5331 // Now that the custom expander is done, expand the result.
5333 ExpandOp(Op, Lo, Hi);
5339 if (Node->getOperand(0).getValueType() == MVT::f32)
5340 LC = RTLIB::FPTOUINT_F32_I64;
5342 LC = RTLIB::FPTOUINT_F64_I64;
5343 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5344 false/*sign irrelevant*/, Hi);
5349 // If the target wants custom lowering, do so.
5350 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5351 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5352 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5353 Op = TLI.LowerOperation(Op, DAG);
5355 // Now that the custom expander is done, expand the result, which is
5357 ExpandOp(Op, Lo, Hi);
5362 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5363 // this X << 1 as X+X.
5364 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5365 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5366 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5367 SDOperand LoOps[2], HiOps[3];
5368 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5369 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5370 LoOps[1] = LoOps[0];
5371 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5373 HiOps[1] = HiOps[0];
5374 HiOps[2] = Lo.getValue(1);
5375 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5380 // If we can emit an efficient shift operation, do so now.
5381 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5384 // If this target supports SHL_PARTS, use it.
5385 TargetLowering::LegalizeAction Action =
5386 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5387 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5388 Action == TargetLowering::Custom) {
5389 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5393 // Otherwise, emit a libcall.
5394 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5395 false/*left shift=unsigned*/, Hi);
5400 // If the target wants custom lowering, do so.
5401 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5402 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5403 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5404 Op = TLI.LowerOperation(Op, DAG);
5406 // Now that the custom expander is done, expand the result, which is
5408 ExpandOp(Op, Lo, Hi);
5413 // If we can emit an efficient shift operation, do so now.
5414 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5417 // If this target supports SRA_PARTS, use it.
5418 TargetLowering::LegalizeAction Action =
5419 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5420 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5421 Action == TargetLowering::Custom) {
5422 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5426 // Otherwise, emit a libcall.
5427 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5428 true/*ashr is signed*/, Hi);
5433 // If the target wants custom lowering, do so.
5434 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5435 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5436 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5437 Op = TLI.LowerOperation(Op, DAG);
5439 // Now that the custom expander is done, expand the result, which is
5441 ExpandOp(Op, Lo, Hi);
5446 // If we can emit an efficient shift operation, do so now.
5447 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5450 // If this target supports SRL_PARTS, use it.
5451 TargetLowering::LegalizeAction Action =
5452 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5453 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5454 Action == TargetLowering::Custom) {
5455 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5459 // Otherwise, emit a libcall.
5460 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5461 false/*lshr is unsigned*/, Hi);
5467 // If the target wants to custom expand this, let them.
5468 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5469 TargetLowering::Custom) {
5470 Op = TLI.LowerOperation(Op, DAG);
5472 ExpandOp(Op, Lo, Hi);
5477 // Expand the subcomponents.
5478 SDOperand LHSL, LHSH, RHSL, RHSH;
5479 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5480 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5481 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5482 SDOperand LoOps[2], HiOps[3];
5487 if (Node->getOpcode() == ISD::ADD) {
5488 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5489 HiOps[2] = Lo.getValue(1);
5490 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5492 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5493 HiOps[2] = Lo.getValue(1);
5494 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5501 // Expand the subcomponents.
5502 SDOperand LHSL, LHSH, RHSL, RHSH;
5503 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5504 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5505 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5506 SDOperand LoOps[2] = { LHSL, RHSL };
5507 SDOperand HiOps[3] = { LHSH, RHSH };
5509 if (Node->getOpcode() == ISD::ADDC) {
5510 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5511 HiOps[2] = Lo.getValue(1);
5512 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5514 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5515 HiOps[2] = Lo.getValue(1);
5516 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5518 // Remember that we legalized the flag.
5519 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5524 // Expand the subcomponents.
5525 SDOperand LHSL, LHSH, RHSL, RHSH;
5526 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5527 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5528 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5529 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5530 SDOperand HiOps[3] = { LHSH, RHSH };
5532 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5533 HiOps[2] = Lo.getValue(1);
5534 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5536 // Remember that we legalized the flag.
5537 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5541 // If the target wants to custom expand this, let them.
5542 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5543 SDOperand New = TLI.LowerOperation(Op, DAG);
5545 ExpandOp(New, Lo, Hi);
5550 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5551 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5552 if (HasMULHS || HasMULHU) {
5553 SDOperand LL, LH, RL, RH;
5554 ExpandOp(Node->getOperand(0), LL, LH);
5555 ExpandOp(Node->getOperand(1), RL, RH);
5556 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5557 // FIXME: Move this to the dag combiner.
5558 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5559 // extended the sign bit of the low half through the upper half, and if so
5560 // emit a MULHS instead of the alternate sequence that is valid for any
5561 // i64 x i64 multiply.
5563 // is RH an extension of the sign bit of RL?
5564 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5565 RH.getOperand(1).getOpcode() == ISD::Constant &&
5566 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5567 // is LH an extension of the sign bit of LL?
5568 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5569 LH.getOperand(1).getOpcode() == ISD::Constant &&
5570 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5572 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5574 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5576 } else if (HasMULHU) {
5578 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5581 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5582 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5583 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5584 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5585 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5590 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5591 false/*sign irrelevant*/, Hi);
5595 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5598 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5601 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5604 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5608 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5609 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5613 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5614 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5618 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5619 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5623 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5624 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5627 case ISD::FP_EXTEND:
5628 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5631 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5634 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5635 ? RTLIB::POWI_F32 : RTLIB::POWI_F64),
5641 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5642 switch(Node->getOpcode()) {
5644 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5647 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5650 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5652 default: assert(0 && "Unreachable!");
5654 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5658 SDOperand Mask = (VT == MVT::f64)
5659 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5660 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5661 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5662 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5663 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5664 if (getTypeAction(NVT) == Expand)
5665 ExpandOp(Lo, Lo, Hi);
5669 SDOperand Mask = (VT == MVT::f64)
5670 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5671 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5672 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5673 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5674 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5675 if (getTypeAction(NVT) == Expand)
5676 ExpandOp(Lo, Lo, Hi);
5679 case ISD::FCOPYSIGN: {
5680 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5681 if (getTypeAction(NVT) == Expand)
5682 ExpandOp(Lo, Lo, Hi);
5685 case ISD::SINT_TO_FP:
5686 case ISD::UINT_TO_FP: {
5687 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5688 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5690 if (Node->getOperand(0).getValueType() == MVT::i64) {
5692 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5694 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5697 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5699 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5702 // Promote the operand if needed.
5703 if (getTypeAction(SrcVT) == Promote) {
5704 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5706 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5707 DAG.getValueType(SrcVT))
5708 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5709 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5712 const char *LibCall = TLI.getLibcallName(LC);
5714 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5716 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5717 Node->getOperand(0));
5718 if (getTypeAction(Lo.getValueType()) == Expand)
5719 ExpandOp(Lo, Lo, Hi);
5725 // Make sure the resultant values have been legalized themselves, unless this
5726 // is a type that requires multi-step expansion.
5727 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5728 Lo = LegalizeOp(Lo);
5730 // Don't legalize the high part if it is expanded to a single node.
5731 Hi = LegalizeOp(Hi);
5734 // Remember in a map if the values will be reused later.
5735 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5736 assert(isNew && "Value already expanded?!?");
5739 /// SplitVectorOp - Given an operand of vector type, break it down into
5740 /// two smaller values, still of vector type.
5741 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5743 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5744 SDNode *Node = Op.Val;
5745 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5746 assert(NumElements > 1 && "Cannot split a single element vector!");
5747 unsigned NewNumElts = NumElements/2;
5748 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5749 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5751 // See if we already split it.
5752 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5753 = SplitNodes.find(Op);
5754 if (I != SplitNodes.end()) {
5755 Lo = I->second.first;
5756 Hi = I->second.second;
5760 switch (Node->getOpcode()) {
5765 assert(0 && "Unhandled operation in SplitVectorOp!");
5766 case ISD::BUILD_PAIR:
5767 Lo = Node->getOperand(0);
5768 Hi = Node->getOperand(1);
5770 case ISD::BUILD_VECTOR: {
5771 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5772 Node->op_begin()+NewNumElts);
5773 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5775 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5777 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5780 case ISD::CONCAT_VECTORS: {
5781 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5782 if (NewNumSubvectors == 1) {
5783 Lo = Node->getOperand(0);
5784 Hi = Node->getOperand(1);
5786 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5787 Node->op_begin()+NewNumSubvectors);
5788 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5790 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5792 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5808 SDOperand LL, LH, RL, RH;
5809 SplitVectorOp(Node->getOperand(0), LL, LH);
5810 SplitVectorOp(Node->getOperand(1), RL, RH);
5812 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5813 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5817 LoadSDNode *LD = cast<LoadSDNode>(Node);
5818 SDOperand Ch = LD->getChain();
5819 SDOperand Ptr = LD->getBasePtr();
5820 const Value *SV = LD->getSrcValue();
5821 int SVOffset = LD->getSrcValueOffset();
5822 unsigned Alignment = LD->getAlignment();
5823 bool isVolatile = LD->isVolatile();
5825 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5826 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5827 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5828 getIntPtrConstant(IncrementSize));
5829 SVOffset += IncrementSize;
5830 if (Alignment > IncrementSize)
5831 Alignment = IncrementSize;
5832 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5834 // Build a factor node to remember that this load is independent of the
5836 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5839 // Remember that we legalized the chain.
5840 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5843 case ISD::BIT_CONVERT: {
5844 // We know the result is a vector. The input may be either a vector or a
5846 SDOperand InOp = Node->getOperand(0);
5847 if (!MVT::isVector(InOp.getValueType()) ||
5848 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5849 // The input is a scalar or single-element vector.
5850 // Lower to a store/load so that it can be split.
5851 // FIXME: this could be improved probably.
5852 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5854 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5855 InOp, Ptr, NULL, 0);
5856 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5858 // Split the vector and convert each of the pieces now.
5859 SplitVectorOp(InOp, Lo, Hi);
5860 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5861 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5866 // Remember in a map if the values will be reused later.
5868 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5869 assert(isNew && "Value already split?!?");
5873 /// ScalarizeVectorOp - Given an operand of single-element vector type
5874 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5875 /// scalar (e.g. f32) value.
5876 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5877 assert(MVT::isVector(Op.getValueType()) &&
5878 "Bad ScalarizeVectorOp invocation!");
5879 SDNode *Node = Op.Val;
5880 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5881 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5883 // See if we already scalarized it.
5884 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5885 if (I != ScalarizedNodes.end()) return I->second;
5888 switch (Node->getOpcode()) {
5891 Node->dump(&DAG); cerr << "\n";
5893 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5909 Result = DAG.getNode(Node->getOpcode(),
5911 ScalarizeVectorOp(Node->getOperand(0)),
5912 ScalarizeVectorOp(Node->getOperand(1)));
5919 Result = DAG.getNode(Node->getOpcode(),
5921 ScalarizeVectorOp(Node->getOperand(0)));
5924 LoadSDNode *LD = cast<LoadSDNode>(Node);
5925 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5926 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5928 const Value *SV = LD->getSrcValue();
5929 int SVOffset = LD->getSrcValueOffset();
5930 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5931 LD->isVolatile(), LD->getAlignment());
5933 // Remember that we legalized the chain.
5934 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5937 case ISD::BUILD_VECTOR:
5938 Result = Node->getOperand(0);
5940 case ISD::INSERT_VECTOR_ELT:
5941 // Returning the inserted scalar element.
5942 Result = Node->getOperand(1);
5944 case ISD::CONCAT_VECTORS:
5945 assert(Node->getOperand(0).getValueType() == NewVT &&
5946 "Concat of non-legal vectors not yet supported!");
5947 Result = Node->getOperand(0);
5949 case ISD::VECTOR_SHUFFLE: {
5950 // Figure out if the scalar is the LHS or RHS and return it.
5951 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5952 if (cast<ConstantSDNode>(EltNum)->getValue())
5953 Result = ScalarizeVectorOp(Node->getOperand(1));
5955 Result = ScalarizeVectorOp(Node->getOperand(0));
5958 case ISD::EXTRACT_SUBVECTOR:
5959 Result = Node->getOperand(0);
5960 assert(Result.getValueType() == NewVT);
5962 case ISD::BIT_CONVERT:
5963 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5966 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5967 ScalarizeVectorOp(Op.getOperand(1)),
5968 ScalarizeVectorOp(Op.getOperand(2)));
5972 if (TLI.isTypeLegal(NewVT))
5973 Result = LegalizeOp(Result);
5974 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
5975 assert(isNew && "Value already scalarized?");
5980 // SelectionDAG::Legalize - This is the entry point for the file.
5982 void SelectionDAG::Legalize() {
5983 if (ViewLegalizeDAGs) viewGraph();
5985 /// run - This is the main entry point to this class.
5987 SelectionDAGLegalize(*this).LegalizeDAG();