1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
81 assert(isNew && "Got into the map somehow?");
83 void AddPromotedOperand(SDOperand From, SDOperand To) {
84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
85 assert(isNew && "Got into the map somehow?");
90 SelectionDAGLegalize(SelectionDAG &DAG);
92 /// Run - While there is still lowering to do, perform a pass over the DAG.
93 /// Most regularization can be done in a single pass, but targets that require
94 /// large values to be split into registers multiple times (e.g. i64 -> 4x
95 /// i16) require iteration for these values (the first iteration will demote
96 /// to i32, the second will demote to i16).
99 NeedsAnotherIteration = false;
101 } while (NeedsAnotherIteration);
104 /// getTypeAction - Return how we should legalize values of this type, either
105 /// it is already legal or we need to expand it into multiple registers of
106 /// smaller integer type, or we need to promote it to a larger type.
107 LegalizeAction getTypeAction(MVT::ValueType VT) const {
108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
111 /// isTypeLegal - Return true if this type is legal on this target.
113 bool isTypeLegal(MVT::ValueType VT) const {
114 return getTypeAction(VT) == Legal;
120 SDOperand LegalizeOp(SDOperand O);
121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
122 SDOperand PromoteOp(SDOperand O);
124 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
129 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
131 MVT::ValueType DestVT);
132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
138 SDOperand &Lo, SDOperand &Hi);
139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
140 SDOperand &Lo, SDOperand &Hi);
141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
142 SDOperand &Lo, SDOperand &Hi);
144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
146 SDOperand getIntPtrConstant(uint64_t Val) {
147 return DAG.getConstant(Val, TLI.getPointerTy());
152 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
154 default: assert(0 && "Don't know how to scalarize this opcode!");
155 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
156 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
157 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
161 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
162 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
163 ValueTypeActions(TLI.getValueTypeActions()) {
164 assert(MVT::LAST_VALUETYPE <= 32 &&
165 "Too many value types for ValueTypeActions to hold!");
168 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
169 /// INT_TO_FP operation of the specified operand when the target requests that
170 /// we expand it. At this point, we know that the result and operand types are
171 /// legal for the target.
172 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
174 MVT::ValueType DestVT) {
175 if (Op0.getValueType() == MVT::i32) {
176 // simple 32-bit [signed|unsigned] integer to float/double expansion
178 // get the stack frame index of a 8 byte buffer
179 MachineFunction &MF = DAG.getMachineFunction();
180 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
181 // get address of 8 byte buffer
182 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
183 // word offset constant for Hi/Lo address computation
184 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
185 // set up Hi and Lo (into buffer) address based on endian
187 if (TLI.isLittleEndian()) {
188 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
192 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
194 // if signed map to unsigned space
197 // constant used to invert sign bit (signed to unsigned mapping)
198 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
199 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
203 // store the lo of the constructed double - based on integer input
204 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
205 Op0Mapped, Lo, DAG.getSrcValue(NULL));
206 // initial hi portion of constructed double
207 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
208 // store the hi of the constructed double - biased exponent
209 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
210 InitialHi, Hi, DAG.getSrcValue(NULL));
211 // load the constructed double
212 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
213 DAG.getSrcValue(NULL));
214 // FP constant to bias correct the final result
215 SDOperand Bias = DAG.getConstantFP(isSigned ?
216 BitsToDouble(0x4330000080000000ULL)
217 : BitsToDouble(0x4330000000000000ULL),
220 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
223 // handle final rounding
224 if (DestVT == MVT::f64) {
228 // if f32 then cast to f32
229 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
231 NeedsAnotherIteration = true;
234 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
235 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
237 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
238 DAG.getConstant(0, Op0.getValueType()),
240 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
241 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
242 SignSet, Four, Zero);
244 // If the sign bit of the integer is set, the large number will be treated
245 // as a negative number. To counteract this, the dynamic code adds an
246 // offset depending on the data type.
248 switch (Op0.getValueType()) {
249 default: assert(0 && "Unsupported integer type!");
250 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
251 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
252 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
253 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
255 if (TLI.isLittleEndian()) FF <<= 32;
256 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
258 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
259 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
260 SDOperand FudgeInReg;
261 if (DestVT == MVT::f32)
262 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
263 DAG.getSrcValue(NULL));
265 assert(DestVT == MVT::f64 && "Unexpected conversion");
266 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
267 DAG.getEntryNode(), CPIdx,
268 DAG.getSrcValue(NULL), MVT::f32));
271 NeedsAnotherIteration = true;
272 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
275 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
276 /// *INT_TO_FP operation of the specified operand when the target requests that
277 /// we promote it. At this point, we know that the result and operand types are
278 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
279 /// operation that takes a larger input.
280 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
281 MVT::ValueType DestVT,
283 // First step, figure out the appropriate *INT_TO_FP operation to use.
284 MVT::ValueType NewInTy = LegalOp.getValueType();
286 unsigned OpToUse = 0;
288 // Scan for the appropriate larger type to use.
290 NewInTy = (MVT::ValueType)(NewInTy+1);
291 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
293 // If the target supports SINT_TO_FP of this type, use it.
294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
296 case TargetLowering::Legal:
297 if (!TLI.isTypeLegal(NewInTy))
298 break; // Can't use this datatype.
300 case TargetLowering::Custom:
301 OpToUse = ISD::SINT_TO_FP;
305 if (isSigned) continue;
307 // If the target supports UINT_TO_FP of this type, use it.
308 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
310 case TargetLowering::Legal:
311 if (!TLI.isTypeLegal(NewInTy))
312 break; // Can't use this datatype.
314 case TargetLowering::Custom:
315 OpToUse = ISD::UINT_TO_FP;
320 // Otherwise, try a larger type.
323 // Make sure to legalize any nodes we create here in the next pass.
324 NeedsAnotherIteration = true;
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 return DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
333 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
334 /// FP_TO_*INT operation of the specified operand when the target requests that
335 /// we promote it. At this point, we know that the result and operand types are
336 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
337 /// operation that returns a larger result.
338 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
339 MVT::ValueType DestVT,
341 // First step, figure out the appropriate FP_TO*INT operation to use.
342 MVT::ValueType NewOutTy = DestVT;
344 unsigned OpToUse = 0;
346 // Scan for the appropriate larger type to use.
348 NewOutTy = (MVT::ValueType)(NewOutTy+1);
349 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
351 // If the target supports FP_TO_SINT returning this type, use it.
352 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
354 case TargetLowering::Legal:
355 if (!TLI.isTypeLegal(NewOutTy))
356 break; // Can't use this datatype.
358 case TargetLowering::Custom:
359 OpToUse = ISD::FP_TO_SINT;
364 // If the target supports FP_TO_UINT of this type, use it.
365 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
367 case TargetLowering::Legal:
368 if (!TLI.isTypeLegal(NewOutTy))
369 break; // Can't use this datatype.
371 case TargetLowering::Custom:
372 OpToUse = ISD::FP_TO_UINT;
377 // Otherwise, try a larger type.
380 // Make sure to legalize any nodes we create here in the next pass.
381 NeedsAnotherIteration = true;
383 // Okay, we found the operation and type to use. Truncate the result of the
384 // extended FP_TO_*INT operation to the desired size.
385 return DAG.getNode(ISD::TRUNCATE, DestVT,
386 DAG.getNode(OpToUse, NewOutTy, LegalOp));
389 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
390 /// not been visited yet and if all of its operands have already been visited.
391 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
392 std::map<SDNode*, unsigned> &Visited) {
393 if (++Visited[N] != N->getNumOperands())
394 return; // Haven't visited all operands yet
398 if (N->hasOneUse()) { // Tail recurse in common case.
399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
403 // Now that we have N in, add anything that uses it if all of their operands
405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
406 ComputeTopDownOrdering(*UI, Order, Visited);
410 void SelectionDAGLegalize::LegalizeDAG() {
411 // The legalize process is inherently a bottom-up recursive process (users
412 // legalize their uses before themselves). Given infinite stack space, we
413 // could just start legalizing on the root and traverse the whole graph. In
414 // practice however, this causes us to run out of stack space on large basic
415 // blocks. To avoid this problem, compute an ordering of the nodes where each
416 // node is only legalized after all of its operands are legalized.
417 std::map<SDNode*, unsigned> Visited;
418 std::vector<SDNode*> Order;
420 // Compute ordering from all of the leaves in the graphs, those (like the
421 // entry node) that have no operands.
422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
423 E = DAG.allnodes_end(); I != E; ++I) {
424 if (I->getNumOperands() == 0) {
426 ComputeTopDownOrdering(I, Order, Visited);
430 assert(Order.size() == Visited.size() &&
432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
433 "Error: DAG is cyclic!");
436 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
437 SDNode *N = Order[i];
438 switch (getTypeAction(N->getValueType(0))) {
439 default: assert(0 && "Bad type action!");
441 LegalizeOp(SDOperand(N, 0));
444 PromoteOp(SDOperand(N, 0));
448 ExpandOp(SDOperand(N, 0), X, Y);
454 // Finally, it's possible the root changed. Get the new root.
455 SDOperand OldRoot = DAG.getRoot();
456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
457 DAG.setRoot(LegalizedNodes[OldRoot]);
459 ExpandedNodes.clear();
460 LegalizedNodes.clear();
461 PromotedNodes.clear();
463 // Remove dead nodes now.
464 DAG.RemoveDeadNodes(OldRoot.Val);
467 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
468 assert(isTypeLegal(Op.getValueType()) &&
469 "Caller should expand or promote operands that are not legal!");
470 SDNode *Node = Op.Val;
472 // If this operation defines any values that cannot be represented in a
473 // register on this target, make sure to expand or promote them.
474 if (Node->getNumValues() > 1) {
475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
476 switch (getTypeAction(Node->getValueType(i))) {
477 case Legal: break; // Nothing to do.
480 ExpandOp(Op.getValue(i), T1, T2);
481 assert(LegalizedNodes.count(Op) &&
482 "Expansion didn't add legal operands!");
483 return LegalizedNodes[Op];
486 PromoteOp(Op.getValue(i));
487 assert(LegalizedNodes.count(Op) &&
488 "Expansion didn't add legal operands!");
489 return LegalizedNodes[Op];
493 // Note that LegalizeOp may be reentered even from single-use nodes, which
494 // means that we always must cache transformed nodes.
495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
496 if (I != LegalizedNodes.end()) return I->second;
498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
500 SDOperand Result = Op;
502 switch (Node->getOpcode()) {
504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
505 // If this is a target node, legalize it by legalizing the operands then
506 // passing it through.
507 std::vector<SDOperand> Ops;
508 bool Changed = false;
509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
510 Ops.push_back(LegalizeOp(Node->getOperand(i)));
511 Changed = Changed || Node->getOperand(i) != Ops.back();
514 if (Node->getNumValues() == 1)
515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
517 std::vector<MVT::ValueType> VTs(Node->value_begin(),
519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
524 return Result.getValue(Op.ResNo);
526 // Otherwise this is an unhandled builtin node. splat.
527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
528 assert(0 && "Do not know how to legalize this operator!");
530 case ISD::EntryToken:
531 case ISD::FrameIndex:
532 case ISD::TargetFrameIndex:
534 case ISD::TargetConstant:
535 case ISD::GlobalAddress:
536 case ISD::TargetGlobalAddress:
537 case ISD::ExternalSymbol:
538 case ISD::ConstantPool: // Nothing to do.
539 case ISD::BasicBlock:
544 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
545 default: assert(0 && "This action is not supported yet!");
546 case TargetLowering::Custom: {
547 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
549 Result = LegalizeOp(Tmp);
552 } // FALLTHROUGH if the target doesn't want to lower this op after all.
553 case TargetLowering::Legal:
554 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
558 case ISD::AssertSext:
559 case ISD::AssertZext:
560 Tmp1 = LegalizeOp(Node->getOperand(0));
561 if (Tmp1 != Node->getOperand(0))
562 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
563 Node->getOperand(1));
565 case ISD::MERGE_VALUES:
566 return LegalizeOp(Node->getOperand(Op.ResNo));
567 case ISD::CopyFromReg:
568 Tmp1 = LegalizeOp(Node->getOperand(0));
569 if (Tmp1 != Node->getOperand(0))
570 Result = DAG.getCopyFromReg(Tmp1,
571 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
572 Node->getValueType(0));
574 Result = Op.getValue(0);
576 // Since CopyFromReg produces two values, make sure to remember that we
577 // legalized both of them.
578 AddLegalizedOperand(Op.getValue(0), Result);
579 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
580 return Result.getValue(Op.ResNo);
581 case ISD::ImplicitDef:
582 Tmp1 = LegalizeOp(Node->getOperand(0));
583 if (Tmp1 != Node->getOperand(0))
584 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
585 Tmp1, Node->getOperand(1));
588 MVT::ValueType VT = Op.getValueType();
589 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
590 default: assert(0 && "This action is not supported yet!");
591 case TargetLowering::Expand:
592 case TargetLowering::Promote:
593 if (MVT::isInteger(VT))
594 Result = DAG.getConstant(0, VT);
595 else if (MVT::isFloatingPoint(VT))
596 Result = DAG.getConstantFP(0, VT);
598 assert(0 && "Unknown value type!");
600 case TargetLowering::Legal:
607 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
608 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
610 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
611 case TargetLowering::Promote:
612 default: assert(0 && "This action is not supported yet!");
613 case TargetLowering::Expand:
614 // If the target doesn't support line numbers, ignore this node.
617 case TargetLowering::Legal:
618 if (Tmp1 != Node->getOperand(0) ||
619 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
620 std::vector<SDOperand> Ops;
622 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
623 Ops.push_back(Node->getOperand(1)); // line # must be legal.
624 Ops.push_back(Node->getOperand(2)); // col # must be legal.
626 // Otherwise promote them.
627 Ops.push_back(PromoteOp(Node->getOperand(1)));
628 Ops.push_back(PromoteOp(Node->getOperand(2)));
630 Ops.push_back(Node->getOperand(3)); // filename must be legal.
631 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
632 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
639 // We know we don't need to expand constants here, constants only have one
640 // value and we check that it is fine above.
642 // FIXME: Maybe we should handle things like targets that don't support full
643 // 32-bit immediates?
645 case ISD::ConstantFP: {
646 // Spill FP immediates to the constant pool if the target cannot directly
647 // codegen them. Targets often have some immediate values that can be
648 // efficiently generated into an FP register without a load. We explicitly
649 // leave these constants as ConstantFP nodes for the target to deal with.
651 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
653 // Check to see if this FP immediate is already legal.
654 bool isLegal = false;
655 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
656 E = TLI.legal_fpimm_end(); I != E; ++I)
657 if (CFP->isExactlyValue(*I)) {
663 // Otherwise we need to spill the constant to memory.
666 // If a FP immediate is precise when represented as a float, we put it
667 // into the constant pool as a float, even if it's is statically typed
669 MVT::ValueType VT = CFP->getValueType(0);
670 bool isDouble = VT == MVT::f64;
671 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
672 Type::FloatTy, CFP->getValue());
673 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
674 // Only do this if the target has a native EXTLOAD instruction from
676 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
677 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
682 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
684 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
685 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
687 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
688 DAG.getSrcValue(NULL));
693 case ISD::ConstantVec: {
694 // We assume that vector constants are not legal, and will be immediately
695 // spilled to the constant pool.
697 // FIXME: revisit this when we have some kind of mechanism by which targets
698 // can decided legality of vector constants, of which there may be very
701 // Create a ConstantPacked, and put it in the constant pool.
702 std::vector<Constant*> CV;
703 MVT::ValueType VT = Node->getValueType(0);
704 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
705 SDOperand OpN = Node->getOperand(I);
706 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
707 if (MVT::isFloatingPoint(VT))
708 CV.push_back(ConstantFP::get(OpNTy,
709 cast<ConstantFPSDNode>(OpN)->getValue()));
711 CV.push_back(ConstantUInt::get(OpNTy,
712 cast<ConstantSDNode>(OpN)->getValue()));
714 Constant *CP = ConstantPacked::get(CV);
715 SDOperand CPIdx = DAG.getConstantPool(CP, Node->getValueType(0));
716 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
719 case ISD::TokenFactor:
720 if (Node->getNumOperands() == 2) {
721 bool Changed = false;
722 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
723 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
724 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
725 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
727 std::vector<SDOperand> Ops;
728 bool Changed = false;
729 // Legalize the operands.
730 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
731 SDOperand Op = Node->getOperand(i);
732 Ops.push_back(LegalizeOp(Op));
733 Changed |= Ops[i] != Op;
736 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
740 case ISD::CALLSEQ_START:
741 case ISD::CALLSEQ_END:
742 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
743 // Do not try to legalize the target-specific arguments (#1+)
744 Tmp2 = Node->getOperand(0);
746 Node->setAdjCallChain(Tmp1);
748 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
749 // nodes are treated specially and are mutated in place. This makes the dag
750 // legalization process more efficient and also makes libcall insertion
753 case ISD::DYNAMIC_STACKALLOC:
754 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
755 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
756 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
757 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
758 Tmp3 != Node->getOperand(2)) {
759 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
760 std::vector<SDOperand> Ops;
761 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
762 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
764 Result = Op.getValue(0);
766 // Since this op produces two values, make sure to remember that we
767 // legalized both of them.
768 AddLegalizedOperand(SDOperand(Node, 0), Result);
769 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
770 return Result.getValue(Op.ResNo);
774 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
775 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
777 bool Changed = false;
778 std::vector<SDOperand> Ops;
779 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
780 Ops.push_back(LegalizeOp(Node->getOperand(i)));
781 Changed |= Ops.back() != Node->getOperand(i);
784 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
785 std::vector<MVT::ValueType> RetTyVTs;
786 RetTyVTs.reserve(Node->getNumValues());
787 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
788 RetTyVTs.push_back(Node->getValueType(i));
789 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
790 Node->getOpcode() == ISD::TAILCALL), 0);
792 Result = Result.getValue(0);
794 // Since calls produce multiple values, make sure to remember that we
795 // legalized all of them.
796 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
797 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
798 return Result.getValue(Op.ResNo);
801 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
802 if (Tmp1 != Node->getOperand(0))
803 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
807 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
809 switch (getTypeAction(Node->getOperand(1).getValueType())) {
810 case Expand: assert(0 && "It's impossible to expand bools");
812 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
815 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
819 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
820 default: assert(0 && "This action is not supported yet!");
821 case TargetLowering::Expand:
822 // Expand brcond's setcc into its constituent parts and create a BR_CC
824 if (Tmp2.getOpcode() == ISD::SETCC) {
825 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
826 Tmp2.getOperand(0), Tmp2.getOperand(1),
827 Node->getOperand(2));
829 // Make sure the condition is either zero or one. It may have been
830 // promoted from something else.
831 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
833 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
834 DAG.getCondCode(ISD::SETNE), Tmp2,
835 DAG.getConstant(0, Tmp2.getValueType()),
836 Node->getOperand(2));
839 case TargetLowering::Legal:
840 // Basic block destination (Op#2) is always legal.
841 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
842 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
843 Node->getOperand(2));
848 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
850 if (isTypeLegal(Node->getOperand(2).getValueType())) {
851 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
852 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
853 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
854 Tmp3 != Node->getOperand(3)) {
855 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
856 Tmp2, Tmp3, Node->getOperand(4));
860 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
861 Node->getOperand(2), // LHS
862 Node->getOperand(3), // RHS
863 Node->getOperand(1)));
864 // If we get a SETCC back from legalizing the SETCC node we just
865 // created, then use its LHS, RHS, and CC directly in creating a new
866 // node. Otherwise, select between the true and false value based on
867 // comparing the result of the legalized with zero.
868 if (Tmp2.getOpcode() == ISD::SETCC) {
869 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
870 Tmp2.getOperand(0), Tmp2.getOperand(1),
871 Node->getOperand(4));
873 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
874 DAG.getCondCode(ISD::SETNE),
875 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
876 Node->getOperand(4));
880 case ISD::BRCONDTWOWAY:
881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
882 switch (getTypeAction(Node->getOperand(1).getValueType())) {
883 case Expand: assert(0 && "It's impossible to expand bools");
885 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
888 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
891 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
893 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
894 case TargetLowering::Promote:
895 default: assert(0 && "This action is not supported yet!");
896 case TargetLowering::Legal:
897 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
898 std::vector<SDOperand> Ops;
901 Ops.push_back(Node->getOperand(2));
902 Ops.push_back(Node->getOperand(3));
903 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
906 case TargetLowering::Expand:
907 // If BRTWOWAY_CC is legal for this target, then simply expand this node
908 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
910 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
911 if (Tmp2.getOpcode() == ISD::SETCC) {
912 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
913 Tmp2.getOperand(0), Tmp2.getOperand(1),
914 Node->getOperand(2), Node->getOperand(3));
916 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
917 DAG.getConstant(0, Tmp2.getValueType()),
918 Node->getOperand(2), Node->getOperand(3));
921 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
922 Node->getOperand(2));
923 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
928 case ISD::BRTWOWAY_CC:
929 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
930 if (isTypeLegal(Node->getOperand(2).getValueType())) {
931 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
932 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
933 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
934 Tmp3 != Node->getOperand(3)) {
935 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
936 Node->getOperand(4), Node->getOperand(5));
940 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
941 Node->getOperand(2), // LHS
942 Node->getOperand(3), // RHS
943 Node->getOperand(1)));
944 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
946 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
947 default: assert(0 && "This action is not supported yet!");
948 case TargetLowering::Legal:
949 // If we get a SETCC back from legalizing the SETCC node we just
950 // created, then use its LHS, RHS, and CC directly in creating a new
951 // node. Otherwise, select between the true and false value based on
952 // comparing the result of the legalized with zero.
953 if (Tmp2.getOpcode() == ISD::SETCC) {
954 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
955 Tmp2.getOperand(0), Tmp2.getOperand(1),
956 Node->getOperand(4), Node->getOperand(5));
958 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
959 DAG.getConstant(0, Tmp2.getValueType()),
960 Node->getOperand(4), Node->getOperand(5));
963 case TargetLowering::Expand:
964 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
965 Node->getOperand(4));
966 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
972 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
973 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
975 if (Tmp1 != Node->getOperand(0) ||
976 Tmp2 != Node->getOperand(1))
977 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
978 Node->getOperand(2));
980 Result = SDOperand(Node, 0);
982 // Since loads produce two values, make sure to remember that we legalized
984 AddLegalizedOperand(SDOperand(Node, 0), Result);
985 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
986 return Result.getValue(Op.ResNo);
990 case ISD::ZEXTLOAD: {
991 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
992 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
994 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
995 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
996 default: assert(0 && "This action is not supported yet!");
997 case TargetLowering::Promote:
998 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
999 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1000 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
1001 // Since loads produce two values, make sure to remember that we legalized
1003 AddLegalizedOperand(SDOperand(Node, 0), Result);
1004 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1005 return Result.getValue(Op.ResNo);
1007 case TargetLowering::Legal:
1008 if (Tmp1 != Node->getOperand(0) ||
1009 Tmp2 != Node->getOperand(1))
1010 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1011 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1013 Result = SDOperand(Node, 0);
1015 // Since loads produce two values, make sure to remember that we legalized
1017 AddLegalizedOperand(SDOperand(Node, 0), Result);
1018 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1019 return Result.getValue(Op.ResNo);
1020 case TargetLowering::Expand:
1021 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1022 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1023 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1024 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1026 return Load.getValue(1);
1029 assert(Node->getOpcode() != ISD::EXTLOAD &&
1030 "EXTLOAD should always be supported!");
1031 // Turn the unsupported load into an EXTLOAD followed by an explicit
1032 // zero/sign extend inreg.
1033 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1034 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1036 if (Node->getOpcode() == ISD::SEXTLOAD)
1037 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1038 Result, DAG.getValueType(SrcVT));
1040 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1041 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1042 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1044 return Result.getValue(1);
1047 assert(0 && "Unreachable");
1049 case ISD::EXTRACT_ELEMENT: {
1050 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1051 switch (getTypeAction(OpTy)) {
1053 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1056 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1058 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1059 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1060 TLI.getShiftAmountTy()));
1061 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1064 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1065 Node->getOperand(0));
1067 Result = LegalizeOp(Result);
1070 // Get both the low and high parts.
1071 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1072 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1073 Result = Tmp2; // 1 -> Hi
1075 Result = Tmp1; // 0 -> Lo
1081 case ISD::CopyToReg:
1082 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1084 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1085 "Register type must be legal!");
1086 // Legalize the incoming value (must be legal).
1087 Tmp2 = LegalizeOp(Node->getOperand(2));
1088 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1089 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1090 Node->getOperand(1), Tmp2);
1094 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1095 switch (Node->getNumOperands()) {
1097 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1099 Tmp2 = LegalizeOp(Node->getOperand(1));
1100 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1101 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1105 ExpandOp(Node->getOperand(1), Lo, Hi);
1106 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1110 Tmp2 = PromoteOp(Node->getOperand(1));
1111 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1116 if (Tmp1 != Node->getOperand(0))
1117 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1119 default: { // ret <values>
1120 std::vector<SDOperand> NewValues;
1121 NewValues.push_back(Tmp1);
1122 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1123 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1125 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1129 ExpandOp(Node->getOperand(i), Lo, Hi);
1130 NewValues.push_back(Lo);
1131 NewValues.push_back(Hi);
1135 assert(0 && "Can't promote multiple return value yet!");
1137 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1143 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1144 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1146 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1147 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1148 if (CFP->getValueType(0) == MVT::f32) {
1149 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1150 DAG.getConstant(FloatToBits(CFP->getValue()),
1153 Node->getOperand(3));
1155 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1156 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1157 DAG.getConstant(DoubleToBits(CFP->getValue()),
1160 Node->getOperand(3));
1165 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1167 SDOperand Val = LegalizeOp(Node->getOperand(1));
1168 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1169 Tmp2 != Node->getOperand(2))
1170 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1171 Node->getOperand(3));
1175 // Truncate the value and store the result.
1176 Tmp3 = PromoteOp(Node->getOperand(1));
1177 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1178 Node->getOperand(3),
1179 DAG.getValueType(Node->getOperand(1).getValueType()));
1184 unsigned IncrementSize;
1185 ExpandOp(Node->getOperand(1), Lo, Hi);
1187 if (!TLI.isLittleEndian())
1190 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1191 Node->getOperand(3));
1192 // If this is a vector type, then we have to calculate the increment as
1193 // the product of the element size in bytes, and the number of elements
1194 // in the high half of the vector.
1195 if (MVT::Vector == Hi.getValueType()) {
1196 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1197 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1198 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1200 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1202 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1203 getIntPtrConstant(IncrementSize));
1204 assert(isTypeLegal(Tmp2.getValueType()) &&
1205 "Pointers must be legal!");
1206 //Again, claiming both parts of the store came form the same Instr
1207 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1208 Node->getOperand(3));
1209 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1214 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1215 if (Tmp1 != Node->getOperand(0))
1216 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1218 case ISD::READCYCLECOUNTER:
1219 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1220 if (Tmp1 != Node->getOperand(0)) {
1221 std::vector<MVT::ValueType> rtypes;
1222 std::vector<SDOperand> rvals;
1223 rtypes.push_back(MVT::i64);
1224 rtypes.push_back(MVT::Other);
1225 rvals.push_back(Tmp1);
1226 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
1229 // Since rdcc produce two values, make sure to remember that we legalized
1231 AddLegalizedOperand(SDOperand(Node, 0), Result);
1232 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1233 return Result.getValue(Op.ResNo);
1236 case ISD::TRUNCSTORE:
1237 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1238 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1240 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1242 Tmp2 = LegalizeOp(Node->getOperand(1));
1244 // The only promote case we handle is TRUNCSTORE:i1 X into
1245 // -> TRUNCSTORE:i8 (and X, 1)
1246 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1247 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1248 TargetLowering::Promote) {
1249 // Promote the bool to a mask then store.
1250 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1251 DAG.getConstant(1, Tmp2.getValueType()));
1252 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1253 Node->getOperand(3), DAG.getValueType(MVT::i8));
1255 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1256 Tmp3 != Node->getOperand(2)) {
1257 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1258 Node->getOperand(3), Node->getOperand(4));
1263 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1267 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1268 case Expand: assert(0 && "It's impossible to expand bools");
1270 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1273 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1276 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1277 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1279 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1280 default: assert(0 && "This action is not supported yet!");
1281 case TargetLowering::Expand:
1282 if (Tmp1.getOpcode() == ISD::SETCC) {
1283 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1285 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1287 // Make sure the condition is either zero or one. It may have been
1288 // promoted from something else.
1289 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1290 Result = DAG.getSelectCC(Tmp1,
1291 DAG.getConstant(0, Tmp1.getValueType()),
1292 Tmp2, Tmp3, ISD::SETNE);
1295 case TargetLowering::Legal:
1296 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1297 Tmp3 != Node->getOperand(2))
1298 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1301 case TargetLowering::Promote: {
1302 MVT::ValueType NVT =
1303 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1304 unsigned ExtOp, TruncOp;
1305 if (MVT::isInteger(Tmp2.getValueType())) {
1306 ExtOp = ISD::ANY_EXTEND;
1307 TruncOp = ISD::TRUNCATE;
1309 ExtOp = ISD::FP_EXTEND;
1310 TruncOp = ISD::FP_ROUND;
1312 // Promote each of the values to the new type.
1313 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1314 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1315 // Perform the larger operation, then round down.
1316 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1317 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1322 case ISD::SELECT_CC:
1323 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1324 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1326 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1327 // Everything is legal, see if we should expand this op or something.
1328 switch (TLI.getOperationAction(ISD::SELECT_CC,
1329 Node->getOperand(0).getValueType())) {
1330 default: assert(0 && "This action is not supported yet!");
1331 case TargetLowering::Custom: {
1333 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1334 Node->getOperand(0),
1335 Node->getOperand(1), Tmp3, Tmp4,
1336 Node->getOperand(4)), DAG);
1338 Result = LegalizeOp(Tmp);
1341 } // FALLTHROUGH if the target can't lower this operation after all.
1342 case TargetLowering::Legal:
1343 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1344 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1345 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1346 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1347 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2,
1348 Tmp3, Tmp4, Node->getOperand(4));
1354 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1355 Node->getOperand(0), // LHS
1356 Node->getOperand(1), // RHS
1357 Node->getOperand(4)));
1358 // If we get a SETCC back from legalizing the SETCC node we just
1359 // created, then use its LHS, RHS, and CC directly in creating a new
1360 // node. Otherwise, select between the true and false value based on
1361 // comparing the result of the legalized with zero.
1362 if (Tmp1.getOpcode() == ISD::SETCC) {
1363 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1364 Tmp1.getOperand(0), Tmp1.getOperand(1),
1365 Tmp3, Tmp4, Tmp1.getOperand(2));
1367 Result = DAG.getSelectCC(Tmp1,
1368 DAG.getConstant(0, Tmp1.getValueType()),
1369 Tmp3, Tmp4, ISD::SETNE);
1374 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1376 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1377 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1380 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1381 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1383 // If this is an FP compare, the operands have already been extended.
1384 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1385 MVT::ValueType VT = Node->getOperand(0).getValueType();
1386 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1388 // Otherwise, we have to insert explicit sign or zero extends. Note
1389 // that we could insert sign extends for ALL conditions, but zero extend
1390 // is cheaper on many machines (an AND instead of two shifts), so prefer
1392 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1393 default: assert(0 && "Unknown integer comparison!");
1400 // ALL of these operations will work if we either sign or zero extend
1401 // the operands (including the unsigned comparisons!). Zero extend is
1402 // usually a simpler/cheaper operation, so prefer it.
1403 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1404 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1410 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1411 DAG.getValueType(VT));
1412 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1413 DAG.getValueType(VT));
1419 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1420 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1421 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1422 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1426 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1427 if (RHSCST->isAllOnesValue()) {
1428 // Comparison to -1.
1429 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1434 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1435 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1436 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1437 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1440 // If this is a comparison of the sign bit, just look at the top part.
1442 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1443 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1444 CST->getValue() == 0) || // X < 0
1445 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1446 (CST->isAllOnesValue()))) { // X > -1
1452 // FIXME: This generated code sucks.
1453 ISD::CondCode LowCC;
1454 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1455 default: assert(0 && "Unknown integer setcc!");
1457 case ISD::SETULT: LowCC = ISD::SETULT; break;
1459 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1461 case ISD::SETULE: LowCC = ISD::SETULE; break;
1463 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1466 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1467 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1468 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1470 // NOTE: on targets without efficient SELECT of bools, we can always use
1471 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1472 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1473 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1474 Node->getOperand(2));
1475 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1476 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1477 Result, Tmp1, Tmp2));
1482 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) {
1484 assert(0 && "Cannot handle this action for SETCC yet!");
1486 case TargetLowering::Promote: {
1487 // First step, figure out the appropriate operation to use.
1488 // Allow SETCC to not be supported for all legal data types
1489 // Mostly this targets FP
1490 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1491 MVT::ValueType OldVT = NewInTy;
1493 // Scan for the appropriate larger type to use.
1495 NewInTy = (MVT::ValueType)(NewInTy+1);
1497 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1498 "Fell off of the edge of the integer world");
1499 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1500 "Fell off of the edge of the floating point world");
1502 // If the target supports SETCC of this type, use it.
1503 if (TLI.getOperationAction(ISD::SETCC, NewInTy) == TargetLowering::Legal)
1506 if (MVT::isInteger(NewInTy))
1507 assert(0 && "Cannot promote Legal Integer SETCC yet");
1509 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1510 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1513 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1514 Node->getOperand(2));
1517 case TargetLowering::Legal:
1518 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1519 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1520 Node->getOperand(2));
1522 case TargetLowering::Expand:
1523 // Expand a setcc node into a select_cc of the same condition, lhs, and
1524 // rhs that selects between const 1 (true) and const 0 (false).
1525 MVT::ValueType VT = Node->getValueType(0);
1526 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1527 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1528 Node->getOperand(2));
1529 Result = LegalizeOp(Result);
1536 case ISD::MEMMOVE: {
1537 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1538 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1540 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1541 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1542 case Expand: assert(0 && "Cannot expand a byte!");
1544 Tmp3 = LegalizeOp(Node->getOperand(2));
1547 Tmp3 = PromoteOp(Node->getOperand(2));
1551 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1555 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1557 // Length is too big, just take the lo-part of the length.
1559 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1563 Tmp4 = LegalizeOp(Node->getOperand(3));
1566 Tmp4 = PromoteOp(Node->getOperand(3));
1571 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1572 case Expand: assert(0 && "Cannot expand this yet!");
1574 Tmp5 = LegalizeOp(Node->getOperand(4));
1577 Tmp5 = PromoteOp(Node->getOperand(4));
1581 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1582 default: assert(0 && "This action not implemented for this operation!");
1583 case TargetLowering::Custom: {
1585 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1586 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1588 Result = LegalizeOp(Tmp);
1591 // FALLTHROUGH if the target thinks it is legal.
1593 case TargetLowering::Legal:
1594 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1595 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1596 Tmp5 != Node->getOperand(4)) {
1597 std::vector<SDOperand> Ops;
1598 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1599 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1600 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1603 case TargetLowering::Expand: {
1604 // Otherwise, the target does not support this operation. Lower the
1605 // operation to an explicit libcall as appropriate.
1606 MVT::ValueType IntPtr = TLI.getPointerTy();
1607 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1608 std::vector<std::pair<SDOperand, const Type*> > Args;
1610 const char *FnName = 0;
1611 if (Node->getOpcode() == ISD::MEMSET) {
1612 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1613 // Extend the ubyte argument to be an int value for the call.
1614 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1615 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1616 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1619 } else if (Node->getOpcode() == ISD::MEMCPY ||
1620 Node->getOpcode() == ISD::MEMMOVE) {
1621 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1622 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1623 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1624 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1626 assert(0 && "Unknown op!");
1629 std::pair<SDOperand,SDOperand> CallResult =
1630 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1631 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1632 Result = CallResult.second;
1633 NeedsAnotherIteration = true;
1641 Tmp1 = LegalizeOp(Node->getOperand(0));
1642 Tmp2 = LegalizeOp(Node->getOperand(1));
1644 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1645 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1646 std::vector<SDOperand> Ops;
1647 Ops.push_back(Tmp1);
1648 Ops.push_back(Tmp2);
1649 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1651 Result = SDOperand(Node, 0);
1652 // Since these produce two values, make sure to remember that we legalized
1654 AddLegalizedOperand(SDOperand(Node, 0), Result);
1655 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1656 return Result.getValue(Op.ResNo);
1657 case ISD::WRITEPORT:
1658 Tmp1 = LegalizeOp(Node->getOperand(0));
1659 Tmp2 = LegalizeOp(Node->getOperand(1));
1660 Tmp3 = LegalizeOp(Node->getOperand(2));
1661 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1662 Tmp3 != Node->getOperand(2))
1663 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1667 Tmp1 = LegalizeOp(Node->getOperand(0));
1668 Tmp2 = LegalizeOp(Node->getOperand(1));
1670 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1671 case TargetLowering::Custom:
1672 default: assert(0 && "This action not implemented for this operation!");
1673 case TargetLowering::Legal:
1674 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1675 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1676 std::vector<SDOperand> Ops;
1677 Ops.push_back(Tmp1);
1678 Ops.push_back(Tmp2);
1679 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1681 Result = SDOperand(Node, 0);
1683 case TargetLowering::Expand:
1684 // Replace this with a load from memory.
1685 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1686 Node->getOperand(1), DAG.getSrcValue(NULL));
1687 Result = LegalizeOp(Result);
1691 // Since these produce two values, make sure to remember that we legalized
1693 AddLegalizedOperand(SDOperand(Node, 0), Result);
1694 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1695 return Result.getValue(Op.ResNo);
1698 Tmp1 = LegalizeOp(Node->getOperand(0));
1699 Tmp2 = LegalizeOp(Node->getOperand(1));
1700 Tmp3 = LegalizeOp(Node->getOperand(2));
1702 switch (TLI.getOperationAction(Node->getOpcode(),
1703 Node->getOperand(1).getValueType())) {
1704 case TargetLowering::Custom:
1705 default: assert(0 && "This action not implemented for this operation!");
1706 case TargetLowering::Legal:
1707 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1708 Tmp3 != Node->getOperand(2))
1709 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1711 case TargetLowering::Expand:
1712 // Replace this with a store to memory.
1713 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1714 Node->getOperand(1), Node->getOperand(2),
1715 DAG.getSrcValue(NULL));
1716 Result = LegalizeOp(Result);
1721 case ISD::ADD_PARTS:
1722 case ISD::SUB_PARTS:
1723 case ISD::SHL_PARTS:
1724 case ISD::SRA_PARTS:
1725 case ISD::SRL_PARTS: {
1726 std::vector<SDOperand> Ops;
1727 bool Changed = false;
1728 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1729 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1730 Changed |= Ops.back() != Node->getOperand(i);
1733 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1734 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1737 // Since these produce multiple values, make sure to remember that we
1738 // legalized all of them.
1739 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1740 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1741 return Result.getValue(Op.ResNo);
1762 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1763 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1764 case Expand: assert(0 && "Not possible");
1766 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1769 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1772 if (Tmp1 != Node->getOperand(0) ||
1773 Tmp2 != Node->getOperand(1))
1774 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1777 case ISD::BUILD_PAIR: {
1778 MVT::ValueType PairTy = Node->getValueType(0);
1779 // TODO: handle the case where the Lo and Hi operands are not of legal type
1780 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1781 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1782 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1783 case TargetLowering::Legal:
1784 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1785 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1787 case TargetLowering::Promote:
1788 case TargetLowering::Custom:
1789 assert(0 && "Cannot promote/custom this yet!");
1790 case TargetLowering::Expand:
1791 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
1792 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
1793 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
1794 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
1795 TLI.getShiftAmountTy()));
1796 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
1805 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1806 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1807 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1808 case TargetLowering::Legal:
1809 if (Tmp1 != Node->getOperand(0) ||
1810 Tmp2 != Node->getOperand(1))
1811 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1814 case TargetLowering::Promote:
1815 case TargetLowering::Custom:
1816 assert(0 && "Cannot promote/custom handle this yet!");
1817 case TargetLowering::Expand:
1818 if (MVT::isInteger(Node->getValueType(0))) {
1819 MVT::ValueType VT = Node->getValueType(0);
1820 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1821 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1822 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1823 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1825 // Floating point mod -> fmod libcall.
1826 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1828 Result = ExpandLibCall(FnName, Node, Dummy);
1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1839 case TargetLowering::Legal:
1840 if (Tmp1 != Node->getOperand(0))
1841 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1843 case TargetLowering::Promote: {
1844 MVT::ValueType OVT = Tmp1.getValueType();
1845 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1847 // Zero extend the argument.
1848 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1849 // Perform the larger operation, then subtract if needed.
1850 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1851 switch(Node->getOpcode())
1857 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1858 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
1859 DAG.getConstant(getSizeInBits(NVT), NVT),
1861 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1862 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1865 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1866 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1867 DAG.getConstant(getSizeInBits(NVT) -
1868 getSizeInBits(OVT), NVT));
1873 case TargetLowering::Custom:
1874 assert(0 && "Cannot custom handle this yet!");
1875 case TargetLowering::Expand:
1876 switch(Node->getOpcode())
1879 static const uint64_t mask[6] = {
1880 0x5555555555555555ULL, 0x3333333333333333ULL,
1881 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1882 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
1884 MVT::ValueType VT = Tmp1.getValueType();
1885 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1886 unsigned len = getSizeInBits(VT);
1887 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1888 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
1889 Tmp2 = DAG.getConstant(mask[i], VT);
1890 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1891 Tmp1 = DAG.getNode(ISD::ADD, VT,
1892 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
1893 DAG.getNode(ISD::AND, VT,
1894 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
1901 /* for now, we do this:
1906 x = x | (x >>32); // for 64-bit input
1907 return popcount(~x);
1909 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
1910 MVT::ValueType VT = Tmp1.getValueType();
1911 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1912 unsigned len = getSizeInBits(VT);
1913 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1914 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1915 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
1916 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
1918 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
1919 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1923 // for now, we use: { return popcount(~x & (x - 1)); }
1924 // unless the target has ctlz but not ctpop, in which case we use:
1925 // { return 32 - nlz(~x & (x-1)); }
1926 // see also http://www.hackersdelight.org/HDcode/ntz.cc
1927 MVT::ValueType VT = Tmp1.getValueType();
1928 Tmp2 = DAG.getConstant(~0ULL, VT);
1929 Tmp3 = DAG.getNode(ISD::AND, VT,
1930 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
1931 DAG.getNode(ISD::SUB, VT, Tmp1,
1932 DAG.getConstant(1, VT)));
1933 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
1934 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
1935 TLI.isOperationLegal(ISD::CTLZ, VT)) {
1936 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
1937 DAG.getConstant(getSizeInBits(VT), VT),
1938 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
1940 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1945 assert(0 && "Cannot expand this yet!");
1958 Tmp1 = LegalizeOp(Node->getOperand(0));
1959 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1960 case TargetLowering::Legal:
1961 if (Tmp1 != Node->getOperand(0))
1962 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1964 case TargetLowering::Promote:
1965 case TargetLowering::Custom:
1966 assert(0 && "Cannot promote/custom handle this yet!");
1967 case TargetLowering::Expand:
1968 switch(Node->getOpcode()) {
1970 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1971 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1972 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
1977 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1978 MVT::ValueType VT = Node->getValueType(0);
1979 Tmp2 = DAG.getConstantFP(0.0, VT);
1980 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
1981 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1982 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1983 Result = LegalizeOp(Result);
1989 MVT::ValueType VT = Node->getValueType(0);
1990 const char *FnName = 0;
1991 switch(Node->getOpcode()) {
1992 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1993 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1994 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1995 default: assert(0 && "Unreachable!");
1998 Result = ExpandLibCall(FnName, Node, Dummy);
2002 assert(0 && "Unreachable!");
2008 // Conversion operators. The source and destination have different types.
2009 case ISD::SINT_TO_FP:
2010 case ISD::UINT_TO_FP: {
2011 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2012 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2014 switch (TLI.getOperationAction(Node->getOpcode(),
2015 Node->getOperand(0).getValueType())) {
2016 default: assert(0 && "Unknown operation action!");
2017 case TargetLowering::Expand:
2018 Result = ExpandLegalINT_TO_FP(isSigned,
2019 LegalizeOp(Node->getOperand(0)),
2020 Node->getValueType(0));
2021 AddLegalizedOperand(Op, Result);
2023 case TargetLowering::Promote:
2024 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2025 Node->getValueType(0),
2027 AddLegalizedOperand(Op, Result);
2029 case TargetLowering::Legal:
2031 case TargetLowering::Custom: {
2032 Tmp1 = LegalizeOp(Node->getOperand(0));
2034 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2035 Tmp = TLI.LowerOperation(Tmp, DAG);
2037 AddLegalizedOperand(Op, Tmp);
2038 NeedsAnotherIteration = true;
2041 assert(0 && "Target Must Lower this");
2046 Tmp1 = LegalizeOp(Node->getOperand(0));
2047 if (Tmp1 != Node->getOperand(0))
2048 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2051 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2052 Node->getValueType(0), Node->getOperand(0));
2056 Result = PromoteOp(Node->getOperand(0));
2057 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2058 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
2059 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
2061 Result = PromoteOp(Node->getOperand(0));
2062 Result = DAG.getZeroExtendInReg(Result,
2063 Node->getOperand(0).getValueType());
2064 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
2071 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2073 Tmp1 = LegalizeOp(Node->getOperand(0));
2074 if (Tmp1 != Node->getOperand(0))
2075 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2078 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2080 // Since the result is legal, we should just be able to truncate the low
2081 // part of the source.
2082 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2085 Result = PromoteOp(Node->getOperand(0));
2086 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2091 case ISD::FP_TO_SINT:
2092 case ISD::FP_TO_UINT:
2093 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2095 Tmp1 = LegalizeOp(Node->getOperand(0));
2097 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2098 default: assert(0 && "Unknown operation action!");
2099 case TargetLowering::Expand:
2100 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2101 SDOperand True, False;
2102 MVT::ValueType VT = Node->getOperand(0).getValueType();
2103 MVT::ValueType NVT = Node->getValueType(0);
2104 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2105 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2106 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2107 Node->getOperand(0), Tmp2, ISD::SETLT);
2108 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2109 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2110 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2112 False = DAG.getNode(ISD::XOR, NVT, False,
2113 DAG.getConstant(1ULL << ShiftAmt, NVT));
2114 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2117 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2120 case TargetLowering::Promote:
2121 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2122 Node->getOpcode() == ISD::FP_TO_SINT);
2123 AddLegalizedOperand(Op, Result);
2125 case TargetLowering::Custom: {
2127 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2128 Tmp = TLI.LowerOperation(Tmp, DAG);
2130 AddLegalizedOperand(Op, Tmp);
2131 NeedsAnotherIteration = true;
2134 // The target thinks this is legal afterall.
2138 case TargetLowering::Legal:
2142 if (Tmp1 != Node->getOperand(0))
2143 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2146 assert(0 && "Shouldn't need to expand other operators here!");
2148 Result = PromoteOp(Node->getOperand(0));
2149 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2154 case ISD::ANY_EXTEND:
2155 case ISD::ZERO_EXTEND:
2156 case ISD::SIGN_EXTEND:
2157 case ISD::FP_EXTEND:
2159 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2161 Tmp1 = LegalizeOp(Node->getOperand(0));
2162 if (Tmp1 != Node->getOperand(0))
2163 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2166 assert(0 && "Shouldn't need to expand other operators here!");
2169 switch (Node->getOpcode()) {
2170 case ISD::ANY_EXTEND:
2171 Result = PromoteOp(Node->getOperand(0));
2172 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2174 case ISD::ZERO_EXTEND:
2175 Result = PromoteOp(Node->getOperand(0));
2176 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2177 Result = DAG.getZeroExtendInReg(Result,
2178 Node->getOperand(0).getValueType());
2180 case ISD::SIGN_EXTEND:
2181 Result = PromoteOp(Node->getOperand(0));
2182 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2183 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2185 DAG.getValueType(Node->getOperand(0).getValueType()));
2187 case ISD::FP_EXTEND:
2188 Result = PromoteOp(Node->getOperand(0));
2189 if (Result.getValueType() != Op.getValueType())
2190 // Dynamically dead while we have only 2 FP types.
2191 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2194 Result = PromoteOp(Node->getOperand(0));
2195 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2200 case ISD::FP_ROUND_INREG:
2201 case ISD::SIGN_EXTEND_INREG: {
2202 Tmp1 = LegalizeOp(Node->getOperand(0));
2203 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2205 // If this operation is not supported, convert it to a shl/shr or load/store
2207 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2208 default: assert(0 && "This action not supported for this op yet!");
2209 case TargetLowering::Legal:
2210 if (Tmp1 != Node->getOperand(0))
2211 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2212 DAG.getValueType(ExtraVT));
2214 case TargetLowering::Expand:
2215 // If this is an integer extend and shifts are supported, do that.
2216 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2217 // NOTE: we could fall back on load/store here too for targets without
2218 // SAR. However, it is doubtful that any exist.
2219 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2220 MVT::getSizeInBits(ExtraVT);
2221 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2222 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2223 Node->getOperand(0), ShiftCst);
2224 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2226 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2227 // The only way we can lower this is to turn it into a STORETRUNC,
2228 // EXTLOAD pair, targetting a temporary location (a stack slot).
2230 // NOTE: there is a choice here between constantly creating new stack
2231 // slots and always reusing the same one. We currently always create
2232 // new ones, as reuse may inhibit scheduling.
2233 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2234 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2235 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2236 MachineFunction &MF = DAG.getMachineFunction();
2238 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2239 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2240 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2241 Node->getOperand(0), StackSlot,
2242 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2243 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2244 Result, StackSlot, DAG.getSrcValue(NULL),
2247 assert(0 && "Unknown op");
2249 Result = LegalizeOp(Result);
2256 // Note that LegalizeOp may be reentered even from single-use nodes, which
2257 // means that we always must cache transformed nodes.
2258 AddLegalizedOperand(Op, Result);
2262 /// PromoteOp - Given an operation that produces a value in an invalid type,
2263 /// promote it to compute the value into a larger type. The produced value will
2264 /// have the correct bits for the low portion of the register, but no guarantee
2265 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2266 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2267 MVT::ValueType VT = Op.getValueType();
2268 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2269 assert(getTypeAction(VT) == Promote &&
2270 "Caller should expand or legalize operands that are not promotable!");
2271 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2272 "Cannot promote to smaller type!");
2274 SDOperand Tmp1, Tmp2, Tmp3;
2277 SDNode *Node = Op.Val;
2279 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2280 if (I != PromotedNodes.end()) return I->second;
2282 // Promotion needs an optimization step to clean up after it, and is not
2283 // careful to avoid operations the target does not support. Make sure that
2284 // all generated operations are legalized in the next iteration.
2285 NeedsAnotherIteration = true;
2287 switch (Node->getOpcode()) {
2288 case ISD::CopyFromReg:
2289 assert(0 && "CopyFromReg must be legal!");
2291 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2292 assert(0 && "Do not know how to promote this operator!");
2295 Result = DAG.getNode(ISD::UNDEF, NVT);
2299 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2301 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2302 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2304 case ISD::ConstantFP:
2305 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2306 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2310 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2311 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2312 Node->getOperand(1), Node->getOperand(2));
2313 Result = LegalizeOp(Result);
2317 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2319 Result = LegalizeOp(Node->getOperand(0));
2320 assert(Result.getValueType() >= NVT &&
2321 "This truncation doesn't make sense!");
2322 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2323 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2326 // The truncation is not required, because we don't guarantee anything
2327 // about high bits anyway.
2328 Result = PromoteOp(Node->getOperand(0));
2331 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2332 // Truncate the low part of the expanded value to the result type
2333 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2336 case ISD::SIGN_EXTEND:
2337 case ISD::ZERO_EXTEND:
2338 case ISD::ANY_EXTEND:
2339 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2340 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2342 // Input is legal? Just do extend all the way to the larger type.
2343 Result = LegalizeOp(Node->getOperand(0));
2344 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2347 // Promote the reg if it's smaller.
2348 Result = PromoteOp(Node->getOperand(0));
2349 // The high bits are not guaranteed to be anything. Insert an extend.
2350 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2351 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2352 DAG.getValueType(Node->getOperand(0).getValueType()));
2353 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2354 Result = DAG.getZeroExtendInReg(Result,
2355 Node->getOperand(0).getValueType());
2360 case ISD::FP_EXTEND:
2361 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2363 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2364 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2365 case Promote: assert(0 && "Unreachable with 2 FP types!");
2367 // Input is legal? Do an FP_ROUND_INREG.
2368 Result = LegalizeOp(Node->getOperand(0));
2369 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2370 DAG.getValueType(VT));
2375 case ISD::SINT_TO_FP:
2376 case ISD::UINT_TO_FP:
2377 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2379 Result = LegalizeOp(Node->getOperand(0));
2380 // No extra round required here.
2381 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2385 Result = PromoteOp(Node->getOperand(0));
2386 if (Node->getOpcode() == ISD::SINT_TO_FP)
2387 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2389 DAG.getValueType(Node->getOperand(0).getValueType()));
2391 Result = DAG.getZeroExtendInReg(Result,
2392 Node->getOperand(0).getValueType());
2393 // No extra round required here.
2394 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2397 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2398 Node->getOperand(0));
2399 // Round if we cannot tolerate excess precision.
2400 if (NoExcessFPPrecision)
2401 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2402 DAG.getValueType(VT));
2407 case ISD::SIGN_EXTEND_INREG:
2408 Result = PromoteOp(Node->getOperand(0));
2409 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2410 Node->getOperand(1));
2412 case ISD::FP_TO_SINT:
2413 case ISD::FP_TO_UINT:
2414 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2416 Tmp1 = LegalizeOp(Node->getOperand(0));
2419 // The input result is prerounded, so we don't have to do anything
2421 Tmp1 = PromoteOp(Node->getOperand(0));
2424 assert(0 && "not implemented");
2426 // If we're promoting a UINT to a larger size, check to see if the new node
2427 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2428 // we can use that instead. This allows us to generate better code for
2429 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2430 // legal, such as PowerPC.
2431 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2432 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2433 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2434 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2435 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2437 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2443 Tmp1 = PromoteOp(Node->getOperand(0));
2444 assert(Tmp1.getValueType() == NVT);
2445 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2446 // NOTE: we do not have to do any extra rounding here for
2447 // NoExcessFPPrecision, because we know the input will have the appropriate
2448 // precision, and these operations don't modify precision at all.
2454 Tmp1 = PromoteOp(Node->getOperand(0));
2455 assert(Tmp1.getValueType() == NVT);
2456 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2457 if(NoExcessFPPrecision)
2458 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2459 DAG.getValueType(VT));
2468 // The input may have strange things in the top bits of the registers, but
2469 // these operations don't care. They may have weird bits going out, but
2470 // that too is okay if they are integer operations.
2471 Tmp1 = PromoteOp(Node->getOperand(0));
2472 Tmp2 = PromoteOp(Node->getOperand(1));
2473 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2474 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2479 // The input may have strange things in the top bits of the registers, but
2480 // these operations don't care.
2481 Tmp1 = PromoteOp(Node->getOperand(0));
2482 Tmp2 = PromoteOp(Node->getOperand(1));
2483 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2484 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2486 // Floating point operations will give excess precision that we may not be
2487 // able to tolerate. If we DO allow excess precision, just leave it,
2488 // otherwise excise it.
2489 // FIXME: Why would we need to round FP ops more than integer ones?
2490 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2491 if (NoExcessFPPrecision)
2492 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2493 DAG.getValueType(VT));
2498 // These operators require that their input be sign extended.
2499 Tmp1 = PromoteOp(Node->getOperand(0));
2500 Tmp2 = PromoteOp(Node->getOperand(1));
2501 if (MVT::isInteger(NVT)) {
2502 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2503 DAG.getValueType(VT));
2504 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2505 DAG.getValueType(VT));
2507 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2509 // Perform FP_ROUND: this is probably overly pessimistic.
2510 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2511 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2512 DAG.getValueType(VT));
2516 // These operators require that their input be fp extended.
2517 Tmp1 = PromoteOp(Node->getOperand(0));
2518 Tmp2 = PromoteOp(Node->getOperand(1));
2519 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2521 // Perform FP_ROUND: this is probably overly pessimistic.
2522 if (NoExcessFPPrecision)
2523 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2524 DAG.getValueType(VT));
2529 // These operators require that their input be zero extended.
2530 Tmp1 = PromoteOp(Node->getOperand(0));
2531 Tmp2 = PromoteOp(Node->getOperand(1));
2532 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2533 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2534 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2535 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2539 Tmp1 = PromoteOp(Node->getOperand(0));
2540 Tmp2 = LegalizeOp(Node->getOperand(1));
2541 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2544 // The input value must be properly sign extended.
2545 Tmp1 = PromoteOp(Node->getOperand(0));
2546 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2547 DAG.getValueType(VT));
2548 Tmp2 = LegalizeOp(Node->getOperand(1));
2549 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2552 // The input value must be properly zero extended.
2553 Tmp1 = PromoteOp(Node->getOperand(0));
2554 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2555 Tmp2 = LegalizeOp(Node->getOperand(1));
2556 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2559 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2560 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2561 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2562 Node->getOperand(2), VT);
2563 // Remember that we legalized the chain.
2564 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2569 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2570 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2571 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2572 Node->getOperand(2),
2573 cast<VTSDNode>(Node->getOperand(3))->getVT());
2574 // Remember that we legalized the chain.
2575 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2578 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2579 case Expand: assert(0 && "It's impossible to expand bools");
2581 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2584 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2587 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2588 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2589 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2591 case ISD::SELECT_CC:
2592 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2593 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2594 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2595 Node->getOperand(1), Tmp2, Tmp3,
2596 Node->getOperand(4));
2600 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2601 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2603 std::vector<SDOperand> Ops;
2604 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2605 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2607 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2608 "Can only promote single result calls");
2609 std::vector<MVT::ValueType> RetTyVTs;
2610 RetTyVTs.reserve(2);
2611 RetTyVTs.push_back(NVT);
2612 RetTyVTs.push_back(MVT::Other);
2613 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2614 Node->getOpcode() == ISD::TAILCALL);
2615 Result = SDOperand(NC, 0);
2617 // Insert the new chain mapping.
2618 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2624 Tmp1 = Node->getOperand(0);
2625 //Zero extend the argument
2626 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2627 // Perform the larger operation, then subtract if needed.
2628 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2629 switch(Node->getOpcode())
2635 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2636 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2637 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2638 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2639 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2642 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2643 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2644 DAG.getConstant(getSizeInBits(NVT) -
2645 getSizeInBits(VT), NVT));
2651 assert(Result.Val && "Didn't set a result!");
2652 AddPromotedOperand(Op, Result);
2656 /// ExpandAddSub - Find a clever way to expand this add operation into
2658 void SelectionDAGLegalize::
2659 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2660 SDOperand &Lo, SDOperand &Hi) {
2661 // Expand the subcomponents.
2662 SDOperand LHSL, LHSH, RHSL, RHSH;
2663 ExpandOp(LHS, LHSL, LHSH);
2664 ExpandOp(RHS, RHSL, RHSH);
2666 std::vector<SDOperand> Ops;
2667 Ops.push_back(LHSL);
2668 Ops.push_back(LHSH);
2669 Ops.push_back(RHSL);
2670 Ops.push_back(RHSH);
2671 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2672 Lo = DAG.getNode(NodeOp, VTs, Ops);
2673 Hi = Lo.getValue(1);
2676 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2677 SDOperand Op, SDOperand Amt,
2678 SDOperand &Lo, SDOperand &Hi) {
2679 // Expand the subcomponents.
2680 SDOperand LHSL, LHSH;
2681 ExpandOp(Op, LHSL, LHSH);
2683 std::vector<SDOperand> Ops;
2684 Ops.push_back(LHSL);
2685 Ops.push_back(LHSH);
2687 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2688 Lo = DAG.getNode(NodeOp, VTs, Ops);
2689 Hi = Lo.getValue(1);
2693 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2694 /// smaller elements. If we can't find a way that is more efficient than a
2695 /// libcall on this target, return false. Otherwise, return true with the
2696 /// low-parts expanded into Lo and Hi.
2697 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2698 SDOperand &Lo, SDOperand &Hi) {
2699 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2700 "This is not a shift!");
2702 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2703 SDOperand ShAmt = LegalizeOp(Amt);
2704 MVT::ValueType ShTy = ShAmt.getValueType();
2705 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2706 unsigned NVTBits = MVT::getSizeInBits(NVT);
2708 // Handle the case when Amt is an immediate. Other cases are currently broken
2709 // and are disabled.
2710 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2711 unsigned Cst = CN->getValue();
2712 // Expand the incoming operand to be shifted, so that we have its parts
2714 ExpandOp(Op, InL, InH);
2718 Lo = DAG.getConstant(0, NVT);
2719 Hi = DAG.getConstant(0, NVT);
2720 } else if (Cst > NVTBits) {
2721 Lo = DAG.getConstant(0, NVT);
2722 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2723 } else if (Cst == NVTBits) {
2724 Lo = DAG.getConstant(0, NVT);
2727 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2728 Hi = DAG.getNode(ISD::OR, NVT,
2729 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2730 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2735 Lo = DAG.getConstant(0, NVT);
2736 Hi = DAG.getConstant(0, NVT);
2737 } else if (Cst > NVTBits) {
2738 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2739 Hi = DAG.getConstant(0, NVT);
2740 } else if (Cst == NVTBits) {
2742 Hi = DAG.getConstant(0, NVT);
2744 Lo = DAG.getNode(ISD::OR, NVT,
2745 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2746 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2747 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2752 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2753 DAG.getConstant(NVTBits-1, ShTy));
2754 } else if (Cst > NVTBits) {
2755 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2756 DAG.getConstant(Cst-NVTBits, ShTy));
2757 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2758 DAG.getConstant(NVTBits-1, ShTy));
2759 } else if (Cst == NVTBits) {
2761 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2762 DAG.getConstant(NVTBits-1, ShTy));
2764 Lo = DAG.getNode(ISD::OR, NVT,
2765 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2766 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2767 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2772 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2773 // so disable it for now. Currently targets are handling this via SHL_PARTS
2777 // If we have an efficient select operation (or if the selects will all fold
2778 // away), lower to some complex code, otherwise just emit the libcall.
2779 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
2783 ExpandOp(Op, InL, InH);
2784 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
2785 DAG.getConstant(NVTBits, ShTy), ShAmt);
2787 // Compare the unmasked shift amount against 32.
2788 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
2789 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
2791 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
2792 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
2793 DAG.getConstant(NVTBits-1, ShTy));
2794 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
2795 DAG.getConstant(NVTBits-1, ShTy));
2798 if (Opc == ISD::SHL) {
2799 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
2800 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
2801 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
2802 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
2804 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2805 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
2807 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
2808 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
2809 DAG.getConstant(32, ShTy),
2811 DAG.getConstant(0, NVT),
2812 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
2813 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
2815 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
2816 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
2819 if (Opc == ISD::SRA)
2820 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
2821 DAG.getConstant(NVTBits-1, ShTy));
2823 HiPart = DAG.getConstant(0, NVT);
2824 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2825 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
2830 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
2831 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
2833 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
2834 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
2836 // If we found an CALLSEQ_START, we already know this node occurs later
2837 // than the Found node. Just remember this node and return.
2838 if (Node->getOpcode() == ISD::CALLSEQ_START) {
2843 // Otherwise, scan the operands of Node to see if any of them is a call.
2844 assert(Node->getNumOperands() != 0 &&
2845 "All leaves should have depth equal to the entry node!");
2846 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
2847 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
2849 // Tail recurse for the last iteration.
2850 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
2855 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
2856 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
2858 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
2859 std::set<SDNode*> &Visited) {
2860 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
2861 !Visited.insert(Node).second) return;
2863 // If we found an CALLSEQ_END, we already know this node occurs earlier
2864 // than the Found node. Just remember this node and return.
2865 if (Node->getOpcode() == ISD::CALLSEQ_END) {
2870 // Otherwise, scan the operands of Node to see if any of them is a call.
2871 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
2872 if (UI == E) return;
2873 for (--E; UI != E; ++UI)
2874 FindEarliestCallSeqEnd(*UI, Found, Visited);
2876 // Tail recurse for the last iteration.
2877 FindEarliestCallSeqEnd(*UI, Found, Visited);
2880 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
2881 /// find the CALLSEQ_END node that terminates the call sequence.
2882 static SDNode *FindCallSeqEnd(SDNode *Node) {
2883 if (Node->getOpcode() == ISD::CALLSEQ_END)
2885 if (Node->use_empty())
2886 return 0; // No CallSeqEnd
2888 SDOperand TheChain(Node, Node->getNumValues()-1);
2889 if (TheChain.getValueType() != MVT::Other)
2890 TheChain = SDOperand(Node, 0);
2891 if (TheChain.getValueType() != MVT::Other)
2894 for (SDNode::use_iterator UI = Node->use_begin(),
2895 E = Node->use_end(); UI != E; ++UI) {
2897 // Make sure to only follow users of our token chain.
2899 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
2900 if (User->getOperand(i) == TheChain)
2901 if (SDNode *Result = FindCallSeqEnd(User))
2907 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
2908 /// find the CALLSEQ_START node that initiates the call sequence.
2909 static SDNode *FindCallSeqStart(SDNode *Node) {
2910 assert(Node && "Didn't find callseq_start for a call??");
2911 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
2913 assert(Node->getOperand(0).getValueType() == MVT::Other &&
2914 "Node doesn't have a token chain argument!");
2915 return FindCallSeqStart(Node->getOperand(0).Val);
2919 /// FindInputOutputChains - If we are replacing an operation with a call we need
2920 /// to find the call that occurs before and the call that occurs after it to
2921 /// properly serialize the calls in the block. The returned operand is the
2922 /// input chain value for the new call (e.g. the entry node or the previous
2923 /// call), and OutChain is set to be the chain node to update to point to the
2924 /// end of the call chain.
2925 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
2927 SDNode *LatestCallSeqStart = Entry.Val;
2928 SDNode *LatestCallSeqEnd = 0;
2929 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
2930 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
2932 // It is possible that no ISD::CALLSEQ_START was found because there is no
2933 // previous call in the function. LatestCallStackDown may in that case be
2934 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
2935 // unless LatestCallStackDown is an CALLSEQ_START.
2936 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
2937 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
2938 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
2940 LatestCallSeqEnd = Entry.Val;
2942 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
2944 // Finally, find the first call that this must come before, first we find the
2945 // CallSeqEnd that ends the call.
2947 std::set<SDNode*> Visited;
2948 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
2950 // If we found one, translate from the adj up to the callseq_start.
2952 OutChain = FindCallSeqStart(OutChain);
2954 return SDOperand(LatestCallSeqEnd, 0);
2957 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
2958 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
2960 // Nothing to splice it into?
2961 if (OutChain == 0) return;
2963 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
2966 // Form a token factor node merging the old inval and the new inval.
2967 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
2968 OutChain->getOperand(0));
2969 // Change the node to refer to the new token.
2970 OutChain->setAdjCallChain(InToken);
2974 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2975 // does not fit into a register, return the lo part and set the hi part to the
2976 // by-reg argument. If it does fit into a single register, return the result
2977 // and leave the Hi part unset.
2978 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
2981 SDOperand InChain = FindInputOutputChains(Node, OutChain,
2982 DAG.getEntryNode());
2983 if (InChain.Val == 0)
2984 InChain = DAG.getEntryNode();
2986 TargetLowering::ArgListTy Args;
2987 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2988 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
2989 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
2990 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
2992 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
2994 // Splice the libcall in wherever FindInputOutputChains tells us to.
2995 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
2996 std::pair<SDOperand,SDOperand> CallInfo =
2997 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3001 switch (getTypeAction(CallInfo.first.getValueType())) {
3002 default: assert(0 && "Unknown thing");
3004 Result = CallInfo.first;
3007 assert(0 && "Cannot promote this yet!");
3009 ExpandOp(CallInfo.first, Result, Hi);
3010 CallInfo.second = LegalizeOp(CallInfo.second);
3014 SpliceCallInto(CallInfo.second, OutChain);
3015 NeedsAnotherIteration = true;
3020 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3021 /// destination type is legal.
3022 SDOperand SelectionDAGLegalize::
3023 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3024 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3025 assert(getTypeAction(Source.getValueType()) == Expand &&
3026 "This is not an expansion!");
3027 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3030 assert(Source.getValueType() == MVT::i64 &&
3031 "This only works for 64-bit -> FP");
3032 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3033 // incoming integer is set. To handle this, we dynamically test to see if
3034 // it is set, and, if so, add a fudge factor.
3036 ExpandOp(Source, Lo, Hi);
3038 // If this is unsigned, and not supported, first perform the conversion to
3039 // signed, then adjust the result if the sign bit is set.
3040 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3041 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3043 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3044 DAG.getConstant(0, Hi.getValueType()),
3046 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3047 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3048 SignSet, Four, Zero);
3049 uint64_t FF = 0x5f800000ULL;
3050 if (TLI.isLittleEndian()) FF <<= 32;
3051 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3053 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3054 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3055 SDOperand FudgeInReg;
3056 if (DestTy == MVT::f32)
3057 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3058 DAG.getSrcValue(NULL));
3060 assert(DestTy == MVT::f64 && "Unexpected conversion");
3061 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3062 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3064 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3067 // Check to see if the target has a custom way to lower this. If so, use it.
3068 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3069 default: assert(0 && "This action not implemented for this operation!");
3070 case TargetLowering::Legal:
3071 case TargetLowering::Expand:
3072 break; // This case is handled below.
3073 case TargetLowering::Custom: {
3074 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3077 return LegalizeOp(NV);
3078 break; // The target decided this was legal after all
3082 // Expand the source, then glue it back together for the call. We must expand
3083 // the source in case it is shared (this pass of legalize must traverse it).
3084 SDOperand SrcLo, SrcHi;
3085 ExpandOp(Source, SrcLo, SrcHi);
3086 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3088 SDNode *OutChain = 0;
3089 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3090 DAG.getEntryNode());
3091 const char *FnName = 0;
3092 if (DestTy == MVT::f32)
3093 FnName = "__floatdisf";
3095 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3096 FnName = "__floatdidf";
3099 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3101 TargetLowering::ArgListTy Args;
3102 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3104 Args.push_back(std::make_pair(Source, ArgTy));
3106 // We don't care about token chains for libcalls. We just use the entry
3107 // node as our input and ignore the output chain. This allows us to place
3108 // calls wherever we need them to satisfy data dependences.
3109 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3111 std::pair<SDOperand,SDOperand> CallResult =
3112 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3115 SpliceCallInto(CallResult.second, OutChain);
3116 return CallResult.first;
3121 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3122 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3123 /// LegalizeNodes map is filled in for any results that are not expanded, the
3124 /// ExpandedNodes map is filled in for any results that are expanded, and the
3125 /// Lo/Hi values are returned.
3126 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3127 MVT::ValueType VT = Op.getValueType();
3128 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3129 SDNode *Node = Op.Val;
3130 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3131 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3132 "Cannot expand FP values!");
3133 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3134 "Cannot expand to FP value or to larger int value!");
3136 // See if we already expanded it.
3137 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3138 = ExpandedNodes.find(Op);
3139 if (I != ExpandedNodes.end()) {
3140 Lo = I->second.first;
3141 Hi = I->second.second;
3145 // Expanding to multiple registers needs to perform an optimization step, and
3146 // is not careful to avoid operations the target does not support. Make sure
3147 // that all generated operations are legalized in the next iteration.
3148 NeedsAnotherIteration = true;
3150 switch (Node->getOpcode()) {
3151 case ISD::CopyFromReg:
3152 assert(0 && "CopyFromReg must be legal!");
3154 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3155 assert(0 && "Do not know how to expand this operator!");
3158 Lo = DAG.getNode(ISD::UNDEF, NVT);
3159 Hi = DAG.getNode(ISD::UNDEF, NVT);
3161 case ISD::Constant: {
3162 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3163 Lo = DAG.getConstant(Cst, NVT);
3164 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3167 case ISD::ConstantVec: {
3168 unsigned NumElements = Node->getNumOperands();
3169 // If we only have two elements left in the constant vector, just break it
3170 // apart into the two scalar constants it contains. Otherwise, bisect the
3171 // ConstantVec, and return each half as a new ConstantVec.
3172 // FIXME: this is hard coded as big endian, it may have to change to support
3173 // SSE and Alpha MVI
3174 if (NumElements == 2) {
3175 Hi = Node->getOperand(0);
3176 Lo = Node->getOperand(1);
3179 std::vector<SDOperand> LoOps, HiOps;
3180 for (unsigned I = 0, E = NumElements; I < E; ++I) {
3181 HiOps.push_back(Node->getOperand(I));
3182 LoOps.push_back(Node->getOperand(I+NumElements));
3184 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
3185 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
3190 case ISD::BUILD_PAIR:
3191 // Legalize both operands. FIXME: in the future we should handle the case
3192 // where the two elements are not legal.
3193 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3194 Lo = LegalizeOp(Node->getOperand(0));
3195 Hi = LegalizeOp(Node->getOperand(1));
3199 ExpandOp(Node->getOperand(0), Lo, Hi);
3200 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3201 DAG.getNode(ISD::CTPOP, NVT, Lo),
3202 DAG.getNode(ISD::CTPOP, NVT, Hi));
3203 Hi = DAG.getConstant(0, NVT);
3207 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3208 ExpandOp(Node->getOperand(0), Lo, Hi);
3209 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3210 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3211 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3213 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3214 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3216 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3217 Hi = DAG.getConstant(0, NVT);
3222 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3223 ExpandOp(Node->getOperand(0), Lo, Hi);
3224 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3225 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3226 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3228 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3229 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3231 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3232 Hi = DAG.getConstant(0, NVT);
3237 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3238 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3239 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3241 // Increment the pointer to the other half.
3242 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3243 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3244 getIntPtrConstant(IncrementSize));
3245 //Is this safe? declaring that the two parts of the split load
3246 //are from the same instruction?
3247 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3249 // Build a factor node to remember that this load is independent of the
3251 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3254 // Remember that we legalized the chain.
3255 AddLegalizedOperand(Op.getValue(1), TF);
3256 if (!TLI.isLittleEndian())
3261 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3262 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3263 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3264 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3266 // If we only have two elements, turn into a pair of scalar loads.
3267 // FIXME: handle case where a vector of two elements is fine, such as
3268 // 2 x double on SSE2.
3269 if (NumElements == 2) {
3270 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3271 // Increment the pointer to the other half.
3272 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3273 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3274 getIntPtrConstant(IncrementSize));
3275 //Is this safe? declaring that the two parts of the split load
3276 //are from the same instruction?
3277 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3279 NumElements /= 2; // Split the vector in half
3280 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3281 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3282 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3283 getIntPtrConstant(IncrementSize));
3284 //Is this safe? declaring that the two parts of the split load
3285 //are from the same instruction?
3286 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3289 // Build a factor node to remember that this load is independent of the
3291 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3294 // Remember that we legalized the chain.
3295 AddLegalizedOperand(Op.getValue(1), TF);
3296 if (!TLI.isLittleEndian())
3303 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3304 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3305 SDOperand LL, LH, RL, RH;
3307 ExpandOp(Node->getOperand(0), LL, LH);
3308 ExpandOp(Node->getOperand(1), RL, RH);
3310 // If we only have two elements, turn into a pair of scalar loads.
3311 // FIXME: handle case where a vector of two elements is fine, such as
3312 // 2 x double on SSE2.
3313 if (NumElements == 2) {
3314 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3315 Lo = DAG.getNode(Opc, EVT, LL, RL);
3316 Hi = DAG.getNode(Opc, EVT, LH, RH);
3318 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3320 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3327 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3328 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3330 bool Changed = false;
3331 std::vector<SDOperand> Ops;
3332 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3333 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3334 Changed |= Ops.back() != Node->getOperand(i);
3337 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3338 "Can only expand a call once so far, not i64 -> i16!");
3340 std::vector<MVT::ValueType> RetTyVTs;
3341 RetTyVTs.reserve(3);
3342 RetTyVTs.push_back(NVT);
3343 RetTyVTs.push_back(NVT);
3344 RetTyVTs.push_back(MVT::Other);
3345 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3346 Node->getOpcode() == ISD::TAILCALL);
3347 Lo = SDOperand(NC, 0);
3348 Hi = SDOperand(NC, 1);
3350 // Insert the new chain mapping.
3351 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3356 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3357 SDOperand LL, LH, RL, RH;
3358 ExpandOp(Node->getOperand(0), LL, LH);
3359 ExpandOp(Node->getOperand(1), RL, RH);
3360 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3361 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3365 SDOperand C, LL, LH, RL, RH;
3367 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3368 case Expand: assert(0 && "It's impossible to expand bools");
3370 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3373 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3376 ExpandOp(Node->getOperand(1), LL, LH);
3377 ExpandOp(Node->getOperand(2), RL, RH);
3378 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3379 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3382 case ISD::SELECT_CC: {
3383 SDOperand TL, TH, FL, FH;
3384 ExpandOp(Node->getOperand(2), TL, TH);
3385 ExpandOp(Node->getOperand(3), FL, FH);
3386 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3387 Node->getOperand(1), TL, FL, Node->getOperand(4));
3388 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3389 Node->getOperand(1), TH, FH, Node->getOperand(4));
3390 Lo = LegalizeOp(Lo);
3391 Hi = LegalizeOp(Hi);
3394 case ISD::SEXTLOAD: {
3395 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3396 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3397 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3400 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3402 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3405 // Remember that we legalized the chain.
3406 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3408 // The high part is obtained by SRA'ing all but one of the bits of the lo
3410 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3411 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3412 TLI.getShiftAmountTy()));
3413 Lo = LegalizeOp(Lo);
3414 Hi = LegalizeOp(Hi);
3417 case ISD::ZEXTLOAD: {
3418 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3419 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3420 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3423 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3425 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3428 // Remember that we legalized the chain.
3429 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3431 // The high part is just a zero.
3432 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3433 Lo = LegalizeOp(Lo);
3436 case ISD::EXTLOAD: {
3437 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3438 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3439 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3442 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3444 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3447 // Remember that we legalized the chain.
3448 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3450 // The high part is undefined.
3451 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3452 Lo = LegalizeOp(Lo);
3455 case ISD::ANY_EXTEND: {
3457 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3458 case Expand: assert(0 && "expand-expand not implemented yet!");
3459 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3461 In = PromoteOp(Node->getOperand(0));
3465 // The low part is any extension of the input (which degenerates to a copy).
3466 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3467 // The high part is undefined.
3468 Hi = DAG.getNode(ISD::UNDEF, NVT);
3471 case ISD::SIGN_EXTEND: {
3473 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3474 case Expand: assert(0 && "expand-expand not implemented yet!");
3475 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3477 In = PromoteOp(Node->getOperand(0));
3478 // Emit the appropriate sign_extend_inreg to get the value we want.
3479 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3480 DAG.getValueType(Node->getOperand(0).getValueType()));
3484 // The low part is just a sign extension of the input (which degenerates to
3486 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3488 // The high part is obtained by SRA'ing all but one of the bits of the lo
3490 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3491 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3492 TLI.getShiftAmountTy()));
3495 case ISD::ZERO_EXTEND: {
3497 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3498 case Expand: assert(0 && "expand-expand not implemented yet!");
3499 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3501 In = PromoteOp(Node->getOperand(0));
3502 // Emit the appropriate zero_extend_inreg to get the value we want.
3503 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3507 // The low part is just a zero extension of the input (which degenerates to
3509 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3511 // The high part is just a zero.
3512 Hi = DAG.getConstant(0, NVT);
3516 case ISD::READCYCLECOUNTER: {
3517 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3518 TargetLowering::Custom &&
3519 "Must custom expand ReadCycleCounter");
3520 SDOperand T = TLI.LowerOperation(Op, DAG);
3521 assert(T.Val && "Node must be custom expanded!");
3522 Lo = LegalizeOp(T.getValue(0));
3523 Hi = LegalizeOp(T.getValue(1));
3524 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3525 LegalizeOp(T.getValue(2)));
3529 // These operators cannot be expanded directly, emit them as calls to
3530 // library functions.
3531 case ISD::FP_TO_SINT:
3532 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3534 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3535 case Expand: assert(0 && "cannot expand FP!");
3536 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3537 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3540 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3542 // Now that the custom expander is done, expand the result, which is still
3545 ExpandOp(Op, Lo, Hi);
3550 if (Node->getOperand(0).getValueType() == MVT::f32)
3551 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3553 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3556 case ISD::FP_TO_UINT:
3557 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3558 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3559 LegalizeOp(Node->getOperand(0)));
3560 // Now that the custom expander is done, expand the result, which is still
3562 Op = TLI.LowerOperation(Op, DAG);
3564 ExpandOp(Op, Lo, Hi);
3569 if (Node->getOperand(0).getValueType() == MVT::f32)
3570 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3572 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3576 // If the target wants custom lowering, do so.
3577 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3578 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3579 LegalizeOp(Node->getOperand(1)));
3580 Op = TLI.LowerOperation(Op, DAG);
3582 // Now that the custom expander is done, expand the result, which is
3584 ExpandOp(Op, Lo, Hi);
3589 // If we can emit an efficient shift operation, do so now.
3590 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3593 // If this target supports SHL_PARTS, use it.
3594 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3595 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3600 // Otherwise, emit a libcall.
3601 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3605 // If the target wants custom lowering, do so.
3606 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3607 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3608 LegalizeOp(Node->getOperand(1)));
3609 Op = TLI.LowerOperation(Op, DAG);
3611 // Now that the custom expander is done, expand the result, which is
3613 ExpandOp(Op, Lo, Hi);
3618 // If we can emit an efficient shift operation, do so now.
3619 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3622 // If this target supports SRA_PARTS, use it.
3623 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3624 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3629 // Otherwise, emit a libcall.
3630 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3633 // If the target wants custom lowering, do so.
3634 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3635 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3636 LegalizeOp(Node->getOperand(1)));
3637 Op = TLI.LowerOperation(Op, DAG);
3639 // Now that the custom expander is done, expand the result, which is
3641 ExpandOp(Op, Lo, Hi);
3646 // If we can emit an efficient shift operation, do so now.
3647 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3650 // If this target supports SRL_PARTS, use it.
3651 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3652 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3657 // Otherwise, emit a libcall.
3658 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3662 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3666 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3670 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3671 SDOperand LL, LH, RL, RH;
3672 ExpandOp(Node->getOperand(0), LL, LH);
3673 ExpandOp(Node->getOperand(1), RL, RH);
3674 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3675 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3676 // extended the sign bit of the low half through the upper half, and if so
3677 // emit a MULHS instead of the alternate sequence that is valid for any
3678 // i64 x i64 multiply.
3679 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3680 // is RH an extension of the sign bit of RL?
3681 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3682 RH.getOperand(1).getOpcode() == ISD::Constant &&
3683 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3684 // is LH an extension of the sign bit of LL?
3685 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3686 LH.getOperand(1).getOpcode() == ISD::Constant &&
3687 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3688 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3690 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3691 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3692 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3693 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3694 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3696 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3698 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3702 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3703 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3704 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3705 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3708 // Remember in a map if the values will be reused later.
3709 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3710 std::make_pair(Lo, Hi))).second;
3711 assert(isNew && "Value already expanded?!?");
3715 // SelectionDAG::Legalize - This is the entry point for the file.
3717 void SelectionDAG::Legalize() {
3718 /// run - This is the main entry point to this class.
3720 SelectionDAGLegalize(*this).Run();