1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/Support/CommandLine.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
39 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
40 cl::desc("Pop up a window to show dags before legalize"));
42 static const bool ViewLegalizeDAGs = 0;
45 //===----------------------------------------------------------------------===//
46 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
47 /// hacks on it until the target machine can handle it. This involves
48 /// eliminating value sizes the machine cannot handle (promoting small sizes to
49 /// large sizes or splitting up large values into small values) as well as
50 /// eliminating operations the machine cannot handle.
52 /// This code also does a small amount of optimization and recognition of idioms
53 /// as part of its processing. For example, if a target does not support a
54 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
55 /// will attempt merge setcc and brc instructions into brcc's.
58 class VISIBILITY_HIDDEN SelectionDAGLegalize {
62 // Libcall insertion helpers.
64 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
65 /// legalized. We use this to ensure that calls are properly serialized
66 /// against each other, including inserted libcalls.
67 SDOperand LastCALLSEQ_END;
69 /// IsLegalizingCall - This member is used *only* for purposes of providing
70 /// helpful assertions that a libcall isn't created while another call is
71 /// being legalized (which could lead to non-serialized call sequences).
72 bool IsLegalizingCall;
75 Legal, // The target natively supports this operation.
76 Promote, // This operation should be executed in a larger type.
77 Expand // Try to expand this to other ops, otherwise use a libcall.
80 /// ValueTypeActions - This is a bitvector that contains two bits for each
81 /// value type, where the two bits correspond to the LegalizeAction enum.
82 /// This can be queried with "getTypeAction(VT)".
83 TargetLowering::ValueTypeActionImpl ValueTypeActions;
85 /// LegalizedNodes - For nodes that are of legal width, and that have more
86 /// than one use, this map indicates what regularized operand to use. This
87 /// allows us to avoid legalizing the same thing more than once.
88 DenseMap<SDOperand, SDOperand> LegalizedNodes;
90 /// PromotedNodes - For nodes that are below legal width, and that have more
91 /// than one use, this map indicates what promoted value to use. This allows
92 /// us to avoid promoting the same thing more than once.
93 DenseMap<SDOperand, SDOperand> PromotedNodes;
95 /// ExpandedNodes - For nodes that need to be expanded this map indicates
96 /// which which operands are the expanded version of the input. This allows
97 /// us to avoid expanding the same node more than once.
98 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
100 /// SplitNodes - For vector nodes that need to be split, this map indicates
101 /// which which operands are the split version of the input. This allows us
102 /// to avoid splitting the same node more than once.
103 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
105 /// ScalarizedNodes - For nodes that need to be converted from vector types to
106 /// scalar types, this contains the mapping of ones we have already
107 /// processed to the result.
108 std::map<SDOperand, SDOperand> ScalarizedNodes;
110 void AddLegalizedOperand(SDOperand From, SDOperand To) {
111 LegalizedNodes.insert(std::make_pair(From, To));
112 // If someone requests legalization of the new node, return itself.
114 LegalizedNodes.insert(std::make_pair(To, To));
116 void AddPromotedOperand(SDOperand From, SDOperand To) {
117 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
118 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
125 SelectionDAGLegalize(SelectionDAG &DAG);
127 /// getTypeAction - Return how we should legalize values of this type, either
128 /// it is already legal or we need to expand it into multiple registers of
129 /// smaller integer type, or we need to promote it to a larger type.
130 LegalizeAction getTypeAction(MVT::ValueType VT) const {
131 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
134 /// isTypeLegal - Return true if this type is legal on this target.
136 bool isTypeLegal(MVT::ValueType VT) const {
137 return getTypeAction(VT) == Legal;
143 /// HandleOp - Legalize, Promote, or Expand the specified operand as
144 /// appropriate for its type.
145 void HandleOp(SDOperand Op);
147 /// LegalizeOp - We know that the specified value has a legal type.
148 /// Recursively ensure that the operands have legal types, then return the
150 SDOperand LegalizeOp(SDOperand O);
152 /// UnrollVectorOp - We know that the given vector has a legal type, however
153 /// the operation it performs is not legal and is an operation that we have
154 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
155 /// operating on each element individually.
156 SDOperand UnrollVectorOp(SDOperand O);
158 /// PromoteOp - Given an operation that produces a value in an invalid type,
159 /// promote it to compute the value into a larger type. The produced value
160 /// will have the correct bits for the low portion of the register, but no
161 /// guarantee is made about the top bits: it may be zero, sign-extended, or
163 SDOperand PromoteOp(SDOperand O);
165 /// ExpandOp - Expand the specified SDOperand into its two component pieces
166 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
167 /// the LegalizeNodes map is filled in for any results that are not expanded,
168 /// the ExpandedNodes map is filled in for any results that are expanded, and
169 /// the Lo/Hi values are returned. This applies to integer types and Vector
171 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
173 /// SplitVectorOp - Given an operand of vector type, break it down into
174 /// two smaller values.
175 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
177 /// ScalarizeVectorOp - Given an operand of single-element vector type
178 /// (e.g. v1f32), convert it into the equivalent operation that returns a
179 /// scalar (e.g. f32) value.
180 SDOperand ScalarizeVectorOp(SDOperand O);
182 /// isShuffleLegal - Return true if a vector shuffle is legal with the
183 /// specified mask and type. Targets can specify exactly which masks they
184 /// support and the code generator is tasked with not creating illegal masks.
186 /// Note that this will also return true for shuffles that are promoted to a
189 /// If this is a legal shuffle, this method returns the (possibly promoted)
190 /// build_vector Mask. If it's not a legal shuffle, it returns null.
191 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
193 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
194 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
196 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
198 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
200 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
203 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
204 MVT::ValueType DestVT);
205 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
206 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
207 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
209 MVT::ValueType DestVT);
210 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
212 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
215 SDOperand ExpandBSWAP(SDOperand Op);
216 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
217 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
218 SDOperand &Lo, SDOperand &Hi);
219 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
220 SDOperand &Lo, SDOperand &Hi);
222 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
223 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
227 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
228 /// specified mask and type. Targets can specify exactly which masks they
229 /// support and the code generator is tasked with not creating illegal masks.
231 /// Note that this will also return true for shuffles that are promoted to a
233 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
234 SDOperand Mask) const {
235 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
237 case TargetLowering::Legal:
238 case TargetLowering::Custom:
240 case TargetLowering::Promote: {
241 // If this is promoted to a different type, convert the shuffle mask and
242 // ask if it is legal in the promoted type!
243 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
245 // If we changed # elements, change the shuffle mask.
246 unsigned NumEltsGrowth =
247 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
248 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
249 if (NumEltsGrowth > 1) {
250 // Renumber the elements.
251 SmallVector<SDOperand, 8> Ops;
252 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
253 SDOperand InOp = Mask.getOperand(i);
254 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
255 if (InOp.getOpcode() == ISD::UNDEF)
256 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
258 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
259 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
263 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
269 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
272 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
273 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
274 ValueTypeActions(TLI.getValueTypeActions()) {
275 assert(MVT::LAST_VALUETYPE <= 32 &&
276 "Too many value types for ValueTypeActions to hold!");
279 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
280 /// contains all of a nodes operands before it contains the node.
281 static void ComputeTopDownOrdering(SelectionDAG &DAG,
282 SmallVector<SDNode*, 64> &Order) {
284 DenseMap<SDNode*, unsigned> Visited;
285 std::vector<SDNode*> Worklist;
286 Worklist.reserve(128);
288 // Compute ordering from all of the leaves in the graphs, those (like the
289 // entry node) that have no operands.
290 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
291 E = DAG.allnodes_end(); I != E; ++I) {
292 if (I->getNumOperands() == 0) {
294 Worklist.push_back(I);
298 while (!Worklist.empty()) {
299 SDNode *N = Worklist.back();
302 if (++Visited[N] != N->getNumOperands())
303 continue; // Haven't visited all operands yet
307 // Now that we have N in, add anything that uses it if all of their operands
309 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
311 Worklist.push_back(*UI);
314 assert(Order.size() == Visited.size() &&
316 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
317 "Error: DAG is cyclic!");
321 void SelectionDAGLegalize::LegalizeDAG() {
322 LastCALLSEQ_END = DAG.getEntryNode();
323 IsLegalizingCall = false;
325 // The legalize process is inherently a bottom-up recursive process (users
326 // legalize their uses before themselves). Given infinite stack space, we
327 // could just start legalizing on the root and traverse the whole graph. In
328 // practice however, this causes us to run out of stack space on large basic
329 // blocks. To avoid this problem, compute an ordering of the nodes where each
330 // node is only legalized after all of its operands are legalized.
331 SmallVector<SDNode*, 64> Order;
332 ComputeTopDownOrdering(DAG, Order);
334 for (unsigned i = 0, e = Order.size(); i != e; ++i)
335 HandleOp(SDOperand(Order[i], 0));
337 // Finally, it's possible the root changed. Get the new root.
338 SDOperand OldRoot = DAG.getRoot();
339 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
340 DAG.setRoot(LegalizedNodes[OldRoot]);
342 ExpandedNodes.clear();
343 LegalizedNodes.clear();
344 PromotedNodes.clear();
346 ScalarizedNodes.clear();
348 // Remove dead nodes now.
349 DAG.RemoveDeadNodes();
353 /// FindCallEndFromCallStart - Given a chained node that is part of a call
354 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
355 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
356 if (Node->getOpcode() == ISD::CALLSEQ_END)
358 if (Node->use_empty())
359 return 0; // No CallSeqEnd
361 // The chain is usually at the end.
362 SDOperand TheChain(Node, Node->getNumValues()-1);
363 if (TheChain.getValueType() != MVT::Other) {
364 // Sometimes it's at the beginning.
365 TheChain = SDOperand(Node, 0);
366 if (TheChain.getValueType() != MVT::Other) {
367 // Otherwise, hunt for it.
368 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
369 if (Node->getValueType(i) == MVT::Other) {
370 TheChain = SDOperand(Node, i);
374 // Otherwise, we walked into a node without a chain.
375 if (TheChain.getValueType() != MVT::Other)
380 for (SDNode::use_iterator UI = Node->use_begin(),
381 E = Node->use_end(); UI != E; ++UI) {
383 // Make sure to only follow users of our token chain.
385 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
386 if (User->getOperand(i) == TheChain)
387 if (SDNode *Result = FindCallEndFromCallStart(User))
393 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
394 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
395 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
396 assert(Node && "Didn't find callseq_start for a call??");
397 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
399 assert(Node->getOperand(0).getValueType() == MVT::Other &&
400 "Node doesn't have a token chain argument!");
401 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
404 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
405 /// see if any uses can reach Dest. If no dest operands can get to dest,
406 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 /// Keep track of the nodes we fine that actually do lead to Dest in
409 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
411 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
412 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
413 if (N == Dest) return true; // N certainly leads to Dest :)
415 // If we've already processed this node and it does lead to Dest, there is no
416 // need to reprocess it.
417 if (NodesLeadingTo.count(N)) return true;
419 // If the first result of this node has been already legalized, then it cannot
421 switch (getTypeAction(N->getValueType(0))) {
423 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
426 if (PromotedNodes.count(SDOperand(N, 0))) return false;
429 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
433 // Okay, this node has not already been legalized. Check and legalize all
434 // operands. If none lead to Dest, then we can legalize this node.
435 bool OperandsLeadToDest = false;
436 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
437 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
438 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
440 if (OperandsLeadToDest) {
441 NodesLeadingTo.insert(N);
445 // Okay, this node looks safe, legalize it and return false.
446 HandleOp(SDOperand(N, 0));
450 /// HandleOp - Legalize, Promote, or Expand the specified operand as
451 /// appropriate for its type.
452 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
453 MVT::ValueType VT = Op.getValueType();
454 switch (getTypeAction(VT)) {
455 default: assert(0 && "Bad type action!");
456 case Legal: (void)LegalizeOp(Op); break;
457 case Promote: (void)PromoteOp(Op); break;
459 if (!MVT::isVector(VT)) {
460 // If this is an illegal scalar, expand it into its two component
463 if (Op.getOpcode() == ISD::TargetConstant)
464 break; // Allow illegal target nodes.
466 } else if (MVT::getVectorNumElements(VT) == 1) {
467 // If this is an illegal single element vector, convert it to a
469 (void)ScalarizeVectorOp(Op);
471 // Otherwise, this is an illegal multiple element vector.
472 // Split it in half and legalize both parts.
474 SplitVectorOp(Op, X, Y);
480 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
481 /// a load from the constant pool.
482 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
483 SelectionDAG &DAG, TargetLowering &TLI) {
486 // If a FP immediate is precise when represented as a float and if the
487 // target can do an extending load from float to double, we put it into
488 // the constant pool as a float, even if it's is statically typed as a
490 MVT::ValueType VT = CFP->getValueType(0);
491 ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
494 if (VT!=MVT::f64 && VT!=MVT::f32)
495 assert(0 && "Invalid type expansion");
496 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt().getZExtValue(),
497 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
500 MVT::ValueType OrigVT = VT;
501 MVT::ValueType SVT = VT;
502 while (SVT != MVT::f32) {
503 SVT = (unsigned)SVT - 1;
504 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
505 // Only do this if the target has a native EXTLOAD instruction from
507 TLI.isLoadXLegal(ISD::EXTLOAD, SVT)) {
508 const Type *SType = MVT::getTypeForValueType(SVT);
509 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
515 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
517 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
518 CPIdx, PseudoSourceValue::getConstantPool(),
520 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
521 PseudoSourceValue::getConstantPool(), 0);
525 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
528 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
529 SelectionDAG &DAG, TargetLowering &TLI) {
530 MVT::ValueType VT = Node->getValueType(0);
531 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
532 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
533 "fcopysign expansion only supported for f32 and f64");
534 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
536 // First get the sign bit of second operand.
537 SDOperand Mask1 = (SrcVT == MVT::f64)
538 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
539 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
540 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
541 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
542 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
543 // Shift right or sign-extend it if the two operands have different types.
544 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
546 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
547 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
548 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
549 } else if (SizeDiff < 0)
550 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
552 // Clear the sign bit of first operand.
553 SDOperand Mask2 = (VT == MVT::f64)
554 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
555 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
556 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
557 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
558 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
560 // Or the value with the sign bit.
561 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
565 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
567 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
568 TargetLowering &TLI) {
569 SDOperand Chain = ST->getChain();
570 SDOperand Ptr = ST->getBasePtr();
571 SDOperand Val = ST->getValue();
572 MVT::ValueType VT = Val.getValueType();
573 int Alignment = ST->getAlignment();
574 int SVOffset = ST->getSrcValueOffset();
575 if (MVT::isFloatingPoint(ST->getMemoryVT()) ||
576 MVT::isVector(ST->getMemoryVT())) {
577 // Expand to a bitconvert of the value to the integer type of the
578 // same size, then a (misaligned) int store.
579 MVT::ValueType intVT;
580 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
582 else if (MVT::is64BitVector(VT) || VT==MVT::f64)
584 else if (VT==MVT::f32)
587 assert(0 && "Unaligned store of unsupported type");
589 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
590 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
591 SVOffset, ST->isVolatile(), Alignment);
593 assert(MVT::isInteger(ST->getMemoryVT()) &&
594 !MVT::isVector(ST->getMemoryVT()) &&
595 "Unaligned store of unknown type.");
596 // Get the half-size VT
597 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
598 int NumBits = MVT::getSizeInBits(NewStoredVT);
599 int IncrementSize = NumBits / 8;
601 // Divide the stored value in two parts.
602 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
604 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
606 // Store the two parts
607 SDOperand Store1, Store2;
608 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
609 ST->getSrcValue(), SVOffset, NewStoredVT,
610 ST->isVolatile(), Alignment);
611 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
612 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
613 Alignment = MinAlign(Alignment, IncrementSize);
614 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
615 ST->getSrcValue(), SVOffset + IncrementSize,
616 NewStoredVT, ST->isVolatile(), Alignment);
618 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
621 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
623 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
624 TargetLowering &TLI) {
625 int SVOffset = LD->getSrcValueOffset();
626 SDOperand Chain = LD->getChain();
627 SDOperand Ptr = LD->getBasePtr();
628 MVT::ValueType VT = LD->getValueType(0);
629 MVT::ValueType LoadedVT = LD->getMemoryVT();
630 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
631 // Expand to a (misaligned) integer load of the same size,
632 // then bitconvert to floating point or vector.
633 MVT::ValueType intVT;
634 if (MVT::is128BitVector(LoadedVT) ||
635 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
637 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
639 else if (LoadedVT == MVT::f32)
642 assert(0 && "Unaligned load of unsupported type");
644 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
645 SVOffset, LD->isVolatile(),
647 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
648 if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
649 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
651 SDOperand Ops[] = { Result, Chain };
652 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
655 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
656 "Unaligned load of unsupported type.");
658 // Compute the new VT that is half the size of the old one. This is an
660 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
661 MVT::ValueType NewLoadedVT;
662 NewLoadedVT = MVT::getIntegerType(NumBits/2);
665 unsigned Alignment = LD->getAlignment();
666 unsigned IncrementSize = NumBits / 8;
667 ISD::LoadExtType HiExtType = LD->getExtensionType();
669 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
670 if (HiExtType == ISD::NON_EXTLOAD)
671 HiExtType = ISD::ZEXTLOAD;
673 // Load the value in two parts
675 if (TLI.isLittleEndian()) {
676 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
677 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
678 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
679 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
680 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
681 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
682 MinAlign(Alignment, IncrementSize));
684 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
685 NewLoadedVT,LD->isVolatile(), Alignment);
686 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
687 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
688 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
689 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
690 MinAlign(Alignment, IncrementSize));
693 // aggregate the two parts
694 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
695 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
696 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
698 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
701 SDOperand Ops[] = { Result, TF };
702 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
705 /// UnrollVectorOp - We know that the given vector has a legal type, however
706 /// the operation it performs is not legal and is an operation that we have
707 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
708 /// operating on each element individually.
709 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
710 MVT::ValueType VT = Op.getValueType();
711 assert(isTypeLegal(VT) &&
712 "Caller should expand or promote operands that are not legal!");
713 assert(Op.Val->getNumValues() == 1 &&
714 "Can't unroll a vector with multiple results!");
715 unsigned NE = MVT::getVectorNumElements(VT);
716 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
718 SmallVector<SDOperand, 8> Scalars;
719 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
720 for (unsigned i = 0; i != NE; ++i) {
721 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
722 SDOperand Operand = Op.getOperand(j);
723 MVT::ValueType OperandVT = Operand.getValueType();
724 if (MVT::isVector(OperandVT)) {
725 // A vector operand; extract a single element.
726 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
727 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
730 DAG.getConstant(i, MVT::i32));
732 // A scalar operand; just use it as is.
733 Operands[j] = Operand;
736 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
737 &Operands[0], Operands.size()));
740 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
743 /// GetFPLibCall - Return the right libcall for the given floating point type.
744 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
745 RTLIB::Libcall Call_F32,
746 RTLIB::Libcall Call_F64,
747 RTLIB::Libcall Call_F80,
748 RTLIB::Libcall Call_PPCF128) {
750 VT == MVT::f32 ? Call_F32 :
751 VT == MVT::f64 ? Call_F64 :
752 VT == MVT::f80 ? Call_F80 :
753 VT == MVT::ppcf128 ? Call_PPCF128 :
754 RTLIB::UNKNOWN_LIBCALL;
757 /// LegalizeOp - We know that the specified value has a legal type, and
758 /// that its operands are legal. Now ensure that the operation itself
759 /// is legal, recursively ensuring that the operands' operations remain
761 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
762 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
765 assert(isTypeLegal(Op.getValueType()) &&
766 "Caller should expand or promote operands that are not legal!");
767 SDNode *Node = Op.Val;
769 // If this operation defines any values that cannot be represented in a
770 // register on this target, make sure to expand or promote them.
771 if (Node->getNumValues() > 1) {
772 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
773 if (getTypeAction(Node->getValueType(i)) != Legal) {
774 HandleOp(Op.getValue(i));
775 assert(LegalizedNodes.count(Op) &&
776 "Handling didn't add legal operands!");
777 return LegalizedNodes[Op];
781 // Note that LegalizeOp may be reentered even from single-use nodes, which
782 // means that we always must cache transformed nodes.
783 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
784 if (I != LegalizedNodes.end()) return I->second;
786 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
787 SDOperand Result = Op;
788 bool isCustom = false;
790 switch (Node->getOpcode()) {
791 case ISD::FrameIndex:
792 case ISD::EntryToken:
794 case ISD::BasicBlock:
795 case ISD::TargetFrameIndex:
796 case ISD::TargetJumpTable:
797 case ISD::TargetConstant:
798 case ISD::TargetConstantFP:
799 case ISD::TargetConstantPool:
800 case ISD::TargetGlobalAddress:
801 case ISD::TargetGlobalTLSAddress:
802 case ISD::TargetExternalSymbol:
805 case ISD::MEMOPERAND:
808 // Primitives must all be legal.
809 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
810 "This must be legal!");
813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
814 // If this is a target node, legalize it by legalizing the operands then
815 // passing it through.
816 SmallVector<SDOperand, 8> Ops;
817 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
818 Ops.push_back(LegalizeOp(Node->getOperand(i)));
820 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
822 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
823 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
824 return Result.getValue(Op.ResNo);
826 // Otherwise this is an unhandled builtin node. splat.
828 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
830 assert(0 && "Do not know how to legalize this operator!");
832 case ISD::GLOBAL_OFFSET_TABLE:
833 case ISD::GlobalAddress:
834 case ISD::GlobalTLSAddress:
835 case ISD::ExternalSymbol:
836 case ISD::ConstantPool:
837 case ISD::JumpTable: // Nothing to do.
838 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
839 default: assert(0 && "This action is not supported yet!");
840 case TargetLowering::Custom:
841 Tmp1 = TLI.LowerOperation(Op, DAG);
842 if (Tmp1.Val) Result = Tmp1;
843 // FALLTHROUGH if the target doesn't want to lower this op after all.
844 case TargetLowering::Legal:
849 case ISD::RETURNADDR:
850 // The only option for these nodes is to custom lower them. If the target
851 // does not custom lower them, then return zero.
852 Tmp1 = TLI.LowerOperation(Op, DAG);
856 Result = DAG.getConstant(0, TLI.getPointerTy());
858 case ISD::FRAME_TO_ARGS_OFFSET: {
859 MVT::ValueType VT = Node->getValueType(0);
860 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
861 default: assert(0 && "This action is not supported yet!");
862 case TargetLowering::Custom:
863 Result = TLI.LowerOperation(Op, DAG);
864 if (Result.Val) break;
866 case TargetLowering::Legal:
867 Result = DAG.getConstant(0, VT);
872 case ISD::EXCEPTIONADDR: {
873 Tmp1 = LegalizeOp(Node->getOperand(0));
874 MVT::ValueType VT = Node->getValueType(0);
875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
876 default: assert(0 && "This action is not supported yet!");
877 case TargetLowering::Expand: {
878 unsigned Reg = TLI.getExceptionAddressRegister();
879 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
882 case TargetLowering::Custom:
883 Result = TLI.LowerOperation(Op, DAG);
884 if (Result.Val) break;
886 case TargetLowering::Legal: {
887 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
888 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
894 if (Result.Val->getNumValues() == 1) break;
896 assert(Result.Val->getNumValues() == 2 &&
897 "Cannot return more than two values!");
899 // Since we produced two values, make sure to remember that we
900 // legalized both of them.
901 Tmp1 = LegalizeOp(Result);
902 Tmp2 = LegalizeOp(Result.getValue(1));
903 AddLegalizedOperand(Op.getValue(0), Tmp1);
904 AddLegalizedOperand(Op.getValue(1), Tmp2);
905 return Op.ResNo ? Tmp2 : Tmp1;
906 case ISD::EHSELECTION: {
907 Tmp1 = LegalizeOp(Node->getOperand(0));
908 Tmp2 = LegalizeOp(Node->getOperand(1));
909 MVT::ValueType VT = Node->getValueType(0);
910 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
911 default: assert(0 && "This action is not supported yet!");
912 case TargetLowering::Expand: {
913 unsigned Reg = TLI.getExceptionSelectorRegister();
914 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
917 case TargetLowering::Custom:
918 Result = TLI.LowerOperation(Op, DAG);
919 if (Result.Val) break;
921 case TargetLowering::Legal: {
922 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
923 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
929 if (Result.Val->getNumValues() == 1) break;
931 assert(Result.Val->getNumValues() == 2 &&
932 "Cannot return more than two values!");
934 // Since we produced two values, make sure to remember that we
935 // legalized both of them.
936 Tmp1 = LegalizeOp(Result);
937 Tmp2 = LegalizeOp(Result.getValue(1));
938 AddLegalizedOperand(Op.getValue(0), Tmp1);
939 AddLegalizedOperand(Op.getValue(1), Tmp2);
940 return Op.ResNo ? Tmp2 : Tmp1;
941 case ISD::EH_RETURN: {
942 MVT::ValueType VT = Node->getValueType(0);
943 // The only "good" option for this node is to custom lower it.
944 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
945 default: assert(0 && "This action is not supported at all!");
946 case TargetLowering::Custom:
947 Result = TLI.LowerOperation(Op, DAG);
948 if (Result.Val) break;
950 case TargetLowering::Legal:
951 // Target does not know, how to lower this, lower to noop
952 Result = LegalizeOp(Node->getOperand(0));
957 case ISD::AssertSext:
958 case ISD::AssertZext:
959 Tmp1 = LegalizeOp(Node->getOperand(0));
960 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
962 case ISD::MERGE_VALUES:
963 // Legalize eliminates MERGE_VALUES nodes.
964 Result = Node->getOperand(Op.ResNo);
966 case ISD::CopyFromReg:
967 Tmp1 = LegalizeOp(Node->getOperand(0));
968 Result = Op.getValue(0);
969 if (Node->getNumValues() == 2) {
970 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
972 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
973 if (Node->getNumOperands() == 3) {
974 Tmp2 = LegalizeOp(Node->getOperand(2));
975 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
977 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
979 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
981 // Since CopyFromReg produces two values, make sure to remember that we
982 // legalized both of them.
983 AddLegalizedOperand(Op.getValue(0), Result);
984 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
985 return Result.getValue(Op.ResNo);
987 MVT::ValueType VT = Op.getValueType();
988 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
989 default: assert(0 && "This action is not supported yet!");
990 case TargetLowering::Expand:
991 if (MVT::isInteger(VT))
992 Result = DAG.getConstant(0, VT);
993 else if (MVT::isFloatingPoint(VT))
994 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
997 assert(0 && "Unknown value type!");
999 case TargetLowering::Legal:
1005 case ISD::INTRINSIC_W_CHAIN:
1006 case ISD::INTRINSIC_WO_CHAIN:
1007 case ISD::INTRINSIC_VOID: {
1008 SmallVector<SDOperand, 8> Ops;
1009 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1010 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1011 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1013 // Allow the target to custom lower its intrinsics if it wants to.
1014 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1015 TargetLowering::Custom) {
1016 Tmp3 = TLI.LowerOperation(Result, DAG);
1017 if (Tmp3.Val) Result = Tmp3;
1020 if (Result.Val->getNumValues() == 1) break;
1022 // Must have return value and chain result.
1023 assert(Result.Val->getNumValues() == 2 &&
1024 "Cannot return more than two values!");
1026 // Since loads produce two values, make sure to remember that we
1027 // legalized both of them.
1028 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1029 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1030 return Result.getValue(Op.ResNo);
1034 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1035 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1037 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1038 case TargetLowering::Promote:
1039 default: assert(0 && "This action is not supported yet!");
1040 case TargetLowering::Expand: {
1041 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1042 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1043 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1045 if (MMI && (useDEBUG_LOC || useLABEL)) {
1046 const std::string &FName =
1047 cast<StringSDNode>(Node->getOperand(3))->getValue();
1048 const std::string &DirName =
1049 cast<StringSDNode>(Node->getOperand(4))->getValue();
1050 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1052 SmallVector<SDOperand, 8> Ops;
1053 Ops.push_back(Tmp1); // chain
1054 SDOperand LineOp = Node->getOperand(1);
1055 SDOperand ColOp = Node->getOperand(2);
1058 Ops.push_back(LineOp); // line #
1059 Ops.push_back(ColOp); // col #
1060 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1061 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1063 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1064 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1065 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1066 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1067 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1068 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1071 Result = Tmp1; // chain
1075 case TargetLowering::Legal:
1076 if (Tmp1 != Node->getOperand(0) ||
1077 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1078 SmallVector<SDOperand, 8> Ops;
1079 Ops.push_back(Tmp1);
1080 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1081 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1082 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1084 // Otherwise promote them.
1085 Ops.push_back(PromoteOp(Node->getOperand(1)));
1086 Ops.push_back(PromoteOp(Node->getOperand(2)));
1088 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1089 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1090 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1097 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1098 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1099 default: assert(0 && "This action is not supported yet!");
1100 case TargetLowering::Legal:
1101 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1102 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1103 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1104 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1106 case TargetLowering::Expand:
1107 Result = LegalizeOp(Node->getOperand(0));
1112 case ISD::DEBUG_LOC:
1113 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1114 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1115 default: assert(0 && "This action is not supported yet!");
1116 case TargetLowering::Legal:
1117 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1118 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1119 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1120 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1121 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1127 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1128 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1129 default: assert(0 && "This action is not supported yet!");
1130 case TargetLowering::Legal:
1131 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1132 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1133 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1134 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1136 case TargetLowering::Expand:
1137 Result = LegalizeOp(Node->getOperand(0));
1142 case ISD::MEMBARRIER: {
1143 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1144 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1145 default: assert(0 && "This action is not supported yet!");
1146 case TargetLowering::Legal: {
1148 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1149 for (int x = 1; x < 6; ++x) {
1150 Ops[x] = Node->getOperand(x);
1151 if (!isTypeLegal(Ops[x].getValueType()))
1152 Ops[x] = PromoteOp(Ops[x]);
1154 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1157 case TargetLowering::Expand:
1158 //There is no libgcc call for this op
1159 Result = Node->getOperand(0); // Noop
1165 case ISD::ATOMIC_LCS:
1166 case ISD::ATOMIC_LAS:
1167 case ISD::ATOMIC_SWAP: {
1168 assert(((Node->getNumOperands() == 4 && Node->getOpcode() == ISD::ATOMIC_LCS) ||
1169 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_LAS) ||
1170 (Node->getNumOperands() == 3 && Node->getOpcode() == ISD::ATOMIC_SWAP)) &&
1171 "Invalid Atomic node!");
1172 int num = Node->getOpcode() == ISD::ATOMIC_LCS ? 4 : 3;
1174 for (int x = 0; x < num; ++x)
1175 Ops[x] = LegalizeOp(Node->getOperand(x));
1176 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num);
1178 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1179 default: assert(0 && "This action is not supported yet!");
1180 case TargetLowering::Custom:
1181 Result = TLI.LowerOperation(Result, DAG);
1183 case TargetLowering::Legal:
1186 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1187 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1188 return Result.getValue(Op.ResNo);
1191 case ISD::Constant: {
1192 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1194 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1196 // We know we don't need to expand constants here, constants only have one
1197 // value and we check that it is fine above.
1199 if (opAction == TargetLowering::Custom) {
1200 Tmp1 = TLI.LowerOperation(Result, DAG);
1206 case ISD::ConstantFP: {
1207 // Spill FP immediates to the constant pool if the target cannot directly
1208 // codegen them. Targets often have some immediate values that can be
1209 // efficiently generated into an FP register without a load. We explicitly
1210 // leave these constants as ConstantFP nodes for the target to deal with.
1211 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1213 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1214 default: assert(0 && "This action is not supported yet!");
1215 case TargetLowering::Legal:
1217 case TargetLowering::Custom:
1218 Tmp3 = TLI.LowerOperation(Result, DAG);
1224 case TargetLowering::Expand: {
1225 // Check to see if this FP immediate is already legal.
1226 bool isLegal = false;
1227 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1228 E = TLI.legal_fpimm_end(); I != E; ++I) {
1229 if (CFP->isExactlyValue(*I)) {
1234 // If this is a legal constant, turn it into a TargetConstantFP node.
1237 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1242 case ISD::TokenFactor:
1243 if (Node->getNumOperands() == 2) {
1244 Tmp1 = LegalizeOp(Node->getOperand(0));
1245 Tmp2 = LegalizeOp(Node->getOperand(1));
1246 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1247 } else if (Node->getNumOperands() == 3) {
1248 Tmp1 = LegalizeOp(Node->getOperand(0));
1249 Tmp2 = LegalizeOp(Node->getOperand(1));
1250 Tmp3 = LegalizeOp(Node->getOperand(2));
1251 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1253 SmallVector<SDOperand, 8> Ops;
1254 // Legalize the operands.
1255 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1256 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1257 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1261 case ISD::FORMAL_ARGUMENTS:
1263 // The only option for this is to custom lower it.
1264 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1265 assert(Tmp3.Val && "Target didn't custom lower this node!");
1267 // The number of incoming and outgoing values should match; unless the final
1268 // outgoing value is a flag.
1269 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1270 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1271 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1273 "Lowering call/formal_arguments produced unexpected # results!");
1275 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1276 // remember that we legalized all of them, so it doesn't get relegalized.
1277 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1278 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1280 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1283 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1286 case ISD::EXTRACT_SUBREG: {
1287 Tmp1 = LegalizeOp(Node->getOperand(0));
1288 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1289 assert(idx && "Operand must be a constant");
1290 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1291 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1294 case ISD::INSERT_SUBREG: {
1295 Tmp1 = LegalizeOp(Node->getOperand(0));
1296 Tmp2 = LegalizeOp(Node->getOperand(1));
1297 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1298 assert(idx && "Operand must be a constant");
1299 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1300 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1303 case ISD::BUILD_VECTOR:
1304 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1305 default: assert(0 && "This action is not supported yet!");
1306 case TargetLowering::Custom:
1307 Tmp3 = TLI.LowerOperation(Result, DAG);
1313 case TargetLowering::Expand:
1314 Result = ExpandBUILD_VECTOR(Result.Val);
1318 case ISD::INSERT_VECTOR_ELT:
1319 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1320 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1322 // The type of the value to insert may not be legal, even though the vector
1323 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1325 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1326 default: assert(0 && "Cannot expand insert element operand");
1327 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1328 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1330 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1332 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1333 Node->getValueType(0))) {
1334 default: assert(0 && "This action is not supported yet!");
1335 case TargetLowering::Legal:
1337 case TargetLowering::Custom:
1338 Tmp4 = TLI.LowerOperation(Result, DAG);
1344 case TargetLowering::Expand: {
1345 // If the insert index is a constant, codegen this as a scalar_to_vector,
1346 // then a shuffle that inserts it into the right position in the vector.
1347 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1348 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1349 // match the element type of the vector being created.
1350 if (Tmp2.getValueType() ==
1351 MVT::getVectorElementType(Op.getValueType())) {
1352 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1353 Tmp1.getValueType(), Tmp2);
1355 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1356 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1357 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1359 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1360 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1361 // elt 0 of the RHS.
1362 SmallVector<SDOperand, 8> ShufOps;
1363 for (unsigned i = 0; i != NumElts; ++i) {
1364 if (i != InsertPos->getValue())
1365 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1367 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1369 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1370 &ShufOps[0], ShufOps.size());
1372 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1373 Tmp1, ScVec, ShufMask);
1374 Result = LegalizeOp(Result);
1379 // If the target doesn't support this, we have to spill the input vector
1380 // to a temporary stack slot, update the element, then reload it. This is
1381 // badness. We could also load the value into a vector register (either
1382 // with a "move to register" or "extload into register" instruction, then
1383 // permute it into place, if the idx is a constant and if the idx is
1384 // supported by the target.
1385 MVT::ValueType VT = Tmp1.getValueType();
1386 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1387 MVT::ValueType IdxVT = Tmp3.getValueType();
1388 MVT::ValueType PtrVT = TLI.getPointerTy();
1389 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
1391 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
1392 int SPFI = StackPtrFI->getIndex();
1394 // Store the vector.
1395 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
1396 PseudoSourceValue::getFixedStack(),
1399 // Truncate or zero extend offset to target pointer type.
1400 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1401 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1402 // Add the offset to the index.
1403 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1404 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1405 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1406 // Store the scalar value.
1407 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
1408 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
1409 // Load the updated vector.
1410 Result = DAG.getLoad(VT, Ch, StackPtr,
1411 PseudoSourceValue::getFixedStack(), SPFI);
1416 case ISD::SCALAR_TO_VECTOR:
1417 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1418 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1422 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1423 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1424 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1425 Node->getValueType(0))) {
1426 default: assert(0 && "This action is not supported yet!");
1427 case TargetLowering::Legal:
1429 case TargetLowering::Custom:
1430 Tmp3 = TLI.LowerOperation(Result, DAG);
1436 case TargetLowering::Expand:
1437 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1441 case ISD::VECTOR_SHUFFLE:
1442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1443 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1444 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1446 // Allow targets to custom lower the SHUFFLEs they support.
1447 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1448 default: assert(0 && "Unknown operation action!");
1449 case TargetLowering::Legal:
1450 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1451 "vector shuffle should not be created if not legal!");
1453 case TargetLowering::Custom:
1454 Tmp3 = TLI.LowerOperation(Result, DAG);
1460 case TargetLowering::Expand: {
1461 MVT::ValueType VT = Node->getValueType(0);
1462 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1463 MVT::ValueType PtrVT = TLI.getPointerTy();
1464 SDOperand Mask = Node->getOperand(2);
1465 unsigned NumElems = Mask.getNumOperands();
1466 SmallVector<SDOperand,8> Ops;
1467 for (unsigned i = 0; i != NumElems; ++i) {
1468 SDOperand Arg = Mask.getOperand(i);
1469 if (Arg.getOpcode() == ISD::UNDEF) {
1470 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1472 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1473 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1475 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1476 DAG.getConstant(Idx, PtrVT)));
1478 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1479 DAG.getConstant(Idx - NumElems, PtrVT)));
1482 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1485 case TargetLowering::Promote: {
1486 // Change base type to a different vector type.
1487 MVT::ValueType OVT = Node->getValueType(0);
1488 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1490 // Cast the two input vectors.
1491 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1492 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1494 // Convert the shuffle mask to the right # elements.
1495 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1496 assert(Tmp3.Val && "Shuffle not legal?");
1497 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1498 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1504 case ISD::EXTRACT_VECTOR_ELT:
1505 Tmp1 = Node->getOperand(0);
1506 Tmp2 = LegalizeOp(Node->getOperand(1));
1507 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1508 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1511 case ISD::EXTRACT_SUBVECTOR:
1512 Tmp1 = Node->getOperand(0);
1513 Tmp2 = LegalizeOp(Node->getOperand(1));
1514 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1515 Result = ExpandEXTRACT_SUBVECTOR(Result);
1518 case ISD::CALLSEQ_START: {
1519 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1521 // Recursively Legalize all of the inputs of the call end that do not lead
1522 // to this call start. This ensures that any libcalls that need be inserted
1523 // are inserted *before* the CALLSEQ_START.
1524 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1525 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1526 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1530 // Now that we legalized all of the inputs (which may have inserted
1531 // libcalls) create the new CALLSEQ_START node.
1532 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1534 // Merge in the last call, to ensure that this call start after the last
1536 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1537 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1538 Tmp1 = LegalizeOp(Tmp1);
1541 // Do not try to legalize the target-specific arguments (#1+).
1542 if (Tmp1 != Node->getOperand(0)) {
1543 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1545 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1548 // Remember that the CALLSEQ_START is legalized.
1549 AddLegalizedOperand(Op.getValue(0), Result);
1550 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1551 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1553 // Now that the callseq_start and all of the non-call nodes above this call
1554 // sequence have been legalized, legalize the call itself. During this
1555 // process, no libcalls can/will be inserted, guaranteeing that no calls
1557 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1558 SDOperand InCallSEQ = LastCALLSEQ_END;
1559 // Note that we are selecting this call!
1560 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1561 IsLegalizingCall = true;
1563 // Legalize the call, starting from the CALLSEQ_END.
1564 LegalizeOp(LastCALLSEQ_END);
1565 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1568 case ISD::CALLSEQ_END:
1569 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1570 // will cause this node to be legalized as well as handling libcalls right.
1571 if (LastCALLSEQ_END.Val != Node) {
1572 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1573 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1574 assert(I != LegalizedNodes.end() &&
1575 "Legalizing the call start should have legalized this node!");
1579 // Otherwise, the call start has been legalized and everything is going
1580 // according to plan. Just legalize ourselves normally here.
1581 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1582 // Do not try to legalize the target-specific arguments (#1+), except for
1583 // an optional flag input.
1584 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1585 if (Tmp1 != Node->getOperand(0)) {
1586 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1588 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1591 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1592 if (Tmp1 != Node->getOperand(0) ||
1593 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1594 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1597 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1600 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1601 // This finishes up call legalization.
1602 IsLegalizingCall = false;
1604 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1605 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1606 if (Node->getNumValues() == 2)
1607 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1608 return Result.getValue(Op.ResNo);
1609 case ISD::DYNAMIC_STACKALLOC: {
1610 MVT::ValueType VT = Node->getValueType(0);
1611 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1612 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1613 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1614 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1616 Tmp1 = Result.getValue(0);
1617 Tmp2 = Result.getValue(1);
1618 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1619 default: assert(0 && "This action is not supported yet!");
1620 case TargetLowering::Expand: {
1621 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1622 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1623 " not tell us which reg is the stack pointer!");
1624 SDOperand Chain = Tmp1.getOperand(0);
1626 // Chain the dynamic stack allocation so that it doesn't modify the stack
1627 // pointer when other instructions are using the stack.
1628 Chain = DAG.getCALLSEQ_START(Chain,
1629 DAG.getConstant(0, TLI.getPointerTy()));
1631 SDOperand Size = Tmp2.getOperand(1);
1632 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1633 Chain = SP.getValue(1);
1634 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1635 unsigned StackAlign =
1636 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1637 if (Align > StackAlign)
1638 SP = DAG.getNode(ISD::AND, VT, SP,
1639 DAG.getConstant(-(uint64_t)Align, VT));
1640 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1641 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1644 DAG.getCALLSEQ_END(Chain,
1645 DAG.getConstant(0, TLI.getPointerTy()),
1646 DAG.getConstant(0, TLI.getPointerTy()),
1649 Tmp1 = LegalizeOp(Tmp1);
1650 Tmp2 = LegalizeOp(Tmp2);
1653 case TargetLowering::Custom:
1654 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1656 Tmp1 = LegalizeOp(Tmp3);
1657 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1660 case TargetLowering::Legal:
1663 // Since this op produce two values, make sure to remember that we
1664 // legalized both of them.
1665 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1666 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1667 return Op.ResNo ? Tmp2 : Tmp1;
1669 case ISD::INLINEASM: {
1670 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1671 bool Changed = false;
1672 // Legalize all of the operands of the inline asm, in case they are nodes
1673 // that need to be expanded or something. Note we skip the asm string and
1674 // all of the TargetConstant flags.
1675 SDOperand Op = LegalizeOp(Ops[0]);
1676 Changed = Op != Ops[0];
1679 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1680 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1681 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1682 for (++i; NumVals; ++i, --NumVals) {
1683 SDOperand Op = LegalizeOp(Ops[i]);
1692 Op = LegalizeOp(Ops.back());
1693 Changed |= Op != Ops.back();
1698 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1700 // INLINE asm returns a chain and flag, make sure to add both to the map.
1701 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1702 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1703 return Result.getValue(Op.ResNo);
1706 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1707 // Ensure that libcalls are emitted before a branch.
1708 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1709 Tmp1 = LegalizeOp(Tmp1);
1710 LastCALLSEQ_END = DAG.getEntryNode();
1712 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1715 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1716 // Ensure that libcalls are emitted before a branch.
1717 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1718 Tmp1 = LegalizeOp(Tmp1);
1719 LastCALLSEQ_END = DAG.getEntryNode();
1721 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1722 default: assert(0 && "Indirect target must be legal type (pointer)!");
1724 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1727 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1730 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1731 // Ensure that libcalls are emitted before a branch.
1732 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1733 Tmp1 = LegalizeOp(Tmp1);
1734 LastCALLSEQ_END = DAG.getEntryNode();
1736 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1737 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1739 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1740 default: assert(0 && "This action is not supported yet!");
1741 case TargetLowering::Legal: break;
1742 case TargetLowering::Custom:
1743 Tmp1 = TLI.LowerOperation(Result, DAG);
1744 if (Tmp1.Val) Result = Tmp1;
1746 case TargetLowering::Expand: {
1747 SDOperand Chain = Result.getOperand(0);
1748 SDOperand Table = Result.getOperand(1);
1749 SDOperand Index = Result.getOperand(2);
1751 MVT::ValueType PTy = TLI.getPointerTy();
1752 MachineFunction &MF = DAG.getMachineFunction();
1753 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1754 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1755 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1758 switch (EntrySize) {
1759 default: assert(0 && "Size of jump table not supported yet."); break;
1760 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1761 PseudoSourceValue::getJumpTable(), 0); break;
1762 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1763 PseudoSourceValue::getJumpTable(), 0); break;
1767 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1768 // For PIC, the sequence is:
1769 // BRIND(load(Jumptable + index) + RelocBase)
1770 // RelocBase can be JumpTable, GOT or some sort of global base.
1771 if (PTy != MVT::i32)
1772 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1773 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1774 TLI.getPICJumpTableRelocBase(Table, DAG));
1776 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1781 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1782 // Ensure that libcalls are emitted before a return.
1783 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1784 Tmp1 = LegalizeOp(Tmp1);
1785 LastCALLSEQ_END = DAG.getEntryNode();
1787 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1788 case Expand: assert(0 && "It's impossible to expand bools");
1790 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1793 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1795 // The top bits of the promoted condition are not necessarily zero, ensure
1796 // that the value is properly zero extended.
1797 unsigned BitWidth = Tmp2.getValueSizeInBits();
1798 if (!DAG.MaskedValueIsZero(Tmp2,
1799 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1800 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1805 // Basic block destination (Op#2) is always legal.
1806 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1808 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1809 default: assert(0 && "This action is not supported yet!");
1810 case TargetLowering::Legal: break;
1811 case TargetLowering::Custom:
1812 Tmp1 = TLI.LowerOperation(Result, DAG);
1813 if (Tmp1.Val) Result = Tmp1;
1815 case TargetLowering::Expand:
1816 // Expand brcond's setcc into its constituent parts and create a BR_CC
1818 if (Tmp2.getOpcode() == ISD::SETCC) {
1819 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1820 Tmp2.getOperand(0), Tmp2.getOperand(1),
1821 Node->getOperand(2));
1823 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1824 DAG.getCondCode(ISD::SETNE), Tmp2,
1825 DAG.getConstant(0, Tmp2.getValueType()),
1826 Node->getOperand(2));
1832 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1833 // Ensure that libcalls are emitted before a branch.
1834 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1835 Tmp1 = LegalizeOp(Tmp1);
1836 Tmp2 = Node->getOperand(2); // LHS
1837 Tmp3 = Node->getOperand(3); // RHS
1838 Tmp4 = Node->getOperand(1); // CC
1840 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1841 LastCALLSEQ_END = DAG.getEntryNode();
1843 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1844 // the LHS is a legal SETCC itself. In this case, we need to compare
1845 // the result against zero to select between true and false values.
1846 if (Tmp3.Val == 0) {
1847 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1848 Tmp4 = DAG.getCondCode(ISD::SETNE);
1851 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1852 Node->getOperand(4));
1854 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1855 default: assert(0 && "Unexpected action for BR_CC!");
1856 case TargetLowering::Legal: break;
1857 case TargetLowering::Custom:
1858 Tmp4 = TLI.LowerOperation(Result, DAG);
1859 if (Tmp4.Val) Result = Tmp4;
1864 LoadSDNode *LD = cast<LoadSDNode>(Node);
1865 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1866 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1868 ISD::LoadExtType ExtType = LD->getExtensionType();
1869 if (ExtType == ISD::NON_EXTLOAD) {
1870 MVT::ValueType VT = Node->getValueType(0);
1871 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1872 Tmp3 = Result.getValue(0);
1873 Tmp4 = Result.getValue(1);
1875 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1876 default: assert(0 && "This action is not supported yet!");
1877 case TargetLowering::Legal:
1878 // If this is an unaligned load and the target doesn't support it,
1880 if (!TLI.allowsUnalignedMemoryAccesses()) {
1881 unsigned ABIAlignment = TLI.getTargetData()->
1882 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1883 if (LD->getAlignment() < ABIAlignment){
1884 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1886 Tmp3 = Result.getOperand(0);
1887 Tmp4 = Result.getOperand(1);
1888 Tmp3 = LegalizeOp(Tmp3);
1889 Tmp4 = LegalizeOp(Tmp4);
1893 case TargetLowering::Custom:
1894 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1896 Tmp3 = LegalizeOp(Tmp1);
1897 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1900 case TargetLowering::Promote: {
1901 // Only promote a load of vector type to another.
1902 assert(MVT::isVector(VT) && "Cannot promote this load!");
1903 // Change base type to a different vector type.
1904 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1906 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1907 LD->getSrcValueOffset(),
1908 LD->isVolatile(), LD->getAlignment());
1909 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1910 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1914 // Since loads produce two values, make sure to remember that we
1915 // legalized both of them.
1916 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1917 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1918 return Op.ResNo ? Tmp4 : Tmp3;
1920 MVT::ValueType SrcVT = LD->getMemoryVT();
1921 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1922 int SVOffset = LD->getSrcValueOffset();
1923 unsigned Alignment = LD->getAlignment();
1924 bool isVolatile = LD->isVolatile();
1926 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
1927 // Some targets pretend to have an i1 loading operation, and actually
1928 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1929 // bits are guaranteed to be zero; it helps the optimizers understand
1930 // that these bits are zero. It is also useful for EXTLOAD, since it
1931 // tells the optimizers that those bits are undefined. It would be
1932 // nice to have an effective generic way of getting these benefits...
1933 // Until such a way is found, don't insist on promoting i1 here.
1934 (SrcVT != MVT::i1 ||
1935 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1936 // Promote to a byte-sized load if not loading an integral number of
1937 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1938 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
1939 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
1942 // The extra bits are guaranteed to be zero, since we stored them that
1943 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1945 ISD::LoadExtType NewExtType =
1946 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1948 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
1949 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1950 NVT, isVolatile, Alignment);
1952 Ch = Result.getValue(1); // The chain.
1954 if (ExtType == ISD::SEXTLOAD)
1955 // Having the top bits zero doesn't help when sign extending.
1956 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1957 Result, DAG.getValueType(SrcVT));
1958 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1959 // All the top bits are guaranteed to be zero - inform the optimizers.
1960 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
1961 DAG.getValueType(SrcVT));
1963 Tmp1 = LegalizeOp(Result);
1964 Tmp2 = LegalizeOp(Ch);
1965 } else if (SrcWidth & (SrcWidth - 1)) {
1966 // If not loading a power-of-2 number of bits, expand as two loads.
1967 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
1968 "Unsupported extload!");
1969 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1970 assert(RoundWidth < SrcWidth);
1971 unsigned ExtraWidth = SrcWidth - RoundWidth;
1972 assert(ExtraWidth < RoundWidth);
1973 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1974 "Load size not an integral number of bytes!");
1975 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
1976 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
1977 SDOperand Lo, Hi, Ch;
1978 unsigned IncrementSize;
1980 if (TLI.isLittleEndian()) {
1981 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1982 // Load the bottom RoundWidth bits.
1983 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
1984 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1987 // Load the remaining ExtraWidth bits.
1988 IncrementSize = RoundWidth / 8;
1989 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1990 DAG.getIntPtrConstant(IncrementSize));
1991 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1992 LD->getSrcValue(), SVOffset + IncrementSize,
1993 ExtraVT, isVolatile,
1994 MinAlign(Alignment, IncrementSize));
1996 // Build a factor node to remember that this load is independent of the
1998 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2001 // Move the top bits to the right place.
2002 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2003 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2005 // Join the hi and lo parts.
2006 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2008 // Big endian - avoid unaligned loads.
2009 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2010 // Load the top RoundWidth bits.
2011 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2012 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2015 // Load the remaining ExtraWidth bits.
2016 IncrementSize = RoundWidth / 8;
2017 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2018 DAG.getIntPtrConstant(IncrementSize));
2019 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2020 LD->getSrcValue(), SVOffset + IncrementSize,
2021 ExtraVT, isVolatile,
2022 MinAlign(Alignment, IncrementSize));
2024 // Build a factor node to remember that this load is independent of the
2026 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2029 // Move the top bits to the right place.
2030 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2031 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2033 // Join the hi and lo parts.
2034 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2037 Tmp1 = LegalizeOp(Result);
2038 Tmp2 = LegalizeOp(Ch);
2040 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2041 default: assert(0 && "This action is not supported yet!");
2042 case TargetLowering::Custom:
2045 case TargetLowering::Legal:
2046 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2047 Tmp1 = Result.getValue(0);
2048 Tmp2 = Result.getValue(1);
2051 Tmp3 = TLI.LowerOperation(Result, DAG);
2053 Tmp1 = LegalizeOp(Tmp3);
2054 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2057 // If this is an unaligned load and the target doesn't support it,
2059 if (!TLI.allowsUnalignedMemoryAccesses()) {
2060 unsigned ABIAlignment = TLI.getTargetData()->
2061 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2062 if (LD->getAlignment() < ABIAlignment){
2063 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2065 Tmp1 = Result.getOperand(0);
2066 Tmp2 = Result.getOperand(1);
2067 Tmp1 = LegalizeOp(Tmp1);
2068 Tmp2 = LegalizeOp(Tmp2);
2073 case TargetLowering::Expand:
2074 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2075 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2076 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2077 LD->getSrcValueOffset(),
2078 LD->isVolatile(), LD->getAlignment());
2079 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2080 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2081 Tmp2 = LegalizeOp(Load.getValue(1));
2084 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2085 // Turn the unsupported load into an EXTLOAD followed by an explicit
2086 // zero/sign extend inreg.
2087 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2088 Tmp1, Tmp2, LD->getSrcValue(),
2089 LD->getSrcValueOffset(), SrcVT,
2090 LD->isVolatile(), LD->getAlignment());
2092 if (ExtType == ISD::SEXTLOAD)
2093 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2094 Result, DAG.getValueType(SrcVT));
2096 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2097 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2098 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2103 // Since loads produce two values, make sure to remember that we legalized
2105 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2106 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2107 return Op.ResNo ? Tmp2 : Tmp1;
2110 case ISD::EXTRACT_ELEMENT: {
2111 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2112 switch (getTypeAction(OpTy)) {
2113 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2115 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2117 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2118 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2119 TLI.getShiftAmountTy()));
2120 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2123 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2124 Node->getOperand(0));
2128 // Get both the low and high parts.
2129 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2130 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2131 Result = Tmp2; // 1 -> Hi
2133 Result = Tmp1; // 0 -> Lo
2139 case ISD::CopyToReg:
2140 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2142 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2143 "Register type must be legal!");
2144 // Legalize the incoming value (must be a legal type).
2145 Tmp2 = LegalizeOp(Node->getOperand(2));
2146 if (Node->getNumValues() == 1) {
2147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2149 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2150 if (Node->getNumOperands() == 4) {
2151 Tmp3 = LegalizeOp(Node->getOperand(3));
2152 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2155 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2158 // Since this produces two values, make sure to remember that we legalized
2160 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2161 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2167 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2169 // Ensure that libcalls are emitted before a return.
2170 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2171 Tmp1 = LegalizeOp(Tmp1);
2172 LastCALLSEQ_END = DAG.getEntryNode();
2174 switch (Node->getNumOperands()) {
2176 Tmp2 = Node->getOperand(1);
2177 Tmp3 = Node->getOperand(2); // Signness
2178 switch (getTypeAction(Tmp2.getValueType())) {
2180 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2183 if (!MVT::isVector(Tmp2.getValueType())) {
2185 ExpandOp(Tmp2, Lo, Hi);
2187 // Big endian systems want the hi reg first.
2188 if (TLI.isBigEndian())
2192 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2194 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2195 Result = LegalizeOp(Result);
2197 SDNode *InVal = Tmp2.Val;
2198 int InIx = Tmp2.ResNo;
2199 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2200 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2202 // Figure out if there is a simple type corresponding to this Vector
2203 // type. If so, convert to the vector type.
2204 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2205 if (TLI.isTypeLegal(TVT)) {
2206 // Turn this into a return of the vector type.
2207 Tmp2 = LegalizeOp(Tmp2);
2208 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2209 } else if (NumElems == 1) {
2210 // Turn this into a return of the scalar type.
2211 Tmp2 = ScalarizeVectorOp(Tmp2);
2212 Tmp2 = LegalizeOp(Tmp2);
2213 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2215 // FIXME: Returns of gcc generic vectors smaller than a legal type
2216 // should be returned in integer registers!
2218 // The scalarized value type may not be legal, e.g. it might require
2219 // promotion or expansion. Relegalize the return.
2220 Result = LegalizeOp(Result);
2222 // FIXME: Returns of gcc generic vectors larger than a legal vector
2223 // type should be returned by reference!
2225 SplitVectorOp(Tmp2, Lo, Hi);
2226 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2227 Result = LegalizeOp(Result);
2232 Tmp2 = PromoteOp(Node->getOperand(1));
2233 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2234 Result = LegalizeOp(Result);
2239 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2241 default: { // ret <values>
2242 SmallVector<SDOperand, 8> NewValues;
2243 NewValues.push_back(Tmp1);
2244 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2245 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2247 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2248 NewValues.push_back(Node->getOperand(i+1));
2252 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2253 "FIXME: TODO: implement returning non-legal vector types!");
2254 ExpandOp(Node->getOperand(i), Lo, Hi);
2255 NewValues.push_back(Lo);
2256 NewValues.push_back(Node->getOperand(i+1));
2258 NewValues.push_back(Hi);
2259 NewValues.push_back(Node->getOperand(i+1));
2264 assert(0 && "Can't promote multiple return value yet!");
2267 if (NewValues.size() == Node->getNumOperands())
2268 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2270 Result = DAG.getNode(ISD::RET, MVT::Other,
2271 &NewValues[0], NewValues.size());
2276 if (Result.getOpcode() == ISD::RET) {
2277 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2278 default: assert(0 && "This action is not supported yet!");
2279 case TargetLowering::Legal: break;
2280 case TargetLowering::Custom:
2281 Tmp1 = TLI.LowerOperation(Result, DAG);
2282 if (Tmp1.Val) Result = Tmp1;
2288 StoreSDNode *ST = cast<StoreSDNode>(Node);
2289 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2290 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2291 int SVOffset = ST->getSrcValueOffset();
2292 unsigned Alignment = ST->getAlignment();
2293 bool isVolatile = ST->isVolatile();
2295 if (!ST->isTruncatingStore()) {
2296 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2297 // FIXME: We shouldn't do this for TargetConstantFP's.
2298 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2299 // to phase ordering between legalized code and the dag combiner. This
2300 // probably means that we need to integrate dag combiner and legalizer
2302 // We generally can't do this one for long doubles.
2303 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2304 if (CFP->getValueType(0) == MVT::f32 &&
2305 getTypeAction(MVT::i32) == Legal) {
2306 Tmp3 = DAG.getConstant((uint32_t)CFP->getValueAPF().
2307 convertToAPInt().getZExtValue(),
2309 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2310 SVOffset, isVolatile, Alignment);
2312 } else if (CFP->getValueType(0) == MVT::f64) {
2313 // If this target supports 64-bit registers, do a single 64-bit store.
2314 if (getTypeAction(MVT::i64) == Legal) {
2315 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2316 getZExtValue(), MVT::i64);
2317 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2318 SVOffset, isVolatile, Alignment);
2320 } else if (getTypeAction(MVT::i32) == Legal) {
2321 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2322 // stores. If the target supports neither 32- nor 64-bits, this
2323 // xform is certainly not worth it.
2324 uint64_t IntVal =CFP->getValueAPF().convertToAPInt().getZExtValue();
2325 SDOperand Lo = DAG.getConstant(uint32_t(IntVal), MVT::i32);
2326 SDOperand Hi = DAG.getConstant(uint32_t(IntVal >>32), MVT::i32);
2327 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2329 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2330 SVOffset, isVolatile, Alignment);
2331 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2332 DAG.getIntPtrConstant(4));
2333 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2334 isVolatile, MinAlign(Alignment, 4U));
2336 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2342 switch (getTypeAction(ST->getMemoryVT())) {
2344 Tmp3 = LegalizeOp(ST->getValue());
2345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2348 MVT::ValueType VT = Tmp3.getValueType();
2349 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2350 default: assert(0 && "This action is not supported yet!");
2351 case TargetLowering::Legal:
2352 // If this is an unaligned store and the target doesn't support it,
2354 if (!TLI.allowsUnalignedMemoryAccesses()) {
2355 unsigned ABIAlignment = TLI.getTargetData()->
2356 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2357 if (ST->getAlignment() < ABIAlignment)
2358 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2362 case TargetLowering::Custom:
2363 Tmp1 = TLI.LowerOperation(Result, DAG);
2364 if (Tmp1.Val) Result = Tmp1;
2366 case TargetLowering::Promote:
2367 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2368 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2369 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2370 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2371 ST->getSrcValue(), SVOffset, isVolatile,
2378 // Truncate the value and store the result.
2379 Tmp3 = PromoteOp(ST->getValue());
2380 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2381 SVOffset, ST->getMemoryVT(),
2382 isVolatile, Alignment);
2386 unsigned IncrementSize = 0;
2389 // If this is a vector type, then we have to calculate the increment as
2390 // the product of the element size in bytes, and the number of elements
2391 // in the high half of the vector.
2392 if (MVT::isVector(ST->getValue().getValueType())) {
2393 SDNode *InVal = ST->getValue().Val;
2394 int InIx = ST->getValue().ResNo;
2395 MVT::ValueType InVT = InVal->getValueType(InIx);
2396 unsigned NumElems = MVT::getVectorNumElements(InVT);
2397 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2399 // Figure out if there is a simple type corresponding to this Vector
2400 // type. If so, convert to the vector type.
2401 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2402 if (TLI.isTypeLegal(TVT)) {
2403 // Turn this into a normal store of the vector type.
2404 Tmp3 = LegalizeOp(ST->getValue());
2405 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2406 SVOffset, isVolatile, Alignment);
2407 Result = LegalizeOp(Result);
2409 } else if (NumElems == 1) {
2410 // Turn this into a normal store of the scalar type.
2411 Tmp3 = ScalarizeVectorOp(ST->getValue());
2412 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2413 SVOffset, isVolatile, Alignment);
2414 // The scalarized value type may not be legal, e.g. it might require
2415 // promotion or expansion. Relegalize the scalar store.
2416 Result = LegalizeOp(Result);
2419 SplitVectorOp(ST->getValue(), Lo, Hi);
2420 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2421 MVT::getSizeInBits(EVT)/8;
2424 ExpandOp(ST->getValue(), Lo, Hi);
2425 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2427 if (TLI.isBigEndian())
2431 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2432 SVOffset, isVolatile, Alignment);
2434 if (Hi.Val == NULL) {
2435 // Must be int <-> float one-to-one expansion.
2440 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2441 DAG.getIntPtrConstant(IncrementSize));
2442 assert(isTypeLegal(Tmp2.getValueType()) &&
2443 "Pointers must be legal!");
2444 SVOffset += IncrementSize;
2445 Alignment = MinAlign(Alignment, IncrementSize);
2446 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2447 SVOffset, isVolatile, Alignment);
2448 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2452 switch (getTypeAction(ST->getValue().getValueType())) {
2454 Tmp3 = LegalizeOp(ST->getValue());
2457 // We can promote the value, the truncstore will still take care of it.
2458 Tmp3 = PromoteOp(ST->getValue());
2461 // Just store the low part. This may become a non-trunc store, so make
2462 // sure to use getTruncStore, not UpdateNodeOperands below.
2463 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2464 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2465 SVOffset, MVT::i8, isVolatile, Alignment);
2468 MVT::ValueType StVT = ST->getMemoryVT();
2469 unsigned StWidth = MVT::getSizeInBits(StVT);
2471 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2472 // Promote to a byte-sized store with upper bits zero if not
2473 // storing an integral number of bytes. For example, promote
2474 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2475 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2476 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2477 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2478 SVOffset, NVT, isVolatile, Alignment);
2479 } else if (StWidth & (StWidth - 1)) {
2480 // If not storing a power-of-2 number of bits, expand as two stores.
2481 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2482 "Unsupported truncstore!");
2483 unsigned RoundWidth = 1 << Log2_32(StWidth);
2484 assert(RoundWidth < StWidth);
2485 unsigned ExtraWidth = StWidth - RoundWidth;
2486 assert(ExtraWidth < RoundWidth);
2487 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2488 "Store size not an integral number of bytes!");
2489 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2490 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2492 unsigned IncrementSize;
2494 if (TLI.isLittleEndian()) {
2495 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2496 // Store the bottom RoundWidth bits.
2497 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2499 isVolatile, Alignment);
2501 // Store the remaining ExtraWidth bits.
2502 IncrementSize = RoundWidth / 8;
2503 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2504 DAG.getIntPtrConstant(IncrementSize));
2505 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2506 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2507 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2508 SVOffset + IncrementSize, ExtraVT, isVolatile,
2509 MinAlign(Alignment, IncrementSize));
2511 // Big endian - avoid unaligned stores.
2512 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2513 // Store the top RoundWidth bits.
2514 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2515 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2516 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2517 RoundVT, isVolatile, Alignment);
2519 // Store the remaining ExtraWidth bits.
2520 IncrementSize = RoundWidth / 8;
2521 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2522 DAG.getIntPtrConstant(IncrementSize));
2523 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2524 SVOffset + IncrementSize, ExtraVT, isVolatile,
2525 MinAlign(Alignment, IncrementSize));
2528 // The order of the stores doesn't matter.
2529 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2531 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2532 Tmp2 != ST->getBasePtr())
2533 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2536 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2537 default: assert(0 && "This action is not supported yet!");
2538 case TargetLowering::Legal:
2539 // If this is an unaligned store and the target doesn't support it,
2541 if (!TLI.allowsUnalignedMemoryAccesses()) {
2542 unsigned ABIAlignment = TLI.getTargetData()->
2543 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2544 if (ST->getAlignment() < ABIAlignment)
2545 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2549 case TargetLowering::Custom:
2550 Result = TLI.LowerOperation(Result, DAG);
2553 // TRUNCSTORE:i16 i32 -> STORE i16
2554 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2555 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2556 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2557 isVolatile, Alignment);
2565 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2566 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2568 case ISD::STACKSAVE:
2569 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2570 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2571 Tmp1 = Result.getValue(0);
2572 Tmp2 = Result.getValue(1);
2574 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2575 default: assert(0 && "This action is not supported yet!");
2576 case TargetLowering::Legal: break;
2577 case TargetLowering::Custom:
2578 Tmp3 = TLI.LowerOperation(Result, DAG);
2580 Tmp1 = LegalizeOp(Tmp3);
2581 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2584 case TargetLowering::Expand:
2585 // Expand to CopyFromReg if the target set
2586 // StackPointerRegisterToSaveRestore.
2587 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2588 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2589 Node->getValueType(0));
2590 Tmp2 = Tmp1.getValue(1);
2592 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2593 Tmp2 = Node->getOperand(0);
2598 // Since stacksave produce two values, make sure to remember that we
2599 // legalized both of them.
2600 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2601 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2602 return Op.ResNo ? Tmp2 : Tmp1;
2604 case ISD::STACKRESTORE:
2605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2606 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2607 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2609 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2610 default: assert(0 && "This action is not supported yet!");
2611 case TargetLowering::Legal: break;
2612 case TargetLowering::Custom:
2613 Tmp1 = TLI.LowerOperation(Result, DAG);
2614 if (Tmp1.Val) Result = Tmp1;
2616 case TargetLowering::Expand:
2617 // Expand to CopyToReg if the target set
2618 // StackPointerRegisterToSaveRestore.
2619 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2620 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2628 case ISD::READCYCLECOUNTER:
2629 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2630 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2631 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2632 Node->getValueType(0))) {
2633 default: assert(0 && "This action is not supported yet!");
2634 case TargetLowering::Legal:
2635 Tmp1 = Result.getValue(0);
2636 Tmp2 = Result.getValue(1);
2638 case TargetLowering::Custom:
2639 Result = TLI.LowerOperation(Result, DAG);
2640 Tmp1 = LegalizeOp(Result.getValue(0));
2641 Tmp2 = LegalizeOp(Result.getValue(1));
2645 // Since rdcc produce two values, make sure to remember that we legalized
2647 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2648 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2652 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2653 case Expand: assert(0 && "It's impossible to expand bools");
2655 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2658 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2659 // Make sure the condition is either zero or one.
2660 unsigned BitWidth = Tmp1.getValueSizeInBits();
2661 if (!DAG.MaskedValueIsZero(Tmp1,
2662 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2663 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2667 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2668 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2670 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2672 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2673 default: assert(0 && "This action is not supported yet!");
2674 case TargetLowering::Legal: break;
2675 case TargetLowering::Custom: {
2676 Tmp1 = TLI.LowerOperation(Result, DAG);
2677 if (Tmp1.Val) Result = Tmp1;
2680 case TargetLowering::Expand:
2681 if (Tmp1.getOpcode() == ISD::SETCC) {
2682 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2684 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2686 Result = DAG.getSelectCC(Tmp1,
2687 DAG.getConstant(0, Tmp1.getValueType()),
2688 Tmp2, Tmp3, ISD::SETNE);
2691 case TargetLowering::Promote: {
2692 MVT::ValueType NVT =
2693 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2694 unsigned ExtOp, TruncOp;
2695 if (MVT::isVector(Tmp2.getValueType())) {
2696 ExtOp = ISD::BIT_CONVERT;
2697 TruncOp = ISD::BIT_CONVERT;
2698 } else if (MVT::isInteger(Tmp2.getValueType())) {
2699 ExtOp = ISD::ANY_EXTEND;
2700 TruncOp = ISD::TRUNCATE;
2702 ExtOp = ISD::FP_EXTEND;
2703 TruncOp = ISD::FP_ROUND;
2705 // Promote each of the values to the new type.
2706 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2707 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2708 // Perform the larger operation, then round down.
2709 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2710 if (TruncOp != ISD::FP_ROUND)
2711 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2713 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2714 DAG.getIntPtrConstant(0));
2719 case ISD::SELECT_CC: {
2720 Tmp1 = Node->getOperand(0); // LHS
2721 Tmp2 = Node->getOperand(1); // RHS
2722 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2723 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2724 SDOperand CC = Node->getOperand(4);
2726 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2728 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2729 // the LHS is a legal SETCC itself. In this case, we need to compare
2730 // the result against zero to select between true and false values.
2731 if (Tmp2.Val == 0) {
2732 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2733 CC = DAG.getCondCode(ISD::SETNE);
2735 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2737 // Everything is legal, see if we should expand this op or something.
2738 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2739 default: assert(0 && "This action is not supported yet!");
2740 case TargetLowering::Legal: break;
2741 case TargetLowering::Custom:
2742 Tmp1 = TLI.LowerOperation(Result, DAG);
2743 if (Tmp1.Val) Result = Tmp1;
2749 Tmp1 = Node->getOperand(0);
2750 Tmp2 = Node->getOperand(1);
2751 Tmp3 = Node->getOperand(2);
2752 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2754 // If we had to Expand the SetCC operands into a SELECT node, then it may
2755 // not always be possible to return a true LHS & RHS. In this case, just
2756 // return the value we legalized, returned in the LHS
2757 if (Tmp2.Val == 0) {
2762 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2763 default: assert(0 && "Cannot handle this action for SETCC yet!");
2764 case TargetLowering::Custom:
2767 case TargetLowering::Legal:
2768 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2770 Tmp4 = TLI.LowerOperation(Result, DAG);
2771 if (Tmp4.Val) Result = Tmp4;
2774 case TargetLowering::Promote: {
2775 // First step, figure out the appropriate operation to use.
2776 // Allow SETCC to not be supported for all legal data types
2777 // Mostly this targets FP
2778 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2779 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2781 // Scan for the appropriate larger type to use.
2783 NewInTy = (MVT::ValueType)(NewInTy+1);
2785 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2786 "Fell off of the edge of the integer world");
2787 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2788 "Fell off of the edge of the floating point world");
2790 // If the target supports SETCC of this type, use it.
2791 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2794 if (MVT::isInteger(NewInTy))
2795 assert(0 && "Cannot promote Legal Integer SETCC yet");
2797 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2798 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2800 Tmp1 = LegalizeOp(Tmp1);
2801 Tmp2 = LegalizeOp(Tmp2);
2802 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2803 Result = LegalizeOp(Result);
2806 case TargetLowering::Expand:
2807 // Expand a setcc node into a select_cc of the same condition, lhs, and
2808 // rhs that selects between const 1 (true) and const 0 (false).
2809 MVT::ValueType VT = Node->getValueType(0);
2810 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2811 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2818 case ISD::MEMMOVE: {
2819 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2820 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2822 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2823 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2824 case Expand: assert(0 && "Cannot expand a byte!");
2826 Tmp3 = LegalizeOp(Node->getOperand(2));
2829 Tmp3 = PromoteOp(Node->getOperand(2));
2833 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2837 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2839 // Length is too big, just take the lo-part of the length.
2841 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2845 Tmp4 = LegalizeOp(Node->getOperand(3));
2848 Tmp4 = PromoteOp(Node->getOperand(3));
2853 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2854 case Expand: assert(0 && "Cannot expand this yet!");
2856 Tmp5 = LegalizeOp(Node->getOperand(4));
2859 Tmp5 = PromoteOp(Node->getOperand(4));
2864 switch (getTypeAction(Node->getOperand(5).getValueType())) { // bool
2865 case Expand: assert(0 && "Cannot expand this yet!");
2867 Tmp6 = LegalizeOp(Node->getOperand(5));
2870 Tmp6 = PromoteOp(Node->getOperand(5));
2874 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2875 default: assert(0 && "This action not implemented for this operation!");
2876 case TargetLowering::Custom:
2879 case TargetLowering::Legal: {
2880 SDOperand Ops[] = { Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6 };
2881 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
2883 Tmp1 = TLI.LowerOperation(Result, DAG);
2884 if (Tmp1.Val) Result = Tmp1;
2888 case TargetLowering::Expand: {
2889 // Otherwise, the target does not support this operation. Lower the
2890 // operation to an explicit libcall as appropriate.
2891 MVT::ValueType IntPtr = TLI.getPointerTy();
2892 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2893 TargetLowering::ArgListTy Args;
2894 TargetLowering::ArgListEntry Entry;
2896 const char *FnName = 0;
2897 if (Node->getOpcode() == ISD::MEMSET) {
2898 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2899 Args.push_back(Entry);
2900 // Extend the (previously legalized) ubyte argument to be an int value
2902 if (Tmp3.getValueType() > MVT::i32)
2903 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2905 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2906 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2907 Args.push_back(Entry);
2908 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2909 Args.push_back(Entry);
2912 } else if (Node->getOpcode() == ISD::MEMCPY ||
2913 Node->getOpcode() == ISD::MEMMOVE) {
2914 Entry.Ty = IntPtrTy;
2915 Entry.Node = Tmp2; Args.push_back(Entry);
2916 Entry.Node = Tmp3; Args.push_back(Entry);
2917 Entry.Node = Tmp4; Args.push_back(Entry);
2918 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2920 assert(0 && "Unknown op!");
2923 std::pair<SDOperand,SDOperand> CallResult =
2924 TLI.LowerCallTo(Tmp1, Type::VoidTy,
2925 false, false, false, CallingConv::C, false,
2926 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2927 Result = CallResult.second;
2934 case ISD::SHL_PARTS:
2935 case ISD::SRA_PARTS:
2936 case ISD::SRL_PARTS: {
2937 SmallVector<SDOperand, 8> Ops;
2938 bool Changed = false;
2939 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2940 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2941 Changed |= Ops.back() != Node->getOperand(i);
2944 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2946 switch (TLI.getOperationAction(Node->getOpcode(),
2947 Node->getValueType(0))) {
2948 default: assert(0 && "This action is not supported yet!");
2949 case TargetLowering::Legal: break;
2950 case TargetLowering::Custom:
2951 Tmp1 = TLI.LowerOperation(Result, DAG);
2953 SDOperand Tmp2, RetVal(0, 0);
2954 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2955 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2956 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2960 assert(RetVal.Val && "Illegal result number");
2966 // Since these produce multiple values, make sure to remember that we
2967 // legalized all of them.
2968 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2969 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2970 return Result.getValue(Op.ResNo);
2992 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2993 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2994 case Expand: assert(0 && "Not possible");
2996 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2999 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3003 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3005 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3006 default: assert(0 && "BinOp legalize operation not supported");
3007 case TargetLowering::Legal: break;
3008 case TargetLowering::Custom:
3009 Tmp1 = TLI.LowerOperation(Result, DAG);
3010 if (Tmp1.Val) Result = Tmp1;
3012 case TargetLowering::Expand: {
3013 MVT::ValueType VT = Op.getValueType();
3015 // See if multiply or divide can be lowered using two-result operations.
3016 SDVTList VTs = DAG.getVTList(VT, VT);
3017 if (Node->getOpcode() == ISD::MUL) {
3018 // We just need the low half of the multiply; try both the signed
3019 // and unsigned forms. If the target supports both SMUL_LOHI and
3020 // UMUL_LOHI, form a preference by checking which forms of plain
3021 // MULH it supports.
3022 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3023 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3024 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3025 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3026 unsigned OpToUse = 0;
3027 if (HasSMUL_LOHI && !HasMULHS) {
3028 OpToUse = ISD::SMUL_LOHI;
3029 } else if (HasUMUL_LOHI && !HasMULHU) {
3030 OpToUse = ISD::UMUL_LOHI;
3031 } else if (HasSMUL_LOHI) {
3032 OpToUse = ISD::SMUL_LOHI;
3033 } else if (HasUMUL_LOHI) {
3034 OpToUse = ISD::UMUL_LOHI;
3037 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
3041 if (Node->getOpcode() == ISD::MULHS &&
3042 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3043 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3046 if (Node->getOpcode() == ISD::MULHU &&
3047 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3048 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3051 if (Node->getOpcode() == ISD::SDIV &&
3052 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3053 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3056 if (Node->getOpcode() == ISD::UDIV &&
3057 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3058 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3062 // Check to see if we have a libcall for this operator.
3063 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3064 bool isSigned = false;
3065 switch (Node->getOpcode()) {
3068 if (VT == MVT::i32) {
3069 LC = Node->getOpcode() == ISD::UDIV
3070 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3071 isSigned = Node->getOpcode() == ISD::SDIV;
3075 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3076 RTLIB::POW_PPCF128);
3080 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3082 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3086 assert(MVT::isVector(Node->getValueType(0)) &&
3087 "Cannot expand this binary operator!");
3088 // Expand the operation into a bunch of nasty scalar code.
3089 Result = LegalizeOp(UnrollVectorOp(Op));
3092 case TargetLowering::Promote: {
3093 switch (Node->getOpcode()) {
3094 default: assert(0 && "Do not know how to promote this BinOp!");
3098 MVT::ValueType OVT = Node->getValueType(0);
3099 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3100 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3101 // Bit convert each of the values to the new type.
3102 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3103 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3104 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3105 // Bit convert the result back the original type.
3106 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3114 case ISD::SMUL_LOHI:
3115 case ISD::UMUL_LOHI:
3118 // These nodes will only be produced by target-specific lowering, so
3119 // they shouldn't be here if they aren't legal.
3120 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3121 "This must be legal!");
3123 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3124 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3125 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3128 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3129 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3130 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3131 case Expand: assert(0 && "Not possible");
3133 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3136 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3140 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3142 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3143 default: assert(0 && "Operation not supported");
3144 case TargetLowering::Custom:
3145 Tmp1 = TLI.LowerOperation(Result, DAG);
3146 if (Tmp1.Val) Result = Tmp1;
3148 case TargetLowering::Legal: break;
3149 case TargetLowering::Expand: {
3150 // If this target supports fabs/fneg natively and select is cheap,
3151 // do this efficiently.
3152 if (!TLI.isSelectExpensive() &&
3153 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3154 TargetLowering::Legal &&
3155 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3156 TargetLowering::Legal) {
3157 // Get the sign bit of the RHS.
3158 MVT::ValueType IVT =
3159 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3160 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3161 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
3162 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3163 // Get the absolute value of the result.
3164 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3165 // Select between the nabs and abs value based on the sign bit of
3167 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3168 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3171 Result = LegalizeOp(Result);
3175 // Otherwise, do bitwise ops!
3176 MVT::ValueType NVT =
3177 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3178 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3179 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3180 Result = LegalizeOp(Result);
3188 Tmp1 = LegalizeOp(Node->getOperand(0));
3189 Tmp2 = LegalizeOp(Node->getOperand(1));
3190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3191 // Since this produces two values, make sure to remember that we legalized
3193 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3194 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3199 Tmp1 = LegalizeOp(Node->getOperand(0));
3200 Tmp2 = LegalizeOp(Node->getOperand(1));
3201 Tmp3 = LegalizeOp(Node->getOperand(2));
3202 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3203 // Since this produces two values, make sure to remember that we legalized
3205 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3206 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3209 case ISD::BUILD_PAIR: {
3210 MVT::ValueType PairTy = Node->getValueType(0);
3211 // TODO: handle the case where the Lo and Hi operands are not of legal type
3212 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3213 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3214 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3215 case TargetLowering::Promote:
3216 case TargetLowering::Custom:
3217 assert(0 && "Cannot promote/custom this yet!");
3218 case TargetLowering::Legal:
3219 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3220 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3222 case TargetLowering::Expand:
3223 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3224 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3225 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3226 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3227 TLI.getShiftAmountTy()));
3228 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3237 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3238 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3240 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3241 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3242 case TargetLowering::Custom:
3245 case TargetLowering::Legal:
3246 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3248 Tmp1 = TLI.LowerOperation(Result, DAG);
3249 if (Tmp1.Val) Result = Tmp1;
3252 case TargetLowering::Expand: {
3253 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3254 bool isSigned = DivOpc == ISD::SDIV;
3255 MVT::ValueType VT = Node->getValueType(0);
3257 // See if remainder can be lowered using two-result operations.
3258 SDVTList VTs = DAG.getVTList(VT, VT);
3259 if (Node->getOpcode() == ISD::SREM &&
3260 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3261 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3264 if (Node->getOpcode() == ISD::UREM &&
3265 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3266 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3270 if (MVT::isInteger(VT)) {
3271 if (TLI.getOperationAction(DivOpc, VT) ==
3272 TargetLowering::Legal) {
3274 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3275 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3276 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3277 } else if (MVT::isVector(VT)) {
3278 Result = LegalizeOp(UnrollVectorOp(Op));
3280 assert(VT == MVT::i32 &&
3281 "Cannot expand this binary operator!");
3282 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3283 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3285 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
3288 assert(MVT::isFloatingPoint(VT) &&
3289 "remainder op must have integer or floating-point type");
3290 if (MVT::isVector(VT)) {
3291 Result = LegalizeOp(UnrollVectorOp(Op));
3293 // Floating point mod -> fmod libcall.
3294 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3295 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3297 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3298 false/*sign irrelevant*/, Dummy);
3306 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3307 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3309 MVT::ValueType VT = Node->getValueType(0);
3310 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3311 default: assert(0 && "This action is not supported yet!");
3312 case TargetLowering::Custom:
3315 case TargetLowering::Legal:
3316 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3317 Result = Result.getValue(0);
3318 Tmp1 = Result.getValue(1);
3321 Tmp2 = TLI.LowerOperation(Result, DAG);
3323 Result = LegalizeOp(Tmp2);
3324 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3328 case TargetLowering::Expand: {
3329 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3330 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3331 // Increment the pointer, VAList, to the next vaarg
3332 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3333 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3334 TLI.getPointerTy()));
3335 // Store the incremented VAList to the legalized pointer
3336 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3337 // Load the actual argument out of the pointer VAList
3338 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3339 Tmp1 = LegalizeOp(Result.getValue(1));
3340 Result = LegalizeOp(Result);
3344 // Since VAARG produces two values, make sure to remember that we
3345 // legalized both of them.
3346 AddLegalizedOperand(SDOperand(Node, 0), Result);
3347 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3348 return Op.ResNo ? Tmp1 : Result;
3352 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3354 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3356 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3357 default: assert(0 && "This action is not supported yet!");
3358 case TargetLowering::Custom:
3361 case TargetLowering::Legal:
3362 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3363 Node->getOperand(3), Node->getOperand(4));
3365 Tmp1 = TLI.LowerOperation(Result, DAG);
3366 if (Tmp1.Val) Result = Tmp1;
3369 case TargetLowering::Expand:
3370 // This defaults to loading a pointer from the input and storing it to the
3371 // output, returning the chain.
3372 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3373 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3374 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VD, 0);
3375 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VS, 0);
3381 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3382 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3384 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3385 default: assert(0 && "This action is not supported yet!");
3386 case TargetLowering::Custom:
3389 case TargetLowering::Legal:
3390 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3392 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3393 if (Tmp1.Val) Result = Tmp1;
3396 case TargetLowering::Expand:
3397 Result = Tmp1; // Default to a no-op, return the chain
3403 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3404 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3408 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3409 default: assert(0 && "This action is not supported yet!");
3410 case TargetLowering::Legal: break;
3411 case TargetLowering::Custom:
3412 Tmp1 = TLI.LowerOperation(Result, DAG);
3413 if (Tmp1.Val) Result = Tmp1;
3420 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3421 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3422 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3423 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3425 assert(0 && "ROTL/ROTR legalize operation not supported");
3427 case TargetLowering::Legal:
3429 case TargetLowering::Custom:
3430 Tmp1 = TLI.LowerOperation(Result, DAG);
3431 if (Tmp1.Val) Result = Tmp1;
3433 case TargetLowering::Promote:
3434 assert(0 && "Do not know how to promote ROTL/ROTR");
3436 case TargetLowering::Expand:
3437 assert(0 && "Do not know how to expand ROTL/ROTR");
3443 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3444 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3445 case TargetLowering::Custom:
3446 assert(0 && "Cannot custom legalize this yet!");
3447 case TargetLowering::Legal:
3448 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3450 case TargetLowering::Promote: {
3451 MVT::ValueType OVT = Tmp1.getValueType();
3452 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3453 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3455 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3456 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3457 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3458 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3461 case TargetLowering::Expand:
3462 Result = ExpandBSWAP(Tmp1);
3470 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3471 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3472 case TargetLowering::Custom:
3473 case TargetLowering::Legal:
3474 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3475 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3476 TargetLowering::Custom) {
3477 Tmp1 = TLI.LowerOperation(Result, DAG);
3483 case TargetLowering::Promote: {
3484 MVT::ValueType OVT = Tmp1.getValueType();
3485 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3487 // Zero extend the argument.
3488 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3489 // Perform the larger operation, then subtract if needed.
3490 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3491 switch (Node->getOpcode()) {
3496 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3497 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3498 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3500 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3501 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3504 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3505 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3506 DAG.getConstant(MVT::getSizeInBits(NVT) -
3507 MVT::getSizeInBits(OVT), NVT));
3512 case TargetLowering::Expand:
3513 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3524 Tmp1 = LegalizeOp(Node->getOperand(0));
3525 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3526 case TargetLowering::Promote:
3527 case TargetLowering::Custom:
3530 case TargetLowering::Legal:
3531 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3533 Tmp1 = TLI.LowerOperation(Result, DAG);
3534 if (Tmp1.Val) Result = Tmp1;
3537 case TargetLowering::Expand:
3538 switch (Node->getOpcode()) {
3539 default: assert(0 && "Unreachable!");
3541 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3542 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3543 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3546 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3547 MVT::ValueType VT = Node->getValueType(0);
3548 Tmp2 = DAG.getConstantFP(0.0, VT);
3549 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
3550 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3551 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3557 MVT::ValueType VT = Node->getValueType(0);
3559 // Expand unsupported unary vector operators by unrolling them.
3560 if (MVT::isVector(VT)) {
3561 Result = LegalizeOp(UnrollVectorOp(Op));
3565 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3566 switch(Node->getOpcode()) {
3568 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3569 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3572 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3573 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3576 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3577 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3579 default: assert(0 && "Unreachable!");
3582 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3583 false/*sign irrelevant*/, Dummy);
3591 MVT::ValueType VT = Node->getValueType(0);
3593 // Expand unsupported unary vector operators by unrolling them.
3594 if (MVT::isVector(VT)) {
3595 Result = LegalizeOp(UnrollVectorOp(Op));
3599 // We always lower FPOWI into a libcall. No target support for it yet.
3600 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3601 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3603 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3604 false/*sign irrelevant*/, Dummy);
3607 case ISD::BIT_CONVERT:
3608 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3609 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3610 Node->getValueType(0));
3611 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3612 // The input has to be a vector type, we have to either scalarize it, pack
3613 // it, or convert it based on whether the input vector type is legal.
3614 SDNode *InVal = Node->getOperand(0).Val;
3615 int InIx = Node->getOperand(0).ResNo;
3616 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3617 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3619 // Figure out if there is a simple type corresponding to this Vector
3620 // type. If so, convert to the vector type.
3621 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3622 if (TLI.isTypeLegal(TVT)) {
3623 // Turn this into a bit convert of the vector input.
3624 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3625 LegalizeOp(Node->getOperand(0)));
3627 } else if (NumElems == 1) {
3628 // Turn this into a bit convert of the scalar input.
3629 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3630 ScalarizeVectorOp(Node->getOperand(0)));
3633 // FIXME: UNIMP! Store then reload
3634 assert(0 && "Cast from unsupported vector type not implemented yet!");
3637 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3638 Node->getOperand(0).getValueType())) {
3639 default: assert(0 && "Unknown operation action!");
3640 case TargetLowering::Expand:
3641 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3642 Node->getValueType(0));
3644 case TargetLowering::Legal:
3645 Tmp1 = LegalizeOp(Node->getOperand(0));
3646 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3652 // Conversion operators. The source and destination have different types.
3653 case ISD::SINT_TO_FP:
3654 case ISD::UINT_TO_FP: {
3655 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3656 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3658 switch (TLI.getOperationAction(Node->getOpcode(),
3659 Node->getOperand(0).getValueType())) {
3660 default: assert(0 && "Unknown operation action!");
3661 case TargetLowering::Custom:
3664 case TargetLowering::Legal:
3665 Tmp1 = LegalizeOp(Node->getOperand(0));
3666 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3668 Tmp1 = TLI.LowerOperation(Result, DAG);
3669 if (Tmp1.Val) Result = Tmp1;
3672 case TargetLowering::Expand:
3673 Result = ExpandLegalINT_TO_FP(isSigned,
3674 LegalizeOp(Node->getOperand(0)),
3675 Node->getValueType(0));
3677 case TargetLowering::Promote:
3678 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3679 Node->getValueType(0),
3685 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3686 Node->getValueType(0), Node->getOperand(0));
3689 Tmp1 = PromoteOp(Node->getOperand(0));
3691 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3692 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3694 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3695 Node->getOperand(0).getValueType());
3697 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3698 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3704 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3706 Tmp1 = LegalizeOp(Node->getOperand(0));
3707 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3710 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3712 // Since the result is legal, we should just be able to truncate the low
3713 // part of the source.
3714 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3717 Result = PromoteOp(Node->getOperand(0));
3718 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3723 case ISD::FP_TO_SINT:
3724 case ISD::FP_TO_UINT:
3725 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3727 Tmp1 = LegalizeOp(Node->getOperand(0));
3729 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3730 default: assert(0 && "Unknown operation action!");
3731 case TargetLowering::Custom:
3734 case TargetLowering::Legal:
3735 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3737 Tmp1 = TLI.LowerOperation(Result, DAG);
3738 if (Tmp1.Val) Result = Tmp1;
3741 case TargetLowering::Promote:
3742 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3743 Node->getOpcode() == ISD::FP_TO_SINT);
3745 case TargetLowering::Expand:
3746 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3747 SDOperand True, False;
3748 MVT::ValueType VT = Node->getOperand(0).getValueType();
3749 MVT::ValueType NVT = Node->getValueType(0);
3750 const uint64_t zero[] = {0, 0};
3751 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3752 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
3753 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3754 Tmp2 = DAG.getConstantFP(apf, VT);
3755 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
3756 Node->getOperand(0), Tmp2, ISD::SETLT);
3757 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3758 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3759 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3761 False = DAG.getNode(ISD::XOR, NVT, False,
3762 DAG.getConstant(x, NVT));
3763 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3766 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3772 MVT::ValueType VT = Op.getValueType();
3773 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3774 // Convert ppcf128 to i32
3775 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3776 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3777 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3778 Node->getOperand(0), DAG.getValueType(MVT::f64));
3779 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3780 DAG.getIntPtrConstant(1));
3781 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3783 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3784 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3785 Tmp2 = DAG.getConstantFP(apf, OVT);
3786 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3787 // FIXME: generated code sucks.
3788 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3789 DAG.getNode(ISD::ADD, MVT::i32,
3790 DAG.getNode(ISD::FP_TO_SINT, VT,
3791 DAG.getNode(ISD::FSUB, OVT,
3792 Node->getOperand(0), Tmp2)),
3793 DAG.getConstant(0x80000000, MVT::i32)),
3794 DAG.getNode(ISD::FP_TO_SINT, VT,
3795 Node->getOperand(0)),
3796 DAG.getCondCode(ISD::SETGE));
3800 // Convert f32 / f64 to i32 / i64.
3801 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3802 switch (Node->getOpcode()) {
3803 case ISD::FP_TO_SINT: {
3804 if (OVT == MVT::f32)
3805 LC = (VT == MVT::i32)
3806 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3807 else if (OVT == MVT::f64)
3808 LC = (VT == MVT::i32)
3809 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3810 else if (OVT == MVT::f80) {
3811 assert(VT == MVT::i64);
3812 LC = RTLIB::FPTOSINT_F80_I64;
3814 else if (OVT == MVT::ppcf128) {
3815 assert(VT == MVT::i64);
3816 LC = RTLIB::FPTOSINT_PPCF128_I64;
3820 case ISD::FP_TO_UINT: {
3821 if (OVT == MVT::f32)
3822 LC = (VT == MVT::i32)
3823 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3824 else if (OVT == MVT::f64)
3825 LC = (VT == MVT::i32)
3826 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3827 else if (OVT == MVT::f80) {
3828 LC = (VT == MVT::i32)
3829 ? RTLIB::FPTOUINT_F80_I32 : RTLIB::FPTOUINT_F80_I64;
3831 else if (OVT == MVT::ppcf128) {
3832 assert(VT == MVT::i64);
3833 LC = RTLIB::FPTOUINT_PPCF128_I64;
3837 default: assert(0 && "Unreachable!");
3840 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3841 false/*sign irrelevant*/, Dummy);
3845 Tmp1 = PromoteOp(Node->getOperand(0));
3846 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3847 Result = LegalizeOp(Result);
3852 case ISD::FP_EXTEND: {
3853 MVT::ValueType DstVT = Op.getValueType();
3854 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3855 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3856 // The only other way we can lower this is to turn it into a STORE,
3857 // LOAD pair, targetting a temporary location (a stack slot).
3858 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3861 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3862 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3864 Tmp1 = LegalizeOp(Node->getOperand(0));
3865 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3868 Tmp1 = PromoteOp(Node->getOperand(0));
3869 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3874 case ISD::FP_ROUND: {
3875 MVT::ValueType DstVT = Op.getValueType();
3876 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3877 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3878 if (SrcVT == MVT::ppcf128) {
3880 ExpandOp(Node->getOperand(0), Lo, Result);
3881 // Round it the rest of the way (e.g. to f32) if needed.
3882 if (DstVT!=MVT::f64)
3883 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3886 // The only other way we can lower this is to turn it into a STORE,
3887 // LOAD pair, targetting a temporary location (a stack slot).
3888 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3891 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3892 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3894 Tmp1 = LegalizeOp(Node->getOperand(0));
3895 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3898 Tmp1 = PromoteOp(Node->getOperand(0));
3899 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3900 Node->getOperand(1));
3905 case ISD::ANY_EXTEND:
3906 case ISD::ZERO_EXTEND:
3907 case ISD::SIGN_EXTEND:
3908 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3909 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3911 Tmp1 = LegalizeOp(Node->getOperand(0));
3912 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3913 TargetLowering::Custom) {
3914 Tmp2 = TLI.LowerOperation(Result, DAG);
3919 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3922 switch (Node->getOpcode()) {
3923 case ISD::ANY_EXTEND:
3924 Tmp1 = PromoteOp(Node->getOperand(0));
3925 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3927 case ISD::ZERO_EXTEND:
3928 Result = PromoteOp(Node->getOperand(0));
3929 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3930 Result = DAG.getZeroExtendInReg(Result,
3931 Node->getOperand(0).getValueType());
3933 case ISD::SIGN_EXTEND:
3934 Result = PromoteOp(Node->getOperand(0));
3935 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3936 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3938 DAG.getValueType(Node->getOperand(0).getValueType()));
3943 case ISD::FP_ROUND_INREG:
3944 case ISD::SIGN_EXTEND_INREG: {
3945 Tmp1 = LegalizeOp(Node->getOperand(0));
3946 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3948 // If this operation is not supported, convert it to a shl/shr or load/store
3950 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3951 default: assert(0 && "This action not supported for this op yet!");
3952 case TargetLowering::Legal:
3953 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3955 case TargetLowering::Expand:
3956 // If this is an integer extend and shifts are supported, do that.
3957 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3958 // NOTE: we could fall back on load/store here too for targets without
3959 // SAR. However, it is doubtful that any exist.
3960 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3961 MVT::getSizeInBits(ExtraVT);
3962 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3963 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3964 Node->getOperand(0), ShiftCst);
3965 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3967 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3968 // The only way we can lower this is to turn it into a TRUNCSTORE,
3969 // EXTLOAD pair, targetting a temporary location (a stack slot).
3971 // NOTE: there is a choice here between constantly creating new stack
3972 // slots and always reusing the same one. We currently always create
3973 // new ones, as reuse may inhibit scheduling.
3974 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3975 Node->getValueType(0));
3977 assert(0 && "Unknown op");
3983 case ISD::TRAMPOLINE: {
3985 for (unsigned i = 0; i != 6; ++i)
3986 Ops[i] = LegalizeOp(Node->getOperand(i));
3987 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3988 // The only option for this node is to custom lower it.
3989 Result = TLI.LowerOperation(Result, DAG);
3990 assert(Result.Val && "Should always custom lower!");
3992 // Since trampoline produces two values, make sure to remember that we
3993 // legalized both of them.
3994 Tmp1 = LegalizeOp(Result.getValue(1));
3995 Result = LegalizeOp(Result);
3996 AddLegalizedOperand(SDOperand(Node, 0), Result);
3997 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3998 return Op.ResNo ? Tmp1 : Result;
4000 case ISD::FLT_ROUNDS_: {
4001 MVT::ValueType VT = Node->getValueType(0);
4002 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4003 default: assert(0 && "This action not supported for this op yet!");
4004 case TargetLowering::Custom:
4005 Result = TLI.LowerOperation(Op, DAG);
4006 if (Result.Val) break;
4008 case TargetLowering::Legal:
4009 // If this operation is not supported, lower it to constant 1
4010 Result = DAG.getConstant(1, VT);
4015 MVT::ValueType VT = Node->getValueType(0);
4016 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4017 default: assert(0 && "This action not supported for this op yet!");
4018 case TargetLowering::Legal:
4019 Tmp1 = LegalizeOp(Node->getOperand(0));
4020 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4022 case TargetLowering::Custom:
4023 Result = TLI.LowerOperation(Op, DAG);
4024 if (Result.Val) break;
4026 case TargetLowering::Expand:
4027 // If this operation is not supported, lower it to 'abort()' call
4028 Tmp1 = LegalizeOp(Node->getOperand(0));
4029 TargetLowering::ArgListTy Args;
4030 std::pair<SDOperand,SDOperand> CallResult =
4031 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4032 false, false, false, CallingConv::C, false,
4033 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4035 Result = CallResult.second;
4042 assert(Result.getValueType() == Op.getValueType() &&
4043 "Bad legalization!");
4045 // Make sure that the generated code is itself legal.
4047 Result = LegalizeOp(Result);
4049 // Note that LegalizeOp may be reentered even from single-use nodes, which
4050 // means that we always must cache transformed nodes.
4051 AddLegalizedOperand(Op, Result);
4055 /// PromoteOp - Given an operation that produces a value in an invalid type,
4056 /// promote it to compute the value into a larger type. The produced value will
4057 /// have the correct bits for the low portion of the register, but no guarantee
4058 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4059 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4060 MVT::ValueType VT = Op.getValueType();
4061 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4062 assert(getTypeAction(VT) == Promote &&
4063 "Caller should expand or legalize operands that are not promotable!");
4064 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4065 "Cannot promote to smaller type!");
4067 SDOperand Tmp1, Tmp2, Tmp3;
4069 SDNode *Node = Op.Val;
4071 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4072 if (I != PromotedNodes.end()) return I->second;
4074 switch (Node->getOpcode()) {
4075 case ISD::CopyFromReg:
4076 assert(0 && "CopyFromReg must be legal!");
4079 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4081 assert(0 && "Do not know how to promote this operator!");
4084 Result = DAG.getNode(ISD::UNDEF, NVT);
4088 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4090 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4091 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4093 case ISD::ConstantFP:
4094 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4095 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4099 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
4100 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
4101 Node->getOperand(1), Node->getOperand(2));
4105 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4107 Result = LegalizeOp(Node->getOperand(0));
4108 assert(Result.getValueType() >= NVT &&
4109 "This truncation doesn't make sense!");
4110 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4111 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4114 // The truncation is not required, because we don't guarantee anything
4115 // about high bits anyway.
4116 Result = PromoteOp(Node->getOperand(0));
4119 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4120 // Truncate the low part of the expanded value to the result type
4121 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4124 case ISD::SIGN_EXTEND:
4125 case ISD::ZERO_EXTEND:
4126 case ISD::ANY_EXTEND:
4127 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4128 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4130 // Input is legal? Just do extend all the way to the larger type.
4131 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4134 // Promote the reg if it's smaller.
4135 Result = PromoteOp(Node->getOperand(0));
4136 // The high bits are not guaranteed to be anything. Insert an extend.
4137 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4138 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4139 DAG.getValueType(Node->getOperand(0).getValueType()));
4140 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4141 Result = DAG.getZeroExtendInReg(Result,
4142 Node->getOperand(0).getValueType());
4146 case ISD::BIT_CONVERT:
4147 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4148 Node->getValueType(0));
4149 Result = PromoteOp(Result);
4152 case ISD::FP_EXTEND:
4153 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4155 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4156 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4157 case Promote: assert(0 && "Unreachable with 2 FP types!");
4159 if (Node->getConstantOperandVal(1) == 0) {
4160 // Input is legal? Do an FP_ROUND_INREG.
4161 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4162 DAG.getValueType(VT));
4164 // Just remove the truncate, it isn't affecting the value.
4165 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4166 Node->getOperand(1));
4171 case ISD::SINT_TO_FP:
4172 case ISD::UINT_TO_FP:
4173 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4175 // No extra round required here.
4176 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4180 Result = PromoteOp(Node->getOperand(0));
4181 if (Node->getOpcode() == ISD::SINT_TO_FP)
4182 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4184 DAG.getValueType(Node->getOperand(0).getValueType()));
4186 Result = DAG.getZeroExtendInReg(Result,
4187 Node->getOperand(0).getValueType());
4188 // No extra round required here.
4189 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4192 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4193 Node->getOperand(0));
4194 // Round if we cannot tolerate excess precision.
4195 if (NoExcessFPPrecision)
4196 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4197 DAG.getValueType(VT));
4202 case ISD::SIGN_EXTEND_INREG:
4203 Result = PromoteOp(Node->getOperand(0));
4204 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4205 Node->getOperand(1));
4207 case ISD::FP_TO_SINT:
4208 case ISD::FP_TO_UINT:
4209 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4212 Tmp1 = Node->getOperand(0);
4215 // The input result is prerounded, so we don't have to do anything
4217 Tmp1 = PromoteOp(Node->getOperand(0));
4220 // If we're promoting a UINT to a larger size, check to see if the new node
4221 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4222 // we can use that instead. This allows us to generate better code for
4223 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4224 // legal, such as PowerPC.
4225 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4226 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4227 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4228 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4229 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4231 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4237 Tmp1 = PromoteOp(Node->getOperand(0));
4238 assert(Tmp1.getValueType() == NVT);
4239 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4240 // NOTE: we do not have to do any extra rounding here for
4241 // NoExcessFPPrecision, because we know the input will have the appropriate
4242 // precision, and these operations don't modify precision at all.
4248 Tmp1 = PromoteOp(Node->getOperand(0));
4249 assert(Tmp1.getValueType() == NVT);
4250 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4251 if (NoExcessFPPrecision)
4252 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4253 DAG.getValueType(VT));
4257 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4258 // directly as well, which may be better.
4259 Tmp1 = PromoteOp(Node->getOperand(0));
4260 assert(Tmp1.getValueType() == NVT);
4261 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4262 if (NoExcessFPPrecision)
4263 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4264 DAG.getValueType(VT));
4268 case ISD::ATOMIC_LCS: {
4269 Tmp2 = PromoteOp(Node->getOperand(2));
4270 Tmp3 = PromoteOp(Node->getOperand(3));
4271 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4272 Node->getOperand(1), Tmp2, Tmp3,
4273 cast<AtomicSDNode>(Node)->getVT());
4274 // Remember that we legalized the chain.
4275 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4278 case ISD::ATOMIC_LAS:
4279 case ISD::ATOMIC_SWAP: {
4280 Tmp2 = PromoteOp(Node->getOperand(2));
4281 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4282 Node->getOperand(1), Tmp2,
4283 cast<AtomicSDNode>(Node)->getVT());
4284 // Remember that we legalized the chain.
4285 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4295 // The input may have strange things in the top bits of the registers, but
4296 // these operations don't care. They may have weird bits going out, but
4297 // that too is okay if they are integer operations.
4298 Tmp1 = PromoteOp(Node->getOperand(0));
4299 Tmp2 = PromoteOp(Node->getOperand(1));
4300 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4301 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4306 Tmp1 = PromoteOp(Node->getOperand(0));
4307 Tmp2 = PromoteOp(Node->getOperand(1));
4308 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4309 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4311 // Floating point operations will give excess precision that we may not be
4312 // able to tolerate. If we DO allow excess precision, just leave it,
4313 // otherwise excise it.
4314 // FIXME: Why would we need to round FP ops more than integer ones?
4315 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4316 if (NoExcessFPPrecision)
4317 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4318 DAG.getValueType(VT));
4323 // These operators require that their input be sign extended.
4324 Tmp1 = PromoteOp(Node->getOperand(0));
4325 Tmp2 = PromoteOp(Node->getOperand(1));
4326 if (MVT::isInteger(NVT)) {
4327 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4328 DAG.getValueType(VT));
4329 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4330 DAG.getValueType(VT));
4332 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4334 // Perform FP_ROUND: this is probably overly pessimistic.
4335 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4336 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4337 DAG.getValueType(VT));
4341 case ISD::FCOPYSIGN:
4342 // These operators require that their input be fp extended.
4343 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4344 case Expand: assert(0 && "not implemented");
4345 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4346 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4348 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4349 case Expand: assert(0 && "not implemented");
4350 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4351 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4353 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4355 // Perform FP_ROUND: this is probably overly pessimistic.
4356 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4357 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4358 DAG.getValueType(VT));
4363 // These operators require that their input be zero extended.
4364 Tmp1 = PromoteOp(Node->getOperand(0));
4365 Tmp2 = PromoteOp(Node->getOperand(1));
4366 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4367 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4368 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4369 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4373 Tmp1 = PromoteOp(Node->getOperand(0));
4374 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4377 // The input value must be properly sign extended.
4378 Tmp1 = PromoteOp(Node->getOperand(0));
4379 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4380 DAG.getValueType(VT));
4381 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4384 // The input value must be properly zero extended.
4385 Tmp1 = PromoteOp(Node->getOperand(0));
4386 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4387 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4391 Tmp1 = Node->getOperand(0); // Get the chain.
4392 Tmp2 = Node->getOperand(1); // Get the pointer.
4393 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4394 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4395 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4397 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4398 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4399 // Increment the pointer, VAList, to the next vaarg
4400 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4401 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4402 TLI.getPointerTy()));
4403 // Store the incremented VAList to the legalized pointer
4404 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4405 // Load the actual argument out of the pointer VAList
4406 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4408 // Remember that we legalized the chain.
4409 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4413 LoadSDNode *LD = cast<LoadSDNode>(Node);
4414 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4415 ? ISD::EXTLOAD : LD->getExtensionType();
4416 Result = DAG.getExtLoad(ExtType, NVT,
4417 LD->getChain(), LD->getBasePtr(),
4418 LD->getSrcValue(), LD->getSrcValueOffset(),
4421 LD->getAlignment());
4422 // Remember that we legalized the chain.
4423 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4427 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4428 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4429 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4431 case ISD::SELECT_CC:
4432 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4433 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4434 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4435 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4438 Tmp1 = Node->getOperand(0);
4439 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4440 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4441 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4442 DAG.getConstant(MVT::getSizeInBits(NVT) -
4443 MVT::getSizeInBits(VT),
4444 TLI.getShiftAmountTy()));
4449 // Zero extend the argument
4450 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4451 // Perform the larger operation, then subtract if needed.
4452 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4453 switch(Node->getOpcode()) {
4458 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4459 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
4460 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4462 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4463 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4466 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4467 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4468 DAG.getConstant(MVT::getSizeInBits(NVT) -
4469 MVT::getSizeInBits(VT), NVT));
4473 case ISD::EXTRACT_SUBVECTOR:
4474 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4476 case ISD::EXTRACT_VECTOR_ELT:
4477 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4481 assert(Result.Val && "Didn't set a result!");
4483 // Make sure the result is itself legal.
4484 Result = LegalizeOp(Result);
4486 // Remember that we promoted this!
4487 AddPromotedOperand(Op, Result);
4491 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4492 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4493 /// based on the vector type. The return type of this matches the element type
4494 /// of the vector, which may not be legal for the target.
4495 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4496 // We know that operand #0 is the Vec vector. If the index is a constant
4497 // or if the invec is a supported hardware type, we can use it. Otherwise,
4498 // lower to a store then an indexed load.
4499 SDOperand Vec = Op.getOperand(0);
4500 SDOperand Idx = Op.getOperand(1);
4502 MVT::ValueType TVT = Vec.getValueType();
4503 unsigned NumElems = MVT::getVectorNumElements(TVT);
4505 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4506 default: assert(0 && "This action is not supported yet!");
4507 case TargetLowering::Custom: {
4508 Vec = LegalizeOp(Vec);
4509 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4510 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4515 case TargetLowering::Legal:
4516 if (isTypeLegal(TVT)) {
4517 Vec = LegalizeOp(Vec);
4518 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4522 case TargetLowering::Expand:
4526 if (NumElems == 1) {
4527 // This must be an access of the only element. Return it.
4528 Op = ScalarizeVectorOp(Vec);
4529 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4530 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4531 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4533 SplitVectorOp(Vec, Lo, Hi);
4534 if (CIdx->getValue() < NumLoElts) {
4538 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4539 Idx.getValueType());
4542 // It's now an extract from the appropriate high or low part. Recurse.
4543 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4544 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4546 // Store the value to a temporary stack slot, then LOAD the scalar
4547 // element back out.
4548 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4549 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4551 // Add the offset to the index.
4552 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4553 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4554 DAG.getConstant(EltSize, Idx.getValueType()));
4556 if (MVT::getSizeInBits(Idx.getValueType()) >
4557 MVT::getSizeInBits(TLI.getPointerTy()))
4558 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4560 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4562 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4564 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4569 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4570 /// we assume the operation can be split if it is not already legal.
4571 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4572 // We know that operand #0 is the Vec vector. For now we assume the index
4573 // is a constant and that the extracted result is a supported hardware type.
4574 SDOperand Vec = Op.getOperand(0);
4575 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4577 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4579 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4580 // This must be an access of the desired vector length. Return it.
4584 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4586 SplitVectorOp(Vec, Lo, Hi);
4587 if (CIdx->getValue() < NumElems/2) {
4591 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4594 // It's now an extract from the appropriate high or low part. Recurse.
4595 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4596 return ExpandEXTRACT_SUBVECTOR(Op);
4599 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4600 /// with condition CC on the current target. This usually involves legalizing
4601 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4602 /// there may be no choice but to create a new SetCC node to represent the
4603 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4604 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4605 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4608 SDOperand Tmp1, Tmp2, Tmp3, Result;
4610 switch (getTypeAction(LHS.getValueType())) {
4612 Tmp1 = LegalizeOp(LHS); // LHS
4613 Tmp2 = LegalizeOp(RHS); // RHS
4616 Tmp1 = PromoteOp(LHS); // LHS
4617 Tmp2 = PromoteOp(RHS); // RHS
4619 // If this is an FP compare, the operands have already been extended.
4620 if (MVT::isInteger(LHS.getValueType())) {
4621 MVT::ValueType VT = LHS.getValueType();
4622 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4624 // Otherwise, we have to insert explicit sign or zero extends. Note
4625 // that we could insert sign extends for ALL conditions, but zero extend
4626 // is cheaper on many machines (an AND instead of two shifts), so prefer
4628 switch (cast<CondCodeSDNode>(CC)->get()) {
4629 default: assert(0 && "Unknown integer comparison!");
4636 // ALL of these operations will work if we either sign or zero extend
4637 // the operands (including the unsigned comparisons!). Zero extend is
4638 // usually a simpler/cheaper operation, so prefer it.
4639 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4640 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4646 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4647 DAG.getValueType(VT));
4648 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4649 DAG.getValueType(VT));
4655 MVT::ValueType VT = LHS.getValueType();
4656 if (VT == MVT::f32 || VT == MVT::f64) {
4657 // Expand into one or more soft-fp libcall(s).
4658 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4659 switch (cast<CondCodeSDNode>(CC)->get()) {
4662 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4666 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4670 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4674 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4678 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4682 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4685 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4688 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4691 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4692 switch (cast<CondCodeSDNode>(CC)->get()) {
4694 // SETONE = SETOLT | SETOGT
4695 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4698 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4701 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4704 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4707 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4710 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4712 default: assert(0 && "Unsupported FP setcc!");
4717 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
4718 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4719 false /*sign irrelevant*/, Dummy);
4720 Tmp2 = DAG.getConstant(0, MVT::i32);
4721 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4722 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4723 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
4724 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
4725 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4726 false /*sign irrelevant*/, Dummy);
4727 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
4728 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4729 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4737 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4738 ExpandOp(LHS, LHSLo, LHSHi);
4739 ExpandOp(RHS, RHSLo, RHSHi);
4740 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4742 if (VT==MVT::ppcf128) {
4743 // FIXME: This generated code sucks. We want to generate
4744 // FCMP crN, hi1, hi2
4746 // FCMP crN, lo1, lo2
4747 // The following can be improved, but not that much.
4748 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4749 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, CCCode);
4750 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4751 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETNE);
4752 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, CCCode);
4753 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4754 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4763 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4764 if (RHSCST->isAllOnesValue()) {
4765 // Comparison to -1.
4766 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4771 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4772 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4773 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4774 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4777 // If this is a comparison of the sign bit, just look at the top part.
4779 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4780 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4781 CST->getValue() == 0) || // X < 0
4782 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4783 CST->isAllOnesValue())) { // X > -1
4789 // FIXME: This generated code sucks.
4790 ISD::CondCode LowCC;
4792 default: assert(0 && "Unknown integer setcc!");
4794 case ISD::SETULT: LowCC = ISD::SETULT; break;
4796 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4798 case ISD::SETULE: LowCC = ISD::SETULE; break;
4800 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4803 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4804 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4805 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4807 // NOTE: on targets without efficient SELECT of bools, we can always use
4808 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4809 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4810 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
4811 false, DagCombineInfo);
4813 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
4814 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4815 CCCode, false, DagCombineInfo);
4817 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi,CC);
4819 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4820 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4821 if ((Tmp1C && Tmp1C->getValue() == 0) ||
4822 (Tmp2C && Tmp2C->getValue() == 0 &&
4823 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4824 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4825 (Tmp2C && Tmp2C->getValue() == 1 &&
4826 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4827 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4828 // low part is known false, returns high part.
4829 // For LE / GE, if high part is known false, ignore the low part.
4830 // For LT / GT, if high part is known true, ignore the low part.
4834 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
4835 ISD::SETEQ, false, DagCombineInfo);
4837 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
4838 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4839 Result, Tmp1, Tmp2));
4850 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4851 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4852 /// a load from the stack slot to DestVT, extending it if needed.
4853 /// The resultant code need not be legal.
4854 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4855 MVT::ValueType SlotVT,
4856 MVT::ValueType DestVT) {
4857 // Create the stack frame object.
4858 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4860 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4861 int SPFI = StackPtrFI->getIndex();
4863 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4864 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4865 unsigned DestSize = MVT::getSizeInBits(DestVT);
4867 // Emit a store to the stack slot. Use a truncstore if the input value is
4868 // later than DestVT.
4870 if (SrcSize > SlotSize)
4871 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4872 PseudoSourceValue::getFixedStack(),
4875 assert(SrcSize == SlotSize && "Invalid store");
4876 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4877 PseudoSourceValue::getFixedStack(),
4881 // Result is a load from the stack slot.
4882 if (SlotSize == DestSize)
4883 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4885 assert(SlotSize < DestSize && "Unknown extension!");
4886 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4889 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4890 // Create a vector sized/aligned stack slot, store the value to element #0,
4891 // then load the whole vector back out.
4892 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4894 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4895 int SPFI = StackPtrFI->getIndex();
4897 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4898 PseudoSourceValue::getFixedStack(), SPFI);
4899 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4900 PseudoSourceValue::getFixedStack(), SPFI);
4904 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4905 /// support the operation, but do support the resultant vector type.
4906 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4908 // If the only non-undef value is the low element, turn this into a
4909 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4910 unsigned NumElems = Node->getNumOperands();
4911 bool isOnlyLowElement = true;
4912 SDOperand SplatValue = Node->getOperand(0);
4913 std::map<SDOperand, std::vector<unsigned> > Values;
4914 Values[SplatValue].push_back(0);
4915 bool isConstant = true;
4916 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4917 SplatValue.getOpcode() != ISD::UNDEF)
4920 for (unsigned i = 1; i < NumElems; ++i) {
4921 SDOperand V = Node->getOperand(i);
4922 Values[V].push_back(i);
4923 if (V.getOpcode() != ISD::UNDEF)
4924 isOnlyLowElement = false;
4925 if (SplatValue != V)
4926 SplatValue = SDOperand(0,0);
4928 // If this isn't a constant element or an undef, we can't use a constant
4930 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4931 V.getOpcode() != ISD::UNDEF)
4935 if (isOnlyLowElement) {
4936 // If the low element is an undef too, then this whole things is an undef.
4937 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4938 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4939 // Otherwise, turn this into a scalar_to_vector node.
4940 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4941 Node->getOperand(0));
4944 // If all elements are constants, create a load from the constant pool.
4946 MVT::ValueType VT = Node->getValueType(0);
4948 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4949 std::vector<Constant*> CV;
4950 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4951 if (ConstantFPSDNode *V =
4952 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4953 CV.push_back(ConstantFP::get(OpNTy, V->getValueAPF()));
4954 } else if (ConstantSDNode *V =
4955 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4956 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
4958 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4959 CV.push_back(UndefValue::get(OpNTy));
4962 Constant *CP = ConstantVector::get(CV);
4963 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4964 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4965 PseudoSourceValue::getConstantPool(), 0);
4968 if (SplatValue.Val) { // Splat of one value?
4969 // Build the shuffle constant vector: <0, 0, 0, 0>
4970 MVT::ValueType MaskVT =
4971 MVT::getIntVectorWithNumElements(NumElems);
4972 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4973 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4974 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4975 &ZeroVec[0], ZeroVec.size());
4977 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4978 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4979 // Get the splatted value into the low element of a vector register.
4980 SDOperand LowValVec =
4981 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4983 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4984 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4985 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4990 // If there are only two unique elements, we may be able to turn this into a
4992 if (Values.size() == 2) {
4993 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4994 MVT::ValueType MaskVT =
4995 MVT::getIntVectorWithNumElements(NumElems);
4996 std::vector<SDOperand> MaskVec(NumElems);
4998 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4999 E = Values.end(); I != E; ++I) {
5000 for (std::vector<unsigned>::iterator II = I->second.begin(),
5001 EE = I->second.end(); II != EE; ++II)
5002 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
5005 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5006 &MaskVec[0], MaskVec.size());
5008 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5009 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5010 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5011 SmallVector<SDOperand, 8> Ops;
5012 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
5013 E = Values.end(); I != E; ++I) {
5014 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5018 Ops.push_back(ShuffleMask);
5020 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5021 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
5022 &Ops[0], Ops.size());
5026 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5027 // aligned object on the stack, store each element into it, then load
5028 // the result as a vector.
5029 MVT::ValueType VT = Node->getValueType(0);
5030 // Create the stack frame object.
5031 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5033 // Emit a store of each element to the stack slot.
5034 SmallVector<SDOperand, 8> Stores;
5035 unsigned TypeByteSize =
5036 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5037 // Store (in the right endianness) the elements to memory.
5038 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5039 // Ignore undef elements.
5040 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5042 unsigned Offset = TypeByteSize*i;
5044 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5045 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5047 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5051 SDOperand StoreChain;
5052 if (!Stores.empty()) // Not all undef elements?
5053 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5054 &Stores[0], Stores.size());
5056 StoreChain = DAG.getEntryNode();
5058 // Result is a load from the stack slot.
5059 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5062 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5063 SDOperand Op, SDOperand Amt,
5064 SDOperand &Lo, SDOperand &Hi) {
5065 // Expand the subcomponents.
5066 SDOperand LHSL, LHSH;
5067 ExpandOp(Op, LHSL, LHSH);
5069 SDOperand Ops[] = { LHSL, LHSH, Amt };
5070 MVT::ValueType VT = LHSL.getValueType();
5071 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5072 Hi = Lo.getValue(1);
5076 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5077 /// smaller elements. If we can't find a way that is more efficient than a
5078 /// libcall on this target, return false. Otherwise, return true with the
5079 /// low-parts expanded into Lo and Hi.
5080 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5081 SDOperand &Lo, SDOperand &Hi) {
5082 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5083 "This is not a shift!");
5085 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5086 SDOperand ShAmt = LegalizeOp(Amt);
5087 MVT::ValueType ShTy = ShAmt.getValueType();
5088 unsigned ShBits = MVT::getSizeInBits(ShTy);
5089 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5090 unsigned NVTBits = MVT::getSizeInBits(NVT);
5092 // Handle the case when Amt is an immediate.
5093 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5094 unsigned Cst = CN->getValue();
5095 // Expand the incoming operand to be shifted, so that we have its parts
5097 ExpandOp(Op, InL, InH);
5101 Lo = DAG.getConstant(0, NVT);
5102 Hi = DAG.getConstant(0, NVT);
5103 } else if (Cst > NVTBits) {
5104 Lo = DAG.getConstant(0, NVT);
5105 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5106 } else if (Cst == NVTBits) {
5107 Lo = DAG.getConstant(0, NVT);
5110 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5111 Hi = DAG.getNode(ISD::OR, NVT,
5112 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5113 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5118 Lo = DAG.getConstant(0, NVT);
5119 Hi = DAG.getConstant(0, NVT);
5120 } else if (Cst > NVTBits) {
5121 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5122 Hi = DAG.getConstant(0, NVT);
5123 } else if (Cst == NVTBits) {
5125 Hi = DAG.getConstant(0, NVT);
5127 Lo = DAG.getNode(ISD::OR, NVT,
5128 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5129 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5130 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5135 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5136 DAG.getConstant(NVTBits-1, ShTy));
5137 } else if (Cst > NVTBits) {
5138 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5139 DAG.getConstant(Cst-NVTBits, ShTy));
5140 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5141 DAG.getConstant(NVTBits-1, ShTy));
5142 } else if (Cst == NVTBits) {
5144 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5145 DAG.getConstant(NVTBits-1, ShTy));
5147 Lo = DAG.getNode(ISD::OR, NVT,
5148 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5149 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5150 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5156 // Okay, the shift amount isn't constant. However, if we can tell that it is
5157 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5158 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5159 APInt KnownZero, KnownOne;
5160 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5162 // If we know that if any of the high bits of the shift amount are one, then
5163 // we can do this as a couple of simple shifts.
5164 if (KnownOne.intersects(Mask)) {
5165 // Mask out the high bit, which we know is set.
5166 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5167 DAG.getConstant(~Mask, Amt.getValueType()));
5169 // Expand the incoming operand to be shifted, so that we have its parts
5171 ExpandOp(Op, InL, InH);
5174 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5175 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5178 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5179 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5182 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5183 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5184 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5189 // If we know that the high bits of the shift amount are all zero, then we can
5190 // do this as a couple of simple shifts.
5191 if ((KnownZero & Mask) == Mask) {
5193 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5194 DAG.getConstant(NVTBits, Amt.getValueType()),
5197 // Expand the incoming operand to be shifted, so that we have its parts
5199 ExpandOp(Op, InL, InH);
5202 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5203 Hi = DAG.getNode(ISD::OR, NVT,
5204 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5205 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5208 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5209 Lo = DAG.getNode(ISD::OR, NVT,
5210 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5211 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5214 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5215 Lo = DAG.getNode(ISD::OR, NVT,
5216 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5217 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5226 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5227 // does not fit into a register, return the lo part and set the hi part to the
5228 // by-reg argument. If it does fit into a single register, return the result
5229 // and leave the Hi part unset.
5230 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
5231 bool isSigned, SDOperand &Hi) {
5232 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5233 // The input chain to this libcall is the entry node of the function.
5234 // Legalizing the call will automatically add the previous call to the
5236 SDOperand InChain = DAG.getEntryNode();
5238 TargetLowering::ArgListTy Args;
5239 TargetLowering::ArgListEntry Entry;
5240 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5241 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5242 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5243 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5244 Entry.isSExt = isSigned;
5245 Entry.isZExt = !isSigned;
5246 Args.push_back(Entry);
5248 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
5250 // Splice the libcall in wherever FindInputOutputChains tells us to.
5251 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5252 std::pair<SDOperand,SDOperand> CallInfo =
5253 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5254 false, Callee, Args, DAG);
5256 // Legalize the call sequence, starting with the chain. This will advance
5257 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5258 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5259 LegalizeOp(CallInfo.second);
5261 switch (getTypeAction(CallInfo.first.getValueType())) {
5262 default: assert(0 && "Unknown thing");
5264 Result = CallInfo.first;
5267 ExpandOp(CallInfo.first, Result, Hi);
5274 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5276 SDOperand SelectionDAGLegalize::
5277 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5278 MVT::ValueType SourceVT = Source.getValueType();
5279 assert(getTypeAction(SourceVT) == Expand &&
5280 "This is not an expansion!");
5283 assert(SourceVT == MVT::i64 &&
5284 "This only works for 64-bit -> FP");
5285 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
5286 // incoming integer is set. To handle this, we dynamically test to see if
5287 // it is set, and, if so, add a fudge factor.
5289 ExpandOp(Source, Lo, Hi);
5291 // If this is unsigned, and not supported, first perform the conversion to
5292 // signed, then adjust the result if the sign bit is set.
5293 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
5294 DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi));
5296 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
5297 DAG.getConstant(0, Hi.getValueType()),
5299 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5300 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5301 SignSet, Four, Zero);
5302 uint64_t FF = 0x5f800000ULL;
5303 if (TLI.isLittleEndian()) FF <<= 32;
5304 static Constant *FudgeFactor =
5305 ConstantInt::get(IntegerType::get(Source.getValueSizeInBits()), FF);
5307 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5308 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5309 SDOperand FudgeInReg;
5310 if (DestTy == MVT::f32)
5311 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5312 PseudoSourceValue::getConstantPool(), 0);
5313 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5314 // FIXME: Avoid the extend by construction the right constantpool?
5315 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5317 PseudoSourceValue::getConstantPool(), 0,
5320 assert(0 && "Unexpected conversion");
5322 MVT::ValueType SCVT = SignedConv.getValueType();
5323 if (SCVT != DestTy) {
5324 // Destination type needs to be expanded as well. The FADD now we are
5325 // constructing will be expanded into a libcall.
5326 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5327 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy));
5328 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5329 SignedConv, SignedConv.getValue(1));
5331 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5333 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5336 // Check to see if the target has a custom way to lower this. If so, use it.
5337 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5338 default: assert(0 && "This action not implemented for this operation!");
5339 case TargetLowering::Legal:
5340 case TargetLowering::Expand:
5341 break; // This case is handled below.
5342 case TargetLowering::Custom: {
5343 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5346 return LegalizeOp(NV);
5347 break; // The target decided this was legal after all
5351 // Expand the source, then glue it back together for the call. We must expand
5352 // the source in case it is shared (this pass of legalize must traverse it).
5353 SDOperand SrcLo, SrcHi;
5354 ExpandOp(Source, SrcLo, SrcHi);
5355 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5358 if (SourceVT == MVT::i64) {
5359 if (DestTy == MVT::f32)
5360 LC = RTLIB::SINTTOFP_I64_F32;
5362 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5363 LC = RTLIB::SINTTOFP_I64_F64;
5365 } else if (SourceVT == MVT::i128) {
5366 if (DestTy == MVT::f32)
5367 LC = RTLIB::SINTTOFP_I128_F32;
5368 else if (DestTy == MVT::f64)
5369 LC = RTLIB::SINTTOFP_I128_F64;
5370 else if (DestTy == MVT::f80)
5371 LC = RTLIB::SINTTOFP_I128_F80;
5373 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5374 LC = RTLIB::SINTTOFP_I128_PPCF128;
5377 assert(0 && "Unknown int value type");
5380 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5381 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5382 SDOperand UnusedHiPart;
5383 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
5387 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5388 /// INT_TO_FP operation of the specified operand when the target requests that
5389 /// we expand it. At this point, we know that the result and operand types are
5390 /// legal for the target.
5391 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5393 MVT::ValueType DestVT) {
5394 if (Op0.getValueType() == MVT::i32) {
5395 // simple 32-bit [signed|unsigned] integer to float/double expansion
5397 // Get the stack frame index of a 8 byte buffer.
5398 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5400 // word offset constant for Hi/Lo address computation
5401 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5402 // set up Hi and Lo (into buffer) address based on endian
5403 SDOperand Hi = StackSlot;
5404 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5405 if (TLI.isLittleEndian())
5408 // if signed map to unsigned space
5409 SDOperand Op0Mapped;
5411 // constant used to invert sign bit (signed to unsigned mapping)
5412 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5413 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5417 // store the lo of the constructed double - based on integer input
5418 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5419 Op0Mapped, Lo, NULL, 0);
5420 // initial hi portion of constructed double
5421 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5422 // store the hi of the constructed double - biased exponent
5423 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5424 // load the constructed double
5425 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5426 // FP constant to bias correct the final result
5427 SDOperand Bias = DAG.getConstantFP(isSigned ?
5428 BitsToDouble(0x4330000080000000ULL)
5429 : BitsToDouble(0x4330000000000000ULL),
5431 // subtract the bias
5432 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5435 // handle final rounding
5436 if (DestVT == MVT::f64) {
5439 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5440 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5441 DAG.getIntPtrConstant(0));
5442 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5443 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5447 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5448 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5450 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
5451 DAG.getConstant(0, Op0.getValueType()),
5453 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5454 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5455 SignSet, Four, Zero);
5457 // If the sign bit of the integer is set, the large number will be treated
5458 // as a negative number. To counteract this, the dynamic code adds an
5459 // offset depending on the data type.
5461 switch (Op0.getValueType()) {
5462 default: assert(0 && "Unsupported integer type!");
5463 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5464 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5465 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5466 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5468 if (TLI.isLittleEndian()) FF <<= 32;
5469 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5471 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5472 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5473 SDOperand FudgeInReg;
5474 if (DestVT == MVT::f32)
5475 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5476 PseudoSourceValue::getConstantPool(), 0);
5479 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5480 DAG.getEntryNode(), CPIdx,
5481 PseudoSourceValue::getConstantPool(), 0,
5485 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5488 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5489 /// *INT_TO_FP operation of the specified operand when the target requests that
5490 /// we promote it. At this point, we know that the result and operand types are
5491 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5492 /// operation that takes a larger input.
5493 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5494 MVT::ValueType DestVT,
5496 // First step, figure out the appropriate *INT_TO_FP operation to use.
5497 MVT::ValueType NewInTy = LegalOp.getValueType();
5499 unsigned OpToUse = 0;
5501 // Scan for the appropriate larger type to use.
5503 NewInTy = (MVT::ValueType)(NewInTy+1);
5504 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5506 // If the target supports SINT_TO_FP of this type, use it.
5507 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5509 case TargetLowering::Legal:
5510 if (!TLI.isTypeLegal(NewInTy))
5511 break; // Can't use this datatype.
5513 case TargetLowering::Custom:
5514 OpToUse = ISD::SINT_TO_FP;
5518 if (isSigned) continue;
5520 // If the target supports UINT_TO_FP of this type, use it.
5521 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5523 case TargetLowering::Legal:
5524 if (!TLI.isTypeLegal(NewInTy))
5525 break; // Can't use this datatype.
5527 case TargetLowering::Custom:
5528 OpToUse = ISD::UINT_TO_FP;
5533 // Otherwise, try a larger type.
5536 // Okay, we found the operation and type to use. Zero extend our input to the
5537 // desired type then run the operation on it.
5538 return DAG.getNode(OpToUse, DestVT,
5539 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5543 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5544 /// FP_TO_*INT operation of the specified operand when the target requests that
5545 /// we promote it. At this point, we know that the result and operand types are
5546 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5547 /// operation that returns a larger result.
5548 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5549 MVT::ValueType DestVT,
5551 // First step, figure out the appropriate FP_TO*INT operation to use.
5552 MVT::ValueType NewOutTy = DestVT;
5554 unsigned OpToUse = 0;
5556 // Scan for the appropriate larger type to use.
5558 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5559 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5561 // If the target supports FP_TO_SINT returning this type, use it.
5562 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5564 case TargetLowering::Legal:
5565 if (!TLI.isTypeLegal(NewOutTy))
5566 break; // Can't use this datatype.
5568 case TargetLowering::Custom:
5569 OpToUse = ISD::FP_TO_SINT;
5574 // If the target supports FP_TO_UINT of this type, use it.
5575 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5577 case TargetLowering::Legal:
5578 if (!TLI.isTypeLegal(NewOutTy))
5579 break; // Can't use this datatype.
5581 case TargetLowering::Custom:
5582 OpToUse = ISD::FP_TO_UINT;
5587 // Otherwise, try a larger type.
5591 // Okay, we found the operation and type to use.
5592 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5594 // If the operation produces an invalid type, it must be custom lowered. Use
5595 // the target lowering hooks to expand it. Just keep the low part of the
5596 // expanded operation, we know that we're truncating anyway.
5597 if (getTypeAction(NewOutTy) == Expand) {
5598 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5599 assert(Operation.Val && "Didn't return anything");
5602 // Truncate the result of the extended FP_TO_*INT operation to the desired
5604 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5607 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5609 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5610 MVT::ValueType VT = Op.getValueType();
5611 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5612 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5614 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5616 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5617 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5618 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5620 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5621 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5622 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5623 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5624 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5625 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5626 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5627 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5628 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5630 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5631 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5632 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5633 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5634 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5635 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5636 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5637 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5638 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5639 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5640 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5641 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5642 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5643 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5644 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5645 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5646 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5647 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5648 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5649 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5650 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5654 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5656 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5658 default: assert(0 && "Cannot expand this yet!");
5660 static const uint64_t mask[6] = {
5661 0x5555555555555555ULL, 0x3333333333333333ULL,
5662 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5663 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5665 MVT::ValueType VT = Op.getValueType();
5666 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5667 unsigned len = MVT::getSizeInBits(VT);
5668 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5669 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5670 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5671 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5672 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5673 DAG.getNode(ISD::AND, VT,
5674 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5679 // for now, we do this:
5680 // x = x | (x >> 1);
5681 // x = x | (x >> 2);
5683 // x = x | (x >>16);
5684 // x = x | (x >>32); // for 64-bit input
5685 // return popcount(~x);
5687 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5688 MVT::ValueType VT = Op.getValueType();
5689 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5690 unsigned len = MVT::getSizeInBits(VT);
5691 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5692 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5693 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5695 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5696 return DAG.getNode(ISD::CTPOP, VT, Op);
5699 // for now, we use: { return popcount(~x & (x - 1)); }
5700 // unless the target has ctlz but not ctpop, in which case we use:
5701 // { return 32 - nlz(~x & (x-1)); }
5702 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5703 MVT::ValueType VT = Op.getValueType();
5704 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5705 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5706 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5707 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5708 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5709 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5710 TLI.isOperationLegal(ISD::CTLZ, VT))
5711 return DAG.getNode(ISD::SUB, VT,
5712 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5713 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5714 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5719 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5720 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5721 /// LegalizeNodes map is filled in for any results that are not expanded, the
5722 /// ExpandedNodes map is filled in for any results that are expanded, and the
5723 /// Lo/Hi values are returned.
5724 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5725 MVT::ValueType VT = Op.getValueType();
5726 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5727 SDNode *Node = Op.Val;
5728 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5729 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5730 MVT::isVector(VT)) &&
5731 "Cannot expand to FP value or to larger int value!");
5733 // See if we already expanded it.
5734 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5735 = ExpandedNodes.find(Op);
5736 if (I != ExpandedNodes.end()) {
5737 Lo = I->second.first;
5738 Hi = I->second.second;
5742 switch (Node->getOpcode()) {
5743 case ISD::CopyFromReg:
5744 assert(0 && "CopyFromReg must be legal!");
5745 case ISD::FP_ROUND_INREG:
5746 if (VT == MVT::ppcf128 &&
5747 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5748 TargetLowering::Custom) {
5749 SDOperand SrcLo, SrcHi, Src;
5750 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5751 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5752 SDOperand Result = TLI.LowerOperation(
5753 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5754 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5755 Lo = Result.Val->getOperand(0);
5756 Hi = Result.Val->getOperand(1);
5762 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5764 assert(0 && "Do not know how to expand this operator!");
5766 case ISD::EXTRACT_ELEMENT:
5767 ExpandOp(Node->getOperand(0), Lo, Hi);
5768 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5769 return ExpandOp(Hi, Lo, Hi);
5770 return ExpandOp(Lo, Lo, Hi);
5771 case ISD::EXTRACT_VECTOR_ELT:
5772 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5773 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5774 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5775 return ExpandOp(Lo, Lo, Hi);
5777 NVT = TLI.getTypeToExpandTo(VT);
5778 Lo = DAG.getNode(ISD::UNDEF, NVT);
5779 Hi = DAG.getNode(ISD::UNDEF, NVT);
5781 case ISD::Constant: {
5782 unsigned NVTBits = MVT::getSizeInBits(NVT);
5783 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5784 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5785 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5788 case ISD::ConstantFP: {
5789 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5790 if (CFP->getValueType(0) == MVT::ppcf128) {
5791 APInt api = CFP->getValueAPF().convertToAPInt();
5792 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5794 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5798 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5799 if (getTypeAction(Lo.getValueType()) == Expand)
5800 ExpandOp(Lo, Lo, Hi);
5803 case ISD::BUILD_PAIR:
5804 // Return the operands.
5805 Lo = Node->getOperand(0);
5806 Hi = Node->getOperand(1);
5809 case ISD::MERGE_VALUES:
5810 if (Node->getNumValues() == 1) {
5811 ExpandOp(Op.getOperand(0), Lo, Hi);
5814 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5815 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5816 Op.getValue(1).getValueType() == MVT::Other &&
5817 "unhandled MERGE_VALUES");
5818 ExpandOp(Op.getOperand(0), Lo, Hi);
5819 // Remember that we legalized the chain.
5820 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5823 case ISD::SIGN_EXTEND_INREG:
5824 ExpandOp(Node->getOperand(0), Lo, Hi);
5825 // sext_inreg the low part if needed.
5826 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5828 // The high part gets the sign extension from the lo-part. This handles
5829 // things like sextinreg V:i64 from i8.
5830 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5831 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5832 TLI.getShiftAmountTy()));
5836 ExpandOp(Node->getOperand(0), Lo, Hi);
5837 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5838 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5844 ExpandOp(Node->getOperand(0), Lo, Hi);
5845 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5846 DAG.getNode(ISD::CTPOP, NVT, Lo),
5847 DAG.getNode(ISD::CTPOP, NVT, Hi));
5848 Hi = DAG.getConstant(0, NVT);
5852 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5853 ExpandOp(Node->getOperand(0), Lo, Hi);
5854 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5855 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5856 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
5858 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5859 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5861 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5862 Hi = DAG.getConstant(0, NVT);
5867 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5868 ExpandOp(Node->getOperand(0), Lo, Hi);
5869 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5870 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5871 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
5873 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5874 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5876 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5877 Hi = DAG.getConstant(0, NVT);
5882 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5883 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5884 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5885 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5887 // Remember that we legalized the chain.
5888 Hi = LegalizeOp(Hi);
5889 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5890 if (TLI.isBigEndian())
5896 LoadSDNode *LD = cast<LoadSDNode>(Node);
5897 SDOperand Ch = LD->getChain(); // Legalize the chain.
5898 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5899 ISD::LoadExtType ExtType = LD->getExtensionType();
5900 int SVOffset = LD->getSrcValueOffset();
5901 unsigned Alignment = LD->getAlignment();
5902 bool isVolatile = LD->isVolatile();
5904 if (ExtType == ISD::NON_EXTLOAD) {
5905 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5906 isVolatile, Alignment);
5907 if (VT == MVT::f32 || VT == MVT::f64) {
5908 // f32->i32 or f64->i64 one to one expansion.
5909 // Remember that we legalized the chain.
5910 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5911 // Recursively expand the new load.
5912 if (getTypeAction(NVT) == Expand)
5913 ExpandOp(Lo, Lo, Hi);
5917 // Increment the pointer to the other half.
5918 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5919 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5920 DAG.getIntPtrConstant(IncrementSize));
5921 SVOffset += IncrementSize;
5922 Alignment = MinAlign(Alignment, IncrementSize);
5923 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5924 isVolatile, Alignment);
5926 // Build a factor node to remember that this load is independent of the
5928 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5931 // Remember that we legalized the chain.
5932 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5933 if (TLI.isBigEndian())
5936 MVT::ValueType EVT = LD->getMemoryVT();
5938 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5939 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5940 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5941 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5942 SVOffset, isVolatile, Alignment);
5943 // Remember that we legalized the chain.
5944 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5945 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5950 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5951 SVOffset, isVolatile, Alignment);
5953 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5954 SVOffset, EVT, isVolatile,
5957 // Remember that we legalized the chain.
5958 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5960 if (ExtType == ISD::SEXTLOAD) {
5961 // The high part is obtained by SRA'ing all but one of the bits of the
5963 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
5964 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5965 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
5966 } else if (ExtType == ISD::ZEXTLOAD) {
5967 // The high part is just a zero.
5968 Hi = DAG.getConstant(0, NVT);
5969 } else /* if (ExtType == ISD::EXTLOAD) */ {
5970 // The high part is undefined.
5971 Hi = DAG.getNode(ISD::UNDEF, NVT);
5978 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
5979 SDOperand LL, LH, RL, RH;
5980 ExpandOp(Node->getOperand(0), LL, LH);
5981 ExpandOp(Node->getOperand(1), RL, RH);
5982 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
5983 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
5987 SDOperand LL, LH, RL, RH;
5988 ExpandOp(Node->getOperand(1), LL, LH);
5989 ExpandOp(Node->getOperand(2), RL, RH);
5990 if (getTypeAction(NVT) == Expand)
5991 NVT = TLI.getTypeToExpandTo(NVT);
5992 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
5994 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
5997 case ISD::SELECT_CC: {
5998 SDOperand TL, TH, FL, FH;
5999 ExpandOp(Node->getOperand(2), TL, TH);
6000 ExpandOp(Node->getOperand(3), FL, FH);
6001 if (getTypeAction(NVT) == Expand)
6002 NVT = TLI.getTypeToExpandTo(NVT);
6003 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6004 Node->getOperand(1), TL, FL, Node->getOperand(4));
6006 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6007 Node->getOperand(1), TH, FH, Node->getOperand(4));
6010 case ISD::ANY_EXTEND:
6011 // The low part is any extension of the input (which degenerates to a copy).
6012 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6013 // The high part is undefined.
6014 Hi = DAG.getNode(ISD::UNDEF, NVT);
6016 case ISD::SIGN_EXTEND: {
6017 // The low part is just a sign extension of the input (which degenerates to
6019 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6021 // The high part is obtained by SRA'ing all but one of the bits of the lo
6023 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6024 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6025 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6028 case ISD::ZERO_EXTEND:
6029 // The low part is just a zero extension of the input (which degenerates to
6031 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6033 // The high part is just a zero.
6034 Hi = DAG.getConstant(0, NVT);
6037 case ISD::TRUNCATE: {
6038 // The input value must be larger than this value. Expand *it*.
6040 ExpandOp(Node->getOperand(0), NewLo, Hi);
6042 // The low part is now either the right size, or it is closer. If not the
6043 // right size, make an illegal truncate so we recursively expand it.
6044 if (NewLo.getValueType() != Node->getValueType(0))
6045 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6046 ExpandOp(NewLo, Lo, Hi);
6050 case ISD::BIT_CONVERT: {
6052 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6053 // If the target wants to, allow it to lower this itself.
6054 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6055 case Expand: assert(0 && "cannot expand FP!");
6056 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6057 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6059 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6062 // f32 / f64 must be expanded to i32 / i64.
6063 if (VT == MVT::f32 || VT == MVT::f64) {
6064 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6065 if (getTypeAction(NVT) == Expand)
6066 ExpandOp(Lo, Lo, Hi);
6070 // If source operand will be expanded to the same type as VT, i.e.
6071 // i64 <- f64, i32 <- f32, expand the source operand instead.
6072 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6073 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6074 ExpandOp(Node->getOperand(0), Lo, Hi);
6078 // Turn this into a load/store pair by default.
6080 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6082 ExpandOp(Tmp, Lo, Hi);
6086 case ISD::READCYCLECOUNTER: {
6087 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6088 TargetLowering::Custom &&
6089 "Must custom expand ReadCycleCounter");
6090 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6091 assert(Tmp.Val && "Node must be custom expanded!");
6092 ExpandOp(Tmp.getValue(0), Lo, Hi);
6093 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6094 LegalizeOp(Tmp.getValue(1)));
6098 case ISD::ATOMIC_LCS: {
6099 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6100 assert(Tmp.Val && "Node must be custom expanded!");
6101 ExpandOp(Tmp.getValue(0), Lo, Hi);
6102 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6103 LegalizeOp(Tmp.getValue(1)));
6109 // These operators cannot be expanded directly, emit them as calls to
6110 // library functions.
6111 case ISD::FP_TO_SINT: {
6112 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6114 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6115 case Expand: assert(0 && "cannot expand FP!");
6116 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6117 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6120 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6122 // Now that the custom expander is done, expand the result, which is still
6125 ExpandOp(Op, Lo, Hi);
6130 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6131 if (Node->getOperand(0).getValueType() == MVT::f32)
6132 LC = RTLIB::FPTOSINT_F32_I64;
6133 else if (Node->getOperand(0).getValueType() == MVT::f64)
6134 LC = RTLIB::FPTOSINT_F64_I64;
6135 else if (Node->getOperand(0).getValueType() == MVT::f80)
6136 LC = RTLIB::FPTOSINT_F80_I64;
6137 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6138 LC = RTLIB::FPTOSINT_PPCF128_I64;
6139 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6140 false/*sign irrelevant*/, Hi);
6144 case ISD::FP_TO_UINT: {
6145 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6147 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6148 case Expand: assert(0 && "cannot expand FP!");
6149 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6150 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6153 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6155 // Now that the custom expander is done, expand the result.
6157 ExpandOp(Op, Lo, Hi);
6162 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6163 if (Node->getOperand(0).getValueType() == MVT::f32)
6164 LC = RTLIB::FPTOUINT_F32_I64;
6165 else if (Node->getOperand(0).getValueType() == MVT::f64)
6166 LC = RTLIB::FPTOUINT_F64_I64;
6167 else if (Node->getOperand(0).getValueType() == MVT::f80)
6168 LC = RTLIB::FPTOUINT_F80_I64;
6169 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6170 LC = RTLIB::FPTOUINT_PPCF128_I64;
6171 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
6172 false/*sign irrelevant*/, Hi);
6177 // If the target wants custom lowering, do so.
6178 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6179 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6180 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6181 Op = TLI.LowerOperation(Op, DAG);
6183 // Now that the custom expander is done, expand the result, which is
6185 ExpandOp(Op, Lo, Hi);
6190 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6191 // this X << 1 as X+X.
6192 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6193 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6194 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6195 SDOperand LoOps[2], HiOps[3];
6196 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6197 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6198 LoOps[1] = LoOps[0];
6199 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6201 HiOps[1] = HiOps[0];
6202 HiOps[2] = Lo.getValue(1);
6203 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6208 // If we can emit an efficient shift operation, do so now.
6209 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6212 // If this target supports SHL_PARTS, use it.
6213 TargetLowering::LegalizeAction Action =
6214 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6215 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6216 Action == TargetLowering::Custom) {
6217 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6221 // Otherwise, emit a libcall.
6222 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
6223 false/*left shift=unsigned*/, Hi);
6228 // If the target wants custom lowering, do so.
6229 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6230 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6231 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6232 Op = TLI.LowerOperation(Op, DAG);
6234 // Now that the custom expander is done, expand the result, which is
6236 ExpandOp(Op, Lo, Hi);
6241 // If we can emit an efficient shift operation, do so now.
6242 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6245 // If this target supports SRA_PARTS, use it.
6246 TargetLowering::LegalizeAction Action =
6247 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6248 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6249 Action == TargetLowering::Custom) {
6250 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6254 // Otherwise, emit a libcall.
6255 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
6256 true/*ashr is signed*/, Hi);
6261 // If the target wants custom lowering, do so.
6262 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6263 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6264 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6265 Op = TLI.LowerOperation(Op, DAG);
6267 // Now that the custom expander is done, expand the result, which is
6269 ExpandOp(Op, Lo, Hi);
6274 // If we can emit an efficient shift operation, do so now.
6275 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6278 // If this target supports SRL_PARTS, use it.
6279 TargetLowering::LegalizeAction Action =
6280 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6281 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6282 Action == TargetLowering::Custom) {
6283 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6287 // Otherwise, emit a libcall.
6288 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
6289 false/*lshr is unsigned*/, Hi);
6295 // If the target wants to custom expand this, let them.
6296 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6297 TargetLowering::Custom) {
6298 Op = TLI.LowerOperation(Op, DAG);
6300 ExpandOp(Op, Lo, Hi);
6305 // Expand the subcomponents.
6306 SDOperand LHSL, LHSH, RHSL, RHSH;
6307 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6308 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6309 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6310 SDOperand LoOps[2], HiOps[3];
6315 if (Node->getOpcode() == ISD::ADD) {
6316 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6317 HiOps[2] = Lo.getValue(1);
6318 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6320 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6321 HiOps[2] = Lo.getValue(1);
6322 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6329 // Expand the subcomponents.
6330 SDOperand LHSL, LHSH, RHSL, RHSH;
6331 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6332 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6333 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6334 SDOperand LoOps[2] = { LHSL, RHSL };
6335 SDOperand HiOps[3] = { LHSH, RHSH };
6337 if (Node->getOpcode() == ISD::ADDC) {
6338 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6339 HiOps[2] = Lo.getValue(1);
6340 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6342 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6343 HiOps[2] = Lo.getValue(1);
6344 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6346 // Remember that we legalized the flag.
6347 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6352 // Expand the subcomponents.
6353 SDOperand LHSL, LHSH, RHSL, RHSH;
6354 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6355 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6356 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6357 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6358 SDOperand HiOps[3] = { LHSH, RHSH };
6360 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6361 HiOps[2] = Lo.getValue(1);
6362 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6364 // Remember that we legalized the flag.
6365 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6369 // If the target wants to custom expand this, let them.
6370 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6371 SDOperand New = TLI.LowerOperation(Op, DAG);
6373 ExpandOp(New, Lo, Hi);
6378 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6379 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6380 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6381 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6382 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6383 SDOperand LL, LH, RL, RH;
6384 ExpandOp(Node->getOperand(0), LL, LH);
6385 ExpandOp(Node->getOperand(1), RL, RH);
6386 unsigned OuterBitSize = Op.getValueSizeInBits();
6387 unsigned InnerBitSize = RH.getValueSizeInBits();
6388 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6389 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6390 if (DAG.MaskedValueIsZero(Op.getOperand(0),
6391 APInt::getHighBitsSet(OuterBitSize, LHSSB)) &&
6392 DAG.MaskedValueIsZero(Op.getOperand(1),
6393 APInt::getHighBitsSet(OuterBitSize, RHSSB))) {
6394 // The inputs are both zero-extended.
6396 // We can emit a umul_lohi.
6397 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6398 Hi = SDOperand(Lo.Val, 1);
6402 // We can emit a mulhu+mul.
6403 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6404 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6408 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6409 // The input values are both sign-extended.
6411 // We can emit a smul_lohi.
6412 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6413 Hi = SDOperand(Lo.Val, 1);
6417 // We can emit a mulhs+mul.
6418 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6419 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6424 // Lo,Hi = umul LHS, RHS.
6425 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6426 DAG.getVTList(NVT, NVT), LL, RL);
6428 Hi = UMulLOHI.getValue(1);
6429 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6430 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6431 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6432 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6436 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6437 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6438 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6439 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6440 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6441 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6446 // If nothing else, we can make a libcall.
6447 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
6448 false/*sign irrelevant*/, Hi);
6452 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
6455 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
6458 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
6461 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
6465 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::ADD_F32,
6468 RTLIB::ADD_PPCF128)),
6472 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::SUB_F32,
6475 RTLIB::SUB_PPCF128)),
6479 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::MUL_F32,
6482 RTLIB::MUL_PPCF128)),
6486 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::DIV_F32,
6489 RTLIB::DIV_PPCF128)),
6492 case ISD::FP_EXTEND:
6493 if (VT == MVT::ppcf128) {
6494 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6495 Node->getOperand(0).getValueType()==MVT::f64);
6496 const uint64_t zero = 0;
6497 if (Node->getOperand(0).getValueType()==MVT::f32)
6498 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6500 Hi = Node->getOperand(0);
6501 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6504 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
6507 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
6510 Lo = ExpandLibCall(TLI.getLibcallName(GetFPLibCall(VT, RTLIB::POWI_F32,
6513 RTLIB::POWI_PPCF128)),
6519 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6520 switch(Node->getOpcode()) {
6522 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6523 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6526 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6527 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6530 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6531 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6533 default: assert(0 && "Unreachable!");
6535 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
6539 if (VT == MVT::ppcf128) {
6541 ExpandOp(Node->getOperand(0), Lo, Tmp);
6542 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6543 // lo = hi==fabs(hi) ? lo : -lo;
6544 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6545 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6546 DAG.getCondCode(ISD::SETEQ));
6549 SDOperand Mask = (VT == MVT::f64)
6550 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6551 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6552 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6553 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6554 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6555 if (getTypeAction(NVT) == Expand)
6556 ExpandOp(Lo, Lo, Hi);
6560 if (VT == MVT::ppcf128) {
6561 ExpandOp(Node->getOperand(0), Lo, Hi);
6562 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6563 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6566 SDOperand Mask = (VT == MVT::f64)
6567 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6568 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6569 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6570 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6571 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6572 if (getTypeAction(NVT) == Expand)
6573 ExpandOp(Lo, Lo, Hi);
6576 case ISD::FCOPYSIGN: {
6577 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6578 if (getTypeAction(NVT) == Expand)
6579 ExpandOp(Lo, Lo, Hi);
6582 case ISD::SINT_TO_FP:
6583 case ISD::UINT_TO_FP: {
6584 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6585 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6586 if (VT == MVT::ppcf128 && SrcVT != MVT::i64) {
6587 static const uint64_t zero = 0;
6589 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6590 Node->getOperand(0)));
6591 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6593 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6594 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6595 Node->getOperand(0)));
6596 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6597 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6598 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6599 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6600 DAG.getConstant(0, MVT::i32),
6601 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6603 APFloat(APInt(128, 2, TwoE32)),
6606 DAG.getCondCode(ISD::SETLT)),
6611 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6612 // si64->ppcf128 done by libcall, below
6613 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6614 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6616 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6617 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6618 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6619 DAG.getConstant(0, MVT::i64),
6620 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6622 APFloat(APInt(128, 2, TwoE64)),
6625 DAG.getCondCode(ISD::SETLT)),
6629 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6630 if (Node->getOperand(0).getValueType() == MVT::i64) {
6632 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
6633 else if (VT == MVT::f64)
6634 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
6635 else if (VT == MVT::f80) {
6637 LC = RTLIB::SINTTOFP_I64_F80;
6639 else if (VT == MVT::ppcf128) {
6641 LC = RTLIB::SINTTOFP_I64_PPCF128;
6645 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
6647 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
6650 // Promote the operand if needed.
6651 if (getTypeAction(SrcVT) == Promote) {
6652 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6654 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6655 DAG.getValueType(SrcVT))
6656 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6657 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6660 const char *LibCall = TLI.getLibcallName(LC);
6662 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
6664 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6665 Node->getOperand(0));
6666 if (getTypeAction(Lo.getValueType()) == Expand)
6667 ExpandOp(Lo, Lo, Hi);
6673 // Make sure the resultant values have been legalized themselves, unless this
6674 // is a type that requires multi-step expansion.
6675 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6676 Lo = LegalizeOp(Lo);
6678 // Don't legalize the high part if it is expanded to a single node.
6679 Hi = LegalizeOp(Hi);
6682 // Remember in a map if the values will be reused later.
6683 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6684 assert(isNew && "Value already expanded?!?");
6687 /// SplitVectorOp - Given an operand of vector type, break it down into
6688 /// two smaller values, still of vector type.
6689 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6691 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6692 SDNode *Node = Op.Val;
6693 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6694 assert(NumElements > 1 && "Cannot split a single element vector!");
6696 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6698 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6699 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6701 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6702 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6704 // See if we already split it.
6705 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6706 = SplitNodes.find(Op);
6707 if (I != SplitNodes.end()) {
6708 Lo = I->second.first;
6709 Hi = I->second.second;
6713 switch (Node->getOpcode()) {
6718 assert(0 && "Unhandled operation in SplitVectorOp!");
6720 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6721 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6723 case ISD::BUILD_PAIR:
6724 Lo = Node->getOperand(0);
6725 Hi = Node->getOperand(1);
6727 case ISD::INSERT_VECTOR_ELT: {
6728 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6729 unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
6730 SDOperand ScalarOp = Node->getOperand(1);
6731 if (Index < NewNumElts_Lo)
6732 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6733 DAG.getConstant(Index, TLI.getPointerTy()));
6735 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6736 DAG.getConstant(Index - NewNumElts_Lo,
6737 TLI.getPointerTy()));
6740 case ISD::VECTOR_SHUFFLE: {
6741 // Build the low part.
6742 SDOperand Mask = Node->getOperand(2);
6743 SmallVector<SDOperand, 8> Ops;
6744 MVT::ValueType PtrVT = TLI.getPointerTy();
6746 // Insert all of the elements from the input that are needed. We use
6747 // buildvector of extractelement here because the input vectors will have
6748 // to be legalized, so this makes the code simpler.
6749 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6750 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6751 SDOperand InVec = Node->getOperand(0);
6752 if (Idx >= NumElements) {
6753 InVec = Node->getOperand(1);
6756 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6757 DAG.getConstant(Idx, PtrVT)));
6759 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6762 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6763 unsigned Idx = cast<ConstantSDNode>(Mask.getOperand(i))->getValue();
6764 SDOperand InVec = Node->getOperand(0);
6765 if (Idx >= NumElements) {
6766 InVec = Node->getOperand(1);
6769 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6770 DAG.getConstant(Idx, PtrVT)));
6772 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6775 case ISD::BUILD_VECTOR: {
6776 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6777 Node->op_begin()+NewNumElts_Lo);
6778 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6780 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6782 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6785 case ISD::CONCAT_VECTORS: {
6786 // FIXME: Handle non-power-of-two vectors?
6787 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6788 if (NewNumSubvectors == 1) {
6789 Lo = Node->getOperand(0);
6790 Hi = Node->getOperand(1);
6792 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6793 Node->op_begin()+NewNumSubvectors);
6794 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6796 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6798 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6803 SDOperand Cond = Node->getOperand(0);
6805 SDOperand LL, LH, RL, RH;
6806 SplitVectorOp(Node->getOperand(1), LL, LH);
6807 SplitVectorOp(Node->getOperand(2), RL, RH);
6809 if (MVT::isVector(Cond.getValueType())) {
6810 // Handle a vector merge.
6812 SplitVectorOp(Cond, CL, CH);
6813 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6814 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6816 // Handle a simple select with vector operands.
6817 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6818 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6838 SDOperand LL, LH, RL, RH;
6839 SplitVectorOp(Node->getOperand(0), LL, LH);
6840 SplitVectorOp(Node->getOperand(1), RL, RH);
6842 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6843 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6848 SplitVectorOp(Node->getOperand(0), L, H);
6850 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6851 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6862 case ISD::FP_TO_SINT:
6863 case ISD::FP_TO_UINT:
6864 case ISD::SINT_TO_FP:
6865 case ISD::UINT_TO_FP: {
6867 SplitVectorOp(Node->getOperand(0), L, H);
6869 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6870 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6874 LoadSDNode *LD = cast<LoadSDNode>(Node);
6875 SDOperand Ch = LD->getChain();
6876 SDOperand Ptr = LD->getBasePtr();
6877 const Value *SV = LD->getSrcValue();
6878 int SVOffset = LD->getSrcValueOffset();
6879 unsigned Alignment = LD->getAlignment();
6880 bool isVolatile = LD->isVolatile();
6882 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6883 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6884 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6885 DAG.getIntPtrConstant(IncrementSize));
6886 SVOffset += IncrementSize;
6887 Alignment = MinAlign(Alignment, IncrementSize);
6888 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6890 // Build a factor node to remember that this load is independent of the
6892 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6895 // Remember that we legalized the chain.
6896 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6899 case ISD::BIT_CONVERT: {
6900 // We know the result is a vector. The input may be either a vector or a
6902 SDOperand InOp = Node->getOperand(0);
6903 if (!MVT::isVector(InOp.getValueType()) ||
6904 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6905 // The input is a scalar or single-element vector.
6906 // Lower to a store/load so that it can be split.
6907 // FIXME: this could be improved probably.
6908 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6909 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6911 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6913 PseudoSourceValue::getFixedStack(),
6915 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6916 PseudoSourceValue::getFixedStack(),
6919 // Split the vector and convert each of the pieces now.
6920 SplitVectorOp(InOp, Lo, Hi);
6921 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6922 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6927 // Remember in a map if the values will be reused later.
6929 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6930 assert(isNew && "Value already split?!?");
6934 /// ScalarizeVectorOp - Given an operand of single-element vector type
6935 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6936 /// scalar (e.g. f32) value.
6937 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6938 assert(MVT::isVector(Op.getValueType()) &&
6939 "Bad ScalarizeVectorOp invocation!");
6940 SDNode *Node = Op.Val;
6941 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6942 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6944 // See if we already scalarized it.
6945 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
6946 if (I != ScalarizedNodes.end()) return I->second;
6949 switch (Node->getOpcode()) {
6952 Node->dump(&DAG); cerr << "\n";
6954 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
6971 Result = DAG.getNode(Node->getOpcode(),
6973 ScalarizeVectorOp(Node->getOperand(0)),
6974 ScalarizeVectorOp(Node->getOperand(1)));
6981 Result = DAG.getNode(Node->getOpcode(),
6983 ScalarizeVectorOp(Node->getOperand(0)));
6986 Result = DAG.getNode(Node->getOpcode(),
6988 ScalarizeVectorOp(Node->getOperand(0)),
6989 Node->getOperand(1));
6992 LoadSDNode *LD = cast<LoadSDNode>(Node);
6993 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
6994 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
6996 const Value *SV = LD->getSrcValue();
6997 int SVOffset = LD->getSrcValueOffset();
6998 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
6999 LD->isVolatile(), LD->getAlignment());
7001 // Remember that we legalized the chain.
7002 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7005 case ISD::BUILD_VECTOR:
7006 Result = Node->getOperand(0);
7008 case ISD::INSERT_VECTOR_ELT:
7009 // Returning the inserted scalar element.
7010 Result = Node->getOperand(1);
7012 case ISD::CONCAT_VECTORS:
7013 assert(Node->getOperand(0).getValueType() == NewVT &&
7014 "Concat of non-legal vectors not yet supported!");
7015 Result = Node->getOperand(0);
7017 case ISD::VECTOR_SHUFFLE: {
7018 // Figure out if the scalar is the LHS or RHS and return it.
7019 SDOperand EltNum = Node->getOperand(2).getOperand(0);
7020 if (cast<ConstantSDNode>(EltNum)->getValue())
7021 Result = ScalarizeVectorOp(Node->getOperand(1));
7023 Result = ScalarizeVectorOp(Node->getOperand(0));
7026 case ISD::EXTRACT_SUBVECTOR:
7027 Result = Node->getOperand(0);
7028 assert(Result.getValueType() == NewVT);
7030 case ISD::BIT_CONVERT:
7031 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
7034 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7035 ScalarizeVectorOp(Op.getOperand(1)),
7036 ScalarizeVectorOp(Op.getOperand(2)));
7040 if (TLI.isTypeLegal(NewVT))
7041 Result = LegalizeOp(Result);
7042 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7043 assert(isNew && "Value already scalarized?");
7048 // SelectionDAG::Legalize - This is the entry point for the file.
7050 void SelectionDAG::Legalize() {
7051 if (ViewLegalizeDAGs) viewGraph();
7053 /// run - This is the main entry point to this class.
7055 SelectionDAGLegalize(*this).LegalizeDAG();