1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 bool TypesNeedLegalizing;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
73 /// IsLegalizingCallArguments - This member is used only for the purpose
74 /// of providing assert to check for LegalizeTypes because legalizing an
75 /// operation might introduce call nodes that might need type legalization.
76 bool IsLegalizingCallArgs;
79 Legal, // The target natively supports this operation.
80 Promote, // This operation should be executed in a larger type.
81 Expand // Try to expand this to other ops, otherwise use a libcall.
84 /// ValueTypeActions - This is a bitvector that contains two bits for each
85 /// value type, where the two bits correspond to the LegalizeAction enum.
86 /// This can be queried with "getTypeAction(VT)".
87 TargetLowering::ValueTypeActionImpl ValueTypeActions;
89 /// LegalizedNodes - For nodes that are of legal width, and that have more
90 /// than one use, this map indicates what regularized operand to use. This
91 /// allows us to avoid legalizing the same thing more than once.
92 DenseMap<SDValue, SDValue> LegalizedNodes;
94 /// PromotedNodes - For nodes that are below legal width, and that have more
95 /// than one use, this map indicates what promoted value to use. This allows
96 /// us to avoid promoting the same thing more than once.
97 DenseMap<SDValue, SDValue> PromotedNodes;
99 /// ExpandedNodes - For nodes that need to be expanded this map indicates
100 /// which operands are the expanded version of the input. This allows
101 /// us to avoid expanding the same node more than once.
102 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
104 /// SplitNodes - For vector nodes that need to be split, this map indicates
105 /// which operands are the split version of the input. This allows us
106 /// to avoid splitting the same node more than once.
107 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
109 /// ScalarizedNodes - For nodes that need to be converted from vector types to
110 /// scalar types, this contains the mapping of ones we have already
111 /// processed to the result.
112 std::map<SDValue, SDValue> ScalarizedNodes;
114 /// WidenNodes - For nodes that need to be widened from one vector type to
115 /// another, this contains the mapping of those that we have already widen.
116 /// This allows us to avoid widening more than once.
117 std::map<SDValue, SDValue> WidenNodes;
119 void AddLegalizedOperand(SDValue From, SDValue To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDValue From, SDValue To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
132 void AddWidenedOperand(SDValue From, SDValue To) {
133 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
134 assert(isNew && "Got into the map somehow?");
136 // If someone requests legalization of the new node, return itself.
137 LegalizedNodes.insert(std::make_pair(To, To));
141 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
144 /// getTypeAction - Return how we should legalize values of this type, either
145 /// it is already legal or we need to expand it into multiple registers of
146 /// smaller integer type, or we need to promote it to a larger type.
147 LegalizeAction getTypeAction(MVT VT) const {
148 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
151 /// isTypeLegal - Return true if this type is legal on this target.
153 bool isTypeLegal(MVT VT) const {
154 return getTypeAction(VT) == Legal;
160 /// HandleOp - Legalize, Promote, or Expand the specified operand as
161 /// appropriate for its type.
162 void HandleOp(SDValue Op);
164 /// LegalizeOp - We know that the specified value has a legal type.
165 /// Recursively ensure that the operands have legal types, then return the
167 SDValue LegalizeOp(SDValue O);
169 /// UnrollVectorOp - We know that the given vector has a legal type, however
170 /// the operation it performs is not legal and is an operation that we have
171 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
172 /// operating on each element individually.
173 SDValue UnrollVectorOp(SDValue O);
175 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
176 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
177 /// is necessary to spill the vector being inserted into to memory, perform
178 /// the insert there, and then read the result back.
179 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
180 SDValue Idx, DebugLoc dl);
182 /// PromoteOp - Given an operation that produces a value in an invalid type,
183 /// promote it to compute the value into a larger type. The produced value
184 /// will have the correct bits for the low portion of the register, but no
185 /// guarantee is made about the top bits: it may be zero, sign-extended, or
187 SDValue PromoteOp(SDValue O);
189 /// ExpandOp - Expand the specified SDValue into its two component pieces
190 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
191 /// the LegalizedNodes map is filled in for any results that are not expanded,
192 /// the ExpandedNodes map is filled in for any results that are expanded, and
193 /// the Lo/Hi values are returned. This applies to integer types and Vector
195 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
197 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
198 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
199 /// for the existing elements but no guarantee is made about the new elements
200 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
201 /// when we have an instruction operating on an illegal vector type and we
202 /// want to widen it to do the computation on a legal wider vector type.
203 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
205 /// SplitVectorOp - Given an operand of vector type, break it down into
206 /// two smaller values.
207 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
209 /// ScalarizeVectorOp - Given an operand of single-element vector type
210 /// (e.g. v1f32), convert it into the equivalent operation that returns a
211 /// scalar (e.g. f32) value.
212 SDValue ScalarizeVectorOp(SDValue O);
214 /// Useful 16 element vector type that is used to pass operands for widening.
215 typedef SmallVector<SDValue, 16> SDValueVector;
217 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
218 /// the LdChain contains a single load and false if it contains a token
219 /// factor for multiple loads. It takes
220 /// Result: location to return the result
221 /// LdChain: location to return the load chain
222 /// Op: load operation to widen
223 /// NVT: widen vector result type we want for the load
224 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
225 SDValue Op, MVT NVT);
227 /// Helper genWidenVectorLoads - Helper function to generate a set of
228 /// loads to load a vector with a resulting wider type. It takes
229 /// LdChain: list of chains for the load we have generated
230 /// Chain: incoming chain for the ld vector
231 /// BasePtr: base pointer to load from
232 /// SV: memory disambiguation source value
233 /// SVOffset: memory disambiugation offset
234 /// Alignment: alignment of the memory
235 /// isVolatile: volatile load
236 /// LdWidth: width of memory that we want to load
237 /// ResType: the wider result result type for the resulting loaded vector
238 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
239 SDValue BasePtr, const Value *SV,
240 int SVOffset, unsigned Alignment,
241 bool isVolatile, unsigned LdWidth,
242 MVT ResType, DebugLoc dl);
244 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
245 /// location. It takes
246 /// ST: store node that we want to replace
247 /// Chain: incoming store chain
248 /// BasePtr: base address of where we want to store into
249 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
252 /// Helper genWidenVectorStores - Helper function to generate a set of
253 /// stores to store a widen vector into non widen memory
255 // StChain: list of chains for the stores we have generated
256 // Chain: incoming chain for the ld vector
257 // BasePtr: base pointer to load from
258 // SV: memory disambiguation source value
259 // SVOffset: memory disambiugation offset
260 // Alignment: alignment of the memory
261 // isVolatile: volatile lod
262 // ValOp: value to store
263 // StWidth: width of memory that we want to store
264 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
265 SDValue BasePtr, const Value *SV,
266 int SVOffset, unsigned Alignment,
267 bool isVolatile, SDValue ValOp,
268 unsigned StWidth, DebugLoc dl);
270 /// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
271 /// same shuffle on a vector of NVT. Must not create an illegal shuffle mask.
272 SDValue promoteShuffle(MVT NVT, MVT VT, DebugLoc dl, SDValue N1, SDValue N2,
273 SmallVectorImpl<int> &Mask) const;
275 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
276 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
278 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
280 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
282 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
284 LegalizeSetCCOperands(LHS, RHS, CC, dl);
285 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
288 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
290 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
292 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
293 SDValue ExpandBUILD_VECTOR(SDNode *Node);
294 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
295 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
296 SDValue Op, DebugLoc dl);
297 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
299 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
301 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
304 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
305 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
306 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
307 SDValue &Lo, SDValue &Hi, DebugLoc dl);
308 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
309 SDValue &Lo, SDValue &Hi, DebugLoc dl);
311 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
312 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
316 /// promoteShuffle - Promote a shuffle mask of a vector VT to perform the
317 /// same shuffle on a vector of NVT. Must not create an illegal shuffle mask.
318 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
319 SDValue SelectionDAGLegalize::promoteShuffle(MVT NVT, MVT VT, DebugLoc dl,
320 SDValue N1, SDValue N2,
321 SmallVectorImpl<int> &Mask) const {
322 MVT EltVT = NVT.getVectorElementType();
323 int NumMaskElts = VT.getVectorNumElements();
324 int NumDestElts = NVT.getVectorNumElements();
325 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
327 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
329 if (NumEltsGrowth == 1)
330 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
332 SmallVector<int, 8> NewMask;
333 for (int i = 0; i != NumMaskElts; ++i) {
335 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
337 NewMask.push_back(-1);
339 NewMask.push_back(Idx * NumEltsGrowth + j);
342 assert((int)NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
343 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
344 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
347 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
348 bool types, bool fast)
349 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
350 Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
351 assert(MVT::LAST_VALUETYPE <= 32 &&
352 "Too many value types for ValueTypeActions to hold!");
355 void SelectionDAGLegalize::LegalizeDAG() {
356 LastCALLSEQ_END = DAG.getEntryNode();
357 IsLegalizingCall = false;
358 IsLegalizingCallArgs = false;
360 // The legalize process is inherently a bottom-up recursive process (users
361 // legalize their uses before themselves). Given infinite stack space, we
362 // could just start legalizing on the root and traverse the whole graph. In
363 // practice however, this causes us to run out of stack space on large basic
364 // blocks. To avoid this problem, compute an ordering of the nodes where each
365 // node is only legalized after all of its operands are legalized.
366 DAG.AssignTopologicalOrder();
367 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
368 E = prior(DAG.allnodes_end()); I != next(E); ++I)
369 HandleOp(SDValue(I, 0));
371 // Finally, it's possible the root changed. Get the new root.
372 SDValue OldRoot = DAG.getRoot();
373 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
374 DAG.setRoot(LegalizedNodes[OldRoot]);
376 ExpandedNodes.clear();
377 LegalizedNodes.clear();
378 PromotedNodes.clear();
380 ScalarizedNodes.clear();
383 // Remove dead nodes now.
384 DAG.RemoveDeadNodes();
388 /// FindCallEndFromCallStart - Given a chained node that is part of a call
389 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
390 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
391 if (Node->getOpcode() == ISD::CALLSEQ_END)
393 if (Node->use_empty())
394 return 0; // No CallSeqEnd
396 // The chain is usually at the end.
397 SDValue TheChain(Node, Node->getNumValues()-1);
398 if (TheChain.getValueType() != MVT::Other) {
399 // Sometimes it's at the beginning.
400 TheChain = SDValue(Node, 0);
401 if (TheChain.getValueType() != MVT::Other) {
402 // Otherwise, hunt for it.
403 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
404 if (Node->getValueType(i) == MVT::Other) {
405 TheChain = SDValue(Node, i);
409 // Otherwise, we walked into a node without a chain.
410 if (TheChain.getValueType() != MVT::Other)
415 for (SDNode::use_iterator UI = Node->use_begin(),
416 E = Node->use_end(); UI != E; ++UI) {
418 // Make sure to only follow users of our token chain.
420 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
421 if (User->getOperand(i) == TheChain)
422 if (SDNode *Result = FindCallEndFromCallStart(User))
428 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
429 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
430 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
431 assert(Node && "Didn't find callseq_start for a call??");
432 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
434 assert(Node->getOperand(0).getValueType() == MVT::Other &&
435 "Node doesn't have a token chain argument!");
436 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
439 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
440 /// see if any uses can reach Dest. If no dest operands can get to dest,
441 /// legalize them, legalize ourself, and return false, otherwise, return true.
443 /// Keep track of the nodes we fine that actually do lead to Dest in
444 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
446 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
447 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
448 if (N == Dest) return true; // N certainly leads to Dest :)
450 // If we've already processed this node and it does lead to Dest, there is no
451 // need to reprocess it.
452 if (NodesLeadingTo.count(N)) return true;
454 // If the first result of this node has been already legalized, then it cannot
456 switch (getTypeAction(N->getValueType(0))) {
458 if (LegalizedNodes.count(SDValue(N, 0))) return false;
461 if (PromotedNodes.count(SDValue(N, 0))) return false;
464 if (ExpandedNodes.count(SDValue(N, 0))) return false;
468 // Okay, this node has not already been legalized. Check and legalize all
469 // operands. If none lead to Dest, then we can legalize this node.
470 bool OperandsLeadToDest = false;
471 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
472 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
473 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
475 if (OperandsLeadToDest) {
476 NodesLeadingTo.insert(N);
480 // Okay, this node looks safe, legalize it and return false.
481 HandleOp(SDValue(N, 0));
485 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
486 /// appropriate for its type.
487 void SelectionDAGLegalize::HandleOp(SDValue Op) {
488 MVT VT = Op.getValueType();
489 // If the type legalizer was run then we should never see any illegal result
490 // types here except for target constants (the type legalizer does not touch
491 // those) or for build vector used as a mask for a vector shuffle.
492 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
493 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
494 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant ||
495 Op.getOpcode() == ISD::BUILD_VECTOR) &&
496 "Illegal type introduced after type legalization?");
497 switch (getTypeAction(VT)) {
498 default: assert(0 && "Bad type action!");
499 case Legal: (void)LegalizeOp(Op); break;
501 if (!VT.isVector()) {
506 // See if we can widen otherwise use Expand to either scalarize or split
507 MVT WidenVT = TLI.getWidenVectorType(VT);
508 if (WidenVT != MVT::Other) {
509 (void) WidenVectorOp(Op, WidenVT);
512 // else fall thru to expand since we can't widen the vector
515 if (!VT.isVector()) {
516 // If this is an illegal scalar, expand it into its two component
519 if (Op.getOpcode() == ISD::TargetConstant)
520 break; // Allow illegal target nodes.
522 } else if (VT.getVectorNumElements() == 1) {
523 // If this is an illegal single element vector, convert it to a
525 (void)ScalarizeVectorOp(Op);
527 // This is an illegal multiple element vector.
528 // Split it in half and legalize both parts.
530 SplitVectorOp(Op, X, Y);
536 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
537 /// a load from the constant pool.
538 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
539 SelectionDAG &DAG, const TargetLowering &TLI) {
541 DebugLoc dl = CFP->getDebugLoc();
543 // If a FP immediate is precise when represented as a float and if the
544 // target can do an extending load from float to double, we put it into
545 // the constant pool as a float, even if it's is statically typed as a
546 // double. This shrinks FP constants and canonicalizes them for targets where
547 // an FP extending load is the same cost as a normal load (such as on the x87
548 // fp stack or PPC FP unit).
549 MVT VT = CFP->getValueType(0);
550 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
552 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
553 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
554 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
559 while (SVT != MVT::f32) {
560 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
561 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
562 // Only do this if the target has a native EXTLOAD instruction from
564 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
565 TLI.ShouldShrinkFPConstant(OrigVT)) {
566 const Type *SType = SVT.getTypeForMVT();
567 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
573 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
574 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
576 return DAG.getExtLoad(ISD::EXTLOAD, dl,
577 OrigVT, DAG.getEntryNode(),
578 CPIdx, PseudoSourceValue::getConstantPool(),
579 0, VT, false, Alignment);
580 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
581 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
585 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
588 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
590 const TargetLowering &TLI) {
591 DebugLoc dl = Node->getDebugLoc();
592 MVT VT = Node->getValueType(0);
593 MVT SrcVT = Node->getOperand(1).getValueType();
594 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
595 "fcopysign expansion only supported for f32 and f64");
596 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
598 // First get the sign bit of second operand.
599 SDValue Mask1 = (SrcVT == MVT::f64)
600 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
601 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
602 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
603 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
604 Node->getOperand(1));
605 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
606 // Shift right or sign-extend it if the two operands have different types.
607 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
609 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
610 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
611 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
612 } else if (SizeDiff < 0) {
613 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
614 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
615 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
618 // Clear the sign bit of first operand.
619 SDValue Mask2 = (VT == MVT::f64)
620 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
621 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
622 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
623 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
624 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
626 // Or the value with the sign bit.
627 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
631 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
633 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
634 const TargetLowering &TLI) {
635 SDValue Chain = ST->getChain();
636 SDValue Ptr = ST->getBasePtr();
637 SDValue Val = ST->getValue();
638 MVT VT = Val.getValueType();
639 int Alignment = ST->getAlignment();
640 int SVOffset = ST->getSrcValueOffset();
641 DebugLoc dl = ST->getDebugLoc();
642 if (ST->getMemoryVT().isFloatingPoint() ||
643 ST->getMemoryVT().isVector()) {
644 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
645 if (TLI.isTypeLegal(intVT)) {
646 // Expand to a bitconvert of the value to the integer type of the
647 // same size, then a (misaligned) int store.
648 // FIXME: Does not handle truncating floating point stores!
649 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
650 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
651 SVOffset, ST->isVolatile(), Alignment);
653 // Do a (aligned) store to a stack slot, then copy from the stack slot
654 // to the final destination using (unaligned) integer loads and stores.
655 MVT StoredVT = ST->getMemoryVT();
657 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
658 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
659 unsigned RegBytes = RegVT.getSizeInBits() / 8;
660 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
662 // Make sure the stack slot is also aligned for the register type.
663 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
665 // Perform the original store, only redirected to the stack slot.
666 SDValue Store = DAG.getTruncStore(Chain, dl,
667 Val, StackPtr, NULL, 0, StoredVT);
668 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
669 SmallVector<SDValue, 8> Stores;
672 // Do all but one copies using the full register width.
673 for (unsigned i = 1; i < NumRegs; i++) {
674 // Load one integer register's worth from the stack slot.
675 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
676 // Store it to the final location. Remember the store.
677 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
678 ST->getSrcValue(), SVOffset + Offset,
680 MinAlign(ST->getAlignment(), Offset)));
681 // Increment the pointers.
683 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
685 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
688 // The last store may be partial. Do a truncating store. On big-endian
689 // machines this requires an extending load from the stack slot to ensure
690 // that the bits are in the right place.
691 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
693 // Load from the stack slot.
694 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
697 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
698 ST->getSrcValue(), SVOffset + Offset,
699 MemVT, ST->isVolatile(),
700 MinAlign(ST->getAlignment(), Offset)));
701 // The order of the stores doesn't matter - say it with a TokenFactor.
702 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
706 assert(ST->getMemoryVT().isInteger() &&
707 !ST->getMemoryVT().isVector() &&
708 "Unaligned store of unknown type.");
709 // Get the half-size VT
711 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
712 int NumBits = NewStoredVT.getSizeInBits();
713 int IncrementSize = NumBits / 8;
715 // Divide the stored value in two parts.
716 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
718 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
720 // Store the two parts
721 SDValue Store1, Store2;
722 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
723 ST->getSrcValue(), SVOffset, NewStoredVT,
724 ST->isVolatile(), Alignment);
725 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
726 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
727 Alignment = MinAlign(Alignment, IncrementSize);
728 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
729 ST->getSrcValue(), SVOffset + IncrementSize,
730 NewStoredVT, ST->isVolatile(), Alignment);
732 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
735 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
737 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
738 const TargetLowering &TLI) {
739 int SVOffset = LD->getSrcValueOffset();
740 SDValue Chain = LD->getChain();
741 SDValue Ptr = LD->getBasePtr();
742 MVT VT = LD->getValueType(0);
743 MVT LoadedVT = LD->getMemoryVT();
744 DebugLoc dl = LD->getDebugLoc();
745 if (VT.isFloatingPoint() || VT.isVector()) {
746 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
747 if (TLI.isTypeLegal(intVT)) {
748 // Expand to a (misaligned) integer load of the same size,
749 // then bitconvert to floating point or vector.
750 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
751 SVOffset, LD->isVolatile(),
753 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
754 if (VT.isFloatingPoint() && LoadedVT != VT)
755 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
757 SDValue Ops[] = { Result, Chain };
758 return DAG.getMergeValues(Ops, 2, dl);
760 // Copy the value to a (aligned) stack slot using (unaligned) integer
761 // loads and stores, then do a (aligned) load from the stack slot.
762 MVT RegVT = TLI.getRegisterType(intVT);
763 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
764 unsigned RegBytes = RegVT.getSizeInBits() / 8;
765 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
767 // Make sure the stack slot is also aligned for the register type.
768 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
770 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
771 SmallVector<SDValue, 8> Stores;
772 SDValue StackPtr = StackBase;
775 // Do all but one copies using the full register width.
776 for (unsigned i = 1; i < NumRegs; i++) {
777 // Load one integer register's worth from the original location.
778 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
779 SVOffset + Offset, LD->isVolatile(),
780 MinAlign(LD->getAlignment(), Offset));
781 // Follow the load with a store to the stack slot. Remember the store.
782 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
784 // Increment the pointers.
786 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
787 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
791 // The last copy may be partial. Do an extending load.
792 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
793 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
794 LD->getSrcValue(), SVOffset + Offset,
795 MemVT, LD->isVolatile(),
796 MinAlign(LD->getAlignment(), Offset));
797 // Follow the load with a store to the stack slot. Remember the store.
798 // On big-endian machines this requires a truncating store to ensure
799 // that the bits end up in the right place.
800 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
803 // The order of the stores doesn't matter - say it with a TokenFactor.
804 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
807 // Finally, perform the original load only redirected to the stack slot.
808 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
811 // Callers expect a MERGE_VALUES node.
812 SDValue Ops[] = { Load, TF };
813 return DAG.getMergeValues(Ops, 2, dl);
816 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
817 "Unaligned load of unsupported type.");
819 // Compute the new VT that is half the size of the old one. This is an
821 unsigned NumBits = LoadedVT.getSizeInBits();
823 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
826 unsigned Alignment = LD->getAlignment();
827 unsigned IncrementSize = NumBits / 8;
828 ISD::LoadExtType HiExtType = LD->getExtensionType();
830 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
831 if (HiExtType == ISD::NON_EXTLOAD)
832 HiExtType = ISD::ZEXTLOAD;
834 // Load the value in two parts
836 if (TLI.isLittleEndian()) {
837 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
838 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
839 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
840 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
841 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
842 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
843 MinAlign(Alignment, IncrementSize));
845 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
846 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
847 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
848 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
849 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
850 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
851 MinAlign(Alignment, IncrementSize));
854 // aggregate the two parts
855 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
856 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
857 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
859 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
862 SDValue Ops[] = { Result, TF };
863 return DAG.getMergeValues(Ops, 2, dl);
866 /// UnrollVectorOp - We know that the given vector has a legal type, however
867 /// the operation it performs is not legal and is an operation that we have
868 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
869 /// operating on each element individually.
870 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
871 MVT VT = Op.getValueType();
872 assert(isTypeLegal(VT) &&
873 "Caller should expand or promote operands that are not legal!");
874 assert(Op.getNode()->getNumValues() == 1 &&
875 "Can't unroll a vector with multiple results!");
876 unsigned NE = VT.getVectorNumElements();
877 MVT EltVT = VT.getVectorElementType();
878 DebugLoc dl = Op.getDebugLoc();
880 SmallVector<SDValue, 8> Scalars;
881 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
882 for (unsigned i = 0; i != NE; ++i) {
883 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
884 SDValue Operand = Op.getOperand(j);
885 MVT OperandVT = Operand.getValueType();
886 if (OperandVT.isVector()) {
887 // A vector operand; extract a single element.
888 MVT OperandEltVT = OperandVT.getVectorElementType();
889 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
892 DAG.getConstant(i, MVT::i32));
894 // A scalar operand; just use it as is.
895 Operands[j] = Operand;
899 switch (Op.getOpcode()) {
901 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
902 &Operands[0], Operands.size()));
909 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
910 DAG.getShiftAmountOperand(Operands[1])));
915 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
918 /// GetFPLibCall - Return the right libcall for the given floating point type.
919 static RTLIB::Libcall GetFPLibCall(MVT VT,
920 RTLIB::Libcall Call_F32,
921 RTLIB::Libcall Call_F64,
922 RTLIB::Libcall Call_F80,
923 RTLIB::Libcall Call_PPCF128) {
925 VT == MVT::f32 ? Call_F32 :
926 VT == MVT::f64 ? Call_F64 :
927 VT == MVT::f80 ? Call_F80 :
928 VT == MVT::ppcf128 ? Call_PPCF128 :
929 RTLIB::UNKNOWN_LIBCALL;
932 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
933 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
934 /// is necessary to spill the vector being inserted into to memory, perform
935 /// the insert there, and then read the result back.
936 SDValue SelectionDAGLegalize::
937 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
943 // If the target doesn't support this, we have to spill the input vector
944 // to a temporary stack slot, update the element, then reload it. This is
945 // badness. We could also load the value into a vector register (either
946 // with a "move to register" or "extload into register" instruction, then
947 // permute it into place, if the idx is a constant and if the idx is
948 // supported by the target.
949 MVT VT = Tmp1.getValueType();
950 MVT EltVT = VT.getVectorElementType();
951 MVT IdxVT = Tmp3.getValueType();
952 MVT PtrVT = TLI.getPointerTy();
953 SDValue StackPtr = DAG.CreateStackTemporary(VT);
955 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
958 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
959 PseudoSourceValue::getFixedStack(SPFI), 0);
961 // Truncate or zero extend offset to target pointer type.
962 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
963 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
964 // Add the offset to the index.
965 unsigned EltSize = EltVT.getSizeInBits()/8;
966 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
967 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
968 // Store the scalar value.
969 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
970 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
971 // Load the updated vector.
972 return DAG.getLoad(VT, dl, Ch, StackPtr,
973 PseudoSourceValue::getFixedStack(SPFI), 0);
977 /// LegalizeOp - We know that the specified value has a legal type, and
978 /// that its operands are legal. Now ensure that the operation itself
979 /// is legal, recursively ensuring that the operands' operations remain
981 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
982 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
985 assert(isTypeLegal(Op.getValueType()) &&
986 "Caller should expand or promote operands that are not legal!");
987 SDNode *Node = Op.getNode();
988 DebugLoc dl = Node->getDebugLoc();
990 // If this operation defines any values that cannot be represented in a
991 // register on this target, make sure to expand or promote them.
992 if (Node->getNumValues() > 1) {
993 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
994 if (getTypeAction(Node->getValueType(i)) != Legal) {
995 HandleOp(Op.getValue(i));
996 assert(LegalizedNodes.count(Op) &&
997 "Handling didn't add legal operands!");
998 return LegalizedNodes[Op];
1002 // Note that LegalizeOp may be reentered even from single-use nodes, which
1003 // means that we always must cache transformed nodes.
1004 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1005 if (I != LegalizedNodes.end()) return I->second;
1007 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1008 SDValue Result = Op;
1009 bool isCustom = false;
1011 switch (Node->getOpcode()) {
1012 case ISD::FrameIndex:
1013 case ISD::EntryToken:
1015 case ISD::BasicBlock:
1016 case ISD::TargetFrameIndex:
1017 case ISD::TargetJumpTable:
1018 case ISD::TargetConstant:
1019 case ISD::TargetConstantFP:
1020 case ISD::TargetConstantPool:
1021 case ISD::TargetGlobalAddress:
1022 case ISD::TargetGlobalTLSAddress:
1023 case ISD::TargetExternalSymbol:
1024 case ISD::VALUETYPE:
1026 case ISD::MEMOPERAND:
1028 case ISD::ARG_FLAGS:
1029 // Primitives must all be legal.
1030 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1031 "This must be legal!");
1034 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1035 // If this is a target node, legalize it by legalizing the operands then
1036 // passing it through.
1037 SmallVector<SDValue, 8> Ops;
1038 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1039 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1041 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1043 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1044 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1045 return Result.getValue(Op.getResNo());
1047 // Otherwise this is an unhandled builtin node. splat.
1049 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1051 assert(0 && "Do not know how to legalize this operator!");
1053 case ISD::GLOBAL_OFFSET_TABLE:
1054 case ISD::GlobalAddress:
1055 case ISD::GlobalTLSAddress:
1056 case ISD::ExternalSymbol:
1057 case ISD::ConstantPool:
1058 case ISD::JumpTable: // Nothing to do.
1059 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1060 default: assert(0 && "This action is not supported yet!");
1061 case TargetLowering::Custom:
1062 Tmp1 = TLI.LowerOperation(Op, DAG);
1063 if (Tmp1.getNode()) Result = Tmp1;
1064 // FALLTHROUGH if the target doesn't want to lower this op after all.
1065 case TargetLowering::Legal:
1069 case ISD::FRAMEADDR:
1070 case ISD::RETURNADDR:
1071 // The only option for these nodes is to custom lower them. If the target
1072 // does not custom lower them, then return zero.
1073 Tmp1 = TLI.LowerOperation(Op, DAG);
1077 Result = DAG.getConstant(0, TLI.getPointerTy());
1079 case ISD::FRAME_TO_ARGS_OFFSET: {
1080 MVT VT = Node->getValueType(0);
1081 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1082 default: assert(0 && "This action is not supported yet!");
1083 case TargetLowering::Custom:
1084 Result = TLI.LowerOperation(Op, DAG);
1085 if (Result.getNode()) break;
1087 case TargetLowering::Legal:
1088 Result = DAG.getConstant(0, VT);
1093 case ISD::EXCEPTIONADDR: {
1094 Tmp1 = LegalizeOp(Node->getOperand(0));
1095 MVT VT = Node->getValueType(0);
1096 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1097 default: assert(0 && "This action is not supported yet!");
1098 case TargetLowering::Expand: {
1099 unsigned Reg = TLI.getExceptionAddressRegister();
1100 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
1103 case TargetLowering::Custom:
1104 Result = TLI.LowerOperation(Op, DAG);
1105 if (Result.getNode()) break;
1107 case TargetLowering::Legal: {
1108 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1109 Result = DAG.getMergeValues(Ops, 2, dl);
1114 if (Result.getNode()->getNumValues() == 1) break;
1116 assert(Result.getNode()->getNumValues() == 2 &&
1117 "Cannot return more than two values!");
1119 // Since we produced two values, make sure to remember that we
1120 // legalized both of them.
1121 Tmp1 = LegalizeOp(Result);
1122 Tmp2 = LegalizeOp(Result.getValue(1));
1123 AddLegalizedOperand(Op.getValue(0), Tmp1);
1124 AddLegalizedOperand(Op.getValue(1), Tmp2);
1125 return Op.getResNo() ? Tmp2 : Tmp1;
1126 case ISD::EHSELECTION: {
1127 Tmp1 = LegalizeOp(Node->getOperand(0));
1128 Tmp2 = LegalizeOp(Node->getOperand(1));
1129 MVT VT = Node->getValueType(0);
1130 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1131 default: assert(0 && "This action is not supported yet!");
1132 case TargetLowering::Expand: {
1133 unsigned Reg = TLI.getExceptionSelectorRegister();
1134 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
1137 case TargetLowering::Custom:
1138 Result = TLI.LowerOperation(Op, DAG);
1139 if (Result.getNode()) break;
1141 case TargetLowering::Legal: {
1142 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1143 Result = DAG.getMergeValues(Ops, 2, dl);
1148 if (Result.getNode()->getNumValues() == 1) break;
1150 assert(Result.getNode()->getNumValues() == 2 &&
1151 "Cannot return more than two values!");
1153 // Since we produced two values, make sure to remember that we
1154 // legalized both of them.
1155 Tmp1 = LegalizeOp(Result);
1156 Tmp2 = LegalizeOp(Result.getValue(1));
1157 AddLegalizedOperand(Op.getValue(0), Tmp1);
1158 AddLegalizedOperand(Op.getValue(1), Tmp2);
1159 return Op.getResNo() ? Tmp2 : Tmp1;
1160 case ISD::EH_RETURN: {
1161 MVT VT = Node->getValueType(0);
1162 // The only "good" option for this node is to custom lower it.
1163 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1164 default: assert(0 && "This action is not supported at all!");
1165 case TargetLowering::Custom:
1166 Result = TLI.LowerOperation(Op, DAG);
1167 if (Result.getNode()) break;
1169 case TargetLowering::Legal:
1170 // Target does not know, how to lower this, lower to noop
1171 Result = LegalizeOp(Node->getOperand(0));
1176 case ISD::AssertSext:
1177 case ISD::AssertZext:
1178 Tmp1 = LegalizeOp(Node->getOperand(0));
1179 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1181 case ISD::MERGE_VALUES:
1182 // Legalize eliminates MERGE_VALUES nodes.
1183 Result = Node->getOperand(Op.getResNo());
1185 case ISD::CopyFromReg:
1186 Tmp1 = LegalizeOp(Node->getOperand(0));
1187 Result = Op.getValue(0);
1188 if (Node->getNumValues() == 2) {
1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1191 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1192 if (Node->getNumOperands() == 3) {
1193 Tmp2 = LegalizeOp(Node->getOperand(2));
1194 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1196 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1198 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1200 // Since CopyFromReg produces two values, make sure to remember that we
1201 // legalized both of them.
1202 AddLegalizedOperand(Op.getValue(0), Result);
1203 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1204 return Result.getValue(Op.getResNo());
1206 MVT VT = Op.getValueType();
1207 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1208 default: assert(0 && "This action is not supported yet!");
1209 case TargetLowering::Expand:
1211 Result = DAG.getConstant(0, VT);
1212 else if (VT.isFloatingPoint())
1213 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1216 assert(0 && "Unknown value type!");
1218 case TargetLowering::Legal:
1224 case ISD::INTRINSIC_W_CHAIN:
1225 case ISD::INTRINSIC_WO_CHAIN:
1226 case ISD::INTRINSIC_VOID: {
1227 SmallVector<SDValue, 8> Ops;
1228 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1229 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1230 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1232 // Allow the target to custom lower its intrinsics if it wants to.
1233 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1234 TargetLowering::Custom) {
1235 Tmp3 = TLI.LowerOperation(Result, DAG);
1236 if (Tmp3.getNode()) Result = Tmp3;
1239 if (Result.getNode()->getNumValues() == 1) break;
1241 // Must have return value and chain result.
1242 assert(Result.getNode()->getNumValues() == 2 &&
1243 "Cannot return more than two values!");
1245 // Since loads produce two values, make sure to remember that we
1246 // legalized both of them.
1247 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1248 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1249 return Result.getValue(Op.getResNo());
1252 case ISD::DBG_STOPPOINT:
1253 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1254 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1256 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1257 case TargetLowering::Promote:
1258 default: assert(0 && "This action is not supported yet!");
1259 case TargetLowering::Expand: {
1260 DwarfWriter *DW = DAG.getDwarfWriter();
1261 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1263 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1265 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1266 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1267 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1268 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1269 std::string Dir, FN;
1270 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
1271 CU.getFilename(FN));
1273 unsigned Line = DSP->getLine();
1274 unsigned Col = DSP->getColumn();
1277 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1278 // won't hurt anything.
1280 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1281 DAG.getConstant(Col, MVT::i32),
1282 DAG.getConstant(SrcFile, MVT::i32) };
1283 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1285 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1286 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1289 Result = Tmp1; // chain
1292 Result = Tmp1; // chain
1296 case TargetLowering::Custom:
1297 Result = TLI.LowerOperation(Op, DAG);
1298 if (Result.getNode())
1300 case TargetLowering::Legal: {
1301 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1302 if (Action == Legal && Tmp1 == Node->getOperand(0))
1305 SmallVector<SDValue, 8> Ops;
1306 Ops.push_back(Tmp1);
1307 if (Action == Legal) {
1308 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1309 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1311 // Otherwise promote them.
1312 Ops.push_back(PromoteOp(Node->getOperand(1)));
1313 Ops.push_back(PromoteOp(Node->getOperand(2)));
1315 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1316 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1317 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1324 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1325 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1326 default: assert(0 && "This action is not supported yet!");
1327 case TargetLowering::Legal:
1328 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1329 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1330 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1331 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1333 case TargetLowering::Expand:
1334 Result = LegalizeOp(Node->getOperand(0));
1339 case ISD::DEBUG_LOC:
1340 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1341 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1342 default: assert(0 && "This action is not supported yet!");
1343 case TargetLowering::Legal: {
1344 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1346 if (Action == Legal && Tmp1 == Node->getOperand(0))
1348 if (Action == Legal) {
1349 Tmp2 = Node->getOperand(1);
1350 Tmp3 = Node->getOperand(2);
1351 Tmp4 = Node->getOperand(3);
1353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1354 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1355 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1357 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1363 case ISD::DBG_LABEL:
1365 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1366 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1367 default: assert(0 && "This action is not supported yet!");
1368 case TargetLowering::Legal:
1369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1370 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1372 case TargetLowering::Expand:
1373 Result = LegalizeOp(Node->getOperand(0));
1379 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1380 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1381 default: assert(0 && "This action is not supported yet!");
1382 case TargetLowering::Legal:
1383 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1384 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1385 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1386 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1389 case TargetLowering::Expand:
1391 Result = LegalizeOp(Node->getOperand(0));
1396 case ISD::MEMBARRIER: {
1397 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1398 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1399 default: assert(0 && "This action is not supported yet!");
1400 case TargetLowering::Legal: {
1402 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1403 for (int x = 1; x < 6; ++x) {
1404 Ops[x] = Node->getOperand(x);
1405 if (!isTypeLegal(Ops[x].getValueType()))
1406 Ops[x] = PromoteOp(Ops[x]);
1408 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1411 case TargetLowering::Expand:
1412 //There is no libgcc call for this op
1413 Result = Node->getOperand(0); // Noop
1419 case ISD::ATOMIC_CMP_SWAP: {
1420 unsigned int num_operands = 4;
1421 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1423 for (unsigned int x = 0; x < num_operands; ++x)
1424 Ops[x] = LegalizeOp(Node->getOperand(x));
1425 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1427 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1428 default: assert(0 && "This action is not supported yet!");
1429 case TargetLowering::Custom:
1430 Result = TLI.LowerOperation(Result, DAG);
1432 case TargetLowering::Legal:
1435 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1436 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1437 return Result.getValue(Op.getResNo());
1439 case ISD::ATOMIC_LOAD_ADD:
1440 case ISD::ATOMIC_LOAD_SUB:
1441 case ISD::ATOMIC_LOAD_AND:
1442 case ISD::ATOMIC_LOAD_OR:
1443 case ISD::ATOMIC_LOAD_XOR:
1444 case ISD::ATOMIC_LOAD_NAND:
1445 case ISD::ATOMIC_LOAD_MIN:
1446 case ISD::ATOMIC_LOAD_MAX:
1447 case ISD::ATOMIC_LOAD_UMIN:
1448 case ISD::ATOMIC_LOAD_UMAX:
1449 case ISD::ATOMIC_SWAP: {
1450 unsigned int num_operands = 3;
1451 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1453 for (unsigned int x = 0; x < num_operands; ++x)
1454 Ops[x] = LegalizeOp(Node->getOperand(x));
1455 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1457 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1458 default: assert(0 && "This action is not supported yet!");
1459 case TargetLowering::Custom:
1460 Result = TLI.LowerOperation(Result, DAG);
1462 case TargetLowering::Legal:
1465 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1466 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1467 return Result.getValue(Op.getResNo());
1469 case ISD::Constant: {
1470 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1472 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1474 // We know we don't need to expand constants here, constants only have one
1475 // value and we check that it is fine above.
1477 if (opAction == TargetLowering::Custom) {
1478 Tmp1 = TLI.LowerOperation(Result, DAG);
1484 case ISD::ConstantFP: {
1485 // Spill FP immediates to the constant pool if the target cannot directly
1486 // codegen them. Targets often have some immediate values that can be
1487 // efficiently generated into an FP register without a load. We explicitly
1488 // leave these constants as ConstantFP nodes for the target to deal with.
1489 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1491 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1492 default: assert(0 && "This action is not supported yet!");
1493 case TargetLowering::Legal:
1495 case TargetLowering::Custom:
1496 Tmp3 = TLI.LowerOperation(Result, DAG);
1497 if (Tmp3.getNode()) {
1502 case TargetLowering::Expand: {
1503 // Check to see if this FP immediate is already legal.
1504 bool isLegal = false;
1505 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1506 E = TLI.legal_fpimm_end(); I != E; ++I) {
1507 if (CFP->isExactlyValue(*I)) {
1512 // If this is a legal constant, turn it into a TargetConstantFP node.
1515 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1520 case ISD::TokenFactor:
1521 if (Node->getNumOperands() == 2) {
1522 Tmp1 = LegalizeOp(Node->getOperand(0));
1523 Tmp2 = LegalizeOp(Node->getOperand(1));
1524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1525 } else if (Node->getNumOperands() == 3) {
1526 Tmp1 = LegalizeOp(Node->getOperand(0));
1527 Tmp2 = LegalizeOp(Node->getOperand(1));
1528 Tmp3 = LegalizeOp(Node->getOperand(2));
1529 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1531 SmallVector<SDValue, 8> Ops;
1532 // Legalize the operands.
1533 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1534 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1535 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1539 case ISD::FORMAL_ARGUMENTS:
1541 // The only option for this is to custom lower it.
1542 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1543 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1544 // A call within a calling sequence must be legalized to something
1545 // other than the normal CALLSEQ_END. Violating this gets Legalize
1546 // into an infinite loop.
1547 assert ((!IsLegalizingCall ||
1548 Node->getOpcode() != ISD::CALL ||
1549 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1550 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1552 // The number of incoming and outgoing values should match; unless the final
1553 // outgoing value is a flag.
1554 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1555 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1556 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1558 "Lowering call/formal_arguments produced unexpected # results!");
1560 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1561 // remember that we legalized all of them, so it doesn't get relegalized.
1562 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1563 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1565 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1566 if (Op.getResNo() == i)
1568 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1571 case ISD::BUILD_VECTOR:
1572 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1573 default: assert(0 && "This action is not supported yet!");
1574 case TargetLowering::Custom:
1575 Tmp3 = TLI.LowerOperation(Result, DAG);
1576 if (Tmp3.getNode()) {
1581 case TargetLowering::Expand:
1582 Result = ExpandBUILD_VECTOR(Result.getNode());
1586 case ISD::INSERT_VECTOR_ELT:
1587 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1588 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1590 // The type of the value to insert may not be legal, even though the vector
1591 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1593 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1594 default: assert(0 && "Cannot expand insert element operand");
1595 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1596 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1598 // FIXME: An alternative would be to check to see if the target is not
1599 // going to custom lower this operation, we could bitcast to half elt
1600 // width and perform two inserts at that width, if that is legal.
1601 Tmp2 = Node->getOperand(1);
1604 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1606 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1607 Node->getValueType(0))) {
1608 default: assert(0 && "This action is not supported yet!");
1609 case TargetLowering::Legal:
1611 case TargetLowering::Custom:
1612 Tmp4 = TLI.LowerOperation(Result, DAG);
1613 if (Tmp4.getNode()) {
1618 case TargetLowering::Promote:
1619 // Fall thru for vector case
1620 case TargetLowering::Expand: {
1621 // If the insert index is a constant, codegen this as a scalar_to_vector,
1622 // then a shuffle that inserts it into the right position in the vector.
1623 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1624 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1625 // match the element type of the vector being created, except for
1626 // integers in which case the inserted value can be over width.
1627 MVT EltVT = Op.getValueType().getVectorElementType();
1628 if (Tmp2.getValueType() == EltVT ||
1629 (EltVT.isInteger() && Tmp2.getValueType().bitsGE(EltVT))) {
1630 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1631 Tmp1.getValueType(), Tmp2);
1633 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1634 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1635 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1636 // elt 0 of the RHS.
1637 SmallVector<int, 8> ShufOps;
1638 for (unsigned i = 0; i != NumElts; ++i)
1639 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
1641 Result = DAG.getVectorShuffle(Tmp1.getValueType(), dl, Tmp1, ScVec,
1643 Result = LegalizeOp(Result);
1647 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1652 case ISD::SCALAR_TO_VECTOR:
1653 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1654 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1658 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1659 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1660 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1661 Node->getValueType(0))) {
1662 default: assert(0 && "This action is not supported yet!");
1663 case TargetLowering::Legal:
1665 case TargetLowering::Custom:
1666 Tmp3 = TLI.LowerOperation(Result, DAG);
1667 if (Tmp3.getNode()) {
1672 case TargetLowering::Expand:
1673 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1677 case ISD::VECTOR_SHUFFLE: {
1678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1679 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1680 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1681 MVT VT = Result.getValueType();
1683 // Copy the Mask to a local SmallVector for use wi
1684 SmallVector<int, 8> Mask;
1685 cast<ShuffleVectorSDNode>(Result)->getMask(Mask);
1687 // Allow targets to custom lower the SHUFFLEs they support.
1688 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
1689 default: assert(0 && "Unknown operation action!");
1690 case TargetLowering::Legal:
1691 assert(TLI.isShuffleMaskLegal(Mask, VT) &&
1692 "vector shuffle should not be created if not legal!");
1694 case TargetLowering::Custom:
1695 Tmp3 = TLI.LowerOperation(Result, DAG);
1696 if (Tmp3.getNode()) {
1701 case TargetLowering::Expand: {
1702 MVT EltVT = VT.getVectorElementType();
1703 int NumElems = VT.getVectorNumElements();
1704 SmallVector<SDValue, 8> Ops;
1705 for (int i = 0; i != NumElems; ++i) {
1707 Ops.push_back(DAG.getUNDEF(EltVT));
1712 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1713 DAG.getIntPtrConstant(Idx)));
1715 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1716 DAG.getIntPtrConstant(Idx - NumElems)));
1718 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1721 case TargetLowering::Promote: {
1722 // Change base type to a different vector type.
1723 MVT OVT = Node->getValueType(0);
1724 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1726 // Cast the two input vectors.
1727 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1728 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1730 // Convert the shuffle mask to the right # elements.
1731 Result = promoteShuffle(NVT, OVT, dl, Tmp1, Tmp2, Mask);
1732 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1738 case ISD::EXTRACT_VECTOR_ELT:
1739 Tmp1 = Node->getOperand(0);
1740 Tmp2 = LegalizeOp(Node->getOperand(1));
1741 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1742 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1745 case ISD::EXTRACT_SUBVECTOR:
1746 Tmp1 = Node->getOperand(0);
1747 Tmp2 = LegalizeOp(Node->getOperand(1));
1748 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1749 Result = ExpandEXTRACT_SUBVECTOR(Result);
1752 case ISD::CONCAT_VECTORS: {
1753 // Use extract/insert/build vector for now. We might try to be
1754 // more clever later.
1755 MVT PtrVT = TLI.getPointerTy();
1756 SmallVector<SDValue, 8> Ops;
1757 unsigned NumOperands = Node->getNumOperands();
1758 for (unsigned i=0; i < NumOperands; ++i) {
1759 SDValue SubOp = Node->getOperand(i);
1760 MVT VVT = SubOp.getNode()->getValueType(0);
1761 MVT EltVT = VVT.getVectorElementType();
1762 unsigned NumSubElem = VVT.getVectorNumElements();
1763 for (unsigned j=0; j < NumSubElem; ++j) {
1764 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1765 DAG.getConstant(j, PtrVT)));
1768 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
1769 &Ops[0], Ops.size()));
1772 case ISD::CALLSEQ_START: {
1773 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1775 // Recursively Legalize all of the inputs of the call end that do not lead
1776 // to this call start. This ensures that any libcalls that need be inserted
1777 // are inserted *before* the CALLSEQ_START.
1778 IsLegalizingCallArgs = true;
1779 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1780 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1781 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1784 IsLegalizingCallArgs = false;
1786 // Now that we legalized all of the inputs (which may have inserted
1787 // libcalls) create the new CALLSEQ_START node.
1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1790 // Merge in the last call, to ensure that this call start after the last
1792 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1793 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1794 Tmp1, LastCALLSEQ_END);
1795 Tmp1 = LegalizeOp(Tmp1);
1798 // Do not try to legalize the target-specific arguments (#1+).
1799 if (Tmp1 != Node->getOperand(0)) {
1800 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1802 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1805 // Remember that the CALLSEQ_START is legalized.
1806 AddLegalizedOperand(Op.getValue(0), Result);
1807 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1808 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1810 // Now that the callseq_start and all of the non-call nodes above this call
1811 // sequence have been legalized, legalize the call itself. During this
1812 // process, no libcalls can/will be inserted, guaranteeing that no calls
1814 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1815 // Note that we are selecting this call!
1816 LastCALLSEQ_END = SDValue(CallEnd, 0);
1817 IsLegalizingCall = true;
1819 // Legalize the call, starting from the CALLSEQ_END.
1820 LegalizeOp(LastCALLSEQ_END);
1821 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1824 case ISD::CALLSEQ_END:
1825 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1826 // will cause this node to be legalized as well as handling libcalls right.
1827 if (LastCALLSEQ_END.getNode() != Node) {
1828 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1829 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1830 assert(I != LegalizedNodes.end() &&
1831 "Legalizing the call start should have legalized this node!");
1835 // Otherwise, the call start has been legalized and everything is going
1836 // according to plan. Just legalize ourselves normally here.
1837 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1838 // Do not try to legalize the target-specific arguments (#1+), except for
1839 // an optional flag input.
1840 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1841 if (Tmp1 != Node->getOperand(0)) {
1842 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1844 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1847 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1848 if (Tmp1 != Node->getOperand(0) ||
1849 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1850 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1853 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1856 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1857 // This finishes up call legalization.
1858 IsLegalizingCall = false;
1860 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1861 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1862 if (Node->getNumValues() == 2)
1863 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1864 return Result.getValue(Op.getResNo());
1865 case ISD::DYNAMIC_STACKALLOC: {
1866 MVT VT = Node->getValueType(0);
1867 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1868 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1869 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1870 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1872 Tmp1 = Result.getValue(0);
1873 Tmp2 = Result.getValue(1);
1874 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1875 default: assert(0 && "This action is not supported yet!");
1876 case TargetLowering::Expand: {
1877 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1878 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1879 " not tell us which reg is the stack pointer!");
1880 SDValue Chain = Tmp1.getOperand(0);
1882 // Chain the dynamic stack allocation so that it doesn't modify the stack
1883 // pointer when other instructions are using the stack.
1884 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1886 SDValue Size = Tmp2.getOperand(1);
1887 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1888 Chain = SP.getValue(1);
1889 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1890 unsigned StackAlign =
1891 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1892 if (Align > StackAlign)
1893 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1894 DAG.getConstant(-(uint64_t)Align, VT));
1895 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1896 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1898 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1899 DAG.getIntPtrConstant(0, true), SDValue());
1901 Tmp1 = LegalizeOp(Tmp1);
1902 Tmp2 = LegalizeOp(Tmp2);
1905 case TargetLowering::Custom:
1906 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1907 if (Tmp3.getNode()) {
1908 Tmp1 = LegalizeOp(Tmp3);
1909 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1912 case TargetLowering::Legal:
1915 // Since this op produce two values, make sure to remember that we
1916 // legalized both of them.
1917 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1918 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1919 return Op.getResNo() ? Tmp2 : Tmp1;
1921 case ISD::INLINEASM: {
1922 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1923 bool Changed = false;
1924 // Legalize all of the operands of the inline asm, in case they are nodes
1925 // that need to be expanded or something. Note we skip the asm string and
1926 // all of the TargetConstant flags.
1927 SDValue Op = LegalizeOp(Ops[0]);
1928 Changed = Op != Ops[0];
1931 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1932 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1933 unsigned NumVals = InlineAsm::
1934 getNumOperandRegisters(cast<ConstantSDNode>(Ops[i])->getZExtValue());
1935 for (++i; NumVals; ++i, --NumVals) {
1936 SDValue Op = LegalizeOp(Ops[i]);
1945 Op = LegalizeOp(Ops.back());
1946 Changed |= Op != Ops.back();
1951 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1953 // INLINE asm returns a chain and flag, make sure to add both to the map.
1954 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1955 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1956 return Result.getValue(Op.getResNo());
1959 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1960 // Ensure that libcalls are emitted before a branch.
1961 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1962 Tmp1 = LegalizeOp(Tmp1);
1963 LastCALLSEQ_END = DAG.getEntryNode();
1965 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1968 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1969 // Ensure that libcalls are emitted before a branch.
1970 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1971 Tmp1 = LegalizeOp(Tmp1);
1972 LastCALLSEQ_END = DAG.getEntryNode();
1974 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1975 default: assert(0 && "Indirect target must be legal type (pointer)!");
1977 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1980 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1983 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1984 // Ensure that libcalls are emitted before a branch.
1985 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1986 Tmp1 = LegalizeOp(Tmp1);
1987 LastCALLSEQ_END = DAG.getEntryNode();
1989 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1990 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1992 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1993 default: assert(0 && "This action is not supported yet!");
1994 case TargetLowering::Legal: break;
1995 case TargetLowering::Custom:
1996 Tmp1 = TLI.LowerOperation(Result, DAG);
1997 if (Tmp1.getNode()) Result = Tmp1;
1999 case TargetLowering::Expand: {
2000 SDValue Chain = Result.getOperand(0);
2001 SDValue Table = Result.getOperand(1);
2002 SDValue Index = Result.getOperand(2);
2004 MVT PTy = TLI.getPointerTy();
2005 MachineFunction &MF = DAG.getMachineFunction();
2006 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2007 Index= DAG.getNode(ISD::MUL, dl, PTy,
2008 Index, DAG.getConstant(EntrySize, PTy));
2009 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2011 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2012 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2013 PseudoSourceValue::getJumpTable(), 0, MemVT);
2015 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2016 // For PIC, the sequence is:
2017 // BRIND(load(Jumptable + index) + RelocBase)
2018 // RelocBase can be JumpTable, GOT or some sort of global base.
2019 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2020 TLI.getPICJumpTableRelocBase(Table, DAG));
2022 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2027 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2028 // Ensure that libcalls are emitted before a return.
2029 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2030 Tmp1 = LegalizeOp(Tmp1);
2031 LastCALLSEQ_END = DAG.getEntryNode();
2033 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2034 case Expand: assert(0 && "It's impossible to expand bools");
2036 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2039 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2041 // The top bits of the promoted condition are not necessarily zero, ensure
2042 // that the value is properly zero extended.
2043 unsigned BitWidth = Tmp2.getValueSizeInBits();
2044 if (!DAG.MaskedValueIsZero(Tmp2,
2045 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2046 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2051 // Basic block destination (Op#2) is always legal.
2052 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2054 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2055 default: assert(0 && "This action is not supported yet!");
2056 case TargetLowering::Legal: break;
2057 case TargetLowering::Custom:
2058 Tmp1 = TLI.LowerOperation(Result, DAG);
2059 if (Tmp1.getNode()) Result = Tmp1;
2061 case TargetLowering::Expand:
2062 // Expand brcond's setcc into its constituent parts and create a BR_CC
2064 if (Tmp2.getOpcode() == ISD::SETCC) {
2065 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2066 Tmp1, Tmp2.getOperand(2),
2067 Tmp2.getOperand(0), Tmp2.getOperand(1),
2068 Node->getOperand(2));
2070 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2071 DAG.getCondCode(ISD::SETNE), Tmp2,
2072 DAG.getConstant(0, Tmp2.getValueType()),
2073 Node->getOperand(2));
2079 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2080 // Ensure that libcalls are emitted before a branch.
2081 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2082 Tmp1 = LegalizeOp(Tmp1);
2083 Tmp2 = Node->getOperand(2); // LHS
2084 Tmp3 = Node->getOperand(3); // RHS
2085 Tmp4 = Node->getOperand(1); // CC
2087 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2088 Tmp2, Tmp3, Tmp4, dl);
2089 LastCALLSEQ_END = DAG.getEntryNode();
2091 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2092 // the LHS is a legal SETCC itself. In this case, we need to compare
2093 // the result against zero to select between true and false values.
2094 if (Tmp3.getNode() == 0) {
2095 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2096 Tmp4 = DAG.getCondCode(ISD::SETNE);
2099 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2100 Node->getOperand(4));
2102 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2103 default: assert(0 && "Unexpected action for BR_CC!");
2104 case TargetLowering::Legal: break;
2105 case TargetLowering::Custom:
2106 Tmp4 = TLI.LowerOperation(Result, DAG);
2107 if (Tmp4.getNode()) Result = Tmp4;
2112 LoadSDNode *LD = cast<LoadSDNode>(Node);
2113 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2114 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2116 ISD::LoadExtType ExtType = LD->getExtensionType();
2117 if (ExtType == ISD::NON_EXTLOAD) {
2118 MVT VT = Node->getValueType(0);
2119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2120 Tmp3 = Result.getValue(0);
2121 Tmp4 = Result.getValue(1);
2123 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2124 default: assert(0 && "This action is not supported yet!");
2125 case TargetLowering::Legal:
2126 // If this is an unaligned load and the target doesn't support it,
2128 if (!TLI.allowsUnalignedMemoryAccesses()) {
2129 unsigned ABIAlignment = TLI.getTargetData()->
2130 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2131 if (LD->getAlignment() < ABIAlignment){
2132 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2134 Tmp3 = Result.getOperand(0);
2135 Tmp4 = Result.getOperand(1);
2136 Tmp3 = LegalizeOp(Tmp3);
2137 Tmp4 = LegalizeOp(Tmp4);
2141 case TargetLowering::Custom:
2142 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2143 if (Tmp1.getNode()) {
2144 Tmp3 = LegalizeOp(Tmp1);
2145 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2148 case TargetLowering::Promote: {
2149 // Only promote a load of vector type to another.
2150 assert(VT.isVector() && "Cannot promote this load!");
2151 // Change base type to a different vector type.
2152 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2154 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2155 LD->getSrcValueOffset(),
2156 LD->isVolatile(), LD->getAlignment());
2157 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
2158 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2162 // Since loads produce two values, make sure to remember that we
2163 // legalized both of them.
2164 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2165 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2166 return Op.getResNo() ? Tmp4 : Tmp3;
2168 MVT SrcVT = LD->getMemoryVT();
2169 unsigned SrcWidth = SrcVT.getSizeInBits();
2170 int SVOffset = LD->getSrcValueOffset();
2171 unsigned Alignment = LD->getAlignment();
2172 bool isVolatile = LD->isVolatile();
2174 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2175 // Some targets pretend to have an i1 loading operation, and actually
2176 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2177 // bits are guaranteed to be zero; it helps the optimizers understand
2178 // that these bits are zero. It is also useful for EXTLOAD, since it
2179 // tells the optimizers that those bits are undefined. It would be
2180 // nice to have an effective generic way of getting these benefits...
2181 // Until such a way is found, don't insist on promoting i1 here.
2182 (SrcVT != MVT::i1 ||
2183 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2184 // Promote to a byte-sized load if not loading an integral number of
2185 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2186 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2187 MVT NVT = MVT::getIntegerVT(NewWidth);
2190 // The extra bits are guaranteed to be zero, since we stored them that
2191 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2193 ISD::LoadExtType NewExtType =
2194 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2196 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2197 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2198 NVT, isVolatile, Alignment);
2200 Ch = Result.getValue(1); // The chain.
2202 if (ExtType == ISD::SEXTLOAD)
2203 // Having the top bits zero doesn't help when sign extending.
2204 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2205 Result.getValueType(),
2206 Result, DAG.getValueType(SrcVT));
2207 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2208 // All the top bits are guaranteed to be zero - inform the optimizers.
2209 Result = DAG.getNode(ISD::AssertZext, dl,
2210 Result.getValueType(), Result,
2211 DAG.getValueType(SrcVT));
2213 Tmp1 = LegalizeOp(Result);
2214 Tmp2 = LegalizeOp(Ch);
2215 } else if (SrcWidth & (SrcWidth - 1)) {
2216 // If not loading a power-of-2 number of bits, expand as two loads.
2217 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2218 "Unsupported extload!");
2219 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2220 assert(RoundWidth < SrcWidth);
2221 unsigned ExtraWidth = SrcWidth - RoundWidth;
2222 assert(ExtraWidth < RoundWidth);
2223 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2224 "Load size not an integral number of bytes!");
2225 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2226 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2228 unsigned IncrementSize;
2230 if (TLI.isLittleEndian()) {
2231 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2232 // Load the bottom RoundWidth bits.
2233 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2234 Node->getValueType(0), Tmp1, Tmp2,
2235 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2238 // Load the remaining ExtraWidth bits.
2239 IncrementSize = RoundWidth / 8;
2240 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2241 DAG.getIntPtrConstant(IncrementSize));
2242 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2243 LD->getSrcValue(), SVOffset + IncrementSize,
2244 ExtraVT, isVolatile,
2245 MinAlign(Alignment, IncrementSize));
2247 // Build a factor node to remember that this load is independent of the
2249 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2252 // Move the top bits to the right place.
2253 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2254 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2256 // Join the hi and lo parts.
2257 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2259 // Big endian - avoid unaligned loads.
2260 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2261 // Load the top RoundWidth bits.
2262 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2263 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2266 // Load the remaining ExtraWidth bits.
2267 IncrementSize = RoundWidth / 8;
2268 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2269 DAG.getIntPtrConstant(IncrementSize));
2270 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2271 Node->getValueType(0), Tmp1, Tmp2,
2272 LD->getSrcValue(), SVOffset + IncrementSize,
2273 ExtraVT, isVolatile,
2274 MinAlign(Alignment, IncrementSize));
2276 // Build a factor node to remember that this load is independent of the
2278 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2281 // Move the top bits to the right place.
2282 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2283 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2285 // Join the hi and lo parts.
2286 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2289 Tmp1 = LegalizeOp(Result);
2290 Tmp2 = LegalizeOp(Ch);
2292 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2293 default: assert(0 && "This action is not supported yet!");
2294 case TargetLowering::Custom:
2297 case TargetLowering::Legal:
2298 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2299 Tmp1 = Result.getValue(0);
2300 Tmp2 = Result.getValue(1);
2303 Tmp3 = TLI.LowerOperation(Result, DAG);
2304 if (Tmp3.getNode()) {
2305 Tmp1 = LegalizeOp(Tmp3);
2306 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2309 // If this is an unaligned load and the target doesn't support it,
2311 if (!TLI.allowsUnalignedMemoryAccesses()) {
2312 unsigned ABIAlignment = TLI.getTargetData()->
2313 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2314 if (LD->getAlignment() < ABIAlignment){
2315 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2317 Tmp1 = Result.getOperand(0);
2318 Tmp2 = Result.getOperand(1);
2319 Tmp1 = LegalizeOp(Tmp1);
2320 Tmp2 = LegalizeOp(Tmp2);
2325 case TargetLowering::Expand:
2326 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2327 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2328 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2329 LD->getSrcValueOffset(),
2330 LD->isVolatile(), LD->getAlignment());
2331 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2332 Node->getValueType(0), Load);
2333 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2334 Tmp2 = LegalizeOp(Load.getValue(1));
2337 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2338 // Turn the unsupported load into an EXTLOAD followed by an explicit
2339 // zero/sign extend inreg.
2340 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2341 Tmp1, Tmp2, LD->getSrcValue(),
2342 LD->getSrcValueOffset(), SrcVT,
2343 LD->isVolatile(), LD->getAlignment());
2345 if (ExtType == ISD::SEXTLOAD)
2346 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2347 Result.getValueType(),
2348 Result, DAG.getValueType(SrcVT));
2350 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2351 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2352 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2357 // Since loads produce two values, make sure to remember that we legalized
2359 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2360 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2361 return Op.getResNo() ? Tmp2 : Tmp1;
2364 case ISD::EXTRACT_ELEMENT: {
2365 MVT OpTy = Node->getOperand(0).getValueType();
2366 switch (getTypeAction(OpTy)) {
2367 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2369 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2371 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2372 DAG.getConstant(OpTy.getSizeInBits()/2,
2373 TLI.getShiftAmountTy()));
2374 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2377 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2378 Node->getOperand(0));
2382 // Get both the low and high parts.
2383 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2384 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2385 Result = Tmp2; // 1 -> Hi
2387 Result = Tmp1; // 0 -> Lo
2393 case ISD::CopyToReg:
2394 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2396 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2397 "Register type must be legal!");
2398 // Legalize the incoming value (must be a legal type).
2399 Tmp2 = LegalizeOp(Node->getOperand(2));
2400 if (Node->getNumValues() == 1) {
2401 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2403 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2404 if (Node->getNumOperands() == 4) {
2405 Tmp3 = LegalizeOp(Node->getOperand(3));
2406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2409 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2412 // Since this produces two values, make sure to remember that we legalized
2414 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2415 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2421 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2423 // Ensure that libcalls are emitted before a return.
2424 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2425 Tmp1 = LegalizeOp(Tmp1);
2426 LastCALLSEQ_END = DAG.getEntryNode();
2428 switch (Node->getNumOperands()) {
2430 Tmp2 = Node->getOperand(1);
2431 Tmp3 = Node->getOperand(2); // Signness
2432 switch (getTypeAction(Tmp2.getValueType())) {
2434 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2437 if (!Tmp2.getValueType().isVector()) {
2439 ExpandOp(Tmp2, Lo, Hi);
2441 // Big endian systems want the hi reg first.
2442 if (TLI.isBigEndian())
2446 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2447 Tmp1, Lo, Tmp3, Hi, Tmp3);
2449 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2450 Result = LegalizeOp(Result);
2452 SDNode *InVal = Tmp2.getNode();
2453 int InIx = Tmp2.getResNo();
2454 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2455 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2457 // Figure out if there is a simple type corresponding to this Vector
2458 // type. If so, convert to the vector type.
2459 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2460 if (TLI.isTypeLegal(TVT)) {
2461 // Turn this into a return of the vector type.
2462 Tmp2 = LegalizeOp(Tmp2);
2463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2464 } else if (NumElems == 1) {
2465 // Turn this into a return of the scalar type.
2466 Tmp2 = ScalarizeVectorOp(Tmp2);
2467 Tmp2 = LegalizeOp(Tmp2);
2468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2470 // FIXME: Returns of gcc generic vectors smaller than a legal type
2471 // should be returned in integer registers!
2473 // The scalarized value type may not be legal, e.g. it might require
2474 // promotion or expansion. Relegalize the return.
2475 Result = LegalizeOp(Result);
2477 // FIXME: Returns of gcc generic vectors larger than a legal vector
2478 // type should be returned by reference!
2480 SplitVectorOp(Tmp2, Lo, Hi);
2481 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2482 Tmp1, Lo, Tmp3, Hi, Tmp3);
2483 Result = LegalizeOp(Result);
2488 Tmp2 = PromoteOp(Node->getOperand(1));
2489 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2490 Result = LegalizeOp(Result);
2495 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2497 default: { // ret <values>
2498 SmallVector<SDValue, 8> NewValues;
2499 NewValues.push_back(Tmp1);
2500 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2501 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2503 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2504 NewValues.push_back(Node->getOperand(i+1));
2508 assert(!Node->getOperand(i).getValueType().isExtended() &&
2509 "FIXME: TODO: implement returning non-legal vector types!");
2510 ExpandOp(Node->getOperand(i), Lo, Hi);
2511 NewValues.push_back(Lo);
2512 NewValues.push_back(Node->getOperand(i+1));
2514 NewValues.push_back(Hi);
2515 NewValues.push_back(Node->getOperand(i+1));
2520 assert(0 && "Can't promote multiple return value yet!");
2523 if (NewValues.size() == Node->getNumOperands())
2524 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2526 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2527 &NewValues[0], NewValues.size());
2532 if (Result.getOpcode() == ISD::RET) {
2533 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2534 default: assert(0 && "This action is not supported yet!");
2535 case TargetLowering::Legal: break;
2536 case TargetLowering::Custom:
2537 Tmp1 = TLI.LowerOperation(Result, DAG);
2538 if (Tmp1.getNode()) Result = Tmp1;
2544 StoreSDNode *ST = cast<StoreSDNode>(Node);
2545 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2546 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2547 int SVOffset = ST->getSrcValueOffset();
2548 unsigned Alignment = ST->getAlignment();
2549 bool isVolatile = ST->isVolatile();
2551 if (!ST->isTruncatingStore()) {
2552 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2553 // FIXME: We shouldn't do this for TargetConstantFP's.
2554 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2555 // to phase ordering between legalized code and the dag combiner. This
2556 // probably means that we need to integrate dag combiner and legalizer
2558 // We generally can't do this one for long doubles.
2559 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2560 if (CFP->getValueType(0) == MVT::f32 &&
2561 getTypeAction(MVT::i32) == Legal) {
2562 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2563 bitcastToAPInt().zextOrTrunc(32),
2565 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2566 SVOffset, isVolatile, Alignment);
2568 } else if (CFP->getValueType(0) == MVT::f64) {
2569 // If this target supports 64-bit registers, do a single 64-bit store.
2570 if (getTypeAction(MVT::i64) == Legal) {
2571 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2572 zextOrTrunc(64), MVT::i64);
2573 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2574 SVOffset, isVolatile, Alignment);
2576 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2577 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2578 // stores. If the target supports neither 32- nor 64-bits, this
2579 // xform is certainly not worth it.
2580 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2581 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2582 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2583 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2585 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2586 SVOffset, isVolatile, Alignment);
2587 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2588 DAG.getIntPtrConstant(4));
2589 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2590 isVolatile, MinAlign(Alignment, 4U));
2592 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2598 switch (getTypeAction(ST->getMemoryVT())) {
2600 Tmp3 = LegalizeOp(ST->getValue());
2601 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2604 MVT VT = Tmp3.getValueType();
2605 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2606 default: assert(0 && "This action is not supported yet!");
2607 case TargetLowering::Legal:
2608 // If this is an unaligned store and the target doesn't support it,
2610 if (!TLI.allowsUnalignedMemoryAccesses()) {
2611 unsigned ABIAlignment = TLI.getTargetData()->
2612 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2613 if (ST->getAlignment() < ABIAlignment)
2614 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2618 case TargetLowering::Custom:
2619 Tmp1 = TLI.LowerOperation(Result, DAG);
2620 if (Tmp1.getNode()) Result = Tmp1;
2622 case TargetLowering::Promote:
2623 assert(VT.isVector() && "Unknown legal promote case!");
2624 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2625 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2626 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2627 ST->getSrcValue(), SVOffset, isVolatile,
2634 if (!ST->getMemoryVT().isVector()) {
2635 // Truncate the value and store the result.
2636 Tmp3 = PromoteOp(ST->getValue());
2637 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2638 SVOffset, ST->getMemoryVT(),
2639 isVolatile, Alignment);
2642 // Fall thru to expand for vector
2644 unsigned IncrementSize = 0;
2647 // If this is a vector type, then we have to calculate the increment as
2648 // the product of the element size in bytes, and the number of elements
2649 // in the high half of the vector.
2650 if (ST->getValue().getValueType().isVector()) {
2651 SDNode *InVal = ST->getValue().getNode();
2652 int InIx = ST->getValue().getResNo();
2653 MVT InVT = InVal->getValueType(InIx);
2654 unsigned NumElems = InVT.getVectorNumElements();
2655 MVT EVT = InVT.getVectorElementType();
2657 // Figure out if there is a simple type corresponding to this Vector
2658 // type. If so, convert to the vector type.
2659 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2660 if (TLI.isTypeLegal(TVT)) {
2661 // Turn this into a normal store of the vector type.
2662 Tmp3 = LegalizeOp(ST->getValue());
2663 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2664 SVOffset, isVolatile, Alignment);
2665 Result = LegalizeOp(Result);
2667 } else if (NumElems == 1) {
2668 // Turn this into a normal store of the scalar type.
2669 Tmp3 = ScalarizeVectorOp(ST->getValue());
2670 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2671 SVOffset, isVolatile, Alignment);
2672 // The scalarized value type may not be legal, e.g. it might require
2673 // promotion or expansion. Relegalize the scalar store.
2674 Result = LegalizeOp(Result);
2677 // Check if we have widen this node with another value
2678 std::map<SDValue, SDValue>::iterator I =
2679 WidenNodes.find(ST->getValue());
2680 if (I != WidenNodes.end()) {
2681 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2685 SplitVectorOp(ST->getValue(), Lo, Hi);
2686 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2687 EVT.getSizeInBits()/8;
2691 ExpandOp(ST->getValue(), Lo, Hi);
2692 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2694 if (Hi.getNode() && TLI.isBigEndian())
2698 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2699 SVOffset, isVolatile, Alignment);
2701 if (Hi.getNode() == NULL) {
2702 // Must be int <-> float one-to-one expansion.
2707 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2708 DAG.getIntPtrConstant(IncrementSize));
2709 assert(isTypeLegal(Tmp2.getValueType()) &&
2710 "Pointers must be legal!");
2711 SVOffset += IncrementSize;
2712 Alignment = MinAlign(Alignment, IncrementSize);
2713 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2714 SVOffset, isVolatile, Alignment);
2715 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2720 switch (getTypeAction(ST->getValue().getValueType())) {
2722 Tmp3 = LegalizeOp(ST->getValue());
2725 if (!ST->getValue().getValueType().isVector()) {
2726 // We can promote the value, the truncstore will still take care of it.
2727 Tmp3 = PromoteOp(ST->getValue());
2730 // Vector case falls through to expand
2732 // Just store the low part. This may become a non-trunc store, so make
2733 // sure to use getTruncStore, not UpdateNodeOperands below.
2734 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2735 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2736 SVOffset, MVT::i8, isVolatile, Alignment);
2739 MVT StVT = ST->getMemoryVT();
2740 unsigned StWidth = StVT.getSizeInBits();
2742 if (StWidth != StVT.getStoreSizeInBits()) {
2743 // Promote to a byte-sized store with upper bits zero if not
2744 // storing an integral number of bytes. For example, promote
2745 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2746 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2747 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2748 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2749 SVOffset, NVT, isVolatile, Alignment);
2750 } else if (StWidth & (StWidth - 1)) {
2751 // If not storing a power-of-2 number of bits, expand as two stores.
2752 assert(StVT.isExtended() && !StVT.isVector() &&
2753 "Unsupported truncstore!");
2754 unsigned RoundWidth = 1 << Log2_32(StWidth);
2755 assert(RoundWidth < StWidth);
2756 unsigned ExtraWidth = StWidth - RoundWidth;
2757 assert(ExtraWidth < RoundWidth);
2758 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2759 "Store size not an integral number of bytes!");
2760 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2761 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2763 unsigned IncrementSize;
2765 if (TLI.isLittleEndian()) {
2766 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2767 // Store the bottom RoundWidth bits.
2768 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2770 isVolatile, Alignment);
2772 // Store the remaining ExtraWidth bits.
2773 IncrementSize = RoundWidth / 8;
2774 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2775 DAG.getIntPtrConstant(IncrementSize));
2776 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2777 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2778 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2779 SVOffset + IncrementSize, ExtraVT, isVolatile,
2780 MinAlign(Alignment, IncrementSize));
2782 // Big endian - avoid unaligned stores.
2783 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2784 // Store the top RoundWidth bits.
2785 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2786 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2787 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2788 SVOffset, RoundVT, isVolatile, Alignment);
2790 // Store the remaining ExtraWidth bits.
2791 IncrementSize = RoundWidth / 8;
2792 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2793 DAG.getIntPtrConstant(IncrementSize));
2794 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2795 SVOffset + IncrementSize, ExtraVT, isVolatile,
2796 MinAlign(Alignment, IncrementSize));
2799 // The order of the stores doesn't matter.
2800 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2802 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2803 Tmp2 != ST->getBasePtr())
2804 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2807 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2808 default: assert(0 && "This action is not supported yet!");
2809 case TargetLowering::Legal:
2810 // If this is an unaligned store and the target doesn't support it,
2812 if (!TLI.allowsUnalignedMemoryAccesses()) {
2813 unsigned ABIAlignment = TLI.getTargetData()->
2814 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2815 if (ST->getAlignment() < ABIAlignment)
2816 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2820 case TargetLowering::Custom:
2821 Result = TLI.LowerOperation(Result, DAG);
2824 // TRUNCSTORE:i16 i32 -> STORE i16
2825 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2826 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2827 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2828 SVOffset, isVolatile, Alignment);
2836 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2837 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2839 case ISD::STACKSAVE:
2840 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2841 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2842 Tmp1 = Result.getValue(0);
2843 Tmp2 = Result.getValue(1);
2845 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2846 default: assert(0 && "This action is not supported yet!");
2847 case TargetLowering::Legal: break;
2848 case TargetLowering::Custom:
2849 Tmp3 = TLI.LowerOperation(Result, DAG);
2850 if (Tmp3.getNode()) {
2851 Tmp1 = LegalizeOp(Tmp3);
2852 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2855 case TargetLowering::Expand:
2856 // Expand to CopyFromReg if the target set
2857 // StackPointerRegisterToSaveRestore.
2858 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2859 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
2860 Node->getValueType(0));
2861 Tmp2 = Tmp1.getValue(1);
2863 Tmp1 = DAG.getUNDEF(Node->getValueType(0));
2864 Tmp2 = Node->getOperand(0);
2869 // Since stacksave produce two values, make sure to remember that we
2870 // legalized both of them.
2871 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2872 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2873 return Op.getResNo() ? Tmp2 : Tmp1;
2875 case ISD::STACKRESTORE:
2876 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2877 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2878 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2880 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2881 default: assert(0 && "This action is not supported yet!");
2882 case TargetLowering::Legal: break;
2883 case TargetLowering::Custom:
2884 Tmp1 = TLI.LowerOperation(Result, DAG);
2885 if (Tmp1.getNode()) Result = Tmp1;
2887 case TargetLowering::Expand:
2888 // Expand to CopyToReg if the target set
2889 // StackPointerRegisterToSaveRestore.
2890 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2891 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
2899 case ISD::READCYCLECOUNTER:
2900 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2901 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2902 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2903 Node->getValueType(0))) {
2904 default: assert(0 && "This action is not supported yet!");
2905 case TargetLowering::Legal:
2906 Tmp1 = Result.getValue(0);
2907 Tmp2 = Result.getValue(1);
2909 case TargetLowering::Custom:
2910 Result = TLI.LowerOperation(Result, DAG);
2911 Tmp1 = LegalizeOp(Result.getValue(0));
2912 Tmp2 = LegalizeOp(Result.getValue(1));
2916 // Since rdcc produce two values, make sure to remember that we legalized
2918 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2919 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2923 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2924 case Expand: assert(0 && "It's impossible to expand bools");
2926 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2929 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2930 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2931 // Make sure the condition is either zero or one.
2932 unsigned BitWidth = Tmp1.getValueSizeInBits();
2933 if (!DAG.MaskedValueIsZero(Tmp1,
2934 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2935 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2939 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2940 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2944 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2945 default: assert(0 && "This action is not supported yet!");
2946 case TargetLowering::Legal: break;
2947 case TargetLowering::Custom: {
2948 Tmp1 = TLI.LowerOperation(Result, DAG);
2949 if (Tmp1.getNode()) Result = Tmp1;
2952 case TargetLowering::Expand:
2953 if (Tmp1.getOpcode() == ISD::SETCC) {
2954 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2956 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2958 Result = DAG.getSelectCC(dl, Tmp1,
2959 DAG.getConstant(0, Tmp1.getValueType()),
2960 Tmp2, Tmp3, ISD::SETNE);
2963 case TargetLowering::Promote: {
2965 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2966 unsigned ExtOp, TruncOp;
2967 if (Tmp2.getValueType().isVector()) {
2968 ExtOp = ISD::BIT_CONVERT;
2969 TruncOp = ISD::BIT_CONVERT;
2970 } else if (Tmp2.getValueType().isInteger()) {
2971 ExtOp = ISD::ANY_EXTEND;
2972 TruncOp = ISD::TRUNCATE;
2974 ExtOp = ISD::FP_EXTEND;
2975 TruncOp = ISD::FP_ROUND;
2977 // Promote each of the values to the new type.
2978 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
2979 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
2980 // Perform the larger operation, then round down.
2981 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
2982 if (TruncOp != ISD::FP_ROUND)
2983 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
2985 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
2986 DAG.getIntPtrConstant(0));
2991 case ISD::SELECT_CC: {
2992 Tmp1 = Node->getOperand(0); // LHS
2993 Tmp2 = Node->getOperand(1); // RHS
2994 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2995 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2996 SDValue CC = Node->getOperand(4);
2998 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
2999 Tmp1, Tmp2, CC, dl);
3001 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3002 // the LHS is a legal SETCC itself. In this case, we need to compare
3003 // the result against zero to select between true and false values.
3004 if (Tmp2.getNode() == 0) {
3005 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3006 CC = DAG.getCondCode(ISD::SETNE);
3008 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3010 // Everything is legal, see if we should expand this op or something.
3011 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3012 default: assert(0 && "This action is not supported yet!");
3013 case TargetLowering::Legal: break;
3014 case TargetLowering::Custom:
3015 Tmp1 = TLI.LowerOperation(Result, DAG);
3016 if (Tmp1.getNode()) Result = Tmp1;
3022 Tmp1 = Node->getOperand(0);
3023 Tmp2 = Node->getOperand(1);
3024 Tmp3 = Node->getOperand(2);
3025 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3027 // If we had to Expand the SetCC operands into a SELECT node, then it may
3028 // not always be possible to return a true LHS & RHS. In this case, just
3029 // return the value we legalized, returned in the LHS
3030 if (Tmp2.getNode() == 0) {
3035 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3036 default: assert(0 && "Cannot handle this action for SETCC yet!");
3037 case TargetLowering::Custom:
3040 case TargetLowering::Legal:
3041 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3043 Tmp4 = TLI.LowerOperation(Result, DAG);
3044 if (Tmp4.getNode()) Result = Tmp4;
3047 case TargetLowering::Promote: {
3048 // First step, figure out the appropriate operation to use.
3049 // Allow SETCC to not be supported for all legal data types
3050 // Mostly this targets FP
3051 MVT NewInTy = Node->getOperand(0).getValueType();
3052 MVT OldVT = NewInTy; OldVT = OldVT;
3054 // Scan for the appropriate larger type to use.
3056 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3058 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3059 "Fell off of the edge of the integer world");
3060 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3061 "Fell off of the edge of the floating point world");
3063 // If the target supports SETCC of this type, use it.
3064 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3067 if (NewInTy.isInteger())
3068 assert(0 && "Cannot promote Legal Integer SETCC yet");
3070 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3071 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3073 Tmp1 = LegalizeOp(Tmp1);
3074 Tmp2 = LegalizeOp(Tmp2);
3075 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3076 Result = LegalizeOp(Result);
3079 case TargetLowering::Expand:
3080 // Expand a setcc node into a select_cc of the same condition, lhs, and
3081 // rhs that selects between const 1 (true) and const 0 (false).
3082 MVT VT = Node->getValueType(0);
3083 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3084 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3090 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3091 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3092 SDValue CC = Node->getOperand(2);
3094 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3096 // Everything is legal, see if we should expand this op or something.
3097 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3098 default: assert(0 && "This action is not supported yet!");
3099 case TargetLowering::Legal: break;
3100 case TargetLowering::Custom:
3101 Tmp1 = TLI.LowerOperation(Result, DAG);
3102 if (Tmp1.getNode()) Result = Tmp1;
3104 case TargetLowering::Expand: {
3105 // Unroll into a nasty set of scalar code for now.
3106 MVT VT = Node->getValueType(0);
3107 unsigned NumElems = VT.getVectorNumElements();
3108 MVT EltVT = VT.getVectorElementType();
3109 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3110 SmallVector<SDValue, 8> Ops(NumElems);
3111 for (unsigned i = 0; i < NumElems; ++i) {
3112 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3113 Tmp1, DAG.getIntPtrConstant(i));
3114 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3115 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3117 DAG.getIntPtrConstant(i)),
3119 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i],
3120 DAG.getConstant(APInt::getAllOnesValue
3121 (EltVT.getSizeInBits()), EltVT),
3122 DAG.getConstant(0, EltVT));
3124 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
3131 case ISD::SHL_PARTS:
3132 case ISD::SRA_PARTS:
3133 case ISD::SRL_PARTS: {
3134 SmallVector<SDValue, 8> Ops;
3135 bool Changed = false;
3136 unsigned N = Node->getNumOperands();
3137 for (unsigned i = 0; i + 1 < N; ++i) {
3138 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3139 Changed |= Ops.back() != Node->getOperand(i);
3141 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3142 Changed |= Ops.back() != Node->getOperand(N-1);
3144 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3146 switch (TLI.getOperationAction(Node->getOpcode(),
3147 Node->getValueType(0))) {
3148 default: assert(0 && "This action is not supported yet!");
3149 case TargetLowering::Legal: break;
3150 case TargetLowering::Custom:
3151 Tmp1 = TLI.LowerOperation(Result, DAG);
3152 if (Tmp1.getNode()) {
3153 SDValue Tmp2, RetVal(0, 0);
3154 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3155 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3156 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3157 if (i == Op.getResNo())
3160 assert(RetVal.getNode() && "Illegal result number");
3166 // Since these produce multiple values, make sure to remember that we
3167 // legalized all of them.
3168 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3169 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3170 return Result.getValue(Op.getResNo());
3192 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3193 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3195 if ((Node->getOpcode() == ISD::SHL ||
3196 Node->getOpcode() == ISD::SRL ||
3197 Node->getOpcode() == ISD::SRA) &&
3198 !Node->getValueType(0).isVector())
3199 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3201 switch (getTypeAction(Tmp2.getValueType())) {
3202 case Expand: assert(0 && "Not possible");
3204 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3207 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3211 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3213 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3214 default: assert(0 && "BinOp legalize operation not supported");
3215 case TargetLowering::Legal: break;
3216 case TargetLowering::Custom:
3217 Tmp1 = TLI.LowerOperation(Result, DAG);
3218 if (Tmp1.getNode()) {
3222 // Fall through if the custom lower can't deal with the operation
3223 case TargetLowering::Expand: {
3224 MVT VT = Op.getValueType();
3226 // See if multiply or divide can be lowered using two-result operations.
3227 SDVTList VTs = DAG.getVTList(VT, VT);
3228 if (Node->getOpcode() == ISD::MUL) {
3229 // We just need the low half of the multiply; try both the signed
3230 // and unsigned forms. If the target supports both SMUL_LOHI and
3231 // UMUL_LOHI, form a preference by checking which forms of plain
3232 // MULH it supports.
3233 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3234 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3235 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3236 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3237 unsigned OpToUse = 0;
3238 if (HasSMUL_LOHI && !HasMULHS) {
3239 OpToUse = ISD::SMUL_LOHI;
3240 } else if (HasUMUL_LOHI && !HasMULHU) {
3241 OpToUse = ISD::UMUL_LOHI;
3242 } else if (HasSMUL_LOHI) {
3243 OpToUse = ISD::SMUL_LOHI;
3244 } else if (HasUMUL_LOHI) {
3245 OpToUse = ISD::UMUL_LOHI;
3248 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3253 if (Node->getOpcode() == ISD::MULHS &&
3254 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3255 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3256 VTs, Tmp1, Tmp2).getNode(),
3260 if (Node->getOpcode() == ISD::MULHU &&
3261 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3262 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3263 VTs, Tmp1, Tmp2).getNode(),
3267 if (Node->getOpcode() == ISD::SDIV &&
3268 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3269 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3270 VTs, Tmp1, Tmp2).getNode(),
3274 if (Node->getOpcode() == ISD::UDIV &&
3275 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3276 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3277 VTs, Tmp1, Tmp2).getNode(),
3282 // Check to see if we have a libcall for this operator.
3283 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3284 bool isSigned = false;
3285 switch (Node->getOpcode()) {
3288 if (VT == MVT::i32) {
3289 LC = Node->getOpcode() == ISD::UDIV
3290 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3291 isSigned = Node->getOpcode() == ISD::SDIV;
3296 LC = RTLIB::MUL_I32;
3297 else if (VT == MVT::i64)
3298 LC = RTLIB::MUL_I64;
3301 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3302 RTLIB::POW_PPCF128);
3305 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3306 RTLIB::DIV_PPCF128);
3310 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3312 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3316 assert(Node->getValueType(0).isVector() &&
3317 "Cannot expand this binary operator!");
3318 // Expand the operation into a bunch of nasty scalar code.
3319 Result = LegalizeOp(UnrollVectorOp(Op));
3322 case TargetLowering::Promote: {
3323 switch (Node->getOpcode()) {
3324 default: assert(0 && "Do not know how to promote this BinOp!");
3328 MVT OVT = Node->getValueType(0);
3329 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3330 assert(OVT.isVector() && "Cannot promote this BinOp!");
3331 // Bit convert each of the values to the new type.
3332 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3333 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3334 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3335 // Bit convert the result back the original type.
3336 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3344 case ISD::SMUL_LOHI:
3345 case ISD::UMUL_LOHI:
3348 // These nodes will only be produced by target-specific lowering, so
3349 // they shouldn't be here if they aren't legal.
3350 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3351 "This must be legal!");
3353 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3354 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3355 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3358 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3359 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3360 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3361 case Expand: assert(0 && "Not possible");
3363 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3366 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3370 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3372 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3373 default: assert(0 && "Operation not supported");
3374 case TargetLowering::Custom:
3375 Tmp1 = TLI.LowerOperation(Result, DAG);
3376 if (Tmp1.getNode()) Result = Tmp1;
3378 case TargetLowering::Legal: break;
3379 case TargetLowering::Expand: {
3380 // If this target supports fabs/fneg natively and select is cheap,
3381 // do this efficiently.
3382 if (!TLI.isSelectExpensive() &&
3383 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3384 TargetLowering::Legal &&
3385 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3386 TargetLowering::Legal) {
3387 // Get the sign bit of the RHS.
3389 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3390 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3391 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3392 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3393 // Get the absolute value of the result.
3394 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3395 // Select between the nabs and abs value based on the sign bit of
3397 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3398 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
3401 Result = LegalizeOp(Result);
3405 // Otherwise, do bitwise ops!
3407 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3408 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3409 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3410 Result = LegalizeOp(Result);
3418 Tmp1 = LegalizeOp(Node->getOperand(0));
3419 Tmp2 = LegalizeOp(Node->getOperand(1));
3420 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3421 Tmp3 = Result.getValue(0);
3422 Tmp4 = Result.getValue(1);
3424 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3425 default: assert(0 && "This action is not supported yet!");
3426 case TargetLowering::Legal:
3428 case TargetLowering::Custom:
3429 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3430 if (Tmp1.getNode() != NULL) {
3431 Tmp3 = LegalizeOp(Tmp1);
3432 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3436 // Since this produces two values, make sure to remember that we legalized
3438 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3439 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3440 return Op.getResNo() ? Tmp4 : Tmp3;
3444 Tmp1 = LegalizeOp(Node->getOperand(0));
3445 Tmp2 = LegalizeOp(Node->getOperand(1));
3446 Tmp3 = LegalizeOp(Node->getOperand(2));
3447 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3448 Tmp3 = Result.getValue(0);
3449 Tmp4 = Result.getValue(1);
3451 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3452 default: assert(0 && "This action is not supported yet!");
3453 case TargetLowering::Legal:
3455 case TargetLowering::Custom:
3456 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3457 if (Tmp1.getNode() != NULL) {
3458 Tmp3 = LegalizeOp(Tmp1);
3459 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3463 // Since this produces two values, make sure to remember that we legalized
3465 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3466 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3467 return Op.getResNo() ? Tmp4 : Tmp3;
3469 case ISD::BUILD_PAIR: {
3470 MVT PairTy = Node->getValueType(0);
3471 // TODO: handle the case where the Lo and Hi operands are not of legal type
3472 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3473 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3474 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3475 case TargetLowering::Promote:
3476 case TargetLowering::Custom:
3477 assert(0 && "Cannot promote/custom this yet!");
3478 case TargetLowering::Legal:
3479 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3480 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3482 case TargetLowering::Expand:
3483 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3484 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3485 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3486 DAG.getConstant(PairTy.getSizeInBits()/2,
3487 TLI.getShiftAmountTy()));
3488 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3497 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3498 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3500 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3501 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3502 case TargetLowering::Custom:
3505 case TargetLowering::Legal:
3506 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3508 Tmp1 = TLI.LowerOperation(Result, DAG);
3509 if (Tmp1.getNode()) Result = Tmp1;
3512 case TargetLowering::Expand: {
3513 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3514 bool isSigned = DivOpc == ISD::SDIV;
3515 MVT VT = Node->getValueType(0);
3517 // See if remainder can be lowered using two-result operations.
3518 SDVTList VTs = DAG.getVTList(VT, VT);
3519 if (Node->getOpcode() == ISD::SREM &&
3520 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3521 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3522 VTs, Tmp1, Tmp2).getNode(), 1);
3525 if (Node->getOpcode() == ISD::UREM &&
3526 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3527 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3528 VTs, Tmp1, Tmp2).getNode(), 1);
3532 if (VT.isInteger()) {
3533 if (TLI.getOperationAction(DivOpc, VT) ==
3534 TargetLowering::Legal) {
3536 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3537 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3538 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3539 } else if (VT.isVector()) {
3540 Result = LegalizeOp(UnrollVectorOp(Op));
3542 assert(VT == MVT::i32 &&
3543 "Cannot expand this binary operator!");
3544 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3545 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3547 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3550 assert(VT.isFloatingPoint() &&
3551 "remainder op must have integer or floating-point type");
3552 if (VT.isVector()) {
3553 Result = LegalizeOp(UnrollVectorOp(Op));
3555 // Floating point mod -> fmod libcall.
3556 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3557 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3559 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3567 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3568 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3570 MVT VT = Node->getValueType(0);
3571 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3572 default: assert(0 && "This action is not supported yet!");
3573 case TargetLowering::Custom:
3576 case TargetLowering::Legal:
3577 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3578 Result = Result.getValue(0);
3579 Tmp1 = Result.getValue(1);
3582 Tmp2 = TLI.LowerOperation(Result, DAG);
3583 if (Tmp2.getNode()) {
3584 Result = LegalizeOp(Tmp2);
3585 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3589 case TargetLowering::Expand: {
3590 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3591 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3592 // Increment the pointer, VAList, to the next vaarg
3593 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3594 DAG.getConstant(TLI.getTargetData()->
3595 getTypePaddedSize(VT.getTypeForMVT()),
3596 TLI.getPointerTy()));
3597 // Store the incremented VAList to the legalized pointer
3598 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3599 // Load the actual argument out of the pointer VAList
3600 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3601 Tmp1 = LegalizeOp(Result.getValue(1));
3602 Result = LegalizeOp(Result);
3606 // Since VAARG produces two values, make sure to remember that we
3607 // legalized both of them.
3608 AddLegalizedOperand(SDValue(Node, 0), Result);
3609 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3610 return Op.getResNo() ? Tmp1 : Result;
3614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3615 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3616 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3618 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3619 default: assert(0 && "This action is not supported yet!");
3620 case TargetLowering::Custom:
3623 case TargetLowering::Legal:
3624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3625 Node->getOperand(3), Node->getOperand(4));
3627 Tmp1 = TLI.LowerOperation(Result, DAG);
3628 if (Tmp1.getNode()) Result = Tmp1;
3631 case TargetLowering::Expand:
3632 // This defaults to loading a pointer from the input and storing it to the
3633 // output, returning the chain.
3634 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3635 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3636 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3637 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3643 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3644 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3646 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3647 default: assert(0 && "This action is not supported yet!");
3648 case TargetLowering::Custom:
3651 case TargetLowering::Legal:
3652 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3654 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3655 if (Tmp1.getNode()) Result = Tmp1;
3658 case TargetLowering::Expand:
3659 Result = Tmp1; // Default to a no-op, return the chain
3665 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3666 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3668 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3670 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3671 default: assert(0 && "This action is not supported yet!");
3672 case TargetLowering::Legal: break;
3673 case TargetLowering::Custom:
3674 Tmp1 = TLI.LowerOperation(Result, DAG);
3675 if (Tmp1.getNode()) Result = Tmp1;
3682 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3683 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3684 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3685 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3687 assert(0 && "ROTL/ROTR legalize operation not supported");
3689 case TargetLowering::Legal:
3691 case TargetLowering::Custom:
3692 Tmp1 = TLI.LowerOperation(Result, DAG);
3693 if (Tmp1.getNode()) Result = Tmp1;
3695 case TargetLowering::Promote:
3696 assert(0 && "Do not know how to promote ROTL/ROTR");
3698 case TargetLowering::Expand:
3699 assert(0 && "Do not know how to expand ROTL/ROTR");
3705 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3706 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3707 case TargetLowering::Custom:
3708 assert(0 && "Cannot custom legalize this yet!");
3709 case TargetLowering::Legal:
3710 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3712 case TargetLowering::Promote: {
3713 MVT OVT = Tmp1.getValueType();
3714 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3715 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3717 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3718 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3719 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3720 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3723 case TargetLowering::Expand:
3724 Result = ExpandBSWAP(Tmp1, dl);
3732 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3733 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3734 case TargetLowering::Custom:
3735 case TargetLowering::Legal:
3736 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3737 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3738 TargetLowering::Custom) {
3739 Tmp1 = TLI.LowerOperation(Result, DAG);
3740 if (Tmp1.getNode()) {
3745 case TargetLowering::Promote: {
3746 MVT OVT = Tmp1.getValueType();
3747 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3749 // Zero extend the argument.
3750 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3751 // Perform the larger operation, then subtract if needed.
3752 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3753 switch (Node->getOpcode()) {
3758 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3759 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3760 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3762 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3763 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3766 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3767 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3768 DAG.getConstant(NVT.getSizeInBits() -
3769 OVT.getSizeInBits(), NVT));
3774 case TargetLowering::Expand:
3775 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3795 case ISD::FNEARBYINT:
3796 Tmp1 = LegalizeOp(Node->getOperand(0));
3797 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3798 case TargetLowering::Promote:
3799 case TargetLowering::Custom:
3802 case TargetLowering::Legal:
3803 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3805 Tmp1 = TLI.LowerOperation(Result, DAG);
3806 if (Tmp1.getNode()) Result = Tmp1;
3809 case TargetLowering::Expand:
3810 switch (Node->getOpcode()) {
3811 default: assert(0 && "Unreachable!");
3813 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3814 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3815 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3818 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3819 MVT VT = Node->getValueType(0);
3820 Tmp2 = DAG.getConstantFP(0.0, VT);
3821 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3822 Tmp1, Tmp2, ISD::SETUGT);
3823 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3824 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3839 case ISD::FNEARBYINT: {
3840 MVT VT = Node->getValueType(0);
3842 // Expand unsupported unary vector operators by unrolling them.
3843 if (VT.isVector()) {
3844 Result = LegalizeOp(UnrollVectorOp(Op));
3848 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3849 switch(Node->getOpcode()) {
3851 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3852 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3855 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3856 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3859 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3860 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3863 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3864 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3867 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3868 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3871 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3872 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3875 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3876 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3879 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3880 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3883 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3884 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3887 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3888 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3891 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3892 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3895 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3896 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3898 case ISD::FNEARBYINT:
3899 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3900 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3903 default: assert(0 && "Unreachable!");
3906 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3914 MVT VT = Node->getValueType(0);
3916 // Expand unsupported unary vector operators by unrolling them.
3917 if (VT.isVector()) {
3918 Result = LegalizeOp(UnrollVectorOp(Op));
3922 // We always lower FPOWI into a libcall. No target support for it yet.
3923 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3924 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3926 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3929 case ISD::BIT_CONVERT:
3930 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3931 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3932 Node->getValueType(0), dl);
3933 } else if (Op.getOperand(0).getValueType().isVector()) {
3934 // The input has to be a vector type, we have to either scalarize it, pack
3935 // it, or convert it based on whether the input vector type is legal.
3936 SDNode *InVal = Node->getOperand(0).getNode();
3937 int InIx = Node->getOperand(0).getResNo();
3938 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3939 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3941 // Figure out if there is a simple type corresponding to this Vector
3942 // type. If so, convert to the vector type.
3943 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3944 if (TLI.isTypeLegal(TVT)) {
3945 // Turn this into a bit convert of the vector input.
3946 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3947 LegalizeOp(Node->getOperand(0)));
3949 } else if (NumElems == 1) {
3950 // Turn this into a bit convert of the scalar input.
3951 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3952 ScalarizeVectorOp(Node->getOperand(0)));
3955 // FIXME: UNIMP! Store then reload
3956 assert(0 && "Cast from unsupported vector type not implemented yet!");
3959 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3960 Node->getOperand(0).getValueType())) {
3961 default: assert(0 && "Unknown operation action!");
3962 case TargetLowering::Expand:
3963 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3964 Node->getValueType(0), dl);
3966 case TargetLowering::Legal:
3967 Tmp1 = LegalizeOp(Node->getOperand(0));
3968 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3973 case ISD::CONVERT_RNDSAT: {
3974 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3976 default: assert(0 && "Unknown cvt code!");
3987 SDValue DTyOp = Node->getOperand(1);
3988 SDValue STyOp = Node->getOperand(2);
3989 SDValue RndOp = Node->getOperand(3);
3990 SDValue SatOp = Node->getOperand(4);
3991 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3992 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3994 Tmp1 = LegalizeOp(Node->getOperand(0));
3995 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
3997 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3998 TargetLowering::Custom) {
3999 Tmp1 = TLI.LowerOperation(Result, DAG);
4000 if (Tmp1.getNode()) Result = Tmp1;
4004 Result = PromoteOp(Node->getOperand(0));
4005 // For FP, make Op1 a i32
4007 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
4008 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4013 } // end switch CvtCode
4016 // Conversion operators. The source and destination have different types.
4017 case ISD::SINT_TO_FP:
4018 case ISD::UINT_TO_FP: {
4019 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4020 Result = LegalizeINT_TO_FP(Result, isSigned,
4021 Node->getValueType(0), Node->getOperand(0), dl);
4025 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4027 Tmp1 = LegalizeOp(Node->getOperand(0));
4028 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4029 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4030 case TargetLowering::Custom:
4033 case TargetLowering::Legal:
4034 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4036 Tmp1 = TLI.LowerOperation(Result, DAG);
4037 if (Tmp1.getNode()) Result = Tmp1;
4040 case TargetLowering::Expand:
4041 assert(Result.getValueType().isVector() && "must be vector type");
4042 // Unroll the truncate. We should do better.
4043 Result = LegalizeOp(UnrollVectorOp(Result));
4047 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4049 // Since the result is legal, we should just be able to truncate the low
4050 // part of the source.
4051 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4054 Result = PromoteOp(Node->getOperand(0));
4055 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4060 case ISD::FP_TO_SINT:
4061 case ISD::FP_TO_UINT:
4062 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4064 Tmp1 = LegalizeOp(Node->getOperand(0));
4066 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4067 default: assert(0 && "Unknown operation action!");
4068 case TargetLowering::Custom:
4071 case TargetLowering::Legal:
4072 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4074 Tmp1 = TLI.LowerOperation(Result, DAG);
4075 if (Tmp1.getNode()) Result = Tmp1;
4078 case TargetLowering::Promote:
4079 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4080 Node->getOpcode() == ISD::FP_TO_SINT,
4083 case TargetLowering::Expand:
4084 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4085 SDValue True, False;
4086 MVT VT = Node->getOperand(0).getValueType();
4087 MVT NVT = Node->getValueType(0);
4088 const uint64_t zero[] = {0, 0};
4089 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4090 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4091 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4092 Tmp2 = DAG.getConstantFP(apf, VT);
4093 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4094 Node->getOperand(0),
4096 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4097 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4098 DAG.getNode(ISD::FSUB, dl, VT,
4099 Node->getOperand(0), Tmp2));
4100 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4101 DAG.getConstant(x, NVT));
4102 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4105 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4111 MVT VT = Op.getValueType();
4112 MVT OVT = Node->getOperand(0).getValueType();
4113 // Convert ppcf128 to i32
4114 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4115 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4116 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4117 Node->getOperand(0), DAG.getValueType(MVT::f64));
4118 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4119 DAG.getIntPtrConstant(1));
4120 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4122 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4123 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4124 Tmp2 = DAG.getConstantFP(apf, OVT);
4125 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4126 // FIXME: generated code sucks.
4127 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4129 DAG.getNode(ISD::ADD, dl, MVT::i32,
4130 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4131 DAG.getNode(ISD::FSUB, dl, OVT,
4132 Node->getOperand(0), Tmp2)),
4133 DAG.getConstant(0x80000000, MVT::i32)),
4134 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4135 Node->getOperand(0)),
4136 DAG.getCondCode(ISD::SETGE));
4140 // Convert f32 / f64 to i32 / i64 / i128.
4141 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4142 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4143 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4145 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4149 Tmp1 = PromoteOp(Node->getOperand(0));
4150 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4151 Result = LegalizeOp(Result);
4156 case ISD::FP_EXTEND: {
4157 MVT DstVT = Op.getValueType();
4158 MVT SrcVT = Op.getOperand(0).getValueType();
4159 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4160 // The only other way we can lower this is to turn it into a STORE,
4161 // LOAD pair, targetting a temporary location (a stack slot).
4162 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4165 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4166 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4168 Tmp1 = LegalizeOp(Node->getOperand(0));
4169 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4172 Tmp1 = PromoteOp(Node->getOperand(0));
4173 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4178 case ISD::FP_ROUND: {
4179 MVT DstVT = Op.getValueType();
4180 MVT SrcVT = Op.getOperand(0).getValueType();
4181 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4182 if (SrcVT == MVT::ppcf128) {
4184 ExpandOp(Node->getOperand(0), Lo, Result);
4185 // Round it the rest of the way (e.g. to f32) if needed.
4186 if (DstVT!=MVT::f64)
4187 Result = DAG.getNode(ISD::FP_ROUND, dl,
4188 DstVT, Result, Op.getOperand(1));
4191 // The only other way we can lower this is to turn it into a STORE,
4192 // LOAD pair, targetting a temporary location (a stack slot).
4193 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4196 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4197 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4199 Tmp1 = LegalizeOp(Node->getOperand(0));
4200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4203 Tmp1 = PromoteOp(Node->getOperand(0));
4204 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4205 Node->getOperand(1));
4210 case ISD::ANY_EXTEND:
4211 case ISD::ZERO_EXTEND:
4212 case ISD::SIGN_EXTEND:
4213 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4214 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4216 Tmp1 = LegalizeOp(Node->getOperand(0));
4217 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4218 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4219 TargetLowering::Custom) {
4220 Tmp1 = TLI.LowerOperation(Result, DAG);
4221 if (Tmp1.getNode()) Result = Tmp1;
4225 switch (Node->getOpcode()) {
4226 case ISD::ANY_EXTEND:
4227 Tmp1 = PromoteOp(Node->getOperand(0));
4228 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4230 case ISD::ZERO_EXTEND:
4231 Result = PromoteOp(Node->getOperand(0));
4232 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4233 Result = DAG.getZeroExtendInReg(Result, dl,
4234 Node->getOperand(0).getValueType());
4236 case ISD::SIGN_EXTEND:
4237 Result = PromoteOp(Node->getOperand(0));
4238 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4239 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4241 DAG.getValueType(Node->getOperand(0).getValueType()));
4246 case ISD::FP_ROUND_INREG:
4247 case ISD::SIGN_EXTEND_INREG: {
4248 Tmp1 = LegalizeOp(Node->getOperand(0));
4249 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4251 // If this operation is not supported, convert it to a shl/shr or load/store
4253 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4254 default: assert(0 && "This action not supported for this op yet!");
4255 case TargetLowering::Legal:
4256 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4258 case TargetLowering::Expand:
4259 // If this is an integer extend and shifts are supported, do that.
4260 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4261 // NOTE: we could fall back on load/store here too for targets without
4262 // SAR. However, it is doubtful that any exist.
4263 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4264 ExtraVT.getSizeInBits();
4265 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4266 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4267 Node->getOperand(0), ShiftCst);
4268 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4270 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4271 // The only way we can lower this is to turn it into a TRUNCSTORE,
4272 // EXTLOAD pair, targetting a temporary location (a stack slot).
4274 // NOTE: there is a choice here between constantly creating new stack
4275 // slots and always reusing the same one. We currently always create
4276 // new ones, as reuse may inhibit scheduling.
4277 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4278 Node->getValueType(0), dl);
4280 assert(0 && "Unknown op");
4286 case ISD::TRAMPOLINE: {
4288 for (unsigned i = 0; i != 6; ++i)
4289 Ops[i] = LegalizeOp(Node->getOperand(i));
4290 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4291 // The only option for this node is to custom lower it.
4292 Result = TLI.LowerOperation(Result, DAG);
4293 assert(Result.getNode() && "Should always custom lower!");
4295 // Since trampoline produces two values, make sure to remember that we
4296 // legalized both of them.
4297 Tmp1 = LegalizeOp(Result.getValue(1));
4298 Result = LegalizeOp(Result);
4299 AddLegalizedOperand(SDValue(Node, 0), Result);
4300 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4301 return Op.getResNo() ? Tmp1 : Result;
4303 case ISD::FLT_ROUNDS_: {
4304 MVT VT = Node->getValueType(0);
4305 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4306 default: assert(0 && "This action not supported for this op yet!");
4307 case TargetLowering::Custom:
4308 Result = TLI.LowerOperation(Op, DAG);
4309 if (Result.getNode()) break;
4311 case TargetLowering::Legal:
4312 // If this operation is not supported, lower it to constant 1
4313 Result = DAG.getConstant(1, VT);
4319 MVT VT = Node->getValueType(0);
4320 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4321 default: assert(0 && "This action not supported for this op yet!");
4322 case TargetLowering::Legal:
4323 Tmp1 = LegalizeOp(Node->getOperand(0));
4324 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4326 case TargetLowering::Custom:
4327 Result = TLI.LowerOperation(Op, DAG);
4328 if (Result.getNode()) break;
4330 case TargetLowering::Expand:
4331 // If this operation is not supported, lower it to 'abort()' call
4332 Tmp1 = LegalizeOp(Node->getOperand(0));
4333 TargetLowering::ArgListTy Args;
4334 std::pair<SDValue, SDValue> CallResult =
4335 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4336 false, false, false, false, CallingConv::C, false,
4337 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4339 Result = CallResult.second;
4347 MVT VT = Node->getValueType(0);
4348 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4349 default: assert(0 && "This action not supported for this op yet!");
4350 case TargetLowering::Custom:
4351 Result = TLI.LowerOperation(Op, DAG);
4352 if (Result.getNode()) break;
4354 case TargetLowering::Legal: {
4355 SDValue LHS = LegalizeOp(Node->getOperand(0));
4356 SDValue RHS = LegalizeOp(Node->getOperand(1));
4358 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4359 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4361 MVT OType = Node->getValueType(1);
4363 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4365 // LHSSign -> LHS >= 0
4366 // RHSSign -> RHS >= 0
4367 // SumSign -> Sum >= 0
4370 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4372 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4374 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4375 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4376 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4377 Node->getOpcode() == ISD::SADDO ?
4378 ISD::SETEQ : ISD::SETNE);
4380 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4381 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4383 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4385 MVT ValueVTs[] = { LHS.getValueType(), OType };
4386 SDValue Ops[] = { Sum, Cmp };
4388 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4389 DAG.getVTList(&ValueVTs[0], 2),
4391 SDNode *RNode = Result.getNode();
4392 DAG.ReplaceAllUsesWith(Node, RNode);
4401 MVT VT = Node->getValueType(0);
4402 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4403 default: assert(0 && "This action not supported for this op yet!");
4404 case TargetLowering::Custom:
4405 Result = TLI.LowerOperation(Op, DAG);
4406 if (Result.getNode()) break;
4408 case TargetLowering::Legal: {
4409 SDValue LHS = LegalizeOp(Node->getOperand(0));
4410 SDValue RHS = LegalizeOp(Node->getOperand(1));
4412 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4413 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4415 MVT OType = Node->getValueType(1);
4416 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4417 Node->getOpcode () == ISD::UADDO ?
4418 ISD::SETULT : ISD::SETUGT);
4420 MVT ValueVTs[] = { LHS.getValueType(), OType };
4421 SDValue Ops[] = { Sum, Cmp };
4423 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4424 DAG.getVTList(&ValueVTs[0], 2),
4426 SDNode *RNode = Result.getNode();
4427 DAG.ReplaceAllUsesWith(Node, RNode);
4436 MVT VT = Node->getValueType(0);
4437 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4438 default: assert(0 && "This action is not supported at all!");
4439 case TargetLowering::Custom:
4440 Result = TLI.LowerOperation(Op, DAG);
4441 if (Result.getNode()) break;
4443 case TargetLowering::Legal:
4444 // FIXME: According to Hacker's Delight, this can be implemented in
4445 // target independent lowering, but it would be inefficient, since it
4446 // requires a division + a branch.
4447 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4455 assert(Result.getValueType() == Op.getValueType() &&
4456 "Bad legalization!");
4458 // Make sure that the generated code is itself legal.
4460 Result = LegalizeOp(Result);
4462 // Note that LegalizeOp may be reentered even from single-use nodes, which
4463 // means that we always must cache transformed nodes.
4464 AddLegalizedOperand(Op, Result);
4468 /// PromoteOp - Given an operation that produces a value in an invalid type,
4469 /// promote it to compute the value into a larger type. The produced value will
4470 /// have the correct bits for the low portion of the register, but no guarantee
4471 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4472 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4473 MVT VT = Op.getValueType();
4474 MVT NVT = TLI.getTypeToTransformTo(VT);
4475 assert(getTypeAction(VT) == Promote &&
4476 "Caller should expand or legalize operands that are not promotable!");
4477 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4478 "Cannot promote to smaller type!");
4480 SDValue Tmp1, Tmp2, Tmp3;
4482 SDNode *Node = Op.getNode();
4483 DebugLoc dl = Node->getDebugLoc();
4485 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4486 if (I != PromotedNodes.end()) return I->second;
4488 switch (Node->getOpcode()) {
4489 case ISD::CopyFromReg:
4490 assert(0 && "CopyFromReg must be legal!");
4493 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4495 assert(0 && "Do not know how to promote this operator!");
4498 Result = DAG.getUNDEF(NVT);
4502 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4504 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4505 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4507 case ISD::ConstantFP:
4508 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4509 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4513 MVT VT0 = Node->getOperand(0).getValueType();
4514 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4515 && "SetCC type is not legal??");
4516 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4517 Node->getOperand(0), Node->getOperand(1),
4518 Node->getOperand(2));
4522 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4524 Result = LegalizeOp(Node->getOperand(0));
4525 assert(Result.getValueType().bitsGE(NVT) &&
4526 "This truncation doesn't make sense!");
4527 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4528 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4531 // The truncation is not required, because we don't guarantee anything
4532 // about high bits anyway.
4533 Result = PromoteOp(Node->getOperand(0));
4536 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4537 // Truncate the low part of the expanded value to the result type
4538 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4541 case ISD::SIGN_EXTEND:
4542 case ISD::ZERO_EXTEND:
4543 case ISD::ANY_EXTEND:
4544 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4545 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4547 // Input is legal? Just do extend all the way to the larger type.
4548 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4551 // Promote the reg if it's smaller.
4552 Result = PromoteOp(Node->getOperand(0));
4553 // The high bits are not guaranteed to be anything. Insert an extend.
4554 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4555 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4556 DAG.getValueType(Node->getOperand(0).getValueType()));
4557 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4558 Result = DAG.getZeroExtendInReg(Result, dl,
4559 Node->getOperand(0).getValueType());
4563 case ISD::CONVERT_RNDSAT: {
4564 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4565 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4566 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4567 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4568 "can only promote integers");
4569 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
4570 Node->getOperand(1), Node->getOperand(2),
4571 Node->getOperand(3), Node->getOperand(4),
4576 case ISD::BIT_CONVERT:
4577 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4578 Node->getValueType(0), dl);
4579 Result = PromoteOp(Result);
4582 case ISD::FP_EXTEND:
4583 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4585 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4586 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4587 case Promote: assert(0 && "Unreachable with 2 FP types!");
4589 if (Node->getConstantOperandVal(1) == 0) {
4590 // Input is legal? Do an FP_ROUND_INREG.
4591 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4592 DAG.getValueType(VT));
4594 // Just remove the truncate, it isn't affecting the value.
4595 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4596 Node->getOperand(1));
4601 case ISD::SINT_TO_FP:
4602 case ISD::UINT_TO_FP:
4603 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4605 // No extra round required here.
4606 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4610 Result = PromoteOp(Node->getOperand(0));
4611 if (Node->getOpcode() == ISD::SINT_TO_FP)
4612 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4614 DAG.getValueType(Node->getOperand(0).getValueType()));
4616 Result = DAG.getZeroExtendInReg(Result, dl,
4617 Node->getOperand(0).getValueType());
4618 // No extra round required here.
4619 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4622 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4623 Node->getOperand(0), dl);
4624 // Round if we cannot tolerate excess precision.
4625 if (NoExcessFPPrecision)
4626 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4627 DAG.getValueType(VT));
4632 case ISD::SIGN_EXTEND_INREG:
4633 Result = PromoteOp(Node->getOperand(0));
4634 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4635 Node->getOperand(1));
4637 case ISD::FP_TO_SINT:
4638 case ISD::FP_TO_UINT:
4639 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4642 Tmp1 = Node->getOperand(0);
4645 // The input result is prerounded, so we don't have to do anything
4647 Tmp1 = PromoteOp(Node->getOperand(0));
4650 // If we're promoting a UINT to a larger size, check to see if the new node
4651 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4652 // we can use that instead. This allows us to generate better code for
4653 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4654 // legal, such as PowerPC.
4655 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4656 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4657 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4658 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4659 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4661 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4667 Tmp1 = PromoteOp(Node->getOperand(0));
4668 assert(Tmp1.getValueType() == NVT);
4669 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4670 // NOTE: we do not have to do any extra rounding here for
4671 // NoExcessFPPrecision, because we know the input will have the appropriate
4672 // precision, and these operations don't modify precision at all.
4687 case ISD::FNEARBYINT:
4688 Tmp1 = PromoteOp(Node->getOperand(0));
4689 assert(Tmp1.getValueType() == NVT);
4690 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4691 if (NoExcessFPPrecision)
4692 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4693 DAG.getValueType(VT));
4698 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4699 // directly as well, which may be better.
4700 Tmp1 = PromoteOp(Node->getOperand(0));
4701 Tmp2 = Node->getOperand(1);
4702 if (Node->getOpcode() == ISD::FPOW)
4703 Tmp2 = PromoteOp(Tmp2);
4704 assert(Tmp1.getValueType() == NVT);
4705 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4706 if (NoExcessFPPrecision)
4707 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4708 DAG.getValueType(VT));
4712 case ISD::ATOMIC_CMP_SWAP: {
4713 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4714 Tmp2 = PromoteOp(Node->getOperand(2));
4715 Tmp3 = PromoteOp(Node->getOperand(3));
4716 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4717 AtomNode->getChain(),
4718 AtomNode->getBasePtr(), Tmp2, Tmp3,
4719 AtomNode->getSrcValue(),
4720 AtomNode->getAlignment());
4721 // Remember that we legalized the chain.
4722 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4725 case ISD::ATOMIC_LOAD_ADD:
4726 case ISD::ATOMIC_LOAD_SUB:
4727 case ISD::ATOMIC_LOAD_AND:
4728 case ISD::ATOMIC_LOAD_OR:
4729 case ISD::ATOMIC_LOAD_XOR:
4730 case ISD::ATOMIC_LOAD_NAND:
4731 case ISD::ATOMIC_LOAD_MIN:
4732 case ISD::ATOMIC_LOAD_MAX:
4733 case ISD::ATOMIC_LOAD_UMIN:
4734 case ISD::ATOMIC_LOAD_UMAX:
4735 case ISD::ATOMIC_SWAP: {
4736 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4737 Tmp2 = PromoteOp(Node->getOperand(2));
4738 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4739 AtomNode->getChain(),
4740 AtomNode->getBasePtr(), Tmp2,
4741 AtomNode->getSrcValue(),
4742 AtomNode->getAlignment());
4743 // Remember that we legalized the chain.
4744 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4754 // The input may have strange things in the top bits of the registers, but
4755 // these operations don't care. They may have weird bits going out, but
4756 // that too is okay if they are integer operations.
4757 Tmp1 = PromoteOp(Node->getOperand(0));
4758 Tmp2 = PromoteOp(Node->getOperand(1));
4759 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4760 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4765 Tmp1 = PromoteOp(Node->getOperand(0));
4766 Tmp2 = PromoteOp(Node->getOperand(1));
4767 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4768 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4770 // Floating point operations will give excess precision that we may not be
4771 // able to tolerate. If we DO allow excess precision, just leave it,
4772 // otherwise excise it.
4773 // FIXME: Why would we need to round FP ops more than integer ones?
4774 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4775 if (NoExcessFPPrecision)
4776 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4777 DAG.getValueType(VT));
4782 // These operators require that their input be sign extended.
4783 Tmp1 = PromoteOp(Node->getOperand(0));
4784 Tmp2 = PromoteOp(Node->getOperand(1));
4785 if (NVT.isInteger()) {
4786 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4787 DAG.getValueType(VT));
4788 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4789 DAG.getValueType(VT));
4791 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4793 // Perform FP_ROUND: this is probably overly pessimistic.
4794 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4795 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4796 DAG.getValueType(VT));
4800 case ISD::FCOPYSIGN:
4801 // These operators require that their input be fp extended.
4802 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4803 case Expand: assert(0 && "not implemented");
4804 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4805 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4807 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4808 case Expand: assert(0 && "not implemented");
4809 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4810 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4812 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4814 // Perform FP_ROUND: this is probably overly pessimistic.
4815 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4816 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4817 DAG.getValueType(VT));
4822 // These operators require that their input be zero extended.
4823 Tmp1 = PromoteOp(Node->getOperand(0));
4824 Tmp2 = PromoteOp(Node->getOperand(1));
4825 assert(NVT.isInteger() && "Operators don't apply to FP!");
4826 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4827 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4828 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4832 Tmp1 = PromoteOp(Node->getOperand(0));
4833 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4836 // The input value must be properly sign extended.
4837 Tmp1 = PromoteOp(Node->getOperand(0));
4838 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4839 DAG.getValueType(VT));
4840 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4843 // The input value must be properly zero extended.
4844 Tmp1 = PromoteOp(Node->getOperand(0));
4845 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4846 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4850 Tmp1 = Node->getOperand(0); // Get the chain.
4851 Tmp2 = Node->getOperand(1); // Get the pointer.
4852 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4853 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
4854 Result = TLI.LowerOperation(Tmp3, DAG);
4856 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4857 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
4858 // Increment the pointer, VAList, to the next vaarg
4859 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4860 DAG.getConstant(VT.getSizeInBits()/8,
4861 TLI.getPointerTy()));
4862 // Store the incremented VAList to the legalized pointer
4863 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4864 // Load the actual argument out of the pointer VAList
4865 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4867 // Remember that we legalized the chain.
4868 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4872 LoadSDNode *LD = cast<LoadSDNode>(Node);
4873 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4874 ? ISD::EXTLOAD : LD->getExtensionType();
4875 Result = DAG.getExtLoad(ExtType, dl, NVT,
4876 LD->getChain(), LD->getBasePtr(),
4877 LD->getSrcValue(), LD->getSrcValueOffset(),
4880 LD->getAlignment());
4881 // Remember that we legalized the chain.
4882 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4886 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4887 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4889 MVT VT2 = Tmp2.getValueType();
4890 assert(VT2 == Tmp3.getValueType()
4891 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4892 // Ensure that the resulting node is at least the same size as the operands'
4893 // value types, because we cannot assume that TLI.getSetCCValueType() is
4895 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4898 case ISD::SELECT_CC:
4899 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4900 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4901 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4902 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4905 Tmp1 = Node->getOperand(0);
4906 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4907 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4908 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4909 DAG.getConstant(NVT.getSizeInBits() -
4911 TLI.getShiftAmountTy()));
4916 // Zero extend the argument
4917 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4918 // Perform the larger operation, then subtract if needed.
4919 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4920 switch(Node->getOpcode()) {
4925 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4926 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4927 DAG.getConstant(NVT.getSizeInBits(), NVT),
4929 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4930 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4933 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4934 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4935 DAG.getConstant(NVT.getSizeInBits() -
4936 VT.getSizeInBits(), NVT));
4940 case ISD::EXTRACT_SUBVECTOR:
4941 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4943 case ISD::EXTRACT_VECTOR_ELT:
4944 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4948 assert(Result.getNode() && "Didn't set a result!");
4950 // Make sure the result is itself legal.
4951 Result = LegalizeOp(Result);
4953 // Remember that we promoted this!
4954 AddPromotedOperand(Op, Result);
4958 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4959 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4960 /// based on the vector type. The return type of this matches the element type
4961 /// of the vector, which may not be legal for the target.
4962 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
4963 // We know that operand #0 is the Vec vector. If the index is a constant
4964 // or if the invec is a supported hardware type, we can use it. Otherwise,
4965 // lower to a store then an indexed load.
4966 SDValue Vec = Op.getOperand(0);
4967 SDValue Idx = Op.getOperand(1);
4968 DebugLoc dl = Op.getDebugLoc();
4970 MVT TVT = Vec.getValueType();
4971 unsigned NumElems = TVT.getVectorNumElements();
4973 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4974 default: assert(0 && "This action is not supported yet!");
4975 case TargetLowering::Custom: {
4976 Vec = LegalizeOp(Vec);
4977 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4978 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
4983 case TargetLowering::Legal:
4984 if (isTypeLegal(TVT)) {
4985 Vec = LegalizeOp(Vec);
4986 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4990 case TargetLowering::Promote:
4991 assert(TVT.isVector() && "not vector type");
4992 // fall thru to expand since vectors are by default are promote
4993 case TargetLowering::Expand:
4997 if (NumElems == 1) {
4998 // This must be an access of the only element. Return it.
4999 Op = ScalarizeVectorOp(Vec);
5000 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5001 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5002 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5004 SplitVectorOp(Vec, Lo, Hi);
5005 if (CIdx->getZExtValue() < NumLoElts) {
5009 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5010 Idx.getValueType());
5013 // It's now an extract from the appropriate high or low part. Recurse.
5014 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5015 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5017 // Store the value to a temporary stack slot, then LOAD the scalar
5018 // element back out.
5019 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5020 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5022 // Add the offset to the index.
5023 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5024 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5025 DAG.getConstant(EltSize, Idx.getValueType()));
5027 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5028 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5030 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5032 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5034 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5039 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5040 /// we assume the operation can be split if it is not already legal.
5041 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5042 // We know that operand #0 is the Vec vector. For now we assume the index
5043 // is a constant and that the extracted result is a supported hardware type.
5044 SDValue Vec = Op.getOperand(0);
5045 SDValue Idx = LegalizeOp(Op.getOperand(1));
5047 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5049 if (NumElems == Op.getValueType().getVectorNumElements()) {
5050 // This must be an access of the desired vector length. Return it.
5054 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5056 SplitVectorOp(Vec, Lo, Hi);
5057 if (CIdx->getZExtValue() < NumElems/2) {
5061 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5062 Idx.getValueType());
5065 // It's now an extract from the appropriate high or low part. Recurse.
5066 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5067 return ExpandEXTRACT_SUBVECTOR(Op);
5070 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5071 /// with condition CC on the current target. This usually involves legalizing
5072 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5073 /// there may be no choice but to create a new SetCC node to represent the
5074 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5075 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5076 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5080 SDValue Tmp1, Tmp2, Tmp3, Result;
5082 switch (getTypeAction(LHS.getValueType())) {
5084 Tmp1 = LegalizeOp(LHS); // LHS
5085 Tmp2 = LegalizeOp(RHS); // RHS
5088 Tmp1 = PromoteOp(LHS); // LHS
5089 Tmp2 = PromoteOp(RHS); // RHS
5091 // If this is an FP compare, the operands have already been extended.
5092 if (LHS.getValueType().isInteger()) {
5093 MVT VT = LHS.getValueType();
5094 MVT NVT = TLI.getTypeToTransformTo(VT);
5096 // Otherwise, we have to insert explicit sign or zero extends. Note
5097 // that we could insert sign extends for ALL conditions, but zero extend
5098 // is cheaper on many machines (an AND instead of two shifts), so prefer
5100 switch (cast<CondCodeSDNode>(CC)->get()) {
5101 default: assert(0 && "Unknown integer comparison!");
5108 // ALL of these operations will work if we either sign or zero extend
5109 // the operands (including the unsigned comparisons!). Zero extend is
5110 // usually a simpler/cheaper operation, so prefer it.
5111 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5112 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5118 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5119 DAG.getValueType(VT));
5120 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5121 DAG.getValueType(VT));
5122 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5123 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5129 MVT VT = LHS.getValueType();
5130 if (VT == MVT::f32 || VT == MVT::f64) {
5131 // Expand into one or more soft-fp libcall(s).
5132 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5133 switch (cast<CondCodeSDNode>(CC)->get()) {
5136 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5140 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5144 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5148 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5152 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5156 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5159 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5162 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5165 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5166 switch (cast<CondCodeSDNode>(CC)->get()) {
5168 // SETONE = SETOLT | SETOGT
5169 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5172 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5175 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5178 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5181 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5184 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5186 default: assert(0 && "Unsupported FP setcc!");
5191 SDValue Ops[2] = { LHS, RHS };
5192 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5193 false /*sign irrelevant*/, Dummy);
5194 Tmp2 = DAG.getConstant(0, MVT::i32);
5195 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5196 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5197 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5198 TLI.getSetCCResultType(Tmp1.getValueType()),
5200 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5201 false /*sign irrelevant*/, Dummy);
5202 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5203 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5204 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5205 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5208 LHS = LegalizeOp(Tmp1);
5213 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5214 ExpandOp(LHS, LHSLo, LHSHi);
5215 ExpandOp(RHS, RHSLo, RHSHi);
5216 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5218 if (VT==MVT::ppcf128) {
5219 // FIXME: This generated code sucks. We want to generate
5220 // FCMPU crN, hi1, hi2
5222 // FCMPU crN, lo1, lo2
5223 // The following can be improved, but not that much.
5224 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5225 LHSHi, RHSHi, ISD::SETOEQ);
5226 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5227 LHSLo, RHSLo, CCCode);
5228 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5229 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5230 LHSHi, RHSHi, ISD::SETUNE);
5231 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5232 LHSHi, RHSHi, CCCode);
5233 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5234 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5243 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5244 if (RHSCST->isAllOnesValue()) {
5245 // Comparison to -1.
5246 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5251 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5252 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5253 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5254 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5257 // If this is a comparison of the sign bit, just look at the top part.
5259 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5260 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5261 CST->isNullValue()) || // X < 0
5262 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5263 CST->isAllOnesValue())) { // X > -1
5269 // FIXME: This generated code sucks.
5270 ISD::CondCode LowCC;
5272 default: assert(0 && "Unknown integer setcc!");
5274 case ISD::SETULT: LowCC = ISD::SETULT; break;
5276 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5278 case ISD::SETULE: LowCC = ISD::SETULE; break;
5280 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5283 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5284 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5285 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5287 // NOTE: on targets without efficient SELECT of bools, we can always use
5288 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5289 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5290 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5291 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5292 if (!Tmp1.getNode())
5293 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5294 LHSLo, RHSLo, LowCC);
5295 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5296 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5297 if (!Tmp2.getNode())
5298 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5299 TLI.getSetCCResultType(LHSHi.getValueType()),
5302 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5303 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5304 if ((Tmp1C && Tmp1C->isNullValue()) ||
5305 (Tmp2C && Tmp2C->isNullValue() &&
5306 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5307 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5308 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5309 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5310 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5311 // low part is known false, returns high part.
5312 // For LE / GE, if high part is known false, ignore the low part.
5313 // For LT / GT, if high part is known true, ignore the low part.
5317 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5318 LHSHi, RHSHi, ISD::SETEQ, false,
5319 DagCombineInfo, dl);
5320 if (!Result.getNode())
5321 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5322 LHSHi, RHSHi, ISD::SETEQ);
5323 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5324 Result, Tmp1, Tmp2));
5335 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5336 /// condition code CC on the current target. This routine assumes LHS and rHS
5337 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5338 /// illegal condition code into AND / OR of multiple SETCC values.
5339 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5340 SDValue &LHS, SDValue &RHS,
5343 MVT OpVT = LHS.getValueType();
5344 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5345 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5346 default: assert(0 && "Unknown condition code action!");
5347 case TargetLowering::Legal:
5350 case TargetLowering::Expand: {
5351 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5354 default: assert(0 && "Don't know how to expand this condition!"); abort();
5355 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5356 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5357 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5358 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5359 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5360 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5361 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5362 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5363 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5364 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5365 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5366 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5367 // FIXME: Implement more expansions.
5370 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5371 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5372 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5380 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5381 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5382 /// a load from the stack slot to DestVT, extending it if needed.
5383 /// The resultant code need not be legal.
5384 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5388 // Create the stack frame object.
5390 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
5392 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5394 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5395 int SPFI = StackPtrFI->getIndex();
5396 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5398 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5399 unsigned SlotSize = SlotVT.getSizeInBits();
5400 unsigned DestSize = DestVT.getSizeInBits();
5401 unsigned DestAlign =
5402 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
5404 // Emit a store to the stack slot. Use a truncstore if the input value is
5405 // later than DestVT.
5408 if (SrcSize > SlotSize)
5409 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5410 SV, 0, SlotVT, false, SrcAlign);
5412 assert(SrcSize == SlotSize && "Invalid store");
5413 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5414 SV, 0, false, SrcAlign);
5417 // Result is a load from the stack slot.
5418 if (SlotSize == DestSize)
5419 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5421 assert(SlotSize < DestSize && "Unknown extension!");
5422 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5426 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5427 DebugLoc dl = Node->getDebugLoc();
5428 // Create a vector sized/aligned stack slot, store the value to element #0,
5429 // then load the whole vector back out.
5430 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5432 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5433 int SPFI = StackPtrFI->getIndex();
5435 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5437 PseudoSourceValue::getFixedStack(SPFI), 0,
5438 Node->getValueType(0).getVectorElementType());
5439 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5440 PseudoSourceValue::getFixedStack(SPFI), 0);
5444 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5445 /// support the operation, but do support the resultant vector type.
5446 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5447 unsigned NumElems = Node->getNumOperands();
5448 SDValue SplatValue = Node->getOperand(0);
5449 DebugLoc dl = Node->getDebugLoc();
5450 MVT VT = Node->getValueType(0);
5451 MVT OpVT = SplatValue.getValueType();
5452 MVT EltVT = VT.getVectorElementType();
5454 // If the only non-undef value is the low element, turn this into a
5455 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5456 bool isOnlyLowElement = true;
5458 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5459 // and use a bitmask instead of a list of elements.
5460 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.
5461 std::map<SDValue, std::vector<unsigned> > Values;
5462 Values[SplatValue].push_back(0);
5463 bool isConstant = true;
5464 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5465 SplatValue.getOpcode() != ISD::UNDEF)
5468 for (unsigned i = 1; i < NumElems; ++i) {
5469 SDValue V = Node->getOperand(i);
5470 Values[V].push_back(i);
5471 if (V.getOpcode() != ISD::UNDEF)
5472 isOnlyLowElement = false;
5473 if (SplatValue != V)
5474 SplatValue = SDValue(0, 0);
5476 // If this isn't a constant element or an undef, we can't use a constant
5478 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5479 V.getOpcode() != ISD::UNDEF)
5483 if (isOnlyLowElement) {
5484 // If the low element is an undef too, then this whole things is an undef.
5485 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5486 return DAG.getUNDEF(VT);
5487 // Otherwise, turn this into a scalar_to_vector node.
5488 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
5491 // If all elements are constants, create a load from the constant pool.
5493 std::vector<Constant*> CV;
5494 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5495 if (ConstantFPSDNode *V =
5496 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5497 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5498 } else if (ConstantSDNode *V =
5499 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5500 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5502 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5503 const Type *OpNTy = OpVT.getTypeForMVT();
5504 CV.push_back(UndefValue::get(OpNTy));
5507 Constant *CP = ConstantVector::get(CV);
5508 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5509 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5510 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5511 PseudoSourceValue::getConstantPool(), 0,
5515 if (SplatValue.getNode()) { // Splat of one value?
5516 // Build the shuffle constant vector: <0, 0, 0, 0>
5517 SmallVector<int, 8> ZeroVec(NumElems, 0);
5519 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5520 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) {
5521 // Get the splatted value into the low element of a vector register.
5523 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue);
5525 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5526 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT),
5531 // If there are only two unique elements, we may be able to turn this into a
5533 if (Values.size() == 2) {
5534 // Get the two values in deterministic order.
5535 SDValue Val1 = Node->getOperand(1);
5537 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5538 if (MI->first != Val1)
5541 Val2 = (++MI)->first;
5543 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our
5544 // vector shuffle has the undef vector on the RHS.
5545 if (Val1.getOpcode() == ISD::UNDEF)
5546 std::swap(Val1, Val2);
5548 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5549 SmallVector<int, 8> ShuffleMask(NumElems, -1);
5551 // Set elements of the shuffle mask for Val1.
5552 std::vector<unsigned> &Val1Elts = Values[Val1];
5553 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5554 ShuffleMask[Val1Elts[i]] = 0;
5556 // Set elements of the shuffle mask for Val2.
5557 std::vector<unsigned> &Val2Elts = Values[Val2];
5558 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5559 if (Val2.getOpcode() != ISD::UNDEF)
5560 ShuffleMask[Val2Elts[i]] = NumElems;
5562 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5563 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) &&
5564 TLI.isShuffleMaskLegal(ShuffleMask, VT)) {
5565 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1);
5566 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2);
5567 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]);
5571 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5572 // aligned object on the stack, store each element into it, then load
5573 // the result as a vector.
5574 // Create the stack frame object.
5575 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5576 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5577 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5579 // Emit a store of each element to the stack slot.
5580 SmallVector<SDValue, 8> Stores;
5581 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
5582 // Store (in the right endianness) the elements to memory.
5583 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5584 // Ignore undef elements.
5585 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5587 unsigned Offset = TypeByteSize*i;
5589 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5590 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5592 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5597 if (!Stores.empty()) // Not all undef elements?
5598 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5599 &Stores[0], Stores.size());
5601 StoreChain = DAG.getEntryNode();
5603 // Result is a load from the stack slot.
5604 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5607 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5608 SDValue Op, SDValue Amt,
5609 SDValue &Lo, SDValue &Hi,
5611 // Expand the subcomponents.
5613 ExpandOp(Op, LHSL, LHSH);
5615 SDValue Ops[] = { LHSL, LHSH, Amt };
5616 MVT VT = LHSL.getValueType();
5617 Lo = DAG.getNode(NodeOp, dl, DAG.getVTList(VT, VT), Ops, 3);
5618 Hi = Lo.getValue(1);
5622 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5623 /// smaller elements. If we can't find a way that is more efficient than a
5624 /// libcall on this target, return false. Otherwise, return true with the
5625 /// low-parts expanded into Lo and Hi.
5626 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
5627 SDValue &Lo, SDValue &Hi,
5629 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5630 "This is not a shift!");
5632 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5633 SDValue ShAmt = LegalizeOp(Amt);
5634 MVT ShTy = ShAmt.getValueType();
5635 unsigned ShBits = ShTy.getSizeInBits();
5636 unsigned VTBits = Op.getValueType().getSizeInBits();
5637 unsigned NVTBits = NVT.getSizeInBits();
5639 // Handle the case when Amt is an immediate.
5640 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5641 unsigned Cst = CN->getZExtValue();
5642 // Expand the incoming operand to be shifted, so that we have its parts
5644 ExpandOp(Op, InL, InH);
5648 Lo = DAG.getConstant(0, NVT);
5649 Hi = DAG.getConstant(0, NVT);
5650 } else if (Cst > NVTBits) {
5651 Lo = DAG.getConstant(0, NVT);
5652 Hi = DAG.getNode(ISD::SHL, dl,
5653 NVT, InL, DAG.getConstant(Cst-NVTBits, ShTy));
5654 } else if (Cst == NVTBits) {
5655 Lo = DAG.getConstant(0, NVT);
5658 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5659 Hi = DAG.getNode(ISD::OR, dl, NVT,
5660 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5661 DAG.getNode(ISD::SRL, dl, NVT, InL,
5662 DAG.getConstant(NVTBits-Cst, ShTy)));
5667 Lo = DAG.getConstant(0, NVT);
5668 Hi = DAG.getConstant(0, NVT);
5669 } else if (Cst > NVTBits) {
5670 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5671 InH, DAG.getConstant(Cst-NVTBits, ShTy));
5672 Hi = DAG.getConstant(0, NVT);
5673 } else if (Cst == NVTBits) {
5675 Hi = DAG.getConstant(0, NVT);
5677 Lo = DAG.getNode(ISD::OR, dl, NVT,
5678 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5679 DAG.getNode(ISD::SHL, dl, NVT, InH,
5680 DAG.getConstant(NVTBits-Cst, ShTy)));
5681 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5686 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5687 DAG.getConstant(NVTBits-1, ShTy));
5688 } else if (Cst > NVTBits) {
5689 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5690 DAG.getConstant(Cst-NVTBits, ShTy));
5691 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5692 DAG.getConstant(NVTBits-1, ShTy));
5693 } else if (Cst == NVTBits) {
5695 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5696 DAG.getConstant(NVTBits-1, ShTy));
5698 Lo = DAG.getNode(ISD::OR, dl, NVT,
5699 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5700 DAG.getNode(ISD::SHL, dl,
5701 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5702 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5708 // Okay, the shift amount isn't constant. However, if we can tell that it is
5709 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5710 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5711 APInt KnownZero, KnownOne;
5712 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5714 // If we know that if any of the high bits of the shift amount are one, then
5715 // we can do this as a couple of simple shifts.
5716 if (KnownOne.intersects(Mask)) {
5717 // Mask out the high bit, which we know is set.
5718 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5719 DAG.getConstant(~Mask, Amt.getValueType()));
5721 // Expand the incoming operand to be shifted, so that we have its parts
5723 ExpandOp(Op, InL, InH);
5726 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5727 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5730 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5731 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5734 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5735 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5736 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5741 // If we know that the high bits of the shift amount are all zero, then we can
5742 // do this as a couple of simple shifts.
5743 if ((KnownZero & Mask) == Mask) {
5745 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5746 DAG.getConstant(NVTBits, Amt.getValueType()),
5749 // Expand the incoming operand to be shifted, so that we have its parts
5751 ExpandOp(Op, InL, InH);
5754 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5755 Hi = DAG.getNode(ISD::OR, dl, NVT,
5756 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5757 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5760 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5761 Lo = DAG.getNode(ISD::OR, dl, NVT,
5762 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5763 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5766 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5767 Lo = DAG.getNode(ISD::OR, dl, NVT,
5768 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5769 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5778 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5779 // does not fit into a register, return the lo part and set the hi part to the
5780 // by-reg argument. If it does fit into a single register, return the result
5781 // and leave the Hi part unset.
5782 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5783 bool isSigned, SDValue &Hi) {
5784 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5785 // The input chain to this libcall is the entry node of the function.
5786 // Legalizing the call will automatically add the previous call to the
5788 SDValue InChain = DAG.getEntryNode();
5790 TargetLowering::ArgListTy Args;
5791 TargetLowering::ArgListEntry Entry;
5792 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5793 MVT ArgVT = Node->getOperand(i).getValueType();
5794 const Type *ArgTy = ArgVT.getTypeForMVT();
5795 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5796 Entry.isSExt = isSigned;
5797 Entry.isZExt = !isSigned;
5798 Args.push_back(Entry);
5800 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5801 TLI.getPointerTy());
5803 // Splice the libcall in wherever FindInputOutputChains tells us to.
5804 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5805 std::pair<SDValue, SDValue> CallInfo =
5806 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5807 CallingConv::C, false, Callee, Args, DAG,
5808 Node->getDebugLoc());
5810 // Legalize the call sequence, starting with the chain. This will advance
5811 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5812 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5813 LegalizeOp(CallInfo.second);
5815 switch (getTypeAction(CallInfo.first.getValueType())) {
5816 default: assert(0 && "Unknown thing");
5818 Result = CallInfo.first;
5821 ExpandOp(CallInfo.first, Result, Hi);
5827 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5829 SDValue SelectionDAGLegalize::
5830 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5832 bool isCustom = false;
5834 switch (getTypeAction(Op.getValueType())) {
5836 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5837 Op.getValueType())) {
5838 default: assert(0 && "Unknown operation action!");
5839 case TargetLowering::Custom:
5842 case TargetLowering::Legal:
5843 Tmp1 = LegalizeOp(Op);
5844 if (Result.getNode())
5845 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5847 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5850 Tmp1 = TLI.LowerOperation(Result, DAG);
5851 if (Tmp1.getNode()) Result = Tmp1;
5854 case TargetLowering::Expand:
5855 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5857 case TargetLowering::Promote:
5858 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5863 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5866 Tmp1 = PromoteOp(Op);
5868 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5869 Tmp1, DAG.getValueType(Op.getValueType()));
5871 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, Op.getValueType());
5873 if (Result.getNode())
5874 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5876 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5878 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5884 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5886 SDValue SelectionDAGLegalize::
5887 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5888 MVT SourceVT = Source.getValueType();
5889 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5891 // Expand unsupported int-to-fp vector casts by unrolling them.
5892 if (DestTy.isVector()) {
5894 return LegalizeOp(UnrollVectorOp(Source));
5895 MVT DestEltTy = DestTy.getVectorElementType();
5896 if (DestTy.getVectorNumElements() == 1) {
5897 SDValue Scalar = ScalarizeVectorOp(Source);
5898 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5899 DestEltTy, Scalar, dl);
5900 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result);
5903 SplitVectorOp(Source, Lo, Hi);
5904 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5905 DestTy.getVectorNumElements() / 2);
5906 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5908 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5910 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5914 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5915 if (!isSigned && SourceVT != MVT::i32) {
5916 // The integer value loaded will be incorrectly if the 'sign bit' of the
5917 // incoming integer is set. To handle this, we dynamically test to see if
5918 // it is set, and, if so, add a fudge factor.
5922 ExpandOp(Source, Lo, Hi);
5923 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5925 // The comparison for the sign bit will use the entire operand.
5929 // Check to see if the target has a custom way to lower this. If so, use
5930 // it. (Note we've already expanded the operand in this case.)
5931 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5932 default: assert(0 && "This action not implemented for this operation!");
5933 case TargetLowering::Legal:
5934 case TargetLowering::Expand:
5935 break; // This case is handled below.
5936 case TargetLowering::Custom: {
5937 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
5940 return LegalizeOp(NV);
5941 break; // The target decided this was legal after all
5945 // If this is unsigned, and not supported, first perform the conversion to
5946 // signed, then adjust the result if the sign bit is set.
5947 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
5949 SDValue SignSet = DAG.getSetCC(dl,
5950 TLI.getSetCCResultType(Hi.getValueType()),
5951 Hi, DAG.getConstant(0, Hi.getValueType()),
5953 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5954 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
5955 SignSet, Four, Zero);
5956 uint64_t FF = 0x5f800000ULL;
5957 if (TLI.isLittleEndian()) FF <<= 32;
5958 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5960 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5961 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5962 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
5963 Alignment = std::min(Alignment, 4u);
5965 if (DestTy == MVT::f32)
5966 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
5967 PseudoSourceValue::getConstantPool(), 0,
5969 else if (DestTy.bitsGT(MVT::f32))
5970 // FIXME: Avoid the extend by construction the right constantpool?
5971 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
5973 PseudoSourceValue::getConstantPool(), 0,
5974 MVT::f32, false, Alignment);
5976 assert(0 && "Unexpected conversion");
5978 MVT SCVT = SignedConv.getValueType();
5979 if (SCVT != DestTy) {
5980 // Destination type needs to be expanded as well. The FADD now we are
5981 // constructing will be expanded into a libcall.
5982 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
5983 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
5984 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
5985 SignedConv, SignedConv.getValue(1));
5987 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
5989 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
5992 // Check to see if the target has a custom way to lower this. If so, use it.
5993 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5994 default: assert(0 && "This action not implemented for this operation!");
5995 case TargetLowering::Legal:
5996 case TargetLowering::Expand:
5997 break; // This case is handled below.
5998 case TargetLowering::Custom: {
5999 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6002 return LegalizeOp(NV);
6003 break; // The target decided this was legal after all
6007 // Expand the source, then glue it back together for the call. We must expand
6008 // the source in case it is shared (this pass of legalize must traverse it).
6010 SDValue SrcLo, SrcHi;
6011 ExpandOp(Source, SrcLo, SrcHi);
6012 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6015 RTLIB::Libcall LC = isSigned ?
6016 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6017 RTLIB::getUINTTOFP(SourceVT, DestTy);
6018 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6020 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6022 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6023 if (Result.getValueType() != DestTy && HiPart.getNode())
6024 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6028 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6029 /// INT_TO_FP operation of the specified operand when the target requests that
6030 /// we expand it. At this point, we know that the result and operand types are
6031 /// legal for the target.
6032 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6036 if (Op0.getValueType() == MVT::i32) {
6037 // simple 32-bit [signed|unsigned] integer to float/double expansion
6039 // Get the stack frame index of a 8 byte buffer.
6040 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6042 // word offset constant for Hi/Lo address computation
6043 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6044 // set up Hi and Lo (into buffer) address based on endian
6045 SDValue Hi = StackSlot;
6046 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6047 TLI.getPointerTy(), StackSlot, WordOff);
6048 if (TLI.isLittleEndian())
6051 // if signed map to unsigned space
6054 // constant used to invert sign bit (signed to unsigned mapping)
6055 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6056 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6060 // store the lo of the constructed double - based on integer input
6061 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6062 Op0Mapped, Lo, NULL, 0);
6063 // initial hi portion of constructed double
6064 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6065 // store the hi of the constructed double - biased exponent
6066 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6067 // load the constructed double
6068 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6069 // FP constant to bias correct the final result
6070 SDValue Bias = DAG.getConstantFP(isSigned ?
6071 BitsToDouble(0x4330000080000000ULL) :
6072 BitsToDouble(0x4330000000000000ULL),
6074 // subtract the bias
6075 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6078 // handle final rounding
6079 if (DestVT == MVT::f64) {
6082 } else if (DestVT.bitsLT(MVT::f64)) {
6083 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6084 DAG.getIntPtrConstant(0));
6085 } else if (DestVT.bitsGT(MVT::f64)) {
6086 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6090 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6091 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6093 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6094 Op0, DAG.getConstant(0, Op0.getValueType()),
6096 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6097 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6098 SignSet, Four, Zero);
6100 // If the sign bit of the integer is set, the large number will be treated
6101 // as a negative number. To counteract this, the dynamic code adds an
6102 // offset depending on the data type.
6104 switch (Op0.getValueType().getSimpleVT()) {
6105 default: assert(0 && "Unsupported integer type!");
6106 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6107 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6108 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6109 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6111 if (TLI.isLittleEndian()) FF <<= 32;
6112 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6114 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6115 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6116 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6117 Alignment = std::min(Alignment, 4u);
6119 if (DestVT == MVT::f32)
6120 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6121 PseudoSourceValue::getConstantPool(), 0,
6125 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6126 DAG.getEntryNode(), CPIdx,
6127 PseudoSourceValue::getConstantPool(), 0,
6128 MVT::f32, false, Alignment));
6131 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6134 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6135 /// *INT_TO_FP operation of the specified operand when the target requests that
6136 /// we promote it. At this point, we know that the result and operand types are
6137 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6138 /// operation that takes a larger input.
6139 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6143 // First step, figure out the appropriate *INT_TO_FP operation to use.
6144 MVT NewInTy = LegalOp.getValueType();
6146 unsigned OpToUse = 0;
6148 // Scan for the appropriate larger type to use.
6150 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6151 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6153 // If the target supports SINT_TO_FP of this type, use it.
6154 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6156 case TargetLowering::Legal:
6157 if (!TLI.isTypeLegal(NewInTy))
6158 break; // Can't use this datatype.
6160 case TargetLowering::Custom:
6161 OpToUse = ISD::SINT_TO_FP;
6165 if (isSigned) continue;
6167 // If the target supports UINT_TO_FP of this type, use it.
6168 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6170 case TargetLowering::Legal:
6171 if (!TLI.isTypeLegal(NewInTy))
6172 break; // Can't use this datatype.
6174 case TargetLowering::Custom:
6175 OpToUse = ISD::UINT_TO_FP;
6180 // Otherwise, try a larger type.
6183 // Okay, we found the operation and type to use. Zero extend our input to the
6184 // desired type then run the operation on it.
6185 return DAG.getNode(OpToUse, dl, DestVT,
6186 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6187 dl, NewInTy, LegalOp));
6190 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6191 /// FP_TO_*INT operation of the specified operand when the target requests that
6192 /// we promote it. At this point, we know that the result and operand types are
6193 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6194 /// operation that returns a larger result.
6195 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6199 // First step, figure out the appropriate FP_TO*INT operation to use.
6200 MVT NewOutTy = DestVT;
6202 unsigned OpToUse = 0;
6204 // Scan for the appropriate larger type to use.
6206 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6207 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6209 // If the target supports FP_TO_SINT returning this type, use it.
6210 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6212 case TargetLowering::Legal:
6213 if (!TLI.isTypeLegal(NewOutTy))
6214 break; // Can't use this datatype.
6216 case TargetLowering::Custom:
6217 OpToUse = ISD::FP_TO_SINT;
6222 // If the target supports FP_TO_UINT of this type, use it.
6223 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6225 case TargetLowering::Legal:
6226 if (!TLI.isTypeLegal(NewOutTy))
6227 break; // Can't use this datatype.
6229 case TargetLowering::Custom:
6230 OpToUse = ISD::FP_TO_UINT;
6235 // Otherwise, try a larger type.
6239 // Okay, we found the operation and type to use.
6240 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6242 // If the operation produces an invalid type, it must be custom lowered. Use
6243 // the target lowering hooks to expand it. Just keep the low part of the
6244 // expanded operation, we know that we're truncating anyway.
6245 if (getTypeAction(NewOutTy) == Expand) {
6246 SmallVector<SDValue, 2> Results;
6247 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6248 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6249 Operation = Results[0];
6252 // Truncate the result of the extended FP_TO_*INT operation to the desired
6254 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6257 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6259 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6260 MVT VT = Op.getValueType();
6261 MVT SHVT = TLI.getShiftAmountTy();
6262 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6263 switch (VT.getSimpleVT()) {
6264 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6266 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6267 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6268 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6270 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6271 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6272 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6273 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6274 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6275 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6276 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6277 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6278 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6280 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6281 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6282 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6283 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6284 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6285 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6286 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6287 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6288 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6289 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6290 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6291 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6292 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6293 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6294 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6295 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6296 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6297 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6298 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6299 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6300 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6304 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6306 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6309 default: assert(0 && "Cannot expand this yet!");
6311 static const uint64_t mask[6] = {
6312 0x5555555555555555ULL, 0x3333333333333333ULL,
6313 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6314 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6316 MVT VT = Op.getValueType();
6317 MVT ShVT = TLI.getShiftAmountTy();
6318 unsigned len = VT.getSizeInBits();
6319 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6320 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6321 unsigned EltSize = VT.isVector() ?
6322 VT.getVectorElementType().getSizeInBits() : len;
6323 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6324 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6325 Op = DAG.getNode(ISD::ADD, dl, VT,
6326 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
6327 DAG.getNode(ISD::AND, dl, VT,
6328 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6334 // for now, we do this:
6335 // x = x | (x >> 1);
6336 // x = x | (x >> 2);
6338 // x = x | (x >>16);
6339 // x = x | (x >>32); // for 64-bit input
6340 // return popcount(~x);
6342 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6343 MVT VT = Op.getValueType();
6344 MVT ShVT = TLI.getShiftAmountTy();
6345 unsigned len = VT.getSizeInBits();
6346 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6347 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6348 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6349 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
6351 Op = DAG.getNOT(dl, Op, VT);
6352 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6355 // for now, we use: { return popcount(~x & (x - 1)); }
6356 // unless the target has ctlz but not ctpop, in which case we use:
6357 // { return 32 - nlz(~x & (x-1)); }
6358 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6359 MVT VT = Op.getValueType();
6360 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6361 DAG.getNOT(dl, Op, VT),
6362 DAG.getNode(ISD::SUB, dl, VT, Op,
6363 DAG.getConstant(1, VT)));
6364 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6365 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6366 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6367 return DAG.getNode(ISD::SUB, dl, VT,
6368 DAG.getConstant(VT.getSizeInBits(), VT),
6369 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6370 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6375 /// ExpandOp - Expand the specified SDValue into its two component pieces
6376 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6377 /// LegalizedNodes map is filled in for any results that are not expanded, the
6378 /// ExpandedNodes map is filled in for any results that are expanded, and the
6379 /// Lo/Hi values are returned.
6380 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6381 MVT VT = Op.getValueType();
6382 MVT NVT = TLI.getTypeToTransformTo(VT);
6383 SDNode *Node = Op.getNode();
6384 DebugLoc dl = Node->getDebugLoc();
6385 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6386 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6387 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6389 // See if we already expanded it.
6390 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6391 = ExpandedNodes.find(Op);
6392 if (I != ExpandedNodes.end()) {
6393 Lo = I->second.first;
6394 Hi = I->second.second;
6398 switch (Node->getOpcode()) {
6399 case ISD::CopyFromReg:
6400 assert(0 && "CopyFromReg must be legal!");
6401 case ISD::FP_ROUND_INREG:
6402 if (VT == MVT::ppcf128 &&
6403 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6404 TargetLowering::Custom) {
6405 SDValue SrcLo, SrcHi, Src;
6406 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6407 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6409 TLI.LowerOperation(DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src,
6410 Op.getOperand(1)), DAG);
6411 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6412 Lo = Result.getNode()->getOperand(0);
6413 Hi = Result.getNode()->getOperand(1);
6419 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6421 assert(0 && "Do not know how to expand this operator!");
6423 case ISD::EXTRACT_ELEMENT:
6424 ExpandOp(Node->getOperand(0), Lo, Hi);
6425 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6426 return ExpandOp(Hi, Lo, Hi);
6427 return ExpandOp(Lo, Lo, Hi);
6428 case ISD::EXTRACT_VECTOR_ELT:
6429 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6430 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6431 return ExpandOp(Lo, Lo, Hi);
6433 Lo = DAG.getUNDEF(NVT);
6434 Hi = DAG.getUNDEF(NVT);
6436 case ISD::Constant: {
6437 unsigned NVTBits = NVT.getSizeInBits();
6438 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6439 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6440 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6443 case ISD::ConstantFP: {
6444 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6445 if (CFP->getValueType(0) == MVT::ppcf128) {
6446 APInt api = CFP->getValueAPF().bitcastToAPInt();
6447 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6449 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6453 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6454 if (getTypeAction(Lo.getValueType()) == Expand)
6455 ExpandOp(Lo, Lo, Hi);
6458 case ISD::BUILD_PAIR:
6459 // Return the operands.
6460 Lo = Node->getOperand(0);
6461 Hi = Node->getOperand(1);
6464 case ISD::MERGE_VALUES:
6465 if (Node->getNumValues() == 1) {
6466 ExpandOp(Op.getOperand(0), Lo, Hi);
6469 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6470 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6471 Op.getValue(1).getValueType() == MVT::Other &&
6472 "unhandled MERGE_VALUES");
6473 ExpandOp(Op.getOperand(0), Lo, Hi);
6474 // Remember that we legalized the chain.
6475 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6478 case ISD::SIGN_EXTEND_INREG:
6479 ExpandOp(Node->getOperand(0), Lo, Hi);
6480 // sext_inreg the low part if needed.
6481 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6483 // The high part gets the sign extension from the lo-part. This handles
6484 // things like sextinreg V:i64 from i8.
6485 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6486 DAG.getConstant(NVT.getSizeInBits()-1,
6487 TLI.getShiftAmountTy()));
6491 ExpandOp(Node->getOperand(0), Lo, Hi);
6492 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6493 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6499 ExpandOp(Node->getOperand(0), Lo, Hi);
6500 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6501 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6502 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6503 Hi = DAG.getConstant(0, NVT);
6507 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6508 ExpandOp(Node->getOperand(0), Lo, Hi);
6509 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6510 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6511 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6513 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6514 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6516 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6517 Hi = DAG.getConstant(0, NVT);
6522 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6523 ExpandOp(Node->getOperand(0), Lo, Hi);
6524 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6525 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6526 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6528 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6529 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6531 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6532 Hi = DAG.getConstant(0, NVT);
6537 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6538 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6539 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
6540 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
6542 // Remember that we legalized the chain.
6543 Hi = LegalizeOp(Hi);
6544 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6545 if (TLI.isBigEndian())
6551 LoadSDNode *LD = cast<LoadSDNode>(Node);
6552 SDValue Ch = LD->getChain(); // Legalize the chain.
6553 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6554 ISD::LoadExtType ExtType = LD->getExtensionType();
6555 const Value *SV = LD->getSrcValue();
6556 int SVOffset = LD->getSrcValueOffset();
6557 unsigned Alignment = LD->getAlignment();
6558 bool isVolatile = LD->isVolatile();
6560 if (ExtType == ISD::NON_EXTLOAD) {
6561 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6562 isVolatile, Alignment);
6563 if (VT == MVT::f32 || VT == MVT::f64) {
6564 // f32->i32 or f64->i64 one to one expansion.
6565 // Remember that we legalized the chain.
6566 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6567 // Recursively expand the new load.
6568 if (getTypeAction(NVT) == Expand)
6569 ExpandOp(Lo, Lo, Hi);
6573 // Increment the pointer to the other half.
6574 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6575 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6576 DAG.getIntPtrConstant(IncrementSize));
6577 SVOffset += IncrementSize;
6578 Alignment = MinAlign(Alignment, IncrementSize);
6579 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6580 isVolatile, Alignment);
6582 // Build a factor node to remember that this load is independent of the
6584 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6587 // Remember that we legalized the chain.
6588 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6589 if (TLI.isBigEndian())
6592 MVT EVT = LD->getMemoryVT();
6594 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6595 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6596 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6597 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6598 SVOffset, isVolatile, Alignment);
6599 // Remember that we legalized the chain.
6600 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6601 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6606 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6607 SVOffset, isVolatile, Alignment);
6609 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6610 SVOffset, EVT, isVolatile,
6613 // Remember that we legalized the chain.
6614 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6616 if (ExtType == ISD::SEXTLOAD) {
6617 // The high part is obtained by SRA'ing all but one of the bits of the
6619 unsigned LoSize = Lo.getValueType().getSizeInBits();
6620 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6621 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6622 } else if (ExtType == ISD::ZEXTLOAD) {
6623 // The high part is just a zero.
6624 Hi = DAG.getConstant(0, NVT);
6625 } else /* if (ExtType == ISD::EXTLOAD) */ {
6626 // The high part is undefined.
6627 Hi = DAG.getUNDEF(NVT);
6634 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6635 SDValue LL, LH, RL, RH;
6636 ExpandOp(Node->getOperand(0), LL, LH);
6637 ExpandOp(Node->getOperand(1), RL, RH);
6638 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6639 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6643 SDValue LL, LH, RL, RH;
6644 ExpandOp(Node->getOperand(1), LL, LH);
6645 ExpandOp(Node->getOperand(2), RL, RH);
6646 if (getTypeAction(NVT) == Expand)
6647 NVT = TLI.getTypeToExpandTo(NVT);
6648 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6650 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6653 case ISD::SELECT_CC: {
6654 SDValue TL, TH, FL, FH;
6655 ExpandOp(Node->getOperand(2), TL, TH);
6656 ExpandOp(Node->getOperand(3), FL, FH);
6657 if (getTypeAction(NVT) == Expand)
6658 NVT = TLI.getTypeToExpandTo(NVT);
6659 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6660 Node->getOperand(1), TL, FL, Node->getOperand(4));
6662 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6663 Node->getOperand(1), TH, FH, Node->getOperand(4));
6666 case ISD::ANY_EXTEND:
6667 // The low part is any extension of the input (which degenerates to a copy).
6668 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6669 // The high part is undefined.
6670 Hi = DAG.getUNDEF(NVT);
6672 case ISD::SIGN_EXTEND: {
6673 // The low part is just a sign extension of the input (which degenerates to
6675 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6677 // The high part is obtained by SRA'ing all but one of the bits of the lo
6679 unsigned LoSize = Lo.getValueType().getSizeInBits();
6680 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6681 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6684 case ISD::ZERO_EXTEND:
6685 // The low part is just a zero extension of the input (which degenerates to
6687 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6689 // The high part is just a zero.
6690 Hi = DAG.getConstant(0, NVT);
6693 case ISD::TRUNCATE: {
6694 // The input value must be larger than this value. Expand *it*.
6696 ExpandOp(Node->getOperand(0), NewLo, Hi);
6698 // The low part is now either the right size, or it is closer. If not the
6699 // right size, make an illegal truncate so we recursively expand it.
6700 if (NewLo.getValueType() != Node->getValueType(0))
6701 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6702 ExpandOp(NewLo, Lo, Hi);
6706 case ISD::BIT_CONVERT: {
6708 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6709 // If the target wants to, allow it to lower this itself.
6710 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6711 case Expand: assert(0 && "cannot expand FP!");
6712 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6713 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6715 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6718 // f32 / f64 must be expanded to i32 / i64.
6719 if (VT == MVT::f32 || VT == MVT::f64) {
6720 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6721 if (getTypeAction(NVT) == Expand)
6722 ExpandOp(Lo, Lo, Hi);
6726 // If source operand will be expanded to the same type as VT, i.e.
6727 // i64 <- f64, i32 <- f32, expand the source operand instead.
6728 MVT VT0 = Node->getOperand(0).getValueType();
6729 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6730 ExpandOp(Node->getOperand(0), Lo, Hi);
6734 // Turn this into a load/store pair by default.
6735 if (Tmp.getNode() == 0)
6736 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6738 ExpandOp(Tmp, Lo, Hi);
6742 case ISD::READCYCLECOUNTER: {
6743 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6744 TargetLowering::Custom &&
6745 "Must custom expand ReadCycleCounter");
6746 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6747 assert(Tmp.getNode() && "Node must be custom expanded!");
6748 ExpandOp(Tmp.getValue(0), Lo, Hi);
6749 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6750 LegalizeOp(Tmp.getValue(1)));
6754 case ISD::ATOMIC_CMP_SWAP: {
6755 // This operation does not need a loop.
6756 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6757 assert(Tmp.getNode() && "Node must be custom expanded!");
6758 ExpandOp(Tmp.getValue(0), Lo, Hi);
6759 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6760 LegalizeOp(Tmp.getValue(1)));
6764 case ISD::ATOMIC_LOAD_ADD:
6765 case ISD::ATOMIC_LOAD_SUB:
6766 case ISD::ATOMIC_LOAD_AND:
6767 case ISD::ATOMIC_LOAD_OR:
6768 case ISD::ATOMIC_LOAD_XOR:
6769 case ISD::ATOMIC_LOAD_NAND:
6770 case ISD::ATOMIC_SWAP: {
6771 // These operations require a loop to be generated. We can't do that yet,
6772 // so substitute a target-dependent pseudo and expand that later.
6773 SDValue In2Lo, In2Hi, In2;
6774 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6775 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6776 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6778 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6779 Op.getOperand(0), Op.getOperand(1), In2,
6780 Anode->getSrcValue(), Anode->getAlignment());
6781 SDValue Result = TLI.LowerOperation(Replace, DAG);
6782 ExpandOp(Result.getValue(0), Lo, Hi);
6783 // Remember that we legalized the chain.
6784 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Result.getValue(1)));
6788 // These operators cannot be expanded directly, emit them as calls to
6789 // library functions.
6790 case ISD::FP_TO_SINT: {
6791 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6793 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6794 case Expand: assert(0 && "cannot expand FP!");
6795 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6796 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6799 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6801 // Now that the custom expander is done, expand the result, which is still
6804 ExpandOp(Op, Lo, Hi);
6809 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6811 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6812 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6816 case ISD::FP_TO_UINT: {
6817 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6819 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6820 case Expand: assert(0 && "cannot expand FP!");
6821 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6822 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6825 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6827 // Now that the custom expander is done, expand the result.
6829 ExpandOp(Op, Lo, Hi);
6834 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6836 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6837 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6842 // If the target wants custom lowering, do so.
6843 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6844 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6845 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6846 Op = TLI.LowerOperation(Op, DAG);
6848 // Now that the custom expander is done, expand the result, which is
6850 ExpandOp(Op, Lo, Hi);
6855 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6856 // this X << 1 as X+X.
6857 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6858 if (ShAmt->getAPIntValue() == 1 &&
6859 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6860 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6861 SDValue LoOps[2], HiOps[3];
6862 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6863 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6864 LoOps[1] = LoOps[0];
6865 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6867 HiOps[1] = HiOps[0];
6868 HiOps[2] = Lo.getValue(1);
6869 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6874 // If we can emit an efficient shift operation, do so now.
6875 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6878 // If this target supports SHL_PARTS, use it.
6879 TargetLowering::LegalizeAction Action =
6880 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6881 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6882 Action == TargetLowering::Custom) {
6883 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6884 ShiftAmt, Lo, Hi, dl);
6888 // Otherwise, emit a libcall.
6889 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6894 // If the target wants custom lowering, do so.
6895 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6896 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6897 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
6898 Op = TLI.LowerOperation(Op, DAG);
6900 // Now that the custom expander is done, expand the result, which is
6902 ExpandOp(Op, Lo, Hi);
6907 // If we can emit an efficient shift operation, do so now.
6908 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6911 // If this target supports SRA_PARTS, use it.
6912 TargetLowering::LegalizeAction Action =
6913 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6914 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6915 Action == TargetLowering::Custom) {
6916 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6917 ShiftAmt, Lo, Hi, dl);
6921 // Otherwise, emit a libcall.
6922 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6927 // If the target wants custom lowering, do so.
6928 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6929 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6930 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6931 Op = TLI.LowerOperation(Op, DAG);
6933 // Now that the custom expander is done, expand the result, which is
6935 ExpandOp(Op, Lo, Hi);
6940 // If we can emit an efficient shift operation, do so now.
6941 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6944 // If this target supports SRL_PARTS, use it.
6945 TargetLowering::LegalizeAction Action =
6946 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6947 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6948 Action == TargetLowering::Custom) {
6949 ExpandShiftParts(ISD::SRL_PARTS,
6950 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
6954 // Otherwise, emit a libcall.
6955 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6961 // If the target wants to custom expand this, let them.
6962 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6963 TargetLowering::Custom) {
6964 SDValue Result = TLI.LowerOperation(Op, DAG);
6965 if (Result.getNode()) {
6966 ExpandOp(Result, Lo, Hi);
6970 // Expand the subcomponents.
6971 SDValue LHSL, LHSH, RHSL, RHSH;
6972 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6973 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6974 SDValue LoOps[2], HiOps[3];
6980 //cascaded check to see if any smaller size has a a carry flag.
6981 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6982 bool hasCarry = false;
6983 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6984 MVT AVT = MVT::getIntegerVT(BitSize);
6985 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
6992 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6993 if (Node->getOpcode() == ISD::ADD) {
6994 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6995 HiOps[2] = Lo.getValue(1);
6996 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6998 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
6999 HiOps[2] = Lo.getValue(1);
7000 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7004 if (Node->getOpcode() == ISD::ADD) {
7005 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7006 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7007 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7008 Lo, LoOps[0], ISD::SETULT);
7009 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7010 DAG.getConstant(1, NVT),
7011 DAG.getConstant(0, NVT));
7012 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7013 Lo, LoOps[1], ISD::SETULT);
7014 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7015 DAG.getConstant(1, NVT),
7017 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7019 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7020 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7021 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7022 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7023 DAG.getConstant(1, NVT),
7024 DAG.getConstant(0, NVT));
7025 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7033 // Expand the subcomponents.
7034 SDValue LHSL, LHSH, RHSL, RHSH;
7035 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7036 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7037 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7038 SDValue LoOps[2] = { LHSL, RHSL };
7039 SDValue HiOps[3] = { LHSH, RHSH };
7041 if (Node->getOpcode() == ISD::ADDC) {
7042 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7043 HiOps[2] = Lo.getValue(1);
7044 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7046 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7047 HiOps[2] = Lo.getValue(1);
7048 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7050 // Remember that we legalized the flag.
7051 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7056 // Expand the subcomponents.
7057 SDValue LHSL, LHSH, RHSL, RHSH;
7058 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7059 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7060 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7061 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7062 SDValue HiOps[3] = { LHSH, RHSH };
7064 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7065 HiOps[2] = Lo.getValue(1);
7066 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7068 // Remember that we legalized the flag.
7069 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7073 // If the target wants to custom expand this, let them.
7074 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7075 SDValue New = TLI.LowerOperation(Op, DAG);
7076 if (New.getNode()) {
7077 ExpandOp(New, Lo, Hi);
7082 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7083 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7084 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7085 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7086 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7087 SDValue LL, LH, RL, RH;
7088 ExpandOp(Node->getOperand(0), LL, LH);
7089 ExpandOp(Node->getOperand(1), RL, RH);
7090 unsigned OuterBitSize = Op.getValueSizeInBits();
7091 unsigned InnerBitSize = RH.getValueSizeInBits();
7092 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7093 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7094 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7095 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7096 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7097 // The inputs are both zero-extended.
7099 // We can emit a umul_lohi.
7100 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7101 Hi = SDValue(Lo.getNode(), 1);
7105 // We can emit a mulhu+mul.
7106 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7107 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7111 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7112 // The input values are both sign-extended.
7114 // We can emit a smul_lohi.
7115 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7116 Hi = SDValue(Lo.getNode(), 1);
7120 // We can emit a mulhs+mul.
7121 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7122 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7127 // Lo,Hi = umul LHS, RHS.
7128 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7129 DAG.getVTList(NVT, NVT), LL, RL);
7131 Hi = UMulLOHI.getValue(1);
7132 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7133 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7134 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7135 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7139 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7140 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7141 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7142 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7143 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7144 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7149 // If nothing else, we can make a libcall.
7150 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7154 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7157 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7160 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7163 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7167 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7170 RTLIB::ADD_PPCF128),
7174 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7177 RTLIB::SUB_PPCF128),
7181 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7184 RTLIB::MUL_PPCF128),
7188 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7191 RTLIB::DIV_PPCF128),
7194 case ISD::FP_EXTEND: {
7195 if (VT == MVT::ppcf128) {
7196 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7197 Node->getOperand(0).getValueType()==MVT::f64);
7198 const uint64_t zero = 0;
7199 if (Node->getOperand(0).getValueType()==MVT::f32)
7200 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7202 Hi = Node->getOperand(0);
7203 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7206 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7207 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7208 Lo = ExpandLibCall(LC, Node, true, Hi);
7211 case ISD::FP_ROUND: {
7212 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7214 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7215 Lo = ExpandLibCall(LC, Node, true, Hi);
7230 case ISD::FNEARBYINT:
7233 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7234 switch(Node->getOpcode()) {
7236 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7237 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7240 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7241 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7244 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7245 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7248 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7249 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7252 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7253 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7256 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7257 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7260 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7261 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7264 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7265 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7268 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7269 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7272 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7273 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7276 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7277 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7280 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7281 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7283 case ISD::FNEARBYINT:
7284 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7285 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7288 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7289 RTLIB::POW_PPCF128);
7292 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7293 RTLIB::POWI_PPCF128);
7295 default: assert(0 && "Unreachable!");
7297 Lo = ExpandLibCall(LC, Node, false, Hi);
7301 if (VT == MVT::ppcf128) {
7303 ExpandOp(Node->getOperand(0), Lo, Tmp);
7304 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7305 // lo = hi==fabs(hi) ? lo : -lo;
7306 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7307 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7308 DAG.getCondCode(ISD::SETEQ));
7311 SDValue Mask = (VT == MVT::f64)
7312 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7313 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7314 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7315 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7316 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7317 if (getTypeAction(NVT) == Expand)
7318 ExpandOp(Lo, Lo, Hi);
7322 if (VT == MVT::ppcf128) {
7323 ExpandOp(Node->getOperand(0), Lo, Hi);
7324 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7325 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7328 SDValue Mask = (VT == MVT::f64)
7329 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7330 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7331 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7332 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7333 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7334 if (getTypeAction(NVT) == Expand)
7335 ExpandOp(Lo, Lo, Hi);
7338 case ISD::FCOPYSIGN: {
7339 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7340 if (getTypeAction(NVT) == Expand)
7341 ExpandOp(Lo, Lo, Hi);
7344 case ISD::SINT_TO_FP:
7345 case ISD::UINT_TO_FP: {
7346 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7347 MVT SrcVT = Node->getOperand(0).getValueType();
7349 // Promote the operand if needed. Do this before checking for
7350 // ppcf128 so conversions of i16 and i8 work.
7351 if (getTypeAction(SrcVT) == Promote) {
7352 SDValue Tmp = PromoteOp(Node->getOperand(0));
7354 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7355 DAG.getValueType(SrcVT))
7356 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7357 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7358 SrcVT = Node->getOperand(0).getValueType();
7361 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7362 static const uint64_t zero = 0;
7364 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7365 Node->getOperand(0)));
7366 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7368 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7369 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7370 Node->getOperand(0)));
7371 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7372 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7373 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7374 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7375 MVT::ppcf128, Node->getOperand(0),
7376 DAG.getConstant(0, MVT::i32),
7377 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7379 (APFloat(APInt(128, 2, TwoE32)),
7382 DAG.getCondCode(ISD::SETLT)),
7387 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7388 // si64->ppcf128 done by libcall, below
7389 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7390 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7391 Node->getOperand(0)), Lo, Hi);
7392 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7393 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7394 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7395 Node->getOperand(0),
7396 DAG.getConstant(0, MVT::i64),
7397 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7399 (APFloat(APInt(128, 2, TwoE64)),
7402 DAG.getCondCode(ISD::SETLT)),
7407 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7408 Node->getOperand(0), dl);
7409 if (getTypeAction(Lo.getValueType()) == Expand)
7410 // float to i32 etc. can be 'expanded' to a single node.
7411 ExpandOp(Lo, Lo, Hi);
7416 // Make sure the resultant values have been legalized themselves, unless this
7417 // is a type that requires multi-step expansion.
7418 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7419 Lo = LegalizeOp(Lo);
7421 // Don't legalize the high part if it is expanded to a single node.
7422 Hi = LegalizeOp(Hi);
7425 // Remember in a map if the values will be reused later.
7427 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7428 assert(isNew && "Value already expanded?!?");
7432 /// SplitVectorOp - Given an operand of vector type, break it down into
7433 /// two smaller values, still of vector type.
7434 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7436 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7437 SDNode *Node = Op.getNode();
7438 DebugLoc dl = Node->getDebugLoc();
7439 unsigned NumElements = Op.getValueType().getVectorNumElements();
7440 assert(NumElements > 1 && "Cannot split a single element vector!");
7442 MVT NewEltVT = Op.getValueType().getVectorElementType();
7444 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7445 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7447 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7448 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7450 // See if we already split it.
7451 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7452 = SplitNodes.find(Op);
7453 if (I != SplitNodes.end()) {
7454 Lo = I->second.first;
7455 Hi = I->second.second;
7459 switch (Node->getOpcode()) {
7464 assert(0 && "Unhandled operation in SplitVectorOp!");
7466 Lo = DAG.getUNDEF(NewVT_Lo);
7467 Hi = DAG.getUNDEF(NewVT_Hi);
7469 case ISD::BUILD_PAIR:
7470 Lo = Node->getOperand(0);
7471 Hi = Node->getOperand(1);
7473 case ISD::INSERT_VECTOR_ELT: {
7474 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7475 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7476 unsigned Index = Idx->getZExtValue();
7477 SDValue ScalarOp = Node->getOperand(1);
7478 if (Index < NewNumElts_Lo)
7479 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7480 DAG.getIntPtrConstant(Index));
7482 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7483 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7486 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7487 Node->getOperand(1),
7488 Node->getOperand(2), dl);
7489 SplitVectorOp(Tmp, Lo, Hi);
7492 case ISD::VECTOR_SHUFFLE: {
7493 // Build the low part.
7494 SDValue Mask = Node->getOperand(2);
7495 SmallVector<SDValue, 8> Ops;
7496 MVT PtrVT = TLI.getPointerTy();
7498 // Insert all of the elements from the input that are needed. We use
7499 // buildvector of extractelement here because the input vectors will have
7500 // to be legalized, so this makes the code simpler.
7501 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7502 SDValue IdxNode = Mask.getOperand(i);
7503 if (IdxNode.getOpcode() == ISD::UNDEF) {
7504 Ops.push_back(DAG.getUNDEF(NewEltVT));
7507 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7508 SDValue InVec = Node->getOperand(0);
7509 if (Idx >= NumElements) {
7510 InVec = Node->getOperand(1);
7513 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7514 DAG.getConstant(Idx, PtrVT)));
7516 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
7519 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7520 SDValue IdxNode = Mask.getOperand(i);
7521 if (IdxNode.getOpcode() == ISD::UNDEF) {
7522 Ops.push_back(DAG.getUNDEF(NewEltVT));
7525 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7526 SDValue InVec = Node->getOperand(0);
7527 if (Idx >= NumElements) {
7528 InVec = Node->getOperand(1);
7531 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7532 DAG.getConstant(Idx, PtrVT)));
7534 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
7537 case ISD::BUILD_VECTOR: {
7538 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7539 Node->op_begin()+NewNumElts_Lo);
7540 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
7542 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7544 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
7547 case ISD::CONCAT_VECTORS: {
7548 // FIXME: Handle non-power-of-two vectors?
7549 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7550 if (NewNumSubvectors == 1) {
7551 Lo = Node->getOperand(0);
7552 Hi = Node->getOperand(1);
7554 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7555 Node->op_begin()+NewNumSubvectors);
7556 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7557 &LoOps[0], LoOps.size());
7559 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7561 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7562 &HiOps[0], HiOps.size());
7566 case ISD::EXTRACT_SUBVECTOR: {
7567 SDValue Vec = Op.getOperand(0);
7568 SDValue Idx = Op.getOperand(1);
7569 MVT IdxVT = Idx.getValueType();
7571 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7572 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7574 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7575 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7578 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7579 DAG.getConstant(NewNumElts_Lo, IdxVT));
7580 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7585 SDValue Cond = Node->getOperand(0);
7587 SDValue LL, LH, RL, RH;
7588 SplitVectorOp(Node->getOperand(1), LL, LH);
7589 SplitVectorOp(Node->getOperand(2), RL, RH);
7591 if (Cond.getValueType().isVector()) {
7592 // Handle a vector merge.
7594 SplitVectorOp(Cond, CL, CH);
7595 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7596 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7598 // Handle a simple select with vector operands.
7599 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7600 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7604 case ISD::SELECT_CC: {
7605 SDValue CondLHS = Node->getOperand(0);
7606 SDValue CondRHS = Node->getOperand(1);
7607 SDValue CondCode = Node->getOperand(4);
7609 SDValue LL, LH, RL, RH;
7610 SplitVectorOp(Node->getOperand(2), LL, LH);
7611 SplitVectorOp(Node->getOperand(3), RL, RH);
7613 // Handle a simple select with vector operands.
7614 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7616 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7621 SDValue LL, LH, RL, RH;
7622 SplitVectorOp(Node->getOperand(0), LL, LH);
7623 SplitVectorOp(Node->getOperand(1), RL, RH);
7624 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7625 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7647 SDValue LL, LH, RL, RH;
7648 SplitVectorOp(Node->getOperand(0), LL, LH);
7649 SplitVectorOp(Node->getOperand(1), RL, RH);
7651 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7652 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7658 SplitVectorOp(Node->getOperand(0), L, H);
7660 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7661 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7677 case ISD::FP_TO_SINT:
7678 case ISD::FP_TO_UINT:
7679 case ISD::SINT_TO_FP:
7680 case ISD::UINT_TO_FP:
7682 case ISD::ANY_EXTEND:
7683 case ISD::SIGN_EXTEND:
7684 case ISD::ZERO_EXTEND:
7685 case ISD::FP_EXTEND: {
7687 SplitVectorOp(Node->getOperand(0), L, H);
7689 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7690 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7693 case ISD::CONVERT_RNDSAT: {
7694 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7696 SplitVectorOp(Node->getOperand(0), L, H);
7697 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7698 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7699 SDValue STyOpL = DAG.getValueType(L.getValueType());
7700 SDValue STyOpH = DAG.getValueType(H.getValueType());
7702 SDValue RndOp = Node->getOperand(3);
7703 SDValue SatOp = Node->getOperand(4);
7705 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
7706 RndOp, SatOp, CvtCode);
7707 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
7708 RndOp, SatOp, CvtCode);
7712 LoadSDNode *LD = cast<LoadSDNode>(Node);
7713 SDValue Ch = LD->getChain();
7714 SDValue Ptr = LD->getBasePtr();
7715 ISD::LoadExtType ExtType = LD->getExtensionType();
7716 const Value *SV = LD->getSrcValue();
7717 int SVOffset = LD->getSrcValueOffset();
7718 MVT MemoryVT = LD->getMemoryVT();
7719 unsigned Alignment = LD->getAlignment();
7720 bool isVolatile = LD->isVolatile();
7722 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7723 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7725 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7726 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7727 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7729 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7730 NewVT_Lo, Ch, Ptr, Offset,
7731 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7732 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7733 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7734 DAG.getIntPtrConstant(IncrementSize));
7735 SVOffset += IncrementSize;
7736 Alignment = MinAlign(Alignment, IncrementSize);
7737 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7738 NewVT_Hi, Ch, Ptr, Offset,
7739 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7741 // Build a factor node to remember that this load is independent of the
7743 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7746 // Remember that we legalized the chain.
7747 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7750 case ISD::BIT_CONVERT: {
7751 // We know the result is a vector. The input may be either a vector or a
7753 SDValue InOp = Node->getOperand(0);
7754 if (!InOp.getValueType().isVector() ||
7755 InOp.getValueType().getVectorNumElements() == 1) {
7756 // The input is a scalar or single-element vector.
7757 // Lower to a store/load so that it can be split.
7758 // FIXME: this could be improved probably.
7759 unsigned LdAlign = TLI.getTargetData()->
7760 getPrefTypeAlignment(Op.getValueType().getTypeForMVT());
7761 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7762 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7764 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7766 PseudoSourceValue::getFixedStack(FI), 0);
7767 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7768 PseudoSourceValue::getFixedStack(FI), 0);
7770 // Split the vector and convert each of the pieces now.
7771 SplitVectorOp(InOp, Lo, Hi);
7772 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7773 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7778 // Remember in a map if the values will be reused later.
7780 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7781 assert(isNew && "Value already split?!?");
7786 /// ScalarizeVectorOp - Given an operand of single-element vector type
7787 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7788 /// scalar (e.g. f32) value.
7789 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7790 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7791 SDNode *Node = Op.getNode();
7792 DebugLoc dl = Node->getDebugLoc();
7793 MVT NewVT = Op.getValueType().getVectorElementType();
7794 assert(Op.getValueType().getVectorNumElements() == 1);
7796 // See if we already scalarized it.
7797 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7798 if (I != ScalarizedNodes.end()) return I->second;
7801 switch (Node->getOpcode()) {
7804 Node->dump(&DAG); cerr << "\n";
7806 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7823 Result = DAG.getNode(Node->getOpcode(), dl,
7825 ScalarizeVectorOp(Node->getOperand(0)),
7826 ScalarizeVectorOp(Node->getOperand(1)));
7838 case ISD::FP_TO_SINT:
7839 case ISD::FP_TO_UINT:
7840 case ISD::SINT_TO_FP:
7841 case ISD::UINT_TO_FP:
7842 case ISD::SIGN_EXTEND:
7843 case ISD::ZERO_EXTEND:
7844 case ISD::ANY_EXTEND:
7846 case ISD::FP_EXTEND:
7847 Result = DAG.getNode(Node->getOpcode(), dl,
7849 ScalarizeVectorOp(Node->getOperand(0)));
7851 case ISD::CONVERT_RNDSAT: {
7852 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7853 Result = DAG.getConvertRndSat(NewVT, dl, Op0,
7854 DAG.getValueType(NewVT),
7855 DAG.getValueType(Op0.getValueType()),
7856 Node->getOperand(3),
7857 Node->getOperand(4),
7858 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7863 Result = DAG.getNode(Node->getOpcode(), dl,
7865 ScalarizeVectorOp(Node->getOperand(0)),
7866 Node->getOperand(1));
7869 LoadSDNode *LD = cast<LoadSDNode>(Node);
7870 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7871 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7872 ISD::LoadExtType ExtType = LD->getExtensionType();
7873 const Value *SV = LD->getSrcValue();
7874 int SVOffset = LD->getSrcValueOffset();
7875 MVT MemoryVT = LD->getMemoryVT();
7876 unsigned Alignment = LD->getAlignment();
7877 bool isVolatile = LD->isVolatile();
7879 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7880 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7882 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7883 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7884 MemoryVT.getVectorElementType(),
7885 isVolatile, Alignment);
7887 // Remember that we legalized the chain.
7888 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7891 case ISD::BUILD_VECTOR:
7892 Result = Node->getOperand(0);
7894 case ISD::INSERT_VECTOR_ELT:
7895 // Returning the inserted scalar element.
7896 Result = Node->getOperand(1);
7898 case ISD::CONCAT_VECTORS:
7899 assert(Node->getOperand(0).getValueType() == NewVT &&
7900 "Concat of non-legal vectors not yet supported!");
7901 Result = Node->getOperand(0);
7903 case ISD::VECTOR_SHUFFLE: {
7904 // Figure out if the scalar is the LHS or RHS and return it.
7905 SDValue EltNum = Node->getOperand(2).getOperand(0);
7906 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7907 Result = ScalarizeVectorOp(Node->getOperand(1));
7909 Result = ScalarizeVectorOp(Node->getOperand(0));
7912 case ISD::EXTRACT_SUBVECTOR:
7913 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7914 Node->getOperand(0), Node->getOperand(1));
7916 case ISD::BIT_CONVERT: {
7917 SDValue Op0 = Op.getOperand(0);
7918 if (Op0.getValueType().getVectorNumElements() == 1)
7919 Op0 = ScalarizeVectorOp(Op0);
7920 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7924 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7925 ScalarizeVectorOp(Op.getOperand(1)),
7926 ScalarizeVectorOp(Op.getOperand(2)));
7928 case ISD::SELECT_CC:
7929 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7930 Node->getOperand(1),
7931 ScalarizeVectorOp(Op.getOperand(2)),
7932 ScalarizeVectorOp(Op.getOperand(3)),
7933 Node->getOperand(4));
7936 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7937 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7938 Result = DAG.getNode(ISD::SETCC, dl,
7939 TLI.getSetCCResultType(Op0.getValueType()),
7940 Op0, Op1, Op.getOperand(2));
7941 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
7942 DAG.getConstant(-1ULL, NewVT),
7943 DAG.getConstant(0ULL, NewVT));
7948 if (TLI.isTypeLegal(NewVT))
7949 Result = LegalizeOp(Result);
7950 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7951 assert(isNew && "Value already scalarized?");
7957 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7958 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7959 if (I != WidenNodes.end()) return I->second;
7961 MVT VT = Op.getValueType();
7962 assert(VT.isVector() && "Cannot widen non-vector type!");
7965 SDNode *Node = Op.getNode();
7966 DebugLoc dl = Node->getDebugLoc();
7967 MVT EVT = VT.getVectorElementType();
7969 unsigned NumElts = VT.getVectorNumElements();
7970 unsigned NewNumElts = WidenVT.getVectorNumElements();
7971 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7972 assert(NewNumElts < 17);
7974 // When widen is called, it is assumed that it is more efficient to use a
7975 // wide type. The default action is to widen to operation to a wider legal
7976 // vector type and then do the operation if it is legal by calling LegalizeOp
7977 // again. If there is no vector equivalent, we will unroll the operation, do
7978 // it, and rebuild the vector. If most of the operations are vectorizible to
7979 // the legal type, the resulting code will be more efficient. If this is not
7980 // the case, the resulting code will preform badly as we end up generating
7981 // code to pack/unpack the results. It is the function that calls widen
7982 // that is responsible for seeing this doesn't happen.
7983 switch (Node->getOpcode()) {
7988 assert(0 && "Unexpected operation in WidenVectorOp!");
7990 case ISD::CopyFromReg:
7991 assert(0 && "CopyFromReg doesn't need widening!");
7993 case ISD::ConstantFP:
7994 // To build a vector of these elements, clients should call BuildVector
7995 // and with each element instead of creating a node with a vector type
7996 assert(0 && "Unexpected operation in WidenVectorOp!");
7998 // Variable Arguments with vector types doesn't make any sense to me
7999 assert(0 && "Unexpected operation in WidenVectorOp!");
8002 Result = DAG.getUNDEF(WidenVT);
8004 case ISD::BUILD_VECTOR: {
8005 // Build a vector with undefined for the new nodes
8006 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8007 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8008 NewOps.push_back(DAG.getUNDEF(EVT));
8010 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
8011 &NewOps[0], NewOps.size());
8014 case ISD::INSERT_VECTOR_ELT: {
8015 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8016 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8017 Node->getOperand(1), Node->getOperand(2));
8020 case ISD::VECTOR_SHUFFLE: {
8021 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8022 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8023 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Node);
8024 SmallVector<int, 8> NewMask;
8025 for (unsigned i = 0; i < NumElts; ++i) {
8026 int Idx = SVOp->getMaskElt(i);
8027 if (Idx < (int)NumElts)
8028 NewMask.push_back(Idx);
8030 NewMask.push_back(Idx + NewNumElts - NumElts);
8032 for (unsigned i = NumElts; i < NewNumElts; ++i)
8033 NewMask.push_back(-1);
8035 Result = DAG.getVectorShuffle(WidenVT, dl, Tmp1, Tmp2, &NewMask[0]);
8039 // If the load widen returns true, we can use a single load for the
8040 // vector. Otherwise, it is returning a token factor for multiple
8043 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8044 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8046 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8050 case ISD::BIT_CONVERT: {
8051 SDValue Tmp1 = Node->getOperand(0);
8052 // Converts between two different types so we need to determine
8053 // the correct widen type for the input operand.
8054 MVT InVT = Tmp1.getValueType();
8055 unsigned WidenSize = WidenVT.getSizeInBits();
8056 if (InVT.isVector()) {
8057 MVT InEltVT = InVT.getVectorElementType();
8058 unsigned InEltSize = InEltVT.getSizeInBits();
8059 assert(WidenSize % InEltSize == 0 &&
8060 "can not widen bit convert that are not multiple of element type");
8061 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8062 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8063 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8064 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8066 // If the result size is a multiple of the input size, widen the input
8067 // and then convert.
8068 unsigned InSize = InVT.getSizeInBits();
8069 assert(WidenSize % InSize == 0 &&
8070 "can not widen bit convert that are not multiple of element type");
8071 unsigned NewNumElts = WidenSize / InSize;
8072 SmallVector<SDValue, 16> Ops(NewNumElts);
8073 SDValue UndefVal = DAG.getUNDEF(InVT);
8075 for (unsigned i = 1; i < NewNumElts; ++i)
8078 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8079 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
8080 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8085 case ISD::SINT_TO_FP:
8086 case ISD::UINT_TO_FP:
8087 case ISD::FP_TO_SINT:
8088 case ISD::FP_TO_UINT:
8089 case ISD::FP_ROUND: {
8090 SDValue Tmp1 = Node->getOperand(0);
8091 // Converts between two different types so we need to determine
8092 // the correct widen type for the input operand.
8093 MVT TVT = Tmp1.getValueType();
8094 assert(TVT.isVector() && "can not widen non vector type");
8095 MVT TEVT = TVT.getVectorElementType();
8096 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8097 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8098 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8099 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8103 case ISD::FP_EXTEND:
8104 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8106 case ISD::SIGN_EXTEND:
8107 case ISD::ZERO_EXTEND:
8108 case ISD::ANY_EXTEND:
8109 case ISD::SIGN_EXTEND_INREG:
8118 // Unary op widening
8120 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8121 assert(Tmp1.getValueType() == WidenVT);
8122 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8125 case ISD::CONVERT_RNDSAT: {
8126 SDValue RndOp = Node->getOperand(3);
8127 SDValue SatOp = Node->getOperand(4);
8128 SDValue SrcOp = Node->getOperand(0);
8130 // Converts between two different types so we need to determine
8131 // the correct widen type for the input operand.
8132 MVT SVT = SrcOp.getValueType();
8133 assert(SVT.isVector() && "can not widen non vector type");
8134 MVT SEVT = SVT.getVectorElementType();
8135 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8137 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8138 assert(SrcOp.getValueType() == WidenVT);
8139 SDValue DTyOp = DAG.getValueType(WidenVT);
8140 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8141 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8143 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
8144 RndOp, SatOp, CvtCode);
8164 case ISD::FCOPYSIGN:
8168 // Binary op widening
8169 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8170 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8171 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8172 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8179 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8180 assert(Tmp1.getValueType() == WidenVT);
8181 SDValue ShOp = Node->getOperand(1);
8182 MVT ShVT = ShOp.getValueType();
8183 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8184 WidenVT.getVectorNumElements());
8185 ShOp = WidenVectorOp(ShOp, NewShVT);
8186 assert(ShOp.getValueType() == NewShVT);
8187 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8191 case ISD::EXTRACT_VECTOR_ELT: {
8192 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8193 assert(Tmp1.getValueType() == WidenVT);
8194 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8197 case ISD::CONCAT_VECTORS: {
8198 // We concurrently support only widen on a multiple of the incoming vector.
8199 // We could widen on a multiple of the incoming operand if necessary.
8200 unsigned NumConcat = NewNumElts / NumElts;
8201 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8202 SDValue UndefVal = DAG.getUNDEF(VT);
8203 SmallVector<SDValue, 8> MOps;
8205 for (unsigned i = 1; i != NumConcat; ++i) {
8206 MOps.push_back(UndefVal);
8208 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8209 &MOps[0], MOps.size()));
8212 case ISD::EXTRACT_SUBVECTOR: {
8213 SDValue Tmp1 = Node->getOperand(0);
8214 SDValue Idx = Node->getOperand(1);
8215 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8216 if (CIdx && CIdx->getZExtValue() == 0) {
8217 // Since we are access the start of the vector, the incoming
8218 // vector type might be the proper.
8219 MVT Tmp1VT = Tmp1.getValueType();
8220 if (Tmp1VT == WidenVT)
8223 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8224 if (Tmp1VTNumElts < NewNumElts)
8225 Result = WidenVectorOp(Tmp1, WidenVT);
8227 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8229 } else if (NewNumElts % NumElts == 0) {
8230 // Widen the extracted subvector.
8231 unsigned NumConcat = NewNumElts / NumElts;
8232 SDValue UndefVal = DAG.getUNDEF(VT);
8233 SmallVector<SDValue, 8> MOps;
8235 for (unsigned i = 1; i != NumConcat; ++i) {
8236 MOps.push_back(UndefVal);
8238 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8239 &MOps[0], MOps.size()));
8241 assert(0 && "can not widen extract subvector");
8242 // This could be implemented using insert and build vector but I would
8243 // like to see when this happens.
8249 // Determine new condition widen type and widen
8250 SDValue Cond1 = Node->getOperand(0);
8251 MVT CondVT = Cond1.getValueType();
8252 assert(CondVT.isVector() && "can not widen non vector type");
8253 MVT CondEVT = CondVT.getVectorElementType();
8254 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8255 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8256 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8258 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8259 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8260 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8261 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8265 case ISD::SELECT_CC: {
8266 // Determine new condition widen type and widen
8267 SDValue Cond1 = Node->getOperand(0);
8268 SDValue Cond2 = Node->getOperand(1);
8269 MVT CondVT = Cond1.getValueType();
8270 assert(CondVT.isVector() && "can not widen non vector type");
8271 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8272 MVT CondEVT = CondVT.getVectorElementType();
8273 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8274 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8275 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8276 assert(Cond1.getValueType() == CondWidenVT &&
8277 Cond2.getValueType() == CondWidenVT && "condition not widen");
8279 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8280 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8281 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8282 "operands not widen");
8283 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8284 Tmp2, Node->getOperand(4));
8288 // Determine widen for the operand
8289 SDValue Tmp1 = Node->getOperand(0);
8290 MVT TmpVT = Tmp1.getValueType();
8291 assert(TmpVT.isVector() && "can not widen non vector type");
8292 MVT TmpEVT = TmpVT.getVectorElementType();
8293 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8294 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8295 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8296 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8297 Node->getOperand(2));
8300 case ISD::ATOMIC_CMP_SWAP:
8301 case ISD::ATOMIC_LOAD_ADD:
8302 case ISD::ATOMIC_LOAD_SUB:
8303 case ISD::ATOMIC_LOAD_AND:
8304 case ISD::ATOMIC_LOAD_OR:
8305 case ISD::ATOMIC_LOAD_XOR:
8306 case ISD::ATOMIC_LOAD_NAND:
8307 case ISD::ATOMIC_LOAD_MIN:
8308 case ISD::ATOMIC_LOAD_MAX:
8309 case ISD::ATOMIC_LOAD_UMIN:
8310 case ISD::ATOMIC_LOAD_UMAX:
8311 case ISD::ATOMIC_SWAP: {
8312 // For now, we assume that using vectors for these operations don't make
8313 // much sense so we just split it. We return an empty result
8315 SplitVectorOp(Op, X, Y);
8320 } // end switch (Node->getOpcode())
8322 assert(Result.getNode() && "Didn't set a result!");
8324 Result = LegalizeOp(Result);
8326 AddWidenedOperand(Op, Result);
8330 // Utility function to find a legal vector type and its associated element
8331 // type from a preferred width and whose vector type must be the same size
8333 // TLI: Target lowering used to determine legal types
8334 // Width: Preferred width of element type
8335 // VVT: Vector value type whose size we must match.
8336 // Returns VecEVT and EVT - the vector type and its associated element type
8337 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8338 MVT& EVT, MVT& VecEVT) {
8339 // We start with the preferred width, make it a power of 2 and see if
8340 // we can find a vector type of that width. If not, we reduce it by
8341 // another power of 2. If we have widen the type, a vector of bytes should
8343 assert(TLI.isTypeLegal(VVT));
8344 unsigned EWidth = Width + 1;
8347 EWidth = (1 << Log2_32(EWidth-1));
8348 EVT = MVT::getIntegerVT(EWidth);
8349 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8350 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8351 } while (!TLI.isTypeLegal(VecEVT) ||
8352 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8355 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8365 // We assume that we have good rules to handle loading power of two loads so
8366 // we break down the operations to power of 2 loads. The strategy is to
8367 // load the largest power of 2 that we can easily transform to a legal vector
8368 // and then insert into that vector, and the cast the result into the legal
8369 // vector that we want. This avoids unnecessary stack converts.
8370 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8371 // the load is nonvolatile, we an use a wider load for the value.
8372 // Find a vector length we can load a large chunk
8375 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8376 EVTWidth = EVT.getSizeInBits();
8378 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8379 isVolatile, Alignment);
8380 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8381 LdChain.push_back(LdOp.getValue(1));
8383 // Check if we can load the element with one instruction
8384 if (LdWidth == EVTWidth) {
8385 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8388 // The vector element order is endianness dependent.
8390 LdWidth -= EVTWidth;
8391 unsigned Offset = 0;
8393 while (LdWidth > 0) {
8394 unsigned Increment = EVTWidth / 8;
8395 Offset += Increment;
8396 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8397 DAG.getIntPtrConstant(Increment));
8399 if (LdWidth < EVTWidth) {
8400 // Our current type we are using is too large, use a smaller size by
8401 // using a smaller power of 2
8402 unsigned oEVTWidth = EVTWidth;
8403 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8404 EVTWidth = EVT.getSizeInBits();
8405 // Readjust position and vector position based on new load type
8406 Idx = Idx * (oEVTWidth/EVTWidth);
8407 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8410 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8411 SVOffset+Offset, isVolatile,
8412 MinAlign(Alignment, Offset));
8413 LdChain.push_back(LdOp.getValue(1));
8414 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8415 DAG.getIntPtrConstant(Idx++));
8417 LdWidth -= EVTWidth;
8420 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8423 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8427 // TODO: Add support for ConcatVec and the ability to load many vector
8428 // types (e.g., v4i8). This will not work when a vector register
8429 // to memory mapping is strange (e.g., vector elements are not
8430 // stored in some sequential order).
8432 // It must be true that the widen vector type is bigger than where
8433 // we need to load from.
8434 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8435 MVT LdVT = LD->getMemoryVT();
8436 DebugLoc dl = LD->getDebugLoc();
8437 assert(LdVT.isVector() && NVT.isVector());
8438 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8441 SDValue Chain = LD->getChain();
8442 SDValue BasePtr = LD->getBasePtr();
8443 int SVOffset = LD->getSrcValueOffset();
8444 unsigned Alignment = LD->getAlignment();
8445 bool isVolatile = LD->isVolatile();
8446 const Value *SV = LD->getSrcValue();
8447 unsigned int LdWidth = LdVT.getSizeInBits();
8449 // Load value as a large register
8450 SDValueVector LdChain;
8451 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8452 Alignment, isVolatile, LdWidth, NVT, dl);
8454 if (LdChain.size() == 1) {
8459 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8460 &LdChain[0], LdChain.size());
8466 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8476 // Breaks the stores into a series of power of 2 width stores. For any
8477 // width, we convert the vector to the vector of element size that we
8478 // want to store. This avoids requiring a stack convert.
8480 // Find a width of the element type we can store with
8481 MVT VVT = ValOp.getValueType();
8484 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8485 EVTWidth = EVT.getSizeInBits();
8487 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8488 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8489 DAG.getIntPtrConstant(0));
8490 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8491 isVolatile, Alignment);
8492 StChain.push_back(StOp);
8494 // Check if we are done
8495 if (StWidth == EVTWidth) {
8500 StWidth -= EVTWidth;
8501 unsigned Offset = 0;
8503 while (StWidth > 0) {
8504 unsigned Increment = EVTWidth / 8;
8505 Offset += Increment;
8506 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8507 DAG.getIntPtrConstant(Increment));
8509 if (StWidth < EVTWidth) {
8510 // Our current type we are using is too large, use a smaller size by
8511 // using a smaller power of 2
8512 unsigned oEVTWidth = EVTWidth;
8513 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8514 EVTWidth = EVT.getSizeInBits();
8515 // Readjust position and vector position based on new load type
8516 Idx = Idx * (oEVTWidth/EVTWidth);
8517 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8520 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8521 DAG.getIntPtrConstant(Idx++));
8522 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8523 SVOffset + Offset, isVolatile,
8524 MinAlign(Alignment, Offset)));
8525 StWidth -= EVTWidth;
8530 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8533 // TODO: It might be cleaner if we can use SplitVector and have more legal
8534 // vector types that can be stored into memory (e.g., v4xi8 can
8535 // be stored as a word). This will not work when a vector register
8536 // to memory mapping is strange (e.g., vector elements are not
8537 // stored in some sequential order).
8539 MVT StVT = ST->getMemoryVT();
8540 SDValue ValOp = ST->getValue();
8541 DebugLoc dl = ST->getDebugLoc();
8543 // Check if we have widen this node with another value
8544 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8545 if (I != WidenNodes.end())
8548 MVT VVT = ValOp.getValueType();
8550 // It must be true that we the widen vector type is bigger than where
8551 // we need to store.
8552 assert(StVT.isVector() && VVT.isVector());
8553 assert(StVT.bitsLT(VVT));
8554 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8557 SDValueVector StChain;
8558 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8559 ST->getSrcValueOffset(), ST->getAlignment(),
8560 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8561 if (StChain.size() == 1)
8564 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8565 &StChain[0], StChain.size());
8569 // SelectionDAG::Legalize - This is the entry point for the file.
8571 void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
8572 /// run - This is the main entry point to this class.
8574 SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();