1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineConstantPool.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/Constants.h"
25 //===----------------------------------------------------------------------===//
26 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
27 /// hacks on it until the target machine can handle it. This involves
28 /// eliminating value sizes the machine cannot handle (promoting small sizes to
29 /// large sizes or splitting up large values into small values) as well as
30 /// eliminating operations the machine cannot handle.
32 /// This code also does a small amount of optimization and recognition of idioms
33 /// as part of its processing. For example, if a target does not support a
34 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
35 /// will attempt merge setcc and brc instructions into brcc's.
38 class SelectionDAGLegalize {
42 /// LegalizeAction - This enum indicates what action we should take for each
43 /// value type the can occur in the program.
45 Legal, // The target natively supports this value type.
46 Promote, // This should be promoted to the next larger type.
47 Expand, // This integer type should be broken into smaller pieces.
50 /// ValueTypeActions - This is a bitvector that contains two bits for each
51 /// value type, where the two bits correspond to the LegalizeAction enum.
52 /// This can be queried with "getTypeAction(VT)".
53 unsigned ValueTypeActions;
55 /// NeedsAnotherIteration - This is set when we expand a large integer
56 /// operation into smaller integer operations, but the smaller operations are
57 /// not set. This occurs only rarely in practice, for targets that don't have
58 /// 32-bit or larger integer registers.
59 bool NeedsAnotherIteration;
61 /// LegalizedNodes - For nodes that are of legal width, and that have more
62 /// than one use, this map indicates what regularized operand to use. This
63 /// allows us to avoid legalizing the same thing more than once.
64 std::map<SDOperand, SDOperand> LegalizedNodes;
66 /// PromotedNodes - For nodes that are below legal width, and that have more
67 /// than one use, this map indicates what promoted value to use. This allows
68 /// us to avoid promoting the same thing more than once.
69 std::map<SDOperand, SDOperand> PromotedNodes;
71 /// ExpandedNodes - For nodes that need to be expanded, and which have more
72 /// than one use, this map indicates which which operands are the expanded
73 /// version of the input. This allows us to avoid expanding the same node
75 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
77 void AddLegalizedOperand(SDOperand From, SDOperand To) {
78 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
79 assert(isNew && "Got into the map somehow?");
81 void AddPromotedOperand(SDOperand From, SDOperand To) {
82 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
83 assert(isNew && "Got into the map somehow?");
88 SelectionDAGLegalize(SelectionDAG &DAG);
90 /// Run - While there is still lowering to do, perform a pass over the DAG.
91 /// Most regularization can be done in a single pass, but targets that require
92 /// large values to be split into registers multiple times (e.g. i64 -> 4x
93 /// i16) require iteration for these values (the first iteration will demote
94 /// to i32, the second will demote to i16).
97 NeedsAnotherIteration = false;
99 } while (NeedsAnotherIteration);
102 /// getTypeAction - Return how we should legalize values of this type, either
103 /// it is already legal or we need to expand it into multiple registers of
104 /// smaller integer type, or we need to promote it to a larger type.
105 LegalizeAction getTypeAction(MVT::ValueType VT) const {
106 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
109 /// isTypeLegal - Return true if this type is legal on this target.
111 bool isTypeLegal(MVT::ValueType VT) const {
112 return getTypeAction(VT) == Legal;
118 SDOperand LegalizeOp(SDOperand O);
119 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
120 SDOperand PromoteOp(SDOperand O);
122 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
124 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
126 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
127 SDOperand &Lo, SDOperand &Hi);
128 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
129 SDOperand &Lo, SDOperand &Hi);
130 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
131 SDOperand &Lo, SDOperand &Hi);
133 SDOperand getIntPtrConstant(uint64_t Val) {
134 return DAG.getConstant(Val, TLI.getPointerTy());
140 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
141 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
142 ValueTypeActions(TLI.getValueTypeActions()) {
143 assert(MVT::LAST_VALUETYPE <= 16 &&
144 "Too many value types for ValueTypeActions to hold!");
147 void SelectionDAGLegalize::LegalizeDAG() {
148 SDOperand OldRoot = DAG.getRoot();
149 SDOperand NewRoot = LegalizeOp(OldRoot);
150 DAG.setRoot(NewRoot);
152 ExpandedNodes.clear();
153 LegalizedNodes.clear();
154 PromotedNodes.clear();
156 // Remove dead nodes now.
157 DAG.RemoveDeadNodes(OldRoot.Val);
160 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
161 assert(getTypeAction(Op.getValueType()) == Legal &&
162 "Caller should expand or promote operands that are not legal!");
164 // If this operation defines any values that cannot be represented in a
165 // register on this target, make sure to expand or promote them.
166 if (Op.Val->getNumValues() > 1) {
167 for (unsigned i = 0, e = Op.Val->getNumValues(); i != e; ++i)
168 switch (getTypeAction(Op.Val->getValueType(i))) {
169 case Legal: break; // Nothing to do.
172 ExpandOp(Op.getValue(i), T1, T2);
173 assert(LegalizedNodes.count(Op) &&
174 "Expansion didn't add legal operands!");
175 return LegalizedNodes[Op];
178 PromoteOp(Op.getValue(i));
179 assert(LegalizedNodes.count(Op) &&
180 "Expansion didn't add legal operands!");
181 return LegalizedNodes[Op];
185 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
186 if (I != LegalizedNodes.end()) return I->second;
188 SDOperand Tmp1, Tmp2, Tmp3;
190 SDOperand Result = Op;
191 SDNode *Node = Op.Val;
193 switch (Node->getOpcode()) {
195 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
196 assert(0 && "Do not know how to legalize this operator!");
198 case ISD::EntryToken:
199 case ISD::FrameIndex:
200 case ISD::GlobalAddress:
201 case ISD::ExternalSymbol:
202 case ISD::ConstantPool: // Nothing to do.
203 assert(getTypeAction(Node->getValueType(0)) == Legal &&
204 "This must be legal!");
206 case ISD::CopyFromReg:
207 Tmp1 = LegalizeOp(Node->getOperand(0));
208 if (Tmp1 != Node->getOperand(0))
209 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(),
210 Node->getValueType(0), Tmp1);
212 Result = Op.getValue(0);
214 // Since CopyFromReg produces two values, make sure to remember that we
215 // legalized both of them.
216 AddLegalizedOperand(Op.getValue(0), Result);
217 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
218 return Result.getValue(Op.ResNo);
219 case ISD::ImplicitDef:
220 Tmp1 = LegalizeOp(Node->getOperand(0));
221 if (Tmp1 != Node->getOperand(0))
222 Result = DAG.getImplicitDef(Tmp1, cast<RegSDNode>(Node)->getReg());
225 MVT::ValueType VT = Op.getValueType();
226 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
227 default: assert(0 && "This action is not supported yet!");
228 case TargetLowering::Expand:
229 case TargetLowering::Promote:
230 if (MVT::isInteger(VT))
231 Result = DAG.getConstant(0, VT);
232 else if (MVT::isFloatingPoint(VT))
233 Result = DAG.getConstantFP(0, VT);
235 assert(0 && "Unknown value type!");
237 case TargetLowering::Legal:
243 // We know we don't need to expand constants here, constants only have one
244 // value and we check that it is fine above.
246 // FIXME: Maybe we should handle things like targets that don't support full
247 // 32-bit immediates?
249 case ISD::ConstantFP: {
250 // Spill FP immediates to the constant pool if the target cannot directly
251 // codegen them. Targets often have some immediate values that can be
252 // efficiently generated into an FP register without a load. We explicitly
253 // leave these constants as ConstantFP nodes for the target to deal with.
255 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
257 // Check to see if this FP immediate is already legal.
258 bool isLegal = false;
259 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
260 E = TLI.legal_fpimm_end(); I != E; ++I)
261 if (CFP->isExactlyValue(*I)) {
267 // Otherwise we need to spill the constant to memory.
268 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
272 // If a FP immediate is precise when represented as a float, we put it
273 // into the constant pool as a float, even if it's is statically typed
275 MVT::ValueType VT = CFP->getValueType(0);
276 bool isDouble = VT == MVT::f64;
277 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
278 Type::FloatTy, CFP->getValue());
279 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
280 // Only do this if the target has a native EXTLOAD instruction from
282 TLI.getOperationAction(ISD::EXTLOAD,
283 MVT::f32) == TargetLowering::Legal) {
284 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
289 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC),
292 Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx,
293 DAG.getSrcValue(NULL), MVT::f32);
295 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
300 case ISD::TokenFactor: {
301 std::vector<SDOperand> Ops;
302 bool Changed = false;
303 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
304 SDOperand Op = Node->getOperand(i);
305 // Fold single-use TokenFactor nodes into this token factor as we go.
306 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
308 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
309 Ops.push_back(LegalizeOp(Op.getOperand(j)));
311 Ops.push_back(LegalizeOp(Op)); // Legalize the operands
312 Changed |= Ops[i] != Op;
316 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
320 case ISD::ADJCALLSTACKDOWN:
321 case ISD::ADJCALLSTACKUP:
322 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
323 // There is no need to legalize the size argument (Operand #1)
324 if (Tmp1 != Node->getOperand(0))
325 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
326 Node->getOperand(1));
328 case ISD::DYNAMIC_STACKALLOC:
329 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
330 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
331 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
332 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
333 Tmp3 != Node->getOperand(2))
334 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, Node->getValueType(0),
337 Result = Op.getValue(0);
339 // Since this op produces two values, make sure to remember that we
340 // legalized both of them.
341 AddLegalizedOperand(SDOperand(Node, 0), Result);
342 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
343 return Result.getValue(Op.ResNo);
346 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
347 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
349 bool Changed = false;
350 std::vector<SDOperand> Ops;
351 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
352 Ops.push_back(LegalizeOp(Node->getOperand(i)));
353 Changed |= Ops.back() != Node->getOperand(i);
356 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
357 std::vector<MVT::ValueType> RetTyVTs;
358 RetTyVTs.reserve(Node->getNumValues());
359 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
360 RetTyVTs.push_back(Node->getValueType(i));
361 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops), 0);
363 Result = Result.getValue(0);
365 // Since calls produce multiple values, make sure to remember that we
366 // legalized all of them.
367 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
368 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
369 return Result.getValue(Op.ResNo);
372 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
373 if (Tmp1 != Node->getOperand(0))
374 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
378 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
380 switch (getTypeAction(Node->getOperand(1).getValueType())) {
381 case Expand: assert(0 && "It's impossible to expand bools");
383 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
386 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
389 // Basic block destination (Op#2) is always legal.
390 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
391 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
392 Node->getOperand(2));
394 case ISD::BRCONDTWOWAY:
395 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
396 switch (getTypeAction(Node->getOperand(1).getValueType())) {
397 case Expand: assert(0 && "It's impossible to expand bools");
399 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
402 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
405 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
407 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
408 case TargetLowering::Promote:
409 default: assert(0 && "This action is not supported yet!");
410 case TargetLowering::Legal:
411 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
412 std::vector<SDOperand> Ops;
415 Ops.push_back(Node->getOperand(2));
416 Ops.push_back(Node->getOperand(3));
417 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
420 case TargetLowering::Expand:
421 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
422 Node->getOperand(2));
423 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
429 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
430 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
432 if (Tmp1 != Node->getOperand(0) ||
433 Tmp2 != Node->getOperand(1))
434 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2, Node->getOperand(2));
436 Result = SDOperand(Node, 0);
438 // Since loads produce two values, make sure to remember that we legalized
440 AddLegalizedOperand(SDOperand(Node, 0), Result);
441 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
442 return Result.getValue(Op.ResNo);
446 case ISD::ZEXTLOAD: {
447 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
448 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
450 MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType();
451 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
452 default: assert(0 && "This action is not supported yet!");
453 case TargetLowering::Promote:
454 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
455 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
456 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
457 // Since loads produce two values, make sure to remember that we legalized
459 AddLegalizedOperand(SDOperand(Node, 0), Result);
460 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
461 return Result.getValue(Op.ResNo);
463 case TargetLowering::Legal:
464 if (Tmp1 != Node->getOperand(0) ||
465 Tmp2 != Node->getOperand(1))
466 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
467 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
469 Result = SDOperand(Node, 0);
471 // Since loads produce two values, make sure to remember that we legalized
473 AddLegalizedOperand(SDOperand(Node, 0), Result);
474 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
475 return Result.getValue(Op.ResNo);
476 case TargetLowering::Expand:
477 assert(Node->getOpcode() != ISD::EXTLOAD &&
478 "EXTLOAD should always be supported!");
479 // Turn the unsupported load into an EXTLOAD followed by an explicit
480 // zero/sign extend inreg.
481 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
482 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
484 if (Node->getOpcode() == ISD::SEXTLOAD)
485 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
488 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
489 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
490 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
492 return Result.getValue(1);
495 assert(0 && "Unreachable");
497 case ISD::EXTRACT_ELEMENT:
498 // Get both the low and high parts.
499 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
500 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
501 Result = Tmp2; // 1 -> Hi
503 Result = Tmp1; // 0 -> Lo
507 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
509 switch (getTypeAction(Node->getOperand(1).getValueType())) {
511 // Legalize the incoming value (must be legal).
512 Tmp2 = LegalizeOp(Node->getOperand(1));
513 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
514 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
517 Tmp2 = PromoteOp(Node->getOperand(1));
518 Result = DAG.getCopyToReg(Tmp1, Tmp2, cast<RegSDNode>(Node)->getReg());
522 ExpandOp(Node->getOperand(1), Lo, Hi);
523 unsigned Reg = cast<RegSDNode>(Node)->getReg();
524 Lo = DAG.getCopyToReg(Tmp1, Lo, Reg);
525 Hi = DAG.getCopyToReg(Tmp1, Hi, Reg+1);
526 // Note that the copytoreg nodes are independent of each other.
527 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
528 assert(isTypeLegal(Result.getValueType()) &&
529 "Cannot expand multiple times yet (i64 -> i16)");
535 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
536 switch (Node->getNumOperands()) {
538 switch (getTypeAction(Node->getOperand(1).getValueType())) {
540 Tmp2 = LegalizeOp(Node->getOperand(1));
541 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
542 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
546 ExpandOp(Node->getOperand(1), Lo, Hi);
547 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
551 Tmp2 = PromoteOp(Node->getOperand(1));
552 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
557 if (Tmp1 != Node->getOperand(0))
558 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
560 default: { // ret <values>
561 std::vector<SDOperand> NewValues;
562 NewValues.push_back(Tmp1);
563 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
564 switch (getTypeAction(Node->getOperand(i).getValueType())) {
566 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
570 ExpandOp(Node->getOperand(i), Lo, Hi);
571 NewValues.push_back(Lo);
572 NewValues.push_back(Hi);
576 assert(0 && "Can't promote multiple return value yet!");
578 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
584 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
585 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
587 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
588 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
589 if (CFP->getValueType(0) == MVT::f32) {
594 V.F = CFP->getValue();
595 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
596 DAG.getConstant(V.I, MVT::i32), Tmp2, Node->getOperand(3));
598 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
603 V.F = CFP->getValue();
604 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
605 DAG.getConstant(V.I, MVT::i64), Tmp2, Node->getOperand(3));
610 switch (getTypeAction(Node->getOperand(1).getValueType())) {
612 SDOperand Val = LegalizeOp(Node->getOperand(1));
613 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
614 Tmp2 != Node->getOperand(2))
615 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2, Node->getOperand(3));
619 // Truncate the value and store the result.
620 Tmp3 = PromoteOp(Node->getOperand(1));
621 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
623 Node->getOperand(1).getValueType());
628 ExpandOp(Node->getOperand(1), Lo, Hi);
630 if (!TLI.isLittleEndian())
633 Lo = DAG.getNode(ISD::STORE, MVT::Other,Tmp1, Lo, Tmp2,Node->getOperand(3));
635 unsigned IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
636 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
637 getIntPtrConstant(IncrementSize));
638 assert(isTypeLegal(Tmp2.getValueType()) &&
639 "Pointers must be legal!");
640 //Again, claiming both parts of the store came form the same Instr
641 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2, Node->getOperand(3));
643 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
648 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
649 if (Tmp1 != Node->getOperand(0))
650 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
652 case ISD::TRUNCSTORE:
653 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
654 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
656 switch (getTypeAction(Node->getOperand(1).getValueType())) {
658 Tmp2 = LegalizeOp(Node->getOperand(1));
659 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
660 Tmp3 != Node->getOperand(2))
661 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
663 cast<MVTSDNode>(Node)->getExtraValueType());
667 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
671 switch (getTypeAction(Node->getOperand(0).getValueType())) {
672 case Expand: assert(0 && "It's impossible to expand bools");
674 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
677 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
680 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
681 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
683 switch (TLI.getOperationAction(Node->getOpcode(), Tmp2.getValueType())) {
684 default: assert(0 && "This action is not supported yet!");
685 case TargetLowering::Legal:
686 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
687 Tmp3 != Node->getOperand(2))
688 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
691 case TargetLowering::Promote: {
693 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
694 unsigned ExtOp, TruncOp;
695 if (MVT::isInteger(Tmp2.getValueType())) {
696 ExtOp = ISD::ZERO_EXTEND;
697 TruncOp = ISD::TRUNCATE;
699 ExtOp = ISD::FP_EXTEND;
700 TruncOp = ISD::FP_ROUND;
702 // Promote each of the values to the new type.
703 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
704 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
705 // Perform the larger operation, then round down.
706 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
707 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
713 switch (getTypeAction(Node->getOperand(0).getValueType())) {
715 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
716 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
717 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
718 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
719 Node->getValueType(0), Tmp1, Tmp2);
722 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
723 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
725 // If this is an FP compare, the operands have already been extended.
726 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
727 MVT::ValueType VT = Node->getOperand(0).getValueType();
728 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
730 // Otherwise, we have to insert explicit sign or zero extends. Note
731 // that we could insert sign extends for ALL conditions, but zero extend
732 // is cheaper on many machines (an AND instead of two shifts), so prefer
734 switch (cast<SetCCSDNode>(Node)->getCondition()) {
735 default: assert(0 && "Unknown integer comparison!");
742 // ALL of these operations will work if we either sign or zero extend
743 // the operands (including the unsigned comparisons!). Zero extend is
744 // usually a simpler/cheaper operation, so prefer it.
745 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
746 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
752 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
753 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT);
758 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
759 Node->getValueType(0), Tmp1, Tmp2);
762 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
763 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
764 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
765 switch (cast<SetCCSDNode>(Node)->getCondition()) {
769 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
770 if (RHSCST->isAllOnesValue()) {
772 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
773 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
774 Node->getValueType(0), Tmp1, RHSLo);
778 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
779 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
780 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
781 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
782 Node->getValueType(0), Tmp1,
783 DAG.getConstant(0, Tmp1.getValueType()));
786 // If this is a comparison of the sign bit, just look at the top part.
788 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
789 if ((cast<SetCCSDNode>(Node)->getCondition() == ISD::SETLT &&
790 CST->getValue() == 0) || // X < 0
791 (cast<SetCCSDNode>(Node)->getCondition() == ISD::SETGT &&
792 (CST->isAllOnesValue()))) // X > -1
793 return DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
794 Node->getValueType(0), LHSHi, RHSHi);
796 // FIXME: This generated code sucks.
798 switch (cast<SetCCSDNode>(Node)->getCondition()) {
799 default: assert(0 && "Unknown integer setcc!");
801 case ISD::SETULT: LowCC = ISD::SETULT; break;
803 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
805 case ISD::SETULE: LowCC = ISD::SETULE; break;
807 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
810 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
811 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
812 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
814 // NOTE: on targets without efficient SELECT of bools, we can always use
815 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
816 Tmp1 = DAG.getSetCC(LowCC, Node->getValueType(0), LHSLo, RHSLo);
817 Tmp2 = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
818 Node->getValueType(0), LHSHi, RHSHi);
819 Result = DAG.getSetCC(ISD::SETEQ, Node->getValueType(0), LHSHi, RHSHi);
820 Result = DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
830 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
831 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
833 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
834 switch (getTypeAction(Node->getOperand(2).getValueType())) {
835 case Expand: assert(0 && "Cannot expand a byte!");
837 Tmp3 = LegalizeOp(Node->getOperand(2));
840 Tmp3 = PromoteOp(Node->getOperand(2));
844 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
848 switch (getTypeAction(Node->getOperand(3).getValueType())) {
849 case Expand: assert(0 && "Cannot expand this yet!");
851 Tmp4 = LegalizeOp(Node->getOperand(3));
854 Tmp4 = PromoteOp(Node->getOperand(3));
859 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
860 case Expand: assert(0 && "Cannot expand this yet!");
862 Tmp5 = LegalizeOp(Node->getOperand(4));
865 Tmp5 = PromoteOp(Node->getOperand(4));
869 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
870 default: assert(0 && "This action not implemented for this operation!");
871 case TargetLowering::Legal:
872 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
873 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
874 Tmp5 != Node->getOperand(4)) {
875 std::vector<SDOperand> Ops;
876 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
877 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
878 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
881 case TargetLowering::Expand: {
882 // Otherwise, the target does not support this operation. Lower the
883 // operation to an explicit libcall as appropriate.
884 MVT::ValueType IntPtr = TLI.getPointerTy();
885 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
886 std::vector<std::pair<SDOperand, const Type*> > Args;
888 const char *FnName = 0;
889 if (Node->getOpcode() == ISD::MEMSET) {
890 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
891 // Extend the ubyte argument to be an int value for the call.
892 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
893 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
894 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
897 } else if (Node->getOpcode() == ISD::MEMCPY ||
898 Node->getOpcode() == ISD::MEMMOVE) {
899 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
900 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
901 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
902 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
904 assert(0 && "Unknown op!");
906 std::pair<SDOperand,SDOperand> CallResult =
907 TLI.LowerCallTo(Tmp1, Type::VoidTy, false,
908 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
909 Result = LegalizeOp(CallResult.second);
912 case TargetLowering::Custom:
913 std::vector<SDOperand> Ops;
914 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
915 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
916 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
917 Result = TLI.LowerOperation(Result);
918 Result = LegalizeOp(Result);
927 case ISD::SRL_PARTS: {
928 std::vector<SDOperand> Ops;
929 bool Changed = false;
930 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
931 Ops.push_back(LegalizeOp(Node->getOperand(i)));
932 Changed |= Ops.back() != Node->getOperand(i);
935 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
937 // Since these produce multiple values, make sure to remember that we
938 // legalized all of them.
939 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
940 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
941 return Result.getValue(Op.ResNo);
958 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
959 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
960 if (Tmp1 != Node->getOperand(0) ||
961 Tmp2 != Node->getOperand(1))
962 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
967 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
968 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
969 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
970 case TargetLowering::Legal:
971 if (Tmp1 != Node->getOperand(0) ||
972 Tmp2 != Node->getOperand(1))
973 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
976 case TargetLowering::Promote:
977 case TargetLowering::Custom:
978 assert(0 && "Cannot promote/custom handle this yet!");
979 case TargetLowering::Expand: {
980 MVT::ValueType VT = Node->getValueType(0);
981 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
982 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
983 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
984 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
994 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
995 case TargetLowering::Legal:
996 if (Tmp1 != Node->getOperand(0))
997 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
999 case TargetLowering::Promote: {
1000 MVT::ValueType OVT = Tmp1.getValueType();
1001 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1002 //Zero extend the argument
1003 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1004 // Perform the larger operation, then subtract if needed.
1005 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1006 switch(Node->getOpcode())
1012 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1013 Tmp2 = DAG.getSetCC(ISD::SETEQ, MVT::i1, Tmp1,
1014 DAG.getConstant(getSizeInBits(NVT), NVT));
1015 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1016 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1019 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1020 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1021 DAG.getConstant(getSizeInBits(NVT) -
1022 getSizeInBits(OVT), NVT));
1027 case TargetLowering::Custom:
1028 assert(0 && "Cannot custom handle this yet!");
1029 case TargetLowering::Expand:
1030 assert(0 && "Cannot expand this yet!");
1041 Tmp1 = LegalizeOp(Node->getOperand(0));
1042 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1043 case TargetLowering::Legal:
1044 if (Tmp1 != Node->getOperand(0))
1045 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1047 case TargetLowering::Promote:
1048 case TargetLowering::Custom:
1049 assert(0 && "Cannot promote/custom handle this yet!");
1050 case TargetLowering::Expand:
1051 switch(Node->getOpcode()) {
1053 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1054 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1055 Result = LegalizeOp(DAG.getNode(ISD::SUB, Node->getValueType(0),
1060 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1061 MVT::ValueType VT = Node->getValueType(0);
1062 Tmp2 = DAG.getConstantFP(0.0, VT);
1063 Tmp2 = DAG.getSetCC(ISD::SETUGT, TLI.getSetCCResultTy(), Tmp1, Tmp2);
1064 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1065 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1066 Result = LegalizeOp(Result);
1072 MVT::ValueType VT = Node->getValueType(0);
1073 Type *T = VT == MVT::f32 ? Type::FloatTy : Type::DoubleTy;
1074 const char *FnName = 0;
1075 switch(Node->getOpcode()) {
1076 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1077 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1078 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1079 default: assert(0 && "Unreachable!");
1081 std::vector<std::pair<SDOperand, const Type*> > Args;
1082 Args.push_back(std::make_pair(Tmp1, T));
1083 std::pair<SDOperand,SDOperand> CallResult =
1084 TLI.LowerCallTo(DAG.getEntryNode(), T, false,
1085 DAG.getExternalSymbol(FnName, VT), Args, DAG);
1086 Result = LegalizeOp(CallResult.first);
1090 assert(0 && "Unreachable!");
1096 // Conversion operators. The source and destination have different types.
1097 case ISD::ZERO_EXTEND:
1098 case ISD::SIGN_EXTEND:
1100 case ISD::FP_EXTEND:
1102 case ISD::FP_TO_SINT:
1103 case ISD::FP_TO_UINT:
1104 case ISD::SINT_TO_FP:
1105 case ISD::UINT_TO_FP:
1106 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1108 Tmp1 = LegalizeOp(Node->getOperand(0));
1109 if (Tmp1 != Node->getOperand(0))
1110 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1113 if (Node->getOpcode() == ISD::SINT_TO_FP ||
1114 Node->getOpcode() == ISD::UINT_TO_FP) {
1115 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
1116 Node->getValueType(0), Node->getOperand(0));
1117 Result = LegalizeOp(Result);
1119 } else if (Node->getOpcode() == ISD::TRUNCATE) {
1120 // In the expand case, we must be dealing with a truncate, because
1121 // otherwise the result would be larger than the source.
1122 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1124 // Since the result is legal, we should just be able to truncate the low
1125 // part of the source.
1126 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
1129 assert(0 && "Shouldn't need to expand other operators here!");
1132 switch (Node->getOpcode()) {
1133 case ISD::ZERO_EXTEND:
1134 Result = PromoteOp(Node->getOperand(0));
1135 // NOTE: Any extend would work here...
1136 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result);
1137 Result = DAG.getZeroExtendInReg(Result,
1138 Node->getOperand(0).getValueType());
1140 case ISD::SIGN_EXTEND:
1141 Result = PromoteOp(Node->getOperand(0));
1142 // NOTE: Any extend would work here...
1143 Result = DAG.getNode(ISD::ZERO_EXTEND, Op.getValueType(), Result);
1144 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1145 Result, Node->getOperand(0).getValueType());
1148 Result = PromoteOp(Node->getOperand(0));
1149 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
1151 case ISD::FP_EXTEND:
1152 Result = PromoteOp(Node->getOperand(0));
1153 if (Result.getValueType() != Op.getValueType())
1154 // Dynamically dead while we have only 2 FP types.
1155 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
1158 case ISD::FP_TO_SINT:
1159 case ISD::FP_TO_UINT:
1160 Result = PromoteOp(Node->getOperand(0));
1161 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
1163 case ISD::SINT_TO_FP:
1164 Result = PromoteOp(Node->getOperand(0));
1165 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1166 Result, Node->getOperand(0).getValueType());
1167 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
1169 case ISD::UINT_TO_FP:
1170 Result = PromoteOp(Node->getOperand(0));
1171 Result = DAG.getZeroExtendInReg(Result,
1172 Node->getOperand(0).getValueType());
1173 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
1178 case ISD::FP_ROUND_INREG:
1179 case ISD::SIGN_EXTEND_INREG: {
1180 Tmp1 = LegalizeOp(Node->getOperand(0));
1181 MVT::ValueType ExtraVT = cast<MVTSDNode>(Node)->getExtraValueType();
1183 // If this operation is not supported, convert it to a shl/shr or load/store
1185 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
1186 default: assert(0 && "This action not supported for this op yet!");
1187 case TargetLowering::Legal:
1188 if (Tmp1 != Node->getOperand(0))
1189 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1192 case TargetLowering::Expand:
1193 // If this is an integer extend and shifts are supported, do that.
1194 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
1195 // NOTE: we could fall back on load/store here too for targets without
1196 // SAR. However, it is doubtful that any exist.
1197 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
1198 MVT::getSizeInBits(ExtraVT);
1199 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
1200 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
1201 Node->getOperand(0), ShiftCst);
1202 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
1204 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
1205 // The only way we can lower this is to turn it into a STORETRUNC,
1206 // EXTLOAD pair, targetting a temporary location (a stack slot).
1208 // NOTE: there is a choice here between constantly creating new stack
1209 // slots and always reusing the same one. We currently always create
1210 // new ones, as reuse may inhibit scheduling.
1211 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
1212 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
1213 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
1214 MachineFunction &MF = DAG.getMachineFunction();
1216 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
1217 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
1218 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
1219 Node->getOperand(0), StackSlot, DAG.getSrcValue(NULL), ExtraVT);
1220 Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
1221 Result, StackSlot, DAG.getSrcValue(NULL), ExtraVT);
1223 assert(0 && "Unknown op");
1225 Result = LegalizeOp(Result);
1232 if (!Op.Val->hasOneUse())
1233 AddLegalizedOperand(Op, Result);
1238 /// PromoteOp - Given an operation that produces a value in an invalid type,
1239 /// promote it to compute the value into a larger type. The produced value will
1240 /// have the correct bits for the low portion of the register, but no guarantee
1241 /// is made about the top bits: it may be zero, sign-extended, or garbage.
1242 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
1243 MVT::ValueType VT = Op.getValueType();
1244 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1245 assert(getTypeAction(VT) == Promote &&
1246 "Caller should expand or legalize operands that are not promotable!");
1247 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
1248 "Cannot promote to smaller type!");
1250 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
1251 if (I != PromotedNodes.end()) return I->second;
1253 SDOperand Tmp1, Tmp2, Tmp3;
1256 SDNode *Node = Op.Val;
1258 // Promotion needs an optimization step to clean up after it, and is not
1259 // careful to avoid operations the target does not support. Make sure that
1260 // all generated operations are legalized in the next iteration.
1261 NeedsAnotherIteration = true;
1263 switch (Node->getOpcode()) {
1265 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
1266 assert(0 && "Do not know how to promote this operator!");
1269 Result = DAG.getNode(ISD::UNDEF, NVT);
1272 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
1273 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
1275 case ISD::ConstantFP:
1276 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
1277 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
1279 case ISD::CopyFromReg:
1280 Result = DAG.getCopyFromReg(cast<RegSDNode>(Node)->getReg(), NVT,
1281 Node->getOperand(0));
1282 // Remember that we legalized the chain.
1283 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1287 assert(getTypeAction(TLI.getSetCCResultTy()) == Legal &&
1288 "SetCC type is not legal??");
1289 Result = DAG.getSetCC(cast<SetCCSDNode>(Node)->getCondition(),
1290 TLI.getSetCCResultTy(), Node->getOperand(0),
1291 Node->getOperand(1));
1292 Result = LegalizeOp(Result);
1296 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1298 Result = LegalizeOp(Node->getOperand(0));
1299 assert(Result.getValueType() >= NVT &&
1300 "This truncation doesn't make sense!");
1301 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
1302 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
1305 // The truncation is not required, because we don't guarantee anything
1306 // about high bits anyway.
1307 Result = PromoteOp(Node->getOperand(0));
1310 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1311 // Truncate the low part of the expanded value to the result type
1312 Result = DAG.getNode(ISD::TRUNCATE, VT, Tmp1);
1315 case ISD::SIGN_EXTEND:
1316 case ISD::ZERO_EXTEND:
1317 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1318 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
1320 // Input is legal? Just do extend all the way to the larger type.
1321 Result = LegalizeOp(Node->getOperand(0));
1322 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1325 // Promote the reg if it's smaller.
1326 Result = PromoteOp(Node->getOperand(0));
1327 // The high bits are not guaranteed to be anything. Insert an extend.
1328 if (Node->getOpcode() == ISD::SIGN_EXTEND)
1329 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
1330 Node->getOperand(0).getValueType());
1332 Result = DAG.getZeroExtendInReg(Result,
1333 Node->getOperand(0).getValueType());
1338 case ISD::FP_EXTEND:
1339 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
1341 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1342 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
1343 case Promote: assert(0 && "Unreachable with 2 FP types!");
1345 // Input is legal? Do an FP_ROUND_INREG.
1346 Result = LegalizeOp(Node->getOperand(0));
1347 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1352 case ISD::SINT_TO_FP:
1353 case ISD::UINT_TO_FP:
1354 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1356 Result = LegalizeOp(Node->getOperand(0));
1357 // No extra round required here.
1358 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1362 Result = PromoteOp(Node->getOperand(0));
1363 if (Node->getOpcode() == ISD::SINT_TO_FP)
1364 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1365 Result, Node->getOperand(0).getValueType());
1367 Result = DAG.getZeroExtendInReg(Result,
1368 Node->getOperand(0).getValueType());
1369 // No extra round required here.
1370 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
1373 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
1374 Node->getOperand(0));
1375 Result = LegalizeOp(Result);
1377 // Round if we cannot tolerate excess precision.
1378 if (NoExcessFPPrecision)
1379 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1384 case ISD::FP_TO_SINT:
1385 case ISD::FP_TO_UINT:
1386 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1388 Tmp1 = LegalizeOp(Node->getOperand(0));
1391 // The input result is prerounded, so we don't have to do anything
1393 Tmp1 = PromoteOp(Node->getOperand(0));
1396 assert(0 && "not implemented");
1398 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1403 Tmp1 = PromoteOp(Node->getOperand(0));
1404 assert(Tmp1.getValueType() == NVT);
1405 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1406 // NOTE: we do not have to do any extra rounding here for
1407 // NoExcessFPPrecision, because we know the input will have the appropriate
1408 // precision, and these operations don't modify precision at all.
1414 Tmp1 = PromoteOp(Node->getOperand(0));
1415 assert(Tmp1.getValueType() == NVT);
1416 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
1417 if(NoExcessFPPrecision)
1418 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1427 // The input may have strange things in the top bits of the registers, but
1428 // these operations don't care. They may have wierd bits going out, but
1429 // that too is okay if they are integer operations.
1430 Tmp1 = PromoteOp(Node->getOperand(0));
1431 Tmp2 = PromoteOp(Node->getOperand(1));
1432 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
1433 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1435 // However, if this is a floating point operation, they will give excess
1436 // precision that we may not be able to tolerate. If we DO allow excess
1437 // precision, just leave it, otherwise excise it.
1438 // FIXME: Why would we need to round FP ops more than integer ones?
1439 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
1440 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
1441 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1446 // These operators require that their input be sign extended.
1447 Tmp1 = PromoteOp(Node->getOperand(0));
1448 Tmp2 = PromoteOp(Node->getOperand(1));
1449 if (MVT::isInteger(NVT)) {
1450 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
1451 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2, VT);
1453 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1455 // Perform FP_ROUND: this is probably overly pessimistic.
1456 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
1457 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
1462 // These operators require that their input be zero extended.
1463 Tmp1 = PromoteOp(Node->getOperand(0));
1464 Tmp2 = PromoteOp(Node->getOperand(1));
1465 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
1466 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1467 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1468 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
1472 Tmp1 = PromoteOp(Node->getOperand(0));
1473 Tmp2 = LegalizeOp(Node->getOperand(1));
1474 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
1477 // The input value must be properly sign extended.
1478 Tmp1 = PromoteOp(Node->getOperand(0));
1479 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1, VT);
1480 Tmp2 = LegalizeOp(Node->getOperand(1));
1481 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
1484 // The input value must be properly zero extended.
1485 Tmp1 = PromoteOp(Node->getOperand(0));
1486 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1487 Tmp2 = LegalizeOp(Node->getOperand(1));
1488 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
1491 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1492 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1493 // FIXME: When the DAG combiner exists, change this to use EXTLOAD!
1494 if (MVT::isInteger(NVT))
1495 Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2), VT);
1497 Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2), VT);
1499 // Remember that we legalized the chain.
1500 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1503 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1504 case Expand: assert(0 && "It's impossible to expand bools");
1506 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
1509 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1512 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
1513 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
1514 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
1517 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1518 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
1520 std::vector<SDOperand> Ops;
1521 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
1522 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1524 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
1525 "Can only promote single result calls");
1526 std::vector<MVT::ValueType> RetTyVTs;
1527 RetTyVTs.reserve(2);
1528 RetTyVTs.push_back(NVT);
1529 RetTyVTs.push_back(MVT::Other);
1530 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops);
1531 Result = SDOperand(NC, 0);
1533 // Insert the new chain mapping.
1534 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1539 assert(Result.Val && "Didn't set a result!");
1540 AddPromotedOperand(Op, Result);
1544 /// ExpandAddSub - Find a clever way to expand this add operation into
1546 void SelectionDAGLegalize::
1547 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
1548 SDOperand &Lo, SDOperand &Hi) {
1549 // Expand the subcomponents.
1550 SDOperand LHSL, LHSH, RHSL, RHSH;
1551 ExpandOp(LHS, LHSL, LHSH);
1552 ExpandOp(RHS, RHSL, RHSH);
1554 // FIXME: this should be moved to the dag combiner someday.
1555 if (NodeOp == ISD::ADD_PARTS || NodeOp == ISD::SUB_PARTS)
1556 if (LHSL.getValueType() == MVT::i32) {
1558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHSL))
1559 if (C->getValue() == 0)
1561 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHSL))
1562 if (C->getValue() == 0)
1565 // Turn this into an add/sub of the high part only.
1567 DAG.getNode(NodeOp == ISD::ADD_PARTS ? ISD::ADD : ISD::SUB,
1568 LowEl.getValueType(), LHSH, RHSH);
1575 std::vector<SDOperand> Ops;
1576 Ops.push_back(LHSL);
1577 Ops.push_back(LHSH);
1578 Ops.push_back(RHSL);
1579 Ops.push_back(RHSH);
1580 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
1581 Hi = Lo.getValue(1);
1584 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
1585 SDOperand Op, SDOperand Amt,
1586 SDOperand &Lo, SDOperand &Hi) {
1587 // Expand the subcomponents.
1588 SDOperand LHSL, LHSH;
1589 ExpandOp(Op, LHSL, LHSH);
1591 std::vector<SDOperand> Ops;
1592 Ops.push_back(LHSL);
1593 Ops.push_back(LHSH);
1595 Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
1596 Hi = Lo.getValue(1);
1600 /// ExpandShift - Try to find a clever way to expand this shift operation out to
1601 /// smaller elements. If we can't find a way that is more efficient than a
1602 /// libcall on this target, return false. Otherwise, return true with the
1603 /// low-parts expanded into Lo and Hi.
1604 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
1605 SDOperand &Lo, SDOperand &Hi) {
1606 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
1607 "This is not a shift!");
1609 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
1610 SDOperand ShAmt = LegalizeOp(Amt);
1611 MVT::ValueType ShTy = ShAmt.getValueType();
1612 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
1613 unsigned NVTBits = MVT::getSizeInBits(NVT);
1615 // Handle the case when Amt is an immediate. Other cases are currently broken
1616 // and are disabled.
1617 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
1618 unsigned Cst = CN->getValue();
1619 // Expand the incoming operand to be shifted, so that we have its parts
1621 ExpandOp(Op, InL, InH);
1625 Lo = DAG.getConstant(0, NVT);
1626 Hi = DAG.getConstant(0, NVT);
1627 } else if (Cst > NVTBits) {
1628 Lo = DAG.getConstant(0, NVT);
1629 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
1630 } else if (Cst == NVTBits) {
1631 Lo = DAG.getConstant(0, NVT);
1634 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
1635 Hi = DAG.getNode(ISD::OR, NVT,
1636 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
1637 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
1642 Lo = DAG.getConstant(0, NVT);
1643 Hi = DAG.getConstant(0, NVT);
1644 } else if (Cst > NVTBits) {
1645 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
1646 Hi = DAG.getConstant(0, NVT);
1647 } else if (Cst == NVTBits) {
1649 Hi = DAG.getConstant(0, NVT);
1651 Lo = DAG.getNode(ISD::OR, NVT,
1652 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
1653 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
1654 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
1659 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
1660 DAG.getConstant(NVTBits-1, ShTy));
1661 } else if (Cst > NVTBits) {
1662 Lo = DAG.getNode(ISD::SRA, NVT, InH,
1663 DAG.getConstant(Cst-NVTBits, ShTy));
1664 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1665 DAG.getConstant(NVTBits-1, ShTy));
1666 } else if (Cst == NVTBits) {
1668 Hi = DAG.getNode(ISD::SRA, NVT, InH,
1669 DAG.getConstant(NVTBits-1, ShTy));
1671 Lo = DAG.getNode(ISD::OR, NVT,
1672 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
1673 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
1674 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
1679 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
1680 // so disable it for now. Currently targets are handling this via SHL_PARTS
1684 // If we have an efficient select operation (or if the selects will all fold
1685 // away), lower to some complex code, otherwise just emit the libcall.
1686 if (TLI.getOperationAction(ISD::SELECT, NVT) != TargetLowering::Legal &&
1687 !isa<ConstantSDNode>(Amt))
1691 ExpandOp(Op, InL, InH);
1692 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
1693 DAG.getConstant(NVTBits, ShTy), ShAmt);
1695 // Compare the unmasked shift amount against 32.
1696 SDOperand Cond = DAG.getSetCC(ISD::SETGE, TLI.getSetCCResultTy(), ShAmt,
1697 DAG.getConstant(NVTBits, ShTy));
1699 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
1700 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
1701 DAG.getConstant(NVTBits-1, ShTy));
1702 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
1703 DAG.getConstant(NVTBits-1, ShTy));
1706 if (Opc == ISD::SHL) {
1707 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
1708 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
1709 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
1710 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
1712 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
1713 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
1715 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
1716 DAG.getSetCC(ISD::SETEQ,
1717 TLI.getSetCCResultTy(), NAmt,
1718 DAG.getConstant(32, ShTy)),
1719 DAG.getConstant(0, NVT),
1720 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
1721 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
1723 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
1724 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
1727 if (Opc == ISD::SRA)
1728 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
1729 DAG.getConstant(NVTBits-1, ShTy));
1731 HiPart = DAG.getConstant(0, NVT);
1732 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
1733 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
1738 /// FindLatestAdjCallStackDown - Scan up the dag to find the latest (highest
1739 /// NodeDepth) node that is an AdjCallStackDown operation and occurs later than
1741 static void FindLatestAdjCallStackDown(SDNode *Node, SDNode *&Found) {
1742 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
1744 // If we found an ADJCALLSTACKDOWN, we already know this node occurs later
1745 // than the Found node. Just remember this node and return.
1746 if (Node->getOpcode() == ISD::ADJCALLSTACKDOWN) {
1751 // Otherwise, scan the operands of Node to see if any of them is a call.
1752 assert(Node->getNumOperands() != 0 &&
1753 "All leaves should have depth equal to the entry node!");
1754 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
1755 FindLatestAdjCallStackDown(Node->getOperand(i).Val, Found);
1757 // Tail recurse for the last iteration.
1758 FindLatestAdjCallStackDown(Node->getOperand(Node->getNumOperands()-1).Val,
1763 /// FindEarliestAdjCallStackUp - Scan down the dag to find the earliest (lowest
1764 /// NodeDepth) node that is an AdjCallStackUp operation and occurs more recent
1766 static void FindEarliestAdjCallStackUp(SDNode *Node, SDNode *&Found) {
1767 if (Found && Node->getNodeDepth() >= Found->getNodeDepth()) return;
1769 // If we found an ADJCALLSTACKUP, we already know this node occurs earlier
1770 // than the Found node. Just remember this node and return.
1771 if (Node->getOpcode() == ISD::ADJCALLSTACKUP) {
1776 // Otherwise, scan the operands of Node to see if any of them is a call.
1777 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
1778 if (UI == E) return;
1779 for (--E; UI != E; ++UI)
1780 FindEarliestAdjCallStackUp(*UI, Found);
1782 // Tail recurse for the last iteration.
1783 FindEarliestAdjCallStackUp(*UI, Found);
1786 /// FindAdjCallStackUp - Given a chained node that is part of a call sequence,
1787 /// find the ADJCALLSTACKUP node that terminates the call sequence.
1788 static SDNode *FindAdjCallStackUp(SDNode *Node) {
1789 if (Node->getOpcode() == ISD::ADJCALLSTACKUP)
1791 if (Node->use_empty())
1792 return 0; // No adjcallstackup
1794 if (Node->hasOneUse()) // Simple case, only has one user to check.
1795 return FindAdjCallStackUp(*Node->use_begin());
1797 SDOperand TheChain(Node, Node->getNumValues()-1);
1798 assert(TheChain.getValueType() == MVT::Other && "Is not a token chain!");
1800 for (SDNode::use_iterator UI = Node->use_begin(),
1801 E = Node->use_end(); ; ++UI) {
1802 assert(UI != E && "Didn't find a user of the tokchain, no ADJCALLSTACKUP!");
1804 // Make sure to only follow users of our token chain.
1806 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
1807 if (User->getOperand(i) == TheChain)
1808 return FindAdjCallStackUp(User);
1810 assert(0 && "Unreachable");
1814 /// FindInputOutputChains - If we are replacing an operation with a call we need
1815 /// to find the call that occurs before and the call that occurs after it to
1816 /// properly serialize the calls in the block.
1817 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
1819 SDNode *LatestAdjCallStackDown = Entry.Val;
1820 SDNode *LatestAdjCallStackUp = 0;
1821 FindLatestAdjCallStackDown(OpNode, LatestAdjCallStackDown);
1822 //std::cerr << "Found node: "; LatestAdjCallStackDown->dump(); std::cerr <<"\n";
1824 // It is possible that no ISD::ADJCALLSTACKDOWN was found because there is no
1825 // previous call in the function. LatestCallStackDown may in that case be
1826 // the entry node itself. Do not attempt to find a matching ADJCALLSTACKUP
1827 // unless LatestCallStackDown is an ADJCALLSTACKDOWN.
1828 if (LatestAdjCallStackDown->getOpcode() == ISD::ADJCALLSTACKDOWN)
1829 LatestAdjCallStackUp = FindAdjCallStackUp(LatestAdjCallStackDown);
1831 LatestAdjCallStackUp = Entry.Val;
1832 assert(LatestAdjCallStackUp && "NULL return from FindAdjCallStackUp");
1834 SDNode *EarliestAdjCallStackUp = 0;
1835 FindEarliestAdjCallStackUp(OpNode, EarliestAdjCallStackUp);
1837 if (EarliestAdjCallStackUp) {
1838 //std::cerr << "Found node: ";
1839 //EarliestAdjCallStackUp->dump(); std::cerr <<"\n";
1842 return SDOperand(LatestAdjCallStackUp, 0);
1847 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1848 // does not fit into a register, return the lo part and set the hi part to the
1849 // by-reg argument. If it does fit into a single register, return the result
1850 // and leave the Hi part unset.
1851 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
1854 SDOperand InChain = FindInputOutputChains(Node, OutChain,
1855 DAG.getEntryNode());
1856 if (InChain.Val == 0)
1857 InChain = DAG.getEntryNode();
1859 TargetLowering::ArgListTy Args;
1860 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1861 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
1862 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
1863 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
1865 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
1867 // We don't care about token chains for libcalls. We just use the entry
1868 // node as our input and ignore the output chain. This allows us to place
1869 // calls wherever we need them to satisfy data dependences.
1870 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
1871 SDOperand Result = TLI.LowerCallTo(InChain, RetTy, false, Callee,
1873 switch (getTypeAction(Result.getValueType())) {
1874 default: assert(0 && "Unknown thing");
1878 assert(0 && "Cannot promote this yet!");
1881 ExpandOp(Result, Lo, Hi);
1887 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
1888 /// destination type is legal.
1889 SDOperand SelectionDAGLegalize::
1890 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
1891 assert(getTypeAction(DestTy) == Legal && "Destination type is not legal!");
1892 assert(getTypeAction(Source.getValueType()) == Expand &&
1893 "This is not an expansion!");
1894 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
1897 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
1898 DAG.getEntryNode());
1900 const char *FnName = 0;
1902 if (DestTy == MVT::f32)
1903 FnName = "__floatdisf";
1905 assert(DestTy == MVT::f64 && "Unknown fp value type!");
1906 FnName = "__floatdidf";
1909 // If this is unsigned, and not supported, first perform the conversion to
1910 // signed, then adjust the result if the sign bit is set.
1911 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
1913 assert(Source.getValueType() == MVT::i64 &&
1914 "This only works for 64-bit -> FP");
1915 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
1916 // incoming integer is set. To handle this, we dynamically test to see if
1917 // it is set, and, if so, add a fudge factor.
1919 ExpandOp(Source, Lo, Hi);
1921 SDOperand SignSet = DAG.getSetCC(ISD::SETLT, TLI.getSetCCResultTy(), Hi,
1922 DAG.getConstant(0, Hi.getValueType()));
1923 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
1924 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
1925 SignSet, Four, Zero);
1926 // FIXME: This is almost certainly broken for big-endian systems. Should
1927 // this just put the fudge factor in the low bits of the uint64 constant or?
1928 static Constant *FudgeFactor =
1929 ConstantUInt::get(Type::ULongTy, 0x5f800000ULL << 32);
1931 MachineConstantPool *CP = DAG.getMachineFunction().getConstantPool();
1932 SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(FudgeFactor),
1933 TLI.getPointerTy());
1934 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
1935 SDOperand FudgeInReg;
1936 if (DestTy == MVT::f32)
1937 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
1939 assert(DestTy == MVT::f64 && "Unexpected conversion");
1940 FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
1941 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
1943 return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg);
1945 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
1947 TargetLowering::ArgListTy Args;
1948 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
1949 Args.push_back(std::make_pair(Source, ArgTy));
1951 // We don't care about token chains for libcalls. We just use the entry
1952 // node as our input and ignore the output chain. This allows us to place
1953 // calls wherever we need them to satisfy data dependences.
1954 const Type *RetTy = MVT::getTypeForValueType(DestTy);
1955 return TLI.LowerCallTo(InChain, RetTy, false, Callee, Args, DAG).first;
1960 /// ExpandOp - Expand the specified SDOperand into its two component pieces
1961 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
1962 /// LegalizeNodes map is filled in for any results that are not expanded, the
1963 /// ExpandedNodes map is filled in for any results that are expanded, and the
1964 /// Lo/Hi values are returned.
1965 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
1966 MVT::ValueType VT = Op.getValueType();
1967 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1968 SDNode *Node = Op.Val;
1969 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
1970 assert(MVT::isInteger(VT) && "Cannot expand FP values!");
1971 assert(MVT::isInteger(NVT) && NVT < VT &&
1972 "Cannot expand to FP value or to larger int value!");
1974 // If there is more than one use of this, see if we already expanded it.
1975 // There is no use remembering values that only have a single use, as the map
1976 // entries will never be reused.
1977 if (!Node->hasOneUse()) {
1978 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
1979 = ExpandedNodes.find(Op);
1980 if (I != ExpandedNodes.end()) {
1981 Lo = I->second.first;
1982 Hi = I->second.second;
1987 // Expanding to multiple registers needs to perform an optimization step, and
1988 // is not careful to avoid operations the target does not support. Make sure
1989 // that all generated operations are legalized in the next iteration.
1990 NeedsAnotherIteration = true;
1992 switch (Node->getOpcode()) {
1994 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
1995 assert(0 && "Do not know how to expand this operator!");
1998 Lo = DAG.getNode(ISD::UNDEF, NVT);
1999 Hi = DAG.getNode(ISD::UNDEF, NVT);
2001 case ISD::Constant: {
2002 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
2003 Lo = DAG.getConstant(Cst, NVT);
2004 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
2008 case ISD::CopyFromReg: {
2009 unsigned Reg = cast<RegSDNode>(Node)->getReg();
2010 // Aggregate register values are always in consequtive pairs.
2011 Lo = DAG.getCopyFromReg(Reg, NVT, Node->getOperand(0));
2012 Hi = DAG.getCopyFromReg(Reg+1, NVT, Lo.getValue(1));
2014 // Remember that we legalized the chain.
2015 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
2017 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
2021 case ISD::BUILD_PAIR:
2022 // Legalize both operands. FIXME: in the future we should handle the case
2023 // where the two elements are not legal.
2024 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
2025 Lo = LegalizeOp(Node->getOperand(0));
2026 Hi = LegalizeOp(Node->getOperand(1));
2030 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2031 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2032 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
2034 // Increment the pointer to the other half.
2035 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
2036 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
2037 getIntPtrConstant(IncrementSize));
2038 //Is this safe? declaring that the two parts of the split load
2039 //are from the same instruction?
2040 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
2042 // Build a factor node to remember that this load is independent of the
2044 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2047 // Remember that we legalized the chain.
2048 AddLegalizedOperand(Op.getValue(1), TF);
2049 if (!TLI.isLittleEndian())
2054 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2055 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2057 bool Changed = false;
2058 std::vector<SDOperand> Ops;
2059 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
2060 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2061 Changed |= Ops.back() != Node->getOperand(i);
2064 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2065 "Can only expand a call once so far, not i64 -> i16!");
2067 std::vector<MVT::ValueType> RetTyVTs;
2068 RetTyVTs.reserve(3);
2069 RetTyVTs.push_back(NVT);
2070 RetTyVTs.push_back(NVT);
2071 RetTyVTs.push_back(MVT::Other);
2072 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops);
2073 Lo = SDOperand(NC, 0);
2074 Hi = SDOperand(NC, 1);
2076 // Insert the new chain mapping.
2077 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
2082 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
2083 SDOperand LL, LH, RL, RH;
2084 ExpandOp(Node->getOperand(0), LL, LH);
2085 ExpandOp(Node->getOperand(1), RL, RH);
2086 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
2087 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
2091 SDOperand C, LL, LH, RL, RH;
2093 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2094 case Expand: assert(0 && "It's impossible to expand bools");
2096 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2099 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
2102 ExpandOp(Node->getOperand(1), LL, LH);
2103 ExpandOp(Node->getOperand(2), RL, RH);
2104 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
2105 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
2108 case ISD::SIGN_EXTEND: {
2110 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2111 case Expand: assert(0 && "expand-expand not implemented yet!");
2112 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
2114 In = PromoteOp(Node->getOperand(0));
2115 // Emit the appropriate sign_extend_inreg to get the value we want.
2116 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
2117 Node->getOperand(0).getValueType());
2121 // The low part is just a sign extension of the input (which degenerates to
2123 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
2125 // The high part is obtained by SRA'ing all but one of the bits of the lo
2127 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
2128 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
2129 TLI.getShiftAmountTy()));
2132 case ISD::ZERO_EXTEND: {
2134 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2135 case Expand: assert(0 && "expand-expand not implemented yet!");
2136 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
2138 In = PromoteOp(Node->getOperand(0));
2139 // Emit the appropriate zero_extend_inreg to get the value we want.
2140 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
2144 // The low part is just a zero extension of the input (which degenerates to
2146 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
2148 // The high part is just a zero.
2149 Hi = DAG.getConstant(0, NVT);
2152 // These operators cannot be expanded directly, emit them as calls to
2153 // library functions.
2154 case ISD::FP_TO_SINT:
2155 if (Node->getOperand(0).getValueType() == MVT::f32)
2156 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
2158 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
2160 case ISD::FP_TO_UINT:
2161 if (Node->getOperand(0).getValueType() == MVT::f32)
2162 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
2164 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
2168 // If we can emit an efficient shift operation, do so now.
2169 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2172 // If this target supports SHL_PARTS, use it.
2173 if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) {
2174 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
2179 // Otherwise, emit a libcall.
2180 Lo = ExpandLibCall("__ashldi3", Node, Hi);
2184 // If we can emit an efficient shift operation, do so now.
2185 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2188 // If this target supports SRA_PARTS, use it.
2189 if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) {
2190 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
2195 // Otherwise, emit a libcall.
2196 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
2199 // If we can emit an efficient shift operation, do so now.
2200 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
2203 // If this target supports SRL_PARTS, use it.
2204 if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) {
2205 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
2210 // Otherwise, emit a libcall.
2211 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
2215 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
2219 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
2223 if (TLI.getOperationAction(ISD::MULHU, NVT) == TargetLowering::Legal) {
2224 SDOperand LL, LH, RL, RH;
2225 ExpandOp(Node->getOperand(0), LL, LH);
2226 ExpandOp(Node->getOperand(1), RL, RH);
2227 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
2228 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
2229 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
2230 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
2231 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
2232 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
2234 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
2238 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
2239 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
2240 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
2241 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
2244 // Remember in a map if the values will be reused later.
2245 if (!Node->hasOneUse()) {
2246 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
2247 std::make_pair(Lo, Hi))).second;
2248 assert(isNew && "Value already expanded?!?");
2253 // SelectionDAG::Legalize - This is the entry point for the file.
2255 void SelectionDAG::Legalize() {
2256 /// run - This is the main entry point to this class.
2258 SelectionDAGLegalize(*this).Run();