1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 bool TypesNeedLegalizing;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
73 /// IsLegalizingCallArguments - This member is used only for the purpose
74 /// of providing assert to check for LegalizeTypes because legalizing an
75 /// operation might introduce call nodes that might need type legalization.
76 bool IsLegalizingCallArgs;
79 Legal, // The target natively supports this operation.
80 Promote, // This operation should be executed in a larger type.
81 Expand // Try to expand this to other ops, otherwise use a libcall.
84 /// ValueTypeActions - This is a bitvector that contains two bits for each
85 /// value type, where the two bits correspond to the LegalizeAction enum.
86 /// This can be queried with "getTypeAction(VT)".
87 TargetLowering::ValueTypeActionImpl ValueTypeActions;
89 /// LegalizedNodes - For nodes that are of legal width, and that have more
90 /// than one use, this map indicates what regularized operand to use. This
91 /// allows us to avoid legalizing the same thing more than once.
92 DenseMap<SDValue, SDValue> LegalizedNodes;
94 /// PromotedNodes - For nodes that are below legal width, and that have more
95 /// than one use, this map indicates what promoted value to use. This allows
96 /// us to avoid promoting the same thing more than once.
97 DenseMap<SDValue, SDValue> PromotedNodes;
99 /// ExpandedNodes - For nodes that need to be expanded this map indicates
100 /// which operands are the expanded version of the input. This allows
101 /// us to avoid expanding the same node more than once.
102 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
104 /// SplitNodes - For vector nodes that need to be split, this map indicates
105 /// which operands are the split version of the input. This allows us
106 /// to avoid splitting the same node more than once.
107 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
109 /// ScalarizedNodes - For nodes that need to be converted from vector types to
110 /// scalar types, this contains the mapping of ones we have already
111 /// processed to the result.
112 std::map<SDValue, SDValue> ScalarizedNodes;
114 /// WidenNodes - For nodes that need to be widened from one vector type to
115 /// another, this contains the mapping of those that we have already widen.
116 /// This allows us to avoid widening more than once.
117 std::map<SDValue, SDValue> WidenNodes;
119 void AddLegalizedOperand(SDValue From, SDValue To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDValue From, SDValue To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
132 void AddWidenedOperand(SDValue From, SDValue To) {
133 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
134 assert(isNew && "Got into the map somehow?");
136 // If someone requests legalization of the new node, return itself.
137 LegalizedNodes.insert(std::make_pair(To, To));
141 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
144 /// getTypeAction - Return how we should legalize values of this type, either
145 /// it is already legal or we need to expand it into multiple registers of
146 /// smaller integer type, or we need to promote it to a larger type.
147 LegalizeAction getTypeAction(MVT VT) const {
148 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
151 /// isTypeLegal - Return true if this type is legal on this target.
153 bool isTypeLegal(MVT VT) const {
154 return getTypeAction(VT) == Legal;
160 /// HandleOp - Legalize, Promote, or Expand the specified operand as
161 /// appropriate for its type.
162 void HandleOp(SDValue Op);
164 /// LegalizeOp - We know that the specified value has a legal type.
165 /// Recursively ensure that the operands have legal types, then return the
167 SDValue LegalizeOp(SDValue O);
169 /// UnrollVectorOp - We know that the given vector has a legal type, however
170 /// the operation it performs is not legal and is an operation that we have
171 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
172 /// operating on each element individually.
173 SDValue UnrollVectorOp(SDValue O);
175 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
176 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
177 /// is necessary to spill the vector being inserted into to memory, perform
178 /// the insert there, and then read the result back.
179 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
180 SDValue Idx, DebugLoc dl);
182 /// PromoteOp - Given an operation that produces a value in an invalid type,
183 /// promote it to compute the value into a larger type. The produced value
184 /// will have the correct bits for the low portion of the register, but no
185 /// guarantee is made about the top bits: it may be zero, sign-extended, or
187 SDValue PromoteOp(SDValue O);
189 /// ExpandOp - Expand the specified SDValue into its two component pieces
190 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
191 /// the LegalizedNodes map is filled in for any results that are not expanded,
192 /// the ExpandedNodes map is filled in for any results that are expanded, and
193 /// the Lo/Hi values are returned. This applies to integer types and Vector
195 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
197 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
198 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
199 /// for the existing elements but no guarantee is made about the new elements
200 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
201 /// when we have an instruction operating on an illegal vector type and we
202 /// want to widen it to do the computation on a legal wider vector type.
203 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
205 /// SplitVectorOp - Given an operand of vector type, break it down into
206 /// two smaller values.
207 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
209 /// ScalarizeVectorOp - Given an operand of single-element vector type
210 /// (e.g. v1f32), convert it into the equivalent operation that returns a
211 /// scalar (e.g. f32) value.
212 SDValue ScalarizeVectorOp(SDValue O);
214 /// Useful 16 element vector type that is used to pass operands for widening.
215 typedef SmallVector<SDValue, 16> SDValueVector;
217 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
218 /// the LdChain contains a single load and false if it contains a token
219 /// factor for multiple loads. It takes
220 /// Result: location to return the result
221 /// LdChain: location to return the load chain
222 /// Op: load operation to widen
223 /// NVT: widen vector result type we want for the load
224 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
225 SDValue Op, MVT NVT);
227 /// Helper genWidenVectorLoads - Helper function to generate a set of
228 /// loads to load a vector with a resulting wider type. It takes
229 /// LdChain: list of chains for the load we have generated
230 /// Chain: incoming chain for the ld vector
231 /// BasePtr: base pointer to load from
232 /// SV: memory disambiguation source value
233 /// SVOffset: memory disambiugation offset
234 /// Alignment: alignment of the memory
235 /// isVolatile: volatile load
236 /// LdWidth: width of memory that we want to load
237 /// ResType: the wider result result type for the resulting loaded vector
238 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
239 SDValue BasePtr, const Value *SV,
240 int SVOffset, unsigned Alignment,
241 bool isVolatile, unsigned LdWidth,
242 MVT ResType, DebugLoc dl);
244 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
245 /// location. It takes
246 /// ST: store node that we want to replace
247 /// Chain: incoming store chain
248 /// BasePtr: base address of where we want to store into
249 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
252 /// Helper genWidenVectorStores - Helper function to generate a set of
253 /// stores to store a widen vector into non widen memory
255 // StChain: list of chains for the stores we have generated
256 // Chain: incoming chain for the ld vector
257 // BasePtr: base pointer to load from
258 // SV: memory disambiguation source value
259 // SVOffset: memory disambiugation offset
260 // Alignment: alignment of the memory
261 // isVolatile: volatile lod
262 // ValOp: value to store
263 // StWidth: width of memory that we want to store
264 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
265 SDValue BasePtr, const Value *SV,
266 int SVOffset, unsigned Alignment,
267 bool isVolatile, SDValue ValOp,
268 unsigned StWidth, DebugLoc dl);
270 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
271 /// specified mask and type. Targets can specify exactly which masks they
272 /// support and the code generator is tasked with not creating illegal masks.
274 /// Note that this will also return true for shuffles that are promoted to a
277 /// If this is a legal shuffle, this method returns the (possibly promoted)
278 /// build_vector Mask. If it's not a legal shuffle, it returns null.
279 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
281 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
282 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
284 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
286 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
288 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
290 LegalizeSetCCOperands(LHS, RHS, CC, dl);
291 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
294 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
296 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
298 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
299 SDValue ExpandBUILD_VECTOR(SDNode *Node);
300 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
301 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
302 SDValue Op, DebugLoc dl);
303 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
305 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
307 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
310 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
311 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
312 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
313 SDValue &Lo, SDValue &Hi, DebugLoc dl);
314 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
315 SDValue &Lo, SDValue &Hi, DebugLoc dl);
317 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
318 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
322 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
323 /// specified mask and type. Targets can specify exactly which masks they
324 /// support and the code generator is tasked with not creating illegal masks.
326 /// Note that this will also return true for shuffles that are promoted to a
328 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
329 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
331 case TargetLowering::Legal:
332 case TargetLowering::Custom:
334 case TargetLowering::Promote: {
335 // If this is promoted to a different type, convert the shuffle mask and
336 // ask if it is legal in the promoted type!
337 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
338 MVT EltVT = NVT.getVectorElementType();
340 // If we changed # elements, change the shuffle mask.
341 unsigned NumEltsGrowth =
342 NVT.getVectorNumElements() / VT.getVectorNumElements();
343 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
344 if (NumEltsGrowth > 1) {
345 // Renumber the elements.
346 SmallVector<SDValue, 8> Ops;
347 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
348 SDValue InOp = Mask.getOperand(i);
349 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
350 if (InOp.getOpcode() == ISD::UNDEF)
351 Ops.push_back(DAG.getUNDEF(EltVT));
353 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
354 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
358 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
359 NVT, &Ops[0], Ops.size());
365 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
368 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
369 bool types, bool fast)
370 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
371 Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
372 assert(MVT::LAST_VALUETYPE <= 32 &&
373 "Too many value types for ValueTypeActions to hold!");
376 void SelectionDAGLegalize::LegalizeDAG() {
377 LastCALLSEQ_END = DAG.getEntryNode();
378 IsLegalizingCall = false;
379 IsLegalizingCallArgs = false;
381 // The legalize process is inherently a bottom-up recursive process (users
382 // legalize their uses before themselves). Given infinite stack space, we
383 // could just start legalizing on the root and traverse the whole graph. In
384 // practice however, this causes us to run out of stack space on large basic
385 // blocks. To avoid this problem, compute an ordering of the nodes where each
386 // node is only legalized after all of its operands are legalized.
387 DAG.AssignTopologicalOrder();
388 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
389 E = prior(DAG.allnodes_end()); I != next(E); ++I)
390 HandleOp(SDValue(I, 0));
392 // Finally, it's possible the root changed. Get the new root.
393 SDValue OldRoot = DAG.getRoot();
394 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
395 DAG.setRoot(LegalizedNodes[OldRoot]);
397 ExpandedNodes.clear();
398 LegalizedNodes.clear();
399 PromotedNodes.clear();
401 ScalarizedNodes.clear();
404 // Remove dead nodes now.
405 DAG.RemoveDeadNodes();
409 /// FindCallEndFromCallStart - Given a chained node that is part of a call
410 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
411 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
412 if (Node->getOpcode() == ISD::CALLSEQ_END)
414 if (Node->use_empty())
415 return 0; // No CallSeqEnd
417 // The chain is usually at the end.
418 SDValue TheChain(Node, Node->getNumValues()-1);
419 if (TheChain.getValueType() != MVT::Other) {
420 // Sometimes it's at the beginning.
421 TheChain = SDValue(Node, 0);
422 if (TheChain.getValueType() != MVT::Other) {
423 // Otherwise, hunt for it.
424 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
425 if (Node->getValueType(i) == MVT::Other) {
426 TheChain = SDValue(Node, i);
430 // Otherwise, we walked into a node without a chain.
431 if (TheChain.getValueType() != MVT::Other)
436 for (SDNode::use_iterator UI = Node->use_begin(),
437 E = Node->use_end(); UI != E; ++UI) {
439 // Make sure to only follow users of our token chain.
441 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
442 if (User->getOperand(i) == TheChain)
443 if (SDNode *Result = FindCallEndFromCallStart(User))
449 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
450 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
451 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
452 assert(Node && "Didn't find callseq_start for a call??");
453 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
455 assert(Node->getOperand(0).getValueType() == MVT::Other &&
456 "Node doesn't have a token chain argument!");
457 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
460 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
461 /// see if any uses can reach Dest. If no dest operands can get to dest,
462 /// legalize them, legalize ourself, and return false, otherwise, return true.
464 /// Keep track of the nodes we fine that actually do lead to Dest in
465 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
467 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
468 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
469 if (N == Dest) return true; // N certainly leads to Dest :)
471 // If we've already processed this node and it does lead to Dest, there is no
472 // need to reprocess it.
473 if (NodesLeadingTo.count(N)) return true;
475 // If the first result of this node has been already legalized, then it cannot
477 switch (getTypeAction(N->getValueType(0))) {
479 if (LegalizedNodes.count(SDValue(N, 0))) return false;
482 if (PromotedNodes.count(SDValue(N, 0))) return false;
485 if (ExpandedNodes.count(SDValue(N, 0))) return false;
489 // Okay, this node has not already been legalized. Check and legalize all
490 // operands. If none lead to Dest, then we can legalize this node.
491 bool OperandsLeadToDest = false;
492 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
493 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
494 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
496 if (OperandsLeadToDest) {
497 NodesLeadingTo.insert(N);
501 // Okay, this node looks safe, legalize it and return false.
502 HandleOp(SDValue(N, 0));
506 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
507 /// appropriate for its type.
508 void SelectionDAGLegalize::HandleOp(SDValue Op) {
509 MVT VT = Op.getValueType();
510 // If the type legalizer was run then we should never see any illegal result
511 // types here except for target constants (the type legalizer does not touch
512 // those) or for build vector used as a mask for a vector shuffle.
513 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
514 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
515 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant ||
516 Op.getOpcode() == ISD::BUILD_VECTOR) &&
517 "Illegal type introduced after type legalization?");
518 switch (getTypeAction(VT)) {
519 default: assert(0 && "Bad type action!");
520 case Legal: (void)LegalizeOp(Op); break;
522 if (!VT.isVector()) {
527 // See if we can widen otherwise use Expand to either scalarize or split
528 MVT WidenVT = TLI.getWidenVectorType(VT);
529 if (WidenVT != MVT::Other) {
530 (void) WidenVectorOp(Op, WidenVT);
533 // else fall thru to expand since we can't widen the vector
536 if (!VT.isVector()) {
537 // If this is an illegal scalar, expand it into its two component
540 if (Op.getOpcode() == ISD::TargetConstant)
541 break; // Allow illegal target nodes.
543 } else if (VT.getVectorNumElements() == 1) {
544 // If this is an illegal single element vector, convert it to a
546 (void)ScalarizeVectorOp(Op);
548 // This is an illegal multiple element vector.
549 // Split it in half and legalize both parts.
551 SplitVectorOp(Op, X, Y);
557 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
558 /// a load from the constant pool.
559 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
560 SelectionDAG &DAG, const TargetLowering &TLI) {
562 DebugLoc dl = CFP->getDebugLoc();
564 // If a FP immediate is precise when represented as a float and if the
565 // target can do an extending load from float to double, we put it into
566 // the constant pool as a float, even if it's is statically typed as a
567 // double. This shrinks FP constants and canonicalizes them for targets where
568 // an FP extending load is the same cost as a normal load (such as on the x87
569 // fp stack or PPC FP unit).
570 MVT VT = CFP->getValueType(0);
571 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
573 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
574 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
575 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
580 while (SVT != MVT::f32) {
581 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
582 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
583 // Only do this if the target has a native EXTLOAD instruction from
585 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
586 TLI.ShouldShrinkFPConstant(OrigVT)) {
587 const Type *SType = SVT.getTypeForMVT();
588 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
594 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
595 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
597 return DAG.getExtLoad(ISD::EXTLOAD, dl,
598 OrigVT, DAG.getEntryNode(),
599 CPIdx, PseudoSourceValue::getConstantPool(),
600 0, VT, false, Alignment);
601 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
602 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
606 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
609 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
611 const TargetLowering &TLI) {
612 DebugLoc dl = Node->getDebugLoc();
613 MVT VT = Node->getValueType(0);
614 MVT SrcVT = Node->getOperand(1).getValueType();
615 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
616 "fcopysign expansion only supported for f32 and f64");
617 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
619 // First get the sign bit of second operand.
620 SDValue Mask1 = (SrcVT == MVT::f64)
621 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
622 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
623 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
624 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
625 Node->getOperand(1));
626 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
627 // Shift right or sign-extend it if the two operands have different types.
628 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
630 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
631 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
632 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
633 } else if (SizeDiff < 0) {
634 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
635 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
636 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
639 // Clear the sign bit of first operand.
640 SDValue Mask2 = (VT == MVT::f64)
641 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
642 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
643 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
644 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
645 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
647 // Or the value with the sign bit.
648 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
652 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
654 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
655 const TargetLowering &TLI) {
656 SDValue Chain = ST->getChain();
657 SDValue Ptr = ST->getBasePtr();
658 SDValue Val = ST->getValue();
659 MVT VT = Val.getValueType();
660 int Alignment = ST->getAlignment();
661 int SVOffset = ST->getSrcValueOffset();
662 DebugLoc dl = ST->getDebugLoc();
663 if (ST->getMemoryVT().isFloatingPoint() ||
664 ST->getMemoryVT().isVector()) {
665 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
666 if (TLI.isTypeLegal(intVT)) {
667 // Expand to a bitconvert of the value to the integer type of the
668 // same size, then a (misaligned) int store.
669 // FIXME: Does not handle truncating floating point stores!
670 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
671 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
672 SVOffset, ST->isVolatile(), Alignment);
674 // Do a (aligned) store to a stack slot, then copy from the stack slot
675 // to the final destination using (unaligned) integer loads and stores.
676 MVT StoredVT = ST->getMemoryVT();
678 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
679 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
680 unsigned RegBytes = RegVT.getSizeInBits() / 8;
681 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
683 // Make sure the stack slot is also aligned for the register type.
684 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
686 // Perform the original store, only redirected to the stack slot.
687 SDValue Store = DAG.getTruncStore(Chain, dl,
688 Val, StackPtr, NULL, 0,StoredVT);
689 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
690 SmallVector<SDValue, 8> Stores;
693 // Do all but one copies using the full register width.
694 for (unsigned i = 1; i < NumRegs; i++) {
695 // Load one integer register's worth from the stack slot.
696 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
697 // Store it to the final location. Remember the store.
698 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
699 ST->getSrcValue(), SVOffset + Offset,
701 MinAlign(ST->getAlignment(), Offset)));
702 // Increment the pointers.
704 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
706 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
709 // The last store may be partial. Do a truncating store. On big-endian
710 // machines this requires an extending load from the stack slot to ensure
711 // that the bits are in the right place.
712 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
714 // Load from the stack slot.
715 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
718 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
719 ST->getSrcValue(), SVOffset + Offset,
720 MemVT, ST->isVolatile(),
721 MinAlign(ST->getAlignment(), Offset)));
722 // The order of the stores doesn't matter - say it with a TokenFactor.
723 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
727 assert(ST->getMemoryVT().isInteger() &&
728 !ST->getMemoryVT().isVector() &&
729 "Unaligned store of unknown type.");
730 // Get the half-size VT
732 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
733 int NumBits = NewStoredVT.getSizeInBits();
734 int IncrementSize = NumBits / 8;
736 // Divide the stored value in two parts.
737 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
739 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
741 // Store the two parts
742 SDValue Store1, Store2;
743 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
744 ST->getSrcValue(), SVOffset, NewStoredVT,
745 ST->isVolatile(), Alignment);
746 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
747 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
748 Alignment = MinAlign(Alignment, IncrementSize);
749 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
750 ST->getSrcValue(), SVOffset + IncrementSize,
751 NewStoredVT, ST->isVolatile(), Alignment);
753 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
756 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
758 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
759 const TargetLowering &TLI) {
760 int SVOffset = LD->getSrcValueOffset();
761 SDValue Chain = LD->getChain();
762 SDValue Ptr = LD->getBasePtr();
763 MVT VT = LD->getValueType(0);
764 MVT LoadedVT = LD->getMemoryVT();
765 DebugLoc dl = LD->getDebugLoc();
766 if (VT.isFloatingPoint() || VT.isVector()) {
767 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
768 if (TLI.isTypeLegal(intVT)) {
769 // Expand to a (misaligned) integer load of the same size,
770 // then bitconvert to floating point or vector.
771 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
772 SVOffset, LD->isVolatile(),
774 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
775 if (VT.isFloatingPoint() && LoadedVT != VT)
776 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
778 SDValue Ops[] = { Result, Chain };
779 return DAG.getMergeValues(Ops, 2, dl);
781 // Copy the value to a (aligned) stack slot using (unaligned) integer
782 // loads and stores, then do a (aligned) load from the stack slot.
783 MVT RegVT = TLI.getRegisterType(intVT);
784 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
785 unsigned RegBytes = RegVT.getSizeInBits() / 8;
786 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
788 // Make sure the stack slot is also aligned for the register type.
789 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
791 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
792 SmallVector<SDValue, 8> Stores;
793 SDValue StackPtr = StackBase;
796 // Do all but one copies using the full register width.
797 for (unsigned i = 1; i < NumRegs; i++) {
798 // Load one integer register's worth from the original location.
799 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
800 SVOffset + Offset, LD->isVolatile(),
801 MinAlign(LD->getAlignment(), Offset));
802 // Follow the load with a store to the stack slot. Remember the store.
803 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
805 // Increment the pointers.
807 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
808 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
812 // The last copy may be partial. Do an extending load.
813 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
814 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
815 LD->getSrcValue(), SVOffset + Offset,
816 MemVT, LD->isVolatile(),
817 MinAlign(LD->getAlignment(), Offset));
818 // Follow the load with a store to the stack slot. Remember the store.
819 // On big-endian machines this requires a truncating store to ensure
820 // that the bits end up in the right place.
821 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
824 // The order of the stores doesn't matter - say it with a TokenFactor.
825 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
828 // Finally, perform the original load only redirected to the stack slot.
829 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
832 // Callers expect a MERGE_VALUES node.
833 SDValue Ops[] = { Load, TF };
834 return DAG.getMergeValues(Ops, 2, dl);
837 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
838 "Unaligned load of unsupported type.");
840 // Compute the new VT that is half the size of the old one. This is an
842 unsigned NumBits = LoadedVT.getSizeInBits();
844 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
847 unsigned Alignment = LD->getAlignment();
848 unsigned IncrementSize = NumBits / 8;
849 ISD::LoadExtType HiExtType = LD->getExtensionType();
851 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
852 if (HiExtType == ISD::NON_EXTLOAD)
853 HiExtType = ISD::ZEXTLOAD;
855 // Load the value in two parts
857 if (TLI.isLittleEndian()) {
858 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
859 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
860 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
861 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
862 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
863 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
864 MinAlign(Alignment, IncrementSize));
866 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
867 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
868 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
869 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
870 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
871 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
872 MinAlign(Alignment, IncrementSize));
875 // aggregate the two parts
876 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
877 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
878 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
880 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
883 SDValue Ops[] = { Result, TF };
884 return DAG.getMergeValues(Ops, 2, dl);
887 /// UnrollVectorOp - We know that the given vector has a legal type, however
888 /// the operation it performs is not legal and is an operation that we have
889 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
890 /// operating on each element individually.
891 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
892 MVT VT = Op.getValueType();
893 assert(isTypeLegal(VT) &&
894 "Caller should expand or promote operands that are not legal!");
895 assert(Op.getNode()->getNumValues() == 1 &&
896 "Can't unroll a vector with multiple results!");
897 unsigned NE = VT.getVectorNumElements();
898 MVT EltVT = VT.getVectorElementType();
899 DebugLoc dl = Op.getDebugLoc();
901 SmallVector<SDValue, 8> Scalars;
902 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
903 for (unsigned i = 0; i != NE; ++i) {
904 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
905 SDValue Operand = Op.getOperand(j);
906 MVT OperandVT = Operand.getValueType();
907 if (OperandVT.isVector()) {
908 // A vector operand; extract a single element.
909 MVT OperandEltVT = OperandVT.getVectorElementType();
910 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
913 DAG.getConstant(i, MVT::i32));
915 // A scalar operand; just use it as is.
916 Operands[j] = Operand;
920 switch (Op.getOpcode()) {
922 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
923 &Operands[0], Operands.size()));
930 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
931 DAG.getShiftAmountOperand(Operands[1])));
936 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
939 /// GetFPLibCall - Return the right libcall for the given floating point type.
940 static RTLIB::Libcall GetFPLibCall(MVT VT,
941 RTLIB::Libcall Call_F32,
942 RTLIB::Libcall Call_F64,
943 RTLIB::Libcall Call_F80,
944 RTLIB::Libcall Call_PPCF128) {
946 VT == MVT::f32 ? Call_F32 :
947 VT == MVT::f64 ? Call_F64 :
948 VT == MVT::f80 ? Call_F80 :
949 VT == MVT::ppcf128 ? Call_PPCF128 :
950 RTLIB::UNKNOWN_LIBCALL;
953 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
954 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
955 /// is necessary to spill the vector being inserted into to memory, perform
956 /// the insert there, and then read the result back.
957 SDValue SelectionDAGLegalize::
958 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
964 // If the target doesn't support this, we have to spill the input vector
965 // to a temporary stack slot, update the element, then reload it. This is
966 // badness. We could also load the value into a vector register (either
967 // with a "move to register" or "extload into register" instruction, then
968 // permute it into place, if the idx is a constant and if the idx is
969 // supported by the target.
970 MVT VT = Tmp1.getValueType();
971 MVT EltVT = VT.getVectorElementType();
972 MVT IdxVT = Tmp3.getValueType();
973 MVT PtrVT = TLI.getPointerTy();
974 SDValue StackPtr = DAG.CreateStackTemporary(VT);
976 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
979 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
980 PseudoSourceValue::getFixedStack(SPFI), 0);
982 // Truncate or zero extend offset to target pointer type.
983 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
984 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
985 // Add the offset to the index.
986 unsigned EltSize = EltVT.getSizeInBits()/8;
987 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
988 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
989 // Store the scalar value.
990 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
991 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
992 // Load the updated vector.
993 return DAG.getLoad(VT, dl, Ch, StackPtr,
994 PseudoSourceValue::getFixedStack(SPFI), 0);
998 /// LegalizeOp - We know that the specified value has a legal type, and
999 /// that its operands are legal. Now ensure that the operation itself
1000 /// is legal, recursively ensuring that the operands' operations remain
1002 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
1003 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1006 assert(isTypeLegal(Op.getValueType()) &&
1007 "Caller should expand or promote operands that are not legal!");
1008 SDNode *Node = Op.getNode();
1009 DebugLoc dl = Node->getDebugLoc();
1011 // If this operation defines any values that cannot be represented in a
1012 // register on this target, make sure to expand or promote them.
1013 if (Node->getNumValues() > 1) {
1014 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1015 if (getTypeAction(Node->getValueType(i)) != Legal) {
1016 HandleOp(Op.getValue(i));
1017 assert(LegalizedNodes.count(Op) &&
1018 "Handling didn't add legal operands!");
1019 return LegalizedNodes[Op];
1023 // Note that LegalizeOp may be reentered even from single-use nodes, which
1024 // means that we always must cache transformed nodes.
1025 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1026 if (I != LegalizedNodes.end()) return I->second;
1028 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1029 SDValue Result = Op;
1030 bool isCustom = false;
1032 switch (Node->getOpcode()) {
1033 case ISD::FrameIndex:
1034 case ISD::EntryToken:
1036 case ISD::BasicBlock:
1037 case ISD::TargetFrameIndex:
1038 case ISD::TargetJumpTable:
1039 case ISD::TargetConstant:
1040 case ISD::TargetConstantFP:
1041 case ISD::TargetConstantPool:
1042 case ISD::TargetGlobalAddress:
1043 case ISD::TargetGlobalTLSAddress:
1044 case ISD::TargetExternalSymbol:
1045 case ISD::VALUETYPE:
1047 case ISD::MEMOPERAND:
1049 case ISD::ARG_FLAGS:
1050 // Primitives must all be legal.
1051 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1052 "This must be legal!");
1055 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1056 // If this is a target node, legalize it by legalizing the operands then
1057 // passing it through.
1058 SmallVector<SDValue, 8> Ops;
1059 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1060 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1062 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1064 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1065 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1066 return Result.getValue(Op.getResNo());
1068 // Otherwise this is an unhandled builtin node. splat.
1070 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1072 assert(0 && "Do not know how to legalize this operator!");
1074 case ISD::GLOBAL_OFFSET_TABLE:
1075 case ISD::GlobalAddress:
1076 case ISD::GlobalTLSAddress:
1077 case ISD::ExternalSymbol:
1078 case ISD::ConstantPool:
1079 case ISD::JumpTable: // Nothing to do.
1080 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1081 default: assert(0 && "This action is not supported yet!");
1082 case TargetLowering::Custom:
1083 Tmp1 = TLI.LowerOperation(Op, DAG);
1084 if (Tmp1.getNode()) Result = Tmp1;
1085 // FALLTHROUGH if the target doesn't want to lower this op after all.
1086 case TargetLowering::Legal:
1090 case ISD::FRAMEADDR:
1091 case ISD::RETURNADDR:
1092 // The only option for these nodes is to custom lower them. If the target
1093 // does not custom lower them, then return zero.
1094 Tmp1 = TLI.LowerOperation(Op, DAG);
1098 Result = DAG.getConstant(0, TLI.getPointerTy());
1100 case ISD::FRAME_TO_ARGS_OFFSET: {
1101 MVT VT = Node->getValueType(0);
1102 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1103 default: assert(0 && "This action is not supported yet!");
1104 case TargetLowering::Custom:
1105 Result = TLI.LowerOperation(Op, DAG);
1106 if (Result.getNode()) break;
1108 case TargetLowering::Legal:
1109 Result = DAG.getConstant(0, VT);
1114 case ISD::EXCEPTIONADDR: {
1115 Tmp1 = LegalizeOp(Node->getOperand(0));
1116 MVT VT = Node->getValueType(0);
1117 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1118 default: assert(0 && "This action is not supported yet!");
1119 case TargetLowering::Expand: {
1120 unsigned Reg = TLI.getExceptionAddressRegister();
1121 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
1124 case TargetLowering::Custom:
1125 Result = TLI.LowerOperation(Op, DAG);
1126 if (Result.getNode()) break;
1128 case TargetLowering::Legal: {
1129 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1130 Result = DAG.getMergeValues(Ops, 2, dl);
1135 if (Result.getNode()->getNumValues() == 1) break;
1137 assert(Result.getNode()->getNumValues() == 2 &&
1138 "Cannot return more than two values!");
1140 // Since we produced two values, make sure to remember that we
1141 // legalized both of them.
1142 Tmp1 = LegalizeOp(Result);
1143 Tmp2 = LegalizeOp(Result.getValue(1));
1144 AddLegalizedOperand(Op.getValue(0), Tmp1);
1145 AddLegalizedOperand(Op.getValue(1), Tmp2);
1146 return Op.getResNo() ? Tmp2 : Tmp1;
1147 case ISD::EHSELECTION: {
1148 Tmp1 = LegalizeOp(Node->getOperand(0));
1149 Tmp2 = LegalizeOp(Node->getOperand(1));
1150 MVT VT = Node->getValueType(0);
1151 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1152 default: assert(0 && "This action is not supported yet!");
1153 case TargetLowering::Expand: {
1154 unsigned Reg = TLI.getExceptionSelectorRegister();
1155 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
1158 case TargetLowering::Custom:
1159 Result = TLI.LowerOperation(Op, DAG);
1160 if (Result.getNode()) break;
1162 case TargetLowering::Legal: {
1163 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1164 Result = DAG.getMergeValues(Ops, 2, dl);
1169 if (Result.getNode()->getNumValues() == 1) break;
1171 assert(Result.getNode()->getNumValues() == 2 &&
1172 "Cannot return more than two values!");
1174 // Since we produced two values, make sure to remember that we
1175 // legalized both of them.
1176 Tmp1 = LegalizeOp(Result);
1177 Tmp2 = LegalizeOp(Result.getValue(1));
1178 AddLegalizedOperand(Op.getValue(0), Tmp1);
1179 AddLegalizedOperand(Op.getValue(1), Tmp2);
1180 return Op.getResNo() ? Tmp2 : Tmp1;
1181 case ISD::EH_RETURN: {
1182 MVT VT = Node->getValueType(0);
1183 // The only "good" option for this node is to custom lower it.
1184 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1185 default: assert(0 && "This action is not supported at all!");
1186 case TargetLowering::Custom:
1187 Result = TLI.LowerOperation(Op, DAG);
1188 if (Result.getNode()) break;
1190 case TargetLowering::Legal:
1191 // Target does not know, how to lower this, lower to noop
1192 Result = LegalizeOp(Node->getOperand(0));
1197 case ISD::AssertSext:
1198 case ISD::AssertZext:
1199 Tmp1 = LegalizeOp(Node->getOperand(0));
1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1202 case ISD::MERGE_VALUES:
1203 // Legalize eliminates MERGE_VALUES nodes.
1204 Result = Node->getOperand(Op.getResNo());
1206 case ISD::CopyFromReg:
1207 Tmp1 = LegalizeOp(Node->getOperand(0));
1208 Result = Op.getValue(0);
1209 if (Node->getNumValues() == 2) {
1210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1212 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1213 if (Node->getNumOperands() == 3) {
1214 Tmp2 = LegalizeOp(Node->getOperand(2));
1215 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1219 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1221 // Since CopyFromReg produces two values, make sure to remember that we
1222 // legalized both of them.
1223 AddLegalizedOperand(Op.getValue(0), Result);
1224 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1225 return Result.getValue(Op.getResNo());
1227 MVT VT = Op.getValueType();
1228 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1229 default: assert(0 && "This action is not supported yet!");
1230 case TargetLowering::Expand:
1232 Result = DAG.getConstant(0, VT);
1233 else if (VT.isFloatingPoint())
1234 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1237 assert(0 && "Unknown value type!");
1239 case TargetLowering::Legal:
1245 case ISD::INTRINSIC_W_CHAIN:
1246 case ISD::INTRINSIC_WO_CHAIN:
1247 case ISD::INTRINSIC_VOID: {
1248 SmallVector<SDValue, 8> Ops;
1249 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1250 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1251 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1253 // Allow the target to custom lower its intrinsics if it wants to.
1254 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1255 TargetLowering::Custom) {
1256 Tmp3 = TLI.LowerOperation(Result, DAG);
1257 if (Tmp3.getNode()) Result = Tmp3;
1260 if (Result.getNode()->getNumValues() == 1) break;
1262 // Must have return value and chain result.
1263 assert(Result.getNode()->getNumValues() == 2 &&
1264 "Cannot return more than two values!");
1266 // Since loads produce two values, make sure to remember that we
1267 // legalized both of them.
1268 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1269 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1270 return Result.getValue(Op.getResNo());
1273 case ISD::DBG_STOPPOINT:
1274 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1277 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1278 case TargetLowering::Promote:
1279 default: assert(0 && "This action is not supported yet!");
1280 case TargetLowering::Expand: {
1281 DwarfWriter *DW = DAG.getDwarfWriter();
1282 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1284 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1286 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1287 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1288 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1289 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1290 std::string Dir, FN;
1291 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
1292 CU.getFilename(FN));
1294 unsigned Line = DSP->getLine();
1295 unsigned Col = DSP->getColumn();
1298 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1299 // won't hurt anything.
1301 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1302 DAG.getConstant(Col, MVT::i32),
1303 DAG.getConstant(SrcFile, MVT::i32) };
1304 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1306 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1307 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1310 Result = Tmp1; // chain
1313 Result = Tmp1; // chain
1317 case TargetLowering::Custom:
1318 Result = TLI.LowerOperation(Op, DAG);
1319 if (Result.getNode())
1321 case TargetLowering::Legal: {
1322 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1323 if (Action == Legal && Tmp1 == Node->getOperand(0))
1326 SmallVector<SDValue, 8> Ops;
1327 Ops.push_back(Tmp1);
1328 if (Action == Legal) {
1329 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1330 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1332 // Otherwise promote them.
1333 Ops.push_back(PromoteOp(Node->getOperand(1)));
1334 Ops.push_back(PromoteOp(Node->getOperand(2)));
1336 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1337 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1338 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1345 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1346 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1347 default: assert(0 && "This action is not supported yet!");
1348 case TargetLowering::Legal:
1349 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1350 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1351 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1352 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1354 case TargetLowering::Expand:
1355 Result = LegalizeOp(Node->getOperand(0));
1360 case ISD::DEBUG_LOC:
1361 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1362 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1363 default: assert(0 && "This action is not supported yet!");
1364 case TargetLowering::Legal: {
1365 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1366 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1367 if (Action == Legal && Tmp1 == Node->getOperand(0))
1369 if (Action == Legal) {
1370 Tmp2 = Node->getOperand(1);
1371 Tmp3 = Node->getOperand(2);
1372 Tmp4 = Node->getOperand(3);
1374 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1375 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1376 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1384 case ISD::DBG_LABEL:
1386 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1387 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1388 default: assert(0 && "This action is not supported yet!");
1389 case TargetLowering::Legal:
1390 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1391 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1393 case TargetLowering::Expand:
1394 Result = LegalizeOp(Node->getOperand(0));
1400 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1401 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1402 default: assert(0 && "This action is not supported yet!");
1403 case TargetLowering::Legal:
1404 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1405 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1406 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1407 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1408 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1410 case TargetLowering::Expand:
1412 Result = LegalizeOp(Node->getOperand(0));
1417 case ISD::MEMBARRIER: {
1418 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1419 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1420 default: assert(0 && "This action is not supported yet!");
1421 case TargetLowering::Legal: {
1423 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1424 for (int x = 1; x < 6; ++x) {
1425 Ops[x] = Node->getOperand(x);
1426 if (!isTypeLegal(Ops[x].getValueType()))
1427 Ops[x] = PromoteOp(Ops[x]);
1429 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1432 case TargetLowering::Expand:
1433 //There is no libgcc call for this op
1434 Result = Node->getOperand(0); // Noop
1440 case ISD::ATOMIC_CMP_SWAP: {
1441 unsigned int num_operands = 4;
1442 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1444 for (unsigned int x = 0; x < num_operands; ++x)
1445 Ops[x] = LegalizeOp(Node->getOperand(x));
1446 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1448 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1449 default: assert(0 && "This action is not supported yet!");
1450 case TargetLowering::Custom:
1451 Result = TLI.LowerOperation(Result, DAG);
1453 case TargetLowering::Legal:
1456 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1457 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1458 return Result.getValue(Op.getResNo());
1460 case ISD::ATOMIC_LOAD_ADD:
1461 case ISD::ATOMIC_LOAD_SUB:
1462 case ISD::ATOMIC_LOAD_AND:
1463 case ISD::ATOMIC_LOAD_OR:
1464 case ISD::ATOMIC_LOAD_XOR:
1465 case ISD::ATOMIC_LOAD_NAND:
1466 case ISD::ATOMIC_LOAD_MIN:
1467 case ISD::ATOMIC_LOAD_MAX:
1468 case ISD::ATOMIC_LOAD_UMIN:
1469 case ISD::ATOMIC_LOAD_UMAX:
1470 case ISD::ATOMIC_SWAP: {
1471 unsigned int num_operands = 3;
1472 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1474 for (unsigned int x = 0; x < num_operands; ++x)
1475 Ops[x] = LegalizeOp(Node->getOperand(x));
1476 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1478 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1479 default: assert(0 && "This action is not supported yet!");
1480 case TargetLowering::Custom:
1481 Result = TLI.LowerOperation(Result, DAG);
1483 case TargetLowering::Legal:
1486 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1487 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1488 return Result.getValue(Op.getResNo());
1490 case ISD::Constant: {
1491 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1493 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1495 // We know we don't need to expand constants here, constants only have one
1496 // value and we check that it is fine above.
1498 if (opAction == TargetLowering::Custom) {
1499 Tmp1 = TLI.LowerOperation(Result, DAG);
1505 case ISD::ConstantFP: {
1506 // Spill FP immediates to the constant pool if the target cannot directly
1507 // codegen them. Targets often have some immediate values that can be
1508 // efficiently generated into an FP register without a load. We explicitly
1509 // leave these constants as ConstantFP nodes for the target to deal with.
1510 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1512 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1513 default: assert(0 && "This action is not supported yet!");
1514 case TargetLowering::Legal:
1516 case TargetLowering::Custom:
1517 Tmp3 = TLI.LowerOperation(Result, DAG);
1518 if (Tmp3.getNode()) {
1523 case TargetLowering::Expand: {
1524 // Check to see if this FP immediate is already legal.
1525 bool isLegal = false;
1526 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1527 E = TLI.legal_fpimm_end(); I != E; ++I) {
1528 if (CFP->isExactlyValue(*I)) {
1533 // If this is a legal constant, turn it into a TargetConstantFP node.
1536 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1541 case ISD::TokenFactor:
1542 if (Node->getNumOperands() == 2) {
1543 Tmp1 = LegalizeOp(Node->getOperand(0));
1544 Tmp2 = LegalizeOp(Node->getOperand(1));
1545 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1546 } else if (Node->getNumOperands() == 3) {
1547 Tmp1 = LegalizeOp(Node->getOperand(0));
1548 Tmp2 = LegalizeOp(Node->getOperand(1));
1549 Tmp3 = LegalizeOp(Node->getOperand(2));
1550 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1552 SmallVector<SDValue, 8> Ops;
1553 // Legalize the operands.
1554 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1555 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1556 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1560 case ISD::FORMAL_ARGUMENTS:
1562 // The only option for this is to custom lower it.
1563 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1564 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1565 // A call within a calling sequence must be legalized to something
1566 // other than the normal CALLSEQ_END. Violating this gets Legalize
1567 // into an infinite loop.
1568 assert ((!IsLegalizingCall ||
1569 Node->getOpcode() != ISD::CALL ||
1570 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1571 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1573 // The number of incoming and outgoing values should match; unless the final
1574 // outgoing value is a flag.
1575 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1576 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1577 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1579 "Lowering call/formal_arguments produced unexpected # results!");
1581 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1582 // remember that we legalized all of them, so it doesn't get relegalized.
1583 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1584 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1586 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1587 if (Op.getResNo() == i)
1589 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1592 case ISD::EXTRACT_SUBREG: {
1593 Tmp1 = LegalizeOp(Node->getOperand(0));
1594 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1595 assert(idx && "Operand must be a constant");
1596 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1597 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1600 case ISD::INSERT_SUBREG: {
1601 Tmp1 = LegalizeOp(Node->getOperand(0));
1602 Tmp2 = LegalizeOp(Node->getOperand(1));
1603 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1604 assert(idx && "Operand must be a constant");
1605 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1609 case ISD::BUILD_VECTOR:
1610 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1611 default: assert(0 && "This action is not supported yet!");
1612 case TargetLowering::Custom:
1613 Tmp3 = TLI.LowerOperation(Result, DAG);
1614 if (Tmp3.getNode()) {
1619 case TargetLowering::Expand:
1620 Result = ExpandBUILD_VECTOR(Result.getNode());
1624 case ISD::INSERT_VECTOR_ELT:
1625 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1626 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1628 // The type of the value to insert may not be legal, even though the vector
1629 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1631 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1632 default: assert(0 && "Cannot expand insert element operand");
1633 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1634 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1636 // FIXME: An alternative would be to check to see if the target is not
1637 // going to custom lower this operation, we could bitcast to half elt
1638 // width and perform two inserts at that width, if that is legal.
1639 Tmp2 = Node->getOperand(1);
1642 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1644 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1645 Node->getValueType(0))) {
1646 default: assert(0 && "This action is not supported yet!");
1647 case TargetLowering::Legal:
1649 case TargetLowering::Custom:
1650 Tmp4 = TLI.LowerOperation(Result, DAG);
1651 if (Tmp4.getNode()) {
1656 case TargetLowering::Promote:
1657 // Fall thru for vector case
1658 case TargetLowering::Expand: {
1659 // If the insert index is a constant, codegen this as a scalar_to_vector,
1660 // then a shuffle that inserts it into the right position in the vector.
1661 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1662 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1663 // match the element type of the vector being created.
1664 if (Tmp2.getValueType() ==
1665 Op.getValueType().getVectorElementType()) {
1666 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1667 Tmp1.getValueType(), Tmp2);
1669 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1671 MVT::getIntVectorWithNumElements(NumElts);
1672 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1674 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1675 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1676 // elt 0 of the RHS.
1677 SmallVector<SDValue, 8> ShufOps;
1678 for (unsigned i = 0; i != NumElts; ++i) {
1679 if (i != InsertPos->getZExtValue())
1680 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1682 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1684 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
1685 &ShufOps[0], ShufOps.size());
1687 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
1688 Tmp1, ScVec, ShufMask);
1689 Result = LegalizeOp(Result);
1693 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1698 case ISD::SCALAR_TO_VECTOR:
1699 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1700 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1704 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1705 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1706 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1707 Node->getValueType(0))) {
1708 default: assert(0 && "This action is not supported yet!");
1709 case TargetLowering::Legal:
1711 case TargetLowering::Custom:
1712 Tmp3 = TLI.LowerOperation(Result, DAG);
1713 if (Tmp3.getNode()) {
1718 case TargetLowering::Expand:
1719 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1723 case ISD::VECTOR_SHUFFLE:
1724 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1725 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1726 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1728 // Allow targets to custom lower the SHUFFLEs they support.
1729 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1730 default: assert(0 && "Unknown operation action!");
1731 case TargetLowering::Legal:
1732 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1733 "vector shuffle should not be created if not legal!");
1735 case TargetLowering::Custom:
1736 Tmp3 = TLI.LowerOperation(Result, DAG);
1737 if (Tmp3.getNode()) {
1742 case TargetLowering::Expand: {
1743 MVT VT = Node->getValueType(0);
1744 MVT EltVT = VT.getVectorElementType();
1745 MVT PtrVT = TLI.getPointerTy();
1746 SDValue Mask = Node->getOperand(2);
1747 unsigned NumElems = Mask.getNumOperands();
1748 SmallVector<SDValue,8> Ops;
1749 for (unsigned i = 0; i != NumElems; ++i) {
1750 SDValue Arg = Mask.getOperand(i);
1751 if (Arg.getOpcode() == ISD::UNDEF) {
1752 Ops.push_back(DAG.getUNDEF(EltVT));
1754 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1755 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1757 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1758 DAG.getConstant(Idx, PtrVT)));
1760 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1761 DAG.getConstant(Idx - NumElems, PtrVT)));
1764 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1767 case TargetLowering::Promote: {
1768 // Change base type to a different vector type.
1769 MVT OVT = Node->getValueType(0);
1770 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1772 // Cast the two input vectors.
1773 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1774 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1776 // Convert the shuffle mask to the right # elements.
1777 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1778 assert(Tmp3.getNode() && "Shuffle not legal?");
1779 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
1780 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1786 case ISD::EXTRACT_VECTOR_ELT:
1787 Tmp1 = Node->getOperand(0);
1788 Tmp2 = LegalizeOp(Node->getOperand(1));
1789 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1790 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1793 case ISD::EXTRACT_SUBVECTOR:
1794 Tmp1 = Node->getOperand(0);
1795 Tmp2 = LegalizeOp(Node->getOperand(1));
1796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1797 Result = ExpandEXTRACT_SUBVECTOR(Result);
1800 case ISD::CONCAT_VECTORS: {
1801 // Use extract/insert/build vector for now. We might try to be
1802 // more clever later.
1803 MVT PtrVT = TLI.getPointerTy();
1804 SmallVector<SDValue, 8> Ops;
1805 unsigned NumOperands = Node->getNumOperands();
1806 for (unsigned i=0; i < NumOperands; ++i) {
1807 SDValue SubOp = Node->getOperand(i);
1808 MVT VVT = SubOp.getNode()->getValueType(0);
1809 MVT EltVT = VVT.getVectorElementType();
1810 unsigned NumSubElem = VVT.getVectorNumElements();
1811 for (unsigned j=0; j < NumSubElem; ++j) {
1812 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1813 DAG.getConstant(j, PtrVT)));
1816 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
1817 &Ops[0], Ops.size()));
1820 case ISD::CALLSEQ_START: {
1821 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1823 // Recursively Legalize all of the inputs of the call end that do not lead
1824 // to this call start. This ensures that any libcalls that need be inserted
1825 // are inserted *before* the CALLSEQ_START.
1826 IsLegalizingCallArgs = true;
1827 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1828 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1829 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1832 IsLegalizingCallArgs = false;
1834 // Now that we legalized all of the inputs (which may have inserted
1835 // libcalls) create the new CALLSEQ_START node.
1836 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1838 // Merge in the last call, to ensure that this call start after the last
1840 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1841 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1842 Tmp1, LastCALLSEQ_END);
1843 Tmp1 = LegalizeOp(Tmp1);
1846 // Do not try to legalize the target-specific arguments (#1+).
1847 if (Tmp1 != Node->getOperand(0)) {
1848 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1850 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1853 // Remember that the CALLSEQ_START is legalized.
1854 AddLegalizedOperand(Op.getValue(0), Result);
1855 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1856 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1858 // Now that the callseq_start and all of the non-call nodes above this call
1859 // sequence have been legalized, legalize the call itself. During this
1860 // process, no libcalls can/will be inserted, guaranteeing that no calls
1862 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1863 // Note that we are selecting this call!
1864 LastCALLSEQ_END = SDValue(CallEnd, 0);
1865 IsLegalizingCall = true;
1867 // Legalize the call, starting from the CALLSEQ_END.
1868 LegalizeOp(LastCALLSEQ_END);
1869 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1872 case ISD::CALLSEQ_END:
1873 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1874 // will cause this node to be legalized as well as handling libcalls right.
1875 if (LastCALLSEQ_END.getNode() != Node) {
1876 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1877 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1878 assert(I != LegalizedNodes.end() &&
1879 "Legalizing the call start should have legalized this node!");
1883 // Otherwise, the call start has been legalized and everything is going
1884 // according to plan. Just legalize ourselves normally here.
1885 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1886 // Do not try to legalize the target-specific arguments (#1+), except for
1887 // an optional flag input.
1888 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1889 if (Tmp1 != Node->getOperand(0)) {
1890 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1892 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1895 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1896 if (Tmp1 != Node->getOperand(0) ||
1897 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1898 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1901 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1904 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1905 // This finishes up call legalization.
1906 IsLegalizingCall = false;
1908 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1909 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1910 if (Node->getNumValues() == 2)
1911 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1912 return Result.getValue(Op.getResNo());
1913 case ISD::DYNAMIC_STACKALLOC: {
1914 MVT VT = Node->getValueType(0);
1915 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1916 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1917 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1918 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1920 Tmp1 = Result.getValue(0);
1921 Tmp2 = Result.getValue(1);
1922 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1923 default: assert(0 && "This action is not supported yet!");
1924 case TargetLowering::Expand: {
1925 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1926 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1927 " not tell us which reg is the stack pointer!");
1928 SDValue Chain = Tmp1.getOperand(0);
1930 // Chain the dynamic stack allocation so that it doesn't modify the stack
1931 // pointer when other instructions are using the stack.
1932 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1934 SDValue Size = Tmp2.getOperand(1);
1935 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1936 Chain = SP.getValue(1);
1937 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1938 unsigned StackAlign =
1939 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1940 if (Align > StackAlign)
1941 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1942 DAG.getConstant(-(uint64_t)Align, VT));
1943 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1944 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1946 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1947 DAG.getIntPtrConstant(0, true), SDValue());
1949 Tmp1 = LegalizeOp(Tmp1);
1950 Tmp2 = LegalizeOp(Tmp2);
1953 case TargetLowering::Custom:
1954 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1955 if (Tmp3.getNode()) {
1956 Tmp1 = LegalizeOp(Tmp3);
1957 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1960 case TargetLowering::Legal:
1963 // Since this op produce two values, make sure to remember that we
1964 // legalized both of them.
1965 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1966 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1967 return Op.getResNo() ? Tmp2 : Tmp1;
1969 case ISD::INLINEASM: {
1970 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1971 bool Changed = false;
1972 // Legalize all of the operands of the inline asm, in case they are nodes
1973 // that need to be expanded or something. Note we skip the asm string and
1974 // all of the TargetConstant flags.
1975 SDValue Op = LegalizeOp(Ops[0]);
1976 Changed = Op != Ops[0];
1979 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1980 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1981 unsigned NumVals = InlineAsm::
1982 getNumOperandRegisters(cast<ConstantSDNode>(Ops[i])->getZExtValue());
1983 for (++i; NumVals; ++i, --NumVals) {
1984 SDValue Op = LegalizeOp(Ops[i]);
1993 Op = LegalizeOp(Ops.back());
1994 Changed |= Op != Ops.back();
1999 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2001 // INLINE asm returns a chain and flag, make sure to add both to the map.
2002 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2003 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2004 return Result.getValue(Op.getResNo());
2007 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2008 // Ensure that libcalls are emitted before a branch.
2009 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2010 Tmp1 = LegalizeOp(Tmp1);
2011 LastCALLSEQ_END = DAG.getEntryNode();
2013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2016 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2017 // Ensure that libcalls are emitted before a branch.
2018 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2019 Tmp1 = LegalizeOp(Tmp1);
2020 LastCALLSEQ_END = DAG.getEntryNode();
2022 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2023 default: assert(0 && "Indirect target must be legal type (pointer)!");
2025 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2028 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2031 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2032 // Ensure that libcalls are emitted before a branch.
2033 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2034 Tmp1 = LegalizeOp(Tmp1);
2035 LastCALLSEQ_END = DAG.getEntryNode();
2037 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2038 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2040 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2041 default: assert(0 && "This action is not supported yet!");
2042 case TargetLowering::Legal: break;
2043 case TargetLowering::Custom:
2044 Tmp1 = TLI.LowerOperation(Result, DAG);
2045 if (Tmp1.getNode()) Result = Tmp1;
2047 case TargetLowering::Expand: {
2048 SDValue Chain = Result.getOperand(0);
2049 SDValue Table = Result.getOperand(1);
2050 SDValue Index = Result.getOperand(2);
2052 MVT PTy = TLI.getPointerTy();
2053 MachineFunction &MF = DAG.getMachineFunction();
2054 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2055 Index= DAG.getNode(ISD::MUL, dl, PTy,
2056 Index, DAG.getConstant(EntrySize, PTy));
2057 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2059 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2060 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2061 PseudoSourceValue::getJumpTable(), 0, MemVT);
2063 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2064 // For PIC, the sequence is:
2065 // BRIND(load(Jumptable + index) + RelocBase)
2066 // RelocBase can be JumpTable, GOT or some sort of global base.
2067 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2068 TLI.getPICJumpTableRelocBase(Table, DAG));
2070 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2075 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2076 // Ensure that libcalls are emitted before a return.
2077 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2078 Tmp1 = LegalizeOp(Tmp1);
2079 LastCALLSEQ_END = DAG.getEntryNode();
2081 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2082 case Expand: assert(0 && "It's impossible to expand bools");
2084 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2087 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2089 // The top bits of the promoted condition are not necessarily zero, ensure
2090 // that the value is properly zero extended.
2091 unsigned BitWidth = Tmp2.getValueSizeInBits();
2092 if (!DAG.MaskedValueIsZero(Tmp2,
2093 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2094 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2099 // Basic block destination (Op#2) is always legal.
2100 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2102 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2103 default: assert(0 && "This action is not supported yet!");
2104 case TargetLowering::Legal: break;
2105 case TargetLowering::Custom:
2106 Tmp1 = TLI.LowerOperation(Result, DAG);
2107 if (Tmp1.getNode()) Result = Tmp1;
2109 case TargetLowering::Expand:
2110 // Expand brcond's setcc into its constituent parts and create a BR_CC
2112 if (Tmp2.getOpcode() == ISD::SETCC) {
2113 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2114 Tmp1, Tmp2.getOperand(2),
2115 Tmp2.getOperand(0), Tmp2.getOperand(1),
2116 Node->getOperand(2));
2118 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2119 DAG.getCondCode(ISD::SETNE), Tmp2,
2120 DAG.getConstant(0, Tmp2.getValueType()),
2121 Node->getOperand(2));
2127 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2128 // Ensure that libcalls are emitted before a branch.
2129 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2130 Tmp1 = LegalizeOp(Tmp1);
2131 Tmp2 = Node->getOperand(2); // LHS
2132 Tmp3 = Node->getOperand(3); // RHS
2133 Tmp4 = Node->getOperand(1); // CC
2135 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2136 Tmp2, Tmp3, Tmp4, dl);
2137 LastCALLSEQ_END = DAG.getEntryNode();
2139 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2140 // the LHS is a legal SETCC itself. In this case, we need to compare
2141 // the result against zero to select between true and false values.
2142 if (Tmp3.getNode() == 0) {
2143 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2144 Tmp4 = DAG.getCondCode(ISD::SETNE);
2147 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2148 Node->getOperand(4));
2150 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2151 default: assert(0 && "Unexpected action for BR_CC!");
2152 case TargetLowering::Legal: break;
2153 case TargetLowering::Custom:
2154 Tmp4 = TLI.LowerOperation(Result, DAG);
2155 if (Tmp4.getNode()) Result = Tmp4;
2160 LoadSDNode *LD = cast<LoadSDNode>(Node);
2161 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2162 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2164 ISD::LoadExtType ExtType = LD->getExtensionType();
2165 if (ExtType == ISD::NON_EXTLOAD) {
2166 MVT VT = Node->getValueType(0);
2167 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2168 Tmp3 = Result.getValue(0);
2169 Tmp4 = Result.getValue(1);
2171 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2172 default: assert(0 && "This action is not supported yet!");
2173 case TargetLowering::Legal:
2174 // If this is an unaligned load and the target doesn't support it,
2176 if (!TLI.allowsUnalignedMemoryAccesses()) {
2177 unsigned ABIAlignment = TLI.getTargetData()->
2178 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2179 if (LD->getAlignment() < ABIAlignment){
2180 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2182 Tmp3 = Result.getOperand(0);
2183 Tmp4 = Result.getOperand(1);
2184 Tmp3 = LegalizeOp(Tmp3);
2185 Tmp4 = LegalizeOp(Tmp4);
2189 case TargetLowering::Custom:
2190 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2191 if (Tmp1.getNode()) {
2192 Tmp3 = LegalizeOp(Tmp1);
2193 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2196 case TargetLowering::Promote: {
2197 // Only promote a load of vector type to another.
2198 assert(VT.isVector() && "Cannot promote this load!");
2199 // Change base type to a different vector type.
2200 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2202 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2203 LD->getSrcValueOffset(),
2204 LD->isVolatile(), LD->getAlignment());
2205 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
2206 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2210 // Since loads produce two values, make sure to remember that we
2211 // legalized both of them.
2212 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2213 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2214 return Op.getResNo() ? Tmp4 : Tmp3;
2216 MVT SrcVT = LD->getMemoryVT();
2217 unsigned SrcWidth = SrcVT.getSizeInBits();
2218 int SVOffset = LD->getSrcValueOffset();
2219 unsigned Alignment = LD->getAlignment();
2220 bool isVolatile = LD->isVolatile();
2222 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2223 // Some targets pretend to have an i1 loading operation, and actually
2224 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2225 // bits are guaranteed to be zero; it helps the optimizers understand
2226 // that these bits are zero. It is also useful for EXTLOAD, since it
2227 // tells the optimizers that those bits are undefined. It would be
2228 // nice to have an effective generic way of getting these benefits...
2229 // Until such a way is found, don't insist on promoting i1 here.
2230 (SrcVT != MVT::i1 ||
2231 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2232 // Promote to a byte-sized load if not loading an integral number of
2233 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2234 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2235 MVT NVT = MVT::getIntegerVT(NewWidth);
2238 // The extra bits are guaranteed to be zero, since we stored them that
2239 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2241 ISD::LoadExtType NewExtType =
2242 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2244 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2245 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2246 NVT, isVolatile, Alignment);
2248 Ch = Result.getValue(1); // The chain.
2250 if (ExtType == ISD::SEXTLOAD)
2251 // Having the top bits zero doesn't help when sign extending.
2252 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2253 Result.getValueType(),
2254 Result, DAG.getValueType(SrcVT));
2255 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2256 // All the top bits are guaranteed to be zero - inform the optimizers.
2257 Result = DAG.getNode(ISD::AssertZext, dl,
2258 Result.getValueType(), Result,
2259 DAG.getValueType(SrcVT));
2261 Tmp1 = LegalizeOp(Result);
2262 Tmp2 = LegalizeOp(Ch);
2263 } else if (SrcWidth & (SrcWidth - 1)) {
2264 // If not loading a power-of-2 number of bits, expand as two loads.
2265 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2266 "Unsupported extload!");
2267 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2268 assert(RoundWidth < SrcWidth);
2269 unsigned ExtraWidth = SrcWidth - RoundWidth;
2270 assert(ExtraWidth < RoundWidth);
2271 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2272 "Load size not an integral number of bytes!");
2273 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2274 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2276 unsigned IncrementSize;
2278 if (TLI.isLittleEndian()) {
2279 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2280 // Load the bottom RoundWidth bits.
2281 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2282 Node->getValueType(0), Tmp1, Tmp2,
2283 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2286 // Load the remaining ExtraWidth bits.
2287 IncrementSize = RoundWidth / 8;
2288 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2289 DAG.getIntPtrConstant(IncrementSize));
2290 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2291 LD->getSrcValue(), SVOffset + IncrementSize,
2292 ExtraVT, isVolatile,
2293 MinAlign(Alignment, IncrementSize));
2295 // Build a factor node to remember that this load is independent of the
2297 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2300 // Move the top bits to the right place.
2301 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2302 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2304 // Join the hi and lo parts.
2305 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2307 // Big endian - avoid unaligned loads.
2308 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2309 // Load the top RoundWidth bits.
2310 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2311 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2314 // Load the remaining ExtraWidth bits.
2315 IncrementSize = RoundWidth / 8;
2316 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2317 DAG.getIntPtrConstant(IncrementSize));
2318 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2319 Node->getValueType(0), Tmp1, Tmp2,
2320 LD->getSrcValue(), SVOffset + IncrementSize,
2321 ExtraVT, isVolatile,
2322 MinAlign(Alignment, IncrementSize));
2324 // Build a factor node to remember that this load is independent of the
2326 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2329 // Move the top bits to the right place.
2330 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2331 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2333 // Join the hi and lo parts.
2334 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2337 Tmp1 = LegalizeOp(Result);
2338 Tmp2 = LegalizeOp(Ch);
2340 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2341 default: assert(0 && "This action is not supported yet!");
2342 case TargetLowering::Custom:
2345 case TargetLowering::Legal:
2346 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2347 Tmp1 = Result.getValue(0);
2348 Tmp2 = Result.getValue(1);
2351 Tmp3 = TLI.LowerOperation(Result, DAG);
2352 if (Tmp3.getNode()) {
2353 Tmp1 = LegalizeOp(Tmp3);
2354 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2357 // If this is an unaligned load and the target doesn't support it,
2359 if (!TLI.allowsUnalignedMemoryAccesses()) {
2360 unsigned ABIAlignment = TLI.getTargetData()->
2361 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2362 if (LD->getAlignment() < ABIAlignment){
2363 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2365 Tmp1 = Result.getOperand(0);
2366 Tmp2 = Result.getOperand(1);
2367 Tmp1 = LegalizeOp(Tmp1);
2368 Tmp2 = LegalizeOp(Tmp2);
2373 case TargetLowering::Expand:
2374 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2375 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2376 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2377 LD->getSrcValueOffset(),
2378 LD->isVolatile(), LD->getAlignment());
2379 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2380 Node->getValueType(0), Load);
2381 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2382 Tmp2 = LegalizeOp(Load.getValue(1));
2385 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2386 // Turn the unsupported load into an EXTLOAD followed by an explicit
2387 // zero/sign extend inreg.
2388 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2389 Tmp1, Tmp2, LD->getSrcValue(),
2390 LD->getSrcValueOffset(), SrcVT,
2391 LD->isVolatile(), LD->getAlignment());
2393 if (ExtType == ISD::SEXTLOAD)
2394 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2395 Result.getValueType(),
2396 Result, DAG.getValueType(SrcVT));
2398 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2399 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2400 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2405 // Since loads produce two values, make sure to remember that we legalized
2407 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2408 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2409 return Op.getResNo() ? Tmp2 : Tmp1;
2412 case ISD::EXTRACT_ELEMENT: {
2413 MVT OpTy = Node->getOperand(0).getValueType();
2414 switch (getTypeAction(OpTy)) {
2415 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2417 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2419 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2420 DAG.getConstant(OpTy.getSizeInBits()/2,
2421 TLI.getShiftAmountTy()));
2422 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2425 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2426 Node->getOperand(0));
2430 // Get both the low and high parts.
2431 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2432 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2433 Result = Tmp2; // 1 -> Hi
2435 Result = Tmp1; // 0 -> Lo
2441 case ISD::CopyToReg:
2442 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2444 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2445 "Register type must be legal!");
2446 // Legalize the incoming value (must be a legal type).
2447 Tmp2 = LegalizeOp(Node->getOperand(2));
2448 if (Node->getNumValues() == 1) {
2449 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2451 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2452 if (Node->getNumOperands() == 4) {
2453 Tmp3 = LegalizeOp(Node->getOperand(3));
2454 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2457 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2460 // Since this produces two values, make sure to remember that we legalized
2462 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2463 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2469 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2471 // Ensure that libcalls are emitted before a return.
2472 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2473 Tmp1 = LegalizeOp(Tmp1);
2474 LastCALLSEQ_END = DAG.getEntryNode();
2476 switch (Node->getNumOperands()) {
2478 Tmp2 = Node->getOperand(1);
2479 Tmp3 = Node->getOperand(2); // Signness
2480 switch (getTypeAction(Tmp2.getValueType())) {
2482 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2485 if (!Tmp2.getValueType().isVector()) {
2487 ExpandOp(Tmp2, Lo, Hi);
2489 // Big endian systems want the hi reg first.
2490 if (TLI.isBigEndian())
2494 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2495 Tmp1, Lo, Tmp3, Hi,Tmp3);
2497 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2498 Result = LegalizeOp(Result);
2500 SDNode *InVal = Tmp2.getNode();
2501 int InIx = Tmp2.getResNo();
2502 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2503 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2505 // Figure out if there is a simple type corresponding to this Vector
2506 // type. If so, convert to the vector type.
2507 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2508 if (TLI.isTypeLegal(TVT)) {
2509 // Turn this into a return of the vector type.
2510 Tmp2 = LegalizeOp(Tmp2);
2511 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2512 } else if (NumElems == 1) {
2513 // Turn this into a return of the scalar type.
2514 Tmp2 = ScalarizeVectorOp(Tmp2);
2515 Tmp2 = LegalizeOp(Tmp2);
2516 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2518 // FIXME: Returns of gcc generic vectors smaller than a legal type
2519 // should be returned in integer registers!
2521 // The scalarized value type may not be legal, e.g. it might require
2522 // promotion or expansion. Relegalize the return.
2523 Result = LegalizeOp(Result);
2525 // FIXME: Returns of gcc generic vectors larger than a legal vector
2526 // type should be returned by reference!
2528 SplitVectorOp(Tmp2, Lo, Hi);
2529 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2530 Tmp1, Lo, Tmp3, Hi,Tmp3);
2531 Result = LegalizeOp(Result);
2536 Tmp2 = PromoteOp(Node->getOperand(1));
2537 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2538 Result = LegalizeOp(Result);
2543 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2545 default: { // ret <values>
2546 SmallVector<SDValue, 8> NewValues;
2547 NewValues.push_back(Tmp1);
2548 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2549 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2551 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2552 NewValues.push_back(Node->getOperand(i+1));
2556 assert(!Node->getOperand(i).getValueType().isExtended() &&
2557 "FIXME: TODO: implement returning non-legal vector types!");
2558 ExpandOp(Node->getOperand(i), Lo, Hi);
2559 NewValues.push_back(Lo);
2560 NewValues.push_back(Node->getOperand(i+1));
2562 NewValues.push_back(Hi);
2563 NewValues.push_back(Node->getOperand(i+1));
2568 assert(0 && "Can't promote multiple return value yet!");
2571 if (NewValues.size() == Node->getNumOperands())
2572 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2574 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2575 &NewValues[0], NewValues.size());
2580 if (Result.getOpcode() == ISD::RET) {
2581 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2582 default: assert(0 && "This action is not supported yet!");
2583 case TargetLowering::Legal: break;
2584 case TargetLowering::Custom:
2585 Tmp1 = TLI.LowerOperation(Result, DAG);
2586 if (Tmp1.getNode()) Result = Tmp1;
2592 StoreSDNode *ST = cast<StoreSDNode>(Node);
2593 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2594 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2595 int SVOffset = ST->getSrcValueOffset();
2596 unsigned Alignment = ST->getAlignment();
2597 bool isVolatile = ST->isVolatile();
2599 if (!ST->isTruncatingStore()) {
2600 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2601 // FIXME: We shouldn't do this for TargetConstantFP's.
2602 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2603 // to phase ordering between legalized code and the dag combiner. This
2604 // probably means that we need to integrate dag combiner and legalizer
2606 // We generally can't do this one for long doubles.
2607 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2608 if (CFP->getValueType(0) == MVT::f32 &&
2609 getTypeAction(MVT::i32) == Legal) {
2610 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2611 bitcastToAPInt().zextOrTrunc(32),
2613 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2614 SVOffset, isVolatile, Alignment);
2616 } else if (CFP->getValueType(0) == MVT::f64) {
2617 // If this target supports 64-bit registers, do a single 64-bit store.
2618 if (getTypeAction(MVT::i64) == Legal) {
2619 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2620 zextOrTrunc(64), MVT::i64);
2621 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2622 SVOffset, isVolatile, Alignment);
2624 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2625 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2626 // stores. If the target supports neither 32- nor 64-bits, this
2627 // xform is certainly not worth it.
2628 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2629 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2630 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2631 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2633 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2634 SVOffset, isVolatile, Alignment);
2635 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2636 DAG.getIntPtrConstant(4));
2637 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2638 isVolatile, MinAlign(Alignment, 4U));
2640 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2646 switch (getTypeAction(ST->getMemoryVT())) {
2648 Tmp3 = LegalizeOp(ST->getValue());
2649 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2652 MVT VT = Tmp3.getValueType();
2653 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2654 default: assert(0 && "This action is not supported yet!");
2655 case TargetLowering::Legal:
2656 // If this is an unaligned store and the target doesn't support it,
2658 if (!TLI.allowsUnalignedMemoryAccesses()) {
2659 unsigned ABIAlignment = TLI.getTargetData()->
2660 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2661 if (ST->getAlignment() < ABIAlignment)
2662 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2666 case TargetLowering::Custom:
2667 Tmp1 = TLI.LowerOperation(Result, DAG);
2668 if (Tmp1.getNode()) Result = Tmp1;
2670 case TargetLowering::Promote:
2671 assert(VT.isVector() && "Unknown legal promote case!");
2672 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2673 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2674 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2675 ST->getSrcValue(), SVOffset, isVolatile,
2682 if (!ST->getMemoryVT().isVector()) {
2683 // Truncate the value and store the result.
2684 Tmp3 = PromoteOp(ST->getValue());
2685 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2686 SVOffset, ST->getMemoryVT(),
2687 isVolatile, Alignment);
2690 // Fall thru to expand for vector
2692 unsigned IncrementSize = 0;
2695 // If this is a vector type, then we have to calculate the increment as
2696 // the product of the element size in bytes, and the number of elements
2697 // in the high half of the vector.
2698 if (ST->getValue().getValueType().isVector()) {
2699 SDNode *InVal = ST->getValue().getNode();
2700 int InIx = ST->getValue().getResNo();
2701 MVT InVT = InVal->getValueType(InIx);
2702 unsigned NumElems = InVT.getVectorNumElements();
2703 MVT EVT = InVT.getVectorElementType();
2705 // Figure out if there is a simple type corresponding to this Vector
2706 // type. If so, convert to the vector type.
2707 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2708 if (TLI.isTypeLegal(TVT)) {
2709 // Turn this into a normal store of the vector type.
2710 Tmp3 = LegalizeOp(ST->getValue());
2711 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2712 SVOffset, isVolatile, Alignment);
2713 Result = LegalizeOp(Result);
2715 } else if (NumElems == 1) {
2716 // Turn this into a normal store of the scalar type.
2717 Tmp3 = ScalarizeVectorOp(ST->getValue());
2718 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2719 SVOffset, isVolatile, Alignment);
2720 // The scalarized value type may not be legal, e.g. it might require
2721 // promotion or expansion. Relegalize the scalar store.
2722 Result = LegalizeOp(Result);
2725 // Check if we have widen this node with another value
2726 std::map<SDValue, SDValue>::iterator I =
2727 WidenNodes.find(ST->getValue());
2728 if (I != WidenNodes.end()) {
2729 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2733 SplitVectorOp(ST->getValue(), Lo, Hi);
2734 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2735 EVT.getSizeInBits()/8;
2739 ExpandOp(ST->getValue(), Lo, Hi);
2740 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2742 if (Hi.getNode() && TLI.isBigEndian())
2746 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2747 SVOffset, isVolatile, Alignment);
2749 if (Hi.getNode() == NULL) {
2750 // Must be int <-> float one-to-one expansion.
2755 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2756 DAG.getIntPtrConstant(IncrementSize));
2757 assert(isTypeLegal(Tmp2.getValueType()) &&
2758 "Pointers must be legal!");
2759 SVOffset += IncrementSize;
2760 Alignment = MinAlign(Alignment, IncrementSize);
2761 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2762 SVOffset, isVolatile, Alignment);
2763 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2768 switch (getTypeAction(ST->getValue().getValueType())) {
2770 Tmp3 = LegalizeOp(ST->getValue());
2773 if (!ST->getValue().getValueType().isVector()) {
2774 // We can promote the value, the truncstore will still take care of it.
2775 Tmp3 = PromoteOp(ST->getValue());
2778 // Vector case falls through to expand
2780 // Just store the low part. This may become a non-trunc store, so make
2781 // sure to use getTruncStore, not UpdateNodeOperands below.
2782 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2783 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2784 SVOffset, MVT::i8, isVolatile, Alignment);
2787 MVT StVT = ST->getMemoryVT();
2788 unsigned StWidth = StVT.getSizeInBits();
2790 if (StWidth != StVT.getStoreSizeInBits()) {
2791 // Promote to a byte-sized store with upper bits zero if not
2792 // storing an integral number of bytes. For example, promote
2793 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2794 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2795 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2796 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2797 SVOffset, NVT, isVolatile, Alignment);
2798 } else if (StWidth & (StWidth - 1)) {
2799 // If not storing a power-of-2 number of bits, expand as two stores.
2800 assert(StVT.isExtended() && !StVT.isVector() &&
2801 "Unsupported truncstore!");
2802 unsigned RoundWidth = 1 << Log2_32(StWidth);
2803 assert(RoundWidth < StWidth);
2804 unsigned ExtraWidth = StWidth - RoundWidth;
2805 assert(ExtraWidth < RoundWidth);
2806 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2807 "Store size not an integral number of bytes!");
2808 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2809 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2811 unsigned IncrementSize;
2813 if (TLI.isLittleEndian()) {
2814 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2815 // Store the bottom RoundWidth bits.
2816 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2818 isVolatile, Alignment);
2820 // Store the remaining ExtraWidth bits.
2821 IncrementSize = RoundWidth / 8;
2822 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2823 DAG.getIntPtrConstant(IncrementSize));
2824 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2825 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2826 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2827 SVOffset + IncrementSize, ExtraVT, isVolatile,
2828 MinAlign(Alignment, IncrementSize));
2830 // Big endian - avoid unaligned stores.
2831 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2832 // Store the top RoundWidth bits.
2833 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2834 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2835 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2836 SVOffset, RoundVT, isVolatile, Alignment);
2838 // Store the remaining ExtraWidth bits.
2839 IncrementSize = RoundWidth / 8;
2840 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2841 DAG.getIntPtrConstant(IncrementSize));
2842 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2843 SVOffset + IncrementSize, ExtraVT, isVolatile,
2844 MinAlign(Alignment, IncrementSize));
2847 // The order of the stores doesn't matter.
2848 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2850 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2851 Tmp2 != ST->getBasePtr())
2852 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2855 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2856 default: assert(0 && "This action is not supported yet!");
2857 case TargetLowering::Legal:
2858 // If this is an unaligned store and the target doesn't support it,
2860 if (!TLI.allowsUnalignedMemoryAccesses()) {
2861 unsigned ABIAlignment = TLI.getTargetData()->
2862 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2863 if (ST->getAlignment() < ABIAlignment)
2864 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2868 case TargetLowering::Custom:
2869 Result = TLI.LowerOperation(Result, DAG);
2872 // TRUNCSTORE:i16 i32 -> STORE i16
2873 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2874 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2875 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2876 SVOffset, isVolatile, Alignment);
2884 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2885 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2887 case ISD::STACKSAVE:
2888 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2889 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2890 Tmp1 = Result.getValue(0);
2891 Tmp2 = Result.getValue(1);
2893 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2894 default: assert(0 && "This action is not supported yet!");
2895 case TargetLowering::Legal: break;
2896 case TargetLowering::Custom:
2897 Tmp3 = TLI.LowerOperation(Result, DAG);
2898 if (Tmp3.getNode()) {
2899 Tmp1 = LegalizeOp(Tmp3);
2900 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2903 case TargetLowering::Expand:
2904 // Expand to CopyFromReg if the target set
2905 // StackPointerRegisterToSaveRestore.
2906 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2907 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
2908 Node->getValueType(0));
2909 Tmp2 = Tmp1.getValue(1);
2911 Tmp1 = DAG.getUNDEF(Node->getValueType(0));
2912 Tmp2 = Node->getOperand(0);
2917 // Since stacksave produce two values, make sure to remember that we
2918 // legalized both of them.
2919 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2920 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2921 return Op.getResNo() ? Tmp2 : Tmp1;
2923 case ISD::STACKRESTORE:
2924 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2925 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2926 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2928 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2929 default: assert(0 && "This action is not supported yet!");
2930 case TargetLowering::Legal: break;
2931 case TargetLowering::Custom:
2932 Tmp1 = TLI.LowerOperation(Result, DAG);
2933 if (Tmp1.getNode()) Result = Tmp1;
2935 case TargetLowering::Expand:
2936 // Expand to CopyToReg if the target set
2937 // StackPointerRegisterToSaveRestore.
2938 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2939 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
2947 case ISD::READCYCLECOUNTER:
2948 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2949 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2950 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2951 Node->getValueType(0))) {
2952 default: assert(0 && "This action is not supported yet!");
2953 case TargetLowering::Legal:
2954 Tmp1 = Result.getValue(0);
2955 Tmp2 = Result.getValue(1);
2957 case TargetLowering::Custom:
2958 Result = TLI.LowerOperation(Result, DAG);
2959 Tmp1 = LegalizeOp(Result.getValue(0));
2960 Tmp2 = LegalizeOp(Result.getValue(1));
2964 // Since rdcc produce two values, make sure to remember that we legalized
2966 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2967 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2971 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2972 case Expand: assert(0 && "It's impossible to expand bools");
2974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2977 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2978 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2979 // Make sure the condition is either zero or one.
2980 unsigned BitWidth = Tmp1.getValueSizeInBits();
2981 if (!DAG.MaskedValueIsZero(Tmp1,
2982 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2983 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2987 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2988 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2990 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2992 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2993 default: assert(0 && "This action is not supported yet!");
2994 case TargetLowering::Legal: break;
2995 case TargetLowering::Custom: {
2996 Tmp1 = TLI.LowerOperation(Result, DAG);
2997 if (Tmp1.getNode()) Result = Tmp1;
3000 case TargetLowering::Expand:
3001 if (Tmp1.getOpcode() == ISD::SETCC) {
3002 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3004 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3006 Result = DAG.getSelectCC(dl, Tmp1,
3007 DAG.getConstant(0, Tmp1.getValueType()),
3008 Tmp2, Tmp3, ISD::SETNE);
3011 case TargetLowering::Promote: {
3013 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
3014 unsigned ExtOp, TruncOp;
3015 if (Tmp2.getValueType().isVector()) {
3016 ExtOp = ISD::BIT_CONVERT;
3017 TruncOp = ISD::BIT_CONVERT;
3018 } else if (Tmp2.getValueType().isInteger()) {
3019 ExtOp = ISD::ANY_EXTEND;
3020 TruncOp = ISD::TRUNCATE;
3022 ExtOp = ISD::FP_EXTEND;
3023 TruncOp = ISD::FP_ROUND;
3025 // Promote each of the values to the new type.
3026 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
3027 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
3028 // Perform the larger operation, then round down.
3029 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
3030 if (TruncOp != ISD::FP_ROUND)
3031 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
3033 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
3034 DAG.getIntPtrConstant(0));
3039 case ISD::SELECT_CC: {
3040 Tmp1 = Node->getOperand(0); // LHS
3041 Tmp2 = Node->getOperand(1); // RHS
3042 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3043 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3044 SDValue CC = Node->getOperand(4);
3046 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3047 Tmp1, Tmp2, CC, dl);
3049 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3050 // the LHS is a legal SETCC itself. In this case, we need to compare
3051 // the result against zero to select between true and false values.
3052 if (Tmp2.getNode() == 0) {
3053 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3054 CC = DAG.getCondCode(ISD::SETNE);
3056 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3058 // Everything is legal, see if we should expand this op or something.
3059 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3060 default: assert(0 && "This action is not supported yet!");
3061 case TargetLowering::Legal: break;
3062 case TargetLowering::Custom:
3063 Tmp1 = TLI.LowerOperation(Result, DAG);
3064 if (Tmp1.getNode()) Result = Tmp1;
3070 Tmp1 = Node->getOperand(0);
3071 Tmp2 = Node->getOperand(1);
3072 Tmp3 = Node->getOperand(2);
3073 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3075 // If we had to Expand the SetCC operands into a SELECT node, then it may
3076 // not always be possible to return a true LHS & RHS. In this case, just
3077 // return the value we legalized, returned in the LHS
3078 if (Tmp2.getNode() == 0) {
3083 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3084 default: assert(0 && "Cannot handle this action for SETCC yet!");
3085 case TargetLowering::Custom:
3088 case TargetLowering::Legal:
3089 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3091 Tmp4 = TLI.LowerOperation(Result, DAG);
3092 if (Tmp4.getNode()) Result = Tmp4;
3095 case TargetLowering::Promote: {
3096 // First step, figure out the appropriate operation to use.
3097 // Allow SETCC to not be supported for all legal data types
3098 // Mostly this targets FP
3099 MVT NewInTy = Node->getOperand(0).getValueType();
3100 MVT OldVT = NewInTy; OldVT = OldVT;
3102 // Scan for the appropriate larger type to use.
3104 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3106 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3107 "Fell off of the edge of the integer world");
3108 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3109 "Fell off of the edge of the floating point world");
3111 // If the target supports SETCC of this type, use it.
3112 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3115 if (NewInTy.isInteger())
3116 assert(0 && "Cannot promote Legal Integer SETCC yet");
3118 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3119 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3121 Tmp1 = LegalizeOp(Tmp1);
3122 Tmp2 = LegalizeOp(Tmp2);
3123 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3124 Result = LegalizeOp(Result);
3127 case TargetLowering::Expand:
3128 // Expand a setcc node into a select_cc of the same condition, lhs, and
3129 // rhs that selects between const 1 (true) and const 0 (false).
3130 MVT VT = Node->getValueType(0);
3131 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3132 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3138 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3139 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3140 SDValue CC = Node->getOperand(2);
3142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3144 // Everything is legal, see if we should expand this op or something.
3145 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3146 default: assert(0 && "This action is not supported yet!");
3147 case TargetLowering::Legal: break;
3148 case TargetLowering::Custom:
3149 Tmp1 = TLI.LowerOperation(Result, DAG);
3150 if (Tmp1.getNode()) Result = Tmp1;
3152 case TargetLowering::Expand: {
3153 // Unroll into a nasty set of scalar code for now.
3154 MVT VT = Node->getValueType(0);
3155 unsigned NumElems = VT.getVectorNumElements();
3156 MVT EltVT = VT.getVectorElementType();
3157 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3158 SmallVector<SDValue, 8> Ops(NumElems);
3159 for (unsigned i = 0; i < NumElems; ++i) {
3160 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3161 Tmp1, DAG.getIntPtrConstant(i));
3162 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3163 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3165 DAG.getIntPtrConstant(i)),
3167 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
3168 APInt::getAllOnesValue(EltVT.getSizeInBits()),
3169 EltVT), DAG.getConstant(0, EltVT));
3171 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
3178 case ISD::SHL_PARTS:
3179 case ISD::SRA_PARTS:
3180 case ISD::SRL_PARTS: {
3181 SmallVector<SDValue, 8> Ops;
3182 bool Changed = false;
3183 unsigned N = Node->getNumOperands();
3184 for (unsigned i = 0; i + 1 < N; ++i) {
3185 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3186 Changed |= Ops.back() != Node->getOperand(i);
3188 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3189 Changed |= Ops.back() != Node->getOperand(N-1);
3191 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3193 switch (TLI.getOperationAction(Node->getOpcode(),
3194 Node->getValueType(0))) {
3195 default: assert(0 && "This action is not supported yet!");
3196 case TargetLowering::Legal: break;
3197 case TargetLowering::Custom:
3198 Tmp1 = TLI.LowerOperation(Result, DAG);
3199 if (Tmp1.getNode()) {
3200 SDValue Tmp2, RetVal(0, 0);
3201 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3202 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3203 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3204 if (i == Op.getResNo())
3207 assert(RetVal.getNode() && "Illegal result number");
3213 // Since these produce multiple values, make sure to remember that we
3214 // legalized all of them.
3215 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3216 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3217 return Result.getValue(Op.getResNo());
3239 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3240 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3242 if ((Node->getOpcode() == ISD::SHL ||
3243 Node->getOpcode() == ISD::SRL ||
3244 Node->getOpcode() == ISD::SRA) &&
3245 !Node->getValueType(0).isVector())
3246 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3248 switch (getTypeAction(Tmp2.getValueType())) {
3249 case Expand: assert(0 && "Not possible");
3251 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3254 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3258 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3260 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3261 default: assert(0 && "BinOp legalize operation not supported");
3262 case TargetLowering::Legal: break;
3263 case TargetLowering::Custom:
3264 Tmp1 = TLI.LowerOperation(Result, DAG);
3265 if (Tmp1.getNode()) {
3269 // Fall through if the custom lower can't deal with the operation
3270 case TargetLowering::Expand: {
3271 MVT VT = Op.getValueType();
3273 // See if multiply or divide can be lowered using two-result operations.
3274 SDVTList VTs = DAG.getVTList(VT, VT);
3275 if (Node->getOpcode() == ISD::MUL) {
3276 // We just need the low half of the multiply; try both the signed
3277 // and unsigned forms. If the target supports both SMUL_LOHI and
3278 // UMUL_LOHI, form a preference by checking which forms of plain
3279 // MULH it supports.
3280 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3281 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3282 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3283 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3284 unsigned OpToUse = 0;
3285 if (HasSMUL_LOHI && !HasMULHS) {
3286 OpToUse = ISD::SMUL_LOHI;
3287 } else if (HasUMUL_LOHI && !HasMULHU) {
3288 OpToUse = ISD::UMUL_LOHI;
3289 } else if (HasSMUL_LOHI) {
3290 OpToUse = ISD::SMUL_LOHI;
3291 } else if (HasUMUL_LOHI) {
3292 OpToUse = ISD::UMUL_LOHI;
3295 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3300 if (Node->getOpcode() == ISD::MULHS &&
3301 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3302 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3303 VTs, Tmp1, Tmp2).getNode(),
3307 if (Node->getOpcode() == ISD::MULHU &&
3308 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3309 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3310 VTs, Tmp1, Tmp2).getNode(),
3314 if (Node->getOpcode() == ISD::SDIV &&
3315 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3316 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3317 VTs, Tmp1, Tmp2).getNode(),
3321 if (Node->getOpcode() == ISD::UDIV &&
3322 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3323 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3324 VTs, Tmp1, Tmp2).getNode(),
3329 // Check to see if we have a libcall for this operator.
3330 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3331 bool isSigned = false;
3332 switch (Node->getOpcode()) {
3335 if (VT == MVT::i32) {
3336 LC = Node->getOpcode() == ISD::UDIV
3337 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3338 isSigned = Node->getOpcode() == ISD::SDIV;
3343 LC = RTLIB::MUL_I32;
3344 else if (VT == MVT::i64)
3345 LC = RTLIB::MUL_I64;
3348 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3349 RTLIB::POW_PPCF128);
3352 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3353 RTLIB::DIV_PPCF128);
3357 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3359 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3363 assert(Node->getValueType(0).isVector() &&
3364 "Cannot expand this binary operator!");
3365 // Expand the operation into a bunch of nasty scalar code.
3366 Result = LegalizeOp(UnrollVectorOp(Op));
3369 case TargetLowering::Promote: {
3370 switch (Node->getOpcode()) {
3371 default: assert(0 && "Do not know how to promote this BinOp!");
3375 MVT OVT = Node->getValueType(0);
3376 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3377 assert(OVT.isVector() && "Cannot promote this BinOp!");
3378 // Bit convert each of the values to the new type.
3379 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3380 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3381 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3382 // Bit convert the result back the original type.
3383 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3391 case ISD::SMUL_LOHI:
3392 case ISD::UMUL_LOHI:
3395 // These nodes will only be produced by target-specific lowering, so
3396 // they shouldn't be here if they aren't legal.
3397 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3398 "This must be legal!");
3400 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3401 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3402 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3405 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3406 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3407 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3408 case Expand: assert(0 && "Not possible");
3410 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3413 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3417 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3419 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3420 default: assert(0 && "Operation not supported");
3421 case TargetLowering::Custom:
3422 Tmp1 = TLI.LowerOperation(Result, DAG);
3423 if (Tmp1.getNode()) Result = Tmp1;
3425 case TargetLowering::Legal: break;
3426 case TargetLowering::Expand: {
3427 // If this target supports fabs/fneg natively and select is cheap,
3428 // do this efficiently.
3429 if (!TLI.isSelectExpensive() &&
3430 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3431 TargetLowering::Legal &&
3432 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3433 TargetLowering::Legal) {
3434 // Get the sign bit of the RHS.
3436 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3437 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3438 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3439 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3440 // Get the absolute value of the result.
3441 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3442 // Select between the nabs and abs value based on the sign bit of
3444 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3445 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
3448 Result = LegalizeOp(Result);
3452 // Otherwise, do bitwise ops!
3454 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3455 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3456 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3457 Result = LegalizeOp(Result);
3465 Tmp1 = LegalizeOp(Node->getOperand(0));
3466 Tmp2 = LegalizeOp(Node->getOperand(1));
3467 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3468 Tmp3 = Result.getValue(0);
3469 Tmp4 = Result.getValue(1);
3471 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3472 default: assert(0 && "This action is not supported yet!");
3473 case TargetLowering::Legal:
3475 case TargetLowering::Custom:
3476 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3477 if (Tmp1.getNode() != NULL) {
3478 Tmp3 = LegalizeOp(Tmp1);
3479 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3483 // Since this produces two values, make sure to remember that we legalized
3485 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3486 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3487 return Op.getResNo() ? Tmp4 : Tmp3;
3491 Tmp1 = LegalizeOp(Node->getOperand(0));
3492 Tmp2 = LegalizeOp(Node->getOperand(1));
3493 Tmp3 = LegalizeOp(Node->getOperand(2));
3494 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3495 Tmp3 = Result.getValue(0);
3496 Tmp4 = Result.getValue(1);
3498 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3499 default: assert(0 && "This action is not supported yet!");
3500 case TargetLowering::Legal:
3502 case TargetLowering::Custom:
3503 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3504 if (Tmp1.getNode() != NULL) {
3505 Tmp3 = LegalizeOp(Tmp1);
3506 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3510 // Since this produces two values, make sure to remember that we legalized
3512 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3513 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3514 return Op.getResNo() ? Tmp4 : Tmp3;
3516 case ISD::BUILD_PAIR: {
3517 MVT PairTy = Node->getValueType(0);
3518 // TODO: handle the case where the Lo and Hi operands are not of legal type
3519 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3520 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3521 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3522 case TargetLowering::Promote:
3523 case TargetLowering::Custom:
3524 assert(0 && "Cannot promote/custom this yet!");
3525 case TargetLowering::Legal:
3526 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3527 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3529 case TargetLowering::Expand:
3530 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3531 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3532 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3533 DAG.getConstant(PairTy.getSizeInBits()/2,
3534 TLI.getShiftAmountTy()));
3535 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3544 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3545 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3547 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3548 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3549 case TargetLowering::Custom:
3552 case TargetLowering::Legal:
3553 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3555 Tmp1 = TLI.LowerOperation(Result, DAG);
3556 if (Tmp1.getNode()) Result = Tmp1;
3559 case TargetLowering::Expand: {
3560 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3561 bool isSigned = DivOpc == ISD::SDIV;
3562 MVT VT = Node->getValueType(0);
3564 // See if remainder can be lowered using two-result operations.
3565 SDVTList VTs = DAG.getVTList(VT, VT);
3566 if (Node->getOpcode() == ISD::SREM &&
3567 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3568 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3569 VTs, Tmp1, Tmp2).getNode(), 1);
3572 if (Node->getOpcode() == ISD::UREM &&
3573 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3574 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3575 VTs, Tmp1, Tmp2).getNode(), 1);
3579 if (VT.isInteger()) {
3580 if (TLI.getOperationAction(DivOpc, VT) ==
3581 TargetLowering::Legal) {
3583 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3584 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3585 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3586 } else if (VT.isVector()) {
3587 Result = LegalizeOp(UnrollVectorOp(Op));
3589 assert(VT == MVT::i32 &&
3590 "Cannot expand this binary operator!");
3591 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3592 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3594 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3597 assert(VT.isFloatingPoint() &&
3598 "remainder op must have integer or floating-point type");
3599 if (VT.isVector()) {
3600 Result = LegalizeOp(UnrollVectorOp(Op));
3602 // Floating point mod -> fmod libcall.
3603 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3604 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3606 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3614 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3615 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3617 MVT VT = Node->getValueType(0);
3618 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3619 default: assert(0 && "This action is not supported yet!");
3620 case TargetLowering::Custom:
3623 case TargetLowering::Legal:
3624 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3625 Result = Result.getValue(0);
3626 Tmp1 = Result.getValue(1);
3629 Tmp2 = TLI.LowerOperation(Result, DAG);
3630 if (Tmp2.getNode()) {
3631 Result = LegalizeOp(Tmp2);
3632 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3636 case TargetLowering::Expand: {
3637 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3638 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3639 // Increment the pointer, VAList, to the next vaarg
3640 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3641 DAG.getConstant(TLI.getTargetData()->
3642 getTypePaddedSize(VT.getTypeForMVT()),
3643 TLI.getPointerTy()));
3644 // Store the incremented VAList to the legalized pointer
3645 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3646 // Load the actual argument out of the pointer VAList
3647 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3648 Tmp1 = LegalizeOp(Result.getValue(1));
3649 Result = LegalizeOp(Result);
3653 // Since VAARG produces two values, make sure to remember that we
3654 // legalized both of them.
3655 AddLegalizedOperand(SDValue(Node, 0), Result);
3656 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3657 return Op.getResNo() ? Tmp1 : Result;
3661 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3662 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3663 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3665 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3666 default: assert(0 && "This action is not supported yet!");
3667 case TargetLowering::Custom:
3670 case TargetLowering::Legal:
3671 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3672 Node->getOperand(3), Node->getOperand(4));
3674 Tmp1 = TLI.LowerOperation(Result, DAG);
3675 if (Tmp1.getNode()) Result = Tmp1;
3678 case TargetLowering::Expand:
3679 // This defaults to loading a pointer from the input and storing it to the
3680 // output, returning the chain.
3681 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3682 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3683 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3684 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3690 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3691 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3693 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3694 default: assert(0 && "This action is not supported yet!");
3695 case TargetLowering::Custom:
3698 case TargetLowering::Legal:
3699 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3701 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3702 if (Tmp1.getNode()) Result = Tmp1;
3705 case TargetLowering::Expand:
3706 Result = Tmp1; // Default to a no-op, return the chain
3712 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3713 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3715 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3717 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3718 default: assert(0 && "This action is not supported yet!");
3719 case TargetLowering::Legal: break;
3720 case TargetLowering::Custom:
3721 Tmp1 = TLI.LowerOperation(Result, DAG);
3722 if (Tmp1.getNode()) Result = Tmp1;
3729 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3730 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3731 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3732 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3734 assert(0 && "ROTL/ROTR legalize operation not supported");
3736 case TargetLowering::Legal:
3738 case TargetLowering::Custom:
3739 Tmp1 = TLI.LowerOperation(Result, DAG);
3740 if (Tmp1.getNode()) Result = Tmp1;
3742 case TargetLowering::Promote:
3743 assert(0 && "Do not know how to promote ROTL/ROTR");
3745 case TargetLowering::Expand:
3746 assert(0 && "Do not know how to expand ROTL/ROTR");
3752 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3753 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3754 case TargetLowering::Custom:
3755 assert(0 && "Cannot custom legalize this yet!");
3756 case TargetLowering::Legal:
3757 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3759 case TargetLowering::Promote: {
3760 MVT OVT = Tmp1.getValueType();
3761 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3762 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3764 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3765 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3766 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3767 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3770 case TargetLowering::Expand:
3771 Result = ExpandBSWAP(Tmp1, dl);
3779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3780 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3781 case TargetLowering::Custom:
3782 case TargetLowering::Legal:
3783 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3784 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3785 TargetLowering::Custom) {
3786 Tmp1 = TLI.LowerOperation(Result, DAG);
3787 if (Tmp1.getNode()) {
3792 case TargetLowering::Promote: {
3793 MVT OVT = Tmp1.getValueType();
3794 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3796 // Zero extend the argument.
3797 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3798 // Perform the larger operation, then subtract if needed.
3799 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3800 switch (Node->getOpcode()) {
3805 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3806 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3807 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3809 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3810 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3813 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3814 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3815 DAG.getConstant(NVT.getSizeInBits() -
3816 OVT.getSizeInBits(), NVT));
3821 case TargetLowering::Expand:
3822 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3842 case ISD::FNEARBYINT:
3843 Tmp1 = LegalizeOp(Node->getOperand(0));
3844 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3845 case TargetLowering::Promote:
3846 case TargetLowering::Custom:
3849 case TargetLowering::Legal:
3850 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3852 Tmp1 = TLI.LowerOperation(Result, DAG);
3853 if (Tmp1.getNode()) Result = Tmp1;
3856 case TargetLowering::Expand:
3857 switch (Node->getOpcode()) {
3858 default: assert(0 && "Unreachable!");
3860 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3861 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3862 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3865 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3866 MVT VT = Node->getValueType(0);
3867 Tmp2 = DAG.getConstantFP(0.0, VT);
3868 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3869 Tmp1, Tmp2, ISD::SETUGT);
3870 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3871 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3886 case ISD::FNEARBYINT: {
3887 MVT VT = Node->getValueType(0);
3889 // Expand unsupported unary vector operators by unrolling them.
3890 if (VT.isVector()) {
3891 Result = LegalizeOp(UnrollVectorOp(Op));
3895 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3896 switch(Node->getOpcode()) {
3898 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3899 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3902 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3903 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3906 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3907 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3910 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3911 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3914 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3915 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3918 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3919 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3922 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3923 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3926 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3927 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3930 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3931 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3934 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3935 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3938 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3939 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3942 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3943 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3945 case ISD::FNEARBYINT:
3946 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3947 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3950 default: assert(0 && "Unreachable!");
3953 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3961 MVT VT = Node->getValueType(0);
3963 // Expand unsupported unary vector operators by unrolling them.
3964 if (VT.isVector()) {
3965 Result = LegalizeOp(UnrollVectorOp(Op));
3969 // We always lower FPOWI into a libcall. No target support for it yet.
3970 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3971 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3973 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3976 case ISD::BIT_CONVERT:
3977 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3978 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3979 Node->getValueType(0), dl);
3980 } else if (Op.getOperand(0).getValueType().isVector()) {
3981 // The input has to be a vector type, we have to either scalarize it, pack
3982 // it, or convert it based on whether the input vector type is legal.
3983 SDNode *InVal = Node->getOperand(0).getNode();
3984 int InIx = Node->getOperand(0).getResNo();
3985 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3986 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3988 // Figure out if there is a simple type corresponding to this Vector
3989 // type. If so, convert to the vector type.
3990 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3991 if (TLI.isTypeLegal(TVT)) {
3992 // Turn this into a bit convert of the vector input.
3993 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3994 LegalizeOp(Node->getOperand(0)));
3996 } else if (NumElems == 1) {
3997 // Turn this into a bit convert of the scalar input.
3998 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3999 ScalarizeVectorOp(Node->getOperand(0)));
4002 // FIXME: UNIMP! Store then reload
4003 assert(0 && "Cast from unsupported vector type not implemented yet!");
4006 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
4007 Node->getOperand(0).getValueType())) {
4008 default: assert(0 && "Unknown operation action!");
4009 case TargetLowering::Expand:
4010 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4011 Node->getValueType(0), dl);
4013 case TargetLowering::Legal:
4014 Tmp1 = LegalizeOp(Node->getOperand(0));
4015 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4020 case ISD::CONVERT_RNDSAT: {
4021 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4023 default: assert(0 && "Unknown cvt code!");
4034 SDValue DTyOp = Node->getOperand(1);
4035 SDValue STyOp = Node->getOperand(2);
4036 SDValue RndOp = Node->getOperand(3);
4037 SDValue SatOp = Node->getOperand(4);
4038 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4039 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4041 Tmp1 = LegalizeOp(Node->getOperand(0));
4042 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4044 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4045 TargetLowering::Custom) {
4046 Tmp1 = TLI.LowerOperation(Result, DAG);
4047 if (Tmp1.getNode()) Result = Tmp1;
4051 Result = PromoteOp(Node->getOperand(0));
4052 // For FP, make Op1 a i32
4054 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
4055 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4060 } // end switch CvtCode
4063 // Conversion operators. The source and destination have different types.
4064 case ISD::SINT_TO_FP:
4065 case ISD::UINT_TO_FP: {
4066 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4067 Result = LegalizeINT_TO_FP(Result, isSigned,
4068 Node->getValueType(0), Node->getOperand(0), dl);
4072 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4074 Tmp1 = LegalizeOp(Node->getOperand(0));
4075 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4076 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4077 case TargetLowering::Custom:
4080 case TargetLowering::Legal:
4081 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4083 Tmp1 = TLI.LowerOperation(Result, DAG);
4084 if (Tmp1.getNode()) Result = Tmp1;
4087 case TargetLowering::Expand:
4088 assert(Result.getValueType().isVector() && "must be vector type");
4089 // Unroll the truncate. We should do better.
4090 Result = LegalizeOp(UnrollVectorOp(Result));
4094 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4096 // Since the result is legal, we should just be able to truncate the low
4097 // part of the source.
4098 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4101 Result = PromoteOp(Node->getOperand(0));
4102 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4107 case ISD::FP_TO_SINT:
4108 case ISD::FP_TO_UINT:
4109 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4111 Tmp1 = LegalizeOp(Node->getOperand(0));
4113 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4114 default: assert(0 && "Unknown operation action!");
4115 case TargetLowering::Custom:
4118 case TargetLowering::Legal:
4119 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4121 Tmp1 = TLI.LowerOperation(Result, DAG);
4122 if (Tmp1.getNode()) Result = Tmp1;
4125 case TargetLowering::Promote:
4126 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4127 Node->getOpcode() == ISD::FP_TO_SINT,
4130 case TargetLowering::Expand:
4131 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4132 SDValue True, False;
4133 MVT VT = Node->getOperand(0).getValueType();
4134 MVT NVT = Node->getValueType(0);
4135 const uint64_t zero[] = {0, 0};
4136 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4137 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4138 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4139 Tmp2 = DAG.getConstantFP(apf, VT);
4140 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4141 Node->getOperand(0),
4143 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4144 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4145 DAG.getNode(ISD::FSUB, dl, VT,
4146 Node->getOperand(0), Tmp2));
4147 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4148 DAG.getConstant(x, NVT));
4149 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4152 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4158 MVT VT = Op.getValueType();
4159 MVT OVT = Node->getOperand(0).getValueType();
4160 // Convert ppcf128 to i32
4161 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4162 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4163 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4164 Node->getOperand(0), DAG.getValueType(MVT::f64));
4165 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4166 DAG.getIntPtrConstant(1));
4167 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4169 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4170 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4171 Tmp2 = DAG.getConstantFP(apf, OVT);
4172 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4173 // FIXME: generated code sucks.
4174 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4176 DAG.getNode(ISD::ADD, dl, MVT::i32,
4177 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4178 DAG.getNode(ISD::FSUB, dl, OVT,
4179 Node->getOperand(0), Tmp2)),
4180 DAG.getConstant(0x80000000, MVT::i32)),
4181 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4182 Node->getOperand(0)),
4183 DAG.getCondCode(ISD::SETGE));
4187 // Convert f32 / f64 to i32 / i64 / i128.
4188 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4189 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4190 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4192 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4196 Tmp1 = PromoteOp(Node->getOperand(0));
4197 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4198 Result = LegalizeOp(Result);
4203 case ISD::FP_EXTEND: {
4204 MVT DstVT = Op.getValueType();
4205 MVT SrcVT = Op.getOperand(0).getValueType();
4206 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4207 // The only other way we can lower this is to turn it into a STORE,
4208 // LOAD pair, targetting a temporary location (a stack slot).
4209 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4212 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4213 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4215 Tmp1 = LegalizeOp(Node->getOperand(0));
4216 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4219 Tmp1 = PromoteOp(Node->getOperand(0));
4220 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4225 case ISD::FP_ROUND: {
4226 MVT DstVT = Op.getValueType();
4227 MVT SrcVT = Op.getOperand(0).getValueType();
4228 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4229 if (SrcVT == MVT::ppcf128) {
4231 ExpandOp(Node->getOperand(0), Lo, Result);
4232 // Round it the rest of the way (e.g. to f32) if needed.
4233 if (DstVT!=MVT::f64)
4234 Result = DAG.getNode(ISD::FP_ROUND, dl,
4235 DstVT, Result, Op.getOperand(1));
4238 // The only other way we can lower this is to turn it into a STORE,
4239 // LOAD pair, targetting a temporary location (a stack slot).
4240 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4243 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4244 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4246 Tmp1 = LegalizeOp(Node->getOperand(0));
4247 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4250 Tmp1 = PromoteOp(Node->getOperand(0));
4251 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4252 Node->getOperand(1));
4257 case ISD::ANY_EXTEND:
4258 case ISD::ZERO_EXTEND:
4259 case ISD::SIGN_EXTEND:
4260 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4261 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4263 Tmp1 = LegalizeOp(Node->getOperand(0));
4264 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4265 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4266 TargetLowering::Custom) {
4267 Tmp1 = TLI.LowerOperation(Result, DAG);
4268 if (Tmp1.getNode()) Result = Tmp1;
4272 switch (Node->getOpcode()) {
4273 case ISD::ANY_EXTEND:
4274 Tmp1 = PromoteOp(Node->getOperand(0));
4275 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4277 case ISD::ZERO_EXTEND:
4278 Result = PromoteOp(Node->getOperand(0));
4279 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4280 Result = DAG.getZeroExtendInReg(Result, dl,
4281 Node->getOperand(0).getValueType());
4283 case ISD::SIGN_EXTEND:
4284 Result = PromoteOp(Node->getOperand(0));
4285 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4286 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4288 DAG.getValueType(Node->getOperand(0).getValueType()));
4293 case ISD::FP_ROUND_INREG:
4294 case ISD::SIGN_EXTEND_INREG: {
4295 Tmp1 = LegalizeOp(Node->getOperand(0));
4296 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4298 // If this operation is not supported, convert it to a shl/shr or load/store
4300 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4301 default: assert(0 && "This action not supported for this op yet!");
4302 case TargetLowering::Legal:
4303 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4305 case TargetLowering::Expand:
4306 // If this is an integer extend and shifts are supported, do that.
4307 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4308 // NOTE: we could fall back on load/store here too for targets without
4309 // SAR. However, it is doubtful that any exist.
4310 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4311 ExtraVT.getSizeInBits();
4312 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4313 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4314 Node->getOperand(0), ShiftCst);
4315 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4317 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4318 // The only way we can lower this is to turn it into a TRUNCSTORE,
4319 // EXTLOAD pair, targetting a temporary location (a stack slot).
4321 // NOTE: there is a choice here between constantly creating new stack
4322 // slots and always reusing the same one. We currently always create
4323 // new ones, as reuse may inhibit scheduling.
4324 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4325 Node->getValueType(0), dl);
4327 assert(0 && "Unknown op");
4333 case ISD::TRAMPOLINE: {
4335 for (unsigned i = 0; i != 6; ++i)
4336 Ops[i] = LegalizeOp(Node->getOperand(i));
4337 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4338 // The only option for this node is to custom lower it.
4339 Result = TLI.LowerOperation(Result, DAG);
4340 assert(Result.getNode() && "Should always custom lower!");
4342 // Since trampoline produces two values, make sure to remember that we
4343 // legalized both of them.
4344 Tmp1 = LegalizeOp(Result.getValue(1));
4345 Result = LegalizeOp(Result);
4346 AddLegalizedOperand(SDValue(Node, 0), Result);
4347 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4348 return Op.getResNo() ? Tmp1 : Result;
4350 case ISD::FLT_ROUNDS_: {
4351 MVT VT = Node->getValueType(0);
4352 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4353 default: assert(0 && "This action not supported for this op yet!");
4354 case TargetLowering::Custom:
4355 Result = TLI.LowerOperation(Op, DAG);
4356 if (Result.getNode()) break;
4358 case TargetLowering::Legal:
4359 // If this operation is not supported, lower it to constant 1
4360 Result = DAG.getConstant(1, VT);
4366 MVT VT = Node->getValueType(0);
4367 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4368 default: assert(0 && "This action not supported for this op yet!");
4369 case TargetLowering::Legal:
4370 Tmp1 = LegalizeOp(Node->getOperand(0));
4371 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4373 case TargetLowering::Custom:
4374 Result = TLI.LowerOperation(Op, DAG);
4375 if (Result.getNode()) break;
4377 case TargetLowering::Expand:
4378 // If this operation is not supported, lower it to 'abort()' call
4379 Tmp1 = LegalizeOp(Node->getOperand(0));
4380 TargetLowering::ArgListTy Args;
4381 std::pair<SDValue,SDValue> CallResult =
4382 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4383 false, false, false, false, CallingConv::C, false,
4384 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4386 Result = CallResult.second;
4394 MVT VT = Node->getValueType(0);
4395 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4396 default: assert(0 && "This action not supported for this op yet!");
4397 case TargetLowering::Custom:
4398 Result = TLI.LowerOperation(Op, DAG);
4399 if (Result.getNode()) break;
4401 case TargetLowering::Legal: {
4402 SDValue LHS = LegalizeOp(Node->getOperand(0));
4403 SDValue RHS = LegalizeOp(Node->getOperand(1));
4405 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4406 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4408 MVT OType = Node->getValueType(1);
4410 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4412 // LHSSign -> LHS >= 0
4413 // RHSSign -> RHS >= 0
4414 // SumSign -> Sum >= 0
4417 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4419 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4421 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4422 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4423 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4424 Node->getOpcode() == ISD::SADDO ?
4425 ISD::SETEQ : ISD::SETNE);
4427 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4428 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4430 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4432 MVT ValueVTs[] = { LHS.getValueType(), OType };
4433 SDValue Ops[] = { Sum, Cmp };
4435 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4436 DAG.getVTList(&ValueVTs[0], 2),
4438 SDNode *RNode = Result.getNode();
4439 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4440 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4449 MVT VT = Node->getValueType(0);
4450 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4451 default: assert(0 && "This action not supported for this op yet!");
4452 case TargetLowering::Custom:
4453 Result = TLI.LowerOperation(Op, DAG);
4454 if (Result.getNode()) break;
4456 case TargetLowering::Legal: {
4457 SDValue LHS = LegalizeOp(Node->getOperand(0));
4458 SDValue RHS = LegalizeOp(Node->getOperand(1));
4460 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4461 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4463 MVT OType = Node->getValueType(1);
4464 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4465 Node->getOpcode () == ISD::UADDO ?
4466 ISD::SETULT : ISD::SETUGT);
4468 MVT ValueVTs[] = { LHS.getValueType(), OType };
4469 SDValue Ops[] = { Sum, Cmp };
4471 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4472 DAG.getVTList(&ValueVTs[0], 2),
4474 SDNode *RNode = Result.getNode();
4475 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4476 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4485 MVT VT = Node->getValueType(0);
4486 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4487 default: assert(0 && "This action is not supported at all!");
4488 case TargetLowering::Custom:
4489 Result = TLI.LowerOperation(Op, DAG);
4490 if (Result.getNode()) break;
4492 case TargetLowering::Legal:
4493 // FIXME: According to Hacker's Delight, this can be implemented in
4494 // target independent lowering, but it would be inefficient, since it
4495 // requires a division + a branch.
4496 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4504 assert(Result.getValueType() == Op.getValueType() &&
4505 "Bad legalization!");
4507 // Make sure that the generated code is itself legal.
4509 Result = LegalizeOp(Result);
4511 // Note that LegalizeOp may be reentered even from single-use nodes, which
4512 // means that we always must cache transformed nodes.
4513 AddLegalizedOperand(Op, Result);
4517 /// PromoteOp - Given an operation that produces a value in an invalid type,
4518 /// promote it to compute the value into a larger type. The produced value will
4519 /// have the correct bits for the low portion of the register, but no guarantee
4520 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4521 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4522 MVT VT = Op.getValueType();
4523 MVT NVT = TLI.getTypeToTransformTo(VT);
4524 assert(getTypeAction(VT) == Promote &&
4525 "Caller should expand or legalize operands that are not promotable!");
4526 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4527 "Cannot promote to smaller type!");
4529 SDValue Tmp1, Tmp2, Tmp3;
4531 SDNode *Node = Op.getNode();
4532 DebugLoc dl = Node->getDebugLoc();
4534 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4535 if (I != PromotedNodes.end()) return I->second;
4537 switch (Node->getOpcode()) {
4538 case ISD::CopyFromReg:
4539 assert(0 && "CopyFromReg must be legal!");
4542 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4544 assert(0 && "Do not know how to promote this operator!");
4547 Result = DAG.getUNDEF(NVT);
4551 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4553 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4554 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4556 case ISD::ConstantFP:
4557 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4558 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4562 MVT VT0 = Node->getOperand(0).getValueType();
4563 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4564 && "SetCC type is not legal??");
4565 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4566 Node->getOperand(0), Node->getOperand(1),
4567 Node->getOperand(2));
4571 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4573 Result = LegalizeOp(Node->getOperand(0));
4574 assert(Result.getValueType().bitsGE(NVT) &&
4575 "This truncation doesn't make sense!");
4576 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4577 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4580 // The truncation is not required, because we don't guarantee anything
4581 // about high bits anyway.
4582 Result = PromoteOp(Node->getOperand(0));
4585 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4586 // Truncate the low part of the expanded value to the result type
4587 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4590 case ISD::SIGN_EXTEND:
4591 case ISD::ZERO_EXTEND:
4592 case ISD::ANY_EXTEND:
4593 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4594 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4596 // Input is legal? Just do extend all the way to the larger type.
4597 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4600 // Promote the reg if it's smaller.
4601 Result = PromoteOp(Node->getOperand(0));
4602 // The high bits are not guaranteed to be anything. Insert an extend.
4603 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4604 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4605 DAG.getValueType(Node->getOperand(0).getValueType()));
4606 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4607 Result = DAG.getZeroExtendInReg(Result, dl,
4608 Node->getOperand(0).getValueType());
4612 case ISD::CONVERT_RNDSAT: {
4613 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4614 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4615 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4616 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4617 "can only promote integers");
4618 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
4619 Node->getOperand(1), Node->getOperand(2),
4620 Node->getOperand(3), Node->getOperand(4),
4625 case ISD::BIT_CONVERT:
4626 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4627 Node->getValueType(0), dl);
4628 Result = PromoteOp(Result);
4631 case ISD::FP_EXTEND:
4632 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4634 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4635 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4636 case Promote: assert(0 && "Unreachable with 2 FP types!");
4638 if (Node->getConstantOperandVal(1) == 0) {
4639 // Input is legal? Do an FP_ROUND_INREG.
4640 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4641 DAG.getValueType(VT));
4643 // Just remove the truncate, it isn't affecting the value.
4644 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4645 Node->getOperand(1));
4650 case ISD::SINT_TO_FP:
4651 case ISD::UINT_TO_FP:
4652 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4654 // No extra round required here.
4655 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4659 Result = PromoteOp(Node->getOperand(0));
4660 if (Node->getOpcode() == ISD::SINT_TO_FP)
4661 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4663 DAG.getValueType(Node->getOperand(0).getValueType()));
4665 Result = DAG.getZeroExtendInReg(Result, dl,
4666 Node->getOperand(0).getValueType());
4667 // No extra round required here.
4668 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4671 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4672 Node->getOperand(0), dl);
4673 // Round if we cannot tolerate excess precision.
4674 if (NoExcessFPPrecision)
4675 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4676 DAG.getValueType(VT));
4681 case ISD::SIGN_EXTEND_INREG:
4682 Result = PromoteOp(Node->getOperand(0));
4683 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4684 Node->getOperand(1));
4686 case ISD::FP_TO_SINT:
4687 case ISD::FP_TO_UINT:
4688 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4691 Tmp1 = Node->getOperand(0);
4694 // The input result is prerounded, so we don't have to do anything
4696 Tmp1 = PromoteOp(Node->getOperand(0));
4699 // If we're promoting a UINT to a larger size, check to see if the new node
4700 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4701 // we can use that instead. This allows us to generate better code for
4702 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4703 // legal, such as PowerPC.
4704 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4705 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4706 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4707 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4708 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4710 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4716 Tmp1 = PromoteOp(Node->getOperand(0));
4717 assert(Tmp1.getValueType() == NVT);
4718 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4719 // NOTE: we do not have to do any extra rounding here for
4720 // NoExcessFPPrecision, because we know the input will have the appropriate
4721 // precision, and these operations don't modify precision at all.
4736 case ISD::FNEARBYINT:
4737 Tmp1 = PromoteOp(Node->getOperand(0));
4738 assert(Tmp1.getValueType() == NVT);
4739 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4740 if (NoExcessFPPrecision)
4741 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4742 DAG.getValueType(VT));
4747 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4748 // directly as well, which may be better.
4749 Tmp1 = PromoteOp(Node->getOperand(0));
4750 Tmp2 = Node->getOperand(1);
4751 if (Node->getOpcode() == ISD::FPOW)
4752 Tmp2 = PromoteOp(Tmp2);
4753 assert(Tmp1.getValueType() == NVT);
4754 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4755 if (NoExcessFPPrecision)
4756 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4757 DAG.getValueType(VT));
4761 case ISD::ATOMIC_CMP_SWAP: {
4762 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4763 Tmp2 = PromoteOp(Node->getOperand(2));
4764 Tmp3 = PromoteOp(Node->getOperand(3));
4765 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4766 AtomNode->getChain(),
4767 AtomNode->getBasePtr(), Tmp2, Tmp3,
4768 AtomNode->getSrcValue(),
4769 AtomNode->getAlignment());
4770 // Remember that we legalized the chain.
4771 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4774 case ISD::ATOMIC_LOAD_ADD:
4775 case ISD::ATOMIC_LOAD_SUB:
4776 case ISD::ATOMIC_LOAD_AND:
4777 case ISD::ATOMIC_LOAD_OR:
4778 case ISD::ATOMIC_LOAD_XOR:
4779 case ISD::ATOMIC_LOAD_NAND:
4780 case ISD::ATOMIC_LOAD_MIN:
4781 case ISD::ATOMIC_LOAD_MAX:
4782 case ISD::ATOMIC_LOAD_UMIN:
4783 case ISD::ATOMIC_LOAD_UMAX:
4784 case ISD::ATOMIC_SWAP: {
4785 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4786 Tmp2 = PromoteOp(Node->getOperand(2));
4787 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4788 AtomNode->getChain(),
4789 AtomNode->getBasePtr(), Tmp2,
4790 AtomNode->getSrcValue(),
4791 AtomNode->getAlignment());
4792 // Remember that we legalized the chain.
4793 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4803 // The input may have strange things in the top bits of the registers, but
4804 // these operations don't care. They may have weird bits going out, but
4805 // that too is okay if they are integer operations.
4806 Tmp1 = PromoteOp(Node->getOperand(0));
4807 Tmp2 = PromoteOp(Node->getOperand(1));
4808 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4809 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4814 Tmp1 = PromoteOp(Node->getOperand(0));
4815 Tmp2 = PromoteOp(Node->getOperand(1));
4816 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4817 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4819 // Floating point operations will give excess precision that we may not be
4820 // able to tolerate. If we DO allow excess precision, just leave it,
4821 // otherwise excise it.
4822 // FIXME: Why would we need to round FP ops more than integer ones?
4823 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4824 if (NoExcessFPPrecision)
4825 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4826 DAG.getValueType(VT));
4831 // These operators require that their input be sign extended.
4832 Tmp1 = PromoteOp(Node->getOperand(0));
4833 Tmp2 = PromoteOp(Node->getOperand(1));
4834 if (NVT.isInteger()) {
4835 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4836 DAG.getValueType(VT));
4837 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4838 DAG.getValueType(VT));
4840 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4842 // Perform FP_ROUND: this is probably overly pessimistic.
4843 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4844 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4845 DAG.getValueType(VT));
4849 case ISD::FCOPYSIGN:
4850 // These operators require that their input be fp extended.
4851 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4852 case Expand: assert(0 && "not implemented");
4853 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4854 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4856 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4857 case Expand: assert(0 && "not implemented");
4858 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4859 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4861 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4863 // Perform FP_ROUND: this is probably overly pessimistic.
4864 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4865 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4866 DAG.getValueType(VT));
4871 // These operators require that their input be zero extended.
4872 Tmp1 = PromoteOp(Node->getOperand(0));
4873 Tmp2 = PromoteOp(Node->getOperand(1));
4874 assert(NVT.isInteger() && "Operators don't apply to FP!");
4875 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4876 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4877 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4881 Tmp1 = PromoteOp(Node->getOperand(0));
4882 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4885 // The input value must be properly sign extended.
4886 Tmp1 = PromoteOp(Node->getOperand(0));
4887 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4888 DAG.getValueType(VT));
4889 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4892 // The input value must be properly zero extended.
4893 Tmp1 = PromoteOp(Node->getOperand(0));
4894 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4895 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4899 Tmp1 = Node->getOperand(0); // Get the chain.
4900 Tmp2 = Node->getOperand(1); // Get the pointer.
4901 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4902 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
4903 Result = TLI.LowerOperation(Tmp3, DAG);
4905 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4906 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
4907 // Increment the pointer, VAList, to the next vaarg
4908 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4909 DAG.getConstant(VT.getSizeInBits()/8,
4910 TLI.getPointerTy()));
4911 // Store the incremented VAList to the legalized pointer
4912 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4913 // Load the actual argument out of the pointer VAList
4914 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4916 // Remember that we legalized the chain.
4917 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4921 LoadSDNode *LD = cast<LoadSDNode>(Node);
4922 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4923 ? ISD::EXTLOAD : LD->getExtensionType();
4924 Result = DAG.getExtLoad(ExtType, dl, NVT,
4925 LD->getChain(), LD->getBasePtr(),
4926 LD->getSrcValue(), LD->getSrcValueOffset(),
4929 LD->getAlignment());
4930 // Remember that we legalized the chain.
4931 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4935 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4936 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4938 MVT VT2 = Tmp2.getValueType();
4939 assert(VT2 == Tmp3.getValueType()
4940 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4941 // Ensure that the resulting node is at least the same size as the operands'
4942 // value types, because we cannot assume that TLI.getSetCCValueType() is
4944 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4947 case ISD::SELECT_CC:
4948 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4949 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4950 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4951 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4954 Tmp1 = Node->getOperand(0);
4955 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4956 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4957 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4958 DAG.getConstant(NVT.getSizeInBits() -
4960 TLI.getShiftAmountTy()));
4965 // Zero extend the argument
4966 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4967 // Perform the larger operation, then subtract if needed.
4968 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4969 switch(Node->getOpcode()) {
4974 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4975 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4976 DAG.getConstant(NVT.getSizeInBits(), NVT),
4978 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4979 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4982 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4983 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4984 DAG.getConstant(NVT.getSizeInBits() -
4985 VT.getSizeInBits(), NVT));
4989 case ISD::EXTRACT_SUBVECTOR:
4990 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4992 case ISD::EXTRACT_VECTOR_ELT:
4993 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4997 assert(Result.getNode() && "Didn't set a result!");
4999 // Make sure the result is itself legal.
5000 Result = LegalizeOp(Result);
5002 // Remember that we promoted this!
5003 AddPromotedOperand(Op, Result);
5007 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
5008 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
5009 /// based on the vector type. The return type of this matches the element type
5010 /// of the vector, which may not be legal for the target.
5011 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
5012 // We know that operand #0 is the Vec vector. If the index is a constant
5013 // or if the invec is a supported hardware type, we can use it. Otherwise,
5014 // lower to a store then an indexed load.
5015 SDValue Vec = Op.getOperand(0);
5016 SDValue Idx = Op.getOperand(1);
5017 DebugLoc dl = Op.getDebugLoc();
5019 MVT TVT = Vec.getValueType();
5020 unsigned NumElems = TVT.getVectorNumElements();
5022 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
5023 default: assert(0 && "This action is not supported yet!");
5024 case TargetLowering::Custom: {
5025 Vec = LegalizeOp(Vec);
5026 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5027 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
5032 case TargetLowering::Legal:
5033 if (isTypeLegal(TVT)) {
5034 Vec = LegalizeOp(Vec);
5035 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5039 case TargetLowering::Promote:
5040 assert(TVT.isVector() && "not vector type");
5041 // fall thru to expand since vectors are by default are promote
5042 case TargetLowering::Expand:
5046 if (NumElems == 1) {
5047 // This must be an access of the only element. Return it.
5048 Op = ScalarizeVectorOp(Vec);
5049 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5050 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5051 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5053 SplitVectorOp(Vec, Lo, Hi);
5054 if (CIdx->getZExtValue() < NumLoElts) {
5058 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5059 Idx.getValueType());
5062 // It's now an extract from the appropriate high or low part. Recurse.
5063 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5064 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5066 // Store the value to a temporary stack slot, then LOAD the scalar
5067 // element back out.
5068 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5069 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5071 // Add the offset to the index.
5072 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5073 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5074 DAG.getConstant(EltSize, Idx.getValueType()));
5076 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5077 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5079 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5081 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5083 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5088 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5089 /// we assume the operation can be split if it is not already legal.
5090 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5091 // We know that operand #0 is the Vec vector. For now we assume the index
5092 // is a constant and that the extracted result is a supported hardware type.
5093 SDValue Vec = Op.getOperand(0);
5094 SDValue Idx = LegalizeOp(Op.getOperand(1));
5096 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5098 if (NumElems == Op.getValueType().getVectorNumElements()) {
5099 // This must be an access of the desired vector length. Return it.
5103 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5105 SplitVectorOp(Vec, Lo, Hi);
5106 if (CIdx->getZExtValue() < NumElems/2) {
5110 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5111 Idx.getValueType());
5114 // It's now an extract from the appropriate high or low part. Recurse.
5115 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5116 return ExpandEXTRACT_SUBVECTOR(Op);
5119 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5120 /// with condition CC on the current target. This usually involves legalizing
5121 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5122 /// there may be no choice but to create a new SetCC node to represent the
5123 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5124 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5125 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5129 SDValue Tmp1, Tmp2, Tmp3, Result;
5131 switch (getTypeAction(LHS.getValueType())) {
5133 Tmp1 = LegalizeOp(LHS); // LHS
5134 Tmp2 = LegalizeOp(RHS); // RHS
5137 Tmp1 = PromoteOp(LHS); // LHS
5138 Tmp2 = PromoteOp(RHS); // RHS
5140 // If this is an FP compare, the operands have already been extended.
5141 if (LHS.getValueType().isInteger()) {
5142 MVT VT = LHS.getValueType();
5143 MVT NVT = TLI.getTypeToTransformTo(VT);
5145 // Otherwise, we have to insert explicit sign or zero extends. Note
5146 // that we could insert sign extends for ALL conditions, but zero extend
5147 // is cheaper on many machines (an AND instead of two shifts), so prefer
5149 switch (cast<CondCodeSDNode>(CC)->get()) {
5150 default: assert(0 && "Unknown integer comparison!");
5157 // ALL of these operations will work if we either sign or zero extend
5158 // the operands (including the unsigned comparisons!). Zero extend is
5159 // usually a simpler/cheaper operation, so prefer it.
5160 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5161 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5167 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5168 DAG.getValueType(VT));
5169 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5170 DAG.getValueType(VT));
5171 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5172 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5178 MVT VT = LHS.getValueType();
5179 if (VT == MVT::f32 || VT == MVT::f64) {
5180 // Expand into one or more soft-fp libcall(s).
5181 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5182 switch (cast<CondCodeSDNode>(CC)->get()) {
5185 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5189 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5193 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5197 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5201 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5205 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5208 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5211 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5214 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5215 switch (cast<CondCodeSDNode>(CC)->get()) {
5217 // SETONE = SETOLT | SETOGT
5218 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5221 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5224 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5227 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5230 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5233 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5235 default: assert(0 && "Unsupported FP setcc!");
5240 SDValue Ops[2] = { LHS, RHS };
5241 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5242 false /*sign irrelevant*/, Dummy);
5243 Tmp2 = DAG.getConstant(0, MVT::i32);
5244 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5245 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5246 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5247 TLI.getSetCCResultType(Tmp1.getValueType()),
5249 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5250 false /*sign irrelevant*/, Dummy);
5251 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5252 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5253 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5254 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5257 LHS = LegalizeOp(Tmp1);
5262 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5263 ExpandOp(LHS, LHSLo, LHSHi);
5264 ExpandOp(RHS, RHSLo, RHSHi);
5265 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5267 if (VT==MVT::ppcf128) {
5268 // FIXME: This generated code sucks. We want to generate
5269 // FCMPU crN, hi1, hi2
5271 // FCMPU crN, lo1, lo2
5272 // The following can be improved, but not that much.
5273 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5274 LHSHi, RHSHi, ISD::SETOEQ);
5275 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5276 LHSLo, RHSLo, CCCode);
5277 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5278 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5279 LHSHi, RHSHi, ISD::SETUNE);
5280 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5281 LHSHi, RHSHi, CCCode);
5282 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5283 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5292 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5293 if (RHSCST->isAllOnesValue()) {
5294 // Comparison to -1.
5295 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5300 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5301 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5302 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5303 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5306 // If this is a comparison of the sign bit, just look at the top part.
5308 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5309 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5310 CST->isNullValue()) || // X < 0
5311 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5312 CST->isAllOnesValue())) { // X > -1
5318 // FIXME: This generated code sucks.
5319 ISD::CondCode LowCC;
5321 default: assert(0 && "Unknown integer setcc!");
5323 case ISD::SETULT: LowCC = ISD::SETULT; break;
5325 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5327 case ISD::SETULE: LowCC = ISD::SETULE; break;
5329 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5332 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5333 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5334 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5336 // NOTE: on targets without efficient SELECT of bools, we can always use
5337 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5338 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5339 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5340 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5341 if (!Tmp1.getNode())
5342 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5343 LHSLo, RHSLo, LowCC);
5344 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5345 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5346 if (!Tmp2.getNode())
5347 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5348 TLI.getSetCCResultType(LHSHi.getValueType()),
5351 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5352 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5353 if ((Tmp1C && Tmp1C->isNullValue()) ||
5354 (Tmp2C && Tmp2C->isNullValue() &&
5355 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5356 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5357 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5358 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5359 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5360 // low part is known false, returns high part.
5361 // For LE / GE, if high part is known false, ignore the low part.
5362 // For LT / GT, if high part is known true, ignore the low part.
5366 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5367 LHSHi, RHSHi, ISD::SETEQ, false,
5368 DagCombineInfo, dl);
5369 if (!Result.getNode())
5370 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5371 LHSHi, RHSHi, ISD::SETEQ);
5372 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5373 Result, Tmp1, Tmp2));
5384 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5385 /// condition code CC on the current target. This routine assumes LHS and rHS
5386 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5387 /// illegal condition code into AND / OR of multiple SETCC values.
5388 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5389 SDValue &LHS, SDValue &RHS,
5392 MVT OpVT = LHS.getValueType();
5393 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5394 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5395 default: assert(0 && "Unknown condition code action!");
5396 case TargetLowering::Legal:
5399 case TargetLowering::Expand: {
5400 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5403 default: assert(0 && "Don't know how to expand this condition!"); abort();
5404 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5405 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5406 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5407 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5408 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5409 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5410 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5411 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5412 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5413 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5414 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5415 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5416 // FIXME: Implement more expansions.
5419 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5420 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5421 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5429 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5430 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5431 /// a load from the stack slot to DestVT, extending it if needed.
5432 /// The resultant code need not be legal.
5433 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5437 // Create the stack frame object.
5438 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5439 SrcOp.getValueType().getTypeForMVT());
5440 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5442 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5443 int SPFI = StackPtrFI->getIndex();
5444 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5446 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5447 unsigned SlotSize = SlotVT.getSizeInBits();
5448 unsigned DestSize = DestVT.getSizeInBits();
5449 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5450 DestVT.getTypeForMVT());
5452 // Emit a store to the stack slot. Use a truncstore if the input value is
5453 // later than DestVT.
5456 if (SrcSize > SlotSize)
5457 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5458 SV, 0, SlotVT, false, SrcAlign);
5460 assert(SrcSize == SlotSize && "Invalid store");
5461 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5462 SV, 0, false, SrcAlign);
5465 // Result is a load from the stack slot.
5466 if (SlotSize == DestSize)
5467 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5469 assert(SlotSize < DestSize && "Unknown extension!");
5470 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5474 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5475 DebugLoc dl = Node->getDebugLoc();
5476 // Create a vector sized/aligned stack slot, store the value to element #0,
5477 // then load the whole vector back out.
5478 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5480 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5481 int SPFI = StackPtrFI->getIndex();
5483 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5485 PseudoSourceValue::getFixedStack(SPFI), 0);
5486 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5487 PseudoSourceValue::getFixedStack(SPFI), 0);
5491 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5492 /// support the operation, but do support the resultant vector type.
5493 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5495 // If the only non-undef value is the low element, turn this into a
5496 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5497 unsigned NumElems = Node->getNumOperands();
5498 bool isOnlyLowElement = true;
5499 SDValue SplatValue = Node->getOperand(0);
5500 DebugLoc dl = Node->getDebugLoc();
5502 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5503 // and use a bitmask instead of a list of elements.
5504 std::map<SDValue, std::vector<unsigned> > Values;
5505 Values[SplatValue].push_back(0);
5506 bool isConstant = true;
5507 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5508 SplatValue.getOpcode() != ISD::UNDEF)
5511 for (unsigned i = 1; i < NumElems; ++i) {
5512 SDValue V = Node->getOperand(i);
5513 Values[V].push_back(i);
5514 if (V.getOpcode() != ISD::UNDEF)
5515 isOnlyLowElement = false;
5516 if (SplatValue != V)
5517 SplatValue = SDValue(0,0);
5519 // If this isn't a constant element or an undef, we can't use a constant
5521 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5522 V.getOpcode() != ISD::UNDEF)
5526 if (isOnlyLowElement) {
5527 // If the low element is an undef too, then this whole things is an undef.
5528 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5529 return DAG.getUNDEF(Node->getValueType(0));
5530 // Otherwise, turn this into a scalar_to_vector node.
5531 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
5532 Node->getOperand(0));
5535 // If all elements are constants, create a load from the constant pool.
5537 MVT VT = Node->getValueType(0);
5538 std::vector<Constant*> CV;
5539 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5540 if (ConstantFPSDNode *V =
5541 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5542 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5543 } else if (ConstantSDNode *V =
5544 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5545 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5547 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5549 Node->getOperand(0).getValueType().getTypeForMVT();
5550 CV.push_back(UndefValue::get(OpNTy));
5553 Constant *CP = ConstantVector::get(CV);
5554 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5555 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5556 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5557 PseudoSourceValue::getConstantPool(), 0,
5561 if (SplatValue.getNode()) { // Splat of one value?
5562 // Build the shuffle constant vector: <0, 0, 0, 0>
5563 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5564 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5565 std::vector<SDValue> ZeroVec(NumElems, Zero);
5566 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5567 &ZeroVec[0], ZeroVec.size());
5569 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5570 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5571 // Get the splatted value into the low element of a vector register.
5573 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5574 Node->getValueType(0), SplatValue);
5576 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5577 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
5578 Node->getValueType(0), LowValVec,
5579 DAG.getUNDEF(Node->getValueType(0)),
5584 // If there are only two unique elements, we may be able to turn this into a
5586 if (Values.size() == 2) {
5587 // Get the two values in deterministic order.
5588 SDValue Val1 = Node->getOperand(1);
5590 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5591 if (MI->first != Val1)
5594 Val2 = (++MI)->first;
5596 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5597 // vector shuffle has the undef vector on the RHS.
5598 if (Val1.getOpcode() == ISD::UNDEF)
5599 std::swap(Val1, Val2);
5601 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5602 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5603 MVT MaskEltVT = MaskVT.getVectorElementType();
5604 std::vector<SDValue> MaskVec(NumElems);
5606 // Set elements of the shuffle mask for Val1.
5607 std::vector<unsigned> &Val1Elts = Values[Val1];
5608 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5609 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5611 // Set elements of the shuffle mask for Val2.
5612 std::vector<unsigned> &Val2Elts = Values[Val2];
5613 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5614 if (Val2.getOpcode() != ISD::UNDEF)
5615 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5617 MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
5619 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5620 &MaskVec[0], MaskVec.size());
5622 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5623 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
5624 Node->getValueType(0)) &&
5625 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5626 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1);
5627 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2);
5628 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5630 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5631 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
5635 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5636 // aligned object on the stack, store each element into it, then load
5637 // the result as a vector.
5638 MVT VT = Node->getValueType(0);
5639 // Create the stack frame object.
5640 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5641 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5642 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5644 // Emit a store of each element to the stack slot.
5645 SmallVector<SDValue, 8> Stores;
5646 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5647 // Store (in the right endianness) the elements to memory.
5648 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5649 // Ignore undef elements.
5650 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5652 unsigned Offset = TypeByteSize*i;
5654 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5655 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5657 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5662 if (!Stores.empty()) // Not all undef elements?
5663 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5664 &Stores[0], Stores.size());
5666 StoreChain = DAG.getEntryNode();
5668 // Result is a load from the stack slot.
5669 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5672 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5673 SDValue Op, SDValue Amt,
5674 SDValue &Lo, SDValue &Hi,
5676 // Expand the subcomponents.
5678 ExpandOp(Op, LHSL, LHSH);
5680 SDValue Ops[] = { LHSL, LHSH, Amt };
5681 MVT VT = LHSL.getValueType();
5682 Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5683 Hi = Lo.getValue(1);
5687 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5688 /// smaller elements. If we can't find a way that is more efficient than a
5689 /// libcall on this target, return false. Otherwise, return true with the
5690 /// low-parts expanded into Lo and Hi.
5691 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5692 SDValue &Lo, SDValue &Hi,
5694 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5695 "This is not a shift!");
5697 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5698 SDValue ShAmt = LegalizeOp(Amt);
5699 MVT ShTy = ShAmt.getValueType();
5700 unsigned ShBits = ShTy.getSizeInBits();
5701 unsigned VTBits = Op.getValueType().getSizeInBits();
5702 unsigned NVTBits = NVT.getSizeInBits();
5704 // Handle the case when Amt is an immediate.
5705 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5706 unsigned Cst = CN->getZExtValue();
5707 // Expand the incoming operand to be shifted, so that we have its parts
5709 ExpandOp(Op, InL, InH);
5713 Lo = DAG.getConstant(0, NVT);
5714 Hi = DAG.getConstant(0, NVT);
5715 } else if (Cst > NVTBits) {
5716 Lo = DAG.getConstant(0, NVT);
5717 Hi = DAG.getNode(ISD::SHL, dl,
5718 NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5719 } else if (Cst == NVTBits) {
5720 Lo = DAG.getConstant(0, NVT);
5723 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5724 Hi = DAG.getNode(ISD::OR, dl, NVT,
5725 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5726 DAG.getNode(ISD::SRL, dl, NVT, InL,
5727 DAG.getConstant(NVTBits-Cst, ShTy)));
5732 Lo = DAG.getConstant(0, NVT);
5733 Hi = DAG.getConstant(0, NVT);
5734 } else if (Cst > NVTBits) {
5735 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5736 InH, DAG.getConstant(Cst-NVTBits,ShTy));
5737 Hi = DAG.getConstant(0, NVT);
5738 } else if (Cst == NVTBits) {
5740 Hi = DAG.getConstant(0, NVT);
5742 Lo = DAG.getNode(ISD::OR, dl, NVT,
5743 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5744 DAG.getNode(ISD::SHL, dl, NVT, InH,
5745 DAG.getConstant(NVTBits-Cst, ShTy)));
5746 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5751 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5752 DAG.getConstant(NVTBits-1, ShTy));
5753 } else if (Cst > NVTBits) {
5754 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5755 DAG.getConstant(Cst-NVTBits, ShTy));
5756 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5757 DAG.getConstant(NVTBits-1, ShTy));
5758 } else if (Cst == NVTBits) {
5760 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5761 DAG.getConstant(NVTBits-1, ShTy));
5763 Lo = DAG.getNode(ISD::OR, dl, NVT,
5764 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5765 DAG.getNode(ISD::SHL, dl,
5766 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5767 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5773 // Okay, the shift amount isn't constant. However, if we can tell that it is
5774 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5775 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5776 APInt KnownZero, KnownOne;
5777 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5779 // If we know that if any of the high bits of the shift amount are one, then
5780 // we can do this as a couple of simple shifts.
5781 if (KnownOne.intersects(Mask)) {
5782 // Mask out the high bit, which we know is set.
5783 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5784 DAG.getConstant(~Mask, Amt.getValueType()));
5786 // Expand the incoming operand to be shifted, so that we have its parts
5788 ExpandOp(Op, InL, InH);
5791 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5792 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5795 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5796 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5799 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5800 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5801 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5806 // If we know that the high bits of the shift amount are all zero, then we can
5807 // do this as a couple of simple shifts.
5808 if ((KnownZero & Mask) == Mask) {
5810 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5811 DAG.getConstant(NVTBits, Amt.getValueType()),
5814 // Expand the incoming operand to be shifted, so that we have its parts
5816 ExpandOp(Op, InL, InH);
5819 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5820 Hi = DAG.getNode(ISD::OR, dl, NVT,
5821 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5822 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5825 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5826 Lo = DAG.getNode(ISD::OR, dl, NVT,
5827 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5828 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5831 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5832 Lo = DAG.getNode(ISD::OR, dl, NVT,
5833 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5834 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5843 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5844 // does not fit into a register, return the lo part and set the hi part to the
5845 // by-reg argument. If it does fit into a single register, return the result
5846 // and leave the Hi part unset.
5847 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5848 bool isSigned, SDValue &Hi) {
5849 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5850 // The input chain to this libcall is the entry node of the function.
5851 // Legalizing the call will automatically add the previous call to the
5853 SDValue InChain = DAG.getEntryNode();
5855 TargetLowering::ArgListTy Args;
5856 TargetLowering::ArgListEntry Entry;
5857 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5858 MVT ArgVT = Node->getOperand(i).getValueType();
5859 const Type *ArgTy = ArgVT.getTypeForMVT();
5860 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5861 Entry.isSExt = isSigned;
5862 Entry.isZExt = !isSigned;
5863 Args.push_back(Entry);
5865 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5866 TLI.getPointerTy());
5868 // Splice the libcall in wherever FindInputOutputChains tells us to.
5869 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5870 std::pair<SDValue,SDValue> CallInfo =
5871 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5872 CallingConv::C, false, Callee, Args, DAG,
5873 Node->getDebugLoc());
5875 // Legalize the call sequence, starting with the chain. This will advance
5876 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5877 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5878 LegalizeOp(CallInfo.second);
5880 switch (getTypeAction(CallInfo.first.getValueType())) {
5881 default: assert(0 && "Unknown thing");
5883 Result = CallInfo.first;
5886 ExpandOp(CallInfo.first, Result, Hi);
5892 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5894 SDValue SelectionDAGLegalize::
5895 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5897 bool isCustom = false;
5899 switch (getTypeAction(Op.getValueType())) {
5901 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5902 Op.getValueType())) {
5903 default: assert(0 && "Unknown operation action!");
5904 case TargetLowering::Custom:
5907 case TargetLowering::Legal:
5908 Tmp1 = LegalizeOp(Op);
5909 if (Result.getNode())
5910 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5912 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5915 Tmp1 = TLI.LowerOperation(Result, DAG);
5916 if (Tmp1.getNode()) Result = Tmp1;
5919 case TargetLowering::Expand:
5920 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5922 case TargetLowering::Promote:
5923 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5928 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5931 Tmp1 = PromoteOp(Op);
5933 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5934 Tmp1, DAG.getValueType(Op.getValueType()));
5936 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
5939 if (Result.getNode())
5940 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5942 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5944 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5950 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5952 SDValue SelectionDAGLegalize::
5953 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5954 MVT SourceVT = Source.getValueType();
5955 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5957 // Expand unsupported int-to-fp vector casts by unrolling them.
5958 if (DestTy.isVector()) {
5960 return LegalizeOp(UnrollVectorOp(Source));
5961 MVT DestEltTy = DestTy.getVectorElementType();
5962 if (DestTy.getVectorNumElements() == 1) {
5963 SDValue Scalar = ScalarizeVectorOp(Source);
5964 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5965 DestEltTy, Scalar, dl);
5966 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result);
5969 SplitVectorOp(Source, Lo, Hi);
5970 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5971 DestTy.getVectorNumElements() / 2);
5972 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5974 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5976 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5980 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5981 if (!isSigned && SourceVT != MVT::i32) {
5982 // The integer value loaded will be incorrectly if the 'sign bit' of the
5983 // incoming integer is set. To handle this, we dynamically test to see if
5984 // it is set, and, if so, add a fudge factor.
5988 ExpandOp(Source, Lo, Hi);
5989 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5991 // The comparison for the sign bit will use the entire operand.
5995 // Check to see if the target has a custom way to lower this. If so, use
5996 // it. (Note we've already expanded the operand in this case.)
5997 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5998 default: assert(0 && "This action not implemented for this operation!");
5999 case TargetLowering::Legal:
6000 case TargetLowering::Expand:
6001 break; // This case is handled below.
6002 case TargetLowering::Custom: {
6003 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
6006 return LegalizeOp(NV);
6007 break; // The target decided this was legal after all
6011 // If this is unsigned, and not supported, first perform the conversion to
6012 // signed, then adjust the result if the sign bit is set.
6013 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
6015 SDValue SignSet = DAG.getSetCC(dl,
6016 TLI.getSetCCResultType(Hi.getValueType()),
6017 Hi, DAG.getConstant(0, Hi.getValueType()),
6019 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6020 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6021 SignSet, Four, Zero);
6022 uint64_t FF = 0x5f800000ULL;
6023 if (TLI.isLittleEndian()) FF <<= 32;
6024 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6026 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6027 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6028 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6029 Alignment = std::min(Alignment, 4u);
6031 if (DestTy == MVT::f32)
6032 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6033 PseudoSourceValue::getConstantPool(), 0,
6035 else if (DestTy.bitsGT(MVT::f32))
6036 // FIXME: Avoid the extend by construction the right constantpool?
6037 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
6039 PseudoSourceValue::getConstantPool(), 0,
6040 MVT::f32, false, Alignment);
6042 assert(0 && "Unexpected conversion");
6044 MVT SCVT = SignedConv.getValueType();
6045 if (SCVT != DestTy) {
6046 // Destination type needs to be expanded as well. The FADD now we are
6047 // constructing will be expanded into a libcall.
6048 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6049 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6050 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
6051 SignedConv, SignedConv.getValue(1));
6053 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
6055 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
6058 // Check to see if the target has a custom way to lower this. If so, use it.
6059 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6060 default: assert(0 && "This action not implemented for this operation!");
6061 case TargetLowering::Legal:
6062 case TargetLowering::Expand:
6063 break; // This case is handled below.
6064 case TargetLowering::Custom: {
6065 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6068 return LegalizeOp(NV);
6069 break; // The target decided this was legal after all
6073 // Expand the source, then glue it back together for the call. We must expand
6074 // the source in case it is shared (this pass of legalize must traverse it).
6076 SDValue SrcLo, SrcHi;
6077 ExpandOp(Source, SrcLo, SrcHi);
6078 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6081 RTLIB::Libcall LC = isSigned ?
6082 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6083 RTLIB::getUINTTOFP(SourceVT, DestTy);
6084 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6086 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6088 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6089 if (Result.getValueType() != DestTy && HiPart.getNode())
6090 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6094 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6095 /// INT_TO_FP operation of the specified operand when the target requests that
6096 /// we expand it. At this point, we know that the result and operand types are
6097 /// legal for the target.
6098 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6102 if (Op0.getValueType() == MVT::i32) {
6103 // simple 32-bit [signed|unsigned] integer to float/double expansion
6105 // Get the stack frame index of a 8 byte buffer.
6106 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6108 // word offset constant for Hi/Lo address computation
6109 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6110 // set up Hi and Lo (into buffer) address based on endian
6111 SDValue Hi = StackSlot;
6112 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6113 TLI.getPointerTy(), StackSlot,WordOff);
6114 if (TLI.isLittleEndian())
6117 // if signed map to unsigned space
6120 // constant used to invert sign bit (signed to unsigned mapping)
6121 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6122 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6126 // store the lo of the constructed double - based on integer input
6127 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6128 Op0Mapped, Lo, NULL, 0);
6129 // initial hi portion of constructed double
6130 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6131 // store the hi of the constructed double - biased exponent
6132 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6133 // load the constructed double
6134 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6135 // FP constant to bias correct the final result
6136 SDValue Bias = DAG.getConstantFP(isSigned ?
6137 BitsToDouble(0x4330000080000000ULL)
6138 : BitsToDouble(0x4330000000000000ULL),
6140 // subtract the bias
6141 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6144 // handle final rounding
6145 if (DestVT == MVT::f64) {
6148 } else if (DestVT.bitsLT(MVT::f64)) {
6149 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6150 DAG.getIntPtrConstant(0));
6151 } else if (DestVT.bitsGT(MVT::f64)) {
6152 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6156 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6157 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6159 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6160 Op0, DAG.getConstant(0, Op0.getValueType()),
6162 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6163 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6164 SignSet, Four, Zero);
6166 // If the sign bit of the integer is set, the large number will be treated
6167 // as a negative number. To counteract this, the dynamic code adds an
6168 // offset depending on the data type.
6170 switch (Op0.getValueType().getSimpleVT()) {
6171 default: assert(0 && "Unsupported integer type!");
6172 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6173 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6174 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6175 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6177 if (TLI.isLittleEndian()) FF <<= 32;
6178 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6180 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6181 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6182 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6183 Alignment = std::min(Alignment, 4u);
6185 if (DestVT == MVT::f32)
6186 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6187 PseudoSourceValue::getConstantPool(), 0,
6191 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6192 DAG.getEntryNode(), CPIdx,
6193 PseudoSourceValue::getConstantPool(), 0,
6194 MVT::f32, false, Alignment));
6197 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6200 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6201 /// *INT_TO_FP operation of the specified operand when the target requests that
6202 /// we promote it. At this point, we know that the result and operand types are
6203 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6204 /// operation that takes a larger input.
6205 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6209 // First step, figure out the appropriate *INT_TO_FP operation to use.
6210 MVT NewInTy = LegalOp.getValueType();
6212 unsigned OpToUse = 0;
6214 // Scan for the appropriate larger type to use.
6216 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6217 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6219 // If the target supports SINT_TO_FP of this type, use it.
6220 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6222 case TargetLowering::Legal:
6223 if (!TLI.isTypeLegal(NewInTy))
6224 break; // Can't use this datatype.
6226 case TargetLowering::Custom:
6227 OpToUse = ISD::SINT_TO_FP;
6231 if (isSigned) continue;
6233 // If the target supports UINT_TO_FP of this type, use it.
6234 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6236 case TargetLowering::Legal:
6237 if (!TLI.isTypeLegal(NewInTy))
6238 break; // Can't use this datatype.
6240 case TargetLowering::Custom:
6241 OpToUse = ISD::UINT_TO_FP;
6246 // Otherwise, try a larger type.
6249 // Okay, we found the operation and type to use. Zero extend our input to the
6250 // desired type then run the operation on it.
6251 return DAG.getNode(OpToUse, dl, DestVT,
6252 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6253 dl, NewInTy, LegalOp));
6256 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6257 /// FP_TO_*INT operation of the specified operand when the target requests that
6258 /// we promote it. At this point, we know that the result and operand types are
6259 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6260 /// operation that returns a larger result.
6261 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6265 // First step, figure out the appropriate FP_TO*INT operation to use.
6266 MVT NewOutTy = DestVT;
6268 unsigned OpToUse = 0;
6270 // Scan for the appropriate larger type to use.
6272 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6273 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6275 // If the target supports FP_TO_SINT returning this type, use it.
6276 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6278 case TargetLowering::Legal:
6279 if (!TLI.isTypeLegal(NewOutTy))
6280 break; // Can't use this datatype.
6282 case TargetLowering::Custom:
6283 OpToUse = ISD::FP_TO_SINT;
6288 // If the target supports FP_TO_UINT of this type, use it.
6289 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6291 case TargetLowering::Legal:
6292 if (!TLI.isTypeLegal(NewOutTy))
6293 break; // Can't use this datatype.
6295 case TargetLowering::Custom:
6296 OpToUse = ISD::FP_TO_UINT;
6301 // Otherwise, try a larger type.
6305 // Okay, we found the operation and type to use.
6306 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6308 // If the operation produces an invalid type, it must be custom lowered. Use
6309 // the target lowering hooks to expand it. Just keep the low part of the
6310 // expanded operation, we know that we're truncating anyway.
6311 if (getTypeAction(NewOutTy) == Expand) {
6312 SmallVector<SDValue, 2> Results;
6313 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6314 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6315 Operation = Results[0];
6318 // Truncate the result of the extended FP_TO_*INT operation to the desired
6320 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6323 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6325 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6326 MVT VT = Op.getValueType();
6327 MVT SHVT = TLI.getShiftAmountTy();
6328 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6329 switch (VT.getSimpleVT()) {
6330 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6332 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6333 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6334 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6336 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6337 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6338 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6339 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6340 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6341 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6342 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6343 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6344 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6346 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6347 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6348 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6349 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6350 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6351 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6352 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6353 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6354 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6355 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6356 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6357 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6358 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6359 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6360 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6361 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6362 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6363 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6364 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6365 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6366 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6370 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6372 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6375 default: assert(0 && "Cannot expand this yet!");
6377 static const uint64_t mask[6] = {
6378 0x5555555555555555ULL, 0x3333333333333333ULL,
6379 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6380 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6382 MVT VT = Op.getValueType();
6383 MVT ShVT = TLI.getShiftAmountTy();
6384 unsigned len = VT.getSizeInBits();
6385 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6386 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6387 unsigned EltSize = VT.isVector() ?
6388 VT.getVectorElementType().getSizeInBits() : len;
6389 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6390 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6391 Op = DAG.getNode(ISD::ADD, dl, VT,
6392 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
6393 DAG.getNode(ISD::AND, dl, VT,
6394 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6400 // for now, we do this:
6401 // x = x | (x >> 1);
6402 // x = x | (x >> 2);
6404 // x = x | (x >>16);
6405 // x = x | (x >>32); // for 64-bit input
6406 // return popcount(~x);
6408 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6409 MVT VT = Op.getValueType();
6410 MVT ShVT = TLI.getShiftAmountTy();
6411 unsigned len = VT.getSizeInBits();
6412 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6413 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6414 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6415 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
6417 Op = DAG.getNOT(dl, Op, VT);
6418 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6421 // for now, we use: { return popcount(~x & (x - 1)); }
6422 // unless the target has ctlz but not ctpop, in which case we use:
6423 // { return 32 - nlz(~x & (x-1)); }
6424 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6425 MVT VT = Op.getValueType();
6426 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6427 DAG.getNOT(dl, Op, VT),
6428 DAG.getNode(ISD::SUB, dl, VT, Op,
6429 DAG.getConstant(1, VT)));
6430 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6431 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6432 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6433 return DAG.getNode(ISD::SUB, dl, VT,
6434 DAG.getConstant(VT.getSizeInBits(), VT),
6435 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6436 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6441 /// ExpandOp - Expand the specified SDValue into its two component pieces
6442 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6443 /// LegalizedNodes map is filled in for any results that are not expanded, the
6444 /// ExpandedNodes map is filled in for any results that are expanded, and the
6445 /// Lo/Hi values are returned.
6446 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6447 MVT VT = Op.getValueType();
6448 MVT NVT = TLI.getTypeToTransformTo(VT);
6449 SDNode *Node = Op.getNode();
6450 DebugLoc dl = Node->getDebugLoc();
6451 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6452 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6453 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6455 // See if we already expanded it.
6456 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6457 = ExpandedNodes.find(Op);
6458 if (I != ExpandedNodes.end()) {
6459 Lo = I->second.first;
6460 Hi = I->second.second;
6464 switch (Node->getOpcode()) {
6465 case ISD::CopyFromReg:
6466 assert(0 && "CopyFromReg must be legal!");
6467 case ISD::FP_ROUND_INREG:
6468 if (VT == MVT::ppcf128 &&
6469 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6470 TargetLowering::Custom) {
6471 SDValue SrcLo, SrcHi, Src;
6472 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6473 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6474 SDValue Result = TLI.LowerOperation(
6475 DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
6476 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6477 Lo = Result.getNode()->getOperand(0);
6478 Hi = Result.getNode()->getOperand(1);
6484 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6486 assert(0 && "Do not know how to expand this operator!");
6488 case ISD::EXTRACT_ELEMENT:
6489 ExpandOp(Node->getOperand(0), Lo, Hi);
6490 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6491 return ExpandOp(Hi, Lo, Hi);
6492 return ExpandOp(Lo, Lo, Hi);
6493 case ISD::EXTRACT_VECTOR_ELT:
6494 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6495 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6496 return ExpandOp(Lo, Lo, Hi);
6498 Lo = DAG.getUNDEF(NVT);
6499 Hi = DAG.getUNDEF(NVT);
6501 case ISD::Constant: {
6502 unsigned NVTBits = NVT.getSizeInBits();
6503 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6504 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6505 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6508 case ISD::ConstantFP: {
6509 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6510 if (CFP->getValueType(0) == MVT::ppcf128) {
6511 APInt api = CFP->getValueAPF().bitcastToAPInt();
6512 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6514 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6518 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6519 if (getTypeAction(Lo.getValueType()) == Expand)
6520 ExpandOp(Lo, Lo, Hi);
6523 case ISD::BUILD_PAIR:
6524 // Return the operands.
6525 Lo = Node->getOperand(0);
6526 Hi = Node->getOperand(1);
6529 case ISD::MERGE_VALUES:
6530 if (Node->getNumValues() == 1) {
6531 ExpandOp(Op.getOperand(0), Lo, Hi);
6534 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6535 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6536 Op.getValue(1).getValueType() == MVT::Other &&
6537 "unhandled MERGE_VALUES");
6538 ExpandOp(Op.getOperand(0), Lo, Hi);
6539 // Remember that we legalized the chain.
6540 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6543 case ISD::SIGN_EXTEND_INREG:
6544 ExpandOp(Node->getOperand(0), Lo, Hi);
6545 // sext_inreg the low part if needed.
6546 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6548 // The high part gets the sign extension from the lo-part. This handles
6549 // things like sextinreg V:i64 from i8.
6550 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6551 DAG.getConstant(NVT.getSizeInBits()-1,
6552 TLI.getShiftAmountTy()));
6556 ExpandOp(Node->getOperand(0), Lo, Hi);
6557 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6558 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6564 ExpandOp(Node->getOperand(0), Lo, Hi);
6565 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6566 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6567 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6568 Hi = DAG.getConstant(0, NVT);
6572 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6573 ExpandOp(Node->getOperand(0), Lo, Hi);
6574 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6575 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6576 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6578 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6579 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6581 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6582 Hi = DAG.getConstant(0, NVT);
6587 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6588 ExpandOp(Node->getOperand(0), Lo, Hi);
6589 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6590 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6591 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6593 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6594 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6596 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6597 Hi = DAG.getConstant(0, NVT);
6602 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6603 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6604 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
6605 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
6607 // Remember that we legalized the chain.
6608 Hi = LegalizeOp(Hi);
6609 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6610 if (TLI.isBigEndian())
6616 LoadSDNode *LD = cast<LoadSDNode>(Node);
6617 SDValue Ch = LD->getChain(); // Legalize the chain.
6618 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6619 ISD::LoadExtType ExtType = LD->getExtensionType();
6620 const Value *SV = LD->getSrcValue();
6621 int SVOffset = LD->getSrcValueOffset();
6622 unsigned Alignment = LD->getAlignment();
6623 bool isVolatile = LD->isVolatile();
6625 if (ExtType == ISD::NON_EXTLOAD) {
6626 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6627 isVolatile, Alignment);
6628 if (VT == MVT::f32 || VT == MVT::f64) {
6629 // f32->i32 or f64->i64 one to one expansion.
6630 // Remember that we legalized the chain.
6631 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6632 // Recursively expand the new load.
6633 if (getTypeAction(NVT) == Expand)
6634 ExpandOp(Lo, Lo, Hi);
6638 // Increment the pointer to the other half.
6639 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6640 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6641 DAG.getIntPtrConstant(IncrementSize));
6642 SVOffset += IncrementSize;
6643 Alignment = MinAlign(Alignment, IncrementSize);
6644 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6645 isVolatile, Alignment);
6647 // Build a factor node to remember that this load is independent of the
6649 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6652 // Remember that we legalized the chain.
6653 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6654 if (TLI.isBigEndian())
6657 MVT EVT = LD->getMemoryVT();
6659 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6660 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6661 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6662 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6663 SVOffset, isVolatile, Alignment);
6664 // Remember that we legalized the chain.
6665 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6666 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6671 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6672 SVOffset, isVolatile, Alignment);
6674 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6675 SVOffset, EVT, isVolatile,
6678 // Remember that we legalized the chain.
6679 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6681 if (ExtType == ISD::SEXTLOAD) {
6682 // The high part is obtained by SRA'ing all but one of the bits of the
6684 unsigned LoSize = Lo.getValueType().getSizeInBits();
6685 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6686 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6687 } else if (ExtType == ISD::ZEXTLOAD) {
6688 // The high part is just a zero.
6689 Hi = DAG.getConstant(0, NVT);
6690 } else /* if (ExtType == ISD::EXTLOAD) */ {
6691 // The high part is undefined.
6692 Hi = DAG.getUNDEF(NVT);
6699 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6700 SDValue LL, LH, RL, RH;
6701 ExpandOp(Node->getOperand(0), LL, LH);
6702 ExpandOp(Node->getOperand(1), RL, RH);
6703 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6704 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6708 SDValue LL, LH, RL, RH;
6709 ExpandOp(Node->getOperand(1), LL, LH);
6710 ExpandOp(Node->getOperand(2), RL, RH);
6711 if (getTypeAction(NVT) == Expand)
6712 NVT = TLI.getTypeToExpandTo(NVT);
6713 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6715 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6718 case ISD::SELECT_CC: {
6719 SDValue TL, TH, FL, FH;
6720 ExpandOp(Node->getOperand(2), TL, TH);
6721 ExpandOp(Node->getOperand(3), FL, FH);
6722 if (getTypeAction(NVT) == Expand)
6723 NVT = TLI.getTypeToExpandTo(NVT);
6724 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6725 Node->getOperand(1), TL, FL, Node->getOperand(4));
6727 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6728 Node->getOperand(1), TH, FH, Node->getOperand(4));
6731 case ISD::ANY_EXTEND:
6732 // The low part is any extension of the input (which degenerates to a copy).
6733 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6734 // The high part is undefined.
6735 Hi = DAG.getUNDEF(NVT);
6737 case ISD::SIGN_EXTEND: {
6738 // The low part is just a sign extension of the input (which degenerates to
6740 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6742 // The high part is obtained by SRA'ing all but one of the bits of the lo
6744 unsigned LoSize = Lo.getValueType().getSizeInBits();
6745 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6746 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6749 case ISD::ZERO_EXTEND:
6750 // The low part is just a zero extension of the input (which degenerates to
6752 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6754 // The high part is just a zero.
6755 Hi = DAG.getConstant(0, NVT);
6758 case ISD::TRUNCATE: {
6759 // The input value must be larger than this value. Expand *it*.
6761 ExpandOp(Node->getOperand(0), NewLo, Hi);
6763 // The low part is now either the right size, or it is closer. If not the
6764 // right size, make an illegal truncate so we recursively expand it.
6765 if (NewLo.getValueType() != Node->getValueType(0))
6766 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6767 ExpandOp(NewLo, Lo, Hi);
6771 case ISD::BIT_CONVERT: {
6773 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6774 // If the target wants to, allow it to lower this itself.
6775 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6776 case Expand: assert(0 && "cannot expand FP!");
6777 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6778 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6780 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6783 // f32 / f64 must be expanded to i32 / i64.
6784 if (VT == MVT::f32 || VT == MVT::f64) {
6785 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6786 if (getTypeAction(NVT) == Expand)
6787 ExpandOp(Lo, Lo, Hi);
6791 // If source operand will be expanded to the same type as VT, i.e.
6792 // i64 <- f64, i32 <- f32, expand the source operand instead.
6793 MVT VT0 = Node->getOperand(0).getValueType();
6794 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6795 ExpandOp(Node->getOperand(0), Lo, Hi);
6799 // Turn this into a load/store pair by default.
6800 if (Tmp.getNode() == 0)
6801 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6803 ExpandOp(Tmp, Lo, Hi);
6807 case ISD::READCYCLECOUNTER: {
6808 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6809 TargetLowering::Custom &&
6810 "Must custom expand ReadCycleCounter");
6811 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6812 assert(Tmp.getNode() && "Node must be custom expanded!");
6813 ExpandOp(Tmp.getValue(0), Lo, Hi);
6814 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6815 LegalizeOp(Tmp.getValue(1)));
6819 case ISD::ATOMIC_CMP_SWAP: {
6820 // This operation does not need a loop.
6821 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6822 assert(Tmp.getNode() && "Node must be custom expanded!");
6823 ExpandOp(Tmp.getValue(0), Lo, Hi);
6824 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6825 LegalizeOp(Tmp.getValue(1)));
6829 case ISD::ATOMIC_LOAD_ADD:
6830 case ISD::ATOMIC_LOAD_SUB:
6831 case ISD::ATOMIC_LOAD_AND:
6832 case ISD::ATOMIC_LOAD_OR:
6833 case ISD::ATOMIC_LOAD_XOR:
6834 case ISD::ATOMIC_LOAD_NAND:
6835 case ISD::ATOMIC_SWAP: {
6836 // These operations require a loop to be generated. We can't do that yet,
6837 // so substitute a target-dependent pseudo and expand that later.
6838 SDValue In2Lo, In2Hi, In2;
6839 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6840 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6841 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6843 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6844 Op.getOperand(0), Op.getOperand(1), In2,
6845 Anode->getSrcValue(), Anode->getAlignment());
6846 SDValue Result = TLI.LowerOperation(Replace, DAG);
6847 ExpandOp(Result.getValue(0), Lo, Hi);
6848 // Remember that we legalized the chain.
6849 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6853 // These operators cannot be expanded directly, emit them as calls to
6854 // library functions.
6855 case ISD::FP_TO_SINT: {
6856 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6858 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6859 case Expand: assert(0 && "cannot expand FP!");
6860 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6861 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6864 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6866 // Now that the custom expander is done, expand the result, which is still
6869 ExpandOp(Op, Lo, Hi);
6874 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6876 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6877 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6881 case ISD::FP_TO_UINT: {
6882 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6884 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6885 case Expand: assert(0 && "cannot expand FP!");
6886 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6887 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6890 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6892 // Now that the custom expander is done, expand the result.
6894 ExpandOp(Op, Lo, Hi);
6899 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6901 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6902 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6907 // If the target wants custom lowering, do so.
6908 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6909 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6910 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6911 Op = TLI.LowerOperation(Op, DAG);
6913 // Now that the custom expander is done, expand the result, which is
6915 ExpandOp(Op, Lo, Hi);
6920 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6921 // this X << 1 as X+X.
6922 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6923 if (ShAmt->getAPIntValue() == 1 &&
6924 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6925 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6926 SDValue LoOps[2], HiOps[3];
6927 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6928 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6929 LoOps[1] = LoOps[0];
6930 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6932 HiOps[1] = HiOps[0];
6933 HiOps[2] = Lo.getValue(1);
6934 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6939 // If we can emit an efficient shift operation, do so now.
6940 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6943 // If this target supports SHL_PARTS, use it.
6944 TargetLowering::LegalizeAction Action =
6945 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6946 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6947 Action == TargetLowering::Custom) {
6948 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6949 ShiftAmt, Lo, Hi, dl);
6953 // Otherwise, emit a libcall.
6954 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6959 // If the target wants custom lowering, do so.
6960 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6961 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6962 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
6963 Op = TLI.LowerOperation(Op, DAG);
6965 // Now that the custom expander is done, expand the result, which is
6967 ExpandOp(Op, Lo, Hi);
6972 // If we can emit an efficient shift operation, do so now.
6973 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6976 // If this target supports SRA_PARTS, use it.
6977 TargetLowering::LegalizeAction Action =
6978 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6979 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6980 Action == TargetLowering::Custom) {
6981 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6982 ShiftAmt, Lo, Hi, dl);
6986 // Otherwise, emit a libcall.
6987 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6992 // If the target wants custom lowering, do so.
6993 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6994 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6995 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6996 Op = TLI.LowerOperation(Op, DAG);
6998 // Now that the custom expander is done, expand the result, which is
7000 ExpandOp(Op, Lo, Hi);
7005 // If we can emit an efficient shift operation, do so now.
7006 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
7009 // If this target supports SRL_PARTS, use it.
7010 TargetLowering::LegalizeAction Action =
7011 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
7012 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
7013 Action == TargetLowering::Custom) {
7014 ExpandShiftParts(ISD::SRL_PARTS,
7015 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
7019 // Otherwise, emit a libcall.
7020 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
7026 // If the target wants to custom expand this, let them.
7027 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
7028 TargetLowering::Custom) {
7029 SDValue Result = TLI.LowerOperation(Op, DAG);
7030 if (Result.getNode()) {
7031 ExpandOp(Result, Lo, Hi);
7035 // Expand the subcomponents.
7036 SDValue LHSL, LHSH, RHSL, RHSH;
7037 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7038 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7039 SDValue LoOps[2], HiOps[3];
7045 //cascaded check to see if any smaller size has a a carry flag.
7046 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
7047 bool hasCarry = false;
7048 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
7049 MVT AVT = MVT::getIntegerVT(BitSize);
7050 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
7057 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7058 if (Node->getOpcode() == ISD::ADD) {
7059 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7060 HiOps[2] = Lo.getValue(1);
7061 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7063 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7064 HiOps[2] = Lo.getValue(1);
7065 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7069 if (Node->getOpcode() == ISD::ADD) {
7070 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7071 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7072 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7073 Lo, LoOps[0], ISD::SETULT);
7074 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7075 DAG.getConstant(1, NVT),
7076 DAG.getConstant(0, NVT));
7077 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7078 Lo, LoOps[1], ISD::SETULT);
7079 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7080 DAG.getConstant(1, NVT),
7082 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7084 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7085 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7086 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7087 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7088 DAG.getConstant(1, NVT),
7089 DAG.getConstant(0, NVT));
7090 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7098 // Expand the subcomponents.
7099 SDValue LHSL, LHSH, RHSL, RHSH;
7100 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7101 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7102 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7103 SDValue LoOps[2] = { LHSL, RHSL };
7104 SDValue HiOps[3] = { LHSH, RHSH };
7106 if (Node->getOpcode() == ISD::ADDC) {
7107 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7108 HiOps[2] = Lo.getValue(1);
7109 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7111 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7112 HiOps[2] = Lo.getValue(1);
7113 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7115 // Remember that we legalized the flag.
7116 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7121 // Expand the subcomponents.
7122 SDValue LHSL, LHSH, RHSL, RHSH;
7123 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7124 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7125 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7126 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7127 SDValue HiOps[3] = { LHSH, RHSH };
7129 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7130 HiOps[2] = Lo.getValue(1);
7131 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7133 // Remember that we legalized the flag.
7134 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7138 // If the target wants to custom expand this, let them.
7139 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7140 SDValue New = TLI.LowerOperation(Op, DAG);
7141 if (New.getNode()) {
7142 ExpandOp(New, Lo, Hi);
7147 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7148 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7149 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7150 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7151 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7152 SDValue LL, LH, RL, RH;
7153 ExpandOp(Node->getOperand(0), LL, LH);
7154 ExpandOp(Node->getOperand(1), RL, RH);
7155 unsigned OuterBitSize = Op.getValueSizeInBits();
7156 unsigned InnerBitSize = RH.getValueSizeInBits();
7157 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7158 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7159 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7160 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7161 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7162 // The inputs are both zero-extended.
7164 // We can emit a umul_lohi.
7165 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7166 Hi = SDValue(Lo.getNode(), 1);
7170 // We can emit a mulhu+mul.
7171 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7172 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7176 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7177 // The input values are both sign-extended.
7179 // We can emit a smul_lohi.
7180 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7181 Hi = SDValue(Lo.getNode(), 1);
7185 // We can emit a mulhs+mul.
7186 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7187 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7192 // Lo,Hi = umul LHS, RHS.
7193 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7194 DAG.getVTList(NVT, NVT), LL, RL);
7196 Hi = UMulLOHI.getValue(1);
7197 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7198 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7199 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7200 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7204 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7205 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7206 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7207 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7208 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7209 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7214 // If nothing else, we can make a libcall.
7215 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7219 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7222 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7225 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7228 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7232 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7235 RTLIB::ADD_PPCF128),
7239 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7242 RTLIB::SUB_PPCF128),
7246 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7249 RTLIB::MUL_PPCF128),
7253 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7256 RTLIB::DIV_PPCF128),
7259 case ISD::FP_EXTEND: {
7260 if (VT == MVT::ppcf128) {
7261 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7262 Node->getOperand(0).getValueType()==MVT::f64);
7263 const uint64_t zero = 0;
7264 if (Node->getOperand(0).getValueType()==MVT::f32)
7265 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7267 Hi = Node->getOperand(0);
7268 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7271 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7272 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7273 Lo = ExpandLibCall(LC, Node, true, Hi);
7276 case ISD::FP_ROUND: {
7277 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7279 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7280 Lo = ExpandLibCall(LC, Node, true, Hi);
7295 case ISD::FNEARBYINT:
7298 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7299 switch(Node->getOpcode()) {
7301 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7302 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7305 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7306 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7309 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7310 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7313 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7314 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7317 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7318 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7321 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7322 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7325 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7326 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7329 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7330 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7333 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7334 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7337 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7338 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7341 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7342 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7345 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7346 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7348 case ISD::FNEARBYINT:
7349 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7350 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7353 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7354 RTLIB::POW_PPCF128);
7357 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7358 RTLIB::POWI_PPCF128);
7360 default: assert(0 && "Unreachable!");
7362 Lo = ExpandLibCall(LC, Node, false, Hi);
7366 if (VT == MVT::ppcf128) {
7368 ExpandOp(Node->getOperand(0), Lo, Tmp);
7369 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7370 // lo = hi==fabs(hi) ? lo : -lo;
7371 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7372 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7373 DAG.getCondCode(ISD::SETEQ));
7376 SDValue Mask = (VT == MVT::f64)
7377 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7378 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7379 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7380 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7381 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7382 if (getTypeAction(NVT) == Expand)
7383 ExpandOp(Lo, Lo, Hi);
7387 if (VT == MVT::ppcf128) {
7388 ExpandOp(Node->getOperand(0), Lo, Hi);
7389 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7390 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7393 SDValue Mask = (VT == MVT::f64)
7394 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7395 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7396 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7397 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7398 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7399 if (getTypeAction(NVT) == Expand)
7400 ExpandOp(Lo, Lo, Hi);
7403 case ISD::FCOPYSIGN: {
7404 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7405 if (getTypeAction(NVT) == Expand)
7406 ExpandOp(Lo, Lo, Hi);
7409 case ISD::SINT_TO_FP:
7410 case ISD::UINT_TO_FP: {
7411 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7412 MVT SrcVT = Node->getOperand(0).getValueType();
7414 // Promote the operand if needed. Do this before checking for
7415 // ppcf128 so conversions of i16 and i8 work.
7416 if (getTypeAction(SrcVT) == Promote) {
7417 SDValue Tmp = PromoteOp(Node->getOperand(0));
7419 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7420 DAG.getValueType(SrcVT))
7421 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7422 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7423 SrcVT = Node->getOperand(0).getValueType();
7426 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7427 static const uint64_t zero = 0;
7429 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7430 Node->getOperand(0)));
7431 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7433 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7434 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7435 Node->getOperand(0)));
7436 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7437 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7438 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7439 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7440 MVT::ppcf128, Node->getOperand(0),
7441 DAG.getConstant(0, MVT::i32),
7442 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7444 APFloat(APInt(128, 2, TwoE32)),
7447 DAG.getCondCode(ISD::SETLT)),
7452 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7453 // si64->ppcf128 done by libcall, below
7454 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7455 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7456 Node->getOperand(0)), Lo, Hi);
7457 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7458 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7459 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7460 Node->getOperand(0),
7461 DAG.getConstant(0, MVT::i64),
7462 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7464 APFloat(APInt(128, 2, TwoE64)),
7467 DAG.getCondCode(ISD::SETLT)),
7472 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7473 Node->getOperand(0), dl);
7474 if (getTypeAction(Lo.getValueType()) == Expand)
7475 // float to i32 etc. can be 'expanded' to a single node.
7476 ExpandOp(Lo, Lo, Hi);
7481 // Make sure the resultant values have been legalized themselves, unless this
7482 // is a type that requires multi-step expansion.
7483 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7484 Lo = LegalizeOp(Lo);
7486 // Don't legalize the high part if it is expanded to a single node.
7487 Hi = LegalizeOp(Hi);
7490 // Remember in a map if the values will be reused later.
7492 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7493 assert(isNew && "Value already expanded?!?");
7497 /// SplitVectorOp - Given an operand of vector type, break it down into
7498 /// two smaller values, still of vector type.
7499 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7501 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7502 SDNode *Node = Op.getNode();
7503 DebugLoc dl = Node->getDebugLoc();
7504 unsigned NumElements = Op.getValueType().getVectorNumElements();
7505 assert(NumElements > 1 && "Cannot split a single element vector!");
7507 MVT NewEltVT = Op.getValueType().getVectorElementType();
7509 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7510 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7512 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7513 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7515 // See if we already split it.
7516 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7517 = SplitNodes.find(Op);
7518 if (I != SplitNodes.end()) {
7519 Lo = I->second.first;
7520 Hi = I->second.second;
7524 switch (Node->getOpcode()) {
7529 assert(0 && "Unhandled operation in SplitVectorOp!");
7531 Lo = DAG.getUNDEF(NewVT_Lo);
7532 Hi = DAG.getUNDEF(NewVT_Hi);
7534 case ISD::BUILD_PAIR:
7535 Lo = Node->getOperand(0);
7536 Hi = Node->getOperand(1);
7538 case ISD::INSERT_VECTOR_ELT: {
7539 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7540 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7541 unsigned Index = Idx->getZExtValue();
7542 SDValue ScalarOp = Node->getOperand(1);
7543 if (Index < NewNumElts_Lo)
7544 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7545 DAG.getIntPtrConstant(Index));
7547 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7548 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7551 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7552 Node->getOperand(1),
7553 Node->getOperand(2), dl);
7554 SplitVectorOp(Tmp, Lo, Hi);
7557 case ISD::VECTOR_SHUFFLE: {
7558 // Build the low part.
7559 SDValue Mask = Node->getOperand(2);
7560 SmallVector<SDValue, 8> Ops;
7561 MVT PtrVT = TLI.getPointerTy();
7563 // Insert all of the elements from the input that are needed. We use
7564 // buildvector of extractelement here because the input vectors will have
7565 // to be legalized, so this makes the code simpler.
7566 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7567 SDValue IdxNode = Mask.getOperand(i);
7568 if (IdxNode.getOpcode() == ISD::UNDEF) {
7569 Ops.push_back(DAG.getUNDEF(NewEltVT));
7572 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7573 SDValue InVec = Node->getOperand(0);
7574 if (Idx >= NumElements) {
7575 InVec = Node->getOperand(1);
7578 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7579 DAG.getConstant(Idx, PtrVT)));
7581 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
7584 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7585 SDValue IdxNode = Mask.getOperand(i);
7586 if (IdxNode.getOpcode() == ISD::UNDEF) {
7587 Ops.push_back(DAG.getUNDEF(NewEltVT));
7590 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7591 SDValue InVec = Node->getOperand(0);
7592 if (Idx >= NumElements) {
7593 InVec = Node->getOperand(1);
7596 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7597 DAG.getConstant(Idx, PtrVT)));
7599 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
7602 case ISD::BUILD_VECTOR: {
7603 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7604 Node->op_begin()+NewNumElts_Lo);
7605 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
7607 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7609 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
7612 case ISD::CONCAT_VECTORS: {
7613 // FIXME: Handle non-power-of-two vectors?
7614 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7615 if (NewNumSubvectors == 1) {
7616 Lo = Node->getOperand(0);
7617 Hi = Node->getOperand(1);
7619 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7620 Node->op_begin()+NewNumSubvectors);
7621 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7622 &LoOps[0], LoOps.size());
7624 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7626 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7627 &HiOps[0], HiOps.size());
7631 case ISD::EXTRACT_SUBVECTOR: {
7632 SDValue Vec = Op.getOperand(0);
7633 SDValue Idx = Op.getOperand(1);
7634 MVT IdxVT = Idx.getValueType();
7636 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7637 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7639 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7640 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7643 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7644 DAG.getConstant(NewNumElts_Lo, IdxVT));
7645 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7650 SDValue Cond = Node->getOperand(0);
7652 SDValue LL, LH, RL, RH;
7653 SplitVectorOp(Node->getOperand(1), LL, LH);
7654 SplitVectorOp(Node->getOperand(2), RL, RH);
7656 if (Cond.getValueType().isVector()) {
7657 // Handle a vector merge.
7659 SplitVectorOp(Cond, CL, CH);
7660 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7661 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7663 // Handle a simple select with vector operands.
7664 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7665 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7669 case ISD::SELECT_CC: {
7670 SDValue CondLHS = Node->getOperand(0);
7671 SDValue CondRHS = Node->getOperand(1);
7672 SDValue CondCode = Node->getOperand(4);
7674 SDValue LL, LH, RL, RH;
7675 SplitVectorOp(Node->getOperand(2), LL, LH);
7676 SplitVectorOp(Node->getOperand(3), RL, RH);
7678 // Handle a simple select with vector operands.
7679 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7681 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7686 SDValue LL, LH, RL, RH;
7687 SplitVectorOp(Node->getOperand(0), LL, LH);
7688 SplitVectorOp(Node->getOperand(1), RL, RH);
7689 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7690 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7712 SDValue LL, LH, RL, RH;
7713 SplitVectorOp(Node->getOperand(0), LL, LH);
7714 SplitVectorOp(Node->getOperand(1), RL, RH);
7716 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7717 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7723 SplitVectorOp(Node->getOperand(0), L, H);
7725 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7726 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7742 case ISD::FP_TO_SINT:
7743 case ISD::FP_TO_UINT:
7744 case ISD::SINT_TO_FP:
7745 case ISD::UINT_TO_FP:
7747 case ISD::ANY_EXTEND:
7748 case ISD::SIGN_EXTEND:
7749 case ISD::ZERO_EXTEND:
7750 case ISD::FP_EXTEND: {
7752 SplitVectorOp(Node->getOperand(0), L, H);
7754 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7755 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7758 case ISD::CONVERT_RNDSAT: {
7759 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7761 SplitVectorOp(Node->getOperand(0), L, H);
7762 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7763 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7764 SDValue STyOpL = DAG.getValueType(L.getValueType());
7765 SDValue STyOpH = DAG.getValueType(H.getValueType());
7767 SDValue RndOp = Node->getOperand(3);
7768 SDValue SatOp = Node->getOperand(4);
7770 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
7771 RndOp, SatOp, CvtCode);
7772 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
7773 RndOp, SatOp, CvtCode);
7777 LoadSDNode *LD = cast<LoadSDNode>(Node);
7778 SDValue Ch = LD->getChain();
7779 SDValue Ptr = LD->getBasePtr();
7780 ISD::LoadExtType ExtType = LD->getExtensionType();
7781 const Value *SV = LD->getSrcValue();
7782 int SVOffset = LD->getSrcValueOffset();
7783 MVT MemoryVT = LD->getMemoryVT();
7784 unsigned Alignment = LD->getAlignment();
7785 bool isVolatile = LD->isVolatile();
7787 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7788 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7790 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7791 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7792 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7794 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7795 NewVT_Lo, Ch, Ptr, Offset,
7796 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7797 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7798 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7799 DAG.getIntPtrConstant(IncrementSize));
7800 SVOffset += IncrementSize;
7801 Alignment = MinAlign(Alignment, IncrementSize);
7802 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7803 NewVT_Hi, Ch, Ptr, Offset,
7804 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7806 // Build a factor node to remember that this load is independent of the
7808 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7811 // Remember that we legalized the chain.
7812 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7815 case ISD::BIT_CONVERT: {
7816 // We know the result is a vector. The input may be either a vector or a
7818 SDValue InOp = Node->getOperand(0);
7819 if (!InOp.getValueType().isVector() ||
7820 InOp.getValueType().getVectorNumElements() == 1) {
7821 // The input is a scalar or single-element vector.
7822 // Lower to a store/load so that it can be split.
7823 // FIXME: this could be improved probably.
7824 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7825 Op.getValueType().getTypeForMVT());
7826 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7827 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7829 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7831 PseudoSourceValue::getFixedStack(FI), 0);
7832 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7833 PseudoSourceValue::getFixedStack(FI), 0);
7835 // Split the vector and convert each of the pieces now.
7836 SplitVectorOp(InOp, Lo, Hi);
7837 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7838 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7843 // Remember in a map if the values will be reused later.
7845 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7846 assert(isNew && "Value already split?!?");
7851 /// ScalarizeVectorOp - Given an operand of single-element vector type
7852 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7853 /// scalar (e.g. f32) value.
7854 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7855 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7856 SDNode *Node = Op.getNode();
7857 DebugLoc dl = Node->getDebugLoc();
7858 MVT NewVT = Op.getValueType().getVectorElementType();
7859 assert(Op.getValueType().getVectorNumElements() == 1);
7861 // See if we already scalarized it.
7862 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7863 if (I != ScalarizedNodes.end()) return I->second;
7866 switch (Node->getOpcode()) {
7869 Node->dump(&DAG); cerr << "\n";
7871 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7888 Result = DAG.getNode(Node->getOpcode(), dl,
7890 ScalarizeVectorOp(Node->getOperand(0)),
7891 ScalarizeVectorOp(Node->getOperand(1)));
7903 case ISD::FP_TO_SINT:
7904 case ISD::FP_TO_UINT:
7905 case ISD::SINT_TO_FP:
7906 case ISD::UINT_TO_FP:
7907 case ISD::SIGN_EXTEND:
7908 case ISD::ZERO_EXTEND:
7909 case ISD::ANY_EXTEND:
7911 case ISD::FP_EXTEND:
7912 Result = DAG.getNode(Node->getOpcode(), dl,
7914 ScalarizeVectorOp(Node->getOperand(0)));
7916 case ISD::CONVERT_RNDSAT: {
7917 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7918 Result = DAG.getConvertRndSat(NewVT, dl, Op0,
7919 DAG.getValueType(NewVT),
7920 DAG.getValueType(Op0.getValueType()),
7921 Node->getOperand(3),
7922 Node->getOperand(4),
7923 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7928 Result = DAG.getNode(Node->getOpcode(), dl,
7930 ScalarizeVectorOp(Node->getOperand(0)),
7931 Node->getOperand(1));
7934 LoadSDNode *LD = cast<LoadSDNode>(Node);
7935 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7936 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7937 ISD::LoadExtType ExtType = LD->getExtensionType();
7938 const Value *SV = LD->getSrcValue();
7939 int SVOffset = LD->getSrcValueOffset();
7940 MVT MemoryVT = LD->getMemoryVT();
7941 unsigned Alignment = LD->getAlignment();
7942 bool isVolatile = LD->isVolatile();
7944 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7945 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7947 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7948 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7949 MemoryVT.getVectorElementType(),
7950 isVolatile, Alignment);
7952 // Remember that we legalized the chain.
7953 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7956 case ISD::BUILD_VECTOR:
7957 Result = Node->getOperand(0);
7959 case ISD::INSERT_VECTOR_ELT:
7960 // Returning the inserted scalar element.
7961 Result = Node->getOperand(1);
7963 case ISD::CONCAT_VECTORS:
7964 assert(Node->getOperand(0).getValueType() == NewVT &&
7965 "Concat of non-legal vectors not yet supported!");
7966 Result = Node->getOperand(0);
7968 case ISD::VECTOR_SHUFFLE: {
7969 // Figure out if the scalar is the LHS or RHS and return it.
7970 SDValue EltNum = Node->getOperand(2).getOperand(0);
7971 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7972 Result = ScalarizeVectorOp(Node->getOperand(1));
7974 Result = ScalarizeVectorOp(Node->getOperand(0));
7977 case ISD::EXTRACT_SUBVECTOR:
7978 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7979 Node->getOperand(0), Node->getOperand(1));
7981 case ISD::BIT_CONVERT: {
7982 SDValue Op0 = Op.getOperand(0);
7983 if (Op0.getValueType().getVectorNumElements() == 1)
7984 Op0 = ScalarizeVectorOp(Op0);
7985 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7989 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7990 ScalarizeVectorOp(Op.getOperand(1)),
7991 ScalarizeVectorOp(Op.getOperand(2)));
7993 case ISD::SELECT_CC:
7994 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7995 Node->getOperand(1),
7996 ScalarizeVectorOp(Op.getOperand(2)),
7997 ScalarizeVectorOp(Op.getOperand(3)),
7998 Node->getOperand(4));
8001 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
8002 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
8003 Result = DAG.getNode(ISD::SETCC, dl,
8004 TLI.getSetCCResultType(Op0.getValueType()),
8005 Op0, Op1, Op.getOperand(2));
8006 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
8007 DAG.getConstant(-1ULL, NewVT),
8008 DAG.getConstant(0ULL, NewVT));
8013 if (TLI.isTypeLegal(NewVT))
8014 Result = LegalizeOp(Result);
8015 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
8016 assert(isNew && "Value already scalarized?");
8022 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
8023 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
8024 if (I != WidenNodes.end()) return I->second;
8026 MVT VT = Op.getValueType();
8027 assert(VT.isVector() && "Cannot widen non-vector type!");
8030 SDNode *Node = Op.getNode();
8031 DebugLoc dl = Node->getDebugLoc();
8032 MVT EVT = VT.getVectorElementType();
8034 unsigned NumElts = VT.getVectorNumElements();
8035 unsigned NewNumElts = WidenVT.getVectorNumElements();
8036 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
8037 assert(NewNumElts < 17);
8039 // When widen is called, it is assumed that it is more efficient to use a
8040 // wide type. The default action is to widen to operation to a wider legal
8041 // vector type and then do the operation if it is legal by calling LegalizeOp
8042 // again. If there is no vector equivalent, we will unroll the operation, do
8043 // it, and rebuild the vector. If most of the operations are vectorizible to
8044 // the legal type, the resulting code will be more efficient. If this is not
8045 // the case, the resulting code will preform badly as we end up generating
8046 // code to pack/unpack the results. It is the function that calls widen
8047 // that is responsible for seeing this doesn't happen.
8048 switch (Node->getOpcode()) {
8053 assert(0 && "Unexpected operation in WidenVectorOp!");
8055 case ISD::CopyFromReg:
8056 assert(0 && "CopyFromReg doesn't need widening!");
8058 case ISD::ConstantFP:
8059 // To build a vector of these elements, clients should call BuildVector
8060 // and with each element instead of creating a node with a vector type
8061 assert(0 && "Unexpected operation in WidenVectorOp!");
8063 // Variable Arguments with vector types doesn't make any sense to me
8064 assert(0 && "Unexpected operation in WidenVectorOp!");
8067 Result = DAG.getUNDEF(WidenVT);
8069 case ISD::BUILD_VECTOR: {
8070 // Build a vector with undefined for the new nodes
8071 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8072 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8073 NewOps.push_back(DAG.getUNDEF(EVT));
8075 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
8076 &NewOps[0], NewOps.size());
8079 case ISD::INSERT_VECTOR_ELT: {
8080 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8081 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8082 Node->getOperand(1), Node->getOperand(2));
8085 case ISD::VECTOR_SHUFFLE: {
8086 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8087 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8088 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
8089 // used as permutation array. We build the vector here instead of widening
8090 // because we don't want to legalize and have it turned to something else.
8091 SDValue PermOp = Node->getOperand(2);
8092 SDValueVector NewOps;
8093 MVT PVT = PermOp.getValueType().getVectorElementType();
8094 for (unsigned i = 0; i < NumElts; ++i) {
8095 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
8096 NewOps.push_back(PermOp.getOperand(i));
8099 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
8100 if (Idx < NumElts) {
8101 NewOps.push_back(PermOp.getOperand(i));
8104 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
8105 PermOp.getOperand(i).getValueType()));
8109 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8110 NewOps.push_back(DAG.getUNDEF(PVT));
8113 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
8114 MVT::getVectorVT(PVT, NewOps.size()),
8115 &NewOps[0], NewOps.size());
8117 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
8121 // If the load widen returns true, we can use a single load for the
8122 // vector. Otherwise, it is returning a token factor for multiple
8125 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8126 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8128 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8132 case ISD::BIT_CONVERT: {
8133 SDValue Tmp1 = Node->getOperand(0);
8134 // Converts between two different types so we need to determine
8135 // the correct widen type for the input operand.
8136 MVT InVT = Tmp1.getValueType();
8137 unsigned WidenSize = WidenVT.getSizeInBits();
8138 if (InVT.isVector()) {
8139 MVT InEltVT = InVT.getVectorElementType();
8140 unsigned InEltSize = InEltVT.getSizeInBits();
8141 assert(WidenSize % InEltSize == 0 &&
8142 "can not widen bit convert that are not multiple of element type");
8143 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8144 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8145 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8146 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8148 // If the result size is a multiple of the input size, widen the input
8149 // and then convert.
8150 unsigned InSize = InVT.getSizeInBits();
8151 assert(WidenSize % InSize == 0 &&
8152 "can not widen bit convert that are not multiple of element type");
8153 unsigned NewNumElts = WidenSize / InSize;
8154 SmallVector<SDValue, 16> Ops(NewNumElts);
8155 SDValue UndefVal = DAG.getUNDEF(InVT);
8157 for (unsigned i = 1; i < NewNumElts; ++i)
8160 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8161 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
8162 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8167 case ISD::SINT_TO_FP:
8168 case ISD::UINT_TO_FP:
8169 case ISD::FP_TO_SINT:
8170 case ISD::FP_TO_UINT:
8171 case ISD::FP_ROUND: {
8172 SDValue Tmp1 = Node->getOperand(0);
8173 // Converts between two different types so we need to determine
8174 // the correct widen type for the input operand.
8175 MVT TVT = Tmp1.getValueType();
8176 assert(TVT.isVector() && "can not widen non vector type");
8177 MVT TEVT = TVT.getVectorElementType();
8178 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8179 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8180 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8181 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8185 case ISD::FP_EXTEND:
8186 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8188 case ISD::SIGN_EXTEND:
8189 case ISD::ZERO_EXTEND:
8190 case ISD::ANY_EXTEND:
8191 case ISD::SIGN_EXTEND_INREG:
8200 // Unary op widening
8202 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8203 assert(Tmp1.getValueType() == WidenVT);
8204 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8207 case ISD::CONVERT_RNDSAT: {
8208 SDValue RndOp = Node->getOperand(3);
8209 SDValue SatOp = Node->getOperand(4);
8210 SDValue SrcOp = Node->getOperand(0);
8212 // Converts between two different types so we need to determine
8213 // the correct widen type for the input operand.
8214 MVT SVT = SrcOp.getValueType();
8215 assert(SVT.isVector() && "can not widen non vector type");
8216 MVT SEVT = SVT.getVectorElementType();
8217 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8219 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8220 assert(SrcOp.getValueType() == WidenVT);
8221 SDValue DTyOp = DAG.getValueType(WidenVT);
8222 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8223 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8225 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
8226 RndOp, SatOp, CvtCode);
8246 case ISD::FCOPYSIGN:
8250 // Binary op widening
8251 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8252 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8253 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8254 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8261 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8262 assert(Tmp1.getValueType() == WidenVT);
8263 SDValue ShOp = Node->getOperand(1);
8264 MVT ShVT = ShOp.getValueType();
8265 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8266 WidenVT.getVectorNumElements());
8267 ShOp = WidenVectorOp(ShOp, NewShVT);
8268 assert(ShOp.getValueType() == NewShVT);
8269 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8273 case ISD::EXTRACT_VECTOR_ELT: {
8274 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8275 assert(Tmp1.getValueType() == WidenVT);
8276 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8279 case ISD::CONCAT_VECTORS: {
8280 // We concurrently support only widen on a multiple of the incoming vector.
8281 // We could widen on a multiple of the incoming operand if necessary.
8282 unsigned NumConcat = NewNumElts / NumElts;
8283 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8284 SDValue UndefVal = DAG.getUNDEF(VT);
8285 SmallVector<SDValue, 8> MOps;
8287 for (unsigned i = 1; i != NumConcat; ++i) {
8288 MOps.push_back(UndefVal);
8290 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8291 &MOps[0], MOps.size()));
8294 case ISD::EXTRACT_SUBVECTOR: {
8295 SDValue Tmp1 = Node->getOperand(0);
8296 SDValue Idx = Node->getOperand(1);
8297 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8298 if (CIdx && CIdx->getZExtValue() == 0) {
8299 // Since we are access the start of the vector, the incoming
8300 // vector type might be the proper.
8301 MVT Tmp1VT = Tmp1.getValueType();
8302 if (Tmp1VT == WidenVT)
8305 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8306 if (Tmp1VTNumElts < NewNumElts)
8307 Result = WidenVectorOp(Tmp1, WidenVT);
8309 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8311 } else if (NewNumElts % NumElts == 0) {
8312 // Widen the extracted subvector.
8313 unsigned NumConcat = NewNumElts / NumElts;
8314 SDValue UndefVal = DAG.getUNDEF(VT);
8315 SmallVector<SDValue, 8> MOps;
8317 for (unsigned i = 1; i != NumConcat; ++i) {
8318 MOps.push_back(UndefVal);
8320 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8321 &MOps[0], MOps.size()));
8323 assert(0 && "can not widen extract subvector");
8324 // This could be implemented using insert and build vector but I would
8325 // like to see when this happens.
8331 // Determine new condition widen type and widen
8332 SDValue Cond1 = Node->getOperand(0);
8333 MVT CondVT = Cond1.getValueType();
8334 assert(CondVT.isVector() && "can not widen non vector type");
8335 MVT CondEVT = CondVT.getVectorElementType();
8336 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8337 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8338 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8340 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8341 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8342 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8343 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8347 case ISD::SELECT_CC: {
8348 // Determine new condition widen type and widen
8349 SDValue Cond1 = Node->getOperand(0);
8350 SDValue Cond2 = Node->getOperand(1);
8351 MVT CondVT = Cond1.getValueType();
8352 assert(CondVT.isVector() && "can not widen non vector type");
8353 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8354 MVT CondEVT = CondVT.getVectorElementType();
8355 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8356 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8357 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8358 assert(Cond1.getValueType() == CondWidenVT &&
8359 Cond2.getValueType() == CondWidenVT && "condition not widen");
8361 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8362 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8363 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8364 "operands not widen");
8365 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8366 Tmp2, Node->getOperand(4));
8370 // Determine widen for the operand
8371 SDValue Tmp1 = Node->getOperand(0);
8372 MVT TmpVT = Tmp1.getValueType();
8373 assert(TmpVT.isVector() && "can not widen non vector type");
8374 MVT TmpEVT = TmpVT.getVectorElementType();
8375 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8376 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8377 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8378 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8379 Node->getOperand(2));
8382 case ISD::ATOMIC_CMP_SWAP:
8383 case ISD::ATOMIC_LOAD_ADD:
8384 case ISD::ATOMIC_LOAD_SUB:
8385 case ISD::ATOMIC_LOAD_AND:
8386 case ISD::ATOMIC_LOAD_OR:
8387 case ISD::ATOMIC_LOAD_XOR:
8388 case ISD::ATOMIC_LOAD_NAND:
8389 case ISD::ATOMIC_LOAD_MIN:
8390 case ISD::ATOMIC_LOAD_MAX:
8391 case ISD::ATOMIC_LOAD_UMIN:
8392 case ISD::ATOMIC_LOAD_UMAX:
8393 case ISD::ATOMIC_SWAP: {
8394 // For now, we assume that using vectors for these operations don't make
8395 // much sense so we just split it. We return an empty result
8397 SplitVectorOp(Op, X, Y);
8402 } // end switch (Node->getOpcode())
8404 assert(Result.getNode() && "Didn't set a result!");
8406 Result = LegalizeOp(Result);
8408 AddWidenedOperand(Op, Result);
8412 // Utility function to find a legal vector type and its associated element
8413 // type from a preferred width and whose vector type must be the same size
8415 // TLI: Target lowering used to determine legal types
8416 // Width: Preferred width of element type
8417 // VVT: Vector value type whose size we must match.
8418 // Returns VecEVT and EVT - the vector type and its associated element type
8419 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8420 MVT& EVT, MVT& VecEVT) {
8421 // We start with the preferred width, make it a power of 2 and see if
8422 // we can find a vector type of that width. If not, we reduce it by
8423 // another power of 2. If we have widen the type, a vector of bytes should
8425 assert(TLI.isTypeLegal(VVT));
8426 unsigned EWidth = Width + 1;
8429 EWidth = (1 << Log2_32(EWidth-1));
8430 EVT = MVT::getIntegerVT(EWidth);
8431 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8432 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8433 } while (!TLI.isTypeLegal(VecEVT) ||
8434 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8437 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8447 // We assume that we have good rules to handle loading power of two loads so
8448 // we break down the operations to power of 2 loads. The strategy is to
8449 // load the largest power of 2 that we can easily transform to a legal vector
8450 // and then insert into that vector, and the cast the result into the legal
8451 // vector that we want. This avoids unnecessary stack converts.
8452 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8453 // the load is nonvolatile, we an use a wider load for the value.
8454 // Find a vector length we can load a large chunk
8457 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8458 EVTWidth = EVT.getSizeInBits();
8460 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8461 isVolatile, Alignment);
8462 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8463 LdChain.push_back(LdOp.getValue(1));
8465 // Check if we can load the element with one instruction
8466 if (LdWidth == EVTWidth) {
8467 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8470 // The vector element order is endianness dependent.
8472 LdWidth -= EVTWidth;
8473 unsigned Offset = 0;
8475 while (LdWidth > 0) {
8476 unsigned Increment = EVTWidth / 8;
8477 Offset += Increment;
8478 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8479 DAG.getIntPtrConstant(Increment));
8481 if (LdWidth < EVTWidth) {
8482 // Our current type we are using is too large, use a smaller size by
8483 // using a smaller power of 2
8484 unsigned oEVTWidth = EVTWidth;
8485 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8486 EVTWidth = EVT.getSizeInBits();
8487 // Readjust position and vector position based on new load type
8488 Idx = Idx * (oEVTWidth/EVTWidth);
8489 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8492 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8493 SVOffset+Offset, isVolatile,
8494 MinAlign(Alignment, Offset));
8495 LdChain.push_back(LdOp.getValue(1));
8496 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8497 DAG.getIntPtrConstant(Idx++));
8499 LdWidth -= EVTWidth;
8502 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8505 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8509 // TODO: Add support for ConcatVec and the ability to load many vector
8510 // types (e.g., v4i8). This will not work when a vector register
8511 // to memory mapping is strange (e.g., vector elements are not
8512 // stored in some sequential order).
8514 // It must be true that the widen vector type is bigger than where
8515 // we need to load from.
8516 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8517 MVT LdVT = LD->getMemoryVT();
8518 DebugLoc dl = LD->getDebugLoc();
8519 assert(LdVT.isVector() && NVT.isVector());
8520 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8523 SDValue Chain = LD->getChain();
8524 SDValue BasePtr = LD->getBasePtr();
8525 int SVOffset = LD->getSrcValueOffset();
8526 unsigned Alignment = LD->getAlignment();
8527 bool isVolatile = LD->isVolatile();
8528 const Value *SV = LD->getSrcValue();
8529 unsigned int LdWidth = LdVT.getSizeInBits();
8531 // Load value as a large register
8532 SDValueVector LdChain;
8533 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8534 Alignment, isVolatile, LdWidth, NVT, dl);
8536 if (LdChain.size() == 1) {
8541 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8542 &LdChain[0], LdChain.size());
8548 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8558 // Breaks the stores into a series of power of 2 width stores. For any
8559 // width, we convert the vector to the vector of element size that we
8560 // want to store. This avoids requiring a stack convert.
8562 // Find a width of the element type we can store with
8563 MVT VVT = ValOp.getValueType();
8566 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8567 EVTWidth = EVT.getSizeInBits();
8569 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8570 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8571 DAG.getIntPtrConstant(0));
8572 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8573 isVolatile, Alignment);
8574 StChain.push_back(StOp);
8576 // Check if we are done
8577 if (StWidth == EVTWidth) {
8582 StWidth -= EVTWidth;
8583 unsigned Offset = 0;
8585 while (StWidth > 0) {
8586 unsigned Increment = EVTWidth / 8;
8587 Offset += Increment;
8588 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8589 DAG.getIntPtrConstant(Increment));
8591 if (StWidth < EVTWidth) {
8592 // Our current type we are using is too large, use a smaller size by
8593 // using a smaller power of 2
8594 unsigned oEVTWidth = EVTWidth;
8595 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8596 EVTWidth = EVT.getSizeInBits();
8597 // Readjust position and vector position based on new load type
8598 Idx = Idx * (oEVTWidth/EVTWidth);
8599 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8602 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8603 DAG.getIntPtrConstant(Idx++));
8604 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8605 SVOffset + Offset, isVolatile,
8606 MinAlign(Alignment, Offset)));
8607 StWidth -= EVTWidth;
8612 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8615 // TODO: It might be cleaner if we can use SplitVector and have more legal
8616 // vector types that can be stored into memory (e.g., v4xi8 can
8617 // be stored as a word). This will not work when a vector register
8618 // to memory mapping is strange (e.g., vector elements are not
8619 // stored in some sequential order).
8621 MVT StVT = ST->getMemoryVT();
8622 SDValue ValOp = ST->getValue();
8623 DebugLoc dl = ST->getDebugLoc();
8625 // Check if we have widen this node with another value
8626 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8627 if (I != WidenNodes.end())
8630 MVT VVT = ValOp.getValueType();
8632 // It must be true that we the widen vector type is bigger than where
8633 // we need to store.
8634 assert(StVT.isVector() && VVT.isVector());
8635 assert(StVT.bitsLT(VVT));
8636 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8639 SDValueVector StChain;
8640 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8641 ST->getSrcValueOffset(), ST->getAlignment(),
8642 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8643 if (StChain.size() == 1)
8646 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8647 &StChain[0], StChain.size());
8651 // SelectionDAG::Legalize - This is the entry point for the file.
8653 void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
8654 /// run - This is the main entry point to this class.
8656 SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();