1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 bool TypesNeedLegalizing;
61 // Libcall insertion helpers.
63 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
64 /// legalized. We use this to ensure that calls are properly serialized
65 /// against each other, including inserted libcalls.
66 SDValue LastCALLSEQ_END;
68 /// IsLegalizingCall - This member is used *only* for purposes of providing
69 /// helpful assertions that a libcall isn't created while another call is
70 /// being legalized (which could lead to non-serialized call sequences).
71 bool IsLegalizingCall;
73 /// IsLegalizingCallArguments - This member is used only for the purpose
74 /// of providing assert to check for LegalizeTypes because legalizing an
75 /// operation might introduce call nodes that might need type legalization.
76 bool IsLegalizingCallArgs;
79 Legal, // The target natively supports this operation.
80 Promote, // This operation should be executed in a larger type.
81 Expand // Try to expand this to other ops, otherwise use a libcall.
84 /// ValueTypeActions - This is a bitvector that contains two bits for each
85 /// value type, where the two bits correspond to the LegalizeAction enum.
86 /// This can be queried with "getTypeAction(VT)".
87 TargetLowering::ValueTypeActionImpl ValueTypeActions;
89 /// LegalizedNodes - For nodes that are of legal width, and that have more
90 /// than one use, this map indicates what regularized operand to use. This
91 /// allows us to avoid legalizing the same thing more than once.
92 DenseMap<SDValue, SDValue> LegalizedNodes;
94 /// PromotedNodes - For nodes that are below legal width, and that have more
95 /// than one use, this map indicates what promoted value to use. This allows
96 /// us to avoid promoting the same thing more than once.
97 DenseMap<SDValue, SDValue> PromotedNodes;
99 /// ExpandedNodes - For nodes that need to be expanded this map indicates
100 /// which operands are the expanded version of the input. This allows
101 /// us to avoid expanding the same node more than once.
102 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
104 /// SplitNodes - For vector nodes that need to be split, this map indicates
105 /// which operands are the split version of the input. This allows us
106 /// to avoid splitting the same node more than once.
107 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
109 /// ScalarizedNodes - For nodes that need to be converted from vector types to
110 /// scalar types, this contains the mapping of ones we have already
111 /// processed to the result.
112 std::map<SDValue, SDValue> ScalarizedNodes;
114 /// WidenNodes - For nodes that need to be widened from one vector type to
115 /// another, this contains the mapping of those that we have already widen.
116 /// This allows us to avoid widening more than once.
117 std::map<SDValue, SDValue> WidenNodes;
119 void AddLegalizedOperand(SDValue From, SDValue To) {
120 LegalizedNodes.insert(std::make_pair(From, To));
121 // If someone requests legalization of the new node, return itself.
123 LegalizedNodes.insert(std::make_pair(To, To));
125 void AddPromotedOperand(SDValue From, SDValue To) {
126 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
127 assert(isNew && "Got into the map somehow?");
129 // If someone requests legalization of the new node, return itself.
130 LegalizedNodes.insert(std::make_pair(To, To));
132 void AddWidenedOperand(SDValue From, SDValue To) {
133 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
134 assert(isNew && "Got into the map somehow?");
136 // If someone requests legalization of the new node, return itself.
137 LegalizedNodes.insert(std::make_pair(To, To));
141 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing,
144 /// getTypeAction - Return how we should legalize values of this type, either
145 /// it is already legal or we need to expand it into multiple registers of
146 /// smaller integer type, or we need to promote it to a larger type.
147 LegalizeAction getTypeAction(MVT VT) const {
148 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
151 /// isTypeLegal - Return true if this type is legal on this target.
153 bool isTypeLegal(MVT VT) const {
154 return getTypeAction(VT) == Legal;
160 /// HandleOp - Legalize, Promote, or Expand the specified operand as
161 /// appropriate for its type.
162 void HandleOp(SDValue Op);
164 /// LegalizeOp - We know that the specified value has a legal type.
165 /// Recursively ensure that the operands have legal types, then return the
167 SDValue LegalizeOp(SDValue O);
169 /// UnrollVectorOp - We know that the given vector has a legal type, however
170 /// the operation it performs is not legal and is an operation that we have
171 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
172 /// operating on each element individually.
173 SDValue UnrollVectorOp(SDValue O);
175 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
176 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
177 /// is necessary to spill the vector being inserted into to memory, perform
178 /// the insert there, and then read the result back.
179 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
180 SDValue Idx, DebugLoc dl);
182 /// PromoteOp - Given an operation that produces a value in an invalid type,
183 /// promote it to compute the value into a larger type. The produced value
184 /// will have the correct bits for the low portion of the register, but no
185 /// guarantee is made about the top bits: it may be zero, sign-extended, or
187 SDValue PromoteOp(SDValue O);
189 /// ExpandOp - Expand the specified SDValue into its two component pieces
190 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
191 /// the LegalizedNodes map is filled in for any results that are not expanded,
192 /// the ExpandedNodes map is filled in for any results that are expanded, and
193 /// the Lo/Hi values are returned. This applies to integer types and Vector
195 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
197 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
198 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
199 /// for the existing elements but no guarantee is made about the new elements
200 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
201 /// when we have an instruction operating on an illegal vector type and we
202 /// want to widen it to do the computation on a legal wider vector type.
203 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
205 /// SplitVectorOp - Given an operand of vector type, break it down into
206 /// two smaller values.
207 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
209 /// ScalarizeVectorOp - Given an operand of single-element vector type
210 /// (e.g. v1f32), convert it into the equivalent operation that returns a
211 /// scalar (e.g. f32) value.
212 SDValue ScalarizeVectorOp(SDValue O);
214 /// Useful 16 element vector type that is used to pass operands for widening.
215 typedef SmallVector<SDValue, 16> SDValueVector;
217 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
218 /// the LdChain contains a single load and false if it contains a token
219 /// factor for multiple loads. It takes
220 /// Result: location to return the result
221 /// LdChain: location to return the load chain
222 /// Op: load operation to widen
223 /// NVT: widen vector result type we want for the load
224 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
225 SDValue Op, MVT NVT);
227 /// Helper genWidenVectorLoads - Helper function to generate a set of
228 /// loads to load a vector with a resulting wider type. It takes
229 /// LdChain: list of chains for the load we have generated
230 /// Chain: incoming chain for the ld vector
231 /// BasePtr: base pointer to load from
232 /// SV: memory disambiguation source value
233 /// SVOffset: memory disambiugation offset
234 /// Alignment: alignment of the memory
235 /// isVolatile: volatile load
236 /// LdWidth: width of memory that we want to load
237 /// ResType: the wider result result type for the resulting loaded vector
238 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
239 SDValue BasePtr, const Value *SV,
240 int SVOffset, unsigned Alignment,
241 bool isVolatile, unsigned LdWidth,
242 MVT ResType, DebugLoc dl);
244 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
245 /// location. It takes
246 /// ST: store node that we want to replace
247 /// Chain: incoming store chain
248 /// BasePtr: base address of where we want to store into
249 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
252 /// Helper genWidenVectorStores - Helper function to generate a set of
253 /// stores to store a widen vector into non widen memory
255 // StChain: list of chains for the stores we have generated
256 // Chain: incoming chain for the ld vector
257 // BasePtr: base pointer to load from
258 // SV: memory disambiguation source value
259 // SVOffset: memory disambiugation offset
260 // Alignment: alignment of the memory
261 // isVolatile: volatile lod
262 // ValOp: value to store
263 // StWidth: width of memory that we want to store
264 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
265 SDValue BasePtr, const Value *SV,
266 int SVOffset, unsigned Alignment,
267 bool isVolatile, SDValue ValOp,
268 unsigned StWidth, DebugLoc dl);
270 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
271 /// specified mask and type. Targets can specify exactly which masks they
272 /// support and the code generator is tasked with not creating illegal masks.
274 /// Note that this will also return true for shuffles that are promoted to a
277 /// If this is a legal shuffle, this method returns the (possibly promoted)
278 /// build_vector Mask. If it's not a legal shuffle, it returns null.
279 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
281 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
282 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
284 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
286 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
288 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
290 LegalizeSetCCOperands(LHS, RHS, CC, dl);
291 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
294 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
296 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl);
298 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
299 SDValue ExpandBUILD_VECTOR(SDNode *Node);
300 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
301 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy,
302 SDValue Op, DebugLoc dl);
303 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
305 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
307 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
310 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
311 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
312 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
313 SDValue &Lo, SDValue &Hi, DebugLoc dl);
314 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
315 SDValue &Lo, SDValue &Hi, DebugLoc dl);
317 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
318 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
322 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
323 /// specified mask and type. Targets can specify exactly which masks they
324 /// support and the code generator is tasked with not creating illegal masks.
326 /// Note that this will also return true for shuffles that are promoted to a
328 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
329 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
331 case TargetLowering::Legal:
332 case TargetLowering::Custom:
334 case TargetLowering::Promote: {
335 // If this is promoted to a different type, convert the shuffle mask and
336 // ask if it is legal in the promoted type!
337 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
338 MVT EltVT = NVT.getVectorElementType();
340 // If we changed # elements, change the shuffle mask.
341 unsigned NumEltsGrowth =
342 NVT.getVectorNumElements() / VT.getVectorNumElements();
343 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
344 if (NumEltsGrowth > 1) {
345 // Renumber the elements.
346 SmallVector<SDValue, 8> Ops;
347 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
348 SDValue InOp = Mask.getOperand(i);
349 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
350 if (InOp.getOpcode() == ISD::UNDEF)
351 Ops.push_back(DAG.getUNDEF(EltVT));
353 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
354 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
358 Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
359 NVT, &Ops[0], Ops.size());
365 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
368 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
369 bool types, bool fast)
370 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
371 Fast(fast), ValueTypeActions(TLI.getValueTypeActions()) {
372 assert(MVT::LAST_VALUETYPE <= 32 &&
373 "Too many value types for ValueTypeActions to hold!");
376 void SelectionDAGLegalize::LegalizeDAG() {
377 LastCALLSEQ_END = DAG.getEntryNode();
378 IsLegalizingCall = false;
379 IsLegalizingCallArgs = false;
381 // The legalize process is inherently a bottom-up recursive process (users
382 // legalize their uses before themselves). Given infinite stack space, we
383 // could just start legalizing on the root and traverse the whole graph. In
384 // practice however, this causes us to run out of stack space on large basic
385 // blocks. To avoid this problem, compute an ordering of the nodes where each
386 // node is only legalized after all of its operands are legalized.
387 DAG.AssignTopologicalOrder();
388 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
389 E = prior(DAG.allnodes_end()); I != next(E); ++I)
390 HandleOp(SDValue(I, 0));
392 // Finally, it's possible the root changed. Get the new root.
393 SDValue OldRoot = DAG.getRoot();
394 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
395 DAG.setRoot(LegalizedNodes[OldRoot]);
397 ExpandedNodes.clear();
398 LegalizedNodes.clear();
399 PromotedNodes.clear();
401 ScalarizedNodes.clear();
404 // Remove dead nodes now.
405 DAG.RemoveDeadNodes();
409 /// FindCallEndFromCallStart - Given a chained node that is part of a call
410 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
411 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
412 if (Node->getOpcode() == ISD::CALLSEQ_END)
414 if (Node->use_empty())
415 return 0; // No CallSeqEnd
417 // The chain is usually at the end.
418 SDValue TheChain(Node, Node->getNumValues()-1);
419 if (TheChain.getValueType() != MVT::Other) {
420 // Sometimes it's at the beginning.
421 TheChain = SDValue(Node, 0);
422 if (TheChain.getValueType() != MVT::Other) {
423 // Otherwise, hunt for it.
424 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
425 if (Node->getValueType(i) == MVT::Other) {
426 TheChain = SDValue(Node, i);
430 // Otherwise, we walked into a node without a chain.
431 if (TheChain.getValueType() != MVT::Other)
436 for (SDNode::use_iterator UI = Node->use_begin(),
437 E = Node->use_end(); UI != E; ++UI) {
439 // Make sure to only follow users of our token chain.
441 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
442 if (User->getOperand(i) == TheChain)
443 if (SDNode *Result = FindCallEndFromCallStart(User))
449 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
450 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
451 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
452 assert(Node && "Didn't find callseq_start for a call??");
453 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
455 assert(Node->getOperand(0).getValueType() == MVT::Other &&
456 "Node doesn't have a token chain argument!");
457 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
460 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
461 /// see if any uses can reach Dest. If no dest operands can get to dest,
462 /// legalize them, legalize ourself, and return false, otherwise, return true.
464 /// Keep track of the nodes we fine that actually do lead to Dest in
465 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
467 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
468 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
469 if (N == Dest) return true; // N certainly leads to Dest :)
471 // If we've already processed this node and it does lead to Dest, there is no
472 // need to reprocess it.
473 if (NodesLeadingTo.count(N)) return true;
475 // If the first result of this node has been already legalized, then it cannot
477 switch (getTypeAction(N->getValueType(0))) {
479 if (LegalizedNodes.count(SDValue(N, 0))) return false;
482 if (PromotedNodes.count(SDValue(N, 0))) return false;
485 if (ExpandedNodes.count(SDValue(N, 0))) return false;
489 // Okay, this node has not already been legalized. Check and legalize all
490 // operands. If none lead to Dest, then we can legalize this node.
491 bool OperandsLeadToDest = false;
492 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
493 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
494 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
496 if (OperandsLeadToDest) {
497 NodesLeadingTo.insert(N);
501 // Okay, this node looks safe, legalize it and return false.
502 HandleOp(SDValue(N, 0));
506 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
507 /// appropriate for its type.
508 void SelectionDAGLegalize::HandleOp(SDValue Op) {
509 MVT VT = Op.getValueType();
510 // If the type legalizer was run then we should never see any illegal result
511 // types here except for target constants (the type legalizer does not touch
512 // those) or for build vector used as a mask for a vector shuffle.
513 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
514 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
515 IsLegalizingCallArgs || Op.getOpcode() == ISD::TargetConstant ||
516 Op.getOpcode() == ISD::BUILD_VECTOR) &&
517 "Illegal type introduced after type legalization?");
518 switch (getTypeAction(VT)) {
519 default: assert(0 && "Bad type action!");
520 case Legal: (void)LegalizeOp(Op); break;
522 if (!VT.isVector()) {
527 // See if we can widen otherwise use Expand to either scalarize or split
528 MVT WidenVT = TLI.getWidenVectorType(VT);
529 if (WidenVT != MVT::Other) {
530 (void) WidenVectorOp(Op, WidenVT);
533 // else fall thru to expand since we can't widen the vector
536 if (!VT.isVector()) {
537 // If this is an illegal scalar, expand it into its two component
540 if (Op.getOpcode() == ISD::TargetConstant)
541 break; // Allow illegal target nodes.
543 } else if (VT.getVectorNumElements() == 1) {
544 // If this is an illegal single element vector, convert it to a
546 (void)ScalarizeVectorOp(Op);
548 // This is an illegal multiple element vector.
549 // Split it in half and legalize both parts.
551 SplitVectorOp(Op, X, Y);
557 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
558 /// a load from the constant pool.
559 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
560 SelectionDAG &DAG, const TargetLowering &TLI) {
562 DebugLoc dl = CFP->getDebugLoc();
564 // If a FP immediate is precise when represented as a float and if the
565 // target can do an extending load from float to double, we put it into
566 // the constant pool as a float, even if it's is statically typed as a
567 // double. This shrinks FP constants and canonicalizes them for targets where
568 // an FP extending load is the same cost as a normal load (such as on the x87
569 // fp stack or PPC FP unit).
570 MVT VT = CFP->getValueType(0);
571 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
573 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
574 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
575 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
580 while (SVT != MVT::f32) {
581 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
582 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
583 // Only do this if the target has a native EXTLOAD instruction from
585 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
586 TLI.ShouldShrinkFPConstant(OrigVT)) {
587 const Type *SType = SVT.getTypeForMVT();
588 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
594 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
595 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
597 return DAG.getExtLoad(ISD::EXTLOAD, dl,
598 OrigVT, DAG.getEntryNode(),
599 CPIdx, PseudoSourceValue::getConstantPool(),
600 0, VT, false, Alignment);
601 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
602 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
606 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
609 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
611 const TargetLowering &TLI) {
612 DebugLoc dl = Node->getDebugLoc();
613 MVT VT = Node->getValueType(0);
614 MVT SrcVT = Node->getOperand(1).getValueType();
615 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
616 "fcopysign expansion only supported for f32 and f64");
617 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
619 // First get the sign bit of second operand.
620 SDValue Mask1 = (SrcVT == MVT::f64)
621 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
622 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
623 Mask1 = DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT, Mask1);
624 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, dl, SrcNVT,
625 Node->getOperand(1));
626 SignBit = DAG.getNode(ISD::AND, dl, SrcNVT, SignBit, Mask1);
627 // Shift right or sign-extend it if the two operands have different types.
628 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
630 SignBit = DAG.getNode(ISD::SRL, dl, SrcNVT, SignBit,
631 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
632 SignBit = DAG.getNode(ISD::TRUNCATE, dl, NVT, SignBit);
633 } else if (SizeDiff < 0) {
634 SignBit = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, SignBit);
635 SignBit = DAG.getNode(ISD::SHL, dl, NVT, SignBit,
636 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
639 // Clear the sign bit of first operand.
640 SDValue Mask2 = (VT == MVT::f64)
641 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
642 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
643 Mask2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask2);
644 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
645 Result = DAG.getNode(ISD::AND, dl, NVT, Result, Mask2);
647 // Or the value with the sign bit.
648 Result = DAG.getNode(ISD::OR, dl, NVT, Result, SignBit);
652 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
654 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
655 const TargetLowering &TLI) {
656 SDValue Chain = ST->getChain();
657 SDValue Ptr = ST->getBasePtr();
658 SDValue Val = ST->getValue();
659 MVT VT = Val.getValueType();
660 int Alignment = ST->getAlignment();
661 int SVOffset = ST->getSrcValueOffset();
662 DebugLoc dl = ST->getDebugLoc();
663 if (ST->getMemoryVT().isFloatingPoint() ||
664 ST->getMemoryVT().isVector()) {
665 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
666 if (TLI.isTypeLegal(intVT)) {
667 // Expand to a bitconvert of the value to the integer type of the
668 // same size, then a (misaligned) int store.
669 // FIXME: Does not handle truncating floating point stores!
670 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
671 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
672 SVOffset, ST->isVolatile(), Alignment);
674 // Do a (aligned) store to a stack slot, then copy from the stack slot
675 // to the final destination using (unaligned) integer loads and stores.
676 MVT StoredVT = ST->getMemoryVT();
678 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
679 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
680 unsigned RegBytes = RegVT.getSizeInBits() / 8;
681 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
683 // Make sure the stack slot is also aligned for the register type.
684 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
686 // Perform the original store, only redirected to the stack slot.
687 SDValue Store = DAG.getTruncStore(Chain, dl,
688 Val, StackPtr, NULL, 0,StoredVT);
689 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
690 SmallVector<SDValue, 8> Stores;
693 // Do all but one copies using the full register width.
694 for (unsigned i = 1; i < NumRegs; i++) {
695 // Load one integer register's worth from the stack slot.
696 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
697 // Store it to the final location. Remember the store.
698 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
699 ST->getSrcValue(), SVOffset + Offset,
701 MinAlign(ST->getAlignment(), Offset)));
702 // Increment the pointers.
704 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
706 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
709 // The last store may be partial. Do a truncating store. On big-endian
710 // machines this requires an extending load from the stack slot to ensure
711 // that the bits are in the right place.
712 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
714 // Load from the stack slot.
715 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
718 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
719 ST->getSrcValue(), SVOffset + Offset,
720 MemVT, ST->isVolatile(),
721 MinAlign(ST->getAlignment(), Offset)));
722 // The order of the stores doesn't matter - say it with a TokenFactor.
723 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
727 assert(ST->getMemoryVT().isInteger() &&
728 !ST->getMemoryVT().isVector() &&
729 "Unaligned store of unknown type.");
730 // Get the half-size VT
732 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
733 int NumBits = NewStoredVT.getSizeInBits();
734 int IncrementSize = NumBits / 8;
736 // Divide the stored value in two parts.
737 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
739 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
741 // Store the two parts
742 SDValue Store1, Store2;
743 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
744 ST->getSrcValue(), SVOffset, NewStoredVT,
745 ST->isVolatile(), Alignment);
746 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
747 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
748 Alignment = MinAlign(Alignment, IncrementSize);
749 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
750 ST->getSrcValue(), SVOffset + IncrementSize,
751 NewStoredVT, ST->isVolatile(), Alignment);
753 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
756 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
758 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
759 const TargetLowering &TLI) {
760 int SVOffset = LD->getSrcValueOffset();
761 SDValue Chain = LD->getChain();
762 SDValue Ptr = LD->getBasePtr();
763 MVT VT = LD->getValueType(0);
764 MVT LoadedVT = LD->getMemoryVT();
765 DebugLoc dl = LD->getDebugLoc();
766 if (VT.isFloatingPoint() || VT.isVector()) {
767 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
768 if (TLI.isTypeLegal(intVT)) {
769 // Expand to a (misaligned) integer load of the same size,
770 // then bitconvert to floating point or vector.
771 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
772 SVOffset, LD->isVolatile(),
774 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
775 if (VT.isFloatingPoint() && LoadedVT != VT)
776 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
778 SDValue Ops[] = { Result, Chain };
779 return DAG.getMergeValues(Ops, 2, dl);
781 // Copy the value to a (aligned) stack slot using (unaligned) integer
782 // loads and stores, then do a (aligned) load from the stack slot.
783 MVT RegVT = TLI.getRegisterType(intVT);
784 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
785 unsigned RegBytes = RegVT.getSizeInBits() / 8;
786 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
788 // Make sure the stack slot is also aligned for the register type.
789 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
791 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
792 SmallVector<SDValue, 8> Stores;
793 SDValue StackPtr = StackBase;
796 // Do all but one copies using the full register width.
797 for (unsigned i = 1; i < NumRegs; i++) {
798 // Load one integer register's worth from the original location.
799 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
800 SVOffset + Offset, LD->isVolatile(),
801 MinAlign(LD->getAlignment(), Offset));
802 // Follow the load with a store to the stack slot. Remember the store.
803 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
805 // Increment the pointers.
807 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
808 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
812 // The last copy may be partial. Do an extending load.
813 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
814 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
815 LD->getSrcValue(), SVOffset + Offset,
816 MemVT, LD->isVolatile(),
817 MinAlign(LD->getAlignment(), Offset));
818 // Follow the load with a store to the stack slot. Remember the store.
819 // On big-endian machines this requires a truncating store to ensure
820 // that the bits end up in the right place.
821 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
824 // The order of the stores doesn't matter - say it with a TokenFactor.
825 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
828 // Finally, perform the original load only redirected to the stack slot.
829 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
832 // Callers expect a MERGE_VALUES node.
833 SDValue Ops[] = { Load, TF };
834 return DAG.getMergeValues(Ops, 2, dl);
837 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
838 "Unaligned load of unsupported type.");
840 // Compute the new VT that is half the size of the old one. This is an
842 unsigned NumBits = LoadedVT.getSizeInBits();
844 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
847 unsigned Alignment = LD->getAlignment();
848 unsigned IncrementSize = NumBits / 8;
849 ISD::LoadExtType HiExtType = LD->getExtensionType();
851 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
852 if (HiExtType == ISD::NON_EXTLOAD)
853 HiExtType = ISD::ZEXTLOAD;
855 // Load the value in two parts
857 if (TLI.isLittleEndian()) {
858 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
859 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
860 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
861 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
862 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
863 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
864 MinAlign(Alignment, IncrementSize));
866 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
867 SVOffset, NewLoadedVT,LD->isVolatile(), Alignment);
868 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
869 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
870 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
871 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
872 MinAlign(Alignment, IncrementSize));
875 // aggregate the two parts
876 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
877 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
878 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
880 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
883 SDValue Ops[] = { Result, TF };
884 return DAG.getMergeValues(Ops, 2, dl);
887 /// UnrollVectorOp - We know that the given vector has a legal type, however
888 /// the operation it performs is not legal and is an operation that we have
889 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
890 /// operating on each element individually.
891 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
892 MVT VT = Op.getValueType();
893 assert(isTypeLegal(VT) &&
894 "Caller should expand or promote operands that are not legal!");
895 assert(Op.getNode()->getNumValues() == 1 &&
896 "Can't unroll a vector with multiple results!");
897 unsigned NE = VT.getVectorNumElements();
898 MVT EltVT = VT.getVectorElementType();
899 DebugLoc dl = Op.getDebugLoc();
901 SmallVector<SDValue, 8> Scalars;
902 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
903 for (unsigned i = 0; i != NE; ++i) {
904 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
905 SDValue Operand = Op.getOperand(j);
906 MVT OperandVT = Operand.getValueType();
907 if (OperandVT.isVector()) {
908 // A vector operand; extract a single element.
909 MVT OperandEltVT = OperandVT.getVectorElementType();
910 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
913 DAG.getConstant(i, MVT::i32));
915 // A scalar operand; just use it as is.
916 Operands[j] = Operand;
920 switch (Op.getOpcode()) {
922 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
923 &Operands[0], Operands.size()));
930 Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
931 DAG.getShiftAmountOperand(Operands[1])));
936 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
939 /// GetFPLibCall - Return the right libcall for the given floating point type.
940 static RTLIB::Libcall GetFPLibCall(MVT VT,
941 RTLIB::Libcall Call_F32,
942 RTLIB::Libcall Call_F64,
943 RTLIB::Libcall Call_F80,
944 RTLIB::Libcall Call_PPCF128) {
946 VT == MVT::f32 ? Call_F32 :
947 VT == MVT::f64 ? Call_F64 :
948 VT == MVT::f80 ? Call_F80 :
949 VT == MVT::ppcf128 ? Call_PPCF128 :
950 RTLIB::UNKNOWN_LIBCALL;
953 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
954 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
955 /// is necessary to spill the vector being inserted into to memory, perform
956 /// the insert there, and then read the result back.
957 SDValue SelectionDAGLegalize::
958 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
964 // If the target doesn't support this, we have to spill the input vector
965 // to a temporary stack slot, update the element, then reload it. This is
966 // badness. We could also load the value into a vector register (either
967 // with a "move to register" or "extload into register" instruction, then
968 // permute it into place, if the idx is a constant and if the idx is
969 // supported by the target.
970 MVT VT = Tmp1.getValueType();
971 MVT EltVT = VT.getVectorElementType();
972 MVT IdxVT = Tmp3.getValueType();
973 MVT PtrVT = TLI.getPointerTy();
974 SDValue StackPtr = DAG.CreateStackTemporary(VT);
976 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
979 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
980 PseudoSourceValue::getFixedStack(SPFI), 0);
982 // Truncate or zero extend offset to target pointer type.
983 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
984 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
985 // Add the offset to the index.
986 unsigned EltSize = EltVT.getSizeInBits()/8;
987 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
988 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
989 // Store the scalar value.
990 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
991 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
992 // Load the updated vector.
993 return DAG.getLoad(VT, dl, Ch, StackPtr,
994 PseudoSourceValue::getFixedStack(SPFI), 0);
998 /// LegalizeOp - We know that the specified value has a legal type, and
999 /// that its operands are legal. Now ensure that the operation itself
1000 /// is legal, recursively ensuring that the operands' operations remain
1002 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
1003 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1006 assert(isTypeLegal(Op.getValueType()) &&
1007 "Caller should expand or promote operands that are not legal!");
1008 SDNode *Node = Op.getNode();
1009 DebugLoc dl = Node->getDebugLoc();
1011 // If this operation defines any values that cannot be represented in a
1012 // register on this target, make sure to expand or promote them.
1013 if (Node->getNumValues() > 1) {
1014 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1015 if (getTypeAction(Node->getValueType(i)) != Legal) {
1016 HandleOp(Op.getValue(i));
1017 assert(LegalizedNodes.count(Op) &&
1018 "Handling didn't add legal operands!");
1019 return LegalizedNodes[Op];
1023 // Note that LegalizeOp may be reentered even from single-use nodes, which
1024 // means that we always must cache transformed nodes.
1025 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1026 if (I != LegalizedNodes.end()) return I->second;
1028 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1029 SDValue Result = Op;
1030 bool isCustom = false;
1032 switch (Node->getOpcode()) {
1033 case ISD::FrameIndex:
1034 case ISD::EntryToken:
1036 case ISD::BasicBlock:
1037 case ISD::TargetFrameIndex:
1038 case ISD::TargetJumpTable:
1039 case ISD::TargetConstant:
1040 case ISD::TargetConstantFP:
1041 case ISD::TargetConstantPool:
1042 case ISD::TargetGlobalAddress:
1043 case ISD::TargetGlobalTLSAddress:
1044 case ISD::TargetExternalSymbol:
1045 case ISD::VALUETYPE:
1047 case ISD::MEMOPERAND:
1049 case ISD::ARG_FLAGS:
1050 // Primitives must all be legal.
1051 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1052 "This must be legal!");
1055 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1056 // If this is a target node, legalize it by legalizing the operands then
1057 // passing it through.
1058 SmallVector<SDValue, 8> Ops;
1059 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1060 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1062 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1064 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1065 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1066 return Result.getValue(Op.getResNo());
1068 // Otherwise this is an unhandled builtin node. splat.
1070 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1072 assert(0 && "Do not know how to legalize this operator!");
1074 case ISD::GLOBAL_OFFSET_TABLE:
1075 case ISD::GlobalAddress:
1076 case ISD::GlobalTLSAddress:
1077 case ISD::ExternalSymbol:
1078 case ISD::ConstantPool:
1079 case ISD::JumpTable: // Nothing to do.
1080 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1081 default: assert(0 && "This action is not supported yet!");
1082 case TargetLowering::Custom:
1083 Tmp1 = TLI.LowerOperation(Op, DAG);
1084 if (Tmp1.getNode()) Result = Tmp1;
1085 // FALLTHROUGH if the target doesn't want to lower this op after all.
1086 case TargetLowering::Legal:
1090 case ISD::FRAMEADDR:
1091 case ISD::RETURNADDR:
1092 // The only option for these nodes is to custom lower them. If the target
1093 // does not custom lower them, then return zero.
1094 Tmp1 = TLI.LowerOperation(Op, DAG);
1098 Result = DAG.getConstant(0, TLI.getPointerTy());
1100 case ISD::FRAME_TO_ARGS_OFFSET: {
1101 MVT VT = Node->getValueType(0);
1102 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1103 default: assert(0 && "This action is not supported yet!");
1104 case TargetLowering::Custom:
1105 Result = TLI.LowerOperation(Op, DAG);
1106 if (Result.getNode()) break;
1108 case TargetLowering::Legal:
1109 Result = DAG.getConstant(0, VT);
1114 case ISD::EXCEPTIONADDR: {
1115 Tmp1 = LegalizeOp(Node->getOperand(0));
1116 MVT VT = Node->getValueType(0);
1117 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1118 default: assert(0 && "This action is not supported yet!");
1119 case TargetLowering::Expand: {
1120 unsigned Reg = TLI.getExceptionAddressRegister();
1121 Result = DAG.getCopyFromReg(Tmp1, dl, Reg, VT);
1124 case TargetLowering::Custom:
1125 Result = TLI.LowerOperation(Op, DAG);
1126 if (Result.getNode()) break;
1128 case TargetLowering::Legal: {
1129 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1130 Result = DAG.getMergeValues(Ops, 2, dl);
1135 if (Result.getNode()->getNumValues() == 1) break;
1137 assert(Result.getNode()->getNumValues() == 2 &&
1138 "Cannot return more than two values!");
1140 // Since we produced two values, make sure to remember that we
1141 // legalized both of them.
1142 Tmp1 = LegalizeOp(Result);
1143 Tmp2 = LegalizeOp(Result.getValue(1));
1144 AddLegalizedOperand(Op.getValue(0), Tmp1);
1145 AddLegalizedOperand(Op.getValue(1), Tmp2);
1146 return Op.getResNo() ? Tmp2 : Tmp1;
1147 case ISD::EHSELECTION: {
1148 Tmp1 = LegalizeOp(Node->getOperand(0));
1149 Tmp2 = LegalizeOp(Node->getOperand(1));
1150 MVT VT = Node->getValueType(0);
1151 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1152 default: assert(0 && "This action is not supported yet!");
1153 case TargetLowering::Expand: {
1154 unsigned Reg = TLI.getExceptionSelectorRegister();
1155 Result = DAG.getCopyFromReg(Tmp2, dl, Reg, VT);
1158 case TargetLowering::Custom:
1159 Result = TLI.LowerOperation(Op, DAG);
1160 if (Result.getNode()) break;
1162 case TargetLowering::Legal: {
1163 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1164 Result = DAG.getMergeValues(Ops, 2, dl);
1169 if (Result.getNode()->getNumValues() == 1) break;
1171 assert(Result.getNode()->getNumValues() == 2 &&
1172 "Cannot return more than two values!");
1174 // Since we produced two values, make sure to remember that we
1175 // legalized both of them.
1176 Tmp1 = LegalizeOp(Result);
1177 Tmp2 = LegalizeOp(Result.getValue(1));
1178 AddLegalizedOperand(Op.getValue(0), Tmp1);
1179 AddLegalizedOperand(Op.getValue(1), Tmp2);
1180 return Op.getResNo() ? Tmp2 : Tmp1;
1181 case ISD::EH_RETURN: {
1182 MVT VT = Node->getValueType(0);
1183 // The only "good" option for this node is to custom lower it.
1184 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1185 default: assert(0 && "This action is not supported at all!");
1186 case TargetLowering::Custom:
1187 Result = TLI.LowerOperation(Op, DAG);
1188 if (Result.getNode()) break;
1190 case TargetLowering::Legal:
1191 // Target does not know, how to lower this, lower to noop
1192 Result = LegalizeOp(Node->getOperand(0));
1197 case ISD::AssertSext:
1198 case ISD::AssertZext:
1199 Tmp1 = LegalizeOp(Node->getOperand(0));
1200 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1202 case ISD::MERGE_VALUES:
1203 // Legalize eliminates MERGE_VALUES nodes.
1204 Result = Node->getOperand(Op.getResNo());
1206 case ISD::CopyFromReg:
1207 Tmp1 = LegalizeOp(Node->getOperand(0));
1208 Result = Op.getValue(0);
1209 if (Node->getNumValues() == 2) {
1210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1212 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1213 if (Node->getNumOperands() == 3) {
1214 Tmp2 = LegalizeOp(Node->getOperand(2));
1215 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1217 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1219 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1221 // Since CopyFromReg produces two values, make sure to remember that we
1222 // legalized both of them.
1223 AddLegalizedOperand(Op.getValue(0), Result);
1224 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1225 return Result.getValue(Op.getResNo());
1227 MVT VT = Op.getValueType();
1228 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1229 default: assert(0 && "This action is not supported yet!");
1230 case TargetLowering::Expand:
1232 Result = DAG.getConstant(0, VT);
1233 else if (VT.isFloatingPoint())
1234 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1237 assert(0 && "Unknown value type!");
1239 case TargetLowering::Legal:
1245 case ISD::INTRINSIC_W_CHAIN:
1246 case ISD::INTRINSIC_WO_CHAIN:
1247 case ISD::INTRINSIC_VOID: {
1248 SmallVector<SDValue, 8> Ops;
1249 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1250 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1251 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1253 // Allow the target to custom lower its intrinsics if it wants to.
1254 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1255 TargetLowering::Custom) {
1256 Tmp3 = TLI.LowerOperation(Result, DAG);
1257 if (Tmp3.getNode()) Result = Tmp3;
1260 if (Result.getNode()->getNumValues() == 1) break;
1262 // Must have return value and chain result.
1263 assert(Result.getNode()->getNumValues() == 2 &&
1264 "Cannot return more than two values!");
1266 // Since loads produce two values, make sure to remember that we
1267 // legalized both of them.
1268 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1269 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1270 return Result.getValue(Op.getResNo());
1273 case ISD::DBG_STOPPOINT:
1274 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1275 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1277 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1278 case TargetLowering::Promote:
1279 default: assert(0 && "This action is not supported yet!");
1280 case TargetLowering::Expand: {
1281 DwarfWriter *DW = DAG.getDwarfWriter();
1282 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1284 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1286 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1287 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1288 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1289 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1290 std::string Dir, FN;
1291 unsigned SrcFile = DW->getOrCreateSourceID(CU.getDirectory(Dir),
1292 CU.getFilename(FN));
1294 unsigned Line = DSP->getLine();
1295 unsigned Col = DSP->getColumn();
1298 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1299 // won't hurt anything.
1301 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1302 DAG.getConstant(Col, MVT::i32),
1303 DAG.getConstant(SrcFile, MVT::i32) };
1304 Result = DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Ops, 4);
1306 unsigned ID = DW->RecordSourceLine(Line, Col, SrcFile);
1307 Result = DAG.getLabel(ISD::DBG_LABEL, dl, Tmp1, ID);
1310 Result = Tmp1; // chain
1313 Result = Tmp1; // chain
1317 case TargetLowering::Legal: {
1318 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1319 if (Action == Legal && Tmp1 == Node->getOperand(0))
1322 SmallVector<SDValue, 8> Ops;
1323 Ops.push_back(Tmp1);
1324 if (Action == Legal) {
1325 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1326 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1328 // Otherwise promote them.
1329 Ops.push_back(PromoteOp(Node->getOperand(1)));
1330 Ops.push_back(PromoteOp(Node->getOperand(2)));
1332 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1333 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1334 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1341 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1342 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1343 default: assert(0 && "This action is not supported yet!");
1344 case TargetLowering::Legal:
1345 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1346 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1347 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1348 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1350 case TargetLowering::Expand:
1351 Result = LegalizeOp(Node->getOperand(0));
1356 case ISD::DEBUG_LOC:
1357 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1358 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1359 default: assert(0 && "This action is not supported yet!");
1360 case TargetLowering::Legal: {
1361 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1362 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1363 if (Action == Legal && Tmp1 == Node->getOperand(0))
1365 if (Action == Legal) {
1366 Tmp2 = Node->getOperand(1);
1367 Tmp3 = Node->getOperand(2);
1368 Tmp4 = Node->getOperand(3);
1370 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1371 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1372 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1380 case ISD::DBG_LABEL:
1382 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1383 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1384 default: assert(0 && "This action is not supported yet!");
1385 case TargetLowering::Legal:
1386 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1387 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1389 case TargetLowering::Expand:
1390 Result = LegalizeOp(Node->getOperand(0));
1396 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1397 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1398 default: assert(0 && "This action is not supported yet!");
1399 case TargetLowering::Legal:
1400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1401 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1402 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1403 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1404 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1406 case TargetLowering::Expand:
1408 Result = LegalizeOp(Node->getOperand(0));
1413 case ISD::MEMBARRIER: {
1414 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1415 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1416 default: assert(0 && "This action is not supported yet!");
1417 case TargetLowering::Legal: {
1419 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1420 for (int x = 1; x < 6; ++x) {
1421 Ops[x] = Node->getOperand(x);
1422 if (!isTypeLegal(Ops[x].getValueType()))
1423 Ops[x] = PromoteOp(Ops[x]);
1425 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1428 case TargetLowering::Expand:
1429 //There is no libgcc call for this op
1430 Result = Node->getOperand(0); // Noop
1436 case ISD::ATOMIC_CMP_SWAP: {
1437 unsigned int num_operands = 4;
1438 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1440 for (unsigned int x = 0; x < num_operands; ++x)
1441 Ops[x] = LegalizeOp(Node->getOperand(x));
1442 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1444 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1445 default: assert(0 && "This action is not supported yet!");
1446 case TargetLowering::Custom:
1447 Result = TLI.LowerOperation(Result, DAG);
1449 case TargetLowering::Legal:
1452 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1453 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1454 return Result.getValue(Op.getResNo());
1456 case ISD::ATOMIC_LOAD_ADD:
1457 case ISD::ATOMIC_LOAD_SUB:
1458 case ISD::ATOMIC_LOAD_AND:
1459 case ISD::ATOMIC_LOAD_OR:
1460 case ISD::ATOMIC_LOAD_XOR:
1461 case ISD::ATOMIC_LOAD_NAND:
1462 case ISD::ATOMIC_LOAD_MIN:
1463 case ISD::ATOMIC_LOAD_MAX:
1464 case ISD::ATOMIC_LOAD_UMIN:
1465 case ISD::ATOMIC_LOAD_UMAX:
1466 case ISD::ATOMIC_SWAP: {
1467 unsigned int num_operands = 3;
1468 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1470 for (unsigned int x = 0; x < num_operands; ++x)
1471 Ops[x] = LegalizeOp(Node->getOperand(x));
1472 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1474 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1475 default: assert(0 && "This action is not supported yet!");
1476 case TargetLowering::Custom:
1477 Result = TLI.LowerOperation(Result, DAG);
1479 case TargetLowering::Legal:
1482 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1483 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1484 return Result.getValue(Op.getResNo());
1486 case ISD::Constant: {
1487 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1489 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1491 // We know we don't need to expand constants here, constants only have one
1492 // value and we check that it is fine above.
1494 if (opAction == TargetLowering::Custom) {
1495 Tmp1 = TLI.LowerOperation(Result, DAG);
1501 case ISD::ConstantFP: {
1502 // Spill FP immediates to the constant pool if the target cannot directly
1503 // codegen them. Targets often have some immediate values that can be
1504 // efficiently generated into an FP register without a load. We explicitly
1505 // leave these constants as ConstantFP nodes for the target to deal with.
1506 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1508 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1509 default: assert(0 && "This action is not supported yet!");
1510 case TargetLowering::Legal:
1512 case TargetLowering::Custom:
1513 Tmp3 = TLI.LowerOperation(Result, DAG);
1514 if (Tmp3.getNode()) {
1519 case TargetLowering::Expand: {
1520 // Check to see if this FP immediate is already legal.
1521 bool isLegal = false;
1522 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1523 E = TLI.legal_fpimm_end(); I != E; ++I) {
1524 if (CFP->isExactlyValue(*I)) {
1529 // If this is a legal constant, turn it into a TargetConstantFP node.
1532 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1537 case ISD::TokenFactor:
1538 if (Node->getNumOperands() == 2) {
1539 Tmp1 = LegalizeOp(Node->getOperand(0));
1540 Tmp2 = LegalizeOp(Node->getOperand(1));
1541 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1542 } else if (Node->getNumOperands() == 3) {
1543 Tmp1 = LegalizeOp(Node->getOperand(0));
1544 Tmp2 = LegalizeOp(Node->getOperand(1));
1545 Tmp3 = LegalizeOp(Node->getOperand(2));
1546 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1548 SmallVector<SDValue, 8> Ops;
1549 // Legalize the operands.
1550 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1551 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1552 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1556 case ISD::FORMAL_ARGUMENTS:
1558 // The only option for this is to custom lower it.
1559 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1560 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1561 // A call within a calling sequence must be legalized to something
1562 // other than the normal CALLSEQ_END. Violating this gets Legalize
1563 // into an infinite loop.
1564 assert ((!IsLegalizingCall ||
1565 Node->getOpcode() != ISD::CALL ||
1566 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1567 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1569 // The number of incoming and outgoing values should match; unless the final
1570 // outgoing value is a flag.
1571 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1572 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1573 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1575 "Lowering call/formal_arguments produced unexpected # results!");
1577 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1578 // remember that we legalized all of them, so it doesn't get relegalized.
1579 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1580 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1582 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1583 if (Op.getResNo() == i)
1585 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1588 case ISD::EXTRACT_SUBREG: {
1589 Tmp1 = LegalizeOp(Node->getOperand(0));
1590 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1591 assert(idx && "Operand must be a constant");
1592 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1593 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1596 case ISD::INSERT_SUBREG: {
1597 Tmp1 = LegalizeOp(Node->getOperand(0));
1598 Tmp2 = LegalizeOp(Node->getOperand(1));
1599 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1600 assert(idx && "Operand must be a constant");
1601 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1602 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1605 case ISD::BUILD_VECTOR:
1606 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1607 default: assert(0 && "This action is not supported yet!");
1608 case TargetLowering::Custom:
1609 Tmp3 = TLI.LowerOperation(Result, DAG);
1610 if (Tmp3.getNode()) {
1615 case TargetLowering::Expand:
1616 Result = ExpandBUILD_VECTOR(Result.getNode());
1620 case ISD::INSERT_VECTOR_ELT:
1621 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1622 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1624 // The type of the value to insert may not be legal, even though the vector
1625 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1627 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1628 default: assert(0 && "Cannot expand insert element operand");
1629 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1630 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1632 // FIXME: An alternative would be to check to see if the target is not
1633 // going to custom lower this operation, we could bitcast to half elt
1634 // width and perform two inserts at that width, if that is legal.
1635 Tmp2 = Node->getOperand(1);
1638 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1640 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1641 Node->getValueType(0))) {
1642 default: assert(0 && "This action is not supported yet!");
1643 case TargetLowering::Legal:
1645 case TargetLowering::Custom:
1646 Tmp4 = TLI.LowerOperation(Result, DAG);
1647 if (Tmp4.getNode()) {
1652 case TargetLowering::Promote:
1653 // Fall thru for vector case
1654 case TargetLowering::Expand: {
1655 // If the insert index is a constant, codegen this as a scalar_to_vector,
1656 // then a shuffle that inserts it into the right position in the vector.
1657 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1658 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1659 // match the element type of the vector being created.
1660 if (Tmp2.getValueType() ==
1661 Op.getValueType().getVectorElementType()) {
1662 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
1663 Tmp1.getValueType(), Tmp2);
1665 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1667 MVT::getIntVectorWithNumElements(NumElts);
1668 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1670 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1671 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1672 // elt 0 of the RHS.
1673 SmallVector<SDValue, 8> ShufOps;
1674 for (unsigned i = 0; i != NumElts; ++i) {
1675 if (i != InsertPos->getZExtValue())
1676 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1678 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1680 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, ShufMaskVT,
1681 &ShufOps[0], ShufOps.size());
1683 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Tmp1.getValueType(),
1684 Tmp1, ScVec, ShufMask);
1685 Result = LegalizeOp(Result);
1689 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3, dl);
1694 case ISD::SCALAR_TO_VECTOR:
1695 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1696 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1700 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1701 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1702 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1703 Node->getValueType(0))) {
1704 default: assert(0 && "This action is not supported yet!");
1705 case TargetLowering::Legal:
1707 case TargetLowering::Custom:
1708 Tmp3 = TLI.LowerOperation(Result, DAG);
1709 if (Tmp3.getNode()) {
1714 case TargetLowering::Expand:
1715 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1719 case ISD::VECTOR_SHUFFLE:
1720 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1721 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1722 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1724 // Allow targets to custom lower the SHUFFLEs they support.
1725 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1726 default: assert(0 && "Unknown operation action!");
1727 case TargetLowering::Legal:
1728 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1729 "vector shuffle should not be created if not legal!");
1731 case TargetLowering::Custom:
1732 Tmp3 = TLI.LowerOperation(Result, DAG);
1733 if (Tmp3.getNode()) {
1738 case TargetLowering::Expand: {
1739 MVT VT = Node->getValueType(0);
1740 MVT EltVT = VT.getVectorElementType();
1741 MVT PtrVT = TLI.getPointerTy();
1742 SDValue Mask = Node->getOperand(2);
1743 unsigned NumElems = Mask.getNumOperands();
1744 SmallVector<SDValue,8> Ops;
1745 for (unsigned i = 0; i != NumElems; ++i) {
1746 SDValue Arg = Mask.getOperand(i);
1747 if (Arg.getOpcode() == ISD::UNDEF) {
1748 Ops.push_back(DAG.getUNDEF(EltVT));
1750 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1751 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1753 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp1,
1754 DAG.getConstant(Idx, PtrVT)));
1756 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Tmp2,
1757 DAG.getConstant(Idx - NumElems, PtrVT)));
1760 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
1763 case TargetLowering::Promote: {
1764 // Change base type to a different vector type.
1765 MVT OVT = Node->getValueType(0);
1766 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1768 // Cast the two input vectors.
1769 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
1770 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
1772 // Convert the shuffle mask to the right # elements.
1773 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1774 assert(Tmp3.getNode() && "Shuffle not legal?");
1775 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NVT, Tmp1, Tmp2, Tmp3);
1776 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
1782 case ISD::EXTRACT_VECTOR_ELT:
1783 Tmp1 = Node->getOperand(0);
1784 Tmp2 = LegalizeOp(Node->getOperand(1));
1785 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1786 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1789 case ISD::EXTRACT_SUBVECTOR:
1790 Tmp1 = Node->getOperand(0);
1791 Tmp2 = LegalizeOp(Node->getOperand(1));
1792 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1793 Result = ExpandEXTRACT_SUBVECTOR(Result);
1796 case ISD::CONCAT_VECTORS: {
1797 // Use extract/insert/build vector for now. We might try to be
1798 // more clever later.
1799 MVT PtrVT = TLI.getPointerTy();
1800 SmallVector<SDValue, 8> Ops;
1801 unsigned NumOperands = Node->getNumOperands();
1802 for (unsigned i=0; i < NumOperands; ++i) {
1803 SDValue SubOp = Node->getOperand(i);
1804 MVT VVT = SubOp.getNode()->getValueType(0);
1805 MVT EltVT = VVT.getVectorElementType();
1806 unsigned NumSubElem = VVT.getVectorNumElements();
1807 for (unsigned j=0; j < NumSubElem; ++j) {
1808 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1809 DAG.getConstant(j, PtrVT)));
1812 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
1813 &Ops[0], Ops.size()));
1816 case ISD::CALLSEQ_START: {
1817 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1819 // Recursively Legalize all of the inputs of the call end that do not lead
1820 // to this call start. This ensures that any libcalls that need be inserted
1821 // are inserted *before* the CALLSEQ_START.
1822 IsLegalizingCallArgs = true;
1823 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1824 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1825 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1828 IsLegalizingCallArgs = false;
1830 // Now that we legalized all of the inputs (which may have inserted
1831 // libcalls) create the new CALLSEQ_START node.
1832 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1834 // Merge in the last call, to ensure that this call start after the last
1836 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1837 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1838 Tmp1, LastCALLSEQ_END);
1839 Tmp1 = LegalizeOp(Tmp1);
1842 // Do not try to legalize the target-specific arguments (#1+).
1843 if (Tmp1 != Node->getOperand(0)) {
1844 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1846 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1849 // Remember that the CALLSEQ_START is legalized.
1850 AddLegalizedOperand(Op.getValue(0), Result);
1851 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1852 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1854 // Now that the callseq_start and all of the non-call nodes above this call
1855 // sequence have been legalized, legalize the call itself. During this
1856 // process, no libcalls can/will be inserted, guaranteeing that no calls
1858 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1859 // Note that we are selecting this call!
1860 LastCALLSEQ_END = SDValue(CallEnd, 0);
1861 IsLegalizingCall = true;
1863 // Legalize the call, starting from the CALLSEQ_END.
1864 LegalizeOp(LastCALLSEQ_END);
1865 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1868 case ISD::CALLSEQ_END:
1869 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1870 // will cause this node to be legalized as well as handling libcalls right.
1871 if (LastCALLSEQ_END.getNode() != Node) {
1872 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1873 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1874 assert(I != LegalizedNodes.end() &&
1875 "Legalizing the call start should have legalized this node!");
1879 // Otherwise, the call start has been legalized and everything is going
1880 // according to plan. Just legalize ourselves normally here.
1881 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1882 // Do not try to legalize the target-specific arguments (#1+), except for
1883 // an optional flag input.
1884 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1885 if (Tmp1 != Node->getOperand(0)) {
1886 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1888 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1891 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1892 if (Tmp1 != Node->getOperand(0) ||
1893 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1894 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1897 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1900 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1901 // This finishes up call legalization.
1902 IsLegalizingCall = false;
1904 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1905 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1906 if (Node->getNumValues() == 2)
1907 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1908 return Result.getValue(Op.getResNo());
1909 case ISD::DYNAMIC_STACKALLOC: {
1910 MVT VT = Node->getValueType(0);
1911 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1912 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1913 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1914 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1916 Tmp1 = Result.getValue(0);
1917 Tmp2 = Result.getValue(1);
1918 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1919 default: assert(0 && "This action is not supported yet!");
1920 case TargetLowering::Expand: {
1921 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1922 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1923 " not tell us which reg is the stack pointer!");
1924 SDValue Chain = Tmp1.getOperand(0);
1926 // Chain the dynamic stack allocation so that it doesn't modify the stack
1927 // pointer when other instructions are using the stack.
1928 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1930 SDValue Size = Tmp2.getOperand(1);
1931 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1932 Chain = SP.getValue(1);
1933 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1934 unsigned StackAlign =
1935 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1936 if (Align > StackAlign)
1937 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1938 DAG.getConstant(-(uint64_t)Align, VT));
1939 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1940 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1942 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1943 DAG.getIntPtrConstant(0, true), SDValue());
1945 Tmp1 = LegalizeOp(Tmp1);
1946 Tmp2 = LegalizeOp(Tmp2);
1949 case TargetLowering::Custom:
1950 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1951 if (Tmp3.getNode()) {
1952 Tmp1 = LegalizeOp(Tmp3);
1953 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1956 case TargetLowering::Legal:
1959 // Since this op produce two values, make sure to remember that we
1960 // legalized both of them.
1961 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1962 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1963 return Op.getResNo() ? Tmp2 : Tmp1;
1965 case ISD::INLINEASM: {
1966 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1967 bool Changed = false;
1968 // Legalize all of the operands of the inline asm, in case they are nodes
1969 // that need to be expanded or something. Note we skip the asm string and
1970 // all of the TargetConstant flags.
1971 SDValue Op = LegalizeOp(Ops[0]);
1972 Changed = Op != Ops[0];
1975 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1976 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1977 unsigned NumVals = InlineAsm::
1978 getNumOperandRegisters(cast<ConstantSDNode>(Ops[i])->getZExtValue());
1979 for (++i; NumVals; ++i, --NumVals) {
1980 SDValue Op = LegalizeOp(Ops[i]);
1989 Op = LegalizeOp(Ops.back());
1990 Changed |= Op != Ops.back();
1995 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1997 // INLINE asm returns a chain and flag, make sure to add both to the map.
1998 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1999 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2000 return Result.getValue(Op.getResNo());
2003 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2004 // Ensure that libcalls are emitted before a branch.
2005 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2006 Tmp1 = LegalizeOp(Tmp1);
2007 LastCALLSEQ_END = DAG.getEntryNode();
2009 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2012 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2013 // Ensure that libcalls are emitted before a branch.
2014 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2015 Tmp1 = LegalizeOp(Tmp1);
2016 LastCALLSEQ_END = DAG.getEntryNode();
2018 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2019 default: assert(0 && "Indirect target must be legal type (pointer)!");
2021 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2024 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2027 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2028 // Ensure that libcalls are emitted before a branch.
2029 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2030 Tmp1 = LegalizeOp(Tmp1);
2031 LastCALLSEQ_END = DAG.getEntryNode();
2033 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2034 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2036 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2037 default: assert(0 && "This action is not supported yet!");
2038 case TargetLowering::Legal: break;
2039 case TargetLowering::Custom:
2040 Tmp1 = TLI.LowerOperation(Result, DAG);
2041 if (Tmp1.getNode()) Result = Tmp1;
2043 case TargetLowering::Expand: {
2044 SDValue Chain = Result.getOperand(0);
2045 SDValue Table = Result.getOperand(1);
2046 SDValue Index = Result.getOperand(2);
2048 MVT PTy = TLI.getPointerTy();
2049 MachineFunction &MF = DAG.getMachineFunction();
2050 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2051 Index= DAG.getNode(ISD::MUL, dl, PTy,
2052 Index, DAG.getConstant(EntrySize, PTy));
2053 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2055 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2056 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2057 PseudoSourceValue::getJumpTable(), 0, MemVT);
2059 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2060 // For PIC, the sequence is:
2061 // BRIND(load(Jumptable + index) + RelocBase)
2062 // RelocBase can be JumpTable, GOT or some sort of global base.
2063 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2064 TLI.getPICJumpTableRelocBase(Table, DAG));
2066 Result = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2071 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2072 // Ensure that libcalls are emitted before a return.
2073 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2074 Tmp1 = LegalizeOp(Tmp1);
2075 LastCALLSEQ_END = DAG.getEntryNode();
2077 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2078 case Expand: assert(0 && "It's impossible to expand bools");
2080 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2083 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2085 // The top bits of the promoted condition are not necessarily zero, ensure
2086 // that the value is properly zero extended.
2087 unsigned BitWidth = Tmp2.getValueSizeInBits();
2088 if (!DAG.MaskedValueIsZero(Tmp2,
2089 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2090 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, MVT::i1);
2095 // Basic block destination (Op#2) is always legal.
2096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2098 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2099 default: assert(0 && "This action is not supported yet!");
2100 case TargetLowering::Legal: break;
2101 case TargetLowering::Custom:
2102 Tmp1 = TLI.LowerOperation(Result, DAG);
2103 if (Tmp1.getNode()) Result = Tmp1;
2105 case TargetLowering::Expand:
2106 // Expand brcond's setcc into its constituent parts and create a BR_CC
2108 if (Tmp2.getOpcode() == ISD::SETCC) {
2109 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2110 Tmp1, Tmp2.getOperand(2),
2111 Tmp2.getOperand(0), Tmp2.getOperand(1),
2112 Node->getOperand(2));
2114 Result = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2115 DAG.getCondCode(ISD::SETNE), Tmp2,
2116 DAG.getConstant(0, Tmp2.getValueType()),
2117 Node->getOperand(2));
2123 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2124 // Ensure that libcalls are emitted before a branch.
2125 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2126 Tmp1 = LegalizeOp(Tmp1);
2127 Tmp2 = Node->getOperand(2); // LHS
2128 Tmp3 = Node->getOperand(3); // RHS
2129 Tmp4 = Node->getOperand(1); // CC
2131 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
2132 Tmp2, Tmp3, Tmp4, dl);
2133 LastCALLSEQ_END = DAG.getEntryNode();
2135 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2136 // the LHS is a legal SETCC itself. In this case, we need to compare
2137 // the result against zero to select between true and false values.
2138 if (Tmp3.getNode() == 0) {
2139 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2140 Tmp4 = DAG.getCondCode(ISD::SETNE);
2143 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2144 Node->getOperand(4));
2146 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2147 default: assert(0 && "Unexpected action for BR_CC!");
2148 case TargetLowering::Legal: break;
2149 case TargetLowering::Custom:
2150 Tmp4 = TLI.LowerOperation(Result, DAG);
2151 if (Tmp4.getNode()) Result = Tmp4;
2156 LoadSDNode *LD = cast<LoadSDNode>(Node);
2157 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2158 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2160 ISD::LoadExtType ExtType = LD->getExtensionType();
2161 if (ExtType == ISD::NON_EXTLOAD) {
2162 MVT VT = Node->getValueType(0);
2163 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2164 Tmp3 = Result.getValue(0);
2165 Tmp4 = Result.getValue(1);
2167 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2168 default: assert(0 && "This action is not supported yet!");
2169 case TargetLowering::Legal:
2170 // If this is an unaligned load and the target doesn't support it,
2172 if (!TLI.allowsUnalignedMemoryAccesses()) {
2173 unsigned ABIAlignment = TLI.getTargetData()->
2174 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2175 if (LD->getAlignment() < ABIAlignment){
2176 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2178 Tmp3 = Result.getOperand(0);
2179 Tmp4 = Result.getOperand(1);
2180 Tmp3 = LegalizeOp(Tmp3);
2181 Tmp4 = LegalizeOp(Tmp4);
2185 case TargetLowering::Custom:
2186 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2187 if (Tmp1.getNode()) {
2188 Tmp3 = LegalizeOp(Tmp1);
2189 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2192 case TargetLowering::Promote: {
2193 // Only promote a load of vector type to another.
2194 assert(VT.isVector() && "Cannot promote this load!");
2195 // Change base type to a different vector type.
2196 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2198 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2199 LD->getSrcValueOffset(),
2200 LD->isVolatile(), LD->getAlignment());
2201 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
2202 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2206 // Since loads produce two values, make sure to remember that we
2207 // legalized both of them.
2208 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2209 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2210 return Op.getResNo() ? Tmp4 : Tmp3;
2212 MVT SrcVT = LD->getMemoryVT();
2213 unsigned SrcWidth = SrcVT.getSizeInBits();
2214 int SVOffset = LD->getSrcValueOffset();
2215 unsigned Alignment = LD->getAlignment();
2216 bool isVolatile = LD->isVolatile();
2218 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2219 // Some targets pretend to have an i1 loading operation, and actually
2220 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2221 // bits are guaranteed to be zero; it helps the optimizers understand
2222 // that these bits are zero. It is also useful for EXTLOAD, since it
2223 // tells the optimizers that those bits are undefined. It would be
2224 // nice to have an effective generic way of getting these benefits...
2225 // Until such a way is found, don't insist on promoting i1 here.
2226 (SrcVT != MVT::i1 ||
2227 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2228 // Promote to a byte-sized load if not loading an integral number of
2229 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2230 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2231 MVT NVT = MVT::getIntegerVT(NewWidth);
2234 // The extra bits are guaranteed to be zero, since we stored them that
2235 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2237 ISD::LoadExtType NewExtType =
2238 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2240 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
2241 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2242 NVT, isVolatile, Alignment);
2244 Ch = Result.getValue(1); // The chain.
2246 if (ExtType == ISD::SEXTLOAD)
2247 // Having the top bits zero doesn't help when sign extending.
2248 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2249 Result.getValueType(),
2250 Result, DAG.getValueType(SrcVT));
2251 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2252 // All the top bits are guaranteed to be zero - inform the optimizers.
2253 Result = DAG.getNode(ISD::AssertZext, dl,
2254 Result.getValueType(), Result,
2255 DAG.getValueType(SrcVT));
2257 Tmp1 = LegalizeOp(Result);
2258 Tmp2 = LegalizeOp(Ch);
2259 } else if (SrcWidth & (SrcWidth - 1)) {
2260 // If not loading a power-of-2 number of bits, expand as two loads.
2261 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2262 "Unsupported extload!");
2263 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2264 assert(RoundWidth < SrcWidth);
2265 unsigned ExtraWidth = SrcWidth - RoundWidth;
2266 assert(ExtraWidth < RoundWidth);
2267 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2268 "Load size not an integral number of bytes!");
2269 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2270 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2272 unsigned IncrementSize;
2274 if (TLI.isLittleEndian()) {
2275 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2276 // Load the bottom RoundWidth bits.
2277 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2278 Node->getValueType(0), Tmp1, Tmp2,
2279 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2282 // Load the remaining ExtraWidth bits.
2283 IncrementSize = RoundWidth / 8;
2284 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2285 DAG.getIntPtrConstant(IncrementSize));
2286 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2287 LD->getSrcValue(), SVOffset + IncrementSize,
2288 ExtraVT, isVolatile,
2289 MinAlign(Alignment, IncrementSize));
2291 // Build a factor node to remember that this load is independent of the
2293 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2296 // Move the top bits to the right place.
2297 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2298 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2300 // Join the hi and lo parts.
2301 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2303 // Big endian - avoid unaligned loads.
2304 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2305 // Load the top RoundWidth bits.
2306 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
2307 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2310 // Load the remaining ExtraWidth bits.
2311 IncrementSize = RoundWidth / 8;
2312 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2313 DAG.getIntPtrConstant(IncrementSize));
2314 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
2315 Node->getValueType(0), Tmp1, Tmp2,
2316 LD->getSrcValue(), SVOffset + IncrementSize,
2317 ExtraVT, isVolatile,
2318 MinAlign(Alignment, IncrementSize));
2320 // Build a factor node to remember that this load is independent of the
2322 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
2325 // Move the top bits to the right place.
2326 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
2327 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2329 // Join the hi and lo parts.
2330 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
2333 Tmp1 = LegalizeOp(Result);
2334 Tmp2 = LegalizeOp(Ch);
2336 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2337 default: assert(0 && "This action is not supported yet!");
2338 case TargetLowering::Custom:
2341 case TargetLowering::Legal:
2342 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2343 Tmp1 = Result.getValue(0);
2344 Tmp2 = Result.getValue(1);
2347 Tmp3 = TLI.LowerOperation(Result, DAG);
2348 if (Tmp3.getNode()) {
2349 Tmp1 = LegalizeOp(Tmp3);
2350 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2353 // If this is an unaligned load and the target doesn't support it,
2355 if (!TLI.allowsUnalignedMemoryAccesses()) {
2356 unsigned ABIAlignment = TLI.getTargetData()->
2357 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2358 if (LD->getAlignment() < ABIAlignment){
2359 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2361 Tmp1 = Result.getOperand(0);
2362 Tmp2 = Result.getOperand(1);
2363 Tmp1 = LegalizeOp(Tmp1);
2364 Tmp2 = LegalizeOp(Tmp2);
2369 case TargetLowering::Expand:
2370 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2371 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2372 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
2373 LD->getSrcValueOffset(),
2374 LD->isVolatile(), LD->getAlignment());
2375 Result = DAG.getNode(ISD::FP_EXTEND, dl,
2376 Node->getValueType(0), Load);
2377 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2378 Tmp2 = LegalizeOp(Load.getValue(1));
2381 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2382 // Turn the unsupported load into an EXTLOAD followed by an explicit
2383 // zero/sign extend inreg.
2384 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
2385 Tmp1, Tmp2, LD->getSrcValue(),
2386 LD->getSrcValueOffset(), SrcVT,
2387 LD->isVolatile(), LD->getAlignment());
2389 if (ExtType == ISD::SEXTLOAD)
2390 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
2391 Result.getValueType(),
2392 Result, DAG.getValueType(SrcVT));
2394 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
2395 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2396 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2401 // Since loads produce two values, make sure to remember that we legalized
2403 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2404 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2405 return Op.getResNo() ? Tmp2 : Tmp1;
2408 case ISD::EXTRACT_ELEMENT: {
2409 MVT OpTy = Node->getOperand(0).getValueType();
2410 switch (getTypeAction(OpTy)) {
2411 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2413 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2415 Result = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2416 DAG.getConstant(OpTy.getSizeInBits()/2,
2417 TLI.getShiftAmountTy()));
2418 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Result);
2421 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2422 Node->getOperand(0));
2426 // Get both the low and high parts.
2427 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2428 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2429 Result = Tmp2; // 1 -> Hi
2431 Result = Tmp1; // 0 -> Lo
2437 case ISD::CopyToReg:
2438 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2440 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2441 "Register type must be legal!");
2442 // Legalize the incoming value (must be a legal type).
2443 Tmp2 = LegalizeOp(Node->getOperand(2));
2444 if (Node->getNumValues() == 1) {
2445 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2447 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2448 if (Node->getNumOperands() == 4) {
2449 Tmp3 = LegalizeOp(Node->getOperand(3));
2450 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2453 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2456 // Since this produces two values, make sure to remember that we legalized
2458 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2459 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2465 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2467 // Ensure that libcalls are emitted before a return.
2468 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
2469 Tmp1 = LegalizeOp(Tmp1);
2470 LastCALLSEQ_END = DAG.getEntryNode();
2472 switch (Node->getNumOperands()) {
2474 Tmp2 = Node->getOperand(1);
2475 Tmp3 = Node->getOperand(2); // Signness
2476 switch (getTypeAction(Tmp2.getValueType())) {
2478 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2481 if (!Tmp2.getValueType().isVector()) {
2483 ExpandOp(Tmp2, Lo, Hi);
2485 // Big endian systems want the hi reg first.
2486 if (TLI.isBigEndian())
2490 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2491 Tmp1, Lo, Tmp3, Hi,Tmp3);
2493 Result = DAG.getNode(ISD::RET, dl, MVT::Other, Tmp1, Lo, Tmp3);
2494 Result = LegalizeOp(Result);
2496 SDNode *InVal = Tmp2.getNode();
2497 int InIx = Tmp2.getResNo();
2498 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2499 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2501 // Figure out if there is a simple type corresponding to this Vector
2502 // type. If so, convert to the vector type.
2503 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2504 if (TLI.isTypeLegal(TVT)) {
2505 // Turn this into a return of the vector type.
2506 Tmp2 = LegalizeOp(Tmp2);
2507 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2508 } else if (NumElems == 1) {
2509 // Turn this into a return of the scalar type.
2510 Tmp2 = ScalarizeVectorOp(Tmp2);
2511 Tmp2 = LegalizeOp(Tmp2);
2512 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2514 // FIXME: Returns of gcc generic vectors smaller than a legal type
2515 // should be returned in integer registers!
2517 // The scalarized value type may not be legal, e.g. it might require
2518 // promotion or expansion. Relegalize the return.
2519 Result = LegalizeOp(Result);
2521 // FIXME: Returns of gcc generic vectors larger than a legal vector
2522 // type should be returned by reference!
2524 SplitVectorOp(Tmp2, Lo, Hi);
2525 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2526 Tmp1, Lo, Tmp3, Hi,Tmp3);
2527 Result = LegalizeOp(Result);
2532 Tmp2 = PromoteOp(Node->getOperand(1));
2533 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2534 Result = LegalizeOp(Result);
2539 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2541 default: { // ret <values>
2542 SmallVector<SDValue, 8> NewValues;
2543 NewValues.push_back(Tmp1);
2544 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2545 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2547 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2548 NewValues.push_back(Node->getOperand(i+1));
2552 assert(!Node->getOperand(i).getValueType().isExtended() &&
2553 "FIXME: TODO: implement returning non-legal vector types!");
2554 ExpandOp(Node->getOperand(i), Lo, Hi);
2555 NewValues.push_back(Lo);
2556 NewValues.push_back(Node->getOperand(i+1));
2558 NewValues.push_back(Hi);
2559 NewValues.push_back(Node->getOperand(i+1));
2564 assert(0 && "Can't promote multiple return value yet!");
2567 if (NewValues.size() == Node->getNumOperands())
2568 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2570 Result = DAG.getNode(ISD::RET, dl, MVT::Other,
2571 &NewValues[0], NewValues.size());
2576 if (Result.getOpcode() == ISD::RET) {
2577 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2578 default: assert(0 && "This action is not supported yet!");
2579 case TargetLowering::Legal: break;
2580 case TargetLowering::Custom:
2581 Tmp1 = TLI.LowerOperation(Result, DAG);
2582 if (Tmp1.getNode()) Result = Tmp1;
2588 StoreSDNode *ST = cast<StoreSDNode>(Node);
2589 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2590 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2591 int SVOffset = ST->getSrcValueOffset();
2592 unsigned Alignment = ST->getAlignment();
2593 bool isVolatile = ST->isVolatile();
2595 if (!ST->isTruncatingStore()) {
2596 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2597 // FIXME: We shouldn't do this for TargetConstantFP's.
2598 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2599 // to phase ordering between legalized code and the dag combiner. This
2600 // probably means that we need to integrate dag combiner and legalizer
2602 // We generally can't do this one for long doubles.
2603 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2604 if (CFP->getValueType(0) == MVT::f32 &&
2605 getTypeAction(MVT::i32) == Legal) {
2606 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2607 bitcastToAPInt().zextOrTrunc(32),
2609 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2610 SVOffset, isVolatile, Alignment);
2612 } else if (CFP->getValueType(0) == MVT::f64) {
2613 // If this target supports 64-bit registers, do a single 64-bit store.
2614 if (getTypeAction(MVT::i64) == Legal) {
2615 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2616 zextOrTrunc(64), MVT::i64);
2617 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2618 SVOffset, isVolatile, Alignment);
2620 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2621 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2622 // stores. If the target supports neither 32- nor 64-bits, this
2623 // xform is certainly not worth it.
2624 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2625 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2626 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2627 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2629 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2630 SVOffset, isVolatile, Alignment);
2631 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2632 DAG.getIntPtrConstant(4));
2633 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2634 isVolatile, MinAlign(Alignment, 4U));
2636 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2642 switch (getTypeAction(ST->getMemoryVT())) {
2644 Tmp3 = LegalizeOp(ST->getValue());
2645 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2648 MVT VT = Tmp3.getValueType();
2649 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2650 default: assert(0 && "This action is not supported yet!");
2651 case TargetLowering::Legal:
2652 // If this is an unaligned store and the target doesn't support it,
2654 if (!TLI.allowsUnalignedMemoryAccesses()) {
2655 unsigned ABIAlignment = TLI.getTargetData()->
2656 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2657 if (ST->getAlignment() < ABIAlignment)
2658 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2662 case TargetLowering::Custom:
2663 Tmp1 = TLI.LowerOperation(Result, DAG);
2664 if (Tmp1.getNode()) Result = Tmp1;
2666 case TargetLowering::Promote:
2667 assert(VT.isVector() && "Unknown legal promote case!");
2668 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
2669 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2670 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
2671 ST->getSrcValue(), SVOffset, isVolatile,
2678 if (!ST->getMemoryVT().isVector()) {
2679 // Truncate the value and store the result.
2680 Tmp3 = PromoteOp(ST->getValue());
2681 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2682 SVOffset, ST->getMemoryVT(),
2683 isVolatile, Alignment);
2686 // Fall thru to expand for vector
2688 unsigned IncrementSize = 0;
2691 // If this is a vector type, then we have to calculate the increment as
2692 // the product of the element size in bytes, and the number of elements
2693 // in the high half of the vector.
2694 if (ST->getValue().getValueType().isVector()) {
2695 SDNode *InVal = ST->getValue().getNode();
2696 int InIx = ST->getValue().getResNo();
2697 MVT InVT = InVal->getValueType(InIx);
2698 unsigned NumElems = InVT.getVectorNumElements();
2699 MVT EVT = InVT.getVectorElementType();
2701 // Figure out if there is a simple type corresponding to this Vector
2702 // type. If so, convert to the vector type.
2703 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2704 if (TLI.isTypeLegal(TVT)) {
2705 // Turn this into a normal store of the vector type.
2706 Tmp3 = LegalizeOp(ST->getValue());
2707 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2708 SVOffset, isVolatile, Alignment);
2709 Result = LegalizeOp(Result);
2711 } else if (NumElems == 1) {
2712 // Turn this into a normal store of the scalar type.
2713 Tmp3 = ScalarizeVectorOp(ST->getValue());
2714 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2715 SVOffset, isVolatile, Alignment);
2716 // The scalarized value type may not be legal, e.g. it might require
2717 // promotion or expansion. Relegalize the scalar store.
2718 Result = LegalizeOp(Result);
2721 // Check if we have widen this node with another value
2722 std::map<SDValue, SDValue>::iterator I =
2723 WidenNodes.find(ST->getValue());
2724 if (I != WidenNodes.end()) {
2725 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2729 SplitVectorOp(ST->getValue(), Lo, Hi);
2730 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2731 EVT.getSizeInBits()/8;
2735 ExpandOp(ST->getValue(), Lo, Hi);
2736 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2738 if (Hi.getNode() && TLI.isBigEndian())
2742 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
2743 SVOffset, isVolatile, Alignment);
2745 if (Hi.getNode() == NULL) {
2746 // Must be int <-> float one-to-one expansion.
2751 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2752 DAG.getIntPtrConstant(IncrementSize));
2753 assert(isTypeLegal(Tmp2.getValueType()) &&
2754 "Pointers must be legal!");
2755 SVOffset += IncrementSize;
2756 Alignment = MinAlign(Alignment, IncrementSize);
2757 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2758 SVOffset, isVolatile, Alignment);
2759 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2764 switch (getTypeAction(ST->getValue().getValueType())) {
2766 Tmp3 = LegalizeOp(ST->getValue());
2769 if (!ST->getValue().getValueType().isVector()) {
2770 // We can promote the value, the truncstore will still take care of it.
2771 Tmp3 = PromoteOp(ST->getValue());
2774 // Vector case falls through to expand
2776 // Just store the low part. This may become a non-trunc store, so make
2777 // sure to use getTruncStore, not UpdateNodeOperands below.
2778 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2779 return DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2780 SVOffset, MVT::i8, isVolatile, Alignment);
2783 MVT StVT = ST->getMemoryVT();
2784 unsigned StWidth = StVT.getSizeInBits();
2786 if (StWidth != StVT.getStoreSizeInBits()) {
2787 // Promote to a byte-sized store with upper bits zero if not
2788 // storing an integral number of bytes. For example, promote
2789 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2790 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2791 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
2792 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2793 SVOffset, NVT, isVolatile, Alignment);
2794 } else if (StWidth & (StWidth - 1)) {
2795 // If not storing a power-of-2 number of bits, expand as two stores.
2796 assert(StVT.isExtended() && !StVT.isVector() &&
2797 "Unsupported truncstore!");
2798 unsigned RoundWidth = 1 << Log2_32(StWidth);
2799 assert(RoundWidth < StWidth);
2800 unsigned ExtraWidth = StWidth - RoundWidth;
2801 assert(ExtraWidth < RoundWidth);
2802 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2803 "Store size not an integral number of bytes!");
2804 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2805 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2807 unsigned IncrementSize;
2809 if (TLI.isLittleEndian()) {
2810 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2811 // Store the bottom RoundWidth bits.
2812 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2814 isVolatile, Alignment);
2816 // Store the remaining ExtraWidth bits.
2817 IncrementSize = RoundWidth / 8;
2818 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2819 DAG.getIntPtrConstant(IncrementSize));
2820 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2821 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2822 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2823 SVOffset + IncrementSize, ExtraVT, isVolatile,
2824 MinAlign(Alignment, IncrementSize));
2826 // Big endian - avoid unaligned stores.
2827 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2828 // Store the top RoundWidth bits.
2829 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
2830 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2831 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
2832 SVOffset, RoundVT, isVolatile, Alignment);
2834 // Store the remaining ExtraWidth bits.
2835 IncrementSize = RoundWidth / 8;
2836 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
2837 DAG.getIntPtrConstant(IncrementSize));
2838 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2839 SVOffset + IncrementSize, ExtraVT, isVolatile,
2840 MinAlign(Alignment, IncrementSize));
2843 // The order of the stores doesn't matter.
2844 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
2846 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2847 Tmp2 != ST->getBasePtr())
2848 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2851 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2852 default: assert(0 && "This action is not supported yet!");
2853 case TargetLowering::Legal:
2854 // If this is an unaligned store and the target doesn't support it,
2856 if (!TLI.allowsUnalignedMemoryAccesses()) {
2857 unsigned ABIAlignment = TLI.getTargetData()->
2858 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2859 if (ST->getAlignment() < ABIAlignment)
2860 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2864 case TargetLowering::Custom:
2865 Result = TLI.LowerOperation(Result, DAG);
2868 // TRUNCSTORE:i16 i32 -> STORE i16
2869 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2870 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
2871 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
2872 SVOffset, isVolatile, Alignment);
2880 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2881 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2883 case ISD::STACKSAVE:
2884 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2885 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2886 Tmp1 = Result.getValue(0);
2887 Tmp2 = Result.getValue(1);
2889 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2890 default: assert(0 && "This action is not supported yet!");
2891 case TargetLowering::Legal: break;
2892 case TargetLowering::Custom:
2893 Tmp3 = TLI.LowerOperation(Result, DAG);
2894 if (Tmp3.getNode()) {
2895 Tmp1 = LegalizeOp(Tmp3);
2896 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2899 case TargetLowering::Expand:
2900 // Expand to CopyFromReg if the target set
2901 // StackPointerRegisterToSaveRestore.
2902 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2903 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), dl, SP,
2904 Node->getValueType(0));
2905 Tmp2 = Tmp1.getValue(1);
2907 Tmp1 = DAG.getUNDEF(Node->getValueType(0));
2908 Tmp2 = Node->getOperand(0);
2913 // Since stacksave produce two values, make sure to remember that we
2914 // legalized both of them.
2915 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2916 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2917 return Op.getResNo() ? Tmp2 : Tmp1;
2919 case ISD::STACKRESTORE:
2920 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2921 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2922 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2924 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2925 default: assert(0 && "This action is not supported yet!");
2926 case TargetLowering::Legal: break;
2927 case TargetLowering::Custom:
2928 Tmp1 = TLI.LowerOperation(Result, DAG);
2929 if (Tmp1.getNode()) Result = Tmp1;
2931 case TargetLowering::Expand:
2932 // Expand to CopyToReg if the target set
2933 // StackPointerRegisterToSaveRestore.
2934 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2935 Result = DAG.getCopyToReg(Tmp1, dl, SP, Tmp2);
2943 case ISD::READCYCLECOUNTER:
2944 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2945 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2946 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2947 Node->getValueType(0))) {
2948 default: assert(0 && "This action is not supported yet!");
2949 case TargetLowering::Legal:
2950 Tmp1 = Result.getValue(0);
2951 Tmp2 = Result.getValue(1);
2953 case TargetLowering::Custom:
2954 Result = TLI.LowerOperation(Result, DAG);
2955 Tmp1 = LegalizeOp(Result.getValue(0));
2956 Tmp2 = LegalizeOp(Result.getValue(1));
2960 // Since rdcc produce two values, make sure to remember that we legalized
2962 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2963 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2967 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2968 case Expand: assert(0 && "It's impossible to expand bools");
2970 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2973 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2974 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2975 // Make sure the condition is either zero or one.
2976 unsigned BitWidth = Tmp1.getValueSizeInBits();
2977 if (!DAG.MaskedValueIsZero(Tmp1,
2978 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2979 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, MVT::i1);
2983 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2984 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2986 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2988 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2989 default: assert(0 && "This action is not supported yet!");
2990 case TargetLowering::Legal: break;
2991 case TargetLowering::Custom: {
2992 Tmp1 = TLI.LowerOperation(Result, DAG);
2993 if (Tmp1.getNode()) Result = Tmp1;
2996 case TargetLowering::Expand:
2997 if (Tmp1.getOpcode() == ISD::SETCC) {
2998 Result = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3000 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3002 Result = DAG.getSelectCC(dl, Tmp1,
3003 DAG.getConstant(0, Tmp1.getValueType()),
3004 Tmp2, Tmp3, ISD::SETNE);
3007 case TargetLowering::Promote: {
3009 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
3010 unsigned ExtOp, TruncOp;
3011 if (Tmp2.getValueType().isVector()) {
3012 ExtOp = ISD::BIT_CONVERT;
3013 TruncOp = ISD::BIT_CONVERT;
3014 } else if (Tmp2.getValueType().isInteger()) {
3015 ExtOp = ISD::ANY_EXTEND;
3016 TruncOp = ISD::TRUNCATE;
3018 ExtOp = ISD::FP_EXTEND;
3019 TruncOp = ISD::FP_ROUND;
3021 // Promote each of the values to the new type.
3022 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Tmp2);
3023 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Tmp3);
3024 // Perform the larger operation, then round down.
3025 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2,Tmp3);
3026 if (TruncOp != ISD::FP_ROUND)
3027 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result);
3029 Result = DAG.getNode(TruncOp, dl, Node->getValueType(0), Result,
3030 DAG.getIntPtrConstant(0));
3035 case ISD::SELECT_CC: {
3036 Tmp1 = Node->getOperand(0); // LHS
3037 Tmp2 = Node->getOperand(1); // RHS
3038 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3039 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3040 SDValue CC = Node->getOperand(4);
3042 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
3043 Tmp1, Tmp2, CC, dl);
3045 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3046 // the LHS is a legal SETCC itself. In this case, we need to compare
3047 // the result against zero to select between true and false values.
3048 if (Tmp2.getNode() == 0) {
3049 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3050 CC = DAG.getCondCode(ISD::SETNE);
3052 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3054 // Everything is legal, see if we should expand this op or something.
3055 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3056 default: assert(0 && "This action is not supported yet!");
3057 case TargetLowering::Legal: break;
3058 case TargetLowering::Custom:
3059 Tmp1 = TLI.LowerOperation(Result, DAG);
3060 if (Tmp1.getNode()) Result = Tmp1;
3066 Tmp1 = Node->getOperand(0);
3067 Tmp2 = Node->getOperand(1);
3068 Tmp3 = Node->getOperand(2);
3069 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3071 // If we had to Expand the SetCC operands into a SELECT node, then it may
3072 // not always be possible to return a true LHS & RHS. In this case, just
3073 // return the value we legalized, returned in the LHS
3074 if (Tmp2.getNode() == 0) {
3079 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3080 default: assert(0 && "Cannot handle this action for SETCC yet!");
3081 case TargetLowering::Custom:
3084 case TargetLowering::Legal:
3085 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3087 Tmp4 = TLI.LowerOperation(Result, DAG);
3088 if (Tmp4.getNode()) Result = Tmp4;
3091 case TargetLowering::Promote: {
3092 // First step, figure out the appropriate operation to use.
3093 // Allow SETCC to not be supported for all legal data types
3094 // Mostly this targets FP
3095 MVT NewInTy = Node->getOperand(0).getValueType();
3096 MVT OldVT = NewInTy; OldVT = OldVT;
3098 // Scan for the appropriate larger type to use.
3100 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3102 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3103 "Fell off of the edge of the integer world");
3104 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3105 "Fell off of the edge of the floating point world");
3107 // If the target supports SETCC of this type, use it.
3108 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3111 if (NewInTy.isInteger())
3112 assert(0 && "Cannot promote Legal Integer SETCC yet");
3114 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3115 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3117 Tmp1 = LegalizeOp(Tmp1);
3118 Tmp2 = LegalizeOp(Tmp2);
3119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3120 Result = LegalizeOp(Result);
3123 case TargetLowering::Expand:
3124 // Expand a setcc node into a select_cc of the same condition, lhs, and
3125 // rhs that selects between const 1 (true) and const 0 (false).
3126 MVT VT = Node->getValueType(0);
3127 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3128 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3134 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3135 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3136 SDValue CC = Node->getOperand(2);
3138 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3140 // Everything is legal, see if we should expand this op or something.
3141 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3142 default: assert(0 && "This action is not supported yet!");
3143 case TargetLowering::Legal: break;
3144 case TargetLowering::Custom:
3145 Tmp1 = TLI.LowerOperation(Result, DAG);
3146 if (Tmp1.getNode()) Result = Tmp1;
3148 case TargetLowering::Expand: {
3149 // Unroll into a nasty set of scalar code for now.
3150 MVT VT = Node->getValueType(0);
3151 unsigned NumElems = VT.getVectorNumElements();
3152 MVT EltVT = VT.getVectorElementType();
3153 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3154 SmallVector<SDValue, 8> Ops(NumElems);
3155 for (unsigned i = 0; i < NumElems; ++i) {
3156 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT,
3157 Tmp1, DAG.getIntPtrConstant(i));
3158 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT),
3159 In1, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
3161 DAG.getIntPtrConstant(i)),
3163 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], DAG.getConstant(
3164 APInt::getAllOnesValue(EltVT.getSizeInBits()),
3165 EltVT), DAG.getConstant(0, EltVT));
3167 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
3174 case ISD::SHL_PARTS:
3175 case ISD::SRA_PARTS:
3176 case ISD::SRL_PARTS: {
3177 SmallVector<SDValue, 8> Ops;
3178 bool Changed = false;
3179 unsigned N = Node->getNumOperands();
3180 for (unsigned i = 0; i + 1 < N; ++i) {
3181 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3182 Changed |= Ops.back() != Node->getOperand(i);
3184 Ops.push_back(LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(N-1))));
3185 Changed |= Ops.back() != Node->getOperand(N-1);
3187 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3189 switch (TLI.getOperationAction(Node->getOpcode(),
3190 Node->getValueType(0))) {
3191 default: assert(0 && "This action is not supported yet!");
3192 case TargetLowering::Legal: break;
3193 case TargetLowering::Custom:
3194 Tmp1 = TLI.LowerOperation(Result, DAG);
3195 if (Tmp1.getNode()) {
3196 SDValue Tmp2, RetVal(0, 0);
3197 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3198 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3199 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3200 if (i == Op.getResNo())
3203 assert(RetVal.getNode() && "Illegal result number");
3209 // Since these produce multiple values, make sure to remember that we
3210 // legalized all of them.
3211 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3212 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3213 return Result.getValue(Op.getResNo());
3235 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3236 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3238 if ((Node->getOpcode() == ISD::SHL ||
3239 Node->getOpcode() == ISD::SRL ||
3240 Node->getOpcode() == ISD::SRA) &&
3241 !Node->getValueType(0).isVector())
3242 Tmp2 = DAG.getShiftAmountOperand(Tmp2);
3244 switch (getTypeAction(Tmp2.getValueType())) {
3245 case Expand: assert(0 && "Not possible");
3247 Tmp2 = LegalizeOp(Tmp2); // Legalize the RHS.
3250 Tmp2 = PromoteOp(Tmp2); // Promote the RHS.
3254 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3256 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3257 default: assert(0 && "BinOp legalize operation not supported");
3258 case TargetLowering::Legal: break;
3259 case TargetLowering::Custom:
3260 Tmp1 = TLI.LowerOperation(Result, DAG);
3261 if (Tmp1.getNode()) {
3265 // Fall through if the custom lower can't deal with the operation
3266 case TargetLowering::Expand: {
3267 MVT VT = Op.getValueType();
3269 // See if multiply or divide can be lowered using two-result operations.
3270 SDVTList VTs = DAG.getVTList(VT, VT);
3271 if (Node->getOpcode() == ISD::MUL) {
3272 // We just need the low half of the multiply; try both the signed
3273 // and unsigned forms. If the target supports both SMUL_LOHI and
3274 // UMUL_LOHI, form a preference by checking which forms of plain
3275 // MULH it supports.
3276 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3277 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3278 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3279 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3280 unsigned OpToUse = 0;
3281 if (HasSMUL_LOHI && !HasMULHS) {
3282 OpToUse = ISD::SMUL_LOHI;
3283 } else if (HasUMUL_LOHI && !HasMULHU) {
3284 OpToUse = ISD::UMUL_LOHI;
3285 } else if (HasSMUL_LOHI) {
3286 OpToUse = ISD::SMUL_LOHI;
3287 } else if (HasUMUL_LOHI) {
3288 OpToUse = ISD::UMUL_LOHI;
3291 Result = SDValue(DAG.getNode(OpToUse, dl, VTs, Tmp1, Tmp2).getNode(),
3296 if (Node->getOpcode() == ISD::MULHS &&
3297 TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) {
3298 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl,
3299 VTs, Tmp1, Tmp2).getNode(),
3303 if (Node->getOpcode() == ISD::MULHU &&
3304 TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) {
3305 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl,
3306 VTs, Tmp1, Tmp2).getNode(),
3310 if (Node->getOpcode() == ISD::SDIV &&
3311 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3312 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3313 VTs, Tmp1, Tmp2).getNode(),
3317 if (Node->getOpcode() == ISD::UDIV &&
3318 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3319 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3320 VTs, Tmp1, Tmp2).getNode(),
3325 // Check to see if we have a libcall for this operator.
3326 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3327 bool isSigned = false;
3328 switch (Node->getOpcode()) {
3331 if (VT == MVT::i32) {
3332 LC = Node->getOpcode() == ISD::UDIV
3333 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3334 isSigned = Node->getOpcode() == ISD::SDIV;
3339 LC = RTLIB::MUL_I32;
3340 else if (VT == MVT::i64)
3341 LC = RTLIB::MUL_I64;
3344 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3345 RTLIB::POW_PPCF128);
3348 LC = GetFPLibCall(VT, RTLIB::DIV_F32, RTLIB::DIV_F64, RTLIB::DIV_F80,
3349 RTLIB::DIV_PPCF128);
3353 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3355 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3359 assert(Node->getValueType(0).isVector() &&
3360 "Cannot expand this binary operator!");
3361 // Expand the operation into a bunch of nasty scalar code.
3362 Result = LegalizeOp(UnrollVectorOp(Op));
3365 case TargetLowering::Promote: {
3366 switch (Node->getOpcode()) {
3367 default: assert(0 && "Do not know how to promote this BinOp!");
3371 MVT OVT = Node->getValueType(0);
3372 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3373 assert(OVT.isVector() && "Cannot promote this BinOp!");
3374 // Bit convert each of the values to the new type.
3375 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp1);
3376 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Tmp2);
3377 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3378 // Bit convert the result back the original type.
3379 Result = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Result);
3387 case ISD::SMUL_LOHI:
3388 case ISD::UMUL_LOHI:
3391 // These nodes will only be produced by target-specific lowering, so
3392 // they shouldn't be here if they aren't legal.
3393 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3394 "This must be legal!");
3396 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3397 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3398 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3401 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3402 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3403 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3404 case Expand: assert(0 && "Not possible");
3406 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3409 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3415 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3416 default: assert(0 && "Operation not supported");
3417 case TargetLowering::Custom:
3418 Tmp1 = TLI.LowerOperation(Result, DAG);
3419 if (Tmp1.getNode()) Result = Tmp1;
3421 case TargetLowering::Legal: break;
3422 case TargetLowering::Expand: {
3423 // If this target supports fabs/fneg natively and select is cheap,
3424 // do this efficiently.
3425 if (!TLI.isSelectExpensive() &&
3426 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3427 TargetLowering::Legal &&
3428 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3429 TargetLowering::Legal) {
3430 // Get the sign bit of the RHS.
3432 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3433 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
3434 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(IVT),
3435 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3436 // Get the absolute value of the result.
3437 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
3438 // Select between the nabs and abs value based on the sign bit of
3440 Result = DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
3441 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(),
3444 Result = LegalizeOp(Result);
3448 // Otherwise, do bitwise ops!
3450 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3451 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3452 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Result);
3453 Result = LegalizeOp(Result);
3461 Tmp1 = LegalizeOp(Node->getOperand(0));
3462 Tmp2 = LegalizeOp(Node->getOperand(1));
3463 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3464 Tmp3 = Result.getValue(0);
3465 Tmp4 = Result.getValue(1);
3467 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3468 default: assert(0 && "This action is not supported yet!");
3469 case TargetLowering::Legal:
3471 case TargetLowering::Custom:
3472 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3473 if (Tmp1.getNode() != NULL) {
3474 Tmp3 = LegalizeOp(Tmp1);
3475 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3479 // Since this produces two values, make sure to remember that we legalized
3481 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3482 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3483 return Op.getResNo() ? Tmp4 : Tmp3;
3487 Tmp1 = LegalizeOp(Node->getOperand(0));
3488 Tmp2 = LegalizeOp(Node->getOperand(1));
3489 Tmp3 = LegalizeOp(Node->getOperand(2));
3490 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3491 Tmp3 = Result.getValue(0);
3492 Tmp4 = Result.getValue(1);
3494 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3495 default: assert(0 && "This action is not supported yet!");
3496 case TargetLowering::Legal:
3498 case TargetLowering::Custom:
3499 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3500 if (Tmp1.getNode() != NULL) {
3501 Tmp3 = LegalizeOp(Tmp1);
3502 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3506 // Since this produces two values, make sure to remember that we legalized
3508 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3509 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3510 return Op.getResNo() ? Tmp4 : Tmp3;
3512 case ISD::BUILD_PAIR: {
3513 MVT PairTy = Node->getValueType(0);
3514 // TODO: handle the case where the Lo and Hi operands are not of legal type
3515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3516 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3517 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3518 case TargetLowering::Promote:
3519 case TargetLowering::Custom:
3520 assert(0 && "Cannot promote/custom this yet!");
3521 case TargetLowering::Legal:
3522 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3523 Result = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Tmp1, Tmp2);
3525 case TargetLowering::Expand:
3526 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Tmp1);
3527 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Tmp2);
3528 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3529 DAG.getConstant(PairTy.getSizeInBits()/2,
3530 TLI.getShiftAmountTy()));
3531 Result = DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2);
3540 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3541 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3543 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3544 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3545 case TargetLowering::Custom:
3548 case TargetLowering::Legal:
3549 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3551 Tmp1 = TLI.LowerOperation(Result, DAG);
3552 if (Tmp1.getNode()) Result = Tmp1;
3555 case TargetLowering::Expand: {
3556 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3557 bool isSigned = DivOpc == ISD::SDIV;
3558 MVT VT = Node->getValueType(0);
3560 // See if remainder can be lowered using two-result operations.
3561 SDVTList VTs = DAG.getVTList(VT, VT);
3562 if (Node->getOpcode() == ISD::SREM &&
3563 TLI.isOperationLegalOrCustom(ISD::SDIVREM, VT)) {
3564 Result = SDValue(DAG.getNode(ISD::SDIVREM, dl,
3565 VTs, Tmp1, Tmp2).getNode(), 1);
3568 if (Node->getOpcode() == ISD::UREM &&
3569 TLI.isOperationLegalOrCustom(ISD::UDIVREM, VT)) {
3570 Result = SDValue(DAG.getNode(ISD::UDIVREM, dl,
3571 VTs, Tmp1, Tmp2).getNode(), 1);
3575 if (VT.isInteger()) {
3576 if (TLI.getOperationAction(DivOpc, VT) ==
3577 TargetLowering::Legal) {
3579 Result = DAG.getNode(DivOpc, dl, VT, Tmp1, Tmp2);
3580 Result = DAG.getNode(ISD::MUL, dl, VT, Result, Tmp2);
3581 Result = DAG.getNode(ISD::SUB, dl, VT, Tmp1, Result);
3582 } else if (VT.isVector()) {
3583 Result = LegalizeOp(UnrollVectorOp(Op));
3585 assert(VT == MVT::i32 &&
3586 "Cannot expand this binary operator!");
3587 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3588 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3590 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3593 assert(VT.isFloatingPoint() &&
3594 "remainder op must have integer or floating-point type");
3595 if (VT.isVector()) {
3596 Result = LegalizeOp(UnrollVectorOp(Op));
3598 // Floating point mod -> fmod libcall.
3599 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3600 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3602 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3610 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3611 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3613 MVT VT = Node->getValueType(0);
3614 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3615 default: assert(0 && "This action is not supported yet!");
3616 case TargetLowering::Custom:
3619 case TargetLowering::Legal:
3620 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3621 Result = Result.getValue(0);
3622 Tmp1 = Result.getValue(1);
3625 Tmp2 = TLI.LowerOperation(Result, DAG);
3626 if (Tmp2.getNode()) {
3627 Result = LegalizeOp(Tmp2);
3628 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3632 case TargetLowering::Expand: {
3633 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3634 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
3635 // Increment the pointer, VAList, to the next vaarg
3636 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3637 DAG.getConstant(TLI.getTargetData()->
3638 getTypePaddedSize(VT.getTypeForMVT()),
3639 TLI.getPointerTy()));
3640 // Store the incremented VAList to the legalized pointer
3641 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
3642 // Load the actual argument out of the pointer VAList
3643 Result = DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0);
3644 Tmp1 = LegalizeOp(Result.getValue(1));
3645 Result = LegalizeOp(Result);
3649 // Since VAARG produces two values, make sure to remember that we
3650 // legalized both of them.
3651 AddLegalizedOperand(SDValue(Node, 0), Result);
3652 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3653 return Op.getResNo() ? Tmp1 : Result;
3657 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3658 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3659 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3661 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3662 default: assert(0 && "This action is not supported yet!");
3663 case TargetLowering::Custom:
3666 case TargetLowering::Legal:
3667 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3668 Node->getOperand(3), Node->getOperand(4));
3670 Tmp1 = TLI.LowerOperation(Result, DAG);
3671 if (Tmp1.getNode()) Result = Tmp1;
3674 case TargetLowering::Expand:
3675 // This defaults to loading a pointer from the input and storing it to the
3676 // output, returning the chain.
3677 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3678 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3679 Tmp4 = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp3, VS, 0);
3680 Result = DAG.getStore(Tmp4.getValue(1), dl, Tmp4, Tmp2, VD, 0);
3686 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3687 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3689 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3690 default: assert(0 && "This action is not supported yet!");
3691 case TargetLowering::Custom:
3694 case TargetLowering::Legal:
3695 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3697 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3698 if (Tmp1.getNode()) Result = Tmp1;
3701 case TargetLowering::Expand:
3702 Result = Tmp1; // Default to a no-op, return the chain
3708 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3709 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3711 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3713 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3714 default: assert(0 && "This action is not supported yet!");
3715 case TargetLowering::Legal: break;
3716 case TargetLowering::Custom:
3717 Tmp1 = TLI.LowerOperation(Result, DAG);
3718 if (Tmp1.getNode()) Result = Tmp1;
3725 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3726 Tmp2 = LegalizeOp(DAG.getShiftAmountOperand(Node->getOperand(1))); // RHS
3727 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3728 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3730 assert(0 && "ROTL/ROTR legalize operation not supported");
3732 case TargetLowering::Legal:
3734 case TargetLowering::Custom:
3735 Tmp1 = TLI.LowerOperation(Result, DAG);
3736 if (Tmp1.getNode()) Result = Tmp1;
3738 case TargetLowering::Promote:
3739 assert(0 && "Do not know how to promote ROTL/ROTR");
3741 case TargetLowering::Expand:
3742 assert(0 && "Do not know how to expand ROTL/ROTR");
3748 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3749 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3750 case TargetLowering::Custom:
3751 assert(0 && "Cannot custom legalize this yet!");
3752 case TargetLowering::Legal:
3753 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3755 case TargetLowering::Promote: {
3756 MVT OVT = Tmp1.getValueType();
3757 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3758 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3760 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3761 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3762 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3763 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3766 case TargetLowering::Expand:
3767 Result = ExpandBSWAP(Tmp1, dl);
3775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3776 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3777 case TargetLowering::Custom:
3778 case TargetLowering::Legal:
3779 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3780 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3781 TargetLowering::Custom) {
3782 Tmp1 = TLI.LowerOperation(Result, DAG);
3783 if (Tmp1.getNode()) {
3788 case TargetLowering::Promote: {
3789 MVT OVT = Tmp1.getValueType();
3790 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3792 // Zero extend the argument.
3793 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3794 // Perform the larger operation, then subtract if needed.
3795 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3796 switch (Node->getOpcode()) {
3801 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3802 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3803 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3805 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3806 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3809 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3810 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3811 DAG.getConstant(NVT.getSizeInBits() -
3812 OVT.getSizeInBits(), NVT));
3817 case TargetLowering::Expand:
3818 Result = ExpandBitCount(Node->getOpcode(), Tmp1, dl);
3838 case ISD::FNEARBYINT:
3839 Tmp1 = LegalizeOp(Node->getOperand(0));
3840 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3841 case TargetLowering::Promote:
3842 case TargetLowering::Custom:
3845 case TargetLowering::Legal:
3846 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3848 Tmp1 = TLI.LowerOperation(Result, DAG);
3849 if (Tmp1.getNode()) Result = Tmp1;
3852 case TargetLowering::Expand:
3853 switch (Node->getOpcode()) {
3854 default: assert(0 && "Unreachable!");
3856 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3857 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3858 Result = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp2, Tmp1);
3861 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3862 MVT VT = Node->getValueType(0);
3863 Tmp2 = DAG.getConstantFP(0.0, VT);
3864 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3865 Tmp1, Tmp2, ISD::SETUGT);
3866 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3867 Result = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3882 case ISD::FNEARBYINT: {
3883 MVT VT = Node->getValueType(0);
3885 // Expand unsupported unary vector operators by unrolling them.
3886 if (VT.isVector()) {
3887 Result = LegalizeOp(UnrollVectorOp(Op));
3891 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3892 switch(Node->getOpcode()) {
3894 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3895 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3898 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3899 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3902 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3903 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3906 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3907 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3910 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3911 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3914 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3915 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3918 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3919 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3922 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3923 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3926 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3927 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3930 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3931 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3934 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3935 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3938 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3939 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3941 case ISD::FNEARBYINT:
3942 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3943 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3946 default: assert(0 && "Unreachable!");
3949 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3957 MVT VT = Node->getValueType(0);
3959 // Expand unsupported unary vector operators by unrolling them.
3960 if (VT.isVector()) {
3961 Result = LegalizeOp(UnrollVectorOp(Op));
3965 // We always lower FPOWI into a libcall. No target support for it yet.
3966 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3967 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3969 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3972 case ISD::BIT_CONVERT:
3973 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3974 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3975 Node->getValueType(0), dl);
3976 } else if (Op.getOperand(0).getValueType().isVector()) {
3977 // The input has to be a vector type, we have to either scalarize it, pack
3978 // it, or convert it based on whether the input vector type is legal.
3979 SDNode *InVal = Node->getOperand(0).getNode();
3980 int InIx = Node->getOperand(0).getResNo();
3981 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3982 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3984 // Figure out if there is a simple type corresponding to this Vector
3985 // type. If so, convert to the vector type.
3986 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3987 if (TLI.isTypeLegal(TVT)) {
3988 // Turn this into a bit convert of the vector input.
3989 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3990 LegalizeOp(Node->getOperand(0)));
3992 } else if (NumElems == 1) {
3993 // Turn this into a bit convert of the scalar input.
3994 Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
3995 ScalarizeVectorOp(Node->getOperand(0)));
3998 // FIXME: UNIMP! Store then reload
3999 assert(0 && "Cast from unsupported vector type not implemented yet!");
4002 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
4003 Node->getOperand(0).getValueType())) {
4004 default: assert(0 && "Unknown operation action!");
4005 case TargetLowering::Expand:
4006 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4007 Node->getValueType(0), dl);
4009 case TargetLowering::Legal:
4010 Tmp1 = LegalizeOp(Node->getOperand(0));
4011 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4016 case ISD::CONVERT_RNDSAT: {
4017 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4019 default: assert(0 && "Unknown cvt code!");
4030 SDValue DTyOp = Node->getOperand(1);
4031 SDValue STyOp = Node->getOperand(2);
4032 SDValue RndOp = Node->getOperand(3);
4033 SDValue SatOp = Node->getOperand(4);
4034 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4035 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4037 Tmp1 = LegalizeOp(Node->getOperand(0));
4038 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4040 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4041 TargetLowering::Custom) {
4042 Tmp1 = TLI.LowerOperation(Result, DAG);
4043 if (Tmp1.getNode()) Result = Tmp1;
4047 Result = PromoteOp(Node->getOperand(0));
4048 // For FP, make Op1 a i32
4050 Result = DAG.getConvertRndSat(Op.getValueType(), dl, Result,
4051 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4056 } // end switch CvtCode
4059 // Conversion operators. The source and destination have different types.
4060 case ISD::SINT_TO_FP:
4061 case ISD::UINT_TO_FP: {
4062 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4063 Result = LegalizeINT_TO_FP(Result, isSigned,
4064 Node->getValueType(0), Node->getOperand(0), dl);
4068 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4070 Tmp1 = LegalizeOp(Node->getOperand(0));
4071 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4072 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4073 case TargetLowering::Custom:
4076 case TargetLowering::Legal:
4077 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4079 Tmp1 = TLI.LowerOperation(Result, DAG);
4080 if (Tmp1.getNode()) Result = Tmp1;
4083 case TargetLowering::Expand:
4084 assert(Result.getValueType().isVector() && "must be vector type");
4085 // Unroll the truncate. We should do better.
4086 Result = LegalizeOp(UnrollVectorOp(Result));
4090 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4092 // Since the result is legal, we should just be able to truncate the low
4093 // part of the source.
4094 Result = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
4097 Result = PromoteOp(Node->getOperand(0));
4098 Result = DAG.getNode(ISD::TRUNCATE, dl, Op.getValueType(), Result);
4103 case ISD::FP_TO_SINT:
4104 case ISD::FP_TO_UINT:
4105 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4107 Tmp1 = LegalizeOp(Node->getOperand(0));
4109 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4110 default: assert(0 && "Unknown operation action!");
4111 case TargetLowering::Custom:
4114 case TargetLowering::Legal:
4115 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4117 Tmp1 = TLI.LowerOperation(Result, DAG);
4118 if (Tmp1.getNode()) Result = Tmp1;
4121 case TargetLowering::Promote:
4122 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4123 Node->getOpcode() == ISD::FP_TO_SINT,
4126 case TargetLowering::Expand:
4127 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4128 SDValue True, False;
4129 MVT VT = Node->getOperand(0).getValueType();
4130 MVT NVT = Node->getValueType(0);
4131 const uint64_t zero[] = {0, 0};
4132 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4133 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4134 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4135 Tmp2 = DAG.getConstantFP(apf, VT);
4136 Tmp3 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
4137 Node->getOperand(0),
4139 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
4140 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
4141 DAG.getNode(ISD::FSUB, dl, VT,
4142 Node->getOperand(0), Tmp2));
4143 False = DAG.getNode(ISD::XOR, dl, NVT, False,
4144 DAG.getConstant(x, NVT));
4145 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp3, True, False);
4148 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4154 MVT VT = Op.getValueType();
4155 MVT OVT = Node->getOperand(0).getValueType();
4156 // Convert ppcf128 to i32
4157 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4158 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4159 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
4160 Node->getOperand(0), DAG.getValueType(MVT::f64));
4161 Result = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Result,
4162 DAG.getIntPtrConstant(1));
4163 Result = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Result);
4165 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4166 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4167 Tmp2 = DAG.getConstantFP(apf, OVT);
4168 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4169 // FIXME: generated code sucks.
4170 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Node->getOperand(0),
4172 DAG.getNode(ISD::ADD, dl, MVT::i32,
4173 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4174 DAG.getNode(ISD::FSUB, dl, OVT,
4175 Node->getOperand(0), Tmp2)),
4176 DAG.getConstant(0x80000000, MVT::i32)),
4177 DAG.getNode(ISD::FP_TO_SINT, dl, VT,
4178 Node->getOperand(0)),
4179 DAG.getCondCode(ISD::SETGE));
4183 // Convert f32 / f64 to i32 / i64 / i128.
4184 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4185 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4186 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4188 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4192 Tmp1 = PromoteOp(Node->getOperand(0));
4193 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4194 Result = LegalizeOp(Result);
4199 case ISD::FP_EXTEND: {
4200 MVT DstVT = Op.getValueType();
4201 MVT SrcVT = Op.getOperand(0).getValueType();
4202 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4203 // The only other way we can lower this is to turn it into a STORE,
4204 // LOAD pair, targetting a temporary location (a stack slot).
4205 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT, dl);
4208 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4209 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4211 Tmp1 = LegalizeOp(Node->getOperand(0));
4212 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4215 Tmp1 = PromoteOp(Node->getOperand(0));
4216 Result = DAG.getNode(ISD::FP_EXTEND, dl, Op.getValueType(), Tmp1);
4221 case ISD::FP_ROUND: {
4222 MVT DstVT = Op.getValueType();
4223 MVT SrcVT = Op.getOperand(0).getValueType();
4224 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4225 if (SrcVT == MVT::ppcf128) {
4227 ExpandOp(Node->getOperand(0), Lo, Result);
4228 // Round it the rest of the way (e.g. to f32) if needed.
4229 if (DstVT!=MVT::f64)
4230 Result = DAG.getNode(ISD::FP_ROUND, dl,
4231 DstVT, Result, Op.getOperand(1));
4234 // The only other way we can lower this is to turn it into a STORE,
4235 // LOAD pair, targetting a temporary location (a stack slot).
4236 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT, dl);
4239 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4240 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4242 Tmp1 = LegalizeOp(Node->getOperand(0));
4243 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4246 Tmp1 = PromoteOp(Node->getOperand(0));
4247 Result = DAG.getNode(ISD::FP_ROUND, dl, Op.getValueType(), Tmp1,
4248 Node->getOperand(1));
4253 case ISD::ANY_EXTEND:
4254 case ISD::ZERO_EXTEND:
4255 case ISD::SIGN_EXTEND:
4256 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4257 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4259 Tmp1 = LegalizeOp(Node->getOperand(0));
4260 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4261 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4262 TargetLowering::Custom) {
4263 Tmp1 = TLI.LowerOperation(Result, DAG);
4264 if (Tmp1.getNode()) Result = Tmp1;
4268 switch (Node->getOpcode()) {
4269 case ISD::ANY_EXTEND:
4270 Tmp1 = PromoteOp(Node->getOperand(0));
4271 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Tmp1);
4273 case ISD::ZERO_EXTEND:
4274 Result = PromoteOp(Node->getOperand(0));
4275 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4276 Result = DAG.getZeroExtendInReg(Result, dl,
4277 Node->getOperand(0).getValueType());
4279 case ISD::SIGN_EXTEND:
4280 Result = PromoteOp(Node->getOperand(0));
4281 Result = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Result);
4282 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4284 DAG.getValueType(Node->getOperand(0).getValueType()));
4289 case ISD::FP_ROUND_INREG:
4290 case ISD::SIGN_EXTEND_INREG: {
4291 Tmp1 = LegalizeOp(Node->getOperand(0));
4292 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4294 // If this operation is not supported, convert it to a shl/shr or load/store
4296 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4297 default: assert(0 && "This action not supported for this op yet!");
4298 case TargetLowering::Legal:
4299 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4301 case TargetLowering::Expand:
4302 // If this is an integer extend and shifts are supported, do that.
4303 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4304 // NOTE: we could fall back on load/store here too for targets without
4305 // SAR. However, it is doubtful that any exist.
4306 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4307 ExtraVT.getSizeInBits();
4308 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4309 Result = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
4310 Node->getOperand(0), ShiftCst);
4311 Result = DAG.getNode(ISD::SRA, dl, Node->getValueType(0),
4313 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4314 // The only way we can lower this is to turn it into a TRUNCSTORE,
4315 // EXTLOAD pair, targetting a temporary location (a stack slot).
4317 // NOTE: there is a choice here between constantly creating new stack
4318 // slots and always reusing the same one. We currently always create
4319 // new ones, as reuse may inhibit scheduling.
4320 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4321 Node->getValueType(0), dl);
4323 assert(0 && "Unknown op");
4329 case ISD::TRAMPOLINE: {
4331 for (unsigned i = 0; i != 6; ++i)
4332 Ops[i] = LegalizeOp(Node->getOperand(i));
4333 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4334 // The only option for this node is to custom lower it.
4335 Result = TLI.LowerOperation(Result, DAG);
4336 assert(Result.getNode() && "Should always custom lower!");
4338 // Since trampoline produces two values, make sure to remember that we
4339 // legalized both of them.
4340 Tmp1 = LegalizeOp(Result.getValue(1));
4341 Result = LegalizeOp(Result);
4342 AddLegalizedOperand(SDValue(Node, 0), Result);
4343 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4344 return Op.getResNo() ? Tmp1 : Result;
4346 case ISD::FLT_ROUNDS_: {
4347 MVT VT = Node->getValueType(0);
4348 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4349 default: assert(0 && "This action not supported for this op yet!");
4350 case TargetLowering::Custom:
4351 Result = TLI.LowerOperation(Op, DAG);
4352 if (Result.getNode()) break;
4354 case TargetLowering::Legal:
4355 // If this operation is not supported, lower it to constant 1
4356 Result = DAG.getConstant(1, VT);
4362 MVT VT = Node->getValueType(0);
4363 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4364 default: assert(0 && "This action not supported for this op yet!");
4365 case TargetLowering::Legal:
4366 Tmp1 = LegalizeOp(Node->getOperand(0));
4367 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4369 case TargetLowering::Custom:
4370 Result = TLI.LowerOperation(Op, DAG);
4371 if (Result.getNode()) break;
4373 case TargetLowering::Expand:
4374 // If this operation is not supported, lower it to 'abort()' call
4375 Tmp1 = LegalizeOp(Node->getOperand(0));
4376 TargetLowering::ArgListTy Args;
4377 std::pair<SDValue,SDValue> CallResult =
4378 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4379 false, false, false, false, CallingConv::C, false,
4380 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4382 Result = CallResult.second;
4390 MVT VT = Node->getValueType(0);
4391 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4392 default: assert(0 && "This action not supported for this op yet!");
4393 case TargetLowering::Custom:
4394 Result = TLI.LowerOperation(Op, DAG);
4395 if (Result.getNode()) break;
4397 case TargetLowering::Legal: {
4398 SDValue LHS = LegalizeOp(Node->getOperand(0));
4399 SDValue RHS = LegalizeOp(Node->getOperand(1));
4401 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4402 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4404 MVT OType = Node->getValueType(1);
4406 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4408 // LHSSign -> LHS >= 0
4409 // RHSSign -> RHS >= 0
4410 // SumSign -> Sum >= 0
4413 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4415 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4417 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
4418 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
4419 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
4420 Node->getOpcode() == ISD::SADDO ?
4421 ISD::SETEQ : ISD::SETNE);
4423 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
4424 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
4426 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
4428 MVT ValueVTs[] = { LHS.getValueType(), OType };
4429 SDValue Ops[] = { Sum, Cmp };
4431 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4432 DAG.getVTList(&ValueVTs[0], 2),
4434 SDNode *RNode = Result.getNode();
4435 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4436 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4445 MVT VT = Node->getValueType(0);
4446 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4447 default: assert(0 && "This action not supported for this op yet!");
4448 case TargetLowering::Custom:
4449 Result = TLI.LowerOperation(Op, DAG);
4450 if (Result.getNode()) break;
4452 case TargetLowering::Legal: {
4453 SDValue LHS = LegalizeOp(Node->getOperand(0));
4454 SDValue RHS = LegalizeOp(Node->getOperand(1));
4456 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4457 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
4459 MVT OType = Node->getValueType(1);
4460 SDValue Cmp = DAG.getSetCC(dl, OType, Sum, LHS,
4461 Node->getOpcode () == ISD::UADDO ?
4462 ISD::SETULT : ISD::SETUGT);
4464 MVT ValueVTs[] = { LHS.getValueType(), OType };
4465 SDValue Ops[] = { Sum, Cmp };
4467 Result = DAG.getNode(ISD::MERGE_VALUES, dl,
4468 DAG.getVTList(&ValueVTs[0], 2),
4470 SDNode *RNode = Result.getNode();
4471 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4472 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4481 MVT VT = Node->getValueType(0);
4482 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4483 default: assert(0 && "This action is not supported at all!");
4484 case TargetLowering::Custom:
4485 Result = TLI.LowerOperation(Op, DAG);
4486 if (Result.getNode()) break;
4488 case TargetLowering::Legal:
4489 // FIXME: According to Hacker's Delight, this can be implemented in
4490 // target independent lowering, but it would be inefficient, since it
4491 // requires a division + a branch.
4492 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4500 assert(Result.getValueType() == Op.getValueType() &&
4501 "Bad legalization!");
4503 // Make sure that the generated code is itself legal.
4505 Result = LegalizeOp(Result);
4507 // Note that LegalizeOp may be reentered even from single-use nodes, which
4508 // means that we always must cache transformed nodes.
4509 AddLegalizedOperand(Op, Result);
4513 /// PromoteOp - Given an operation that produces a value in an invalid type,
4514 /// promote it to compute the value into a larger type. The produced value will
4515 /// have the correct bits for the low portion of the register, but no guarantee
4516 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4517 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4518 MVT VT = Op.getValueType();
4519 MVT NVT = TLI.getTypeToTransformTo(VT);
4520 assert(getTypeAction(VT) == Promote &&
4521 "Caller should expand or legalize operands that are not promotable!");
4522 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4523 "Cannot promote to smaller type!");
4525 SDValue Tmp1, Tmp2, Tmp3;
4527 SDNode *Node = Op.getNode();
4528 DebugLoc dl = Node->getDebugLoc();
4530 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4531 if (I != PromotedNodes.end()) return I->second;
4533 switch (Node->getOpcode()) {
4534 case ISD::CopyFromReg:
4535 assert(0 && "CopyFromReg must be legal!");
4538 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4540 assert(0 && "Do not know how to promote this operator!");
4543 Result = DAG.getUNDEF(NVT);
4547 Result = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Op);
4549 Result = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Op);
4550 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4552 case ISD::ConstantFP:
4553 Result = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Op);
4554 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4558 MVT VT0 = Node->getOperand(0).getValueType();
4559 assert(isTypeLegal(TLI.getSetCCResultType(VT0))
4560 && "SetCC type is not legal??");
4561 Result = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(VT0),
4562 Node->getOperand(0), Node->getOperand(1),
4563 Node->getOperand(2));
4567 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4569 Result = LegalizeOp(Node->getOperand(0));
4570 assert(Result.getValueType().bitsGE(NVT) &&
4571 "This truncation doesn't make sense!");
4572 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4573 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Result);
4576 // The truncation is not required, because we don't guarantee anything
4577 // about high bits anyway.
4578 Result = PromoteOp(Node->getOperand(0));
4581 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4582 // Truncate the low part of the expanded value to the result type
4583 Result = DAG.getNode(ISD::TRUNCATE, dl, NVT, Tmp1);
4586 case ISD::SIGN_EXTEND:
4587 case ISD::ZERO_EXTEND:
4588 case ISD::ANY_EXTEND:
4589 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4590 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4592 // Input is legal? Just do extend all the way to the larger type.
4593 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4596 // Promote the reg if it's smaller.
4597 Result = PromoteOp(Node->getOperand(0));
4598 // The high bits are not guaranteed to be anything. Insert an extend.
4599 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4600 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4601 DAG.getValueType(Node->getOperand(0).getValueType()));
4602 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4603 Result = DAG.getZeroExtendInReg(Result, dl,
4604 Node->getOperand(0).getValueType());
4608 case ISD::CONVERT_RNDSAT: {
4609 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4610 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4611 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4612 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4613 "can only promote integers");
4614 Result = DAG.getConvertRndSat(NVT, dl, Node->getOperand(0),
4615 Node->getOperand(1), Node->getOperand(2),
4616 Node->getOperand(3), Node->getOperand(4),
4621 case ISD::BIT_CONVERT:
4622 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4623 Node->getValueType(0), dl);
4624 Result = PromoteOp(Result);
4627 case ISD::FP_EXTEND:
4628 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4630 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4631 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4632 case Promote: assert(0 && "Unreachable with 2 FP types!");
4634 if (Node->getConstantOperandVal(1) == 0) {
4635 // Input is legal? Do an FP_ROUND_INREG.
4636 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Node->getOperand(0),
4637 DAG.getValueType(VT));
4639 // Just remove the truncate, it isn't affecting the value.
4640 Result = DAG.getNode(ISD::FP_ROUND, dl, NVT, Node->getOperand(0),
4641 Node->getOperand(1));
4646 case ISD::SINT_TO_FP:
4647 case ISD::UINT_TO_FP:
4648 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4650 // No extra round required here.
4651 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Node->getOperand(0));
4655 Result = PromoteOp(Node->getOperand(0));
4656 if (Node->getOpcode() == ISD::SINT_TO_FP)
4657 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Result.getValueType(),
4659 DAG.getValueType(Node->getOperand(0).getValueType()));
4661 Result = DAG.getZeroExtendInReg(Result, dl,
4662 Node->getOperand(0).getValueType());
4663 // No extra round required here.
4664 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Result);
4667 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4668 Node->getOperand(0), dl);
4669 // Round if we cannot tolerate excess precision.
4670 if (NoExcessFPPrecision)
4671 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4672 DAG.getValueType(VT));
4677 case ISD::SIGN_EXTEND_INREG:
4678 Result = PromoteOp(Node->getOperand(0));
4679 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Result,
4680 Node->getOperand(1));
4682 case ISD::FP_TO_SINT:
4683 case ISD::FP_TO_UINT:
4684 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4687 Tmp1 = Node->getOperand(0);
4690 // The input result is prerounded, so we don't have to do anything
4692 Tmp1 = PromoteOp(Node->getOperand(0));
4695 // If we're promoting a UINT to a larger size, check to see if the new node
4696 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4697 // we can use that instead. This allows us to generate better code for
4698 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4699 // legal, such as PowerPC.
4700 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4701 !TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NVT) &&
4702 (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NVT) ||
4703 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4704 Result = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Tmp1);
4706 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4712 Tmp1 = PromoteOp(Node->getOperand(0));
4713 assert(Tmp1.getValueType() == NVT);
4714 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4715 // NOTE: we do not have to do any extra rounding here for
4716 // NoExcessFPPrecision, because we know the input will have the appropriate
4717 // precision, and these operations don't modify precision at all.
4732 case ISD::FNEARBYINT:
4733 Tmp1 = PromoteOp(Node->getOperand(0));
4734 assert(Tmp1.getValueType() == NVT);
4735 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4736 if (NoExcessFPPrecision)
4737 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4738 DAG.getValueType(VT));
4743 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4744 // directly as well, which may be better.
4745 Tmp1 = PromoteOp(Node->getOperand(0));
4746 Tmp2 = Node->getOperand(1);
4747 if (Node->getOpcode() == ISD::FPOW)
4748 Tmp2 = PromoteOp(Tmp2);
4749 assert(Tmp1.getValueType() == NVT);
4750 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4751 if (NoExcessFPPrecision)
4752 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4753 DAG.getValueType(VT));
4757 case ISD::ATOMIC_CMP_SWAP: {
4758 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4759 Tmp2 = PromoteOp(Node->getOperand(2));
4760 Tmp3 = PromoteOp(Node->getOperand(3));
4761 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4762 AtomNode->getChain(),
4763 AtomNode->getBasePtr(), Tmp2, Tmp3,
4764 AtomNode->getSrcValue(),
4765 AtomNode->getAlignment());
4766 // Remember that we legalized the chain.
4767 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4770 case ISD::ATOMIC_LOAD_ADD:
4771 case ISD::ATOMIC_LOAD_SUB:
4772 case ISD::ATOMIC_LOAD_AND:
4773 case ISD::ATOMIC_LOAD_OR:
4774 case ISD::ATOMIC_LOAD_XOR:
4775 case ISD::ATOMIC_LOAD_NAND:
4776 case ISD::ATOMIC_LOAD_MIN:
4777 case ISD::ATOMIC_LOAD_MAX:
4778 case ISD::ATOMIC_LOAD_UMIN:
4779 case ISD::ATOMIC_LOAD_UMAX:
4780 case ISD::ATOMIC_SWAP: {
4781 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4782 Tmp2 = PromoteOp(Node->getOperand(2));
4783 Result = DAG.getAtomic(Node->getOpcode(), dl, AtomNode->getMemoryVT(),
4784 AtomNode->getChain(),
4785 AtomNode->getBasePtr(), Tmp2,
4786 AtomNode->getSrcValue(),
4787 AtomNode->getAlignment());
4788 // Remember that we legalized the chain.
4789 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4799 // The input may have strange things in the top bits of the registers, but
4800 // these operations don't care. They may have weird bits going out, but
4801 // that too is okay if they are integer operations.
4802 Tmp1 = PromoteOp(Node->getOperand(0));
4803 Tmp2 = PromoteOp(Node->getOperand(1));
4804 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4805 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4810 Tmp1 = PromoteOp(Node->getOperand(0));
4811 Tmp2 = PromoteOp(Node->getOperand(1));
4812 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4813 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4815 // Floating point operations will give excess precision that we may not be
4816 // able to tolerate. If we DO allow excess precision, just leave it,
4817 // otherwise excise it.
4818 // FIXME: Why would we need to round FP ops more than integer ones?
4819 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4820 if (NoExcessFPPrecision)
4821 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4822 DAG.getValueType(VT));
4827 // These operators require that their input be sign extended.
4828 Tmp1 = PromoteOp(Node->getOperand(0));
4829 Tmp2 = PromoteOp(Node->getOperand(1));
4830 if (NVT.isInteger()) {
4831 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4832 DAG.getValueType(VT));
4833 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
4834 DAG.getValueType(VT));
4836 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4838 // Perform FP_ROUND: this is probably overly pessimistic.
4839 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4840 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4841 DAG.getValueType(VT));
4845 case ISD::FCOPYSIGN:
4846 // These operators require that their input be fp extended.
4847 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4848 case Expand: assert(0 && "not implemented");
4849 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4850 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4852 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4853 case Expand: assert(0 && "not implemented");
4854 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4855 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4857 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4859 // Perform FP_ROUND: this is probably overly pessimistic.
4860 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4861 Result = DAG.getNode(ISD::FP_ROUND_INREG, dl, NVT, Result,
4862 DAG.getValueType(VT));
4867 // These operators require that their input be zero extended.
4868 Tmp1 = PromoteOp(Node->getOperand(0));
4869 Tmp2 = PromoteOp(Node->getOperand(1));
4870 assert(NVT.isInteger() && "Operators don't apply to FP!");
4871 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4872 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
4873 Result = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4877 Tmp1 = PromoteOp(Node->getOperand(0));
4878 Result = DAG.getNode(ISD::SHL, dl, NVT, Tmp1, Node->getOperand(1));
4881 // The input value must be properly sign extended.
4882 Tmp1 = PromoteOp(Node->getOperand(0));
4883 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
4884 DAG.getValueType(VT));
4885 Result = DAG.getNode(ISD::SRA, dl, NVT, Tmp1, Node->getOperand(1));
4888 // The input value must be properly zero extended.
4889 Tmp1 = PromoteOp(Node->getOperand(0));
4890 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
4891 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, Node->getOperand(1));
4895 Tmp1 = Node->getOperand(0); // Get the chain.
4896 Tmp2 = Node->getOperand(1); // Get the pointer.
4897 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4898 Tmp3 = DAG.getVAArg(VT, dl, Tmp1, Tmp2, Node->getOperand(2));
4899 Result = TLI.LowerOperation(Tmp3, DAG);
4901 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4902 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
4903 // Increment the pointer, VAList, to the next vaarg
4904 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
4905 DAG.getConstant(VT.getSizeInBits()/8,
4906 TLI.getPointerTy()));
4907 // Store the incremented VAList to the legalized pointer
4908 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
4909 // Load the actual argument out of the pointer VAList
4910 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
4912 // Remember that we legalized the chain.
4913 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4917 LoadSDNode *LD = cast<LoadSDNode>(Node);
4918 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4919 ? ISD::EXTLOAD : LD->getExtensionType();
4920 Result = DAG.getExtLoad(ExtType, dl, NVT,
4921 LD->getChain(), LD->getBasePtr(),
4922 LD->getSrcValue(), LD->getSrcValueOffset(),
4925 LD->getAlignment());
4926 // Remember that we legalized the chain.
4927 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4931 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4932 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4934 MVT VT2 = Tmp2.getValueType();
4935 assert(VT2 == Tmp3.getValueType()
4936 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4937 // Ensure that the resulting node is at least the same size as the operands'
4938 // value types, because we cannot assume that TLI.getSetCCValueType() is
4940 Result = DAG.getNode(ISD::SELECT, dl, VT2, Node->getOperand(0), Tmp2, Tmp3);
4943 case ISD::SELECT_CC:
4944 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4945 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4946 Result = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
4947 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4950 Tmp1 = Node->getOperand(0);
4951 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
4952 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4953 Result = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4954 DAG.getConstant(NVT.getSizeInBits() -
4956 TLI.getShiftAmountTy()));
4961 // Zero extend the argument
4962 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4963 // Perform the larger operation, then subtract if needed.
4964 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4965 switch(Node->getOpcode()) {
4970 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4971 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), Tmp1,
4972 DAG.getConstant(NVT.getSizeInBits(), NVT),
4974 Result = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
4975 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4978 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4979 Result = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4980 DAG.getConstant(NVT.getSizeInBits() -
4981 VT.getSizeInBits(), NVT));
4985 case ISD::EXTRACT_SUBVECTOR:
4986 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4988 case ISD::EXTRACT_VECTOR_ELT:
4989 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4993 assert(Result.getNode() && "Didn't set a result!");
4995 // Make sure the result is itself legal.
4996 Result = LegalizeOp(Result);
4998 // Remember that we promoted this!
4999 AddPromotedOperand(Op, Result);
5003 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
5004 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
5005 /// based on the vector type. The return type of this matches the element type
5006 /// of the vector, which may not be legal for the target.
5007 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
5008 // We know that operand #0 is the Vec vector. If the index is a constant
5009 // or if the invec is a supported hardware type, we can use it. Otherwise,
5010 // lower to a store then an indexed load.
5011 SDValue Vec = Op.getOperand(0);
5012 SDValue Idx = Op.getOperand(1);
5013 DebugLoc dl = Op.getDebugLoc();
5015 MVT TVT = Vec.getValueType();
5016 unsigned NumElems = TVT.getVectorNumElements();
5018 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
5019 default: assert(0 && "This action is not supported yet!");
5020 case TargetLowering::Custom: {
5021 Vec = LegalizeOp(Vec);
5022 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5023 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
5028 case TargetLowering::Legal:
5029 if (isTypeLegal(TVT)) {
5030 Vec = LegalizeOp(Vec);
5031 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5035 case TargetLowering::Promote:
5036 assert(TVT.isVector() && "not vector type");
5037 // fall thru to expand since vectors are by default are promote
5038 case TargetLowering::Expand:
5042 if (NumElems == 1) {
5043 // This must be an access of the only element. Return it.
5044 Op = ScalarizeVectorOp(Vec);
5045 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5046 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5047 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5049 SplitVectorOp(Vec, Lo, Hi);
5050 if (CIdx->getZExtValue() < NumLoElts) {
5054 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5055 Idx.getValueType());
5058 // It's now an extract from the appropriate high or low part. Recurse.
5059 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5060 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5062 // Store the value to a temporary stack slot, then LOAD the scalar
5063 // element back out.
5064 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5065 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
5067 // Add the offset to the index.
5068 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5069 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
5070 DAG.getConstant(EltSize, Idx.getValueType()));
5072 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5073 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
5075 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
5077 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
5079 Op = DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
5084 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5085 /// we assume the operation can be split if it is not already legal.
5086 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5087 // We know that operand #0 is the Vec vector. For now we assume the index
5088 // is a constant and that the extracted result is a supported hardware type.
5089 SDValue Vec = Op.getOperand(0);
5090 SDValue Idx = LegalizeOp(Op.getOperand(1));
5092 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5094 if (NumElems == Op.getValueType().getVectorNumElements()) {
5095 // This must be an access of the desired vector length. Return it.
5099 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5101 SplitVectorOp(Vec, Lo, Hi);
5102 if (CIdx->getZExtValue() < NumElems/2) {
5106 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5107 Idx.getValueType());
5110 // It's now an extract from the appropriate high or low part. Recurse.
5111 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5112 return ExpandEXTRACT_SUBVECTOR(Op);
5115 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5116 /// with condition CC on the current target. This usually involves legalizing
5117 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5118 /// there may be no choice but to create a new SetCC node to represent the
5119 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5120 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5121 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5125 SDValue Tmp1, Tmp2, Tmp3, Result;
5127 switch (getTypeAction(LHS.getValueType())) {
5129 Tmp1 = LegalizeOp(LHS); // LHS
5130 Tmp2 = LegalizeOp(RHS); // RHS
5133 Tmp1 = PromoteOp(LHS); // LHS
5134 Tmp2 = PromoteOp(RHS); // RHS
5136 // If this is an FP compare, the operands have already been extended.
5137 if (LHS.getValueType().isInteger()) {
5138 MVT VT = LHS.getValueType();
5139 MVT NVT = TLI.getTypeToTransformTo(VT);
5141 // Otherwise, we have to insert explicit sign or zero extends. Note
5142 // that we could insert sign extends for ALL conditions, but zero extend
5143 // is cheaper on many machines (an AND instead of two shifts), so prefer
5145 switch (cast<CondCodeSDNode>(CC)->get()) {
5146 default: assert(0 && "Unknown integer comparison!");
5153 // ALL of these operations will work if we either sign or zero extend
5154 // the operands (including the unsigned comparisons!). Zero extend is
5155 // usually a simpler/cheaper operation, so prefer it.
5156 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl, VT);
5157 Tmp2 = DAG.getZeroExtendInReg(Tmp2, dl, VT);
5163 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp1,
5164 DAG.getValueType(VT));
5165 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Tmp2,
5166 DAG.getValueType(VT));
5167 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5168 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5174 MVT VT = LHS.getValueType();
5175 if (VT == MVT::f32 || VT == MVT::f64) {
5176 // Expand into one or more soft-fp libcall(s).
5177 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5178 switch (cast<CondCodeSDNode>(CC)->get()) {
5181 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5185 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5189 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5193 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5197 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5201 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5204 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5207 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5210 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5211 switch (cast<CondCodeSDNode>(CC)->get()) {
5213 // SETONE = SETOLT | SETOGT
5214 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5217 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5220 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5223 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5226 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5229 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5231 default: assert(0 && "Unsupported FP setcc!");
5236 SDValue Ops[2] = { LHS, RHS };
5237 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2, dl).getNode(),
5238 false /*sign irrelevant*/, Dummy);
5239 Tmp2 = DAG.getConstant(0, MVT::i32);
5240 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5241 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5242 Tmp1 = DAG.getNode(ISD::SETCC, dl,
5243 TLI.getSetCCResultType(Tmp1.getValueType()),
5245 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2, dl).getNode(),
5246 false /*sign irrelevant*/, Dummy);
5247 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5248 TLI.getSetCCResultType(LHS.getValueType()), LHS,
5249 Tmp2, DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5250 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5253 LHS = LegalizeOp(Tmp1);
5258 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5259 ExpandOp(LHS, LHSLo, LHSHi);
5260 ExpandOp(RHS, RHSLo, RHSHi);
5261 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5263 if (VT==MVT::ppcf128) {
5264 // FIXME: This generated code sucks. We want to generate
5265 // FCMPU crN, hi1, hi2
5267 // FCMPU crN, lo1, lo2
5268 // The following can be improved, but not that much.
5269 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5270 LHSHi, RHSHi, ISD::SETOEQ);
5271 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5272 LHSLo, RHSLo, CCCode);
5273 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5274 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5275 LHSHi, RHSHi, ISD::SETUNE);
5276 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5277 LHSHi, RHSHi, CCCode);
5278 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5279 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
5288 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5289 if (RHSCST->isAllOnesValue()) {
5290 // Comparison to -1.
5291 Tmp1 = DAG.getNode(ISD::AND, dl,LHSLo.getValueType(), LHSLo, LHSHi);
5296 Tmp1 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSLo, RHSLo);
5297 Tmp2 = DAG.getNode(ISD::XOR, dl, LHSLo.getValueType(), LHSHi, RHSHi);
5298 Tmp1 = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp2);
5299 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5302 // If this is a comparison of the sign bit, just look at the top part.
5304 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5305 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5306 CST->isNullValue()) || // X < 0
5307 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5308 CST->isAllOnesValue())) { // X > -1
5314 // FIXME: This generated code sucks.
5315 ISD::CondCode LowCC;
5317 default: assert(0 && "Unknown integer setcc!");
5319 case ISD::SETULT: LowCC = ISD::SETULT; break;
5321 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5323 case ISD::SETULE: LowCC = ISD::SETULE; break;
5325 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5328 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5329 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5330 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5332 // NOTE: on targets without efficient SELECT of bools, we can always use
5333 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5334 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5335 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo.getValueType()),
5336 LHSLo, RHSLo, LowCC, false, DagCombineInfo, dl);
5337 if (!Tmp1.getNode())
5338 Tmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(LHSLo.getValueType()),
5339 LHSLo, RHSLo, LowCC);
5340 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5341 LHSHi, RHSHi, CCCode, false, DagCombineInfo, dl);
5342 if (!Tmp2.getNode())
5343 Tmp2 = DAG.getNode(ISD::SETCC, dl,
5344 TLI.getSetCCResultType(LHSHi.getValueType()),
5347 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5348 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5349 if ((Tmp1C && Tmp1C->isNullValue()) ||
5350 (Tmp2C && Tmp2C->isNullValue() &&
5351 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5352 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5353 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5354 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5355 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5356 // low part is known false, returns high part.
5357 // For LE / GE, if high part is known false, ignore the low part.
5358 // For LT / GT, if high part is known true, ignore the low part.
5362 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi.getValueType()),
5363 LHSHi, RHSHi, ISD::SETEQ, false,
5364 DagCombineInfo, dl);
5365 if (!Result.getNode())
5366 Result=DAG.getSetCC(dl, TLI.getSetCCResultType(LHSHi.getValueType()),
5367 LHSHi, RHSHi, ISD::SETEQ);
5368 Result = LegalizeOp(DAG.getNode(ISD::SELECT, dl, Tmp1.getValueType(),
5369 Result, Tmp1, Tmp2));
5380 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5381 /// condition code CC on the current target. This routine assumes LHS and rHS
5382 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5383 /// illegal condition code into AND / OR of multiple SETCC values.
5384 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5385 SDValue &LHS, SDValue &RHS,
5388 MVT OpVT = LHS.getValueType();
5389 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5390 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5391 default: assert(0 && "Unknown condition code action!");
5392 case TargetLowering::Legal:
5395 case TargetLowering::Expand: {
5396 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5399 default: assert(0 && "Don't know how to expand this condition!"); abort();
5400 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5401 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5402 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5403 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5404 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5405 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5406 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5407 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5408 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5409 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5410 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5411 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5412 // FIXME: Implement more expansions.
5415 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
5416 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
5417 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
5425 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5426 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5427 /// a load from the stack slot to DestVT, extending it if needed.
5428 /// The resultant code need not be legal.
5429 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5433 // Create the stack frame object.
5434 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5435 SrcOp.getValueType().getTypeForMVT());
5436 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5438 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5439 int SPFI = StackPtrFI->getIndex();
5440 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
5442 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5443 unsigned SlotSize = SlotVT.getSizeInBits();
5444 unsigned DestSize = DestVT.getSizeInBits();
5445 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5446 DestVT.getTypeForMVT());
5448 // Emit a store to the stack slot. Use a truncstore if the input value is
5449 // later than DestVT.
5452 if (SrcSize > SlotSize)
5453 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5454 SV, 0, SlotVT, false, SrcAlign);
5456 assert(SrcSize == SlotSize && "Invalid store");
5457 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
5458 SV, 0, false, SrcAlign);
5461 // Result is a load from the stack slot.
5462 if (SlotSize == DestSize)
5463 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
5465 assert(SlotSize < DestSize && "Unknown extension!");
5466 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
5470 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5471 DebugLoc dl = Node->getDebugLoc();
5472 // Create a vector sized/aligned stack slot, store the value to element #0,
5473 // then load the whole vector back out.
5474 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5476 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5477 int SPFI = StackPtrFI->getIndex();
5479 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(0),
5481 PseudoSourceValue::getFixedStack(SPFI), 0);
5482 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
5483 PseudoSourceValue::getFixedStack(SPFI), 0);
5487 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5488 /// support the operation, but do support the resultant vector type.
5489 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5491 // If the only non-undef value is the low element, turn this into a
5492 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5493 unsigned NumElems = Node->getNumOperands();
5494 bool isOnlyLowElement = true;
5495 SDValue SplatValue = Node->getOperand(0);
5496 DebugLoc dl = Node->getDebugLoc();
5498 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5499 // and use a bitmask instead of a list of elements.
5500 std::map<SDValue, std::vector<unsigned> > Values;
5501 Values[SplatValue].push_back(0);
5502 bool isConstant = true;
5503 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5504 SplatValue.getOpcode() != ISD::UNDEF)
5507 for (unsigned i = 1; i < NumElems; ++i) {
5508 SDValue V = Node->getOperand(i);
5509 Values[V].push_back(i);
5510 if (V.getOpcode() != ISD::UNDEF)
5511 isOnlyLowElement = false;
5512 if (SplatValue != V)
5513 SplatValue = SDValue(0,0);
5515 // If this isn't a constant element or an undef, we can't use a constant
5517 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5518 V.getOpcode() != ISD::UNDEF)
5522 if (isOnlyLowElement) {
5523 // If the low element is an undef too, then this whole things is an undef.
5524 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5525 return DAG.getUNDEF(Node->getValueType(0));
5526 // Otherwise, turn this into a scalar_to_vector node.
5527 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Node->getValueType(0),
5528 Node->getOperand(0));
5531 // If all elements are constants, create a load from the constant pool.
5533 MVT VT = Node->getValueType(0);
5534 std::vector<Constant*> CV;
5535 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5536 if (ConstantFPSDNode *V =
5537 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5538 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5539 } else if (ConstantSDNode *V =
5540 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5541 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5543 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5545 Node->getOperand(0).getValueType().getTypeForMVT();
5546 CV.push_back(UndefValue::get(OpNTy));
5549 Constant *CP = ConstantVector::get(CV);
5550 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5551 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5552 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
5553 PseudoSourceValue::getConstantPool(), 0,
5557 if (SplatValue.getNode()) { // Splat of one value?
5558 // Build the shuffle constant vector: <0, 0, 0, 0>
5559 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5560 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5561 std::vector<SDValue> ZeroVec(NumElems, Zero);
5562 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5563 &ZeroVec[0], ZeroVec.size());
5565 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5566 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5567 // Get the splatted value into the low element of a vector register.
5569 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
5570 Node->getValueType(0), SplatValue);
5572 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5573 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,
5574 Node->getValueType(0), LowValVec,
5575 DAG.getUNDEF(Node->getValueType(0)),
5580 // If there are only two unique elements, we may be able to turn this into a
5582 if (Values.size() == 2) {
5583 // Get the two values in deterministic order.
5584 SDValue Val1 = Node->getOperand(1);
5586 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5587 if (MI->first != Val1)
5590 Val2 = (++MI)->first;
5592 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5593 // vector shuffle has the undef vector on the RHS.
5594 if (Val1.getOpcode() == ISD::UNDEF)
5595 std::swap(Val1, Val2);
5597 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5598 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5599 MVT MaskEltVT = MaskVT.getVectorElementType();
5600 std::vector<SDValue> MaskVec(NumElems);
5602 // Set elements of the shuffle mask for Val1.
5603 std::vector<unsigned> &Val1Elts = Values[Val1];
5604 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5605 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5607 // Set elements of the shuffle mask for Val2.
5608 std::vector<unsigned> &Val2Elts = Values[Val2];
5609 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5610 if (Val2.getOpcode() != ISD::UNDEF)
5611 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5613 MaskVec[Val2Elts[i]] = DAG.getUNDEF(MaskEltVT);
5615 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
5616 &MaskVec[0], MaskVec.size());
5618 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5619 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR,
5620 Node->getValueType(0)) &&
5621 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5622 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val1);
5623 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,Node->getValueType(0), Val2);
5624 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5626 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5627 return DAG.getNode(ISD::VECTOR_SHUFFLE, dl,Node->getValueType(0), Ops, 3);
5631 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5632 // aligned object on the stack, store each element into it, then load
5633 // the result as a vector.
5634 MVT VT = Node->getValueType(0);
5635 // Create the stack frame object.
5636 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5637 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
5638 const Value *SV = PseudoSourceValue::getFixedStack(FI);
5640 // Emit a store of each element to the stack slot.
5641 SmallVector<SDValue, 8> Stores;
5642 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5643 // Store (in the right endianness) the elements to memory.
5644 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5645 // Ignore undef elements.
5646 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5648 unsigned Offset = TypeByteSize*i;
5650 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5651 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
5653 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
5658 if (!Stores.empty()) // Not all undef elements?
5659 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5660 &Stores[0], Stores.size());
5662 StoreChain = DAG.getEntryNode();
5664 // Result is a load from the stack slot.
5665 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
5668 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5669 SDValue Op, SDValue Amt,
5670 SDValue &Lo, SDValue &Hi,
5672 // Expand the subcomponents.
5674 ExpandOp(Op, LHSL, LHSH);
5676 SDValue Ops[] = { LHSL, LHSH, Amt };
5677 MVT VT = LHSL.getValueType();
5678 Lo = DAG.getNode(NodeOp, dl, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5679 Hi = Lo.getValue(1);
5683 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5684 /// smaller elements. If we can't find a way that is more efficient than a
5685 /// libcall on this target, return false. Otherwise, return true with the
5686 /// low-parts expanded into Lo and Hi.
5687 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5688 SDValue &Lo, SDValue &Hi,
5690 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5691 "This is not a shift!");
5693 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5694 SDValue ShAmt = LegalizeOp(Amt);
5695 MVT ShTy = ShAmt.getValueType();
5696 unsigned ShBits = ShTy.getSizeInBits();
5697 unsigned VTBits = Op.getValueType().getSizeInBits();
5698 unsigned NVTBits = NVT.getSizeInBits();
5700 // Handle the case when Amt is an immediate.
5701 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5702 unsigned Cst = CN->getZExtValue();
5703 // Expand the incoming operand to be shifted, so that we have its parts
5705 ExpandOp(Op, InL, InH);
5709 Lo = DAG.getConstant(0, NVT);
5710 Hi = DAG.getConstant(0, NVT);
5711 } else if (Cst > NVTBits) {
5712 Lo = DAG.getConstant(0, NVT);
5713 Hi = DAG.getNode(ISD::SHL, dl,
5714 NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5715 } else if (Cst == NVTBits) {
5716 Lo = DAG.getConstant(0, NVT);
5719 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, DAG.getConstant(Cst, ShTy));
5720 Hi = DAG.getNode(ISD::OR, dl, NVT,
5721 DAG.getNode(ISD::SHL, dl, NVT, InH, DAG.getConstant(Cst, ShTy)),
5722 DAG.getNode(ISD::SRL, dl, NVT, InL,
5723 DAG.getConstant(NVTBits-Cst, ShTy)));
5728 Lo = DAG.getConstant(0, NVT);
5729 Hi = DAG.getConstant(0, NVT);
5730 } else if (Cst > NVTBits) {
5731 Lo = DAG.getNode(ISD::SRL, dl, NVT,
5732 InH, DAG.getConstant(Cst-NVTBits,ShTy));
5733 Hi = DAG.getConstant(0, NVT);
5734 } else if (Cst == NVTBits) {
5736 Hi = DAG.getConstant(0, NVT);
5738 Lo = DAG.getNode(ISD::OR, dl, NVT,
5739 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5740 DAG.getNode(ISD::SHL, dl, NVT, InH,
5741 DAG.getConstant(NVTBits-Cst, ShTy)));
5742 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5747 Hi = Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5748 DAG.getConstant(NVTBits-1, ShTy));
5749 } else if (Cst > NVTBits) {
5750 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH,
5751 DAG.getConstant(Cst-NVTBits, ShTy));
5752 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5753 DAG.getConstant(NVTBits-1, ShTy));
5754 } else if (Cst == NVTBits) {
5756 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
5757 DAG.getConstant(NVTBits-1, ShTy));
5759 Lo = DAG.getNode(ISD::OR, dl, NVT,
5760 DAG.getNode(ISD::SRL, dl, NVT, InL, DAG.getConstant(Cst, ShTy)),
5761 DAG.getNode(ISD::SHL, dl,
5762 NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5763 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, DAG.getConstant(Cst, ShTy));
5769 // Okay, the shift amount isn't constant. However, if we can tell that it is
5770 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5771 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5772 APInt KnownZero, KnownOne;
5773 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5775 // If we know that if any of the high bits of the shift amount are one, then
5776 // we can do this as a couple of simple shifts.
5777 if (KnownOne.intersects(Mask)) {
5778 // Mask out the high bit, which we know is set.
5779 Amt = DAG.getNode(ISD::AND, dl, Amt.getValueType(), Amt,
5780 DAG.getConstant(~Mask, Amt.getValueType()));
5782 // Expand the incoming operand to be shifted, so that we have its parts
5784 ExpandOp(Op, InL, InH);
5787 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5788 Hi = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part.
5791 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5792 Lo = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt); // Lo part from Hi part.
5795 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
5796 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5797 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
5802 // If we know that the high bits of the shift amount are all zero, then we can
5803 // do this as a couple of simple shifts.
5804 if ((KnownZero & Mask) == Mask) {
5806 SDValue Amt2 = DAG.getNode(ISD::SUB, dl, Amt.getValueType(),
5807 DAG.getConstant(NVTBits, Amt.getValueType()),
5810 // Expand the incoming operand to be shifted, so that we have its parts
5812 ExpandOp(Op, InL, InH);
5815 Lo = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt);
5816 Hi = DAG.getNode(ISD::OR, dl, NVT,
5817 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt),
5818 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt2));
5821 Hi = DAG.getNode(ISD::SRL, dl, NVT, InH, Amt);
5822 Lo = DAG.getNode(ISD::OR, dl, NVT,
5823 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5824 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5827 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
5828 Lo = DAG.getNode(ISD::OR, dl, NVT,
5829 DAG.getNode(ISD::SRL, dl, NVT, InL, Amt),
5830 DAG.getNode(ISD::SHL, dl, NVT, InH, Amt2));
5839 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5840 // does not fit into a register, return the lo part and set the hi part to the
5841 // by-reg argument. If it does fit into a single register, return the result
5842 // and leave the Hi part unset.
5843 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5844 bool isSigned, SDValue &Hi) {
5845 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5846 // The input chain to this libcall is the entry node of the function.
5847 // Legalizing the call will automatically add the previous call to the
5849 SDValue InChain = DAG.getEntryNode();
5851 TargetLowering::ArgListTy Args;
5852 TargetLowering::ArgListEntry Entry;
5853 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5854 MVT ArgVT = Node->getOperand(i).getValueType();
5855 const Type *ArgTy = ArgVT.getTypeForMVT();
5856 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5857 Entry.isSExt = isSigned;
5858 Entry.isZExt = !isSigned;
5859 Args.push_back(Entry);
5861 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5862 TLI.getPointerTy());
5864 // Splice the libcall in wherever FindInputOutputChains tells us to.
5865 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5866 std::pair<SDValue,SDValue> CallInfo =
5867 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5868 CallingConv::C, false, Callee, Args, DAG,
5869 Node->getDebugLoc());
5871 // Legalize the call sequence, starting with the chain. This will advance
5872 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5873 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5874 LegalizeOp(CallInfo.second);
5876 switch (getTypeAction(CallInfo.first.getValueType())) {
5877 default: assert(0 && "Unknown thing");
5879 Result = CallInfo.first;
5882 ExpandOp(CallInfo.first, Result, Hi);
5888 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5890 SDValue SelectionDAGLegalize::
5891 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op,
5893 bool isCustom = false;
5895 switch (getTypeAction(Op.getValueType())) {
5897 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5898 Op.getValueType())) {
5899 default: assert(0 && "Unknown operation action!");
5900 case TargetLowering::Custom:
5903 case TargetLowering::Legal:
5904 Tmp1 = LegalizeOp(Op);
5905 if (Result.getNode())
5906 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5908 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5911 Tmp1 = TLI.LowerOperation(Result, DAG);
5912 if (Tmp1.getNode()) Result = Tmp1;
5915 case TargetLowering::Expand:
5916 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy, dl);
5918 case TargetLowering::Promote:
5919 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned, dl);
5924 Result = ExpandIntToFP(isSigned, DestTy, Op, dl) ;
5927 Tmp1 = PromoteOp(Op);
5929 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp1.getValueType(),
5930 Tmp1, DAG.getValueType(Op.getValueType()));
5932 Tmp1 = DAG.getZeroExtendInReg(Tmp1, dl,
5935 if (Result.getNode())
5936 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5938 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, dl,
5940 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5946 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5948 SDValue SelectionDAGLegalize::
5949 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source, DebugLoc dl) {
5950 MVT SourceVT = Source.getValueType();
5951 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5953 // Expand unsupported int-to-fp vector casts by unrolling them.
5954 if (DestTy.isVector()) {
5956 return LegalizeOp(UnrollVectorOp(Source));
5957 MVT DestEltTy = DestTy.getVectorElementType();
5958 if (DestTy.getVectorNumElements() == 1) {
5959 SDValue Scalar = ScalarizeVectorOp(Source);
5960 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5961 DestEltTy, Scalar, dl);
5962 return DAG.getNode(ISD::BUILD_VECTOR, dl, DestTy, Result);
5965 SplitVectorOp(Source, Lo, Hi);
5966 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5967 DestTy.getVectorNumElements() / 2);
5968 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5970 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy,
5972 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, DestTy, LoResult,
5976 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5977 if (!isSigned && SourceVT != MVT::i32) {
5978 // The integer value loaded will be incorrectly if the 'sign bit' of the
5979 // incoming integer is set. To handle this, we dynamically test to see if
5980 // it is set, and, if so, add a fudge factor.
5984 ExpandOp(Source, Lo, Hi);
5985 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, Lo, Hi);
5987 // The comparison for the sign bit will use the entire operand.
5991 // Check to see if the target has a custom way to lower this. If so, use
5992 // it. (Note we've already expanded the operand in this case.)
5993 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5994 default: assert(0 && "This action not implemented for this operation!");
5995 case TargetLowering::Legal:
5996 case TargetLowering::Expand:
5997 break; // This case is handled below.
5998 case TargetLowering::Custom: {
5999 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, dl, DestTy,
6002 return LegalizeOp(NV);
6003 break; // The target decided this was legal after all
6007 // If this is unsigned, and not supported, first perform the conversion to
6008 // signed, then adjust the result if the sign bit is set.
6009 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source, dl);
6011 SDValue SignSet = DAG.getSetCC(dl,
6012 TLI.getSetCCResultType(Hi.getValueType()),
6013 Hi, DAG.getConstant(0, Hi.getValueType()),
6015 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6016 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6017 SignSet, Four, Zero);
6018 uint64_t FF = 0x5f800000ULL;
6019 if (TLI.isLittleEndian()) FF <<= 32;
6020 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6022 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6023 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6024 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6025 Alignment = std::min(Alignment, 4u);
6027 if (DestTy == MVT::f32)
6028 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6029 PseudoSourceValue::getConstantPool(), 0,
6031 else if (DestTy.bitsGT(MVT::f32))
6032 // FIXME: Avoid the extend by construction the right constantpool?
6033 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, dl, DestTy, DAG.getEntryNode(),
6035 PseudoSourceValue::getConstantPool(), 0,
6036 MVT::f32, false, Alignment);
6038 assert(0 && "Unexpected conversion");
6040 MVT SCVT = SignedConv.getValueType();
6041 if (SCVT != DestTy) {
6042 // Destination type needs to be expanded as well. The FADD now we are
6043 // constructing will be expanded into a libcall.
6044 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6045 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6046 SignedConv = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy,
6047 SignedConv, SignedConv.getValue(1));
6049 SignedConv = DAG.getNode(ISD::BIT_CONVERT, dl, DestTy, SignedConv);
6051 return DAG.getNode(ISD::FADD, dl, DestTy, SignedConv, FudgeInReg);
6054 // Check to see if the target has a custom way to lower this. If so, use it.
6055 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6056 default: assert(0 && "This action not implemented for this operation!");
6057 case TargetLowering::Legal:
6058 case TargetLowering::Expand:
6059 break; // This case is handled below.
6060 case TargetLowering::Custom: {
6061 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, dl, DestTy,
6064 return LegalizeOp(NV);
6065 break; // The target decided this was legal after all
6069 // Expand the source, then glue it back together for the call. We must expand
6070 // the source in case it is shared (this pass of legalize must traverse it).
6072 SDValue SrcLo, SrcHi;
6073 ExpandOp(Source, SrcLo, SrcHi);
6074 Source = DAG.getNode(ISD::BUILD_PAIR, dl, SourceVT, SrcLo, SrcHi);
6077 RTLIB::Libcall LC = isSigned ?
6078 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6079 RTLIB::getUINTTOFP(SourceVT, DestTy);
6080 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6082 Source = DAG.getNode(ISD::SINT_TO_FP, dl, DestTy, Source);
6084 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6085 if (Result.getValueType() != DestTy && HiPart.getNode())
6086 Result = DAG.getNode(ISD::BUILD_PAIR, dl, DestTy, Result, HiPart);
6090 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6091 /// INT_TO_FP operation of the specified operand when the target requests that
6092 /// we expand it. At this point, we know that the result and operand types are
6093 /// legal for the target.
6094 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6098 if (Op0.getValueType() == MVT::i32) {
6099 // simple 32-bit [signed|unsigned] integer to float/double expansion
6101 // Get the stack frame index of a 8 byte buffer.
6102 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6104 // word offset constant for Hi/Lo address computation
6105 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6106 // set up Hi and Lo (into buffer) address based on endian
6107 SDValue Hi = StackSlot;
6108 SDValue Lo = DAG.getNode(ISD::ADD, dl,
6109 TLI.getPointerTy(), StackSlot,WordOff);
6110 if (TLI.isLittleEndian())
6113 // if signed map to unsigned space
6116 // constant used to invert sign bit (signed to unsigned mapping)
6117 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6118 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
6122 // store the lo of the constructed double - based on integer input
6123 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
6124 Op0Mapped, Lo, NULL, 0);
6125 // initial hi portion of constructed double
6126 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6127 // store the hi of the constructed double - biased exponent
6128 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
6129 // load the constructed double
6130 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
6131 // FP constant to bias correct the final result
6132 SDValue Bias = DAG.getConstantFP(isSigned ?
6133 BitsToDouble(0x4330000080000000ULL)
6134 : BitsToDouble(0x4330000000000000ULL),
6136 // subtract the bias
6137 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
6140 // handle final rounding
6141 if (DestVT == MVT::f64) {
6144 } else if (DestVT.bitsLT(MVT::f64)) {
6145 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
6146 DAG.getIntPtrConstant(0));
6147 } else if (DestVT.bitsGT(MVT::f64)) {
6148 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
6152 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6153 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
6155 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
6156 Op0, DAG.getConstant(0, Op0.getValueType()),
6158 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6159 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
6160 SignSet, Four, Zero);
6162 // If the sign bit of the integer is set, the large number will be treated
6163 // as a negative number. To counteract this, the dynamic code adds an
6164 // offset depending on the data type.
6166 switch (Op0.getValueType().getSimpleVT()) {
6167 default: assert(0 && "Unsupported integer type!");
6168 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6169 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6170 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6171 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6173 if (TLI.isLittleEndian()) FF <<= 32;
6174 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6176 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6177 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6178 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
6179 Alignment = std::min(Alignment, 4u);
6181 if (DestVT == MVT::f32)
6182 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
6183 PseudoSourceValue::getConstantPool(), 0,
6187 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
6188 DAG.getEntryNode(), CPIdx,
6189 PseudoSourceValue::getConstantPool(), 0,
6190 MVT::f32, false, Alignment));
6193 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
6196 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6197 /// *INT_TO_FP operation of the specified operand when the target requests that
6198 /// we promote it. At this point, we know that the result and operand types are
6199 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6200 /// operation that takes a larger input.
6201 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6205 // First step, figure out the appropriate *INT_TO_FP operation to use.
6206 MVT NewInTy = LegalOp.getValueType();
6208 unsigned OpToUse = 0;
6210 // Scan for the appropriate larger type to use.
6212 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6213 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6215 // If the target supports SINT_TO_FP of this type, use it.
6216 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6218 case TargetLowering::Legal:
6219 if (!TLI.isTypeLegal(NewInTy))
6220 break; // Can't use this datatype.
6222 case TargetLowering::Custom:
6223 OpToUse = ISD::SINT_TO_FP;
6227 if (isSigned) continue;
6229 // If the target supports UINT_TO_FP of this type, use it.
6230 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6232 case TargetLowering::Legal:
6233 if (!TLI.isTypeLegal(NewInTy))
6234 break; // Can't use this datatype.
6236 case TargetLowering::Custom:
6237 OpToUse = ISD::UINT_TO_FP;
6242 // Otherwise, try a larger type.
6245 // Okay, we found the operation and type to use. Zero extend our input to the
6246 // desired type then run the operation on it.
6247 return DAG.getNode(OpToUse, dl, DestVT,
6248 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6249 dl, NewInTy, LegalOp));
6252 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6253 /// FP_TO_*INT operation of the specified operand when the target requests that
6254 /// we promote it. At this point, we know that the result and operand types are
6255 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6256 /// operation that returns a larger result.
6257 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6261 // First step, figure out the appropriate FP_TO*INT operation to use.
6262 MVT NewOutTy = DestVT;
6264 unsigned OpToUse = 0;
6266 // Scan for the appropriate larger type to use.
6268 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6269 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6271 // If the target supports FP_TO_SINT returning this type, use it.
6272 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6274 case TargetLowering::Legal:
6275 if (!TLI.isTypeLegal(NewOutTy))
6276 break; // Can't use this datatype.
6278 case TargetLowering::Custom:
6279 OpToUse = ISD::FP_TO_SINT;
6284 // If the target supports FP_TO_UINT of this type, use it.
6285 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6287 case TargetLowering::Legal:
6288 if (!TLI.isTypeLegal(NewOutTy))
6289 break; // Can't use this datatype.
6291 case TargetLowering::Custom:
6292 OpToUse = ISD::FP_TO_UINT;
6297 // Otherwise, try a larger type.
6301 // Okay, we found the operation and type to use.
6302 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
6304 // If the operation produces an invalid type, it must be custom lowered. Use
6305 // the target lowering hooks to expand it. Just keep the low part of the
6306 // expanded operation, we know that we're truncating anyway.
6307 if (getTypeAction(NewOutTy) == Expand) {
6308 SmallVector<SDValue, 2> Results;
6309 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6310 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6311 Operation = Results[0];
6314 // Truncate the result of the extended FP_TO_*INT operation to the desired
6316 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
6319 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6321 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
6322 MVT VT = Op.getValueType();
6323 MVT SHVT = TLI.getShiftAmountTy();
6324 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6325 switch (VT.getSimpleVT()) {
6326 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6328 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6329 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6330 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
6332 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6333 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6334 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6335 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6336 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6337 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6338 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6339 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6340 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6342 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
6343 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
6344 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
6345 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
6346 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
6347 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
6348 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
6349 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
6350 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6351 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6352 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6353 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6354 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6355 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6356 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
6357 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
6358 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
6359 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
6360 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
6361 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
6362 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
6366 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6368 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
6371 default: assert(0 && "Cannot expand this yet!");
6373 static const uint64_t mask[6] = {
6374 0x5555555555555555ULL, 0x3333333333333333ULL,
6375 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6376 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6378 MVT VT = Op.getValueType();
6379 MVT ShVT = TLI.getShiftAmountTy();
6380 unsigned len = VT.getSizeInBits();
6381 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6382 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6383 unsigned EltSize = VT.isVector() ?
6384 VT.getVectorElementType().getSizeInBits() : len;
6385 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
6386 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6387 Op = DAG.getNode(ISD::ADD, dl, VT,
6388 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
6389 DAG.getNode(ISD::AND, dl, VT,
6390 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
6396 // for now, we do this:
6397 // x = x | (x >> 1);
6398 // x = x | (x >> 2);
6400 // x = x | (x >>16);
6401 // x = x | (x >>32); // for 64-bit input
6402 // return popcount(~x);
6404 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6405 MVT VT = Op.getValueType();
6406 MVT ShVT = TLI.getShiftAmountTy();
6407 unsigned len = VT.getSizeInBits();
6408 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6409 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6410 Op = DAG.getNode(ISD::OR, dl, VT, Op,
6411 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
6413 Op = DAG.getNOT(dl, Op, VT);
6414 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
6417 // for now, we use: { return popcount(~x & (x - 1)); }
6418 // unless the target has ctlz but not ctpop, in which case we use:
6419 // { return 32 - nlz(~x & (x-1)); }
6420 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6421 MVT VT = Op.getValueType();
6422 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
6423 DAG.getNOT(dl, Op, VT),
6424 DAG.getNode(ISD::SUB, dl, VT, Op,
6425 DAG.getConstant(1, VT)));
6426 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6427 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
6428 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
6429 return DAG.getNode(ISD::SUB, dl, VT,
6430 DAG.getConstant(VT.getSizeInBits(), VT),
6431 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
6432 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
6437 /// ExpandOp - Expand the specified SDValue into its two component pieces
6438 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6439 /// LegalizedNodes map is filled in for any results that are not expanded, the
6440 /// ExpandedNodes map is filled in for any results that are expanded, and the
6441 /// Lo/Hi values are returned.
6442 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6443 MVT VT = Op.getValueType();
6444 MVT NVT = TLI.getTypeToTransformTo(VT);
6445 SDNode *Node = Op.getNode();
6446 DebugLoc dl = Node->getDebugLoc();
6447 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6448 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6449 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6451 // See if we already expanded it.
6452 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6453 = ExpandedNodes.find(Op);
6454 if (I != ExpandedNodes.end()) {
6455 Lo = I->second.first;
6456 Hi = I->second.second;
6460 switch (Node->getOpcode()) {
6461 case ISD::CopyFromReg:
6462 assert(0 && "CopyFromReg must be legal!");
6463 case ISD::FP_ROUND_INREG:
6464 if (VT == MVT::ppcf128 &&
6465 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6466 TargetLowering::Custom) {
6467 SDValue SrcLo, SrcHi, Src;
6468 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6469 Src = DAG.getNode(ISD::BUILD_PAIR, dl, VT, SrcLo, SrcHi);
6470 SDValue Result = TLI.LowerOperation(
6471 DAG.getNode(ISD::FP_ROUND_INREG, dl, VT, Src, Op.getOperand(1)), DAG);
6472 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6473 Lo = Result.getNode()->getOperand(0);
6474 Hi = Result.getNode()->getOperand(1);
6480 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6482 assert(0 && "Do not know how to expand this operator!");
6484 case ISD::EXTRACT_ELEMENT:
6485 ExpandOp(Node->getOperand(0), Lo, Hi);
6486 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6487 return ExpandOp(Hi, Lo, Hi);
6488 return ExpandOp(Lo, Lo, Hi);
6489 case ISD::EXTRACT_VECTOR_ELT:
6490 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6491 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6492 return ExpandOp(Lo, Lo, Hi);
6494 Lo = DAG.getUNDEF(NVT);
6495 Hi = DAG.getUNDEF(NVT);
6497 case ISD::Constant: {
6498 unsigned NVTBits = NVT.getSizeInBits();
6499 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6500 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6501 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6504 case ISD::ConstantFP: {
6505 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6506 if (CFP->getValueType(0) == MVT::ppcf128) {
6507 APInt api = CFP->getValueAPF().bitcastToAPInt();
6508 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6510 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6514 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6515 if (getTypeAction(Lo.getValueType()) == Expand)
6516 ExpandOp(Lo, Lo, Hi);
6519 case ISD::BUILD_PAIR:
6520 // Return the operands.
6521 Lo = Node->getOperand(0);
6522 Hi = Node->getOperand(1);
6525 case ISD::MERGE_VALUES:
6526 if (Node->getNumValues() == 1) {
6527 ExpandOp(Op.getOperand(0), Lo, Hi);
6530 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6531 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6532 Op.getValue(1).getValueType() == MVT::Other &&
6533 "unhandled MERGE_VALUES");
6534 ExpandOp(Op.getOperand(0), Lo, Hi);
6535 // Remember that we legalized the chain.
6536 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6539 case ISD::SIGN_EXTEND_INREG:
6540 ExpandOp(Node->getOperand(0), Lo, Hi);
6541 // sext_inreg the low part if needed.
6542 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NVT, Lo, Node->getOperand(1));
6544 // The high part gets the sign extension from the lo-part. This handles
6545 // things like sextinreg V:i64 from i8.
6546 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6547 DAG.getConstant(NVT.getSizeInBits()-1,
6548 TLI.getShiftAmountTy()));
6552 ExpandOp(Node->getOperand(0), Lo, Hi);
6553 SDValue TempLo = DAG.getNode(ISD::BSWAP, dl, NVT, Hi);
6554 Hi = DAG.getNode(ISD::BSWAP, dl, NVT, Lo);
6560 ExpandOp(Node->getOperand(0), Lo, Hi);
6561 Lo = DAG.getNode(ISD::ADD, dl, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6562 DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
6563 DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
6564 Hi = DAG.getConstant(0, NVT);
6568 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6569 ExpandOp(Node->getOperand(0), Lo, Hi);
6570 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6571 SDValue HLZ = DAG.getNode(ISD::CTLZ, dl, NVT, Hi);
6572 SDValue TopNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), HLZ,
6574 SDValue LowPart = DAG.getNode(ISD::CTLZ, dl, NVT, Lo);
6575 LowPart = DAG.getNode(ISD::ADD, dl, NVT, LowPart, BitsC);
6577 Lo = DAG.getNode(ISD::SELECT, dl, NVT, TopNotZero, HLZ, LowPart);
6578 Hi = DAG.getConstant(0, NVT);
6583 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6584 ExpandOp(Node->getOperand(0), Lo, Hi);
6585 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6586 SDValue LTZ = DAG.getNode(ISD::CTTZ, dl, NVT, Lo);
6587 SDValue BotNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), LTZ,
6589 SDValue HiPart = DAG.getNode(ISD::CTTZ, dl, NVT, Hi);
6590 HiPart = DAG.getNode(ISD::ADD, dl, NVT, HiPart, BitsC);
6592 Lo = DAG.getNode(ISD::SELECT, dl, NVT, BotNotZero, LTZ, HiPart);
6593 Hi = DAG.getConstant(0, NVT);
6598 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6599 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6600 Lo = DAG.getVAArg(NVT, dl, Ch, Ptr, Node->getOperand(2));
6601 Hi = DAG.getVAArg(NVT, dl, Lo.getValue(1), Ptr, Node->getOperand(2));
6603 // Remember that we legalized the chain.
6604 Hi = LegalizeOp(Hi);
6605 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6606 if (TLI.isBigEndian())
6612 LoadSDNode *LD = cast<LoadSDNode>(Node);
6613 SDValue Ch = LD->getChain(); // Legalize the chain.
6614 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6615 ISD::LoadExtType ExtType = LD->getExtensionType();
6616 const Value *SV = LD->getSrcValue();
6617 int SVOffset = LD->getSrcValueOffset();
6618 unsigned Alignment = LD->getAlignment();
6619 bool isVolatile = LD->isVolatile();
6621 if (ExtType == ISD::NON_EXTLOAD) {
6622 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6623 isVolatile, Alignment);
6624 if (VT == MVT::f32 || VT == MVT::f64) {
6625 // f32->i32 or f64->i64 one to one expansion.
6626 // Remember that we legalized the chain.
6627 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6628 // Recursively expand the new load.
6629 if (getTypeAction(NVT) == Expand)
6630 ExpandOp(Lo, Lo, Hi);
6634 // Increment the pointer to the other half.
6635 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6636 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
6637 DAG.getIntPtrConstant(IncrementSize));
6638 SVOffset += IncrementSize;
6639 Alignment = MinAlign(Alignment, IncrementSize);
6640 Hi = DAG.getLoad(NVT, dl, Ch, Ptr, SV, SVOffset,
6641 isVolatile, Alignment);
6643 // Build a factor node to remember that this load is independent of the
6645 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
6648 // Remember that we legalized the chain.
6649 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6650 if (TLI.isBigEndian())
6653 MVT EVT = LD->getMemoryVT();
6655 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6656 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6657 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6658 SDValue Load = DAG.getLoad(EVT, dl, Ch, Ptr, SV,
6659 SVOffset, isVolatile, Alignment);
6660 // Remember that we legalized the chain.
6661 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6662 ExpandOp(DAG.getNode(ISD::FP_EXTEND, dl, VT, Load), Lo, Hi);
6667 Lo = DAG.getLoad(NVT, dl, Ch, Ptr, SV,
6668 SVOffset, isVolatile, Alignment);
6670 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, SV,
6671 SVOffset, EVT, isVolatile,
6674 // Remember that we legalized the chain.
6675 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6677 if (ExtType == ISD::SEXTLOAD) {
6678 // The high part is obtained by SRA'ing all but one of the bits of the
6680 unsigned LoSize = Lo.getValueType().getSizeInBits();
6681 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6682 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6683 } else if (ExtType == ISD::ZEXTLOAD) {
6684 // The high part is just a zero.
6685 Hi = DAG.getConstant(0, NVT);
6686 } else /* if (ExtType == ISD::EXTLOAD) */ {
6687 // The high part is undefined.
6688 Hi = DAG.getUNDEF(NVT);
6695 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6696 SDValue LL, LH, RL, RH;
6697 ExpandOp(Node->getOperand(0), LL, LH);
6698 ExpandOp(Node->getOperand(1), RL, RH);
6699 Lo = DAG.getNode(Node->getOpcode(), dl, NVT, LL, RL);
6700 Hi = DAG.getNode(Node->getOpcode(), dl, NVT, LH, RH);
6704 SDValue LL, LH, RL, RH;
6705 ExpandOp(Node->getOperand(1), LL, LH);
6706 ExpandOp(Node->getOperand(2), RL, RH);
6707 if (getTypeAction(NVT) == Expand)
6708 NVT = TLI.getTypeToExpandTo(NVT);
6709 Lo = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LL, RL);
6711 Hi = DAG.getNode(ISD::SELECT, dl, NVT, Node->getOperand(0), LH, RH);
6714 case ISD::SELECT_CC: {
6715 SDValue TL, TH, FL, FH;
6716 ExpandOp(Node->getOperand(2), TL, TH);
6717 ExpandOp(Node->getOperand(3), FL, FH);
6718 if (getTypeAction(NVT) == Expand)
6719 NVT = TLI.getTypeToExpandTo(NVT);
6720 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6721 Node->getOperand(1), TL, FL, Node->getOperand(4));
6723 Hi = DAG.getNode(ISD::SELECT_CC, dl, NVT, Node->getOperand(0),
6724 Node->getOperand(1), TH, FH, Node->getOperand(4));
6727 case ISD::ANY_EXTEND:
6728 // The low part is any extension of the input (which degenerates to a copy).
6729 Lo = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0));
6730 // The high part is undefined.
6731 Hi = DAG.getUNDEF(NVT);
6733 case ISD::SIGN_EXTEND: {
6734 // The low part is just a sign extension of the input (which degenerates to
6736 Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, Node->getOperand(0));
6738 // The high part is obtained by SRA'ing all but one of the bits of the lo
6740 unsigned LoSize = Lo.getValueType().getSizeInBits();
6741 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
6742 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6745 case ISD::ZERO_EXTEND:
6746 // The low part is just a zero extension of the input (which degenerates to
6748 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
6750 // The high part is just a zero.
6751 Hi = DAG.getConstant(0, NVT);
6754 case ISD::TRUNCATE: {
6755 // The input value must be larger than this value. Expand *it*.
6757 ExpandOp(Node->getOperand(0), NewLo, Hi);
6759 // The low part is now either the right size, or it is closer. If not the
6760 // right size, make an illegal truncate so we recursively expand it.
6761 if (NewLo.getValueType() != Node->getValueType(0))
6762 NewLo = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), NewLo);
6763 ExpandOp(NewLo, Lo, Hi);
6767 case ISD::BIT_CONVERT: {
6769 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6770 // If the target wants to, allow it to lower this itself.
6771 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6772 case Expand: assert(0 && "cannot expand FP!");
6773 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6774 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6776 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp), DAG);
6779 // f32 / f64 must be expanded to i32 / i64.
6780 if (VT == MVT::f32 || VT == MVT::f64) {
6781 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
6782 if (getTypeAction(NVT) == Expand)
6783 ExpandOp(Lo, Lo, Hi);
6787 // If source operand will be expanded to the same type as VT, i.e.
6788 // i64 <- f64, i32 <- f32, expand the source operand instead.
6789 MVT VT0 = Node->getOperand(0).getValueType();
6790 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6791 ExpandOp(Node->getOperand(0), Lo, Hi);
6795 // Turn this into a load/store pair by default.
6796 if (Tmp.getNode() == 0)
6797 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT, dl);
6799 ExpandOp(Tmp, Lo, Hi);
6803 case ISD::READCYCLECOUNTER: {
6804 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6805 TargetLowering::Custom &&
6806 "Must custom expand ReadCycleCounter");
6807 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6808 assert(Tmp.getNode() && "Node must be custom expanded!");
6809 ExpandOp(Tmp.getValue(0), Lo, Hi);
6810 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6811 LegalizeOp(Tmp.getValue(1)));
6815 case ISD::ATOMIC_CMP_SWAP: {
6816 // This operation does not need a loop.
6817 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6818 assert(Tmp.getNode() && "Node must be custom expanded!");
6819 ExpandOp(Tmp.getValue(0), Lo, Hi);
6820 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6821 LegalizeOp(Tmp.getValue(1)));
6825 case ISD::ATOMIC_LOAD_ADD:
6826 case ISD::ATOMIC_LOAD_SUB:
6827 case ISD::ATOMIC_LOAD_AND:
6828 case ISD::ATOMIC_LOAD_OR:
6829 case ISD::ATOMIC_LOAD_XOR:
6830 case ISD::ATOMIC_LOAD_NAND:
6831 case ISD::ATOMIC_SWAP: {
6832 // These operations require a loop to be generated. We can't do that yet,
6833 // so substitute a target-dependent pseudo and expand that later.
6834 SDValue In2Lo, In2Hi, In2;
6835 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6836 In2 = DAG.getNode(ISD::BUILD_PAIR, dl, VT, In2Lo, In2Hi);
6837 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6839 DAG.getAtomic(Op.getOpcode(), dl, Anode->getMemoryVT(),
6840 Op.getOperand(0), Op.getOperand(1), In2,
6841 Anode->getSrcValue(), Anode->getAlignment());
6842 SDValue Result = TLI.LowerOperation(Replace, DAG);
6843 ExpandOp(Result.getValue(0), Lo, Hi);
6844 // Remember that we legalized the chain.
6845 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6849 // These operators cannot be expanded directly, emit them as calls to
6850 // library functions.
6851 case ISD::FP_TO_SINT: {
6852 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6854 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6855 case Expand: assert(0 && "cannot expand FP!");
6856 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6857 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6860 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op), DAG);
6862 // Now that the custom expander is done, expand the result, which is still
6865 ExpandOp(Op, Lo, Hi);
6870 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6872 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6873 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6877 case ISD::FP_TO_UINT: {
6878 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6880 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6881 case Expand: assert(0 && "cannot expand FP!");
6882 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6883 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6886 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, dl, VT, Op), DAG);
6888 // Now that the custom expander is done, expand the result.
6890 ExpandOp(Op, Lo, Hi);
6895 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6897 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6898 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6903 // If the target wants custom lowering, do so.
6904 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6905 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6906 SDValue Op = DAG.getNode(ISD::SHL, dl, VT, Node->getOperand(0), ShiftAmt);
6907 Op = TLI.LowerOperation(Op, DAG);
6909 // Now that the custom expander is done, expand the result, which is
6911 ExpandOp(Op, Lo, Hi);
6916 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6917 // this X << 1 as X+X.
6918 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6919 if (ShAmt->getAPIntValue() == 1 &&
6920 TLI.isOperationLegalOrCustom(ISD::ADDC, NVT) &&
6921 TLI.isOperationLegalOrCustom(ISD::ADDE, NVT)) {
6922 SDValue LoOps[2], HiOps[3];
6923 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6924 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6925 LoOps[1] = LoOps[0];
6926 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
6928 HiOps[1] = HiOps[0];
6929 HiOps[2] = Lo.getValue(1);
6930 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
6935 // If we can emit an efficient shift operation, do so now.
6936 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6939 // If this target supports SHL_PARTS, use it.
6940 TargetLowering::LegalizeAction Action =
6941 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6942 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6943 Action == TargetLowering::Custom) {
6944 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0),
6945 ShiftAmt, Lo, Hi, dl);
6949 // Otherwise, emit a libcall.
6950 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6955 // If the target wants custom lowering, do so.
6956 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6957 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6958 SDValue Op = DAG.getNode(ISD::SRA, dl, VT, Node->getOperand(0), ShiftAmt);
6959 Op = TLI.LowerOperation(Op, DAG);
6961 // Now that the custom expander is done, expand the result, which is
6963 ExpandOp(Op, Lo, Hi);
6968 // If we can emit an efficient shift operation, do so now.
6969 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
6972 // If this target supports SRA_PARTS, use it.
6973 TargetLowering::LegalizeAction Action =
6974 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6975 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6976 Action == TargetLowering::Custom) {
6977 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0),
6978 ShiftAmt, Lo, Hi, dl);
6982 // Otherwise, emit a libcall.
6983 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6988 // If the target wants custom lowering, do so.
6989 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6990 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6991 SDValue Op = DAG.getNode(ISD::SRL, dl, VT, Node->getOperand(0), ShiftAmt);
6992 Op = TLI.LowerOperation(Op, DAG);
6994 // Now that the custom expander is done, expand the result, which is
6996 ExpandOp(Op, Lo, Hi);
7001 // If we can emit an efficient shift operation, do so now.
7002 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi, dl))
7005 // If this target supports SRL_PARTS, use it.
7006 TargetLowering::LegalizeAction Action =
7007 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
7008 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
7009 Action == TargetLowering::Custom) {
7010 ExpandShiftParts(ISD::SRL_PARTS,
7011 Node->getOperand(0), ShiftAmt, Lo, Hi, dl);
7015 // Otherwise, emit a libcall.
7016 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
7022 // If the target wants to custom expand this, let them.
7023 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
7024 TargetLowering::Custom) {
7025 SDValue Result = TLI.LowerOperation(Op, DAG);
7026 if (Result.getNode()) {
7027 ExpandOp(Result, Lo, Hi);
7031 // Expand the subcomponents.
7032 SDValue LHSL, LHSH, RHSL, RHSH;
7033 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7034 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7035 SDValue LoOps[2], HiOps[3];
7041 //cascaded check to see if any smaller size has a a carry flag.
7042 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
7043 bool hasCarry = false;
7044 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
7045 MVT AVT = MVT::getIntegerVT(BitSize);
7046 if (TLI.isOperationLegalOrCustom(OpV, AVT)) {
7053 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7054 if (Node->getOpcode() == ISD::ADD) {
7055 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7056 HiOps[2] = Lo.getValue(1);
7057 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7059 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7060 HiOps[2] = Lo.getValue(1);
7061 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7065 if (Node->getOpcode() == ISD::ADD) {
7066 Lo = DAG.getNode(ISD::ADD, dl, NVT, LoOps, 2);
7067 Hi = DAG.getNode(ISD::ADD, dl, NVT, HiOps, 2);
7068 SDValue Cmp1 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7069 Lo, LoOps[0], ISD::SETULT);
7070 SDValue Carry1 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp1,
7071 DAG.getConstant(1, NVT),
7072 DAG.getConstant(0, NVT));
7073 SDValue Cmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
7074 Lo, LoOps[1], ISD::SETULT);
7075 SDValue Carry2 = DAG.getNode(ISD::SELECT, dl, NVT, Cmp2,
7076 DAG.getConstant(1, NVT),
7078 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, Carry2);
7080 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2);
7081 Hi = DAG.getNode(ISD::SUB, dl, NVT, HiOps, 2);
7082 SDValue Cmp = DAG.getSetCC(dl, NVT, LoOps[0], LoOps[1], ISD::SETULT);
7083 SDValue Borrow = DAG.getNode(ISD::SELECT, dl, NVT, Cmp,
7084 DAG.getConstant(1, NVT),
7085 DAG.getConstant(0, NVT));
7086 Hi = DAG.getNode(ISD::SUB, dl, NVT, Hi, Borrow);
7094 // Expand the subcomponents.
7095 SDValue LHSL, LHSH, RHSL, RHSH;
7096 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7097 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7098 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7099 SDValue LoOps[2] = { LHSL, RHSL };
7100 SDValue HiOps[3] = { LHSH, RHSH };
7102 if (Node->getOpcode() == ISD::ADDC) {
7103 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
7104 HiOps[2] = Lo.getValue(1);
7105 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3);
7107 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps, 2);
7108 HiOps[2] = Lo.getValue(1);
7109 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3);
7111 // Remember that we legalized the flag.
7112 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7117 // Expand the subcomponents.
7118 SDValue LHSL, LHSH, RHSL, RHSH;
7119 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7120 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7121 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7122 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7123 SDValue HiOps[3] = { LHSH, RHSH };
7125 Lo = DAG.getNode(Node->getOpcode(), dl, VTList, LoOps, 3);
7126 HiOps[2] = Lo.getValue(1);
7127 Hi = DAG.getNode(Node->getOpcode(), dl, VTList, HiOps, 3);
7129 // Remember that we legalized the flag.
7130 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7134 // If the target wants to custom expand this, let them.
7135 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7136 SDValue New = TLI.LowerOperation(Op, DAG);
7137 if (New.getNode()) {
7138 ExpandOp(New, Lo, Hi);
7143 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
7144 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, NVT);
7145 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, NVT);
7146 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, NVT);
7147 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7148 SDValue LL, LH, RL, RH;
7149 ExpandOp(Node->getOperand(0), LL, LH);
7150 ExpandOp(Node->getOperand(1), RL, RH);
7151 unsigned OuterBitSize = Op.getValueSizeInBits();
7152 unsigned InnerBitSize = RH.getValueSizeInBits();
7153 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7154 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7155 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7156 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7157 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7158 // The inputs are both zero-extended.
7160 // We can emit a umul_lohi.
7161 Lo = DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7162 Hi = SDValue(Lo.getNode(), 1);
7166 // We can emit a mulhu+mul.
7167 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7168 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7172 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7173 // The input values are both sign-extended.
7175 // We can emit a smul_lohi.
7176 Lo = DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(NVT, NVT), LL, RL);
7177 Hi = SDValue(Lo.getNode(), 1);
7181 // We can emit a mulhs+mul.
7182 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7183 Hi = DAG.getNode(ISD::MULHS, dl, NVT, LL, RL);
7188 // Lo,Hi = umul LHS, RHS.
7189 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI, dl,
7190 DAG.getVTList(NVT, NVT), LL, RL);
7192 Hi = UMulLOHI.getValue(1);
7193 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7194 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7195 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7196 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7200 Lo = DAG.getNode(ISD::MUL, dl, NVT, LL, RL);
7201 Hi = DAG.getNode(ISD::MULHU, dl, NVT, LL, RL);
7202 RH = DAG.getNode(ISD::MUL, dl, NVT, LL, RH);
7203 LH = DAG.getNode(ISD::MUL, dl, NVT, LH, RL);
7204 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, RH);
7205 Hi = DAG.getNode(ISD::ADD, dl, NVT, Hi, LH);
7210 // If nothing else, we can make a libcall.
7211 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7215 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7218 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7221 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7224 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7228 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7231 RTLIB::ADD_PPCF128),
7235 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7238 RTLIB::SUB_PPCF128),
7242 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7245 RTLIB::MUL_PPCF128),
7249 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7252 RTLIB::DIV_PPCF128),
7255 case ISD::FP_EXTEND: {
7256 if (VT == MVT::ppcf128) {
7257 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7258 Node->getOperand(0).getValueType()==MVT::f64);
7259 const uint64_t zero = 0;
7260 if (Node->getOperand(0).getValueType()==MVT::f32)
7261 Hi = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Node->getOperand(0));
7263 Hi = Node->getOperand(0);
7264 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7267 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7268 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7269 Lo = ExpandLibCall(LC, Node, true, Hi);
7272 case ISD::FP_ROUND: {
7273 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7275 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7276 Lo = ExpandLibCall(LC, Node, true, Hi);
7291 case ISD::FNEARBYINT:
7294 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7295 switch(Node->getOpcode()) {
7297 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7298 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7301 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7302 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7305 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7306 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7309 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7310 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7313 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7314 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7317 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7318 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7321 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7322 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7325 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7326 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7329 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7330 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7333 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7334 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7337 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7338 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7341 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7342 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7344 case ISD::FNEARBYINT:
7345 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7346 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7349 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7350 RTLIB::POW_PPCF128);
7353 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7354 RTLIB::POWI_PPCF128);
7356 default: assert(0 && "Unreachable!");
7358 Lo = ExpandLibCall(LC, Node, false, Hi);
7362 if (VT == MVT::ppcf128) {
7364 ExpandOp(Node->getOperand(0), Lo, Tmp);
7365 Hi = DAG.getNode(ISD::FABS, dl, NVT, Tmp);
7366 // lo = hi==fabs(hi) ? lo : -lo;
7367 Lo = DAG.getNode(ISD::SELECT_CC, dl, NVT, Hi, Tmp,
7368 Lo, DAG.getNode(ISD::FNEG, dl, NVT, Lo),
7369 DAG.getCondCode(ISD::SETEQ));
7372 SDValue Mask = (VT == MVT::f64)
7373 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7374 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7375 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7376 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7377 Lo = DAG.getNode(ISD::AND, dl, NVT, Lo, Mask);
7378 if (getTypeAction(NVT) == Expand)
7379 ExpandOp(Lo, Lo, Hi);
7383 if (VT == MVT::ppcf128) {
7384 ExpandOp(Node->getOperand(0), Lo, Hi);
7385 Lo = DAG.getNode(ISD::FNEG, dl, MVT::f64, Lo);
7386 Hi = DAG.getNode(ISD::FNEG, dl, MVT::f64, Hi);
7389 SDValue Mask = (VT == MVT::f64)
7390 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7391 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7392 Mask = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Mask);
7393 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
7394 Lo = DAG.getNode(ISD::XOR, dl, NVT, Lo, Mask);
7395 if (getTypeAction(NVT) == Expand)
7396 ExpandOp(Lo, Lo, Hi);
7399 case ISD::FCOPYSIGN: {
7400 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7401 if (getTypeAction(NVT) == Expand)
7402 ExpandOp(Lo, Lo, Hi);
7405 case ISD::SINT_TO_FP:
7406 case ISD::UINT_TO_FP: {
7407 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7408 MVT SrcVT = Node->getOperand(0).getValueType();
7410 // Promote the operand if needed. Do this before checking for
7411 // ppcf128 so conversions of i16 and i8 work.
7412 if (getTypeAction(SrcVT) == Promote) {
7413 SDValue Tmp = PromoteOp(Node->getOperand(0));
7415 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Tmp.getValueType(), Tmp,
7416 DAG.getValueType(SrcVT))
7417 : DAG.getZeroExtendInReg(Tmp, dl, SrcVT);
7418 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7419 SrcVT = Node->getOperand(0).getValueType();
7422 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7423 static const uint64_t zero = 0;
7425 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7426 Node->getOperand(0)));
7427 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7429 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7430 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f64,
7431 Node->getOperand(0)));
7432 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7433 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7434 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7435 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl,
7436 MVT::ppcf128, Node->getOperand(0),
7437 DAG.getConstant(0, MVT::i32),
7438 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7440 APFloat(APInt(128, 2, TwoE32)),
7443 DAG.getCondCode(ISD::SETLT)),
7448 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7449 // si64->ppcf128 done by libcall, below
7450 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7451 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, dl, MVT::ppcf128,
7452 Node->getOperand(0)), Lo, Hi);
7453 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi);
7454 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7455 ExpandOp(DAG.getNode(ISD::SELECT_CC, dl, MVT::ppcf128,
7456 Node->getOperand(0),
7457 DAG.getConstant(0, MVT::i64),
7458 DAG.getNode(ISD::FADD, dl, MVT::ppcf128, Hi,
7460 APFloat(APInt(128, 2, TwoE64)),
7463 DAG.getCondCode(ISD::SETLT)),
7468 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7469 Node->getOperand(0), dl);
7470 if (getTypeAction(Lo.getValueType()) == Expand)
7471 // float to i32 etc. can be 'expanded' to a single node.
7472 ExpandOp(Lo, Lo, Hi);
7477 // Make sure the resultant values have been legalized themselves, unless this
7478 // is a type that requires multi-step expansion.
7479 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7480 Lo = LegalizeOp(Lo);
7482 // Don't legalize the high part if it is expanded to a single node.
7483 Hi = LegalizeOp(Hi);
7486 // Remember in a map if the values will be reused later.
7488 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7489 assert(isNew && "Value already expanded?!?");
7493 /// SplitVectorOp - Given an operand of vector type, break it down into
7494 /// two smaller values, still of vector type.
7495 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7497 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7498 SDNode *Node = Op.getNode();
7499 DebugLoc dl = Node->getDebugLoc();
7500 unsigned NumElements = Op.getValueType().getVectorNumElements();
7501 assert(NumElements > 1 && "Cannot split a single element vector!");
7503 MVT NewEltVT = Op.getValueType().getVectorElementType();
7505 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7506 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7508 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7509 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7511 // See if we already split it.
7512 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7513 = SplitNodes.find(Op);
7514 if (I != SplitNodes.end()) {
7515 Lo = I->second.first;
7516 Hi = I->second.second;
7520 switch (Node->getOpcode()) {
7525 assert(0 && "Unhandled operation in SplitVectorOp!");
7527 Lo = DAG.getUNDEF(NewVT_Lo);
7528 Hi = DAG.getUNDEF(NewVT_Hi);
7530 case ISD::BUILD_PAIR:
7531 Lo = Node->getOperand(0);
7532 Hi = Node->getOperand(1);
7534 case ISD::INSERT_VECTOR_ELT: {
7535 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7536 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7537 unsigned Index = Idx->getZExtValue();
7538 SDValue ScalarOp = Node->getOperand(1);
7539 if (Index < NewNumElts_Lo)
7540 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Lo, Lo, ScalarOp,
7541 DAG.getIntPtrConstant(Index));
7543 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, NewVT_Hi, Hi, ScalarOp,
7544 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7547 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7548 Node->getOperand(1),
7549 Node->getOperand(2), dl);
7550 SplitVectorOp(Tmp, Lo, Hi);
7553 case ISD::VECTOR_SHUFFLE: {
7554 // Build the low part.
7555 SDValue Mask = Node->getOperand(2);
7556 SmallVector<SDValue, 8> Ops;
7557 MVT PtrVT = TLI.getPointerTy();
7559 // Insert all of the elements from the input that are needed. We use
7560 // buildvector of extractelement here because the input vectors will have
7561 // to be legalized, so this makes the code simpler.
7562 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7563 SDValue IdxNode = Mask.getOperand(i);
7564 if (IdxNode.getOpcode() == ISD::UNDEF) {
7565 Ops.push_back(DAG.getUNDEF(NewEltVT));
7568 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7569 SDValue InVec = Node->getOperand(0);
7570 if (Idx >= NumElements) {
7571 InVec = Node->getOperand(1);
7574 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7575 DAG.getConstant(Idx, PtrVT)));
7577 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &Ops[0], Ops.size());
7580 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7581 SDValue IdxNode = Mask.getOperand(i);
7582 if (IdxNode.getOpcode() == ISD::UNDEF) {
7583 Ops.push_back(DAG.getUNDEF(NewEltVT));
7586 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7587 SDValue InVec = Node->getOperand(0);
7588 if (Idx >= NumElements) {
7589 InVec = Node->getOperand(1);
7592 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewEltVT, InVec,
7593 DAG.getConstant(Idx, PtrVT)));
7595 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &Ops[0], Ops.size());
7598 case ISD::BUILD_VECTOR: {
7599 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7600 Node->op_begin()+NewNumElts_Lo);
7601 Lo = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Lo, &LoOps[0], LoOps.size());
7603 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7605 Hi = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT_Hi, &HiOps[0], HiOps.size());
7608 case ISD::CONCAT_VECTORS: {
7609 // FIXME: Handle non-power-of-two vectors?
7610 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7611 if (NewNumSubvectors == 1) {
7612 Lo = Node->getOperand(0);
7613 Hi = Node->getOperand(1);
7615 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7616 Node->op_begin()+NewNumSubvectors);
7617 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Lo,
7618 &LoOps[0], LoOps.size());
7620 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7622 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewVT_Hi,
7623 &HiOps[0], HiOps.size());
7627 case ISD::EXTRACT_SUBVECTOR: {
7628 SDValue Vec = Op.getOperand(0);
7629 SDValue Idx = Op.getOperand(1);
7630 MVT IdxVT = Idx.getValueType();
7632 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Lo, Vec, Idx);
7633 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7635 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec,
7636 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7639 Idx = DAG.getNode(ISD::ADD, dl, IdxVT, Idx,
7640 DAG.getConstant(NewNumElts_Lo, IdxVT));
7641 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NewVT_Hi, Vec, Idx);
7646 SDValue Cond = Node->getOperand(0);
7648 SDValue LL, LH, RL, RH;
7649 SplitVectorOp(Node->getOperand(1), LL, LH);
7650 SplitVectorOp(Node->getOperand(2), RL, RH);
7652 if (Cond.getValueType().isVector()) {
7653 // Handle a vector merge.
7655 SplitVectorOp(Cond, CL, CH);
7656 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, CL, LL, RL);
7657 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, CH, LH, RH);
7659 // Handle a simple select with vector operands.
7660 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, Cond, LL, RL);
7661 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, Cond, LH, RH);
7665 case ISD::SELECT_CC: {
7666 SDValue CondLHS = Node->getOperand(0);
7667 SDValue CondRHS = Node->getOperand(1);
7668 SDValue CondCode = Node->getOperand(4);
7670 SDValue LL, LH, RL, RH;
7671 SplitVectorOp(Node->getOperand(2), LL, LH);
7672 SplitVectorOp(Node->getOperand(3), RL, RH);
7674 // Handle a simple select with vector operands.
7675 Lo = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Lo, CondLHS, CondRHS,
7677 Hi = DAG.getNode(ISD::SELECT_CC, dl, NewVT_Hi, CondLHS, CondRHS,
7682 SDValue LL, LH, RL, RH;
7683 SplitVectorOp(Node->getOperand(0), LL, LH);
7684 SplitVectorOp(Node->getOperand(1), RL, RH);
7685 Lo = DAG.getNode(ISD::VSETCC, dl, NewVT_Lo, LL, RL, Node->getOperand(2));
7686 Hi = DAG.getNode(ISD::VSETCC, dl, NewVT_Hi, LH, RH, Node->getOperand(2));
7708 SDValue LL, LH, RL, RH;
7709 SplitVectorOp(Node->getOperand(0), LL, LH);
7710 SplitVectorOp(Node->getOperand(1), RL, RH);
7712 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, LL, RL);
7713 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, LH, RH);
7719 SplitVectorOp(Node->getOperand(0), L, H);
7721 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L, Node->getOperand(1));
7722 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H, Node->getOperand(1));
7738 case ISD::FP_TO_SINT:
7739 case ISD::FP_TO_UINT:
7740 case ISD::SINT_TO_FP:
7741 case ISD::UINT_TO_FP:
7743 case ISD::ANY_EXTEND:
7744 case ISD::SIGN_EXTEND:
7745 case ISD::ZERO_EXTEND:
7746 case ISD::FP_EXTEND: {
7748 SplitVectorOp(Node->getOperand(0), L, H);
7750 Lo = DAG.getNode(Node->getOpcode(), dl, NewVT_Lo, L);
7751 Hi = DAG.getNode(Node->getOpcode(), dl, NewVT_Hi, H);
7754 case ISD::CONVERT_RNDSAT: {
7755 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7757 SplitVectorOp(Node->getOperand(0), L, H);
7758 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7759 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7760 SDValue STyOpL = DAG.getValueType(L.getValueType());
7761 SDValue STyOpH = DAG.getValueType(H.getValueType());
7763 SDValue RndOp = Node->getOperand(3);
7764 SDValue SatOp = Node->getOperand(4);
7766 Lo = DAG.getConvertRndSat(NewVT_Lo, dl, L, DTyOpL, STyOpL,
7767 RndOp, SatOp, CvtCode);
7768 Hi = DAG.getConvertRndSat(NewVT_Hi, dl, H, DTyOpH, STyOpH,
7769 RndOp, SatOp, CvtCode);
7773 LoadSDNode *LD = cast<LoadSDNode>(Node);
7774 SDValue Ch = LD->getChain();
7775 SDValue Ptr = LD->getBasePtr();
7776 ISD::LoadExtType ExtType = LD->getExtensionType();
7777 const Value *SV = LD->getSrcValue();
7778 int SVOffset = LD->getSrcValueOffset();
7779 MVT MemoryVT = LD->getMemoryVT();
7780 unsigned Alignment = LD->getAlignment();
7781 bool isVolatile = LD->isVolatile();
7783 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7784 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7786 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7787 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7788 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7790 Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7791 NewVT_Lo, Ch, Ptr, Offset,
7792 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7793 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7794 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
7795 DAG.getIntPtrConstant(IncrementSize));
7796 SVOffset += IncrementSize;
7797 Alignment = MinAlign(Alignment, IncrementSize);
7798 Hi = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7799 NewVT_Hi, Ch, Ptr, Offset,
7800 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7802 // Build a factor node to remember that this load is independent of the
7804 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
7807 // Remember that we legalized the chain.
7808 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7811 case ISD::BIT_CONVERT: {
7812 // We know the result is a vector. The input may be either a vector or a
7814 SDValue InOp = Node->getOperand(0);
7815 if (!InOp.getValueType().isVector() ||
7816 InOp.getValueType().getVectorNumElements() == 1) {
7817 // The input is a scalar or single-element vector.
7818 // Lower to a store/load so that it can be split.
7819 // FIXME: this could be improved probably.
7820 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7821 Op.getValueType().getTypeForMVT());
7822 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7823 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7825 SDValue St = DAG.getStore(DAG.getEntryNode(), dl,
7827 PseudoSourceValue::getFixedStack(FI), 0);
7828 InOp = DAG.getLoad(Op.getValueType(), dl, St, Ptr,
7829 PseudoSourceValue::getFixedStack(FI), 0);
7831 // Split the vector and convert each of the pieces now.
7832 SplitVectorOp(InOp, Lo, Hi);
7833 Lo = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Lo, Lo);
7834 Hi = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT_Hi, Hi);
7839 // Remember in a map if the values will be reused later.
7841 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7842 assert(isNew && "Value already split?!?");
7847 /// ScalarizeVectorOp - Given an operand of single-element vector type
7848 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7849 /// scalar (e.g. f32) value.
7850 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7851 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7852 SDNode *Node = Op.getNode();
7853 DebugLoc dl = Node->getDebugLoc();
7854 MVT NewVT = Op.getValueType().getVectorElementType();
7855 assert(Op.getValueType().getVectorNumElements() == 1);
7857 // See if we already scalarized it.
7858 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7859 if (I != ScalarizedNodes.end()) return I->second;
7862 switch (Node->getOpcode()) {
7865 Node->dump(&DAG); cerr << "\n";
7867 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7884 Result = DAG.getNode(Node->getOpcode(), dl,
7886 ScalarizeVectorOp(Node->getOperand(0)),
7887 ScalarizeVectorOp(Node->getOperand(1)));
7899 case ISD::FP_TO_SINT:
7900 case ISD::FP_TO_UINT:
7901 case ISD::SINT_TO_FP:
7902 case ISD::UINT_TO_FP:
7903 case ISD::SIGN_EXTEND:
7904 case ISD::ZERO_EXTEND:
7905 case ISD::ANY_EXTEND:
7907 case ISD::FP_EXTEND:
7908 Result = DAG.getNode(Node->getOpcode(), dl,
7910 ScalarizeVectorOp(Node->getOperand(0)));
7912 case ISD::CONVERT_RNDSAT: {
7913 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7914 Result = DAG.getConvertRndSat(NewVT, dl, Op0,
7915 DAG.getValueType(NewVT),
7916 DAG.getValueType(Op0.getValueType()),
7917 Node->getOperand(3),
7918 Node->getOperand(4),
7919 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7924 Result = DAG.getNode(Node->getOpcode(), dl,
7926 ScalarizeVectorOp(Node->getOperand(0)),
7927 Node->getOperand(1));
7930 LoadSDNode *LD = cast<LoadSDNode>(Node);
7931 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7932 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7933 ISD::LoadExtType ExtType = LD->getExtensionType();
7934 const Value *SV = LD->getSrcValue();
7935 int SVOffset = LD->getSrcValueOffset();
7936 MVT MemoryVT = LD->getMemoryVT();
7937 unsigned Alignment = LD->getAlignment();
7938 bool isVolatile = LD->isVolatile();
7940 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7941 SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
7943 Result = DAG.getLoad(ISD::UNINDEXED, dl, ExtType,
7944 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7945 MemoryVT.getVectorElementType(),
7946 isVolatile, Alignment);
7948 // Remember that we legalized the chain.
7949 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7952 case ISD::BUILD_VECTOR:
7953 Result = Node->getOperand(0);
7955 case ISD::INSERT_VECTOR_ELT:
7956 // Returning the inserted scalar element.
7957 Result = Node->getOperand(1);
7959 case ISD::CONCAT_VECTORS:
7960 assert(Node->getOperand(0).getValueType() == NewVT &&
7961 "Concat of non-legal vectors not yet supported!");
7962 Result = Node->getOperand(0);
7964 case ISD::VECTOR_SHUFFLE: {
7965 // Figure out if the scalar is the LHS or RHS and return it.
7966 SDValue EltNum = Node->getOperand(2).getOperand(0);
7967 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7968 Result = ScalarizeVectorOp(Node->getOperand(1));
7970 Result = ScalarizeVectorOp(Node->getOperand(0));
7973 case ISD::EXTRACT_SUBVECTOR:
7974 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT,
7975 Node->getOperand(0), Node->getOperand(1));
7977 case ISD::BIT_CONVERT: {
7978 SDValue Op0 = Op.getOperand(0);
7979 if (Op0.getValueType().getVectorNumElements() == 1)
7980 Op0 = ScalarizeVectorOp(Op0);
7981 Result = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, Op0);
7985 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Op.getOperand(0),
7986 ScalarizeVectorOp(Op.getOperand(1)),
7987 ScalarizeVectorOp(Op.getOperand(2)));
7989 case ISD::SELECT_CC:
7990 Result = DAG.getNode(ISD::SELECT_CC, dl, NewVT, Node->getOperand(0),
7991 Node->getOperand(1),
7992 ScalarizeVectorOp(Op.getOperand(2)),
7993 ScalarizeVectorOp(Op.getOperand(3)),
7994 Node->getOperand(4));
7997 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7998 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7999 Result = DAG.getNode(ISD::SETCC, dl,
8000 TLI.getSetCCResultType(Op0.getValueType()),
8001 Op0, Op1, Op.getOperand(2));
8002 Result = DAG.getNode(ISD::SELECT, dl, NewVT, Result,
8003 DAG.getConstant(-1ULL, NewVT),
8004 DAG.getConstant(0ULL, NewVT));
8009 if (TLI.isTypeLegal(NewVT))
8010 Result = LegalizeOp(Result);
8011 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
8012 assert(isNew && "Value already scalarized?");
8018 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
8019 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
8020 if (I != WidenNodes.end()) return I->second;
8022 MVT VT = Op.getValueType();
8023 assert(VT.isVector() && "Cannot widen non-vector type!");
8026 SDNode *Node = Op.getNode();
8027 DebugLoc dl = Node->getDebugLoc();
8028 MVT EVT = VT.getVectorElementType();
8030 unsigned NumElts = VT.getVectorNumElements();
8031 unsigned NewNumElts = WidenVT.getVectorNumElements();
8032 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
8033 assert(NewNumElts < 17);
8035 // When widen is called, it is assumed that it is more efficient to use a
8036 // wide type. The default action is to widen to operation to a wider legal
8037 // vector type and then do the operation if it is legal by calling LegalizeOp
8038 // again. If there is no vector equivalent, we will unroll the operation, do
8039 // it, and rebuild the vector. If most of the operations are vectorizible to
8040 // the legal type, the resulting code will be more efficient. If this is not
8041 // the case, the resulting code will preform badly as we end up generating
8042 // code to pack/unpack the results. It is the function that calls widen
8043 // that is responsible for seeing this doesn't happen.
8044 switch (Node->getOpcode()) {
8049 assert(0 && "Unexpected operation in WidenVectorOp!");
8051 case ISD::CopyFromReg:
8052 assert(0 && "CopyFromReg doesn't need widening!");
8054 case ISD::ConstantFP:
8055 // To build a vector of these elements, clients should call BuildVector
8056 // and with each element instead of creating a node with a vector type
8057 assert(0 && "Unexpected operation in WidenVectorOp!");
8059 // Variable Arguments with vector types doesn't make any sense to me
8060 assert(0 && "Unexpected operation in WidenVectorOp!");
8063 Result = DAG.getUNDEF(WidenVT);
8065 case ISD::BUILD_VECTOR: {
8066 // Build a vector with undefined for the new nodes
8067 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8068 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8069 NewOps.push_back(DAG.getUNDEF(EVT));
8071 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, WidenVT,
8072 &NewOps[0], NewOps.size());
8075 case ISD::INSERT_VECTOR_ELT: {
8076 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8077 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, WidenVT, Tmp1,
8078 Node->getOperand(1), Node->getOperand(2));
8081 case ISD::VECTOR_SHUFFLE: {
8082 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8083 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8084 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
8085 // used as permutation array. We build the vector here instead of widening
8086 // because we don't want to legalize and have it turned to something else.
8087 SDValue PermOp = Node->getOperand(2);
8088 SDValueVector NewOps;
8089 MVT PVT = PermOp.getValueType().getVectorElementType();
8090 for (unsigned i = 0; i < NumElts; ++i) {
8091 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
8092 NewOps.push_back(PermOp.getOperand(i));
8095 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
8096 if (Idx < NumElts) {
8097 NewOps.push_back(PermOp.getOperand(i));
8100 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
8101 PermOp.getOperand(i).getValueType()));
8105 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8106 NewOps.push_back(DAG.getUNDEF(PVT));
8109 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR, dl,
8110 MVT::getVectorVT(PVT, NewOps.size()),
8111 &NewOps[0], NewOps.size());
8113 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, WidenVT, Tmp1, Tmp2, Tmp3);
8117 // If the load widen returns true, we can use a single load for the
8118 // vector. Otherwise, it is returning a token factor for multiple
8121 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8122 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8124 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8128 case ISD::BIT_CONVERT: {
8129 SDValue Tmp1 = Node->getOperand(0);
8130 // Converts between two different types so we need to determine
8131 // the correct widen type for the input operand.
8132 MVT InVT = Tmp1.getValueType();
8133 unsigned WidenSize = WidenVT.getSizeInBits();
8134 if (InVT.isVector()) {
8135 MVT InEltVT = InVT.getVectorElementType();
8136 unsigned InEltSize = InEltVT.getSizeInBits();
8137 assert(WidenSize % InEltSize == 0 &&
8138 "can not widen bit convert that are not multiple of element type");
8139 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8140 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8141 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8142 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Tmp1);
8144 // If the result size is a multiple of the input size, widen the input
8145 // and then convert.
8146 unsigned InSize = InVT.getSizeInBits();
8147 assert(WidenSize % InSize == 0 &&
8148 "can not widen bit convert that are not multiple of element type");
8149 unsigned NewNumElts = WidenSize / InSize;
8150 SmallVector<SDValue, 16> Ops(NewNumElts);
8151 SDValue UndefVal = DAG.getUNDEF(InVT);
8153 for (unsigned i = 1; i < NewNumElts; ++i)
8156 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8157 Result = DAG.getNode(ISD::BUILD_VECTOR, dl, NewInVT, &Ops[0], NewNumElts);
8158 Result = DAG.getNode(ISD::BIT_CONVERT, dl, WidenVT, Result);
8163 case ISD::SINT_TO_FP:
8164 case ISD::UINT_TO_FP:
8165 case ISD::FP_TO_SINT:
8166 case ISD::FP_TO_UINT:
8167 case ISD::FP_ROUND: {
8168 SDValue Tmp1 = Node->getOperand(0);
8169 // Converts between two different types so we need to determine
8170 // the correct widen type for the input operand.
8171 MVT TVT = Tmp1.getValueType();
8172 assert(TVT.isVector() && "can not widen non vector type");
8173 MVT TEVT = TVT.getVectorElementType();
8174 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8175 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8176 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8177 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8181 case ISD::FP_EXTEND:
8182 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8184 case ISD::SIGN_EXTEND:
8185 case ISD::ZERO_EXTEND:
8186 case ISD::ANY_EXTEND:
8187 case ISD::SIGN_EXTEND_INREG:
8196 // Unary op widening
8198 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8199 assert(Tmp1.getValueType() == WidenVT);
8200 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1);
8203 case ISD::CONVERT_RNDSAT: {
8204 SDValue RndOp = Node->getOperand(3);
8205 SDValue SatOp = Node->getOperand(4);
8206 SDValue SrcOp = Node->getOperand(0);
8208 // Converts between two different types so we need to determine
8209 // the correct widen type for the input operand.
8210 MVT SVT = SrcOp.getValueType();
8211 assert(SVT.isVector() && "can not widen non vector type");
8212 MVT SEVT = SVT.getVectorElementType();
8213 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8215 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8216 assert(SrcOp.getValueType() == WidenVT);
8217 SDValue DTyOp = DAG.getValueType(WidenVT);
8218 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8219 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8221 Result = DAG.getConvertRndSat(WidenVT, dl, SrcOp, DTyOp, STyOp,
8222 RndOp, SatOp, CvtCode);
8242 case ISD::FCOPYSIGN:
8246 // Binary op widening
8247 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8248 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8249 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8250 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2);
8257 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8258 assert(Tmp1.getValueType() == WidenVT);
8259 SDValue ShOp = Node->getOperand(1);
8260 MVT ShVT = ShOp.getValueType();
8261 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8262 WidenVT.getVectorNumElements());
8263 ShOp = WidenVectorOp(ShOp, NewShVT);
8264 assert(ShOp.getValueType() == NewShVT);
8265 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, ShOp);
8269 case ISD::EXTRACT_VECTOR_ELT: {
8270 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8271 assert(Tmp1.getValueType() == WidenVT);
8272 Result = DAG.getNode(Node->getOpcode(), dl, EVT, Tmp1, Node->getOperand(1));
8275 case ISD::CONCAT_VECTORS: {
8276 // We concurrently support only widen on a multiple of the incoming vector.
8277 // We could widen on a multiple of the incoming operand if necessary.
8278 unsigned NumConcat = NewNumElts / NumElts;
8279 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8280 SDValue UndefVal = DAG.getUNDEF(VT);
8281 SmallVector<SDValue, 8> MOps;
8283 for (unsigned i = 1; i != NumConcat; ++i) {
8284 MOps.push_back(UndefVal);
8286 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8287 &MOps[0], MOps.size()));
8290 case ISD::EXTRACT_SUBVECTOR: {
8291 SDValue Tmp1 = Node->getOperand(0);
8292 SDValue Idx = Node->getOperand(1);
8293 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8294 if (CIdx && CIdx->getZExtValue() == 0) {
8295 // Since we are access the start of the vector, the incoming
8296 // vector type might be the proper.
8297 MVT Tmp1VT = Tmp1.getValueType();
8298 if (Tmp1VT == WidenVT)
8301 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8302 if (Tmp1VTNumElts < NewNumElts)
8303 Result = WidenVectorOp(Tmp1, WidenVT);
8305 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, WidenVT, Tmp1, Idx);
8307 } else if (NewNumElts % NumElts == 0) {
8308 // Widen the extracted subvector.
8309 unsigned NumConcat = NewNumElts / NumElts;
8310 SDValue UndefVal = DAG.getUNDEF(VT);
8311 SmallVector<SDValue, 8> MOps;
8313 for (unsigned i = 1; i != NumConcat; ++i) {
8314 MOps.push_back(UndefVal);
8316 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, dl, WidenVT,
8317 &MOps[0], MOps.size()));
8319 assert(0 && "can not widen extract subvector");
8320 // This could be implemented using insert and build vector but I would
8321 // like to see when this happens.
8327 // Determine new condition widen type and widen
8328 SDValue Cond1 = Node->getOperand(0);
8329 MVT CondVT = Cond1.getValueType();
8330 assert(CondVT.isVector() && "can not widen non vector type");
8331 MVT CondEVT = CondVT.getVectorElementType();
8332 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8333 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8334 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8336 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8337 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8338 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8339 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Tmp1, Tmp2);
8343 case ISD::SELECT_CC: {
8344 // Determine new condition widen type and widen
8345 SDValue Cond1 = Node->getOperand(0);
8346 SDValue Cond2 = Node->getOperand(1);
8347 MVT CondVT = Cond1.getValueType();
8348 assert(CondVT.isVector() && "can not widen non vector type");
8349 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8350 MVT CondEVT = CondVT.getVectorElementType();
8351 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8352 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8353 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8354 assert(Cond1.getValueType() == CondWidenVT &&
8355 Cond2.getValueType() == CondWidenVT && "condition not widen");
8357 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8358 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8359 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8360 "operands not widen");
8361 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Cond1, Cond2, Tmp1,
8362 Tmp2, Node->getOperand(4));
8366 // Determine widen for the operand
8367 SDValue Tmp1 = Node->getOperand(0);
8368 MVT TmpVT = Tmp1.getValueType();
8369 assert(TmpVT.isVector() && "can not widen non vector type");
8370 MVT TmpEVT = TmpVT.getVectorElementType();
8371 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8372 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8373 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8374 Result = DAG.getNode(Node->getOpcode(), dl, WidenVT, Tmp1, Tmp2,
8375 Node->getOperand(2));
8378 case ISD::ATOMIC_CMP_SWAP:
8379 case ISD::ATOMIC_LOAD_ADD:
8380 case ISD::ATOMIC_LOAD_SUB:
8381 case ISD::ATOMIC_LOAD_AND:
8382 case ISD::ATOMIC_LOAD_OR:
8383 case ISD::ATOMIC_LOAD_XOR:
8384 case ISD::ATOMIC_LOAD_NAND:
8385 case ISD::ATOMIC_LOAD_MIN:
8386 case ISD::ATOMIC_LOAD_MAX:
8387 case ISD::ATOMIC_LOAD_UMIN:
8388 case ISD::ATOMIC_LOAD_UMAX:
8389 case ISD::ATOMIC_SWAP: {
8390 // For now, we assume that using vectors for these operations don't make
8391 // much sense so we just split it. We return an empty result
8393 SplitVectorOp(Op, X, Y);
8398 } // end switch (Node->getOpcode())
8400 assert(Result.getNode() && "Didn't set a result!");
8402 Result = LegalizeOp(Result);
8404 AddWidenedOperand(Op, Result);
8408 // Utility function to find a legal vector type and its associated element
8409 // type from a preferred width and whose vector type must be the same size
8411 // TLI: Target lowering used to determine legal types
8412 // Width: Preferred width of element type
8413 // VVT: Vector value type whose size we must match.
8414 // Returns VecEVT and EVT - the vector type and its associated element type
8415 static void FindWidenVecType(const TargetLowering &TLI, unsigned Width, MVT VVT,
8416 MVT& EVT, MVT& VecEVT) {
8417 // We start with the preferred width, make it a power of 2 and see if
8418 // we can find a vector type of that width. If not, we reduce it by
8419 // another power of 2. If we have widen the type, a vector of bytes should
8421 assert(TLI.isTypeLegal(VVT));
8422 unsigned EWidth = Width + 1;
8425 EWidth = (1 << Log2_32(EWidth-1));
8426 EVT = MVT::getIntegerVT(EWidth);
8427 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8428 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8429 } while (!TLI.isTypeLegal(VecEVT) ||
8430 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8433 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8443 // We assume that we have good rules to handle loading power of two loads so
8444 // we break down the operations to power of 2 loads. The strategy is to
8445 // load the largest power of 2 that we can easily transform to a legal vector
8446 // and then insert into that vector, and the cast the result into the legal
8447 // vector that we want. This avoids unnecessary stack converts.
8448 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8449 // the load is nonvolatile, we an use a wider load for the value.
8450 // Find a vector length we can load a large chunk
8453 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8454 EVTWidth = EVT.getSizeInBits();
8456 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV, SVOffset,
8457 isVolatile, Alignment);
8458 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecEVT, LdOp);
8459 LdChain.push_back(LdOp.getValue(1));
8461 // Check if we can load the element with one instruction
8462 if (LdWidth == EVTWidth) {
8463 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8466 // The vector element order is endianness dependent.
8468 LdWidth -= EVTWidth;
8469 unsigned Offset = 0;
8471 while (LdWidth > 0) {
8472 unsigned Increment = EVTWidth / 8;
8473 Offset += Increment;
8474 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8475 DAG.getIntPtrConstant(Increment));
8477 if (LdWidth < EVTWidth) {
8478 // Our current type we are using is too large, use a smaller size by
8479 // using a smaller power of 2
8480 unsigned oEVTWidth = EVTWidth;
8481 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8482 EVTWidth = EVT.getSizeInBits();
8483 // Readjust position and vector position based on new load type
8484 Idx = Idx * (oEVTWidth/EVTWidth);
8485 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8488 SDValue LdOp = DAG.getLoad(EVT, dl, Chain, BasePtr, SV,
8489 SVOffset+Offset, isVolatile,
8490 MinAlign(Alignment, Offset));
8491 LdChain.push_back(LdOp.getValue(1));
8492 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecEVT, VecOp, LdOp,
8493 DAG.getIntPtrConstant(Idx++));
8495 LdWidth -= EVTWidth;
8498 return DAG.getNode(ISD::BIT_CONVERT, dl, ResType, VecOp);
8501 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8505 // TODO: Add support for ConcatVec and the ability to load many vector
8506 // types (e.g., v4i8). This will not work when a vector register
8507 // to memory mapping is strange (e.g., vector elements are not
8508 // stored in some sequential order).
8510 // It must be true that the widen vector type is bigger than where
8511 // we need to load from.
8512 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8513 MVT LdVT = LD->getMemoryVT();
8514 DebugLoc dl = LD->getDebugLoc();
8515 assert(LdVT.isVector() && NVT.isVector());
8516 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8519 SDValue Chain = LD->getChain();
8520 SDValue BasePtr = LD->getBasePtr();
8521 int SVOffset = LD->getSrcValueOffset();
8522 unsigned Alignment = LD->getAlignment();
8523 bool isVolatile = LD->isVolatile();
8524 const Value *SV = LD->getSrcValue();
8525 unsigned int LdWidth = LdVT.getSizeInBits();
8527 // Load value as a large register
8528 SDValueVector LdChain;
8529 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8530 Alignment, isVolatile, LdWidth, NVT, dl);
8532 if (LdChain.size() == 1) {
8537 TFOp=DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8538 &LdChain[0], LdChain.size());
8544 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8554 // Breaks the stores into a series of power of 2 width stores. For any
8555 // width, we convert the vector to the vector of element size that we
8556 // want to store. This avoids requiring a stack convert.
8558 // Find a width of the element type we can store with
8559 MVT VVT = ValOp.getValueType();
8562 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8563 EVTWidth = EVT.getSizeInBits();
8565 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, ValOp);
8566 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8567 DAG.getIntPtrConstant(0));
8568 SDValue StOp = DAG.getStore(Chain, dl, EOp, BasePtr, SV, SVOffset,
8569 isVolatile, Alignment);
8570 StChain.push_back(StOp);
8572 // Check if we are done
8573 if (StWidth == EVTWidth) {
8578 StWidth -= EVTWidth;
8579 unsigned Offset = 0;
8581 while (StWidth > 0) {
8582 unsigned Increment = EVTWidth / 8;
8583 Offset += Increment;
8584 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
8585 DAG.getIntPtrConstant(Increment));
8587 if (StWidth < EVTWidth) {
8588 // Our current type we are using is too large, use a smaller size by
8589 // using a smaller power of 2
8590 unsigned oEVTWidth = EVTWidth;
8591 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8592 EVTWidth = EVT.getSizeInBits();
8593 // Readjust position and vector position based on new load type
8594 Idx = Idx * (oEVTWidth/EVTWidth);
8595 VecOp = DAG.getNode(ISD::BIT_CONVERT, dl, VecEVT, VecOp);
8598 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT, VecOp,
8599 DAG.getIntPtrConstant(Idx++));
8600 StChain.push_back(DAG.getStore(Chain, dl, EOp, BasePtr, SV,
8601 SVOffset + Offset, isVolatile,
8602 MinAlign(Alignment, Offset)));
8603 StWidth -= EVTWidth;
8608 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8611 // TODO: It might be cleaner if we can use SplitVector and have more legal
8612 // vector types that can be stored into memory (e.g., v4xi8 can
8613 // be stored as a word). This will not work when a vector register
8614 // to memory mapping is strange (e.g., vector elements are not
8615 // stored in some sequential order).
8617 MVT StVT = ST->getMemoryVT();
8618 SDValue ValOp = ST->getValue();
8619 DebugLoc dl = ST->getDebugLoc();
8621 // Check if we have widen this node with another value
8622 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8623 if (I != WidenNodes.end())
8626 MVT VVT = ValOp.getValueType();
8628 // It must be true that we the widen vector type is bigger than where
8629 // we need to store.
8630 assert(StVT.isVector() && VVT.isVector());
8631 assert(StVT.bitsLT(VVT));
8632 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8635 SDValueVector StChain;
8636 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8637 ST->getSrcValueOffset(), ST->getAlignment(),
8638 ST->isVolatile(), ValOp, StVT.getSizeInBits(), dl);
8639 if (StChain.size() == 1)
8642 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8643 &StChain[0], StChain.size());
8647 // SelectionDAG::Legalize - This is the entry point for the file.
8649 void SelectionDAG::Legalize(bool TypesNeedLegalizing, bool Fast) {
8650 /// run - This is the main entry point to this class.
8652 SelectionDAGLegalize(*this, TypesNeedLegalizing, Fast).LegalizeDAG();