1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Support/MathExtras.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetOptions.h"
21 #include "llvm/CallingConv.h"
22 #include "llvm/Constants.h"
27 //===----------------------------------------------------------------------===//
28 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
29 /// hacks on it until the target machine can handle it. This involves
30 /// eliminating value sizes the machine cannot handle (promoting small sizes to
31 /// large sizes or splitting up large values into small values) as well as
32 /// eliminating operations the machine cannot handle.
34 /// This code also does a small amount of optimization and recognition of idioms
35 /// as part of its processing. For example, if a target does not support a
36 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
37 /// will attempt merge setcc and brc instructions into brcc's.
40 class SelectionDAGLegalize {
44 /// LegalizeAction - This enum indicates what action we should take for each
45 /// value type the can occur in the program.
47 Legal, // The target natively supports this value type.
48 Promote, // This should be promoted to the next larger type.
49 Expand, // This integer type should be broken into smaller pieces.
52 /// ValueTypeActions - This is a bitvector that contains two bits for each
53 /// value type, where the two bits correspond to the LegalizeAction enum.
54 /// This can be queried with "getTypeAction(VT)".
55 unsigned long long ValueTypeActions;
57 /// NeedsAnotherIteration - This is set when we expand a large integer
58 /// operation into smaller integer operations, but the smaller operations are
59 /// not set. This occurs only rarely in practice, for targets that don't have
60 /// 32-bit or larger integer registers.
61 bool NeedsAnotherIteration;
63 /// LegalizedNodes - For nodes that are of legal width, and that have more
64 /// than one use, this map indicates what regularized operand to use. This
65 /// allows us to avoid legalizing the same thing more than once.
66 std::map<SDOperand, SDOperand> LegalizedNodes;
68 /// PromotedNodes - For nodes that are below legal width, and that have more
69 /// than one use, this map indicates what promoted value to use. This allows
70 /// us to avoid promoting the same thing more than once.
71 std::map<SDOperand, SDOperand> PromotedNodes;
73 /// ExpandedNodes - For nodes that need to be expanded, and which have more
74 /// than one use, this map indicates which which operands are the expanded
75 /// version of the input. This allows us to avoid expanding the same node
77 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
79 void AddLegalizedOperand(SDOperand From, SDOperand To) {
80 bool isNew = LegalizedNodes.insert(std::make_pair(From, To)).second;
81 assert(isNew && "Got into the map somehow?");
83 void AddPromotedOperand(SDOperand From, SDOperand To) {
84 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
85 assert(isNew && "Got into the map somehow?");
90 SelectionDAGLegalize(SelectionDAG &DAG);
92 /// Run - While there is still lowering to do, perform a pass over the DAG.
93 /// Most regularization can be done in a single pass, but targets that require
94 /// large values to be split into registers multiple times (e.g. i64 -> 4x
95 /// i16) require iteration for these values (the first iteration will demote
96 /// to i32, the second will demote to i16).
99 NeedsAnotherIteration = false;
101 } while (NeedsAnotherIteration);
104 /// getTypeAction - Return how we should legalize values of this type, either
105 /// it is already legal or we need to expand it into multiple registers of
106 /// smaller integer type, or we need to promote it to a larger type.
107 LegalizeAction getTypeAction(MVT::ValueType VT) const {
108 return (LegalizeAction)((ValueTypeActions >> (2*VT)) & 3);
111 /// isTypeLegal - Return true if this type is legal on this target.
113 bool isTypeLegal(MVT::ValueType VT) const {
114 return getTypeAction(VT) == Legal;
120 SDOperand LegalizeOp(SDOperand O);
121 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
122 SDOperand PromoteOp(SDOperand O);
124 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
126 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
129 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
131 MVT::ValueType DestVT);
132 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
134 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
137 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
138 SDOperand &Lo, SDOperand &Hi);
139 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
140 SDOperand &Lo, SDOperand &Hi);
141 void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
142 SDOperand &Lo, SDOperand &Hi);
144 void SpliceCallInto(const SDOperand &CallResult, SDNode *OutChain);
146 SDOperand getIntPtrConstant(uint64_t Val) {
147 return DAG.getConstant(Val, TLI.getPointerTy());
152 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
154 default: assert(0 && "Don't know how to scalarize this opcode!");
155 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
156 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
157 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
161 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
162 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
163 ValueTypeActions(TLI.getValueTypeActions()) {
164 assert(MVT::LAST_VALUETYPE <= 32 &&
165 "Too many value types for ValueTypeActions to hold!");
168 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
169 /// INT_TO_FP operation of the specified operand when the target requests that
170 /// we expand it. At this point, we know that the result and operand types are
171 /// legal for the target.
172 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
174 MVT::ValueType DestVT) {
175 if (Op0.getValueType() == MVT::i32) {
176 // simple 32-bit [signed|unsigned] integer to float/double expansion
178 // get the stack frame index of a 8 byte buffer
179 MachineFunction &MF = DAG.getMachineFunction();
180 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
181 // get address of 8 byte buffer
182 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
183 // word offset constant for Hi/Lo address computation
184 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
185 // set up Hi and Lo (into buffer) address based on endian
187 if (TLI.isLittleEndian()) {
188 Hi = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
192 Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot, WordOff);
194 // if signed map to unsigned space
197 // constant used to invert sign bit (signed to unsigned mapping)
198 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
199 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
203 // store the lo of the constructed double - based on integer input
204 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
205 Op0Mapped, Lo, DAG.getSrcValue(NULL));
206 // initial hi portion of constructed double
207 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
208 // store the hi of the constructed double - biased exponent
209 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
210 InitialHi, Hi, DAG.getSrcValue(NULL));
211 // load the constructed double
212 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
213 DAG.getSrcValue(NULL));
214 // FP constant to bias correct the final result
215 SDOperand Bias = DAG.getConstantFP(isSigned ?
216 BitsToDouble(0x4330000080000000ULL)
217 : BitsToDouble(0x4330000000000000ULL),
220 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
223 // handle final rounding
224 if (DestVT == MVT::f64) {
228 // if f32 then cast to f32
229 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
231 NeedsAnotherIteration = true;
234 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
235 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
237 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
238 DAG.getConstant(0, Op0.getValueType()),
240 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
241 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
242 SignSet, Four, Zero);
244 // If the sign bit of the integer is set, the large number will be treated
245 // as a negative number. To counteract this, the dynamic code adds an
246 // offset depending on the data type.
248 switch (Op0.getValueType()) {
249 default: assert(0 && "Unsupported integer type!");
250 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
251 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
252 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
253 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
255 if (TLI.isLittleEndian()) FF <<= 32;
256 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
258 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
259 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
260 SDOperand FudgeInReg;
261 if (DestVT == MVT::f32)
262 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
263 DAG.getSrcValue(NULL));
265 assert(DestVT == MVT::f64 && "Unexpected conversion");
266 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
267 DAG.getEntryNode(), CPIdx,
268 DAG.getSrcValue(NULL), MVT::f32));
271 NeedsAnotherIteration = true;
272 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
275 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
276 /// *INT_TO_FP operation of the specified operand when the target requests that
277 /// we promote it. At this point, we know that the result and operand types are
278 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
279 /// operation that takes a larger input.
280 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
281 MVT::ValueType DestVT,
283 // First step, figure out the appropriate *INT_TO_FP operation to use.
284 MVT::ValueType NewInTy = LegalOp.getValueType();
286 unsigned OpToUse = 0;
288 // Scan for the appropriate larger type to use.
290 NewInTy = (MVT::ValueType)(NewInTy+1);
291 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
293 // If the target supports SINT_TO_FP of this type, use it.
294 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
296 case TargetLowering::Legal:
297 if (!TLI.isTypeLegal(NewInTy))
298 break; // Can't use this datatype.
300 case TargetLowering::Custom:
301 OpToUse = ISD::SINT_TO_FP;
305 if (isSigned) continue;
307 // If the target supports UINT_TO_FP of this type, use it.
308 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
310 case TargetLowering::Legal:
311 if (!TLI.isTypeLegal(NewInTy))
312 break; // Can't use this datatype.
314 case TargetLowering::Custom:
315 OpToUse = ISD::UINT_TO_FP;
320 // Otherwise, try a larger type.
323 // Make sure to legalize any nodes we create here in the next pass.
324 NeedsAnotherIteration = true;
326 // Okay, we found the operation and type to use. Zero extend our input to the
327 // desired type then run the operation on it.
328 return DAG.getNode(OpToUse, DestVT,
329 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
333 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
334 /// FP_TO_*INT operation of the specified operand when the target requests that
335 /// we promote it. At this point, we know that the result and operand types are
336 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
337 /// operation that returns a larger result.
338 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
339 MVT::ValueType DestVT,
341 // First step, figure out the appropriate FP_TO*INT operation to use.
342 MVT::ValueType NewOutTy = DestVT;
344 unsigned OpToUse = 0;
346 // Scan for the appropriate larger type to use.
348 NewOutTy = (MVT::ValueType)(NewOutTy+1);
349 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
351 // If the target supports FP_TO_SINT returning this type, use it.
352 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
354 case TargetLowering::Legal:
355 if (!TLI.isTypeLegal(NewOutTy))
356 break; // Can't use this datatype.
358 case TargetLowering::Custom:
359 OpToUse = ISD::FP_TO_SINT;
364 // If the target supports FP_TO_UINT of this type, use it.
365 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
367 case TargetLowering::Legal:
368 if (!TLI.isTypeLegal(NewOutTy))
369 break; // Can't use this datatype.
371 case TargetLowering::Custom:
372 OpToUse = ISD::FP_TO_UINT;
377 // Otherwise, try a larger type.
380 // Make sure to legalize any nodes we create here in the next pass.
381 NeedsAnotherIteration = true;
383 // Okay, we found the operation and type to use. Truncate the result of the
384 // extended FP_TO_*INT operation to the desired size.
385 return DAG.getNode(ISD::TRUNCATE, DestVT,
386 DAG.getNode(OpToUse, NewOutTy, LegalOp));
389 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
390 /// not been visited yet and if all of its operands have already been visited.
391 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
392 std::map<SDNode*, unsigned> &Visited) {
393 if (++Visited[N] != N->getNumOperands())
394 return; // Haven't visited all operands yet
398 if (N->hasOneUse()) { // Tail recurse in common case.
399 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
403 // Now that we have N in, add anything that uses it if all of their operands
405 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
406 ComputeTopDownOrdering(*UI, Order, Visited);
410 void SelectionDAGLegalize::LegalizeDAG() {
411 // The legalize process is inherently a bottom-up recursive process (users
412 // legalize their uses before themselves). Given infinite stack space, we
413 // could just start legalizing on the root and traverse the whole graph. In
414 // practice however, this causes us to run out of stack space on large basic
415 // blocks. To avoid this problem, compute an ordering of the nodes where each
416 // node is only legalized after all of its operands are legalized.
417 std::map<SDNode*, unsigned> Visited;
418 std::vector<SDNode*> Order;
420 // Compute ordering from all of the leaves in the graphs, those (like the
421 // entry node) that have no operands.
422 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
423 E = DAG.allnodes_end(); I != E; ++I) {
424 if (I->getNumOperands() == 0) {
426 ComputeTopDownOrdering(I, Order, Visited);
430 assert(Order.size() == Visited.size() &&
432 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
433 "Error: DAG is cyclic!");
436 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
437 SDNode *N = Order[i];
438 switch (getTypeAction(N->getValueType(0))) {
439 default: assert(0 && "Bad type action!");
441 LegalizeOp(SDOperand(N, 0));
444 PromoteOp(SDOperand(N, 0));
448 ExpandOp(SDOperand(N, 0), X, Y);
454 // Finally, it's possible the root changed. Get the new root.
455 SDOperand OldRoot = DAG.getRoot();
456 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
457 DAG.setRoot(LegalizedNodes[OldRoot]);
459 ExpandedNodes.clear();
460 LegalizedNodes.clear();
461 PromotedNodes.clear();
463 // Remove dead nodes now.
464 DAG.RemoveDeadNodes(OldRoot.Val);
467 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
468 assert(isTypeLegal(Op.getValueType()) &&
469 "Caller should expand or promote operands that are not legal!");
470 SDNode *Node = Op.Val;
472 // If this operation defines any values that cannot be represented in a
473 // register on this target, make sure to expand or promote them.
474 if (Node->getNumValues() > 1) {
475 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
476 switch (getTypeAction(Node->getValueType(i))) {
477 case Legal: break; // Nothing to do.
480 ExpandOp(Op.getValue(i), T1, T2);
481 assert(LegalizedNodes.count(Op) &&
482 "Expansion didn't add legal operands!");
483 return LegalizedNodes[Op];
486 PromoteOp(Op.getValue(i));
487 assert(LegalizedNodes.count(Op) &&
488 "Expansion didn't add legal operands!");
489 return LegalizedNodes[Op];
493 // Note that LegalizeOp may be reentered even from single-use nodes, which
494 // means that we always must cache transformed nodes.
495 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
496 if (I != LegalizedNodes.end()) return I->second;
498 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
500 SDOperand Result = Op;
502 switch (Node->getOpcode()) {
504 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
505 // If this is a target node, legalize it by legalizing the operands then
506 // passing it through.
507 std::vector<SDOperand> Ops;
508 bool Changed = false;
509 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
510 Ops.push_back(LegalizeOp(Node->getOperand(i)));
511 Changed = Changed || Node->getOperand(i) != Ops.back();
514 if (Node->getNumValues() == 1)
515 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Ops);
517 std::vector<MVT::ValueType> VTs(Node->value_begin(),
519 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
522 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
523 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
524 return Result.getValue(Op.ResNo);
526 // Otherwise this is an unhandled builtin node. splat.
527 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
528 assert(0 && "Do not know how to legalize this operator!");
530 case ISD::EntryToken:
531 case ISD::FrameIndex:
532 case ISD::TargetFrameIndex:
534 case ISD::TargetConstant:
535 case ISD::TargetConstantPool:
536 case ISD::GlobalAddress:
537 case ISD::TargetGlobalAddress:
538 case ISD::ExternalSymbol:
539 case ISD::ConstantPool: // Nothing to do.
540 case ISD::BasicBlock:
545 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
546 default: assert(0 && "This action is not supported yet!");
547 case TargetLowering::Custom: {
548 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
550 Result = LegalizeOp(Tmp);
553 } // FALLTHROUGH if the target doesn't want to lower this op after all.
554 case TargetLowering::Legal:
555 assert(isTypeLegal(Node->getValueType(0)) && "This must be legal!");
559 case ISD::AssertSext:
560 case ISD::AssertZext:
561 Tmp1 = LegalizeOp(Node->getOperand(0));
562 if (Tmp1 != Node->getOperand(0))
563 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
564 Node->getOperand(1));
566 case ISD::MERGE_VALUES:
567 return LegalizeOp(Node->getOperand(Op.ResNo));
568 case ISD::CopyFromReg:
569 Tmp1 = LegalizeOp(Node->getOperand(0));
570 if (Tmp1 != Node->getOperand(0))
571 Result = DAG.getCopyFromReg(Tmp1,
572 cast<RegisterSDNode>(Node->getOperand(1))->getReg(),
573 Node->getValueType(0));
575 Result = Op.getValue(0);
577 // Since CopyFromReg produces two values, make sure to remember that we
578 // legalized both of them.
579 AddLegalizedOperand(Op.getValue(0), Result);
580 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
581 return Result.getValue(Op.ResNo);
582 case ISD::ImplicitDef:
583 Tmp1 = LegalizeOp(Node->getOperand(0));
584 if (Tmp1 != Node->getOperand(0))
585 Result = DAG.getNode(ISD::ImplicitDef, MVT::Other,
586 Tmp1, Node->getOperand(1));
589 MVT::ValueType VT = Op.getValueType();
590 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
591 default: assert(0 && "This action is not supported yet!");
592 case TargetLowering::Expand:
593 case TargetLowering::Promote:
594 if (MVT::isInteger(VT))
595 Result = DAG.getConstant(0, VT);
596 else if (MVT::isFloatingPoint(VT))
597 Result = DAG.getConstantFP(0, VT);
599 assert(0 && "Unknown value type!");
601 case TargetLowering::Legal:
608 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
609 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
611 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
612 case TargetLowering::Promote:
613 default: assert(0 && "This action is not supported yet!");
614 case TargetLowering::Expand:
615 // If the target doesn't support line numbers, ignore this node.
618 case TargetLowering::Legal:
619 if (Tmp1 != Node->getOperand(0) ||
620 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
621 std::vector<SDOperand> Ops;
623 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
624 Ops.push_back(Node->getOperand(1)); // line # must be legal.
625 Ops.push_back(Node->getOperand(2)); // col # must be legal.
627 // Otherwise promote them.
628 Ops.push_back(PromoteOp(Node->getOperand(1)));
629 Ops.push_back(PromoteOp(Node->getOperand(2)));
631 Ops.push_back(Node->getOperand(3)); // filename must be legal.
632 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
633 Result = DAG.getNode(ISD::LOCATION, MVT::Other, Ops);
640 // We know we don't need to expand constants here, constants only have one
641 // value and we check that it is fine above.
643 // FIXME: Maybe we should handle things like targets that don't support full
644 // 32-bit immediates?
646 case ISD::ConstantFP: {
647 // Spill FP immediates to the constant pool if the target cannot directly
648 // codegen them. Targets often have some immediate values that can be
649 // efficiently generated into an FP register without a load. We explicitly
650 // leave these constants as ConstantFP nodes for the target to deal with.
652 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
654 // Check to see if this FP immediate is already legal.
655 bool isLegal = false;
656 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
657 E = TLI.legal_fpimm_end(); I != E; ++I)
658 if (CFP->isExactlyValue(*I)) {
664 // Otherwise we need to spill the constant to memory.
667 // If a FP immediate is precise when represented as a float, we put it
668 // into the constant pool as a float, even if it's is statically typed
670 MVT::ValueType VT = CFP->getValueType(0);
671 bool isDouble = VT == MVT::f64;
672 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
673 Type::FloatTy, CFP->getValue());
674 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
675 // Only do this if the target has a native EXTLOAD instruction from
677 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
678 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
684 LegalizeOp(DAG.getConstantPool(LLVMC, TLI.getPointerTy()));
686 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
687 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
689 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
690 DAG.getSrcValue(NULL));
695 case ISD::ConstantVec: {
696 // We assume that vector constants are not legal, and will be immediately
697 // spilled to the constant pool.
699 // FIXME: revisit this when we have some kind of mechanism by which targets
700 // can decided legality of vector constants, of which there may be very
703 // Create a ConstantPacked, and put it in the constant pool.
704 std::vector<Constant*> CV;
705 MVT::ValueType VT = Node->getValueType(0);
706 for (unsigned I = 0, E = Node->getNumOperands(); I < E; ++I) {
707 SDOperand OpN = Node->getOperand(I);
708 const Type* OpNTy = MVT::getTypeForValueType(OpN.getValueType());
709 if (MVT::isFloatingPoint(VT))
710 CV.push_back(ConstantFP::get(OpNTy,
711 cast<ConstantFPSDNode>(OpN)->getValue()));
713 CV.push_back(ConstantUInt::get(OpNTy,
714 cast<ConstantSDNode>(OpN)->getValue()));
716 Constant *CP = ConstantPacked::get(CV);
717 SDOperand CPIdx = DAG.getConstantPool(CP, Node->getValueType(0));
718 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, DAG.getSrcValue(NULL));
721 case ISD::TokenFactor:
722 if (Node->getNumOperands() == 2) {
723 bool Changed = false;
724 SDOperand Op0 = LegalizeOp(Node->getOperand(0));
725 SDOperand Op1 = LegalizeOp(Node->getOperand(1));
726 if (Op0 != Node->getOperand(0) || Op1 != Node->getOperand(1))
727 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
729 std::vector<SDOperand> Ops;
730 bool Changed = false;
731 // Legalize the operands.
732 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
733 SDOperand Op = Node->getOperand(i);
734 Ops.push_back(LegalizeOp(Op));
735 Changed |= Ops[i] != Op;
738 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
742 case ISD::CALLSEQ_START:
743 case ISD::CALLSEQ_END:
744 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
745 // Do not try to legalize the target-specific arguments (#1+)
746 Tmp2 = Node->getOperand(0);
748 Node->setAdjCallChain(Tmp1);
750 // Note that we do not create new CALLSEQ_DOWN/UP nodes here. These
751 // nodes are treated specially and are mutated in place. This makes the dag
752 // legalization process more efficient and also makes libcall insertion
755 case ISD::DYNAMIC_STACKALLOC:
756 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
757 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
758 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
759 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
760 Tmp3 != Node->getOperand(2)) {
761 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
762 std::vector<SDOperand> Ops;
763 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
764 Result = DAG.getNode(ISD::DYNAMIC_STACKALLOC, VTs, Ops);
766 Result = Op.getValue(0);
768 // Since this op produces two values, make sure to remember that we
769 // legalized both of them.
770 AddLegalizedOperand(SDOperand(Node, 0), Result);
771 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
772 return Result.getValue(Op.ResNo);
776 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
777 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
779 bool Changed = false;
780 std::vector<SDOperand> Ops;
781 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
782 Ops.push_back(LegalizeOp(Node->getOperand(i)));
783 Changed |= Ops.back() != Node->getOperand(i);
786 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) || Changed) {
787 std::vector<MVT::ValueType> RetTyVTs;
788 RetTyVTs.reserve(Node->getNumValues());
789 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
790 RetTyVTs.push_back(Node->getValueType(i));
791 Result = SDOperand(DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
792 Node->getOpcode() == ISD::TAILCALL), 0);
794 Result = Result.getValue(0);
796 // Since calls produce multiple values, make sure to remember that we
797 // legalized all of them.
798 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
799 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
800 return Result.getValue(Op.ResNo);
803 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
804 if (Tmp1 != Node->getOperand(0))
805 Result = DAG.getNode(ISD::BR, MVT::Other, Tmp1, Node->getOperand(1));
809 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
811 switch (getTypeAction(Node->getOperand(1).getValueType())) {
812 case Expand: assert(0 && "It's impossible to expand bools");
814 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
817 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
821 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
822 default: assert(0 && "This action is not supported yet!");
823 case TargetLowering::Expand:
824 // Expand brcond's setcc into its constituent parts and create a BR_CC
826 if (Tmp2.getOpcode() == ISD::SETCC) {
827 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
828 Tmp2.getOperand(0), Tmp2.getOperand(1),
829 Node->getOperand(2));
831 // Make sure the condition is either zero or one. It may have been
832 // promoted from something else.
833 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
835 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
836 DAG.getCondCode(ISD::SETNE), Tmp2,
837 DAG.getConstant(0, Tmp2.getValueType()),
838 Node->getOperand(2));
841 case TargetLowering::Legal:
842 // Basic block destination (Op#2) is always legal.
843 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
844 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
845 Node->getOperand(2));
850 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
852 if (isTypeLegal(Node->getOperand(2).getValueType())) {
853 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
854 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
855 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
856 Tmp3 != Node->getOperand(3)) {
857 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Node->getOperand(1),
858 Tmp2, Tmp3, Node->getOperand(4));
862 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
863 Node->getOperand(2), // LHS
864 Node->getOperand(3), // RHS
865 Node->getOperand(1)));
866 // If we get a SETCC back from legalizing the SETCC node we just
867 // created, then use its LHS, RHS, and CC directly in creating a new
868 // node. Otherwise, select between the true and false value based on
869 // comparing the result of the legalized with zero.
870 if (Tmp2.getOpcode() == ISD::SETCC) {
871 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
872 Tmp2.getOperand(0), Tmp2.getOperand(1),
873 Node->getOperand(4));
875 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
876 DAG.getCondCode(ISD::SETNE),
877 Tmp2, DAG.getConstant(0, Tmp2.getValueType()),
878 Node->getOperand(4));
882 case ISD::BRCONDTWOWAY:
883 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
884 switch (getTypeAction(Node->getOperand(1).getValueType())) {
885 case Expand: assert(0 && "It's impossible to expand bools");
887 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
890 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
893 // If this target does not support BRCONDTWOWAY, lower it to a BRCOND/BR
895 switch (TLI.getOperationAction(ISD::BRCONDTWOWAY, MVT::Other)) {
896 case TargetLowering::Promote:
897 default: assert(0 && "This action is not supported yet!");
898 case TargetLowering::Legal:
899 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
900 std::vector<SDOperand> Ops;
903 Ops.push_back(Node->getOperand(2));
904 Ops.push_back(Node->getOperand(3));
905 Result = DAG.getNode(ISD::BRCONDTWOWAY, MVT::Other, Ops);
908 case TargetLowering::Expand:
909 // If BRTWOWAY_CC is legal for this target, then simply expand this node
910 // to that. Otherwise, skip BRTWOWAY_CC and expand directly to a
912 if (TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
913 if (Tmp2.getOpcode() == ISD::SETCC) {
914 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
915 Tmp2.getOperand(0), Tmp2.getOperand(1),
916 Node->getOperand(2), Node->getOperand(3));
918 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
919 DAG.getConstant(0, Tmp2.getValueType()),
920 Node->getOperand(2), Node->getOperand(3));
923 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
924 Node->getOperand(2));
925 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(3));
930 case ISD::BRTWOWAY_CC:
931 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
932 if (isTypeLegal(Node->getOperand(2).getValueType())) {
933 Tmp2 = LegalizeOp(Node->getOperand(2)); // LHS
934 Tmp3 = LegalizeOp(Node->getOperand(3)); // RHS
935 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2) ||
936 Tmp3 != Node->getOperand(3)) {
937 Result = DAG.getBR2Way_CC(Tmp1, Node->getOperand(1), Tmp2, Tmp3,
938 Node->getOperand(4), Node->getOperand(5));
942 Tmp2 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
943 Node->getOperand(2), // LHS
944 Node->getOperand(3), // RHS
945 Node->getOperand(1)));
946 // If this target does not support BRTWOWAY_CC, lower it to a BRCOND/BR
948 switch (TLI.getOperationAction(ISD::BRTWOWAY_CC, MVT::Other)) {
949 default: assert(0 && "This action is not supported yet!");
950 case TargetLowering::Legal:
951 // If we get a SETCC back from legalizing the SETCC node we just
952 // created, then use its LHS, RHS, and CC directly in creating a new
953 // node. Otherwise, select between the true and false value based on
954 // comparing the result of the legalized with zero.
955 if (Tmp2.getOpcode() == ISD::SETCC) {
956 Result = DAG.getBR2Way_CC(Tmp1, Tmp2.getOperand(2),
957 Tmp2.getOperand(0), Tmp2.getOperand(1),
958 Node->getOperand(4), Node->getOperand(5));
960 Result = DAG.getBR2Way_CC(Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2,
961 DAG.getConstant(0, Tmp2.getValueType()),
962 Node->getOperand(4), Node->getOperand(5));
965 case TargetLowering::Expand:
966 Result = DAG.getNode(ISD::BRCOND, MVT::Other, Tmp1, Tmp2,
967 Node->getOperand(4));
968 Result = DAG.getNode(ISD::BR, MVT::Other, Result, Node->getOperand(5));
974 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
975 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
977 if (Tmp1 != Node->getOperand(0) ||
978 Tmp2 != Node->getOperand(1))
979 Result = DAG.getLoad(Node->getValueType(0), Tmp1, Tmp2,
980 Node->getOperand(2));
982 Result = SDOperand(Node, 0);
984 // Since loads produce two values, make sure to remember that we legalized
986 AddLegalizedOperand(SDOperand(Node, 0), Result);
987 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
988 return Result.getValue(Op.ResNo);
992 case ISD::ZEXTLOAD: {
993 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
994 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
996 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
997 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
998 default: assert(0 && "This action is not supported yet!");
999 case TargetLowering::Promote:
1000 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1001 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1002 Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
1003 // Since loads produce two values, make sure to remember that we legalized
1005 AddLegalizedOperand(SDOperand(Node, 0), Result);
1006 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1007 return Result.getValue(Op.ResNo);
1009 case TargetLowering::Legal:
1010 if (Tmp1 != Node->getOperand(0) ||
1011 Tmp2 != Node->getOperand(1))
1012 Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
1013 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1015 Result = SDOperand(Node, 0);
1017 // Since loads produce two values, make sure to remember that we legalized
1019 AddLegalizedOperand(SDOperand(Node, 0), Result);
1020 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1021 return Result.getValue(Op.ResNo);
1022 case TargetLowering::Expand:
1023 //f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1024 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1025 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1026 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1028 return Load.getValue(1);
1031 assert(Node->getOpcode() != ISD::EXTLOAD &&
1032 "EXTLOAD should always be supported!");
1033 // Turn the unsupported load into an EXTLOAD followed by an explicit
1034 // zero/sign extend inreg.
1035 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1036 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1038 if (Node->getOpcode() == ISD::SEXTLOAD)
1039 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1040 Result, DAG.getValueType(SrcVT));
1042 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1043 AddLegalizedOperand(SDOperand(Node, 0), ValRes);
1044 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1046 return Result.getValue(1);
1049 assert(0 && "Unreachable");
1051 case ISD::EXTRACT_ELEMENT: {
1052 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1053 switch (getTypeAction(OpTy)) {
1055 assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1058 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1060 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1061 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1062 TLI.getShiftAmountTy()));
1063 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1066 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1067 Node->getOperand(0));
1069 Result = LegalizeOp(Result);
1072 // Get both the low and high parts.
1073 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1074 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1075 Result = Tmp2; // 1 -> Hi
1077 Result = Tmp1; // 0 -> Lo
1083 case ISD::CopyToReg:
1084 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1086 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1087 "Register type must be legal!");
1088 // Legalize the incoming value (must be legal).
1089 Tmp2 = LegalizeOp(Node->getOperand(2));
1090 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(2))
1091 Result = DAG.getNode(ISD::CopyToReg, MVT::Other, Tmp1,
1092 Node->getOperand(1), Tmp2);
1096 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1097 switch (Node->getNumOperands()) {
1099 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1101 Tmp2 = LegalizeOp(Node->getOperand(1));
1102 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1103 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1107 ExpandOp(Node->getOperand(1), Lo, Hi);
1108 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1112 Tmp2 = PromoteOp(Node->getOperand(1));
1113 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Tmp2);
1118 if (Tmp1 != Node->getOperand(0))
1119 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1);
1121 default: { // ret <values>
1122 std::vector<SDOperand> NewValues;
1123 NewValues.push_back(Tmp1);
1124 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1125 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1127 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1131 ExpandOp(Node->getOperand(i), Lo, Hi);
1132 NewValues.push_back(Lo);
1133 NewValues.push_back(Hi);
1137 assert(0 && "Can't promote multiple return value yet!");
1139 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1145 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1146 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1148 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1149 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1150 if (CFP->getValueType(0) == MVT::f32) {
1151 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1152 DAG.getConstant(FloatToBits(CFP->getValue()),
1155 Node->getOperand(3));
1157 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1158 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1,
1159 DAG.getConstant(DoubleToBits(CFP->getValue()),
1162 Node->getOperand(3));
1167 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1169 SDOperand Val = LegalizeOp(Node->getOperand(1));
1170 if (Val != Node->getOperand(1) || Tmp1 != Node->getOperand(0) ||
1171 Tmp2 != Node->getOperand(2))
1172 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Val, Tmp2,
1173 Node->getOperand(3));
1177 // Truncate the value and store the result.
1178 Tmp3 = PromoteOp(Node->getOperand(1));
1179 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1180 Node->getOperand(3),
1181 DAG.getValueType(Node->getOperand(1).getValueType()));
1186 unsigned IncrementSize;
1187 ExpandOp(Node->getOperand(1), Lo, Hi);
1189 if (!TLI.isLittleEndian())
1192 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1193 Node->getOperand(3));
1194 // If this is a vector type, then we have to calculate the increment as
1195 // the product of the element size in bytes, and the number of elements
1196 // in the high half of the vector.
1197 if (MVT::Vector == Hi.getValueType()) {
1198 unsigned NumElems = cast<ConstantSDNode>(Hi.getOperand(2))->getValue();
1199 MVT::ValueType EVT = cast<VTSDNode>(Hi.getOperand(3))->getVT();
1200 IncrementSize = NumElems * MVT::getSizeInBits(EVT)/8;
1202 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1204 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1205 getIntPtrConstant(IncrementSize));
1206 assert(isTypeLegal(Tmp2.getValueType()) &&
1207 "Pointers must be legal!");
1208 //Again, claiming both parts of the store came form the same Instr
1209 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1210 Node->getOperand(3));
1211 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1216 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1217 if (Tmp1 != Node->getOperand(0))
1218 Result = DAG.getNode(ISD::PCMARKER, MVT::Other, Tmp1,Node->getOperand(1));
1220 case ISD::READCYCLECOUNTER:
1221 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1222 if (Tmp1 != Node->getOperand(0)) {
1223 std::vector<MVT::ValueType> rtypes;
1224 std::vector<SDOperand> rvals;
1225 rtypes.push_back(MVT::i64);
1226 rtypes.push_back(MVT::Other);
1227 rvals.push_back(Tmp1);
1228 Result = DAG.getNode(ISD::READCYCLECOUNTER, rtypes, rvals);
1231 // Since rdcc produce two values, make sure to remember that we legalized
1233 AddLegalizedOperand(SDOperand(Node, 0), Result);
1234 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1235 return Result.getValue(Op.ResNo);
1238 case ISD::TRUNCSTORE:
1239 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1240 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1242 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1244 Tmp2 = LegalizeOp(Node->getOperand(1));
1246 // The only promote case we handle is TRUNCSTORE:i1 X into
1247 // -> TRUNCSTORE:i8 (and X, 1)
1248 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1249 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1250 TargetLowering::Promote) {
1251 // Promote the bool to a mask then store.
1252 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1253 DAG.getConstant(1, Tmp2.getValueType()));
1254 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1255 Node->getOperand(3), DAG.getValueType(MVT::i8));
1257 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1258 Tmp3 != Node->getOperand(2)) {
1259 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1260 Node->getOperand(3), Node->getOperand(4));
1265 assert(0 && "Cannot handle illegal TRUNCSTORE yet!");
1269 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1270 case Expand: assert(0 && "It's impossible to expand bools");
1272 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1275 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1278 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1279 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1281 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1282 default: assert(0 && "This action is not supported yet!");
1283 case TargetLowering::Expand:
1284 if (Tmp1.getOpcode() == ISD::SETCC) {
1285 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1287 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1289 // Make sure the condition is either zero or one. It may have been
1290 // promoted from something else.
1291 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1292 Result = DAG.getSelectCC(Tmp1,
1293 DAG.getConstant(0, Tmp1.getValueType()),
1294 Tmp2, Tmp3, ISD::SETNE);
1297 case TargetLowering::Legal:
1298 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1299 Tmp3 != Node->getOperand(2))
1300 Result = DAG.getNode(ISD::SELECT, Node->getValueType(0),
1303 case TargetLowering::Promote: {
1304 MVT::ValueType NVT =
1305 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1306 unsigned ExtOp, TruncOp;
1307 if (MVT::isInteger(Tmp2.getValueType())) {
1308 ExtOp = ISD::ANY_EXTEND;
1309 TruncOp = ISD::TRUNCATE;
1311 ExtOp = ISD::FP_EXTEND;
1312 TruncOp = ISD::FP_ROUND;
1314 // Promote each of the values to the new type.
1315 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1316 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1317 // Perform the larger operation, then round down.
1318 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1319 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1324 case ISD::SELECT_CC:
1325 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1326 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1328 if (isTypeLegal(Node->getOperand(0).getValueType())) {
1329 // Everything is legal, see if we should expand this op or something.
1330 switch (TLI.getOperationAction(ISD::SELECT_CC,
1331 Node->getOperand(0).getValueType())) {
1332 default: assert(0 && "This action is not supported yet!");
1333 case TargetLowering::Custom: {
1335 TLI.LowerOperation(DAG.getNode(ISD::SELECT_CC, Node->getValueType(0),
1336 Node->getOperand(0),
1337 Node->getOperand(1), Tmp3, Tmp4,
1338 Node->getOperand(4)), DAG);
1340 Result = LegalizeOp(Tmp);
1343 } // FALLTHROUGH if the target can't lower this operation after all.
1344 case TargetLowering::Legal:
1345 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1346 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1347 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1348 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3)) {
1349 Result = DAG.getNode(ISD::SELECT_CC, Node->getValueType(0), Tmp1, Tmp2,
1350 Tmp3, Tmp4, Node->getOperand(4));
1356 Tmp1 = LegalizeOp(DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),
1357 Node->getOperand(0), // LHS
1358 Node->getOperand(1), // RHS
1359 Node->getOperand(4)));
1360 // If we get a SETCC back from legalizing the SETCC node we just
1361 // created, then use its LHS, RHS, and CC directly in creating a new
1362 // node. Otherwise, select between the true and false value based on
1363 // comparing the result of the legalized with zero.
1364 if (Tmp1.getOpcode() == ISD::SETCC) {
1365 Result = DAG.getNode(ISD::SELECT_CC, Tmp3.getValueType(),
1366 Tmp1.getOperand(0), Tmp1.getOperand(1),
1367 Tmp3, Tmp4, Tmp1.getOperand(2));
1369 Result = DAG.getSelectCC(Tmp1,
1370 DAG.getConstant(0, Tmp1.getValueType()),
1371 Tmp3, Tmp4, ISD::SETNE);
1376 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1378 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1379 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1382 Tmp1 = PromoteOp(Node->getOperand(0)); // LHS
1383 Tmp2 = PromoteOp(Node->getOperand(1)); // RHS
1385 // If this is an FP compare, the operands have already been extended.
1386 if (MVT::isInteger(Node->getOperand(0).getValueType())) {
1387 MVT::ValueType VT = Node->getOperand(0).getValueType();
1388 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
1390 // Otherwise, we have to insert explicit sign or zero extends. Note
1391 // that we could insert sign extends for ALL conditions, but zero extend
1392 // is cheaper on many machines (an AND instead of two shifts), so prefer
1394 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1395 default: assert(0 && "Unknown integer comparison!");
1402 // ALL of these operations will work if we either sign or zero extend
1403 // the operands (including the unsigned comparisons!). Zero extend is
1404 // usually a simpler/cheaper operation, so prefer it.
1405 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
1406 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
1412 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
1413 DAG.getValueType(VT));
1414 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
1415 DAG.getValueType(VT));
1421 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
1422 ExpandOp(Node->getOperand(0), LHSLo, LHSHi);
1423 ExpandOp(Node->getOperand(1), RHSLo, RHSHi);
1424 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1428 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
1429 if (RHSCST->isAllOnesValue()) {
1430 // Comparison to -1.
1431 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
1436 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
1437 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
1438 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
1439 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1442 // If this is a comparison of the sign bit, just look at the top part.
1444 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Node->getOperand(1)))
1445 if ((cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETLT &&
1446 CST->getValue() == 0) || // X < 0
1447 (cast<CondCodeSDNode>(Node->getOperand(2))->get() == ISD::SETGT &&
1448 (CST->isAllOnesValue()))) { // X > -1
1454 // FIXME: This generated code sucks.
1455 ISD::CondCode LowCC;
1456 switch (cast<CondCodeSDNode>(Node->getOperand(2))->get()) {
1457 default: assert(0 && "Unknown integer setcc!");
1459 case ISD::SETULT: LowCC = ISD::SETULT; break;
1461 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
1463 case ISD::SETULE: LowCC = ISD::SETULE; break;
1465 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
1468 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
1469 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
1470 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
1472 // NOTE: on targets without efficient SELECT of bools, we can always use
1473 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
1474 Tmp1 = DAG.getSetCC(Node->getValueType(0), LHSLo, RHSLo, LowCC);
1475 Tmp2 = DAG.getNode(ISD::SETCC, Node->getValueType(0), LHSHi, RHSHi,
1476 Node->getOperand(2));
1477 Result = DAG.getSetCC(Node->getValueType(0), LHSHi, RHSHi, ISD::SETEQ);
1478 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
1479 Result, Tmp1, Tmp2));
1484 switch(TLI.getOperationAction(ISD::SETCC, Node->getOperand(0).getValueType())) {
1486 assert(0 && "Cannot handle this action for SETCC yet!");
1488 case TargetLowering::Promote: {
1489 // First step, figure out the appropriate operation to use.
1490 // Allow SETCC to not be supported for all legal data types
1491 // Mostly this targets FP
1492 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1493 MVT::ValueType OldVT = NewInTy;
1495 // Scan for the appropriate larger type to use.
1497 NewInTy = (MVT::ValueType)(NewInTy+1);
1499 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1500 "Fell off of the edge of the integer world");
1501 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1502 "Fell off of the edge of the floating point world");
1504 // If the target supports SETCC of this type, use it.
1505 if (TLI.getOperationAction(ISD::SETCC, NewInTy) == TargetLowering::Legal)
1508 if (MVT::isInteger(NewInTy))
1509 assert(0 && "Cannot promote Legal Integer SETCC yet");
1511 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1512 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1515 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1516 Node->getOperand(2));
1519 case TargetLowering::Legal:
1520 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1521 Result = DAG.getNode(ISD::SETCC, Node->getValueType(0), Tmp1, Tmp2,
1522 Node->getOperand(2));
1524 case TargetLowering::Expand:
1525 // Expand a setcc node into a select_cc of the same condition, lhs, and
1526 // rhs that selects between const 1 (true) and const 0 (false).
1527 MVT::ValueType VT = Node->getValueType(0);
1528 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1529 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1530 Node->getOperand(2));
1531 Result = LegalizeOp(Result);
1538 case ISD::MEMMOVE: {
1539 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1540 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1542 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1543 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1544 case Expand: assert(0 && "Cannot expand a byte!");
1546 Tmp3 = LegalizeOp(Node->getOperand(2));
1549 Tmp3 = PromoteOp(Node->getOperand(2));
1553 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1557 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1559 // Length is too big, just take the lo-part of the length.
1561 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1565 Tmp4 = LegalizeOp(Node->getOperand(3));
1568 Tmp4 = PromoteOp(Node->getOperand(3));
1573 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1574 case Expand: assert(0 && "Cannot expand this yet!");
1576 Tmp5 = LegalizeOp(Node->getOperand(4));
1579 Tmp5 = PromoteOp(Node->getOperand(4));
1583 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1584 default: assert(0 && "This action not implemented for this operation!");
1585 case TargetLowering::Custom: {
1587 TLI.LowerOperation(DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1,
1588 Tmp2, Tmp3, Tmp4, Tmp5), DAG);
1590 Result = LegalizeOp(Tmp);
1593 // FALLTHROUGH if the target thinks it is legal.
1595 case TargetLowering::Legal:
1596 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1597 Tmp3 != Node->getOperand(2) || Tmp4 != Node->getOperand(3) ||
1598 Tmp5 != Node->getOperand(4)) {
1599 std::vector<SDOperand> Ops;
1600 Ops.push_back(Tmp1); Ops.push_back(Tmp2); Ops.push_back(Tmp3);
1601 Ops.push_back(Tmp4); Ops.push_back(Tmp5);
1602 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Ops);
1605 case TargetLowering::Expand: {
1606 // Otherwise, the target does not support this operation. Lower the
1607 // operation to an explicit libcall as appropriate.
1608 MVT::ValueType IntPtr = TLI.getPointerTy();
1609 const Type *IntPtrTy = TLI.getTargetData().getIntPtrType();
1610 std::vector<std::pair<SDOperand, const Type*> > Args;
1612 const char *FnName = 0;
1613 if (Node->getOpcode() == ISD::MEMSET) {
1614 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1615 // Extend the ubyte argument to be an int value for the call.
1616 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
1617 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
1618 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1621 } else if (Node->getOpcode() == ISD::MEMCPY ||
1622 Node->getOpcode() == ISD::MEMMOVE) {
1623 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
1624 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
1625 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
1626 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
1628 assert(0 && "Unknown op!");
1631 std::pair<SDOperand,SDOperand> CallResult =
1632 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
1633 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
1634 Result = CallResult.second;
1635 NeedsAnotherIteration = true;
1643 Tmp1 = LegalizeOp(Node->getOperand(0));
1644 Tmp2 = LegalizeOp(Node->getOperand(1));
1646 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1647 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1648 std::vector<SDOperand> Ops;
1649 Ops.push_back(Tmp1);
1650 Ops.push_back(Tmp2);
1651 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1653 Result = SDOperand(Node, 0);
1654 // Since these produce two values, make sure to remember that we legalized
1656 AddLegalizedOperand(SDOperand(Node, 0), Result);
1657 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1658 return Result.getValue(Op.ResNo);
1659 case ISD::WRITEPORT:
1660 Tmp1 = LegalizeOp(Node->getOperand(0));
1661 Tmp2 = LegalizeOp(Node->getOperand(1));
1662 Tmp3 = LegalizeOp(Node->getOperand(2));
1663 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1664 Tmp3 != Node->getOperand(2))
1665 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1669 Tmp1 = LegalizeOp(Node->getOperand(0));
1670 Tmp2 = LegalizeOp(Node->getOperand(1));
1672 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1673 case TargetLowering::Custom:
1674 default: assert(0 && "This action not implemented for this operation!");
1675 case TargetLowering::Legal:
1676 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1)) {
1677 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1678 std::vector<SDOperand> Ops;
1679 Ops.push_back(Tmp1);
1680 Ops.push_back(Tmp2);
1681 Result = DAG.getNode(ISD::READPORT, VTs, Ops);
1683 Result = SDOperand(Node, 0);
1685 case TargetLowering::Expand:
1686 // Replace this with a load from memory.
1687 Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
1688 Node->getOperand(1), DAG.getSrcValue(NULL));
1689 Result = LegalizeOp(Result);
1693 // Since these produce two values, make sure to remember that we legalized
1695 AddLegalizedOperand(SDOperand(Node, 0), Result);
1696 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1697 return Result.getValue(Op.ResNo);
1700 Tmp1 = LegalizeOp(Node->getOperand(0));
1701 Tmp2 = LegalizeOp(Node->getOperand(1));
1702 Tmp3 = LegalizeOp(Node->getOperand(2));
1704 switch (TLI.getOperationAction(Node->getOpcode(),
1705 Node->getOperand(1).getValueType())) {
1706 case TargetLowering::Custom:
1707 default: assert(0 && "This action not implemented for this operation!");
1708 case TargetLowering::Legal:
1709 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1710 Tmp3 != Node->getOperand(2))
1711 Result = DAG.getNode(Node->getOpcode(), MVT::Other, Tmp1, Tmp2, Tmp3);
1713 case TargetLowering::Expand:
1714 // Replace this with a store to memory.
1715 Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
1716 Node->getOperand(1), Node->getOperand(2),
1717 DAG.getSrcValue(NULL));
1718 Result = LegalizeOp(Result);
1723 case ISD::ADD_PARTS:
1724 case ISD::SUB_PARTS:
1725 case ISD::SHL_PARTS:
1726 case ISD::SRA_PARTS:
1727 case ISD::SRL_PARTS: {
1728 std::vector<SDOperand> Ops;
1729 bool Changed = false;
1730 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1731 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1732 Changed |= Ops.back() != Node->getOperand(i);
1735 std::vector<MVT::ValueType> VTs(Node->value_begin(), Node->value_end());
1736 Result = DAG.getNode(Node->getOpcode(), VTs, Ops);
1739 // Since these produce multiple values, make sure to remember that we
1740 // legalized all of them.
1741 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1742 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
1743 return Result.getValue(Op.ResNo);
1764 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1765 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1766 case Expand: assert(0 && "Not possible");
1768 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
1771 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
1774 if (Tmp1 != Node->getOperand(0) ||
1775 Tmp2 != Node->getOperand(1))
1776 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
1779 case ISD::BUILD_PAIR: {
1780 MVT::ValueType PairTy = Node->getValueType(0);
1781 // TODO: handle the case where the Lo and Hi operands are not of legal type
1782 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
1783 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
1784 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
1785 case TargetLowering::Legal:
1786 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
1787 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
1789 case TargetLowering::Promote:
1790 case TargetLowering::Custom:
1791 assert(0 && "Cannot promote/custom this yet!");
1792 case TargetLowering::Expand:
1793 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
1794 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
1795 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
1796 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
1797 TLI.getShiftAmountTy()));
1798 Result = LegalizeOp(DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2));
1807 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
1808 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
1809 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1810 case TargetLowering::Legal:
1811 if (Tmp1 != Node->getOperand(0) ||
1812 Tmp2 != Node->getOperand(1))
1813 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
1816 case TargetLowering::Promote:
1817 case TargetLowering::Custom:
1818 assert(0 && "Cannot promote/custom handle this yet!");
1819 case TargetLowering::Expand:
1820 if (MVT::isInteger(Node->getValueType(0))) {
1821 MVT::ValueType VT = Node->getValueType(0);
1822 unsigned Opc = (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
1823 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
1824 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
1825 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
1827 // Floating point mod -> fmod libcall.
1828 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
1830 Result = ExpandLibCall(FnName, Node, Dummy);
1839 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
1840 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1841 case TargetLowering::Legal:
1842 if (Tmp1 != Node->getOperand(0))
1843 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1845 case TargetLowering::Promote: {
1846 MVT::ValueType OVT = Tmp1.getValueType();
1847 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1849 // Zero extend the argument.
1850 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
1851 // Perform the larger operation, then subtract if needed.
1852 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1853 switch(Node->getOpcode())
1859 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
1860 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
1861 DAG.getConstant(getSizeInBits(NVT), NVT),
1863 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
1864 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
1867 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
1868 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
1869 DAG.getConstant(getSizeInBits(NVT) -
1870 getSizeInBits(OVT), NVT));
1875 case TargetLowering::Custom:
1876 assert(0 && "Cannot custom handle this yet!");
1877 case TargetLowering::Expand:
1878 switch(Node->getOpcode())
1881 static const uint64_t mask[6] = {
1882 0x5555555555555555ULL, 0x3333333333333333ULL,
1883 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
1884 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
1886 MVT::ValueType VT = Tmp1.getValueType();
1887 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1888 unsigned len = getSizeInBits(VT);
1889 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1890 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
1891 Tmp2 = DAG.getConstant(mask[i], VT);
1892 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1893 Tmp1 = DAG.getNode(ISD::ADD, VT,
1894 DAG.getNode(ISD::AND, VT, Tmp1, Tmp2),
1895 DAG.getNode(ISD::AND, VT,
1896 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3),
1903 /* for now, we do this:
1908 x = x | (x >>32); // for 64-bit input
1909 return popcount(~x);
1911 but see also: http://www.hackersdelight.org/HDcode/nlz.cc */
1912 MVT::ValueType VT = Tmp1.getValueType();
1913 MVT::ValueType ShVT = TLI.getShiftAmountTy();
1914 unsigned len = getSizeInBits(VT);
1915 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
1916 Tmp3 = DAG.getConstant(1ULL << i, ShVT);
1917 Tmp1 = DAG.getNode(ISD::OR, VT, Tmp1,
1918 DAG.getNode(ISD::SRL, VT, Tmp1, Tmp3));
1920 Tmp3 = DAG.getNode(ISD::XOR, VT, Tmp1, DAG.getConstant(~0ULL, VT));
1921 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1925 // for now, we use: { return popcount(~x & (x - 1)); }
1926 // unless the target has ctlz but not ctpop, in which case we use:
1927 // { return 32 - nlz(~x & (x-1)); }
1928 // see also http://www.hackersdelight.org/HDcode/ntz.cc
1929 MVT::ValueType VT = Tmp1.getValueType();
1930 Tmp2 = DAG.getConstant(~0ULL, VT);
1931 Tmp3 = DAG.getNode(ISD::AND, VT,
1932 DAG.getNode(ISD::XOR, VT, Tmp1, Tmp2),
1933 DAG.getNode(ISD::SUB, VT, Tmp1,
1934 DAG.getConstant(1, VT)));
1935 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead
1936 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
1937 TLI.isOperationLegal(ISD::CTLZ, VT)) {
1938 Result = LegalizeOp(DAG.getNode(ISD::SUB, VT,
1939 DAG.getConstant(getSizeInBits(VT), VT),
1940 DAG.getNode(ISD::CTLZ, VT, Tmp3)));
1942 Result = LegalizeOp(DAG.getNode(ISD::CTPOP, VT, Tmp3));
1947 assert(0 && "Cannot expand this yet!");
1960 Tmp1 = LegalizeOp(Node->getOperand(0));
1961 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1962 case TargetLowering::Legal:
1963 if (Tmp1 != Node->getOperand(0))
1964 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
1966 case TargetLowering::Promote:
1967 case TargetLowering::Custom:
1968 assert(0 && "Cannot promote/custom handle this yet!");
1969 case TargetLowering::Expand:
1970 switch(Node->getOpcode()) {
1972 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
1973 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
1974 Result = LegalizeOp(DAG.getNode(ISD::FSUB, Node->getValueType(0),
1979 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
1980 MVT::ValueType VT = Node->getValueType(0);
1981 Tmp2 = DAG.getConstantFP(0.0, VT);
1982 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
1983 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
1984 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
1985 Result = LegalizeOp(Result);
1991 MVT::ValueType VT = Node->getValueType(0);
1992 const char *FnName = 0;
1993 switch(Node->getOpcode()) {
1994 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
1995 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
1996 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
1997 default: assert(0 && "Unreachable!");
2000 Result = ExpandLibCall(FnName, Node, Dummy);
2004 assert(0 && "Unreachable!");
2010 // Conversion operators. The source and destination have different types.
2011 case ISD::SINT_TO_FP:
2012 case ISD::UINT_TO_FP: {
2013 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2014 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2016 switch (TLI.getOperationAction(Node->getOpcode(),
2017 Node->getOperand(0).getValueType())) {
2018 default: assert(0 && "Unknown operation action!");
2019 case TargetLowering::Expand:
2020 Result = ExpandLegalINT_TO_FP(isSigned,
2021 LegalizeOp(Node->getOperand(0)),
2022 Node->getValueType(0));
2023 AddLegalizedOperand(Op, Result);
2025 case TargetLowering::Promote:
2026 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2027 Node->getValueType(0),
2029 AddLegalizedOperand(Op, Result);
2031 case TargetLowering::Legal:
2033 case TargetLowering::Custom: {
2034 Tmp1 = LegalizeOp(Node->getOperand(0));
2036 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2037 Tmp = TLI.LowerOperation(Tmp, DAG);
2039 AddLegalizedOperand(Op, Tmp);
2040 NeedsAnotherIteration = true;
2043 assert(0 && "Target Must Lower this");
2048 Tmp1 = LegalizeOp(Node->getOperand(0));
2049 if (Tmp1 != Node->getOperand(0))
2050 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2053 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2054 Node->getValueType(0), Node->getOperand(0));
2058 Result = PromoteOp(Node->getOperand(0));
2059 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2060 Result, DAG.getValueType(Node->getOperand(0).getValueType()));
2061 Result = DAG.getNode(ISD::SINT_TO_FP, Op.getValueType(), Result);
2063 Result = PromoteOp(Node->getOperand(0));
2064 Result = DAG.getZeroExtendInReg(Result,
2065 Node->getOperand(0).getValueType());
2066 Result = DAG.getNode(ISD::UINT_TO_FP, Op.getValueType(), Result);
2073 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2075 Tmp1 = LegalizeOp(Node->getOperand(0));
2076 if (Tmp1 != Node->getOperand(0))
2077 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2080 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2082 // Since the result is legal, we should just be able to truncate the low
2083 // part of the source.
2084 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2087 Result = PromoteOp(Node->getOperand(0));
2088 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2093 case ISD::FP_TO_SINT:
2094 case ISD::FP_TO_UINT:
2095 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2097 Tmp1 = LegalizeOp(Node->getOperand(0));
2099 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2100 default: assert(0 && "Unknown operation action!");
2101 case TargetLowering::Expand:
2102 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2103 SDOperand True, False;
2104 MVT::ValueType VT = Node->getOperand(0).getValueType();
2105 MVT::ValueType NVT = Node->getValueType(0);
2106 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2107 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2108 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2109 Node->getOperand(0), Tmp2, ISD::SETLT);
2110 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2111 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2112 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2114 False = DAG.getNode(ISD::XOR, NVT, False,
2115 DAG.getConstant(1ULL << ShiftAmt, NVT));
2116 Result = LegalizeOp(DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False));
2119 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2122 case TargetLowering::Promote:
2123 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2124 Node->getOpcode() == ISD::FP_TO_SINT);
2125 AddLegalizedOperand(Op, Result);
2127 case TargetLowering::Custom: {
2129 DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2130 Tmp = TLI.LowerOperation(Tmp, DAG);
2132 AddLegalizedOperand(Op, Tmp);
2133 NeedsAnotherIteration = true;
2136 // The target thinks this is legal afterall.
2140 case TargetLowering::Legal:
2144 if (Tmp1 != Node->getOperand(0))
2145 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2148 assert(0 && "Shouldn't need to expand other operators here!");
2150 Result = PromoteOp(Node->getOperand(0));
2151 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2156 case ISD::ANY_EXTEND:
2157 case ISD::ZERO_EXTEND:
2158 case ISD::SIGN_EXTEND:
2159 case ISD::FP_EXTEND:
2161 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2163 Tmp1 = LegalizeOp(Node->getOperand(0));
2164 if (Tmp1 != Node->getOperand(0))
2165 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2168 assert(0 && "Shouldn't need to expand other operators here!");
2171 switch (Node->getOpcode()) {
2172 case ISD::ANY_EXTEND:
2173 Result = PromoteOp(Node->getOperand(0));
2174 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2176 case ISD::ZERO_EXTEND:
2177 Result = PromoteOp(Node->getOperand(0));
2178 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2179 Result = DAG.getZeroExtendInReg(Result,
2180 Node->getOperand(0).getValueType());
2182 case ISD::SIGN_EXTEND:
2183 Result = PromoteOp(Node->getOperand(0));
2184 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2185 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2187 DAG.getValueType(Node->getOperand(0).getValueType()));
2189 case ISD::FP_EXTEND:
2190 Result = PromoteOp(Node->getOperand(0));
2191 if (Result.getValueType() != Op.getValueType())
2192 // Dynamically dead while we have only 2 FP types.
2193 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2196 Result = PromoteOp(Node->getOperand(0));
2197 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2202 case ISD::FP_ROUND_INREG:
2203 case ISD::SIGN_EXTEND_INREG: {
2204 Tmp1 = LegalizeOp(Node->getOperand(0));
2205 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2207 // If this operation is not supported, convert it to a shl/shr or load/store
2209 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2210 default: assert(0 && "This action not supported for this op yet!");
2211 case TargetLowering::Legal:
2212 if (Tmp1 != Node->getOperand(0))
2213 Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
2214 DAG.getValueType(ExtraVT));
2216 case TargetLowering::Expand:
2217 // If this is an integer extend and shifts are supported, do that.
2218 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2219 // NOTE: we could fall back on load/store here too for targets without
2220 // SAR. However, it is doubtful that any exist.
2221 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2222 MVT::getSizeInBits(ExtraVT);
2223 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2224 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2225 Node->getOperand(0), ShiftCst);
2226 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2228 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2229 // The only way we can lower this is to turn it into a STORETRUNC,
2230 // EXTLOAD pair, targetting a temporary location (a stack slot).
2232 // NOTE: there is a choice here between constantly creating new stack
2233 // slots and always reusing the same one. We currently always create
2234 // new ones, as reuse may inhibit scheduling.
2235 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2236 unsigned TySize = (unsigned)TLI.getTargetData().getTypeSize(Ty);
2237 unsigned Align = TLI.getTargetData().getTypeAlignment(Ty);
2238 MachineFunction &MF = DAG.getMachineFunction();
2240 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2241 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2242 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2243 Node->getOperand(0), StackSlot,
2244 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2245 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2246 Result, StackSlot, DAG.getSrcValue(NULL),
2249 assert(0 && "Unknown op");
2251 Result = LegalizeOp(Result);
2258 // Note that LegalizeOp may be reentered even from single-use nodes, which
2259 // means that we always must cache transformed nodes.
2260 AddLegalizedOperand(Op, Result);
2264 /// PromoteOp - Given an operation that produces a value in an invalid type,
2265 /// promote it to compute the value into a larger type. The produced value will
2266 /// have the correct bits for the low portion of the register, but no guarantee
2267 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2268 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2269 MVT::ValueType VT = Op.getValueType();
2270 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2271 assert(getTypeAction(VT) == Promote &&
2272 "Caller should expand or legalize operands that are not promotable!");
2273 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2274 "Cannot promote to smaller type!");
2276 SDOperand Tmp1, Tmp2, Tmp3;
2279 SDNode *Node = Op.Val;
2281 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2282 if (I != PromotedNodes.end()) return I->second;
2284 // Promotion needs an optimization step to clean up after it, and is not
2285 // careful to avoid operations the target does not support. Make sure that
2286 // all generated operations are legalized in the next iteration.
2287 NeedsAnotherIteration = true;
2289 switch (Node->getOpcode()) {
2290 case ISD::CopyFromReg:
2291 assert(0 && "CopyFromReg must be legal!");
2293 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2294 assert(0 && "Do not know how to promote this operator!");
2297 Result = DAG.getNode(ISD::UNDEF, NVT);
2301 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2303 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2304 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2306 case ISD::ConstantFP:
2307 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2308 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2312 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2313 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2314 Node->getOperand(1), Node->getOperand(2));
2315 Result = LegalizeOp(Result);
2319 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2321 Result = LegalizeOp(Node->getOperand(0));
2322 assert(Result.getValueType() >= NVT &&
2323 "This truncation doesn't make sense!");
2324 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2325 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2328 // The truncation is not required, because we don't guarantee anything
2329 // about high bits anyway.
2330 Result = PromoteOp(Node->getOperand(0));
2333 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2334 // Truncate the low part of the expanded value to the result type
2335 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2338 case ISD::SIGN_EXTEND:
2339 case ISD::ZERO_EXTEND:
2340 case ISD::ANY_EXTEND:
2341 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2342 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2344 // Input is legal? Just do extend all the way to the larger type.
2345 Result = LegalizeOp(Node->getOperand(0));
2346 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2349 // Promote the reg if it's smaller.
2350 Result = PromoteOp(Node->getOperand(0));
2351 // The high bits are not guaranteed to be anything. Insert an extend.
2352 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2353 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2354 DAG.getValueType(Node->getOperand(0).getValueType()));
2355 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2356 Result = DAG.getZeroExtendInReg(Result,
2357 Node->getOperand(0).getValueType());
2362 case ISD::FP_EXTEND:
2363 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2365 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2366 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2367 case Promote: assert(0 && "Unreachable with 2 FP types!");
2369 // Input is legal? Do an FP_ROUND_INREG.
2370 Result = LegalizeOp(Node->getOperand(0));
2371 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2372 DAG.getValueType(VT));
2377 case ISD::SINT_TO_FP:
2378 case ISD::UINT_TO_FP:
2379 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2381 Result = LegalizeOp(Node->getOperand(0));
2382 // No extra round required here.
2383 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2387 Result = PromoteOp(Node->getOperand(0));
2388 if (Node->getOpcode() == ISD::SINT_TO_FP)
2389 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2391 DAG.getValueType(Node->getOperand(0).getValueType()));
2393 Result = DAG.getZeroExtendInReg(Result,
2394 Node->getOperand(0).getValueType());
2395 // No extra round required here.
2396 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2399 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2400 Node->getOperand(0));
2401 // Round if we cannot tolerate excess precision.
2402 if (NoExcessFPPrecision)
2403 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2404 DAG.getValueType(VT));
2409 case ISD::SIGN_EXTEND_INREG:
2410 Result = PromoteOp(Node->getOperand(0));
2411 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2412 Node->getOperand(1));
2414 case ISD::FP_TO_SINT:
2415 case ISD::FP_TO_UINT:
2416 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2418 Tmp1 = LegalizeOp(Node->getOperand(0));
2421 // The input result is prerounded, so we don't have to do anything
2423 Tmp1 = PromoteOp(Node->getOperand(0));
2426 assert(0 && "not implemented");
2428 // If we're promoting a UINT to a larger size, check to see if the new node
2429 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2430 // we can use that instead. This allows us to generate better code for
2431 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2432 // legal, such as PowerPC.
2433 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2434 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2435 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2436 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2437 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2439 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2445 Tmp1 = PromoteOp(Node->getOperand(0));
2446 assert(Tmp1.getValueType() == NVT);
2447 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2448 // NOTE: we do not have to do any extra rounding here for
2449 // NoExcessFPPrecision, because we know the input will have the appropriate
2450 // precision, and these operations don't modify precision at all.
2456 Tmp1 = PromoteOp(Node->getOperand(0));
2457 assert(Tmp1.getValueType() == NVT);
2458 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2459 if(NoExcessFPPrecision)
2460 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2461 DAG.getValueType(VT));
2470 // The input may have strange things in the top bits of the registers, but
2471 // these operations don't care. They may have weird bits going out, but
2472 // that too is okay if they are integer operations.
2473 Tmp1 = PromoteOp(Node->getOperand(0));
2474 Tmp2 = PromoteOp(Node->getOperand(1));
2475 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2476 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2481 // The input may have strange things in the top bits of the registers, but
2482 // these operations don't care.
2483 Tmp1 = PromoteOp(Node->getOperand(0));
2484 Tmp2 = PromoteOp(Node->getOperand(1));
2485 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
2486 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2488 // Floating point operations will give excess precision that we may not be
2489 // able to tolerate. If we DO allow excess precision, just leave it,
2490 // otherwise excise it.
2491 // FIXME: Why would we need to round FP ops more than integer ones?
2492 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
2493 if (NoExcessFPPrecision)
2494 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2495 DAG.getValueType(VT));
2500 // These operators require that their input be sign extended.
2501 Tmp1 = PromoteOp(Node->getOperand(0));
2502 Tmp2 = PromoteOp(Node->getOperand(1));
2503 if (MVT::isInteger(NVT)) {
2504 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2505 DAG.getValueType(VT));
2506 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
2507 DAG.getValueType(VT));
2509 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2511 // Perform FP_ROUND: this is probably overly pessimistic.
2512 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
2513 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2514 DAG.getValueType(VT));
2518 // These operators require that their input be fp extended.
2519 Tmp1 = PromoteOp(Node->getOperand(0));
2520 Tmp2 = PromoteOp(Node->getOperand(1));
2521 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2523 // Perform FP_ROUND: this is probably overly pessimistic.
2524 if (NoExcessFPPrecision)
2525 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2526 DAG.getValueType(VT));
2531 // These operators require that their input be zero extended.
2532 Tmp1 = PromoteOp(Node->getOperand(0));
2533 Tmp2 = PromoteOp(Node->getOperand(1));
2534 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
2535 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2536 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
2537 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2541 Tmp1 = PromoteOp(Node->getOperand(0));
2542 Tmp2 = LegalizeOp(Node->getOperand(1));
2543 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Tmp2);
2546 // The input value must be properly sign extended.
2547 Tmp1 = PromoteOp(Node->getOperand(0));
2548 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
2549 DAG.getValueType(VT));
2550 Tmp2 = LegalizeOp(Node->getOperand(1));
2551 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Tmp2);
2554 // The input value must be properly zero extended.
2555 Tmp1 = PromoteOp(Node->getOperand(0));
2556 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
2557 Tmp2 = LegalizeOp(Node->getOperand(1));
2558 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Tmp2);
2561 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2562 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2563 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
2564 Node->getOperand(2), VT);
2565 // Remember that we legalized the chain.
2566 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2571 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2572 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2573 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Tmp1, Tmp2,
2574 Node->getOperand(2),
2575 cast<VTSDNode>(Node->getOperand(3))->getVT());
2576 // Remember that we legalized the chain.
2577 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2580 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2581 case Expand: assert(0 && "It's impossible to expand bools");
2583 Tmp1 = LegalizeOp(Node->getOperand(0));// Legalize the condition.
2586 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2589 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
2590 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
2591 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2, Tmp3);
2593 case ISD::SELECT_CC:
2594 Tmp2 = PromoteOp(Node->getOperand(2)); // True
2595 Tmp3 = PromoteOp(Node->getOperand(3)); // False
2596 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
2597 Node->getOperand(1), Tmp2, Tmp3,
2598 Node->getOperand(4));
2602 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2603 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
2605 std::vector<SDOperand> Ops;
2606 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i)
2607 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2609 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
2610 "Can only promote single result calls");
2611 std::vector<MVT::ValueType> RetTyVTs;
2612 RetTyVTs.reserve(2);
2613 RetTyVTs.push_back(NVT);
2614 RetTyVTs.push_back(MVT::Other);
2615 SDNode *NC = DAG.getCall(RetTyVTs, Tmp1, Tmp2, Ops,
2616 Node->getOpcode() == ISD::TAILCALL);
2617 Result = SDOperand(NC, 0);
2619 // Insert the new chain mapping.
2620 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
2626 Tmp1 = Node->getOperand(0);
2627 //Zero extend the argument
2628 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2629 // Perform the larger operation, then subtract if needed.
2630 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2631 switch(Node->getOpcode())
2637 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2638 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2639 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
2640 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2641 DAG.getConstant(getSizeInBits(VT),NVT), Tmp1);
2644 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2645 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2646 DAG.getConstant(getSizeInBits(NVT) -
2647 getSizeInBits(VT), NVT));
2653 assert(Result.Val && "Didn't set a result!");
2654 AddPromotedOperand(Op, Result);
2658 /// ExpandAddSub - Find a clever way to expand this add operation into
2660 void SelectionDAGLegalize::
2661 ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
2662 SDOperand &Lo, SDOperand &Hi) {
2663 // Expand the subcomponents.
2664 SDOperand LHSL, LHSH, RHSL, RHSH;
2665 ExpandOp(LHS, LHSL, LHSH);
2666 ExpandOp(RHS, RHSL, RHSH);
2668 std::vector<SDOperand> Ops;
2669 Ops.push_back(LHSL);
2670 Ops.push_back(LHSH);
2671 Ops.push_back(RHSL);
2672 Ops.push_back(RHSH);
2673 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2674 Lo = DAG.getNode(NodeOp, VTs, Ops);
2675 Hi = Lo.getValue(1);
2678 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
2679 SDOperand Op, SDOperand Amt,
2680 SDOperand &Lo, SDOperand &Hi) {
2681 // Expand the subcomponents.
2682 SDOperand LHSL, LHSH;
2683 ExpandOp(Op, LHSL, LHSH);
2685 std::vector<SDOperand> Ops;
2686 Ops.push_back(LHSL);
2687 Ops.push_back(LHSH);
2689 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
2690 Lo = DAG.getNode(NodeOp, VTs, Ops);
2691 Hi = Lo.getValue(1);
2695 /// ExpandShift - Try to find a clever way to expand this shift operation out to
2696 /// smaller elements. If we can't find a way that is more efficient than a
2697 /// libcall on this target, return false. Otherwise, return true with the
2698 /// low-parts expanded into Lo and Hi.
2699 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
2700 SDOperand &Lo, SDOperand &Hi) {
2701 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
2702 "This is not a shift!");
2704 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
2705 SDOperand ShAmt = LegalizeOp(Amt);
2706 MVT::ValueType ShTy = ShAmt.getValueType();
2707 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
2708 unsigned NVTBits = MVT::getSizeInBits(NVT);
2710 // Handle the case when Amt is an immediate. Other cases are currently broken
2711 // and are disabled.
2712 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
2713 unsigned Cst = CN->getValue();
2714 // Expand the incoming operand to be shifted, so that we have its parts
2716 ExpandOp(Op, InL, InH);
2720 Lo = DAG.getConstant(0, NVT);
2721 Hi = DAG.getConstant(0, NVT);
2722 } else if (Cst > NVTBits) {
2723 Lo = DAG.getConstant(0, NVT);
2724 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
2725 } else if (Cst == NVTBits) {
2726 Lo = DAG.getConstant(0, NVT);
2729 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
2730 Hi = DAG.getNode(ISD::OR, NVT,
2731 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
2732 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
2737 Lo = DAG.getConstant(0, NVT);
2738 Hi = DAG.getConstant(0, NVT);
2739 } else if (Cst > NVTBits) {
2740 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
2741 Hi = DAG.getConstant(0, NVT);
2742 } else if (Cst == NVTBits) {
2744 Hi = DAG.getConstant(0, NVT);
2746 Lo = DAG.getNode(ISD::OR, NVT,
2747 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2748 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2749 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
2754 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
2755 DAG.getConstant(NVTBits-1, ShTy));
2756 } else if (Cst > NVTBits) {
2757 Lo = DAG.getNode(ISD::SRA, NVT, InH,
2758 DAG.getConstant(Cst-NVTBits, ShTy));
2759 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2760 DAG.getConstant(NVTBits-1, ShTy));
2761 } else if (Cst == NVTBits) {
2763 Hi = DAG.getNode(ISD::SRA, NVT, InH,
2764 DAG.getConstant(NVTBits-1, ShTy));
2766 Lo = DAG.getNode(ISD::OR, NVT,
2767 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
2768 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
2769 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
2774 // FIXME: The following code for expanding shifts using ISD::SELECT is buggy,
2775 // so disable it for now. Currently targets are handling this via SHL_PARTS
2779 // If we have an efficient select operation (or if the selects will all fold
2780 // away), lower to some complex code, otherwise just emit the libcall.
2781 if (!TLI.isOperationLegal(ISD::SELECT, NVT) && !isa<ConstantSDNode>(Amt))
2785 ExpandOp(Op, InL, InH);
2786 SDOperand NAmt = DAG.getNode(ISD::SUB, ShTy, // NAmt = 32-ShAmt
2787 DAG.getConstant(NVTBits, ShTy), ShAmt);
2789 // Compare the unmasked shift amount against 32.
2790 SDOperand Cond = DAG.getSetCC(TLI.getSetCCResultTy(), ShAmt,
2791 DAG.getConstant(NVTBits, ShTy), ISD::SETGE);
2793 if (TLI.getShiftAmountFlavor() != TargetLowering::Mask) {
2794 ShAmt = DAG.getNode(ISD::AND, ShTy, ShAmt, // ShAmt &= 31
2795 DAG.getConstant(NVTBits-1, ShTy));
2796 NAmt = DAG.getNode(ISD::AND, ShTy, NAmt, // NAmt &= 31
2797 DAG.getConstant(NVTBits-1, ShTy));
2800 if (Opc == ISD::SHL) {
2801 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << Amt) | (Lo >> NAmt)
2802 DAG.getNode(ISD::SHL, NVT, InH, ShAmt),
2803 DAG.getNode(ISD::SRL, NVT, InL, NAmt));
2804 SDOperand T2 = DAG.getNode(ISD::SHL, NVT, InL, ShAmt); // T2 = Lo << Amt&31
2806 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2807 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, DAG.getConstant(0, NVT), T2);
2809 SDOperand HiLoPart = DAG.getNode(ISD::SELECT, NVT,
2810 DAG.getSetCC(TLI.getSetCCResultTy(), NAmt,
2811 DAG.getConstant(32, ShTy),
2813 DAG.getConstant(0, NVT),
2814 DAG.getNode(ISD::SHL, NVT, InH, NAmt));
2815 SDOperand T1 = DAG.getNode(ISD::OR, NVT,// T1 = (Hi << NAmt) | (Lo >> Amt)
2817 DAG.getNode(ISD::SRL, NVT, InL, ShAmt));
2818 SDOperand T2 = DAG.getNode(Opc, NVT, InH, ShAmt); // T2 = InH >> ShAmt&31
2821 if (Opc == ISD::SRA)
2822 HiPart = DAG.getNode(ISD::SRA, NVT, InH,
2823 DAG.getConstant(NVTBits-1, ShTy));
2825 HiPart = DAG.getConstant(0, NVT);
2826 Lo = DAG.getNode(ISD::SELECT, NVT, Cond, T2, T1);
2827 Hi = DAG.getNode(ISD::SELECT, NVT, Cond, HiPart, T2);
2832 /// FindLatestCallSeqStart - Scan up the dag to find the latest (highest
2833 /// NodeDepth) node that is an CallSeqStart operation and occurs later than
2835 static void FindLatestCallSeqStart(SDNode *Node, SDNode *&Found) {
2836 if (Node->getNodeDepth() <= Found->getNodeDepth()) return;
2838 // If we found an CALLSEQ_START, we already know this node occurs later
2839 // than the Found node. Just remember this node and return.
2840 if (Node->getOpcode() == ISD::CALLSEQ_START) {
2845 // Otherwise, scan the operands of Node to see if any of them is a call.
2846 assert(Node->getNumOperands() != 0 &&
2847 "All leaves should have depth equal to the entry node!");
2848 for (unsigned i = 0, e = Node->getNumOperands()-1; i != e; ++i)
2849 FindLatestCallSeqStart(Node->getOperand(i).Val, Found);
2851 // Tail recurse for the last iteration.
2852 FindLatestCallSeqStart(Node->getOperand(Node->getNumOperands()-1).Val,
2857 /// FindEarliestCallSeqEnd - Scan down the dag to find the earliest (lowest
2858 /// NodeDepth) node that is an CallSeqEnd operation and occurs more recent
2860 static void FindEarliestCallSeqEnd(SDNode *Node, SDNode *&Found,
2861 std::set<SDNode*> &Visited) {
2862 if ((Found && Node->getNodeDepth() >= Found->getNodeDepth()) ||
2863 !Visited.insert(Node).second) return;
2865 // If we found an CALLSEQ_END, we already know this node occurs earlier
2866 // than the Found node. Just remember this node and return.
2867 if (Node->getOpcode() == ISD::CALLSEQ_END) {
2872 // Otherwise, scan the operands of Node to see if any of them is a call.
2873 SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
2874 if (UI == E) return;
2875 for (--E; UI != E; ++UI)
2876 FindEarliestCallSeqEnd(*UI, Found, Visited);
2878 // Tail recurse for the last iteration.
2879 FindEarliestCallSeqEnd(*UI, Found, Visited);
2882 /// FindCallSeqEnd - Given a chained node that is part of a call sequence,
2883 /// find the CALLSEQ_END node that terminates the call sequence.
2884 static SDNode *FindCallSeqEnd(SDNode *Node) {
2885 if (Node->getOpcode() == ISD::CALLSEQ_END)
2887 if (Node->use_empty())
2888 return 0; // No CallSeqEnd
2890 SDOperand TheChain(Node, Node->getNumValues()-1);
2891 if (TheChain.getValueType() != MVT::Other)
2892 TheChain = SDOperand(Node, 0);
2893 if (TheChain.getValueType() != MVT::Other)
2896 for (SDNode::use_iterator UI = Node->use_begin(),
2897 E = Node->use_end(); UI != E; ++UI) {
2899 // Make sure to only follow users of our token chain.
2901 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
2902 if (User->getOperand(i) == TheChain)
2903 if (SDNode *Result = FindCallSeqEnd(User))
2909 /// FindCallSeqStart - Given a chained node that is part of a call sequence,
2910 /// find the CALLSEQ_START node that initiates the call sequence.
2911 static SDNode *FindCallSeqStart(SDNode *Node) {
2912 assert(Node && "Didn't find callseq_start for a call??");
2913 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
2915 assert(Node->getOperand(0).getValueType() == MVT::Other &&
2916 "Node doesn't have a token chain argument!");
2917 return FindCallSeqStart(Node->getOperand(0).Val);
2921 /// FindInputOutputChains - If we are replacing an operation with a call we need
2922 /// to find the call that occurs before and the call that occurs after it to
2923 /// properly serialize the calls in the block. The returned operand is the
2924 /// input chain value for the new call (e.g. the entry node or the previous
2925 /// call), and OutChain is set to be the chain node to update to point to the
2926 /// end of the call chain.
2927 static SDOperand FindInputOutputChains(SDNode *OpNode, SDNode *&OutChain,
2929 SDNode *LatestCallSeqStart = Entry.Val;
2930 SDNode *LatestCallSeqEnd = 0;
2931 FindLatestCallSeqStart(OpNode, LatestCallSeqStart);
2932 //std::cerr<<"Found node: "; LatestCallSeqStart->dump(); std::cerr <<"\n";
2934 // It is possible that no ISD::CALLSEQ_START was found because there is no
2935 // previous call in the function. LatestCallStackDown may in that case be
2936 // the entry node itself. Do not attempt to find a matching CALLSEQ_END
2937 // unless LatestCallStackDown is an CALLSEQ_START.
2938 if (LatestCallSeqStart->getOpcode() == ISD::CALLSEQ_START) {
2939 LatestCallSeqEnd = FindCallSeqEnd(LatestCallSeqStart);
2940 //std::cerr<<"Found end node: "; LatestCallSeqEnd->dump(); std::cerr <<"\n";
2942 LatestCallSeqEnd = Entry.Val;
2944 assert(LatestCallSeqEnd && "NULL return from FindCallSeqEnd");
2946 // Finally, find the first call that this must come before, first we find the
2947 // CallSeqEnd that ends the call.
2949 std::set<SDNode*> Visited;
2950 FindEarliestCallSeqEnd(OpNode, OutChain, Visited);
2952 // If we found one, translate from the adj up to the callseq_start.
2954 OutChain = FindCallSeqStart(OutChain);
2956 return SDOperand(LatestCallSeqEnd, 0);
2959 /// SpliceCallInto - Given the result chain of a libcall (CallResult), and a
2960 void SelectionDAGLegalize::SpliceCallInto(const SDOperand &CallResult,
2962 // Nothing to splice it into?
2963 if (OutChain == 0) return;
2965 assert(OutChain->getOperand(0).getValueType() == MVT::Other);
2968 // Form a token factor node merging the old inval and the new inval.
2969 SDOperand InToken = DAG.getNode(ISD::TokenFactor, MVT::Other, CallResult,
2970 OutChain->getOperand(0));
2971 // Change the node to refer to the new token.
2972 OutChain->setAdjCallChain(InToken);
2976 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2977 // does not fit into a register, return the lo part and set the hi part to the
2978 // by-reg argument. If it does fit into a single register, return the result
2979 // and leave the Hi part unset.
2980 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
2983 SDOperand InChain = FindInputOutputChains(Node, OutChain,
2984 DAG.getEntryNode());
2985 if (InChain.Val == 0)
2986 InChain = DAG.getEntryNode();
2988 TargetLowering::ArgListTy Args;
2989 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2990 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
2991 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
2992 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
2994 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
2996 // Splice the libcall in wherever FindInputOutputChains tells us to.
2997 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
2998 std::pair<SDOperand,SDOperand> CallInfo =
2999 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3003 switch (getTypeAction(CallInfo.first.getValueType())) {
3004 default: assert(0 && "Unknown thing");
3006 Result = CallInfo.first;
3009 assert(0 && "Cannot promote this yet!");
3011 ExpandOp(CallInfo.first, Result, Hi);
3012 CallInfo.second = LegalizeOp(CallInfo.second);
3016 SpliceCallInto(CallInfo.second, OutChain);
3017 NeedsAnotherIteration = true;
3022 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3023 /// destination type is legal.
3024 SDOperand SelectionDAGLegalize::
3025 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3026 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3027 assert(getTypeAction(Source.getValueType()) == Expand &&
3028 "This is not an expansion!");
3029 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3032 assert(Source.getValueType() == MVT::i64 &&
3033 "This only works for 64-bit -> FP");
3034 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3035 // incoming integer is set. To handle this, we dynamically test to see if
3036 // it is set, and, if so, add a fudge factor.
3038 ExpandOp(Source, Lo, Hi);
3040 // If this is unsigned, and not supported, first perform the conversion to
3041 // signed, then adjust the result if the sign bit is set.
3042 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3043 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3045 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3046 DAG.getConstant(0, Hi.getValueType()),
3048 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3049 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3050 SignSet, Four, Zero);
3051 uint64_t FF = 0x5f800000ULL;
3052 if (TLI.isLittleEndian()) FF <<= 32;
3053 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3055 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3056 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3057 SDOperand FudgeInReg;
3058 if (DestTy == MVT::f32)
3059 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3060 DAG.getSrcValue(NULL));
3062 assert(DestTy == MVT::f64 && "Unexpected conversion");
3063 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3064 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3066 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3069 // Check to see if the target has a custom way to lower this. If so, use it.
3070 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3071 default: assert(0 && "This action not implemented for this operation!");
3072 case TargetLowering::Legal:
3073 case TargetLowering::Expand:
3074 break; // This case is handled below.
3075 case TargetLowering::Custom: {
3076 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3079 return LegalizeOp(NV);
3080 break; // The target decided this was legal after all
3084 // Expand the source, then glue it back together for the call. We must expand
3085 // the source in case it is shared (this pass of legalize must traverse it).
3086 SDOperand SrcLo, SrcHi;
3087 ExpandOp(Source, SrcLo, SrcHi);
3088 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3090 SDNode *OutChain = 0;
3091 SDOperand InChain = FindInputOutputChains(Source.Val, OutChain,
3092 DAG.getEntryNode());
3093 const char *FnName = 0;
3094 if (DestTy == MVT::f32)
3095 FnName = "__floatdisf";
3097 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3098 FnName = "__floatdidf";
3101 SDOperand Callee = DAG.getExternalSymbol(FnName, TLI.getPointerTy());
3103 TargetLowering::ArgListTy Args;
3104 const Type *ArgTy = MVT::getTypeForValueType(Source.getValueType());
3106 Args.push_back(std::make_pair(Source, ArgTy));
3108 // We don't care about token chains for libcalls. We just use the entry
3109 // node as our input and ignore the output chain. This allows us to place
3110 // calls wherever we need them to satisfy data dependences.
3111 const Type *RetTy = MVT::getTypeForValueType(DestTy);
3113 std::pair<SDOperand,SDOperand> CallResult =
3114 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, true,
3117 SpliceCallInto(CallResult.second, OutChain);
3118 return CallResult.first;
3123 /// ExpandOp - Expand the specified SDOperand into its two component pieces
3124 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
3125 /// LegalizeNodes map is filled in for any results that are not expanded, the
3126 /// ExpandedNodes map is filled in for any results that are expanded, and the
3127 /// Lo/Hi values are returned.
3128 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
3129 MVT::ValueType VT = Op.getValueType();
3130 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3131 SDNode *Node = Op.Val;
3132 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
3133 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
3134 "Cannot expand FP values!");
3135 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
3136 "Cannot expand to FP value or to larger int value!");
3138 // See if we already expanded it.
3139 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
3140 = ExpandedNodes.find(Op);
3141 if (I != ExpandedNodes.end()) {
3142 Lo = I->second.first;
3143 Hi = I->second.second;
3147 // Expanding to multiple registers needs to perform an optimization step, and
3148 // is not careful to avoid operations the target does not support. Make sure
3149 // that all generated operations are legalized in the next iteration.
3150 NeedsAnotherIteration = true;
3152 switch (Node->getOpcode()) {
3153 case ISD::CopyFromReg:
3154 assert(0 && "CopyFromReg must be legal!");
3156 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
3157 assert(0 && "Do not know how to expand this operator!");
3160 Lo = DAG.getNode(ISD::UNDEF, NVT);
3161 Hi = DAG.getNode(ISD::UNDEF, NVT);
3163 case ISD::Constant: {
3164 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
3165 Lo = DAG.getConstant(Cst, NVT);
3166 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
3169 case ISD::ConstantVec: {
3170 unsigned NumElements = Node->getNumOperands();
3171 // If we only have two elements left in the constant vector, just break it
3172 // apart into the two scalar constants it contains. Otherwise, bisect the
3173 // ConstantVec, and return each half as a new ConstantVec.
3174 // FIXME: this is hard coded as big endian, it may have to change to support
3175 // SSE and Alpha MVI
3176 if (NumElements == 2) {
3177 Hi = Node->getOperand(0);
3178 Lo = Node->getOperand(1);
3181 std::vector<SDOperand> LoOps, HiOps;
3182 for (unsigned I = 0, E = NumElements; I < E; ++I) {
3183 HiOps.push_back(Node->getOperand(I));
3184 LoOps.push_back(Node->getOperand(I+NumElements));
3186 Lo = DAG.getNode(ISD::ConstantVec, MVT::Vector, LoOps);
3187 Hi = DAG.getNode(ISD::ConstantVec, MVT::Vector, HiOps);
3192 case ISD::BUILD_PAIR:
3193 // Legalize both operands. FIXME: in the future we should handle the case
3194 // where the two elements are not legal.
3195 assert(isTypeLegal(NVT) && "Cannot expand this multiple times yet!");
3196 Lo = LegalizeOp(Node->getOperand(0));
3197 Hi = LegalizeOp(Node->getOperand(1));
3200 case ISD::SIGN_EXTEND_INREG:
3201 ExpandOp(Node->getOperand(0), Lo, Hi);
3202 // Sign extend the lo-part.
3203 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
3204 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
3205 TLI.getShiftAmountTy()));
3206 // sext_inreg the low part if needed.
3207 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
3211 ExpandOp(Node->getOperand(0), Lo, Hi);
3212 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
3213 DAG.getNode(ISD::CTPOP, NVT, Lo),
3214 DAG.getNode(ISD::CTPOP, NVT, Hi));
3215 Hi = DAG.getConstant(0, NVT);
3219 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
3220 ExpandOp(Node->getOperand(0), Lo, Hi);
3221 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3222 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
3223 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
3225 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
3226 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
3228 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
3229 Hi = DAG.getConstant(0, NVT);
3234 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
3235 ExpandOp(Node->getOperand(0), Lo, Hi);
3236 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
3237 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
3238 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
3240 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
3241 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
3243 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
3244 Hi = DAG.getConstant(0, NVT);
3249 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3250 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3251 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3253 // Increment the pointer to the other half.
3254 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
3255 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3256 getIntPtrConstant(IncrementSize));
3257 //Is this safe? declaring that the two parts of the split load
3258 //are from the same instruction?
3259 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
3261 // Build a factor node to remember that this load is independent of the
3263 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3266 // Remember that we legalized the chain.
3267 AddLegalizedOperand(Op.getValue(1), TF);
3268 if (!TLI.isLittleEndian())
3273 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3274 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3275 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3276 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3278 // If we only have two elements, turn into a pair of scalar loads.
3279 // FIXME: handle case where a vector of two elements is fine, such as
3280 // 2 x double on SSE2.
3281 if (NumElements == 2) {
3282 Lo = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3283 // Increment the pointer to the other half.
3284 unsigned IncrementSize = MVT::getSizeInBits(EVT)/8;
3285 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3286 getIntPtrConstant(IncrementSize));
3287 //Is this safe? declaring that the two parts of the split load
3288 //are from the same instruction?
3289 Hi = DAG.getLoad(EVT, Ch, Ptr, Node->getOperand(4));
3291 NumElements /= 2; // Split the vector in half
3292 Lo = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3293 unsigned IncrementSize = NumElements * MVT::getSizeInBits(EVT)/8;
3294 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
3295 getIntPtrConstant(IncrementSize));
3296 //Is this safe? declaring that the two parts of the split load
3297 //are from the same instruction?
3298 Hi = DAG.getVecLoad(NumElements, EVT, Ch, Ptr, Node->getOperand(4));
3301 // Build a factor node to remember that this load is independent of the
3303 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
3306 // Remember that we legalized the chain.
3307 AddLegalizedOperand(Op.getValue(1), TF);
3308 if (!TLI.isLittleEndian())
3315 unsigned NumElements =cast<ConstantSDNode>(Node->getOperand(2))->getValue();
3316 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3317 SDOperand LL, LH, RL, RH;
3319 ExpandOp(Node->getOperand(0), LL, LH);
3320 ExpandOp(Node->getOperand(1), RL, RH);
3322 // If we only have two elements, turn into a pair of scalar loads.
3323 // FIXME: handle case where a vector of two elements is fine, such as
3324 // 2 x double on SSE2.
3325 if (NumElements == 2) {
3326 unsigned Opc = getScalarizedOpcode(Node->getOpcode(), EVT);
3327 Lo = DAG.getNode(Opc, EVT, LL, RL);
3328 Hi = DAG.getNode(Opc, EVT, LH, RH);
3330 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL, LL.getOperand(2),
3332 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH, LH.getOperand(2),
3339 SDOperand Chain = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3340 SDOperand Callee = LegalizeOp(Node->getOperand(1)); // Legalize the callee.
3342 bool Changed = false;
3343 std::vector<SDOperand> Ops;
3344 for (unsigned i = 2, e = Node->getNumOperands(); i != e; ++i) {
3345 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3346 Changed |= Ops.back() != Node->getOperand(i);
3349 assert(Node->getNumValues() == 2 && Op.ResNo == 0 &&
3350 "Can only expand a call once so far, not i64 -> i16!");
3352 std::vector<MVT::ValueType> RetTyVTs;
3353 RetTyVTs.reserve(3);
3354 RetTyVTs.push_back(NVT);
3355 RetTyVTs.push_back(NVT);
3356 RetTyVTs.push_back(MVT::Other);
3357 SDNode *NC = DAG.getCall(RetTyVTs, Chain, Callee, Ops,
3358 Node->getOpcode() == ISD::TAILCALL);
3359 Lo = SDOperand(NC, 0);
3360 Hi = SDOperand(NC, 1);
3362 // Insert the new chain mapping.
3363 AddLegalizedOperand(Op.getValue(1), Hi.getValue(2));
3368 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
3369 SDOperand LL, LH, RL, RH;
3370 ExpandOp(Node->getOperand(0), LL, LH);
3371 ExpandOp(Node->getOperand(1), RL, RH);
3372 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
3373 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
3377 SDOperand C, LL, LH, RL, RH;
3379 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3380 case Expand: assert(0 && "It's impossible to expand bools");
3382 C = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
3385 C = PromoteOp(Node->getOperand(0)); // Promote the condition.
3388 ExpandOp(Node->getOperand(1), LL, LH);
3389 ExpandOp(Node->getOperand(2), RL, RH);
3390 Lo = DAG.getNode(ISD::SELECT, NVT, C, LL, RL);
3391 Hi = DAG.getNode(ISD::SELECT, NVT, C, LH, RH);
3394 case ISD::SELECT_CC: {
3395 SDOperand TL, TH, FL, FH;
3396 ExpandOp(Node->getOperand(2), TL, TH);
3397 ExpandOp(Node->getOperand(3), FL, FH);
3398 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3399 Node->getOperand(1), TL, FL, Node->getOperand(4));
3400 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3401 Node->getOperand(1), TH, FH, Node->getOperand(4));
3402 Lo = LegalizeOp(Lo);
3403 Hi = LegalizeOp(Hi);
3406 case ISD::SEXTLOAD: {
3407 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3408 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3409 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3412 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3414 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3417 // Remember that we legalized the chain.
3418 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3420 // The high part is obtained by SRA'ing all but one of the bits of the lo
3422 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3423 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3424 TLI.getShiftAmountTy()));
3425 Lo = LegalizeOp(Lo);
3426 Hi = LegalizeOp(Hi);
3429 case ISD::ZEXTLOAD: {
3430 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3431 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3432 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3435 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3437 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3440 // Remember that we legalized the chain.
3441 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3443 // The high part is just a zero.
3444 Hi = LegalizeOp(DAG.getConstant(0, NVT));
3445 Lo = LegalizeOp(Lo);
3448 case ISD::EXTLOAD: {
3449 SDOperand Chain = LegalizeOp(Node->getOperand(0));
3450 SDOperand Ptr = LegalizeOp(Node->getOperand(1));
3451 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
3454 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
3456 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
3459 // Remember that we legalized the chain.
3460 AddLegalizedOperand(SDOperand(Node, 1), Lo.getValue(1));
3462 // The high part is undefined.
3463 Hi = LegalizeOp(DAG.getNode(ISD::UNDEF, NVT));
3464 Lo = LegalizeOp(Lo);
3467 case ISD::ANY_EXTEND: {
3469 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3470 case Expand: assert(0 && "expand-expand not implemented yet!");
3471 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3473 In = PromoteOp(Node->getOperand(0));
3477 // The low part is any extension of the input (which degenerates to a copy).
3478 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, In);
3479 // The high part is undefined.
3480 Hi = DAG.getNode(ISD::UNDEF, NVT);
3483 case ISD::SIGN_EXTEND: {
3485 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3486 case Expand: assert(0 && "expand-expand not implemented yet!");
3487 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3489 In = PromoteOp(Node->getOperand(0));
3490 // Emit the appropriate sign_extend_inreg to get the value we want.
3491 In = DAG.getNode(ISD::SIGN_EXTEND_INREG, In.getValueType(), In,
3492 DAG.getValueType(Node->getOperand(0).getValueType()));
3496 // The low part is just a sign extension of the input (which degenerates to
3498 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, In);
3500 // The high part is obtained by SRA'ing all but one of the bits of the lo
3502 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
3503 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
3504 TLI.getShiftAmountTy()));
3507 case ISD::ZERO_EXTEND: {
3509 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3510 case Expand: assert(0 && "expand-expand not implemented yet!");
3511 case Legal: In = LegalizeOp(Node->getOperand(0)); break;
3513 In = PromoteOp(Node->getOperand(0));
3514 // Emit the appropriate zero_extend_inreg to get the value we want.
3515 In = DAG.getZeroExtendInReg(In, Node->getOperand(0).getValueType());
3519 // The low part is just a zero extension of the input (which degenerates to
3521 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, In);
3523 // The high part is just a zero.
3524 Hi = DAG.getConstant(0, NVT);
3528 case ISD::READCYCLECOUNTER: {
3529 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
3530 TargetLowering::Custom &&
3531 "Must custom expand ReadCycleCounter");
3532 SDOperand T = TLI.LowerOperation(Op, DAG);
3533 assert(T.Val && "Node must be custom expanded!");
3534 Lo = LegalizeOp(T.getValue(0));
3535 Hi = LegalizeOp(T.getValue(1));
3536 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
3537 LegalizeOp(T.getValue(2)));
3541 // These operators cannot be expanded directly, emit them as calls to
3542 // library functions.
3543 case ISD::FP_TO_SINT:
3544 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
3546 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3547 case Expand: assert(0 && "cannot expand FP!");
3548 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
3549 case Promote: Op = PromoteOp(Node->getOperand(0)); break;
3552 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
3554 // Now that the custom expander is done, expand the result, which is still
3557 ExpandOp(Op, Lo, Hi);
3562 if (Node->getOperand(0).getValueType() == MVT::f32)
3563 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
3565 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
3568 case ISD::FP_TO_UINT:
3569 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
3570 SDOperand Op = DAG.getNode(ISD::FP_TO_UINT, VT,
3571 LegalizeOp(Node->getOperand(0)));
3572 // Now that the custom expander is done, expand the result, which is still
3574 Op = TLI.LowerOperation(Op, DAG);
3576 ExpandOp(Op, Lo, Hi);
3581 if (Node->getOperand(0).getValueType() == MVT::f32)
3582 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
3584 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
3588 // If the target wants custom lowering, do so.
3589 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
3590 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0),
3591 LegalizeOp(Node->getOperand(1)));
3592 Op = TLI.LowerOperation(Op, DAG);
3594 // Now that the custom expander is done, expand the result, which is
3596 ExpandOp(Op, Lo, Hi);
3601 // If we can emit an efficient shift operation, do so now.
3602 if (ExpandShift(ISD::SHL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3605 // If this target supports SHL_PARTS, use it.
3606 if (TLI.isOperationLegal(ISD::SHL_PARTS, NVT)) {
3607 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
3612 // Otherwise, emit a libcall.
3613 Lo = ExpandLibCall("__ashldi3", Node, Hi);
3617 // If the target wants custom lowering, do so.
3618 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
3619 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0),
3620 LegalizeOp(Node->getOperand(1)));
3621 Op = TLI.LowerOperation(Op, DAG);
3623 // Now that the custom expander is done, expand the result, which is
3625 ExpandOp(Op, Lo, Hi);
3630 // If we can emit an efficient shift operation, do so now.
3631 if (ExpandShift(ISD::SRA, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3634 // If this target supports SRA_PARTS, use it.
3635 if (TLI.isOperationLegal(ISD::SRA_PARTS, NVT)) {
3636 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
3641 // Otherwise, emit a libcall.
3642 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
3645 // If the target wants custom lowering, do so.
3646 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
3647 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0),
3648 LegalizeOp(Node->getOperand(1)));
3649 Op = TLI.LowerOperation(Op, DAG);
3651 // Now that the custom expander is done, expand the result, which is
3653 ExpandOp(Op, Lo, Hi);
3658 // If we can emit an efficient shift operation, do so now.
3659 if (ExpandShift(ISD::SRL, Node->getOperand(0), Node->getOperand(1), Lo, Hi))
3662 // If this target supports SRL_PARTS, use it.
3663 if (TLI.isOperationLegal(ISD::SRL_PARTS, NVT)) {
3664 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
3669 // Otherwise, emit a libcall.
3670 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
3674 ExpandByParts(ISD::ADD_PARTS, Node->getOperand(0), Node->getOperand(1),
3678 ExpandByParts(ISD::SUB_PARTS, Node->getOperand(0), Node->getOperand(1),
3682 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
3683 SDOperand LL, LH, RL, RH;
3684 ExpandOp(Node->getOperand(0), LL, LH);
3685 ExpandOp(Node->getOperand(1), RL, RH);
3686 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
3687 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
3688 // extended the sign bit of the low half through the upper half, and if so
3689 // emit a MULHS instead of the alternate sequence that is valid for any
3690 // i64 x i64 multiply.
3691 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
3692 // is RH an extension of the sign bit of RL?
3693 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
3694 RH.getOperand(1).getOpcode() == ISD::Constant &&
3695 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
3696 // is LH an extension of the sign bit of LL?
3697 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
3698 LH.getOperand(1).getOpcode() == ISD::Constant &&
3699 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
3700 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
3702 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
3703 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
3704 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
3705 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
3706 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
3708 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
3710 Lo = ExpandLibCall("__muldi3" , Node, Hi); break;
3714 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
3715 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
3716 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
3717 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
3720 // Remember in a map if the values will be reused later.
3721 bool isNew = ExpandedNodes.insert(std::make_pair(Op,
3722 std::make_pair(Lo, Hi))).second;
3723 assert(isNew && "Value already expanded?!?");
3727 // SelectionDAG::Legalize - This is the entry point for the file.
3729 void SelectionDAG::Legalize() {
3730 /// run - This is the main entry point to this class.
3732 SelectionDAGLegalize(*this).Run();