1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/ADT/SetVector.h"
16 #include "llvm/ADT/SmallPtrSet.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/Triple.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineJumpTableInfo.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/DebugInfo.h"
27 #include "llvm/IR/DerivedTypes.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetFrameLowering.h"
35 #include "llvm/Target/TargetLowering.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetSubtargetInfo.h"
40 #define DEBUG_TYPE "legalizedag"
42 //===----------------------------------------------------------------------===//
43 /// This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class SelectionDAGLegalize {
56 const TargetMachine &TM;
57 const TargetLowering &TLI;
60 /// \brief The set of nodes which have already been legalized. We hold a
61 /// reference to it in order to update as necessary on node deletion.
62 SmallPtrSetImpl<SDNode *> &LegalizedNodes;
64 /// \brief A set of all the nodes updated during legalization.
65 SmallSetVector<SDNode *, 16> *UpdatedNodes;
67 EVT getSetCCResultType(EVT VT) const {
68 return TLI.getSetCCResultType(*DAG.getContext(), VT);
71 // Libcall insertion helpers.
74 SelectionDAGLegalize(SelectionDAG &DAG,
75 SmallPtrSetImpl<SDNode *> &LegalizedNodes,
76 SmallSetVector<SDNode *, 16> *UpdatedNodes = nullptr)
77 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG),
78 LegalizedNodes(LegalizedNodes), UpdatedNodes(UpdatedNodes) {}
80 /// \brief Legalizes the given operation.
81 void LegalizeOp(SDNode *Node);
84 SDValue OptimizeFloatStore(StoreSDNode *ST);
86 void LegalizeLoadOps(SDNode *Node);
87 void LegalizeStoreOps(SDNode *Node);
89 /// Some targets cannot handle a variable
90 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
91 /// is necessary to spill the vector being inserted into to memory, perform
92 /// the insert there, and then read the result back.
93 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
94 SDValue Idx, SDLoc dl);
95 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
96 SDValue Idx, SDLoc dl);
98 /// Return a vector shuffle operation which
99 /// performs the same shuffe in terms of order or result bytes, but on a type
100 /// whose vector element type is narrower than the original shuffle type.
101 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
102 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
103 SDValue N1, SDValue N2,
104 ArrayRef<int> Mask) const;
106 bool LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
107 bool &NeedInvert, SDLoc dl);
109 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
110 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
111 unsigned NumOps, bool isSigned, SDLoc dl);
113 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
114 SDNode *Node, bool isSigned);
115 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
116 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
117 RTLIB::Libcall Call_F128,
118 RTLIB::Libcall Call_PPCF128);
119 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
120 RTLIB::Libcall Call_I8,
121 RTLIB::Libcall Call_I16,
122 RTLIB::Libcall Call_I32,
123 RTLIB::Libcall Call_I64,
124 RTLIB::Libcall Call_I128);
125 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
126 void ExpandSinCosLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
128 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, SDLoc dl);
129 SDValue ExpandBUILD_VECTOR(SDNode *Node);
130 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
131 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
132 SmallVectorImpl<SDValue> &Results);
133 SDValue ExpandFCOPYSIGN(SDNode *Node);
134 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
136 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
138 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
141 SDValue ExpandBSWAP(SDValue Op, SDLoc dl);
142 SDValue ExpandBitCount(unsigned Opc, SDValue Op, SDLoc dl);
144 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
145 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
146 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
148 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
150 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
152 void ExpandNode(SDNode *Node);
153 void PromoteNode(SDNode *Node);
156 // Node replacement helpers
157 void ReplacedNode(SDNode *N) {
158 LegalizedNodes.erase(N);
160 UpdatedNodes->insert(N);
162 void ReplaceNode(SDNode *Old, SDNode *New) {
163 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
164 dbgs() << " with: "; New->dump(&DAG));
166 assert(Old->getNumValues() == New->getNumValues() &&
167 "Replacing one node with another that produces a different number "
169 DAG.ReplaceAllUsesWith(Old, New);
170 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i)
171 DAG.TransferDbgValues(SDValue(Old, i), SDValue(New, i));
173 UpdatedNodes->insert(New);
176 void ReplaceNode(SDValue Old, SDValue New) {
177 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG);
178 dbgs() << " with: "; New->dump(&DAG));
180 DAG.ReplaceAllUsesWith(Old, New);
181 DAG.TransferDbgValues(Old, New);
183 UpdatedNodes->insert(New.getNode());
184 ReplacedNode(Old.getNode());
186 void ReplaceNode(SDNode *Old, const SDValue *New) {
187 DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG));
189 DAG.ReplaceAllUsesWith(Old, New);
190 for (unsigned i = 0, e = Old->getNumValues(); i != e; ++i) {
191 DEBUG(dbgs() << (i == 0 ? " with: "
194 DAG.TransferDbgValues(SDValue(Old, i), New[i]);
196 UpdatedNodes->insert(New[i].getNode());
203 /// Return a vector shuffle operation which
204 /// performs the same shuffe in terms of order or result bytes, but on a type
205 /// whose vector element type is narrower than the original shuffle type.
206 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
208 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, SDLoc dl,
209 SDValue N1, SDValue N2,
210 ArrayRef<int> Mask) const {
211 unsigned NumMaskElts = VT.getVectorNumElements();
212 unsigned NumDestElts = NVT.getVectorNumElements();
213 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
215 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
217 if (NumEltsGrowth == 1)
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
220 SmallVector<int, 8> NewMask;
221 for (unsigned i = 0; i != NumMaskElts; ++i) {
223 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
225 NewMask.push_back(-1);
227 NewMask.push_back(Idx * NumEltsGrowth + j);
230 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
231 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
235 /// Expands the ConstantFP node to an integer constant or
236 /// a load from the constant pool.
238 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) {
242 // If a FP immediate is precise when represented as a float and if the
243 // target can do an extending load from float to double, we put it into
244 // the constant pool as a float, even if it's is statically typed as a
245 // double. This shrinks FP constants and canonicalizes them for targets where
246 // an FP extending load is the same cost as a normal load (such as on the x87
247 // fp stack or PPC FP unit).
248 EVT VT = CFP->getValueType(0);
249 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
251 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
252 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
253 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
258 while (SVT != MVT::f32 && SVT != MVT::f16) {
259 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
260 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
261 // Only do this if the target has a native EXTLOAD instruction from
263 TLI.isLoadExtLegal(ISD::EXTLOAD, OrigVT, SVT) &&
264 TLI.ShouldShrinkFPConstant(OrigVT)) {
265 Type *SType = SVT.getTypeForEVT(*DAG.getContext());
266 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
272 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
273 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
276 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
278 CPIdx, MachinePointerInfo::getConstantPool(),
279 VT, false, false, false, Alignment);
283 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
284 MachinePointerInfo::getConstantPool(), false, false, false,
289 /// Expands an unaligned store to 2 half-size stores.
290 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
291 const TargetLowering &TLI,
292 SelectionDAGLegalize *DAGLegalize) {
293 assert(ST->getAddressingMode() == ISD::UNINDEXED &&
294 "unaligned indexed stores not implemented!");
295 SDValue Chain = ST->getChain();
296 SDValue Ptr = ST->getBasePtr();
297 SDValue Val = ST->getValue();
298 EVT VT = Val.getValueType();
299 int Alignment = ST->getAlignment();
300 unsigned AS = ST->getAddressSpace();
303 if (ST->getMemoryVT().isFloatingPoint() ||
304 ST->getMemoryVT().isVector()) {
305 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
306 if (TLI.isTypeLegal(intVT)) {
307 // Expand to a bitconvert of the value to the integer type of the
308 // same size, then a (misaligned) int store.
309 // FIXME: Does not handle truncating floating point stores!
310 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
311 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
312 ST->isVolatile(), ST->isNonTemporal(), Alignment);
313 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
316 // Do a (aligned) store to a stack slot, then copy from the stack slot
317 // to the final destination using (unaligned) integer loads and stores.
318 EVT StoredVT = ST->getMemoryVT();
320 TLI.getRegisterType(*DAG.getContext(),
321 EVT::getIntegerVT(*DAG.getContext(),
322 StoredVT.getSizeInBits()));
323 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
324 unsigned RegBytes = RegVT.getSizeInBits() / 8;
325 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
327 // Make sure the stack slot is also aligned for the register type.
328 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
330 // Perform the original store, only redirected to the stack slot.
331 SDValue Store = DAG.getTruncStore(Chain, dl,
332 Val, StackPtr, MachinePointerInfo(),
333 StoredVT, false, false, 0);
334 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy(AS));
335 SmallVector<SDValue, 8> Stores;
338 // Do all but one copies using the full register width.
339 for (unsigned i = 1; i < NumRegs; i++) {
340 // Load one integer register's worth from the stack slot.
341 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
342 MachinePointerInfo(),
343 false, false, false, 0);
344 // Store it to the final location. Remember the store.
345 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
346 ST->getPointerInfo().getWithOffset(Offset),
347 ST->isVolatile(), ST->isNonTemporal(),
348 MinAlign(ST->getAlignment(), Offset)));
349 // Increment the pointers.
351 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
353 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
356 // The last store may be partial. Do a truncating store. On big-endian
357 // machines this requires an extending load from the stack slot to ensure
358 // that the bits are in the right place.
359 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
360 8 * (StoredBytes - Offset));
362 // Load from the stack slot.
363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
364 MachinePointerInfo(),
365 MemVT, false, false, false, 0);
367 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
369 .getWithOffset(Offset),
370 MemVT, ST->isVolatile(),
372 MinAlign(ST->getAlignment(), Offset),
374 // The order of the stores doesn't matter - say it with a TokenFactor.
375 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
376 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
379 assert(ST->getMemoryVT().isInteger() &&
380 !ST->getMemoryVT().isVector() &&
381 "Unaligned store of unknown type.");
382 // Get the half-size VT
383 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
384 int NumBits = NewStoredVT.getSizeInBits();
385 int IncrementSize = NumBits / 8;
387 // Divide the stored value in two parts.
388 SDValue ShiftAmount = DAG.getConstant(NumBits,
389 TLI.getShiftAmountTy(Val.getValueType()));
391 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
393 // Store the two parts
394 SDValue Store1, Store2;
395 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
396 ST->getPointerInfo(), NewStoredVT,
397 ST->isVolatile(), ST->isNonTemporal(), Alignment);
399 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
400 DAG.getConstant(IncrementSize, TLI.getPointerTy(AS)));
401 Alignment = MinAlign(Alignment, IncrementSize);
402 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
403 ST->getPointerInfo().getWithOffset(IncrementSize),
404 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
405 Alignment, ST->getAAInfo());
408 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
409 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result);
412 /// Expands an unaligned load to 2 half-size loads.
414 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
415 const TargetLowering &TLI,
416 SDValue &ValResult, SDValue &ChainResult) {
417 assert(LD->getAddressingMode() == ISD::UNINDEXED &&
418 "unaligned indexed loads not implemented!");
419 SDValue Chain = LD->getChain();
420 SDValue Ptr = LD->getBasePtr();
421 EVT VT = LD->getValueType(0);
422 EVT LoadedVT = LD->getMemoryVT();
424 if (VT.isFloatingPoint() || VT.isVector()) {
425 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
426 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) {
427 // Expand to a (misaligned) integer load of the same size,
428 // then bitconvert to floating point or vector.
429 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr,
430 LD->getMemOperand());
431 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
433 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
434 ISD::ANY_EXTEND, dl, VT, Result);
441 // Copy the value to a (aligned) stack slot using (unaligned) integer
442 // loads and stores, then do a (aligned) load from the stack slot.
443 MVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
444 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
445 unsigned RegBytes = RegVT.getSizeInBits() / 8;
446 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
448 // Make sure the stack slot is also aligned for the register type.
449 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
451 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
452 SmallVector<SDValue, 8> Stores;
453 SDValue StackPtr = StackBase;
456 // Do all but one copies using the full register width.
457 for (unsigned i = 1; i < NumRegs; i++) {
458 // Load one integer register's worth from the original location.
459 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
460 LD->getPointerInfo().getWithOffset(Offset),
461 LD->isVolatile(), LD->isNonTemporal(),
463 MinAlign(LD->getAlignment(), Offset),
465 // Follow the load with a store to the stack slot. Remember the store.
466 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
467 MachinePointerInfo(), false, false, 0));
468 // Increment the pointers.
470 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
471 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
475 // The last copy may be partial. Do an extending load.
476 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
477 8 * (LoadedBytes - Offset));
478 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
479 LD->getPointerInfo().getWithOffset(Offset),
480 MemVT, LD->isVolatile(),
483 MinAlign(LD->getAlignment(), Offset),
485 // Follow the load with a store to the stack slot. Remember the store.
486 // On big-endian machines this requires a truncating store to ensure
487 // that the bits end up in the right place.
488 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
489 MachinePointerInfo(), MemVT,
492 // The order of the stores doesn't matter - say it with a TokenFactor.
493 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
495 // Finally, perform the original load only redirected to the stack slot.
496 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
497 MachinePointerInfo(), LoadedVT, false,false, false,
500 // Callers expect a MERGE_VALUES node.
505 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
506 "Unaligned load of unsupported type.");
508 // Compute the new VT that is half the size of the old one. This is an
510 unsigned NumBits = LoadedVT.getSizeInBits();
512 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
515 unsigned Alignment = LD->getAlignment();
516 unsigned IncrementSize = NumBits / 8;
517 ISD::LoadExtType HiExtType = LD->getExtensionType();
519 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
520 if (HiExtType == ISD::NON_EXTLOAD)
521 HiExtType = ISD::ZEXTLOAD;
523 // Load the value in two parts
525 if (TLI.isLittleEndian()) {
526 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
527 NewLoadedVT, LD->isVolatile(),
528 LD->isNonTemporal(), LD->isInvariant(), Alignment,
530 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
531 DAG.getConstant(IncrementSize, Ptr.getValueType()));
532 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
533 LD->getPointerInfo().getWithOffset(IncrementSize),
534 NewLoadedVT, LD->isVolatile(),
535 LD->isNonTemporal(),LD->isInvariant(),
536 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
538 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
539 NewLoadedVT, LD->isVolatile(),
540 LD->isNonTemporal(), LD->isInvariant(), Alignment,
542 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
543 DAG.getConstant(IncrementSize, Ptr.getValueType()));
544 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
545 LD->getPointerInfo().getWithOffset(IncrementSize),
546 NewLoadedVT, LD->isVolatile(),
547 LD->isNonTemporal(), LD->isInvariant(),
548 MinAlign(Alignment, IncrementSize), LD->getAAInfo());
551 // aggregate the two parts
552 SDValue ShiftAmount = DAG.getConstant(NumBits,
553 TLI.getShiftAmountTy(Hi.getValueType()));
554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
564 /// Some target cannot handle a variable insertion index for the
565 /// INSERT_VECTOR_ELT instruction. In this case, it
566 /// is necessary to spill the vector being inserted into to memory, perform
567 /// the insert there, and then read the result back.
568 SDValue SelectionDAGLegalize::
569 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
575 // If the target doesn't support this, we have to spill the input vector
576 // to a temporary stack slot, update the element, then reload it. This is
577 // badness. We could also load the value into a vector register (either
578 // with a "move to register" or "extload into register" instruction, then
579 // permute it into place, if the idx is a constant and if the idx is
580 // supported by the target.
581 EVT VT = Tmp1.getValueType();
582 EVT EltVT = VT.getVectorElementType();
583 EVT IdxVT = Tmp3.getValueType();
584 EVT PtrVT = TLI.getPointerTy();
585 SDValue StackPtr = DAG.CreateStackTemporary(VT);
587 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
591 MachinePointerInfo::getFixedStack(SPFI),
594 // Truncate or zero extend offset to target pointer type.
595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
596 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
597 // Add the offset to the index.
598 unsigned EltSize = EltVT.getSizeInBits()/8;
599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
600 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
601 // Store the scalar value.
602 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
604 // Load the updated vector.
605 return DAG.getLoad(VT, dl, Ch, StackPtr,
606 MachinePointerInfo::getFixedStack(SPFI), false, false,
611 SDValue SelectionDAGLegalize::
612 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, SDLoc dl) {
613 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
614 // SCALAR_TO_VECTOR requires that the type of the value being inserted
615 // match the element type of the vector being created, except for
616 // integers in which case the inserted value can be over width.
617 EVT EltVT = Vec.getValueType().getVectorElementType();
618 if (Val.getValueType() == EltVT ||
619 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
620 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
621 Vec.getValueType(), Val);
623 unsigned NumElts = Vec.getValueType().getVectorNumElements();
624 // We generate a shuffle of InVec and ScVec, so the shuffle mask
625 // should be 0,1,2,3,4,5... with the appropriate element replaced with
627 SmallVector<int, 8> ShufOps;
628 for (unsigned i = 0; i != NumElts; ++i)
629 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
631 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
635 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
638 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
639 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
640 // FIXME: We shouldn't do this for TargetConstantFP's.
641 // FIXME: move this to the DAG Combiner! Note that we can't regress due
642 // to phase ordering between legalized code and the dag combiner. This
643 // probably means that we need to integrate dag combiner and legalizer
645 // We generally can't do this one for long doubles.
646 SDValue Chain = ST->getChain();
647 SDValue Ptr = ST->getBasePtr();
648 unsigned Alignment = ST->getAlignment();
649 bool isVolatile = ST->isVolatile();
650 bool isNonTemporal = ST->isNonTemporal();
651 AAMDNodes AAInfo = ST->getAAInfo();
653 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
654 if (CFP->getValueType(0) == MVT::f32 &&
655 TLI.isTypeLegal(MVT::i32)) {
656 SDValue Con = DAG.getConstant(CFP->getValueAPF().
657 bitcastToAPInt().zextOrTrunc(32),
659 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
660 isVolatile, isNonTemporal, Alignment, AAInfo);
663 if (CFP->getValueType(0) == MVT::f64) {
664 // If this target supports 64-bit registers, do a single 64-bit store.
665 if (TLI.isTypeLegal(MVT::i64)) {
666 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
667 zextOrTrunc(64), MVT::i64);
668 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(),
669 isVolatile, isNonTemporal, Alignment, AAInfo);
672 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) {
673 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
674 // stores. If the target supports neither 32- nor 64-bits, this
675 // xform is certainly not worth it.
676 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
677 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
678 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
679 if (TLI.isBigEndian()) std::swap(Lo, Hi);
681 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile,
682 isNonTemporal, Alignment, AAInfo);
683 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
684 DAG.getConstant(4, Ptr.getValueType()));
685 Hi = DAG.getStore(Chain, dl, Hi, Ptr,
686 ST->getPointerInfo().getWithOffset(4),
687 isVolatile, isNonTemporal, MinAlign(Alignment, 4U),
690 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
694 return SDValue(nullptr, 0);
697 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
698 StoreSDNode *ST = cast<StoreSDNode>(Node);
699 SDValue Chain = ST->getChain();
700 SDValue Ptr = ST->getBasePtr();
703 unsigned Alignment = ST->getAlignment();
704 bool isVolatile = ST->isVolatile();
705 bool isNonTemporal = ST->isNonTemporal();
706 AAMDNodes AAInfo = ST->getAAInfo();
708 if (!ST->isTruncatingStore()) {
709 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
710 ReplaceNode(ST, OptStore);
715 SDValue Value = ST->getValue();
716 MVT VT = Value.getSimpleValueType();
717 switch (TLI.getOperationAction(ISD::STORE, VT)) {
718 default: llvm_unreachable("This action is not supported yet!");
719 case TargetLowering::Legal: {
720 // If this is an unaligned store and the target doesn't support it,
722 unsigned AS = ST->getAddressSpace();
723 unsigned Align = ST->getAlignment();
724 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
725 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
726 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
727 if (Align < ABIAlignment)
728 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
732 case TargetLowering::Custom: {
733 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
734 if (Res && Res != SDValue(Node, 0))
735 ReplaceNode(SDValue(Node, 0), Res);
738 case TargetLowering::Promote: {
739 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
740 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
741 "Can only promote stores to same size type");
742 Value = DAG.getNode(ISD::BITCAST, dl, NVT, Value);
744 DAG.getStore(Chain, dl, Value, Ptr,
745 ST->getPointerInfo(), isVolatile,
746 isNonTemporal, Alignment, AAInfo);
747 ReplaceNode(SDValue(Node, 0), Result);
754 SDValue Value = ST->getValue();
756 EVT StVT = ST->getMemoryVT();
757 unsigned StWidth = StVT.getSizeInBits();
759 if (StWidth != StVT.getStoreSizeInBits()) {
760 // Promote to a byte-sized store with upper bits zero if not
761 // storing an integral number of bytes. For example, promote
762 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
763 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
764 StVT.getStoreSizeInBits());
765 Value = DAG.getZeroExtendInReg(Value, dl, StVT);
767 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
768 NVT, isVolatile, isNonTemporal, Alignment, AAInfo);
769 ReplaceNode(SDValue(Node, 0), Result);
770 } else if (StWidth & (StWidth - 1)) {
771 // If not storing a power-of-2 number of bits, expand as two stores.
772 assert(!StVT.isVector() && "Unsupported truncstore!");
773 unsigned RoundWidth = 1 << Log2_32(StWidth);
774 assert(RoundWidth < StWidth);
775 unsigned ExtraWidth = StWidth - RoundWidth;
776 assert(ExtraWidth < RoundWidth);
777 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
778 "Store size not an integral number of bytes!");
779 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
780 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
782 unsigned IncrementSize;
784 if (TLI.isLittleEndian()) {
785 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
786 // Store the bottom RoundWidth bits.
787 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
789 isVolatile, isNonTemporal, Alignment,
792 // Store the remaining ExtraWidth bits.
793 IncrementSize = RoundWidth / 8;
794 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
795 DAG.getConstant(IncrementSize, Ptr.getValueType()));
796 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
797 DAG.getConstant(RoundWidth,
798 TLI.getShiftAmountTy(Value.getValueType())));
799 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr,
800 ST->getPointerInfo().getWithOffset(IncrementSize),
801 ExtraVT, isVolatile, isNonTemporal,
802 MinAlign(Alignment, IncrementSize), AAInfo);
804 // Big endian - avoid unaligned stores.
805 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
806 // Store the top RoundWidth bits.
807 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value,
808 DAG.getConstant(ExtraWidth,
809 TLI.getShiftAmountTy(Value.getValueType())));
810 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(),
811 RoundVT, isVolatile, isNonTemporal, Alignment,
814 // Store the remaining ExtraWidth bits.
815 IncrementSize = RoundWidth / 8;
816 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
817 DAG.getConstant(IncrementSize, Ptr.getValueType()));
818 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr,
819 ST->getPointerInfo().getWithOffset(IncrementSize),
820 ExtraVT, isVolatile, isNonTemporal,
821 MinAlign(Alignment, IncrementSize), AAInfo);
824 // The order of the stores doesn't matter.
825 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
826 ReplaceNode(SDValue(Node, 0), Result);
828 switch (TLI.getTruncStoreAction(ST->getValue().getSimpleValueType(),
829 StVT.getSimpleVT())) {
830 default: llvm_unreachable("This action is not supported yet!");
831 case TargetLowering::Legal: {
832 unsigned AS = ST->getAddressSpace();
833 unsigned Align = ST->getAlignment();
834 // If this is an unaligned store and the target doesn't support it,
836 if (!TLI.allowsMisalignedMemoryAccesses(ST->getMemoryVT(), AS, Align)) {
837 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
838 unsigned ABIAlignment= TLI.getDataLayout()->getABITypeAlignment(Ty);
839 if (Align < ABIAlignment)
840 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
844 case TargetLowering::Custom: {
845 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
846 if (Res && Res != SDValue(Node, 0))
847 ReplaceNode(SDValue(Node, 0), Res);
850 case TargetLowering::Expand:
851 assert(!StVT.isVector() &&
852 "Vector Stores are handled in LegalizeVectorOps");
854 // TRUNCSTORE:i16 i32 -> STORE i16
855 assert(TLI.isTypeLegal(StVT) &&
856 "Do not know how to expand this store!");
857 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value);
859 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(),
860 isVolatile, isNonTemporal, Alignment, AAInfo);
861 ReplaceNode(SDValue(Node, 0), Result);
868 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
869 LoadSDNode *LD = cast<LoadSDNode>(Node);
870 SDValue Chain = LD->getChain(); // The chain.
871 SDValue Ptr = LD->getBasePtr(); // The base pointer.
872 SDValue Value; // The value returned by the load op.
875 ISD::LoadExtType ExtType = LD->getExtensionType();
876 if (ExtType == ISD::NON_EXTLOAD) {
877 MVT VT = Node->getSimpleValueType(0);
878 SDValue RVal = SDValue(Node, 0);
879 SDValue RChain = SDValue(Node, 1);
881 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
882 default: llvm_unreachable("This action is not supported yet!");
883 case TargetLowering::Legal: {
884 unsigned AS = LD->getAddressSpace();
885 unsigned Align = LD->getAlignment();
886 // If this is an unaligned load and the target doesn't support it,
888 if (!TLI.allowsMisalignedMemoryAccesses(LD->getMemoryVT(), AS, Align)) {
889 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
890 unsigned ABIAlignment =
891 TLI.getDataLayout()->getABITypeAlignment(Ty);
892 if (Align < ABIAlignment){
893 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, RVal, RChain);
898 case TargetLowering::Custom: {
899 SDValue Res = TLI.LowerOperation(RVal, DAG);
902 RChain = Res.getValue(1);
906 case TargetLowering::Promote: {
907 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
908 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
909 "Can only promote loads to same size type");
911 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getMemOperand());
912 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
913 RChain = Res.getValue(1);
917 if (RChain.getNode() != Node) {
918 assert(RVal.getNode() != Node && "Load must be completely replaced");
919 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal);
920 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain);
922 UpdatedNodes->insert(RVal.getNode());
923 UpdatedNodes->insert(RChain.getNode());
930 EVT SrcVT = LD->getMemoryVT();
931 unsigned SrcWidth = SrcVT.getSizeInBits();
932 unsigned Alignment = LD->getAlignment();
933 bool isVolatile = LD->isVolatile();
934 bool isNonTemporal = LD->isNonTemporal();
935 bool isInvariant = LD->isInvariant();
936 AAMDNodes AAInfo = LD->getAAInfo();
938 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
939 // Some targets pretend to have an i1 loading operation, and actually
940 // load an i8. This trick is correct for ZEXTLOAD because the top 7
941 // bits are guaranteed to be zero; it helps the optimizers understand
942 // that these bits are zero. It is also useful for EXTLOAD, since it
943 // tells the optimizers that those bits are undefined. It would be
944 // nice to have an effective generic way of getting these benefits...
945 // Until such a way is found, don't insist on promoting i1 here.
947 TLI.getLoadExtAction(ExtType, Node->getValueType(0), MVT::i1) ==
948 TargetLowering::Promote)) {
949 // Promote to a byte-sized load if not loading an integral number of
950 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
951 unsigned NewWidth = SrcVT.getStoreSizeInBits();
952 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
955 // The extra bits are guaranteed to be zero, since we stored them that
956 // way. A zext load from NVT thus automatically gives zext from SrcVT.
958 ISD::LoadExtType NewExtType =
959 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
962 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
963 Chain, Ptr, LD->getPointerInfo(),
964 NVT, isVolatile, isNonTemporal, isInvariant, Alignment,
967 Ch = Result.getValue(1); // The chain.
969 if (ExtType == ISD::SEXTLOAD)
970 // Having the top bits zero doesn't help when sign extending.
971 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
972 Result.getValueType(),
973 Result, DAG.getValueType(SrcVT));
974 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
975 // All the top bits are guaranteed to be zero - inform the optimizers.
976 Result = DAG.getNode(ISD::AssertZext, dl,
977 Result.getValueType(), Result,
978 DAG.getValueType(SrcVT));
982 } else if (SrcWidth & (SrcWidth - 1)) {
983 // If not loading a power-of-2 number of bits, expand as two loads.
984 assert(!SrcVT.isVector() && "Unsupported extload!");
985 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
986 assert(RoundWidth < SrcWidth);
987 unsigned ExtraWidth = SrcWidth - RoundWidth;
988 assert(ExtraWidth < RoundWidth);
989 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
990 "Load size not an integral number of bytes!");
991 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
992 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
994 unsigned IncrementSize;
996 if (TLI.isLittleEndian()) {
997 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
998 // Load the bottom RoundWidth bits.
999 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1001 LD->getPointerInfo(), RoundVT, isVolatile,
1002 isNonTemporal, isInvariant, Alignment, AAInfo);
1004 // Load the remaining ExtraWidth bits.
1005 IncrementSize = RoundWidth / 8;
1006 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1007 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1008 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1009 LD->getPointerInfo().getWithOffset(IncrementSize),
1010 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1011 MinAlign(Alignment, IncrementSize), AAInfo);
1013 // Build a factor node to remember that this load is independent of
1015 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1018 // Move the top bits to the right place.
1019 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1020 DAG.getConstant(RoundWidth,
1021 TLI.getShiftAmountTy(Hi.getValueType())));
1023 // Join the hi and lo parts.
1024 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1026 // Big endian - avoid unaligned loads.
1027 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1028 // Load the top RoundWidth bits.
1029 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr,
1030 LD->getPointerInfo(), RoundVT, isVolatile,
1031 isNonTemporal, isInvariant, Alignment, AAInfo);
1033 // Load the remaining ExtraWidth bits.
1034 IncrementSize = RoundWidth / 8;
1035 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
1036 DAG.getConstant(IncrementSize, Ptr.getValueType()));
1037 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1038 dl, Node->getValueType(0), Chain, Ptr,
1039 LD->getPointerInfo().getWithOffset(IncrementSize),
1040 ExtraVT, isVolatile, isNonTemporal, isInvariant,
1041 MinAlign(Alignment, IncrementSize), AAInfo);
1043 // Build a factor node to remember that this load is independent of
1045 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1048 // Move the top bits to the right place.
1049 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1050 DAG.getConstant(ExtraWidth,
1051 TLI.getShiftAmountTy(Hi.getValueType())));
1053 // Join the hi and lo parts.
1054 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1059 bool isCustom = false;
1060 switch (TLI.getLoadExtAction(ExtType, Node->getValueType(0),
1061 SrcVT.getSimpleVT())) {
1062 default: llvm_unreachable("This action is not supported yet!");
1063 case TargetLowering::Custom:
1066 case TargetLowering::Legal: {
1067 Value = SDValue(Node, 0);
1068 Chain = SDValue(Node, 1);
1071 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1072 if (Res.getNode()) {
1074 Chain = Res.getValue(1);
1077 // If this is an unaligned load and the target doesn't support
1079 EVT MemVT = LD->getMemoryVT();
1080 unsigned AS = LD->getAddressSpace();
1081 unsigned Align = LD->getAlignment();
1082 if (!TLI.allowsMisalignedMemoryAccesses(MemVT, AS, Align)) {
1083 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1084 unsigned ABIAlignment = TLI.getDataLayout()->getABITypeAlignment(Ty);
1085 if (Align < ABIAlignment){
1086 ExpandUnalignedLoad(cast<LoadSDNode>(Node), DAG, TLI, Value, Chain);
1092 case TargetLowering::Expand:
1093 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, Node->getValueType(0), SrcVT)) {
1094 // If the source type is not legal, see if there is a legal extload to
1095 // an intermediate type that we can then extend further.
1096 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT());
1097 if (TLI.isTypeLegal(SrcVT) || // Same as SrcVT == LoadVT?
1098 TLI.isLoadExtLegal(ExtType, LoadVT, SrcVT)) {
1099 // If we are loading a legal type, this is a non-extload followed by a
1101 ISD::LoadExtType MidExtType =
1102 (LoadVT == SrcVT) ? ISD::NON_EXTLOAD : ExtType;
1104 SDValue Load = DAG.getExtLoad(MidExtType, dl, LoadVT, Chain, Ptr,
1105 SrcVT, LD->getMemOperand());
1107 ISD::getExtForLoadExtType(SrcVT.isFloatingPoint(), ExtType);
1108 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1109 Chain = Load.getValue(1);
1114 assert(!SrcVT.isVector() &&
1115 "Vector Loads are handled in LegalizeVectorOps");
1117 // FIXME: This does not work for vectors on most targets. Sign-
1118 // and zero-extend operations are currently folded into extending
1119 // loads, whether they are legal or not, and then we end up here
1120 // without any support for legalizing them.
1121 assert(ExtType != ISD::EXTLOAD &&
1122 "EXTLOAD should always be supported!");
1123 // Turn the unsupported load into an EXTLOAD followed by an
1124 // explicit zero/sign extend inreg.
1125 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl,
1126 Node->getValueType(0),
1128 LD->getMemOperand());
1130 if (ExtType == ISD::SEXTLOAD)
1131 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1132 Result.getValueType(),
1133 Result, DAG.getValueType(SrcVT));
1135 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1137 Chain = Result.getValue(1);
1142 // Since loads produce two values, make sure to remember that we legalized
1144 if (Chain.getNode() != Node) {
1145 assert(Value.getNode() != Node && "Load must be completely replaced");
1146 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value);
1147 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
1149 UpdatedNodes->insert(Value.getNode());
1150 UpdatedNodes->insert(Chain.getNode());
1156 /// Return a legal replacement for the given operation, with all legal operands.
1157 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
1158 DEBUG(dbgs() << "\nLegalizing: "; Node->dump(&DAG));
1160 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
1163 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1164 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) ==
1165 TargetLowering::TypeLegal &&
1166 "Unexpected illegal type!");
1168 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1169 assert((TLI.getTypeAction(*DAG.getContext(),
1170 Node->getOperand(i).getValueType()) ==
1171 TargetLowering::TypeLegal ||
1172 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
1173 "Unexpected illegal type!");
1175 // Figure out the correct action; the way to query this varies by opcode
1176 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
1177 bool SimpleFinishLegalizing = true;
1178 switch (Node->getOpcode()) {
1179 case ISD::INTRINSIC_W_CHAIN:
1180 case ISD::INTRINSIC_WO_CHAIN:
1181 case ISD::INTRINSIC_VOID:
1182 case ISD::STACKSAVE:
1183 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1186 Action = TLI.getOperationAction(Node->getOpcode(),
1187 Node->getValueType(0));
1188 if (Action != TargetLowering::Promote)
1189 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
1191 case ISD::FP_TO_FP16:
1192 case ISD::SINT_TO_FP:
1193 case ISD::UINT_TO_FP:
1194 case ISD::EXTRACT_VECTOR_ELT:
1195 Action = TLI.getOperationAction(Node->getOpcode(),
1196 Node->getOperand(0).getValueType());
1198 case ISD::FP_ROUND_INREG:
1199 case ISD::SIGN_EXTEND_INREG: {
1200 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
1201 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
1204 case ISD::ATOMIC_STORE: {
1205 Action = TLI.getOperationAction(Node->getOpcode(),
1206 Node->getOperand(2).getValueType());
1209 case ISD::SELECT_CC:
1212 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
1213 Node->getOpcode() == ISD::SETCC ? 2 : 1;
1214 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
1215 MVT OpVT = Node->getOperand(CompareOperand).getSimpleValueType();
1216 ISD::CondCode CCCode =
1217 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
1218 Action = TLI.getCondCodeAction(CCCode, OpVT);
1219 if (Action == TargetLowering::Legal) {
1220 if (Node->getOpcode() == ISD::SELECT_CC)
1221 Action = TLI.getOperationAction(Node->getOpcode(),
1222 Node->getValueType(0));
1224 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
1230 // FIXME: Model these properly. LOAD and STORE are complicated, and
1231 // STORE expects the unlegalized operand in some cases.
1232 SimpleFinishLegalizing = false;
1234 case ISD::CALLSEQ_START:
1235 case ISD::CALLSEQ_END:
1236 // FIXME: This shouldn't be necessary. These nodes have special properties
1237 // dealing with the recursive nature of legalization. Removing this
1238 // special case should be done as part of making LegalizeDAG non-recursive.
1239 SimpleFinishLegalizing = false;
1241 case ISD::EXTRACT_ELEMENT:
1242 case ISD::FLT_ROUNDS_:
1250 case ISD::MERGE_VALUES:
1251 case ISD::EH_RETURN:
1252 case ISD::FRAME_TO_ARGS_OFFSET:
1253 case ISD::EH_SJLJ_SETJMP:
1254 case ISD::EH_SJLJ_LONGJMP:
1255 // These operations lie about being legal: when they claim to be legal,
1256 // they should actually be expanded.
1257 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1258 if (Action == TargetLowering::Legal)
1259 Action = TargetLowering::Expand;
1261 case ISD::INIT_TRAMPOLINE:
1262 case ISD::ADJUST_TRAMPOLINE:
1263 case ISD::FRAMEADDR:
1264 case ISD::RETURNADDR:
1265 // These operations lie about being legal: when they claim to be legal,
1266 // they should actually be custom-lowered.
1267 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1268 if (Action == TargetLowering::Legal)
1269 Action = TargetLowering::Custom;
1271 case ISD::READ_REGISTER:
1272 case ISD::WRITE_REGISTER:
1273 // Named register is legal in the DAG, but blocked by register name
1274 // selection if not implemented by target (to chose the correct register)
1275 // They'll be converted to Copy(To/From)Reg.
1276 Action = TargetLowering::Legal;
1278 case ISD::DEBUGTRAP:
1279 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1280 if (Action == TargetLowering::Expand) {
1281 // replace ISD::DEBUGTRAP with ISD::TRAP
1283 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
1284 Node->getOperand(0));
1285 ReplaceNode(Node, NewVal.getNode());
1286 LegalizeOp(NewVal.getNode());
1292 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1293 Action = TargetLowering::Legal;
1295 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
1300 if (SimpleFinishLegalizing) {
1301 SDNode *NewNode = Node;
1302 switch (Node->getOpcode()) {
1309 // Legalizing shifts/rotates requires adjusting the shift amount
1310 // to the appropriate width.
1311 if (!Node->getOperand(1).getValueType().isVector()) {
1313 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1314 Node->getOperand(1));
1315 HandleSDNode Handle(SAO);
1316 LegalizeOp(SAO.getNode());
1317 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1321 case ISD::SRL_PARTS:
1322 case ISD::SRA_PARTS:
1323 case ISD::SHL_PARTS:
1324 // Legalizing shifts/rotates requires adjusting the shift amount
1325 // to the appropriate width.
1326 if (!Node->getOperand(2).getValueType().isVector()) {
1328 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(),
1329 Node->getOperand(2));
1330 HandleSDNode Handle(SAO);
1331 LegalizeOp(SAO.getNode());
1332 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0),
1333 Node->getOperand(1),
1339 if (NewNode != Node) {
1340 ReplaceNode(Node, NewNode);
1344 case TargetLowering::Legal:
1346 case TargetLowering::Custom: {
1347 // FIXME: The handling for custom lowering with multiple results is
1349 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG);
1350 if (Res.getNode()) {
1351 if (!(Res.getNode() != Node || Res.getResNo() != 0))
1354 if (Node->getNumValues() == 1) {
1355 // We can just directly replace this node with the lowered value.
1356 ReplaceNode(SDValue(Node, 0), Res);
1360 SmallVector<SDValue, 8> ResultVals;
1361 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1362 ResultVals.push_back(Res.getValue(i));
1363 ReplaceNode(Node, ResultVals.data());
1368 case TargetLowering::Expand:
1371 case TargetLowering::Promote:
1377 switch (Node->getOpcode()) {
1384 llvm_unreachable("Do not know how to legalize this operator!");
1386 case ISD::CALLSEQ_START:
1387 case ISD::CALLSEQ_END:
1390 return LegalizeLoadOps(Node);
1393 return LegalizeStoreOps(Node);
1398 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1399 SDValue Vec = Op.getOperand(0);
1400 SDValue Idx = Op.getOperand(1);
1403 // Before we generate a new store to a temporary stack slot, see if there is
1404 // already one that we can use. There often is because when we scalarize
1405 // vector operations (using SelectionDAG::UnrollVectorOp for example) a whole
1406 // series of EXTRACT_VECTOR_ELT nodes are generated, one for each element in
1407 // the vector. If all are expanded here, we don't want one store per vector
1409 SDValue StackPtr, Ch;
1410 for (SDNode::use_iterator UI = Vec.getNode()->use_begin(),
1411 UE = Vec.getNode()->use_end(); UI != UE; ++UI) {
1413 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(User)) {
1414 if (ST->isIndexed() || ST->isTruncatingStore() ||
1415 ST->getValue() != Vec)
1418 // Make sure that nothing else could have stored into the destination of
1420 if (!ST->getChain().reachesChainWithoutSideEffects(DAG.getEntryNode()))
1423 StackPtr = ST->getBasePtr();
1424 Ch = SDValue(ST, 0);
1429 if (!Ch.getNode()) {
1430 // Store the value to a temporary stack slot, then LOAD the returned part.
1431 StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1432 Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1433 MachinePointerInfo(), false, false, 0);
1436 // Add the offset to the index.
1438 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1439 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1440 DAG.getConstant(EltSize, Idx.getValueType()));
1442 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1443 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1445 if (Op.getValueType().isVector())
1446 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1447 false, false, false, 0);
1448 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1449 MachinePointerInfo(),
1450 Vec.getValueType().getVectorElementType(),
1451 false, false, false, 0);
1454 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1455 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1457 SDValue Vec = Op.getOperand(0);
1458 SDValue Part = Op.getOperand(1);
1459 SDValue Idx = Op.getOperand(2);
1462 // Store the value to a temporary stack slot, then LOAD the returned part.
1464 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1465 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1466 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1468 // First store the whole vector.
1469 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1472 // Then store the inserted part.
1474 // Add the offset to the index.
1476 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1478 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1479 DAG.getConstant(EltSize, Idx.getValueType()));
1480 Idx = DAG.getZExtOrTrunc(Idx, dl, TLI.getPointerTy());
1482 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1485 // Store the subvector.
1486 Ch = DAG.getStore(Ch, dl, Part, SubStackPtr,
1487 MachinePointerInfo(), false, false, 0);
1489 // Finally, load the updated vector.
1490 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1491 false, false, false, 0);
1494 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1495 // We can't handle this case efficiently. Allocate a sufficiently
1496 // aligned object on the stack, store each element into it, then load
1497 // the result as a vector.
1498 // Create the stack frame object.
1499 EVT VT = Node->getValueType(0);
1500 EVT EltVT = VT.getVectorElementType();
1502 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1503 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1504 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1506 // Emit a store of each element to the stack slot.
1507 SmallVector<SDValue, 8> Stores;
1508 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1509 // Store (in the right endianness) the elements to memory.
1510 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1511 // Ignore undef elements.
1512 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1514 unsigned Offset = TypeByteSize*i;
1516 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1517 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1519 // If the destination vector element type is narrower than the source
1520 // element type, only store the bits necessary.
1521 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1522 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1523 Node->getOperand(i), Idx,
1524 PtrInfo.getWithOffset(Offset),
1525 EltVT, false, false, 0));
1527 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1528 Node->getOperand(i), Idx,
1529 PtrInfo.getWithOffset(Offset),
1534 if (!Stores.empty()) // Not all undef elements?
1535 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
1537 StoreChain = DAG.getEntryNode();
1539 // Result is a load from the stack slot.
1540 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1541 false, false, false, 0);
1544 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1546 SDValue Tmp1 = Node->getOperand(0);
1547 SDValue Tmp2 = Node->getOperand(1);
1549 // Get the sign bit of the RHS. First obtain a value that has the same
1550 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1552 EVT FloatVT = Tmp2.getValueType();
1553 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1554 if (TLI.isTypeLegal(IVT)) {
1555 // Convert to an integer with the same sign bit.
1556 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1558 // Store the float to memory, then load the sign part out as an integer.
1559 MVT LoadTy = TLI.getPointerTy();
1560 // First create a temporary that is aligned for both the load and store.
1561 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1562 // Then store the float to it.
1564 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1566 if (TLI.isBigEndian()) {
1567 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1568 // Load out a legal integer with the same sign bit as the float.
1569 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1570 false, false, false, 0);
1571 } else { // Little endian
1572 SDValue LoadPtr = StackPtr;
1573 // The float may be wider than the integer we are going to load. Advance
1574 // the pointer so that the loaded integer will contain the sign bit.
1575 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1576 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1577 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), LoadPtr,
1578 DAG.getConstant(ByteOffset, LoadPtr.getValueType()));
1579 // Load a legal integer containing the sign bit.
1580 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1581 false, false, false, 0);
1582 // Move the sign bit to the top bit of the loaded integer.
1583 unsigned BitShift = LoadTy.getSizeInBits() -
1584 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1585 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1587 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1588 DAG.getConstant(BitShift,
1589 TLI.getShiftAmountTy(SignBit.getValueType())));
1592 // Now get the sign bit proper, by seeing whether the value is negative.
1593 SignBit = DAG.getSetCC(dl, getSetCCResultType(SignBit.getValueType()),
1594 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1596 // Get the absolute value of the result.
1597 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1598 // Select between the nabs and abs value based on the sign bit of
1600 return DAG.getSelect(dl, AbsVal.getValueType(), SignBit,
1601 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1605 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1606 SmallVectorImpl<SDValue> &Results) {
1607 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1608 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1609 " not tell us which reg is the stack pointer!");
1611 EVT VT = Node->getValueType(0);
1612 SDValue Tmp1 = SDValue(Node, 0);
1613 SDValue Tmp2 = SDValue(Node, 1);
1614 SDValue Tmp3 = Node->getOperand(2);
1615 SDValue Chain = Tmp1.getOperand(0);
1617 // Chain the dynamic stack allocation so that it doesn't modify the stack
1618 // pointer when other instructions are using the stack.
1619 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),
1622 SDValue Size = Tmp2.getOperand(1);
1623 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1624 Chain = SP.getValue(1);
1625 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1626 unsigned StackAlign =
1627 DAG.getSubtarget().getFrameLowering()->getStackAlignment();
1628 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1629 if (Align > StackAlign)
1630 Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
1631 DAG.getConstant(-(uint64_t)Align, VT));
1632 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1634 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1635 DAG.getIntPtrConstant(0, true), SDValue(),
1638 Results.push_back(Tmp1);
1639 Results.push_back(Tmp2);
1642 /// Legalize a SETCC with given LHS and RHS and condition code CC on the current
1645 /// If the SETCC has been legalized using AND / OR, then the legalized node
1646 /// will be stored in LHS. RHS and CC will be set to SDValue(). NeedInvert
1647 /// will be set to false.
1649 /// If the SETCC has been legalized by using getSetCCSwappedOperands(),
1650 /// then the values of LHS and RHS will be swapped, CC will be set to the
1651 /// new condition, and NeedInvert will be set to false.
1653 /// If the SETCC has been legalized using the inverse condcode, then LHS and
1654 /// RHS will be unchanged, CC will set to the inverted condcode, and NeedInvert
1655 /// will be set to true. The caller must invert the result of the SETCC with
1656 /// SelectionDAG::getLogicalNOT() or take equivalent action to swap the effect
1657 /// of a true/false result.
1659 /// \returns true if the SetCC has been legalized, false if it hasn't.
1660 bool SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1661 SDValue &LHS, SDValue &RHS,
1665 MVT OpVT = LHS.getSimpleValueType();
1666 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1668 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1669 default: llvm_unreachable("Unknown condition code action!");
1670 case TargetLowering::Legal:
1673 case TargetLowering::Expand: {
1674 ISD::CondCode InvCC = ISD::getSetCCSwappedOperands(CCCode);
1675 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1676 std::swap(LHS, RHS);
1677 CC = DAG.getCondCode(InvCC);
1680 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1683 default: llvm_unreachable("Don't know how to expand this condition!");
1685 assert(TLI.getCondCodeAction(ISD::SETOEQ, OpVT)
1686 == TargetLowering::Legal
1687 && "If SETO is expanded, SETOEQ must be legal!");
1688 CC1 = ISD::SETOEQ; CC2 = ISD::SETOEQ; Opc = ISD::AND; break;
1690 assert(TLI.getCondCodeAction(ISD::SETUNE, OpVT)
1691 == TargetLowering::Legal
1692 && "If SETUO is expanded, SETUNE must be legal!");
1693 CC1 = ISD::SETUNE; CC2 = ISD::SETUNE; Opc = ISD::OR; break;
1706 // If we are floating point, assign and break, otherwise fall through.
1707 if (!OpVT.isInteger()) {
1708 // We can use the 4th bit to tell if we are the unordered
1709 // or ordered version of the opcode.
1710 CC2 = ((unsigned)CCCode & 0x8U) ? ISD::SETUO : ISD::SETO;
1711 Opc = ((unsigned)CCCode & 0x8U) ? ISD::OR : ISD::AND;
1712 CC1 = (ISD::CondCode)(((int)CCCode & 0x7) | 0x10);
1715 // Fallthrough if we are unsigned integer.
1720 // We only support using the inverted operation, which is computed above
1721 // and not a different manner of supporting expanding these cases.
1722 llvm_unreachable("Don't know how to expand this condition!");
1725 // Try inverting the result of the inverse condition.
1726 InvCC = CCCode == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ;
1727 if (TLI.isCondCodeLegal(InvCC, OpVT)) {
1728 CC = DAG.getCondCode(InvCC);
1732 // If inverting the condition didn't work then we have no means to expand
1734 llvm_unreachable("Don't know how to expand this condition!");
1737 SDValue SetCC1, SetCC2;
1738 if (CCCode != ISD::SETO && CCCode != ISD::SETUO) {
1739 // If we aren't the ordered or unorder operation,
1740 // then the pattern is (LHS CC1 RHS) Opc (LHS CC2 RHS).
1741 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1742 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1744 // Otherwise, the pattern is (LHS CC1 LHS) Opc (RHS CC2 RHS)
1745 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1746 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1748 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1757 /// Emit a store/load combination to the stack. This stores
1758 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1759 /// a load from the stack slot to DestVT, extending it if needed.
1760 /// The resultant code need not be legal.
1761 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1765 // Create the stack frame object.
1767 TLI.getDataLayout()->getPrefTypeAlignment(SrcOp.getValueType().
1768 getTypeForEVT(*DAG.getContext()));
1769 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1771 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1772 int SPFI = StackPtrFI->getIndex();
1773 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
1775 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1776 unsigned SlotSize = SlotVT.getSizeInBits();
1777 unsigned DestSize = DestVT.getSizeInBits();
1778 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
1779 unsigned DestAlign = TLI.getDataLayout()->getPrefTypeAlignment(DestType);
1781 // Emit a store to the stack slot. Use a truncstore if the input value is
1782 // later than DestVT.
1785 if (SrcSize > SlotSize)
1786 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1787 PtrInfo, SlotVT, false, false, SrcAlign);
1789 assert(SrcSize == SlotSize && "Invalid store");
1790 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1791 PtrInfo, false, false, SrcAlign);
1794 // Result is a load from the stack slot.
1795 if (SlotSize == DestSize)
1796 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
1797 false, false, false, DestAlign);
1799 assert(SlotSize < DestSize && "Unknown extension!");
1800 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
1801 PtrInfo, SlotVT, false, false, false, DestAlign);
1804 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1806 // Create a vector sized/aligned stack slot, store the value to element #0,
1807 // then load the whole vector back out.
1808 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1810 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1811 int SPFI = StackPtrFI->getIndex();
1813 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1815 MachinePointerInfo::getFixedStack(SPFI),
1816 Node->getValueType(0).getVectorElementType(),
1818 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1819 MachinePointerInfo::getFixedStack(SPFI),
1820 false, false, false, 0);
1824 ExpandBVWithShuffles(SDNode *Node, SelectionDAG &DAG,
1825 const TargetLowering &TLI, SDValue &Res) {
1826 unsigned NumElems = Node->getNumOperands();
1828 EVT VT = Node->getValueType(0);
1830 // Try to group the scalars into pairs, shuffle the pairs together, then
1831 // shuffle the pairs of pairs together, etc. until the vector has
1832 // been built. This will work only if all of the necessary shuffle masks
1835 // We do this in two phases; first to check the legality of the shuffles,
1836 // and next, assuming that all shuffles are legal, to create the new nodes.
1837 for (int Phase = 0; Phase < 2; ++Phase) {
1838 SmallVector<std::pair<SDValue, SmallVector<int, 16> >, 16> IntermedVals,
1840 for (unsigned i = 0; i < NumElems; ++i) {
1841 SDValue V = Node->getOperand(i);
1842 if (V.getOpcode() == ISD::UNDEF)
1847 Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, V);
1848 IntermedVals.push_back(std::make_pair(Vec, SmallVector<int, 16>(1, i)));
1851 while (IntermedVals.size() > 2) {
1852 NewIntermedVals.clear();
1853 for (unsigned i = 0, e = (IntermedVals.size() & ~1u); i < e; i += 2) {
1854 // This vector and the next vector are shuffled together (simply to
1855 // append the one to the other).
1856 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1858 SmallVector<int, 16> FinalIndices;
1859 FinalIndices.reserve(IntermedVals[i].second.size() +
1860 IntermedVals[i+1].second.size());
1863 for (unsigned j = 0, f = IntermedVals[i].second.size(); j != f;
1866 FinalIndices.push_back(IntermedVals[i].second[j]);
1868 for (unsigned j = 0, f = IntermedVals[i+1].second.size(); j != f;
1870 ShuffleVec[k] = NumElems + j;
1871 FinalIndices.push_back(IntermedVals[i+1].second[j]);
1876 Shuffle = DAG.getVectorShuffle(VT, dl, IntermedVals[i].first,
1877 IntermedVals[i+1].first,
1879 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1881 NewIntermedVals.push_back(
1882 std::make_pair(Shuffle, std::move(FinalIndices)));
1885 // If we had an odd number of defined values, then append the last
1886 // element to the array of new vectors.
1887 if ((IntermedVals.size() & 1) != 0)
1888 NewIntermedVals.push_back(IntermedVals.back());
1890 IntermedVals.swap(NewIntermedVals);
1893 assert(IntermedVals.size() <= 2 && IntermedVals.size() > 0 &&
1894 "Invalid number of intermediate vectors");
1895 SDValue Vec1 = IntermedVals[0].first;
1897 if (IntermedVals.size() > 1)
1898 Vec2 = IntermedVals[1].first;
1900 Vec2 = DAG.getUNDEF(VT);
1902 SmallVector<int, 16> ShuffleVec(NumElems, -1);
1903 for (unsigned i = 0, e = IntermedVals[0].second.size(); i != e; ++i)
1904 ShuffleVec[IntermedVals[0].second[i]] = i;
1905 for (unsigned i = 0, e = IntermedVals[1].second.size(); i != e; ++i)
1906 ShuffleVec[IntermedVals[1].second[i]] = NumElems + i;
1909 Res = DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1910 else if (!TLI.isShuffleMaskLegal(ShuffleVec, VT))
1917 /// Expand a BUILD_VECTOR node on targets that don't
1918 /// support the operation, but do support the resultant vector type.
1919 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1920 unsigned NumElems = Node->getNumOperands();
1921 SDValue Value1, Value2;
1923 EVT VT = Node->getValueType(0);
1924 EVT OpVT = Node->getOperand(0).getValueType();
1925 EVT EltVT = VT.getVectorElementType();
1927 // If the only non-undef value is the low element, turn this into a
1928 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1929 bool isOnlyLowElement = true;
1930 bool MoreThanTwoValues = false;
1931 bool isConstant = true;
1932 for (unsigned i = 0; i < NumElems; ++i) {
1933 SDValue V = Node->getOperand(i);
1934 if (V.getOpcode() == ISD::UNDEF)
1937 isOnlyLowElement = false;
1938 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1941 if (!Value1.getNode()) {
1943 } else if (!Value2.getNode()) {
1946 } else if (V != Value1 && V != Value2) {
1947 MoreThanTwoValues = true;
1951 if (!Value1.getNode())
1952 return DAG.getUNDEF(VT);
1954 if (isOnlyLowElement)
1955 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1957 // If all elements are constants, create a load from the constant pool.
1959 SmallVector<Constant*, 16> CV;
1960 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1961 if (ConstantFPSDNode *V =
1962 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1963 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1964 } else if (ConstantSDNode *V =
1965 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1967 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1969 // If OpVT and EltVT don't match, EltVT is not legal and the
1970 // element values have been promoted/truncated earlier. Undo this;
1971 // we don't want a v16i8 to become a v16i32 for example.
1972 const ConstantInt *CI = V->getConstantIntValue();
1973 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
1974 CI->getZExtValue()));
1977 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1978 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
1979 CV.push_back(UndefValue::get(OpNTy));
1982 Constant *CP = ConstantVector::get(CV);
1983 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1984 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1985 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1986 MachinePointerInfo::getConstantPool(),
1987 false, false, false, Alignment);
1990 SmallSet<SDValue, 16> DefinedValues;
1991 for (unsigned i = 0; i < NumElems; ++i) {
1992 if (Node->getOperand(i).getOpcode() == ISD::UNDEF)
1994 DefinedValues.insert(Node->getOperand(i));
1997 if (TLI.shouldExpandBuildVectorWithShuffles(VT, DefinedValues.size())) {
1998 if (!MoreThanTwoValues) {
1999 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2000 for (unsigned i = 0; i < NumElems; ++i) {
2001 SDValue V = Node->getOperand(i);
2002 if (V.getOpcode() == ISD::UNDEF)
2004 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2006 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2007 // Get the splatted value into the low element of a vector register.
2008 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2010 if (Value2.getNode())
2011 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2013 Vec2 = DAG.getUNDEF(VT);
2015 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2016 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2020 if (ExpandBVWithShuffles(Node, DAG, TLI, Res))
2025 // Otherwise, we can't handle this case efficiently.
2026 return ExpandVectorBuildThroughStack(Node);
2029 // Expand a node into a call to a libcall. If the result value
2030 // does not fit into a register, return the lo part and set the hi part to the
2031 // by-reg argument. If it does fit into a single register, return the result
2032 // and leave the Hi part unset.
2033 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2035 TargetLowering::ArgListTy Args;
2036 TargetLowering::ArgListEntry Entry;
2037 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2038 EVT ArgVT = Node->getOperand(i).getValueType();
2039 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2040 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2041 Entry.isSExt = isSigned;
2042 Entry.isZExt = !isSigned;
2043 Args.push_back(Entry);
2045 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2046 TLI.getPointerTy());
2048 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2050 // By default, the input chain to this libcall is the entry node of the
2051 // function. If the libcall is going to be emitted as a tail call then
2052 // TLI.isUsedByReturnOnly will change it to the right chain if the return
2053 // node which is being folded has a non-entry input chain.
2054 SDValue InChain = DAG.getEntryNode();
2056 // isTailCall may be true since the callee does not reference caller stack
2057 // frame. Check if it's in the right position.
2058 SDValue TCChain = InChain;
2059 bool isTailCall = TLI.isInTailCallPosition(DAG, Node, TCChain);
2063 TargetLowering::CallLoweringInfo CLI(DAG);
2064 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2065 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2066 .setTailCall(isTailCall).setSExtResult(isSigned).setZExtResult(!isSigned);
2068 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2070 if (!CallInfo.second.getNode())
2071 // It's a tailcall, return the chain (which is the DAG root).
2072 return DAG.getRoot();
2074 return CallInfo.first;
2077 /// Generate a libcall taking the given operands as arguments
2078 /// and returning a result of type RetVT.
2079 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2080 const SDValue *Ops, unsigned NumOps,
2081 bool isSigned, SDLoc dl) {
2082 TargetLowering::ArgListTy Args;
2083 Args.reserve(NumOps);
2085 TargetLowering::ArgListEntry Entry;
2086 for (unsigned i = 0; i != NumOps; ++i) {
2087 Entry.Node = Ops[i];
2088 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2089 Entry.isSExt = isSigned;
2090 Entry.isZExt = !isSigned;
2091 Args.push_back(Entry);
2093 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2094 TLI.getPointerTy());
2096 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2098 TargetLowering::CallLoweringInfo CLI(DAG);
2099 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
2100 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2101 .setSExtResult(isSigned).setZExtResult(!isSigned);
2103 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI);
2105 return CallInfo.first;
2108 // Expand a node into a call to a libcall. Similar to
2109 // ExpandLibCall except that the first operand is the in-chain.
2110 std::pair<SDValue, SDValue>
2111 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2114 SDValue InChain = Node->getOperand(0);
2116 TargetLowering::ArgListTy Args;
2117 TargetLowering::ArgListEntry Entry;
2118 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2119 EVT ArgVT = Node->getOperand(i).getValueType();
2120 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2121 Entry.Node = Node->getOperand(i);
2123 Entry.isSExt = isSigned;
2124 Entry.isZExt = !isSigned;
2125 Args.push_back(Entry);
2127 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2128 TLI.getPointerTy());
2130 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2132 TargetLowering::CallLoweringInfo CLI(DAG);
2133 CLI.setDebugLoc(SDLoc(Node)).setChain(InChain)
2134 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2135 .setSExtResult(isSigned).setZExtResult(!isSigned);
2137 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2142 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2143 RTLIB::Libcall Call_F32,
2144 RTLIB::Libcall Call_F64,
2145 RTLIB::Libcall Call_F80,
2146 RTLIB::Libcall Call_F128,
2147 RTLIB::Libcall Call_PPCF128) {
2149 switch (Node->getSimpleValueType(0).SimpleTy) {
2150 default: llvm_unreachable("Unexpected request for libcall!");
2151 case MVT::f32: LC = Call_F32; break;
2152 case MVT::f64: LC = Call_F64; break;
2153 case MVT::f80: LC = Call_F80; break;
2154 case MVT::f128: LC = Call_F128; break;
2155 case MVT::ppcf128: LC = Call_PPCF128; break;
2157 return ExpandLibCall(LC, Node, false);
2160 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2161 RTLIB::Libcall Call_I8,
2162 RTLIB::Libcall Call_I16,
2163 RTLIB::Libcall Call_I32,
2164 RTLIB::Libcall Call_I64,
2165 RTLIB::Libcall Call_I128) {
2167 switch (Node->getSimpleValueType(0).SimpleTy) {
2168 default: llvm_unreachable("Unexpected request for libcall!");
2169 case MVT::i8: LC = Call_I8; break;
2170 case MVT::i16: LC = Call_I16; break;
2171 case MVT::i32: LC = Call_I32; break;
2172 case MVT::i64: LC = Call_I64; break;
2173 case MVT::i128: LC = Call_I128; break;
2175 return ExpandLibCall(LC, Node, isSigned);
2178 /// Return true if divmod libcall is available.
2179 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2180 const TargetLowering &TLI) {
2182 switch (Node->getSimpleValueType(0).SimpleTy) {
2183 default: llvm_unreachable("Unexpected request for libcall!");
2184 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2185 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2186 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2187 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2188 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2191 return TLI.getLibcallName(LC) != nullptr;
2194 /// Only issue divrem libcall if both quotient and remainder are needed.
2195 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2196 // The other use might have been replaced with a divrem already.
2197 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2198 unsigned OtherOpcode = 0;
2200 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2202 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2204 SDValue Op0 = Node->getOperand(0);
2205 SDValue Op1 = Node->getOperand(1);
2206 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2207 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2211 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) &&
2212 User->getOperand(0) == Op0 &&
2213 User->getOperand(1) == Op1)
2219 /// Issue libcalls to __{u}divmod to compute div / rem pairs.
2221 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2222 SmallVectorImpl<SDValue> &Results) {
2223 unsigned Opcode = Node->getOpcode();
2224 bool isSigned = Opcode == ISD::SDIVREM;
2227 switch (Node->getSimpleValueType(0).SimpleTy) {
2228 default: llvm_unreachable("Unexpected request for libcall!");
2229 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2230 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2231 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2232 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2233 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2236 // The input chain to this libcall is the entry node of the function.
2237 // Legalizing the call will automatically add the previous call to the
2239 SDValue InChain = DAG.getEntryNode();
2241 EVT RetVT = Node->getValueType(0);
2242 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2244 TargetLowering::ArgListTy Args;
2245 TargetLowering::ArgListEntry Entry;
2246 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2247 EVT ArgVT = Node->getOperand(i).getValueType();
2248 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2249 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2250 Entry.isSExt = isSigned;
2251 Entry.isZExt = !isSigned;
2252 Args.push_back(Entry);
2255 // Also pass the return address of the remainder.
2256 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2258 Entry.Ty = RetTy->getPointerTo();
2259 Entry.isSExt = isSigned;
2260 Entry.isZExt = !isSigned;
2261 Args.push_back(Entry);
2263 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2264 TLI.getPointerTy());
2267 TargetLowering::CallLoweringInfo CLI(DAG);
2268 CLI.setDebugLoc(dl).setChain(InChain)
2269 .setCallee(TLI.getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
2270 .setSExtResult(isSigned).setZExtResult(!isSigned);
2272 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2274 // Remainder is loaded back from the stack frame.
2275 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
2276 MachinePointerInfo(), false, false, false, 0);
2277 Results.push_back(CallInfo.first);
2278 Results.push_back(Rem);
2281 /// Return true if sincos libcall is available.
2282 static bool isSinCosLibcallAvailable(SDNode *Node, const TargetLowering &TLI) {
2284 switch (Node->getSimpleValueType(0).SimpleTy) {
2285 default: llvm_unreachable("Unexpected request for libcall!");
2286 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2287 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2288 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2289 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2290 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2292 return TLI.getLibcallName(LC) != nullptr;
2295 /// Return true if sincos libcall is available and can be used to combine sin
2297 static bool canCombineSinCosLibcall(SDNode *Node, const TargetLowering &TLI,
2298 const TargetMachine &TM) {
2299 if (!isSinCosLibcallAvailable(Node, TLI))
2301 // GNU sin/cos functions set errno while sincos does not. Therefore
2302 // combining sin and cos is only safe if unsafe-fpmath is enabled.
2303 bool isGNU = Triple(TM.getTargetTriple()).getEnvironment() == Triple::GNU;
2304 if (isGNU && !TM.Options.UnsafeFPMath)
2309 /// Only issue sincos libcall if both sin and cos are needed.
2310 static bool useSinCos(SDNode *Node) {
2311 unsigned OtherOpcode = Node->getOpcode() == ISD::FSIN
2312 ? ISD::FCOS : ISD::FSIN;
2314 SDValue Op0 = Node->getOperand(0);
2315 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2316 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2320 // The other user might have been turned into sincos already.
2321 if (User->getOpcode() == OtherOpcode || User->getOpcode() == ISD::FSINCOS)
2327 /// Issue libcalls to sincos to compute sin / cos pairs.
2329 SelectionDAGLegalize::ExpandSinCosLibCall(SDNode *Node,
2330 SmallVectorImpl<SDValue> &Results) {
2332 switch (Node->getSimpleValueType(0).SimpleTy) {
2333 default: llvm_unreachable("Unexpected request for libcall!");
2334 case MVT::f32: LC = RTLIB::SINCOS_F32; break;
2335 case MVT::f64: LC = RTLIB::SINCOS_F64; break;
2336 case MVT::f80: LC = RTLIB::SINCOS_F80; break;
2337 case MVT::f128: LC = RTLIB::SINCOS_F128; break;
2338 case MVT::ppcf128: LC = RTLIB::SINCOS_PPCF128; break;
2341 // The input chain to this libcall is the entry node of the function.
2342 // Legalizing the call will automatically add the previous call to the
2344 SDValue InChain = DAG.getEntryNode();
2346 EVT RetVT = Node->getValueType(0);
2347 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2349 TargetLowering::ArgListTy Args;
2350 TargetLowering::ArgListEntry Entry;
2352 // Pass the argument.
2353 Entry.Node = Node->getOperand(0);
2355 Entry.isSExt = false;
2356 Entry.isZExt = false;
2357 Args.push_back(Entry);
2359 // Pass the return address of sin.
2360 SDValue SinPtr = DAG.CreateStackTemporary(RetVT);
2361 Entry.Node = SinPtr;
2362 Entry.Ty = RetTy->getPointerTo();
2363 Entry.isSExt = false;
2364 Entry.isZExt = false;
2365 Args.push_back(Entry);
2367 // Also pass the return address of the cos.
2368 SDValue CosPtr = DAG.CreateStackTemporary(RetVT);
2369 Entry.Node = CosPtr;
2370 Entry.Ty = RetTy->getPointerTo();
2371 Entry.isSExt = false;
2372 Entry.isZExt = false;
2373 Args.push_back(Entry);
2375 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2376 TLI.getPointerTy());
2379 TargetLowering::CallLoweringInfo CLI(DAG);
2380 CLI.setDebugLoc(dl).setChain(InChain)
2381 .setCallee(TLI.getLibcallCallingConv(LC),
2382 Type::getVoidTy(*DAG.getContext()), Callee, std::move(Args), 0);
2384 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI);
2386 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, SinPtr,
2387 MachinePointerInfo(), false, false, false, 0));
2388 Results.push_back(DAG.getLoad(RetVT, dl, CallInfo.second, CosPtr,
2389 MachinePointerInfo(), false, false, false, 0));
2392 /// This function is responsible for legalizing a
2393 /// INT_TO_FP operation of the specified operand when the target requests that
2394 /// we expand it. At this point, we know that the result and operand types are
2395 /// legal for the target.
2396 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2400 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
2401 // simple 32-bit [signed|unsigned] integer to float/double expansion
2403 // Get the stack frame index of a 8 byte buffer.
2404 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2406 // word offset constant for Hi/Lo address computation
2407 SDValue WordOff = DAG.getConstant(sizeof(int), StackSlot.getValueType());
2408 // set up Hi and Lo (into buffer) address based on endian
2409 SDValue Hi = StackSlot;
2410 SDValue Lo = DAG.getNode(ISD::ADD, dl, StackSlot.getValueType(),
2411 StackSlot, WordOff);
2412 if (TLI.isLittleEndian())
2415 // if signed map to unsigned space
2418 // constant used to invert sign bit (signed to unsigned mapping)
2419 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2420 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2424 // store the lo of the constructed double - based on integer input
2425 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2426 Op0Mapped, Lo, MachinePointerInfo(),
2428 // initial hi portion of constructed double
2429 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2430 // store the hi of the constructed double - biased exponent
2431 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2432 MachinePointerInfo(),
2434 // load the constructed double
2435 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2436 MachinePointerInfo(), false, false, false, 0);
2437 // FP constant to bias correct the final result
2438 SDValue Bias = DAG.getConstantFP(isSigned ?
2439 BitsToDouble(0x4330000080000000ULL) :
2440 BitsToDouble(0x4330000000000000ULL),
2442 // subtract the bias
2443 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2446 // handle final rounding
2447 if (DestVT == MVT::f64) {
2450 } else if (DestVT.bitsLT(MVT::f64)) {
2451 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2452 DAG.getIntPtrConstant(0));
2453 } else if (DestVT.bitsGT(MVT::f64)) {
2454 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2458 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2459 // Code below here assumes !isSigned without checking again.
2461 // Implementation of unsigned i64 to f64 following the algorithm in
2462 // __floatundidf in compiler_rt. This implementation has the advantage
2463 // of performing rounding correctly, both in the default rounding mode
2464 // and in all alternate rounding modes.
2465 // TODO: Generalize this for use with other types.
2466 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2468 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2469 SDValue TwoP84PlusTwoP52 =
2470 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2472 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2474 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2475 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2476 DAG.getConstant(32, MVT::i64));
2477 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2478 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2479 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2480 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2481 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2483 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2486 // Implementation of unsigned i64 to f32.
2487 // TODO: Generalize this for use with other types.
2488 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2489 // For unsigned conversions, convert them to signed conversions using the
2490 // algorithm from the x86_64 __floatundidf in compiler_rt.
2492 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2494 SDValue ShiftConst =
2495 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2496 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2497 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2498 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2499 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2501 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2502 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2504 // TODO: This really should be implemented using a branch rather than a
2505 // select. We happen to get lucky and machinesink does the right
2506 // thing most of the time. This would be a good candidate for a
2507 //pseudo-op, or, even better, for whole-function isel.
2508 SDValue SignBitTest = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2509 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2510 return DAG.getSelect(dl, MVT::f32, SignBitTest, Slow, Fast);
2513 // Otherwise, implement the fully general conversion.
2515 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2516 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2517 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2518 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2519 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2520 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2521 SDValue Ne = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2522 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2523 SDValue Sel = DAG.getSelect(dl, MVT::i64, Ne, Or, Op0);
2524 SDValue Ge = DAG.getSetCC(dl, getSetCCResultType(MVT::i64),
2525 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2527 SDValue Sel2 = DAG.getSelect(dl, MVT::i64, Ge, Sel, Op0);
2528 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2530 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2531 DAG.getConstant(32, SHVT));
2532 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2533 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2535 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2536 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2537 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2538 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2539 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2540 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2541 DAG.getIntPtrConstant(0));
2544 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2546 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
2547 Op0, DAG.getConstant(0, Op0.getValueType()),
2549 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2550 SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
2551 SignSet, Four, Zero);
2553 // If the sign bit of the integer is set, the large number will be treated
2554 // as a negative number. To counteract this, the dynamic code adds an
2555 // offset depending on the data type.
2557 switch (Op0.getSimpleValueType().SimpleTy) {
2558 default: llvm_unreachable("Unsupported integer type!");
2559 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2560 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2561 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2562 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2564 if (TLI.isLittleEndian()) FF <<= 32;
2565 Constant *FudgeFactor = ConstantInt::get(
2566 Type::getInt64Ty(*DAG.getContext()), FF);
2568 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2569 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2570 CPIdx = DAG.getNode(ISD::ADD, dl, CPIdx.getValueType(), CPIdx, CstOffset);
2571 Alignment = std::min(Alignment, 4u);
2573 if (DestVT == MVT::f32)
2574 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2575 MachinePointerInfo::getConstantPool(),
2576 false, false, false, Alignment);
2578 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2579 DAG.getEntryNode(), CPIdx,
2580 MachinePointerInfo::getConstantPool(),
2581 MVT::f32, false, false, false, Alignment);
2582 HandleSDNode Handle(Load);
2583 LegalizeOp(Load.getNode());
2584 FudgeInReg = Handle.getValue();
2587 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2590 /// This function is responsible for legalizing a
2591 /// *INT_TO_FP operation of the specified operand when the target requests that
2592 /// we promote it. At this point, we know that the result and operand types are
2593 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2594 /// operation that takes a larger input.
2595 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2599 // First step, figure out the appropriate *INT_TO_FP operation to use.
2600 EVT NewInTy = LegalOp.getValueType();
2602 unsigned OpToUse = 0;
2604 // Scan for the appropriate larger type to use.
2606 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2607 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2609 // If the target supports SINT_TO_FP of this type, use it.
2610 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2611 OpToUse = ISD::SINT_TO_FP;
2614 if (isSigned) continue;
2616 // If the target supports UINT_TO_FP of this type, use it.
2617 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2618 OpToUse = ISD::UINT_TO_FP;
2622 // Otherwise, try a larger type.
2625 // Okay, we found the operation and type to use. Zero extend our input to the
2626 // desired type then run the operation on it.
2627 return DAG.getNode(OpToUse, dl, DestVT,
2628 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2629 dl, NewInTy, LegalOp));
2632 /// This function is responsible for legalizing a
2633 /// FP_TO_*INT operation of the specified operand when the target requests that
2634 /// we promote it. At this point, we know that the result and operand types are
2635 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2636 /// operation that returns a larger result.
2637 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2641 // First step, figure out the appropriate FP_TO*INT operation to use.
2642 EVT NewOutTy = DestVT;
2644 unsigned OpToUse = 0;
2646 // Scan for the appropriate larger type to use.
2648 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2649 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2651 // A larger signed type can hold all unsigned values of the requested type,
2652 // so using FP_TO_SINT is valid
2653 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2654 OpToUse = ISD::FP_TO_SINT;
2658 // However, if the value may be < 0.0, we *must* use some FP_TO_SINT.
2659 if (!isSigned && TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2660 OpToUse = ISD::FP_TO_UINT;
2664 // Otherwise, try a larger type.
2668 // Okay, we found the operation and type to use.
2669 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2671 // Truncate the result of the extended FP_TO_*INT operation to the desired
2673 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2676 /// Open code the operations for BSWAP of the specified operation.
2677 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, SDLoc dl) {
2678 EVT VT = Op.getValueType();
2679 EVT SHVT = TLI.getShiftAmountTy(VT);
2680 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2681 switch (VT.getSimpleVT().SimpleTy) {
2682 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2684 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2685 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2686 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2688 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2689 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2690 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2691 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2692 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2693 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2694 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2695 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2696 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2698 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2699 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2700 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2701 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2702 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2703 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2704 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2705 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2706 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2707 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2708 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2709 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2710 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2711 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2712 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2713 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2714 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2715 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2716 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2717 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2718 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2722 /// Expand the specified bitcount instruction into operations.
2723 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2726 default: llvm_unreachable("Cannot expand this yet!");
2728 EVT VT = Op.getValueType();
2729 EVT ShVT = TLI.getShiftAmountTy(VT);
2730 unsigned Len = VT.getSizeInBits();
2732 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2733 "CTPOP not implemented for this type.");
2735 // This is the "best" algorithm from
2736 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2738 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2739 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2740 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2741 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2743 // v = v - ((v >> 1) & 0x55555555...)
2744 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2745 DAG.getNode(ISD::AND, dl, VT,
2746 DAG.getNode(ISD::SRL, dl, VT, Op,
2747 DAG.getConstant(1, ShVT)),
2749 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2750 Op = DAG.getNode(ISD::ADD, dl, VT,
2751 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2752 DAG.getNode(ISD::AND, dl, VT,
2753 DAG.getNode(ISD::SRL, dl, VT, Op,
2754 DAG.getConstant(2, ShVT)),
2756 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2757 Op = DAG.getNode(ISD::AND, dl, VT,
2758 DAG.getNode(ISD::ADD, dl, VT, Op,
2759 DAG.getNode(ISD::SRL, dl, VT, Op,
2760 DAG.getConstant(4, ShVT))),
2762 // v = (v * 0x01010101...) >> (Len - 8)
2763 Op = DAG.getNode(ISD::SRL, dl, VT,
2764 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2765 DAG.getConstant(Len - 8, ShVT));
2769 case ISD::CTLZ_ZERO_UNDEF:
2770 // This trivially expands to CTLZ.
2771 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op);
2773 // for now, we do this:
2774 // x = x | (x >> 1);
2775 // x = x | (x >> 2);
2777 // x = x | (x >>16);
2778 // x = x | (x >>32); // for 64-bit input
2779 // return popcount(~x);
2781 // Ref: "Hacker's Delight" by Henry Warren
2782 EVT VT = Op.getValueType();
2783 EVT ShVT = TLI.getShiftAmountTy(VT);
2784 unsigned len = VT.getSizeInBits();
2785 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2786 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2787 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2788 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2790 Op = DAG.getNOT(dl, Op, VT);
2791 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2793 case ISD::CTTZ_ZERO_UNDEF:
2794 // This trivially expands to CTTZ.
2795 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op);
2797 // for now, we use: { return popcount(~x & (x - 1)); }
2798 // unless the target has ctlz but not ctpop, in which case we use:
2799 // { return 32 - nlz(~x & (x-1)); }
2800 // Ref: "Hacker's Delight" by Henry Warren
2801 EVT VT = Op.getValueType();
2802 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2803 DAG.getNOT(dl, Op, VT),
2804 DAG.getNode(ISD::SUB, dl, VT, Op,
2805 DAG.getConstant(1, VT)));
2806 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2807 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2808 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2809 return DAG.getNode(ISD::SUB, dl, VT,
2810 DAG.getConstant(VT.getSizeInBits(), VT),
2811 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2812 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2817 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2818 unsigned Opc = Node->getOpcode();
2819 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2824 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2825 case ISD::ATOMIC_SWAP:
2826 switch (VT.SimpleTy) {
2827 default: llvm_unreachable("Unexpected value type for atomic!");
2828 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2829 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2830 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2831 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2832 case MVT::i128:LC = RTLIB::SYNC_LOCK_TEST_AND_SET_16;break;
2835 case ISD::ATOMIC_CMP_SWAP:
2836 switch (VT.SimpleTy) {
2837 default: llvm_unreachable("Unexpected value type for atomic!");
2838 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2839 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2840 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2841 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2842 case MVT::i128:LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16;break;
2845 case ISD::ATOMIC_LOAD_ADD:
2846 switch (VT.SimpleTy) {
2847 default: llvm_unreachable("Unexpected value type for atomic!");
2848 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2849 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2850 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2851 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2852 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_ADD_16;break;
2855 case ISD::ATOMIC_LOAD_SUB:
2856 switch (VT.SimpleTy) {
2857 default: llvm_unreachable("Unexpected value type for atomic!");
2858 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2859 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2860 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2861 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2862 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_SUB_16;break;
2865 case ISD::ATOMIC_LOAD_AND:
2866 switch (VT.SimpleTy) {
2867 default: llvm_unreachable("Unexpected value type for atomic!");
2868 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2869 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2870 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2871 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2872 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_AND_16;break;
2875 case ISD::ATOMIC_LOAD_OR:
2876 switch (VT.SimpleTy) {
2877 default: llvm_unreachable("Unexpected value type for atomic!");
2878 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2879 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2880 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2881 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2882 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_OR_16;break;
2885 case ISD::ATOMIC_LOAD_XOR:
2886 switch (VT.SimpleTy) {
2887 default: llvm_unreachable("Unexpected value type for atomic!");
2888 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2889 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2890 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2891 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2892 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_XOR_16;break;
2895 case ISD::ATOMIC_LOAD_NAND:
2896 switch (VT.SimpleTy) {
2897 default: llvm_unreachable("Unexpected value type for atomic!");
2898 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2899 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2900 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2901 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2902 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_NAND_16;break;
2905 case ISD::ATOMIC_LOAD_MAX:
2906 switch (VT.SimpleTy) {
2907 default: llvm_unreachable("Unexpected value type for atomic!");
2908 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MAX_1; break;
2909 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MAX_2; break;
2910 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MAX_4; break;
2911 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MAX_8; break;
2912 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MAX_16;break;
2915 case ISD::ATOMIC_LOAD_UMAX:
2916 switch (VT.SimpleTy) {
2917 default: llvm_unreachable("Unexpected value type for atomic!");
2918 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMAX_1; break;
2919 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMAX_2; break;
2920 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMAX_4; break;
2921 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMAX_8; break;
2922 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMAX_16;break;
2925 case ISD::ATOMIC_LOAD_MIN:
2926 switch (VT.SimpleTy) {
2927 default: llvm_unreachable("Unexpected value type for atomic!");
2928 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_MIN_1; break;
2929 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_MIN_2; break;
2930 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_MIN_4; break;
2931 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_MIN_8; break;
2932 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_MIN_16;break;
2935 case ISD::ATOMIC_LOAD_UMIN:
2936 switch (VT.SimpleTy) {
2937 default: llvm_unreachable("Unexpected value type for atomic!");
2938 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_UMIN_1; break;
2939 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_UMIN_2; break;
2940 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_UMIN_4; break;
2941 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_UMIN_8; break;
2942 case MVT::i128:LC = RTLIB::SYNC_FETCH_AND_UMIN_16;break;
2947 return ExpandChainLibCall(LC, Node, false);
2950 void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
2951 SmallVector<SDValue, 8> Results;
2953 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2955 switch (Node->getOpcode()) {
2958 case ISD::CTLZ_ZERO_UNDEF:
2960 case ISD::CTTZ_ZERO_UNDEF:
2961 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2962 Results.push_back(Tmp1);
2965 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2967 case ISD::FRAMEADDR:
2968 case ISD::RETURNADDR:
2969 case ISD::FRAME_TO_ARGS_OFFSET:
2970 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2972 case ISD::FLT_ROUNDS_:
2973 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2975 case ISD::EH_RETURN:
2979 case ISD::EH_SJLJ_LONGJMP:
2980 // If the target didn't expand these, there's nothing to do, so just
2981 // preserve the chain and be done.
2982 Results.push_back(Node->getOperand(0));
2984 case ISD::EH_SJLJ_SETJMP:
2985 // If the target didn't expand this, just return 'zero' and preserve the
2987 Results.push_back(DAG.getConstant(0, MVT::i32));
2988 Results.push_back(Node->getOperand(0));
2990 case ISD::ATOMIC_FENCE: {
2991 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2992 // FIXME: handle "fence singlethread" more efficiently.
2993 TargetLowering::ArgListTy Args;
2995 TargetLowering::CallLoweringInfo CLI(DAG);
2996 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
2997 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2998 DAG.getExternalSymbol("__sync_synchronize",
2999 TLI.getPointerTy()), std::move(Args), 0);
3001 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3003 Results.push_back(CallResult.second);
3006 case ISD::ATOMIC_LOAD: {
3007 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP.
3008 SDValue Zero = DAG.getConstant(0, Node->getValueType(0));
3009 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3010 SDValue Swap = DAG.getAtomicCmpSwap(
3011 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3012 Node->getOperand(0), Node->getOperand(1), Zero, Zero,
3013 cast<AtomicSDNode>(Node)->getMemOperand(),
3014 cast<AtomicSDNode>(Node)->getOrdering(),
3015 cast<AtomicSDNode>(Node)->getOrdering(),
3016 cast<AtomicSDNode>(Node)->getSynchScope());
3017 Results.push_back(Swap.getValue(0));
3018 Results.push_back(Swap.getValue(1));
3021 case ISD::ATOMIC_STORE: {
3022 // There is no libcall for atomic store; fake it with ATOMIC_SWAP.
3023 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl,
3024 cast<AtomicSDNode>(Node)->getMemoryVT(),
3025 Node->getOperand(0),
3026 Node->getOperand(1), Node->getOperand(2),
3027 cast<AtomicSDNode>(Node)->getMemOperand(),
3028 cast<AtomicSDNode>(Node)->getOrdering(),
3029 cast<AtomicSDNode>(Node)->getSynchScope());
3030 Results.push_back(Swap.getValue(1));
3033 // By default, atomic intrinsics are marked Legal and lowered. Targets
3034 // which don't support them directly, however, may want libcalls, in which
3035 // case they mark them Expand, and we get here.
3036 case ISD::ATOMIC_SWAP:
3037 case ISD::ATOMIC_LOAD_ADD:
3038 case ISD::ATOMIC_LOAD_SUB:
3039 case ISD::ATOMIC_LOAD_AND:
3040 case ISD::ATOMIC_LOAD_OR:
3041 case ISD::ATOMIC_LOAD_XOR:
3042 case ISD::ATOMIC_LOAD_NAND:
3043 case ISD::ATOMIC_LOAD_MIN:
3044 case ISD::ATOMIC_LOAD_MAX:
3045 case ISD::ATOMIC_LOAD_UMIN:
3046 case ISD::ATOMIC_LOAD_UMAX:
3047 case ISD::ATOMIC_CMP_SWAP: {
3048 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3049 Results.push_back(Tmp.first);
3050 Results.push_back(Tmp.second);
3053 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS: {
3054 // Expanding an ATOMIC_CMP_SWAP_WITH_SUCCESS produces an ATOMIC_CMP_SWAP and
3055 // splits out the success value as a comparison. Expanding the resulting
3056 // ATOMIC_CMP_SWAP will produce a libcall.
3057 SDVTList VTs = DAG.getVTList(Node->getValueType(0), MVT::Other);
3058 SDValue Res = DAG.getAtomicCmpSwap(
3059 ISD::ATOMIC_CMP_SWAP, dl, cast<AtomicSDNode>(Node)->getMemoryVT(), VTs,
3060 Node->getOperand(0), Node->getOperand(1), Node->getOperand(2),
3061 Node->getOperand(3), cast<MemSDNode>(Node)->getMemOperand(),
3062 cast<AtomicSDNode>(Node)->getSuccessOrdering(),
3063 cast<AtomicSDNode>(Node)->getFailureOrdering(),
3064 cast<AtomicSDNode>(Node)->getSynchScope());
3066 SDValue Success = DAG.getSetCC(SDLoc(Node), Node->getValueType(1),
3067 Res, Node->getOperand(2), ISD::SETEQ);
3069 Results.push_back(Res.getValue(0));
3070 Results.push_back(Success);
3071 Results.push_back(Res.getValue(1));
3074 case ISD::DYNAMIC_STACKALLOC:
3075 ExpandDYNAMIC_STACKALLOC(Node, Results);
3077 case ISD::MERGE_VALUES:
3078 for (unsigned i = 0; i < Node->getNumValues(); i++)
3079 Results.push_back(Node->getOperand(i));
3082 EVT VT = Node->getValueType(0);
3084 Results.push_back(DAG.getConstant(0, VT));
3086 assert(VT.isFloatingPoint() && "Unknown value type!");
3087 Results.push_back(DAG.getConstantFP(0, VT));
3092 // If this operation is not supported, lower it to 'abort()' call
3093 TargetLowering::ArgListTy Args;
3094 TargetLowering::CallLoweringInfo CLI(DAG);
3095 CLI.setDebugLoc(dl).setChain(Node->getOperand(0))
3096 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
3097 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3098 std::move(Args), 0);
3099 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI);
3101 Results.push_back(CallResult.second);
3106 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3107 Node->getValueType(0), dl);
3108 Results.push_back(Tmp1);
3110 case ISD::FP_EXTEND:
3111 Tmp1 = EmitStackConvert(Node->getOperand(0),
3112 Node->getOperand(0).getValueType(),
3113 Node->getValueType(0), dl);
3114 Results.push_back(Tmp1);
3116 case ISD::SIGN_EXTEND_INREG: {
3117 // NOTE: we could fall back on load/store here too for targets without
3118 // SAR. However, it is doubtful that any exist.
3119 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3120 EVT VT = Node->getValueType(0);
3121 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3124 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3125 ExtraVT.getScalarType().getSizeInBits();
3126 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3127 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3128 Node->getOperand(0), ShiftCst);
3129 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3130 Results.push_back(Tmp1);
3133 case ISD::FP_ROUND_INREG: {
3134 // The only way we can lower this is to turn it into a TRUNCSTORE,
3135 // EXTLOAD pair, targeting a temporary location (a stack slot).
3137 // NOTE: there is a choice here between constantly creating new stack
3138 // slots and always reusing the same one. We currently always create
3139 // new ones, as reuse may inhibit scheduling.
3140 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3141 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3142 Node->getValueType(0), dl);
3143 Results.push_back(Tmp1);
3146 case ISD::SINT_TO_FP:
3147 case ISD::UINT_TO_FP:
3148 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3149 Node->getOperand(0), Node->getValueType(0), dl);
3150 Results.push_back(Tmp1);
3152 case ISD::FP_TO_SINT:
3153 if (TLI.expandFP_TO_SINT(Node, Tmp1, DAG))
3154 Results.push_back(Tmp1);
3156 case ISD::FP_TO_UINT: {
3157 SDValue True, False;
3158 EVT VT = Node->getOperand(0).getValueType();
3159 EVT NVT = Node->getValueType(0);
3160 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
3161 APInt::getNullValue(VT.getSizeInBits()));
3162 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3163 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3164 Tmp1 = DAG.getConstantFP(apf, VT);
3165 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(VT),
3166 Node->getOperand(0),
3168 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3169 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3170 DAG.getNode(ISD::FSUB, dl, VT,
3171 Node->getOperand(0), Tmp1));
3172 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3173 DAG.getConstant(x, NVT));
3174 Tmp1 = DAG.getSelect(dl, NVT, Tmp2, True, False);
3175 Results.push_back(Tmp1);
3179 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3180 EVT VT = Node->getValueType(0);
3181 Tmp1 = Node->getOperand(0);
3182 Tmp2 = Node->getOperand(1);
3183 unsigned Align = Node->getConstantOperandVal(3);
3185 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3186 MachinePointerInfo(V),
3187 false, false, false, 0);
3188 SDValue VAList = VAListLoad;
3190 if (Align > TLI.getMinStackArgumentAlignment()) {
3191 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3193 VAList = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3194 DAG.getConstant(Align - 1,
3195 VAList.getValueType()));
3197 VAList = DAG.getNode(ISD::AND, dl, VAList.getValueType(), VAList,
3198 DAG.getConstant(-(int64_t)Align,
3199 VAList.getValueType()));
3202 // Increment the pointer, VAList, to the next vaarg
3203 Tmp3 = DAG.getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
3204 DAG.getConstant(TLI.getDataLayout()->
3205 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3206 VAList.getValueType()));
3207 // Store the incremented VAList to the legalized pointer
3208 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3209 MachinePointerInfo(V), false, false, 0);
3210 // Load the actual argument out of the pointer VAList
3211 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3212 false, false, false, 0));
3213 Results.push_back(Results[0].getValue(1));
3217 // This defaults to loading a pointer from the input and storing it to the
3218 // output, returning the chain.
3219 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3220 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3221 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3222 Node->getOperand(2), MachinePointerInfo(VS),
3223 false, false, false, 0);
3224 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3225 MachinePointerInfo(VD), false, false, 0);
3226 Results.push_back(Tmp1);
3229 case ISD::EXTRACT_VECTOR_ELT:
3230 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3231 // This must be an access of the only element. Return it.
3232 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3233 Node->getOperand(0));
3235 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3236 Results.push_back(Tmp1);
3238 case ISD::EXTRACT_SUBVECTOR:
3239 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3241 case ISD::INSERT_SUBVECTOR:
3242 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3244 case ISD::CONCAT_VECTORS: {
3245 Results.push_back(ExpandVectorBuildThroughStack(Node));
3248 case ISD::SCALAR_TO_VECTOR:
3249 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3251 case ISD::INSERT_VECTOR_ELT:
3252 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3253 Node->getOperand(1),
3254 Node->getOperand(2), dl));
3256 case ISD::VECTOR_SHUFFLE: {
3257 SmallVector<int, 32> NewMask;
3258 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
3260 EVT VT = Node->getValueType(0);
3261 EVT EltVT = VT.getVectorElementType();
3262 SDValue Op0 = Node->getOperand(0);
3263 SDValue Op1 = Node->getOperand(1);
3264 if (!TLI.isTypeLegal(EltVT)) {
3266 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3268 // BUILD_VECTOR operands are allowed to be wider than the element type.
3269 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept
3271 if (NewEltVT.bitsLT(EltVT)) {
3273 // Convert shuffle node.
3274 // If original node was v4i64 and the new EltVT is i32,
3275 // cast operands to v8i32 and re-build the mask.
3277 // Calculate new VT, the size of the new VT should be equal to original.
3279 EVT::getVectorVT(*DAG.getContext(), NewEltVT,
3280 VT.getSizeInBits() / NewEltVT.getSizeInBits());
3281 assert(NewVT.bitsEq(VT));
3283 // cast operands to new VT
3284 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0);
3285 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1);
3287 // Convert the shuffle mask
3288 unsigned int factor =
3289 NewVT.getVectorNumElements()/VT.getVectorNumElements();
3291 // EltVT gets smaller
3294 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3296 for (unsigned fi = 0; fi < factor; ++fi)
3297 NewMask.push_back(Mask[i]);
3300 for (unsigned fi = 0; fi < factor; ++fi)
3301 NewMask.push_back(Mask[i]*factor+fi);
3309 unsigned NumElems = VT.getVectorNumElements();
3310 SmallVector<SDValue, 16> Ops;
3311 for (unsigned i = 0; i != NumElems; ++i) {
3313 Ops.push_back(DAG.getUNDEF(EltVT));
3316 unsigned Idx = Mask[i];
3318 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3320 DAG.getConstant(Idx, TLI.getVectorIdxTy())));
3322 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3324 DAG.getConstant(Idx - NumElems,
3325 TLI.getVectorIdxTy())));
3328 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);
3329 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type.
3330 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1);
3331 Results.push_back(Tmp1);
3334 case ISD::EXTRACT_ELEMENT: {
3335 EVT OpTy = Node->getOperand(0).getValueType();
3336 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3338 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3339 DAG.getConstant(OpTy.getSizeInBits()/2,
3340 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3341 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3344 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3345 Node->getOperand(0));
3347 Results.push_back(Tmp1);
3350 case ISD::STACKSAVE:
3351 // Expand to CopyFromReg if the target set
3352 // StackPointerRegisterToSaveRestore.
3353 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3354 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3355 Node->getValueType(0)));
3356 Results.push_back(Results[0].getValue(1));
3358 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3359 Results.push_back(Node->getOperand(0));
3362 case ISD::STACKRESTORE:
3363 // Expand to CopyToReg if the target set
3364 // StackPointerRegisterToSaveRestore.
3365 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3366 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3367 Node->getOperand(1)));
3369 Results.push_back(Node->getOperand(0));
3372 case ISD::FCOPYSIGN:
3373 Results.push_back(ExpandFCOPYSIGN(Node));
3376 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3377 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3378 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3379 Node->getOperand(0));
3380 Results.push_back(Tmp1);
3383 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3384 EVT VT = Node->getValueType(0);
3385 Tmp1 = Node->getOperand(0);
3386 Tmp2 = DAG.getConstantFP(0.0, VT);
3387 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(Tmp1.getValueType()),
3388 Tmp1, Tmp2, ISD::SETUGT);
3389 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3390 Tmp1 = DAG.getSelect(dl, VT, Tmp2, Tmp1, Tmp3);
3391 Results.push_back(Tmp1);
3395 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMIN_F32, RTLIB::FMIN_F64,
3396 RTLIB::FMIN_F80, RTLIB::FMIN_F128,
3397 RTLIB::FMIN_PPCF128));
3400 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMAX_F32, RTLIB::FMAX_F64,
3401 RTLIB::FMAX_F80, RTLIB::FMAX_F128,
3402 RTLIB::FMAX_PPCF128));
3405 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3406 RTLIB::SQRT_F80, RTLIB::SQRT_F128,
3407 RTLIB::SQRT_PPCF128));
3411 EVT VT = Node->getValueType(0);
3412 bool isSIN = Node->getOpcode() == ISD::FSIN;
3413 // Turn fsin / fcos into ISD::FSINCOS node if there are a pair of fsin /
3414 // fcos which share the same operand and both are used.
3415 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3416 canCombineSinCosLibcall(Node, TLI, TM))
3417 && useSinCos(Node)) {
3418 SDVTList VTs = DAG.getVTList(VT, VT);
3419 Tmp1 = DAG.getNode(ISD::FSINCOS, dl, VTs, Node->getOperand(0));
3421 Tmp1 = Tmp1.getValue(1);
3422 Results.push_back(Tmp1);
3424 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3425 RTLIB::SIN_F80, RTLIB::SIN_F128,
3426 RTLIB::SIN_PPCF128));
3428 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3429 RTLIB::COS_F80, RTLIB::COS_F128,
3430 RTLIB::COS_PPCF128));
3435 // Expand into sincos libcall.
3436 ExpandSinCosLibCall(Node, Results);
3439 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3440 RTLIB::LOG_F80, RTLIB::LOG_F128,
3441 RTLIB::LOG_PPCF128));
3444 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3445 RTLIB::LOG2_F80, RTLIB::LOG2_F128,
3446 RTLIB::LOG2_PPCF128));
3449 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3450 RTLIB::LOG10_F80, RTLIB::LOG10_F128,
3451 RTLIB::LOG10_PPCF128));
3454 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3455 RTLIB::EXP_F80, RTLIB::EXP_F128,
3456 RTLIB::EXP_PPCF128));
3459 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3460 RTLIB::EXP2_F80, RTLIB::EXP2_F128,
3461 RTLIB::EXP2_PPCF128));
3464 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3465 RTLIB::TRUNC_F80, RTLIB::TRUNC_F128,
3466 RTLIB::TRUNC_PPCF128));
3469 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3470 RTLIB::FLOOR_F80, RTLIB::FLOOR_F128,
3471 RTLIB::FLOOR_PPCF128));
3474 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3475 RTLIB::CEIL_F80, RTLIB::CEIL_F128,
3476 RTLIB::CEIL_PPCF128));
3479 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3480 RTLIB::RINT_F80, RTLIB::RINT_F128,
3481 RTLIB::RINT_PPCF128));
3483 case ISD::FNEARBYINT:
3484 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3485 RTLIB::NEARBYINT_F64,
3486 RTLIB::NEARBYINT_F80,
3487 RTLIB::NEARBYINT_F128,
3488 RTLIB::NEARBYINT_PPCF128));
3491 Results.push_back(ExpandFPLibCall(Node, RTLIB::ROUND_F32,
3495 RTLIB::ROUND_PPCF128));
3498 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3499 RTLIB::POWI_F80, RTLIB::POWI_F128,
3500 RTLIB::POWI_PPCF128));
3503 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3504 RTLIB::POW_F80, RTLIB::POW_F128,
3505 RTLIB::POW_PPCF128));
3508 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3509 RTLIB::DIV_F80, RTLIB::DIV_F128,
3510 RTLIB::DIV_PPCF128));
3513 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3514 RTLIB::REM_F80, RTLIB::REM_F128,
3515 RTLIB::REM_PPCF128));
3518 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3519 RTLIB::FMA_F80, RTLIB::FMA_F128,
3520 RTLIB::FMA_PPCF128));
3523 llvm_unreachable("Illegal fmad should never be formed");
3526 Results.push_back(ExpandFPLibCall(Node, RTLIB::ADD_F32, RTLIB::ADD_F64,
3527 RTLIB::ADD_F80, RTLIB::ADD_F128,
3528 RTLIB::ADD_PPCF128));
3531 Results.push_back(ExpandFPLibCall(Node, RTLIB::MUL_F32, RTLIB::MUL_F64,
3532 RTLIB::MUL_F80, RTLIB::MUL_F128,
3533 RTLIB::MUL_PPCF128));
3535 case ISD::FP16_TO_FP: {
3536 if (Node->getValueType(0) == MVT::f32) {
3537 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3541 // We can extend to types bigger than f32 in two steps without changing the
3542 // result. Since "f16 -> f32" is much more commonly available, give CodeGen
3543 // the option of emitting that before resorting to a libcall.
3545 DAG.getNode(ISD::FP16_TO_FP, dl, MVT::f32, Node->getOperand(0));
3547 DAG.getNode(ISD::FP_EXTEND, dl, Node->getValueType(0), Res));
3550 case ISD::FP_TO_FP16: {
3551 if (!TM.Options.UseSoftFloat && TM.Options.UnsafeFPMath) {
3552 SDValue Op = Node->getOperand(0);
3553 MVT SVT = Op.getSimpleValueType();
3554 if ((SVT == MVT::f64 || SVT == MVT::f80) &&
3555 TLI.isOperationLegalOrCustom(ISD::FP_TO_FP16, MVT::f32)) {
3556 // Under fastmath, we can expand this node into a fround followed by
3557 // a float-half conversion.
3558 SDValue FloatVal = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Op,
3559 DAG.getIntPtrConstant(0));
3561 DAG.getNode(ISD::FP_TO_FP16, dl, MVT::i16, FloatVal));
3567 RTLIB::getFPROUND(Node->getOperand(0).getValueType(), MVT::f16);
3568 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unable to expand fp_to_fp16");
3569 Results.push_back(ExpandLibCall(LC, Node, false));
3572 case ISD::ConstantFP: {
3573 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3574 // Check to see if this FP immediate is already legal.
3575 // If this is a legal constant, turn it into a TargetConstantFP node.
3576 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3577 Results.push_back(ExpandConstantFP(CFP, true));
3581 EVT VT = Node->getValueType(0);
3582 if (TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3583 TLI.isOperationLegalOrCustom(ISD::FNEG, VT)) {
3584 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3585 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3586 Results.push_back(Tmp1);
3588 Results.push_back(ExpandFPLibCall(Node, RTLIB::SUB_F32, RTLIB::SUB_F64,
3589 RTLIB::SUB_F80, RTLIB::SUB_F128,
3590 RTLIB::SUB_PPCF128));
3595 EVT VT = Node->getValueType(0);
3596 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3597 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3598 "Don't know how to expand this subtraction!");
3599 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3600 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3601 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3602 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3607 EVT VT = Node->getValueType(0);
3608 bool isSigned = Node->getOpcode() == ISD::SREM;
3609 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3610 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3611 Tmp2 = Node->getOperand(0);
3612 Tmp3 = Node->getOperand(1);
3613 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3614 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3615 // If div is legal, it's better to do the normal expansion
3616 !TLI.isOperationLegalOrCustom(DivOpc, Node->getValueType(0)) &&
3617 useDivRem(Node, isSigned, false))) {
3618 SDVTList VTs = DAG.getVTList(VT, VT);
3619 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3620 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3622 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3623 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3624 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3625 } else if (isSigned)
3626 Tmp1 = ExpandIntLibCall(Node, true,
3628 RTLIB::SREM_I16, RTLIB::SREM_I32,
3629 RTLIB::SREM_I64, RTLIB::SREM_I128);
3631 Tmp1 = ExpandIntLibCall(Node, false,
3633 RTLIB::UREM_I16, RTLIB::UREM_I32,
3634 RTLIB::UREM_I64, RTLIB::UREM_I128);
3635 Results.push_back(Tmp1);
3640 bool isSigned = Node->getOpcode() == ISD::SDIV;
3641 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3642 EVT VT = Node->getValueType(0);
3643 SDVTList VTs = DAG.getVTList(VT, VT);
3644 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3645 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3646 useDivRem(Node, isSigned, true)))
3647 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3648 Node->getOperand(1));
3650 Tmp1 = ExpandIntLibCall(Node, true,
3652 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3653 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3655 Tmp1 = ExpandIntLibCall(Node, false,
3657 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3658 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3659 Results.push_back(Tmp1);
3664 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3666 EVT VT = Node->getValueType(0);
3667 SDVTList VTs = DAG.getVTList(VT, VT);
3668 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3669 "If this wasn't legal, it shouldn't have been created!");
3670 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3671 Node->getOperand(1));
3672 Results.push_back(Tmp1.getValue(1));
3677 // Expand into divrem libcall
3678 ExpandDivRemLibCall(Node, Results);
3681 EVT VT = Node->getValueType(0);
3682 SDVTList VTs = DAG.getVTList(VT, VT);
3683 // See if multiply or divide can be lowered using two-result operations.
3684 // We just need the low half of the multiply; try both the signed
3685 // and unsigned forms. If the target supports both SMUL_LOHI and
3686 // UMUL_LOHI, form a preference by checking which forms of plain
3687 // MULH it supports.
3688 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3689 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3690 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3691 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3692 unsigned OpToUse = 0;
3693 if (HasSMUL_LOHI && !HasMULHS) {
3694 OpToUse = ISD::SMUL_LOHI;
3695 } else if (HasUMUL_LOHI && !HasMULHU) {
3696 OpToUse = ISD::UMUL_LOHI;
3697 } else if (HasSMUL_LOHI) {
3698 OpToUse = ISD::SMUL_LOHI;
3699 } else if (HasUMUL_LOHI) {
3700 OpToUse = ISD::UMUL_LOHI;
3703 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3704 Node->getOperand(1)));
3709 EVT HalfType = VT.getHalfSizedIntegerVT(*DAG.getContext());
3710 if (TLI.isOperationLegalOrCustom(ISD::ZERO_EXTEND, VT) &&
3711 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) &&
3712 TLI.isOperationLegalOrCustom(ISD::SHL, VT) &&
3713 TLI.isOperationLegalOrCustom(ISD::OR, VT) &&
3714 TLI.expandMUL(Node, Lo, Hi, HalfType, DAG)) {
3715 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Lo);
3716 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi);
3717 SDValue Shift = DAG.getConstant(HalfType.getSizeInBits(),
3718 TLI.getShiftAmountTy(HalfType));
3719 Hi = DAG.getNode(ISD::SHL, dl, VT, Hi, Shift);
3720 Results.push_back(DAG.getNode(ISD::OR, dl, VT, Lo, Hi));
3724 Tmp1 = ExpandIntLibCall(Node, false,
3726 RTLIB::MUL_I16, RTLIB::MUL_I32,
3727 RTLIB::MUL_I64, RTLIB::MUL_I128);
3728 Results.push_back(Tmp1);
3733 SDValue LHS = Node->getOperand(0);
3734 SDValue RHS = Node->getOperand(1);
3735 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3736 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3738 Results.push_back(Sum);
3739 EVT ResultType = Node->getValueType(1);
3740 EVT OType = getSetCCResultType(Node->getValueType(0));
3742 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3744 // LHSSign -> LHS >= 0
3745 // RHSSign -> RHS >= 0
3746 // SumSign -> Sum >= 0
3749 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3751 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3753 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3754 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3755 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3756 Node->getOpcode() == ISD::SADDO ?
3757 ISD::SETEQ : ISD::SETNE);
3759 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3760 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3762 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3763 Results.push_back(DAG.getBoolExtOrTrunc(Cmp, dl, ResultType, ResultType));
3768 SDValue LHS = Node->getOperand(0);
3769 SDValue RHS = Node->getOperand(1);
3770 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3771 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3773 Results.push_back(Sum);
3775 EVT ResultType = Node->getValueType(1);
3776 EVT SetCCType = getSetCCResultType(Node->getValueType(0));
3778 = Node->getOpcode() == ISD::UADDO ? ISD::SETULT : ISD::SETUGT;
3779 SDValue SetCC = DAG.getSetCC(dl, SetCCType, Sum, LHS, CC);
3781 Results.push_back(DAG.getBoolExtOrTrunc(SetCC, dl, ResultType, ResultType));
3786 EVT VT = Node->getValueType(0);
3787 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3788 SDValue LHS = Node->getOperand(0);
3789 SDValue RHS = Node->getOperand(1);
3792 static const unsigned Ops[2][3] =
3793 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3794 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3795 bool isSigned = Node->getOpcode() == ISD::SMULO;
3796 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3797 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3798 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3799 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3800 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3802 TopHalf = BottomHalf.getValue(1);
3803 } else if (TLI.isTypeLegal(WideVT)) {
3804 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3805 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3806 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3807 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3808 DAG.getIntPtrConstant(0));
3809 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3810 DAG.getIntPtrConstant(1));
3812 // We can fall back to a libcall with an illegal type for the MUL if we
3813 // have a libcall big enough.
3814 // Also, we can fall back to a division in some cases, but that's a big
3815 // performance hit in the general case.
3816 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3817 if (WideVT == MVT::i16)
3818 LC = RTLIB::MUL_I16;
3819 else if (WideVT == MVT::i32)
3820 LC = RTLIB::MUL_I32;
3821 else if (WideVT == MVT::i64)
3822 LC = RTLIB::MUL_I64;
3823 else if (WideVT == MVT::i128)
3824 LC = RTLIB::MUL_I128;
3825 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3827 // The high part is obtained by SRA'ing all but one of the bits of low
3829 unsigned LoSize = VT.getSizeInBits();
3830 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3831 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3832 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3833 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3835 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3836 // pre-lowered to the correct types. This all depends upon WideVT not
3837 // being a legal type for the architecture and thus has to be split to
3839 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3840 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3841 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3842 DAG.getIntPtrConstant(0));
3843 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3844 DAG.getIntPtrConstant(1));
3845 // Ret is a node with an illegal type. Because such things are not
3846 // generally permitted during this phase of legalization, make sure the
3847 // node has no more uses. The above EXTRACT_ELEMENT nodes should have been
3849 assert(Ret->use_empty() &&
3850 "Unexpected uses of illegally type from expanded lib call.");
3854 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3855 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3856 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3857 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf, Tmp1,
3860 TopHalf = DAG.getSetCC(dl, getSetCCResultType(VT), TopHalf,
3861 DAG.getConstant(0, VT), ISD::SETNE);
3863 Results.push_back(BottomHalf);
3864 Results.push_back(TopHalf);
3867 case ISD::BUILD_PAIR: {
3868 EVT PairTy = Node->getValueType(0);
3869 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3870 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3871 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3872 DAG.getConstant(PairTy.getSizeInBits()/2,
3873 TLI.getShiftAmountTy(PairTy)));
3874 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3878 Tmp1 = Node->getOperand(0);
3879 Tmp2 = Node->getOperand(1);
3880 Tmp3 = Node->getOperand(2);
3881 if (Tmp1.getOpcode() == ISD::SETCC) {
3882 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3884 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3886 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3887 DAG.getConstant(0, Tmp1.getValueType()),
3888 Tmp2, Tmp3, ISD::SETNE);
3890 Results.push_back(Tmp1);
3893 SDValue Chain = Node->getOperand(0);
3894 SDValue Table = Node->getOperand(1);
3895 SDValue Index = Node->getOperand(2);
3897 EVT PTy = TLI.getPointerTy();
3899 const DataLayout &TD = *TLI.getDataLayout();
3900 unsigned EntrySize =
3901 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3903 Index = DAG.getNode(ISD::MUL, dl, Index.getValueType(),
3904 Index, DAG.getConstant(EntrySize, Index.getValueType()));
3905 SDValue Addr = DAG.getNode(ISD::ADD, dl, Index.getValueType(),
3908 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3909 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3910 MachinePointerInfo::getJumpTable(), MemVT,
3911 false, false, false, 0);
3913 if (TM.getRelocationModel() == Reloc::PIC_) {
3914 // For PIC, the sequence is:
3915 // BRIND(load(Jumptable + index) + RelocBase)
3916 // RelocBase can be JumpTable, GOT or some sort of global base.
3917 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3918 TLI.getPICJumpTableRelocBase(Table, DAG));
3920 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3921 Results.push_back(Tmp1);
3925 // Expand brcond's setcc into its constituent parts and create a BR_CC
3927 Tmp1 = Node->getOperand(0);
3928 Tmp2 = Node->getOperand(1);
3929 if (Tmp2.getOpcode() == ISD::SETCC) {
3930 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3931 Tmp1, Tmp2.getOperand(2),
3932 Tmp2.getOperand(0), Tmp2.getOperand(1),
3933 Node->getOperand(2));
3935 // We test only the i1 bit. Skip the AND if UNDEF.
3936 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3937 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3938 DAG.getConstant(1, Tmp2.getValueType()));
3939 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3940 DAG.getCondCode(ISD::SETNE), Tmp3,
3941 DAG.getConstant(0, Tmp3.getValueType()),
3942 Node->getOperand(2));
3944 Results.push_back(Tmp1);
3947 Tmp1 = Node->getOperand(0);
3948 Tmp2 = Node->getOperand(1);
3949 Tmp3 = Node->getOperand(2);
3950 bool Legalized = LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2,
3951 Tmp3, NeedInvert, dl);
3954 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
3955 // condition code, create a new SETCC node.
3957 Tmp1 = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3960 // If we expanded the SETCC by inverting the condition code, then wrap
3961 // the existing SETCC in a NOT to restore the intended condition.
3963 Tmp1 = DAG.getLogicalNOT(dl, Tmp1, Tmp1->getValueType(0));
3965 Results.push_back(Tmp1);
3969 // Otherwise, SETCC for the given comparison type must be completely
3970 // illegal; expand it into a SELECT_CC.
3971 EVT VT = Node->getValueType(0);
3973 switch (TLI.getBooleanContents(Tmp1->getValueType(0))) {
3974 case TargetLowering::ZeroOrOneBooleanContent:
3975 case TargetLowering::UndefinedBooleanContent:
3978 case TargetLowering::ZeroOrNegativeOneBooleanContent:
3982 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3983 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3985 Results.push_back(Tmp1);
3988 case ISD::SELECT_CC: {
3989 Tmp1 = Node->getOperand(0); // LHS
3990 Tmp2 = Node->getOperand(1); // RHS
3991 Tmp3 = Node->getOperand(2); // True
3992 Tmp4 = Node->getOperand(3); // False
3993 EVT VT = Node->getValueType(0);
3994 SDValue CC = Node->getOperand(4);
3995 ISD::CondCode CCOp = cast<CondCodeSDNode>(CC)->get();
3997 if (TLI.isCondCodeLegal(CCOp, Tmp1.getSimpleValueType())) {
3998 // If the condition code is legal, then we need to expand this
3999 // node using SETCC and SELECT.
4000 EVT CmpVT = Tmp1.getValueType();
4001 assert(!TLI.isOperationExpand(ISD::SELECT, VT) &&
4002 "Cannot expand ISD::SELECT_CC when ISD::SELECT also needs to be "
4004 EVT CCVT = TLI.getSetCCResultType(*DAG.getContext(), CmpVT);
4005 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC);
4006 Results.push_back(DAG.getSelect(dl, VT, Cond, Tmp3, Tmp4));
4010 // SELECT_CC is legal, so the condition code must not be.
4011 bool Legalized = false;
4012 // Try to legalize by inverting the condition. This is for targets that
4013 // might support an ordered version of a condition, but not the unordered
4014 // version (or vice versa).
4015 ISD::CondCode InvCC = ISD::getSetCCInverse(CCOp,
4016 Tmp1.getValueType().isInteger());
4017 if (TLI.isCondCodeLegal(InvCC, Tmp1.getSimpleValueType())) {
4018 // Use the new condition code and swap true and false
4020 Tmp1 = DAG.getSelectCC(dl, Tmp1, Tmp2, Tmp4, Tmp3, InvCC);
4022 // If The inverse is not legal, then try to swap the arguments using
4023 // the inverse condition code.
4024 ISD::CondCode SwapInvCC = ISD::getSetCCSwappedOperands(InvCC);
4025 if (TLI.isCondCodeLegal(SwapInvCC, Tmp1.getSimpleValueType())) {
4026 // The swapped inverse condition is legal, so swap true and false,
4029 Tmp1 = DAG.getSelectCC(dl, Tmp2, Tmp1, Tmp4, Tmp3, SwapInvCC);
4034 Legalized = LegalizeSetCCCondCode(
4035 getSetCCResultType(Tmp1.getValueType()), Tmp1, Tmp2, CC, NeedInvert,
4038 assert(Legalized && "Can't legalize SELECT_CC with legal condition!");
4040 // If we expanded the SETCC by inverting the condition code, then swap
4041 // the True/False operands to match.
4043 std::swap(Tmp3, Tmp4);
4045 // If we expanded the SETCC by swapping LHS and RHS, or by inverting the
4046 // condition code, create a new SELECT_CC node.
4048 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0),
4049 Tmp1, Tmp2, Tmp3, Tmp4, CC);
4051 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4052 CC = DAG.getCondCode(ISD::SETNE);
4053 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1,
4054 Tmp2, Tmp3, Tmp4, CC);
4057 Results.push_back(Tmp1);
4061 Tmp1 = Node->getOperand(0); // Chain
4062 Tmp2 = Node->getOperand(2); // LHS
4063 Tmp3 = Node->getOperand(3); // RHS
4064 Tmp4 = Node->getOperand(1); // CC
4066 bool Legalized = LegalizeSetCCCondCode(getSetCCResultType(
4067 Tmp2.getValueType()), Tmp2, Tmp3, Tmp4, NeedInvert, dl);
4069 assert(Legalized && "Can't legalize BR_CC with legal condition!");
4071 // If we expanded the SETCC by inverting the condition code, then wrap
4072 // the existing SETCC in a NOT to restore the intended condition.
4074 Tmp4 = DAG.getNOT(dl, Tmp4, Tmp4->getValueType(0));
4076 // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC
4078 if (Tmp4.getNode()) {
4079 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1,
4080 Tmp4, Tmp2, Tmp3, Node->getOperand(4));
4082 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
4083 Tmp4 = DAG.getCondCode(ISD::SETNE);
4084 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4,
4085 Tmp2, Tmp3, Node->getOperand(4));
4087 Results.push_back(Tmp1);
4090 case ISD::BUILD_VECTOR:
4091 Results.push_back(ExpandBUILD_VECTOR(Node));
4096 // Scalarize vector SRA/SRL/SHL.
4097 EVT VT = Node->getValueType(0);
4098 assert(VT.isVector() && "Unable to legalize non-vector shift");
4099 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
4100 unsigned NumElem = VT.getVectorNumElements();
4102 SmallVector<SDValue, 8> Scalars;
4103 for (unsigned Idx = 0; Idx < NumElem; Idx++) {
4104 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4106 Node->getOperand(0), DAG.getConstant(Idx,
4107 TLI.getVectorIdxTy()));
4108 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
4110 Node->getOperand(1), DAG.getConstant(Idx,
4111 TLI.getVectorIdxTy()));
4112 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
4113 VT.getScalarType(), Ex, Sh));
4116 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Scalars);
4117 ReplaceNode(SDValue(Node, 0), Result);
4120 case ISD::GLOBAL_OFFSET_TABLE:
4121 case ISD::GlobalAddress:
4122 case ISD::GlobalTLSAddress:
4123 case ISD::ExternalSymbol:
4124 case ISD::ConstantPool:
4125 case ISD::JumpTable:
4126 case ISD::INTRINSIC_W_CHAIN:
4127 case ISD::INTRINSIC_WO_CHAIN:
4128 case ISD::INTRINSIC_VOID:
4129 // FIXME: Custom lowering for these operations shouldn't return null!
4133 // Replace the original node with the legalized result.
4134 if (!Results.empty())
4135 ReplaceNode(Node, Results.data());
4138 void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
4139 SmallVector<SDValue, 8> Results;
4140 MVT OVT = Node->getSimpleValueType(0);
4141 if (Node->getOpcode() == ISD::UINT_TO_FP ||
4142 Node->getOpcode() == ISD::SINT_TO_FP ||
4143 Node->getOpcode() == ISD::SETCC) {
4144 OVT = Node->getOperand(0).getSimpleValueType();
4146 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
4148 SDValue Tmp1, Tmp2, Tmp3;
4149 switch (Node->getOpcode()) {
4151 case ISD::CTTZ_ZERO_UNDEF:
4153 case ISD::CTLZ_ZERO_UNDEF:
4155 // Zero extend the argument.
4156 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4157 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is
4158 // already the correct result.
4159 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4160 if (Node->getOpcode() == ISD::CTTZ) {
4161 // FIXME: This should set a bit in the zero extended value instead.
4162 Tmp2 = DAG.getSetCC(dl, getSetCCResultType(NVT),
4163 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
4165 Tmp1 = DAG.getSelect(dl, NVT, Tmp2,
4166 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
4167 } else if (Node->getOpcode() == ISD::CTLZ ||
4168 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) {
4169 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4170 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
4171 DAG.getConstant(NVT.getSizeInBits() -
4172 OVT.getSizeInBits(), NVT));
4174 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
4177 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
4178 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
4179 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
4180 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
4181 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
4182 Results.push_back(Tmp1);
4185 case ISD::FP_TO_UINT:
4186 case ISD::FP_TO_SINT:
4187 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
4188 Node->getOpcode() == ISD::FP_TO_SINT, dl);
4189 Results.push_back(Tmp1);
4191 case ISD::UINT_TO_FP:
4192 case ISD::SINT_TO_FP:
4193 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
4194 Node->getOpcode() == ISD::SINT_TO_FP, dl);
4195 Results.push_back(Tmp1);
4198 SDValue Chain = Node->getOperand(0); // Get the chain.
4199 SDValue Ptr = Node->getOperand(1); // Get the pointer.
4202 if (OVT.isVector()) {
4203 TruncOp = ISD::BITCAST;
4205 assert(OVT.isInteger()
4206 && "VAARG promotion is supported only for vectors or integer types");
4207 TruncOp = ISD::TRUNCATE;
4210 // Perform the larger operation, then convert back
4211 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2),
4212 Node->getConstantOperandVal(3));
4213 Chain = Tmp1.getValue(1);
4215 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1);
4217 // Modified the chain result - switch anything that used the old chain to
4219 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2);
4220 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain);
4222 UpdatedNodes->insert(Tmp2.getNode());
4223 UpdatedNodes->insert(Chain.getNode());
4231 unsigned ExtOp, TruncOp;
4232 if (OVT.isVector()) {
4233 ExtOp = ISD::BITCAST;
4234 TruncOp = ISD::BITCAST;
4236 assert(OVT.isInteger() && "Cannot promote logic operation");
4237 ExtOp = ISD::ANY_EXTEND;
4238 TruncOp = ISD::TRUNCATE;
4240 // Promote each of the values to the new type.
4241 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4242 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4243 // Perform the larger operation, then convert back
4244 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4245 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
4249 unsigned ExtOp, TruncOp;
4250 if (Node->getValueType(0).isVector() ||
4251 Node->getValueType(0).getSizeInBits() == NVT.getSizeInBits()) {
4252 ExtOp = ISD::BITCAST;
4253 TruncOp = ISD::BITCAST;
4254 } else if (Node->getValueType(0).isInteger()) {
4255 ExtOp = ISD::ANY_EXTEND;
4256 TruncOp = ISD::TRUNCATE;
4258 ExtOp = ISD::FP_EXTEND;
4259 TruncOp = ISD::FP_ROUND;
4261 Tmp1 = Node->getOperand(0);
4262 // Promote each of the values to the new type.
4263 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4264 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
4265 // Perform the larger operation, then round down.
4266 Tmp1 = DAG.getSelect(dl, NVT, Tmp1, Tmp2, Tmp3);
4267 if (TruncOp != ISD::FP_ROUND)
4268 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
4270 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
4271 DAG.getIntPtrConstant(0));
4272 Results.push_back(Tmp1);
4275 case ISD::VECTOR_SHUFFLE: {
4276 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask();
4278 // Cast the two input vectors.
4279 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
4280 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
4282 // Convert the shuffle mask to the right # elements.
4283 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
4284 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
4285 Results.push_back(Tmp1);
4289 unsigned ExtOp = ISD::FP_EXTEND;
4290 if (NVT.isInteger()) {
4291 ISD::CondCode CCCode =
4292 cast<CondCodeSDNode>(Node->getOperand(2))->get();
4293 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4295 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
4296 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
4297 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
4298 Tmp1, Tmp2, Node->getOperand(2)));
4307 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4308 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1));
4309 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
4310 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4311 Tmp3, DAG.getIntPtrConstant(0)));
4318 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0));
4319 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
4320 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT,
4321 Tmp2, DAG.getIntPtrConstant(0)));
4326 // Replace the original node with the legalized result.
4327 if (!Results.empty())
4328 ReplaceNode(Node, Results.data());
4331 /// This is the entry point for the file.
4332 void SelectionDAG::Legalize() {
4333 AssignTopologicalOrder();
4335 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4336 SelectionDAGLegalize Legalizer(*this, LegalizedNodes);
4338 // Visit all the nodes. We start in topological order, so that we see
4339 // nodes with their original operands intact. Legalization can produce
4340 // new nodes which may themselves need to be legalized. Iterate until all
4341 // nodes have been legalized.
4343 bool AnyLegalized = false;
4344 for (auto NI = allnodes_end(); NI != allnodes_begin();) {
4348 if (N->use_empty() && N != getRoot().getNode()) {
4354 if (LegalizedNodes.insert(N).second) {
4355 AnyLegalized = true;
4356 Legalizer.LegalizeOp(N);
4358 if (N->use_empty() && N != getRoot().getNode()) {
4369 // Remove dead nodes now.
4373 bool SelectionDAG::LegalizeOp(SDNode *N,
4374 SmallSetVector<SDNode *, 16> &UpdatedNodes) {
4375 SmallPtrSet<SDNode *, 16> LegalizedNodes;
4376 SelectionDAGLegalize Legalizer(*this, LegalizedNodes, &UpdatedNodes);
4378 // Directly insert the node in question, and legalize it. This will recurse
4379 // as needed through operands.
4380 LegalizedNodes.insert(N);
4381 Legalizer.LegalizeOp(N);
4383 return LegalizedNodes.count(N);