1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
40 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
41 cl::desc("Pop up a window to show dags before legalize"));
43 static const bool ViewLegalizeDAGs = 0;
46 //===----------------------------------------------------------------------===//
47 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
48 /// hacks on it until the target machine can handle it. This involves
49 /// eliminating value sizes the machine cannot handle (promoting small sizes to
50 /// large sizes or splitting up large values into small values) as well as
51 /// eliminating operations the machine cannot handle.
53 /// This code also does a small amount of optimization and recognition of idioms
54 /// as part of its processing. For example, if a target does not support a
55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
59 class VISIBILITY_HIDDEN SelectionDAGLegalize {
63 // Libcall insertion helpers.
65 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
66 /// legalized. We use this to ensure that calls are properly serialized
67 /// against each other, including inserted libcalls.
68 SDOperand LastCALLSEQ_END;
70 /// IsLegalizingCall - This member is used *only* for purposes of providing
71 /// helpful assertions that a libcall isn't created while another call is
72 /// being legalized (which could lead to non-serialized call sequences).
73 bool IsLegalizingCall;
76 Legal, // The target natively supports this operation.
77 Promote, // This operation should be executed in a larger type.
78 Expand // Try to expand this to other ops, otherwise use a libcall.
81 /// ValueTypeActions - This is a bitvector that contains two bits for each
82 /// value type, where the two bits correspond to the LegalizeAction enum.
83 /// This can be queried with "getTypeAction(VT)".
84 TargetLowering::ValueTypeActionImpl ValueTypeActions;
86 /// LegalizedNodes - For nodes that are of legal width, and that have more
87 /// than one use, this map indicates what regularized operand to use. This
88 /// allows us to avoid legalizing the same thing more than once.
89 DenseMap<SDOperand, SDOperand> LegalizedNodes;
91 /// PromotedNodes - For nodes that are below legal width, and that have more
92 /// than one use, this map indicates what promoted value to use. This allows
93 /// us to avoid promoting the same thing more than once.
94 DenseMap<SDOperand, SDOperand> PromotedNodes;
96 /// ExpandedNodes - For nodes that need to be expanded this map indicates
97 /// which which operands are the expanded version of the input. This allows
98 /// us to avoid expanding the same node more than once.
99 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
101 /// SplitNodes - For vector nodes that need to be split, this map indicates
102 /// which which operands are the split version of the input. This allows us
103 /// to avoid splitting the same node more than once.
104 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
106 /// ScalarizedNodes - For nodes that need to be converted from vector types to
107 /// scalar types, this contains the mapping of ones we have already
108 /// processed to the result.
109 std::map<SDOperand, SDOperand> ScalarizedNodes;
111 void AddLegalizedOperand(SDOperand From, SDOperand To) {
112 LegalizedNodes.insert(std::make_pair(From, To));
113 // If someone requests legalization of the new node, return itself.
115 LegalizedNodes.insert(std::make_pair(To, To));
117 void AddPromotedOperand(SDOperand From, SDOperand To) {
118 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
119 assert(isNew && "Got into the map somehow?");
120 // If someone requests legalization of the new node, return itself.
121 LegalizedNodes.insert(std::make_pair(To, To));
126 SelectionDAGLegalize(SelectionDAG &DAG);
128 /// getTypeAction - Return how we should legalize values of this type, either
129 /// it is already legal or we need to expand it into multiple registers of
130 /// smaller integer type, or we need to promote it to a larger type.
131 LegalizeAction getTypeAction(MVT::ValueType VT) const {
132 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
135 /// isTypeLegal - Return true if this type is legal on this target.
137 bool isTypeLegal(MVT::ValueType VT) const {
138 return getTypeAction(VT) == Legal;
144 /// HandleOp - Legalize, Promote, or Expand the specified operand as
145 /// appropriate for its type.
146 void HandleOp(SDOperand Op);
148 /// LegalizeOp - We know that the specified value has a legal type.
149 /// Recursively ensure that the operands have legal types, then return the
151 SDOperand LegalizeOp(SDOperand O);
153 /// UnrollVectorOp - We know that the given vector has a legal type, however
154 /// the operation it performs is not legal and is an operation that we have
155 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
156 /// operating on each element individually.
157 SDOperand UnrollVectorOp(SDOperand O);
159 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
160 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
161 /// is necessary to spill the vector being inserted into to memory, perform
162 /// the insert there, and then read the result back.
163 SDOperand PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val,
166 /// PromoteOp - Given an operation that produces a value in an invalid type,
167 /// promote it to compute the value into a larger type. The produced value
168 /// will have the correct bits for the low portion of the register, but no
169 /// guarantee is made about the top bits: it may be zero, sign-extended, or
171 SDOperand PromoteOp(SDOperand O);
173 /// ExpandOp - Expand the specified SDOperand into its two component pieces
174 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
175 /// the LegalizeNodes map is filled in for any results that are not expanded,
176 /// the ExpandedNodes map is filled in for any results that are expanded, and
177 /// the Lo/Hi values are returned. This applies to integer types and Vector
179 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
181 /// SplitVectorOp - Given an operand of vector type, break it down into
182 /// two smaller values.
183 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
185 /// ScalarizeVectorOp - Given an operand of single-element vector type
186 /// (e.g. v1f32), convert it into the equivalent operation that returns a
187 /// scalar (e.g. f32) value.
188 SDOperand ScalarizeVectorOp(SDOperand O);
190 /// isShuffleLegal - Return true if a vector shuffle is legal with the
191 /// specified mask and type. Targets can specify exactly which masks they
192 /// support and the code generator is tasked with not creating illegal masks.
194 /// Note that this will also return true for shuffles that are promoted to a
197 /// If this is a legal shuffle, this method returns the (possibly promoted)
198 /// build_vector Mask. If it's not a legal shuffle, it returns null.
199 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
201 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
202 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
204 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
206 SDOperand ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
208 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
211 SDOperand EmitStackConvert(SDOperand SrcOp, MVT::ValueType SlotVT,
212 MVT::ValueType DestVT);
213 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
214 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
215 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
217 MVT::ValueType DestVT);
218 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
220 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
223 SDOperand ExpandBSWAP(SDOperand Op);
224 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
225 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
226 SDOperand &Lo, SDOperand &Hi);
227 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
228 SDOperand &Lo, SDOperand &Hi);
230 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
231 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
235 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
236 /// specified mask and type. Targets can specify exactly which masks they
237 /// support and the code generator is tasked with not creating illegal masks.
239 /// Note that this will also return true for shuffles that are promoted to a
241 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
242 SDOperand Mask) const {
243 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
245 case TargetLowering::Legal:
246 case TargetLowering::Custom:
248 case TargetLowering::Promote: {
249 // If this is promoted to a different type, convert the shuffle mask and
250 // ask if it is legal in the promoted type!
251 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
253 // If we changed # elements, change the shuffle mask.
254 unsigned NumEltsGrowth =
255 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
256 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
257 if (NumEltsGrowth > 1) {
258 // Renumber the elements.
259 SmallVector<SDOperand, 8> Ops;
260 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
261 SDOperand InOp = Mask.getOperand(i);
262 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
263 if (InOp.getOpcode() == ISD::UNDEF)
264 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
266 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
267 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
271 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
277 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
280 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
281 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
282 ValueTypeActions(TLI.getValueTypeActions()) {
283 assert(MVT::LAST_VALUETYPE <= 32 &&
284 "Too many value types for ValueTypeActions to hold!");
287 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
288 /// contains all of a nodes operands before it contains the node.
289 static void ComputeTopDownOrdering(SelectionDAG &DAG,
290 SmallVector<SDNode*, 64> &Order) {
292 DenseMap<SDNode*, unsigned> Visited;
293 std::vector<SDNode*> Worklist;
294 Worklist.reserve(128);
296 // Compute ordering from all of the leaves in the graphs, those (like the
297 // entry node) that have no operands.
298 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
299 E = DAG.allnodes_end(); I != E; ++I) {
300 if (I->getNumOperands() == 0) {
302 Worklist.push_back(I);
306 while (!Worklist.empty()) {
307 SDNode *N = Worklist.back();
310 if (++Visited[N] != N->getNumOperands())
311 continue; // Haven't visited all operands yet
315 // Now that we have N in, add anything that uses it if all of their operands
317 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
319 Worklist.push_back(UI->getUser());
322 assert(Order.size() == Visited.size() &&
324 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
325 "Error: DAG is cyclic!");
329 void SelectionDAGLegalize::LegalizeDAG() {
330 LastCALLSEQ_END = DAG.getEntryNode();
331 IsLegalizingCall = false;
333 // The legalize process is inherently a bottom-up recursive process (users
334 // legalize their uses before themselves). Given infinite stack space, we
335 // could just start legalizing on the root and traverse the whole graph. In
336 // practice however, this causes us to run out of stack space on large basic
337 // blocks. To avoid this problem, compute an ordering of the nodes where each
338 // node is only legalized after all of its operands are legalized.
339 SmallVector<SDNode*, 64> Order;
340 ComputeTopDownOrdering(DAG, Order);
342 for (unsigned i = 0, e = Order.size(); i != e; ++i)
343 HandleOp(SDOperand(Order[i], 0));
345 // Finally, it's possible the root changed. Get the new root.
346 SDOperand OldRoot = DAG.getRoot();
347 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
348 DAG.setRoot(LegalizedNodes[OldRoot]);
350 ExpandedNodes.clear();
351 LegalizedNodes.clear();
352 PromotedNodes.clear();
354 ScalarizedNodes.clear();
356 // Remove dead nodes now.
357 DAG.RemoveDeadNodes();
361 /// FindCallEndFromCallStart - Given a chained node that is part of a call
362 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
363 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
364 if (Node->getOpcode() == ISD::CALLSEQ_END)
366 if (Node->use_empty())
367 return 0; // No CallSeqEnd
369 // The chain is usually at the end.
370 SDOperand TheChain(Node, Node->getNumValues()-1);
371 if (TheChain.getValueType() != MVT::Other) {
372 // Sometimes it's at the beginning.
373 TheChain = SDOperand(Node, 0);
374 if (TheChain.getValueType() != MVT::Other) {
375 // Otherwise, hunt for it.
376 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
377 if (Node->getValueType(i) == MVT::Other) {
378 TheChain = SDOperand(Node, i);
382 // Otherwise, we walked into a node without a chain.
383 if (TheChain.getValueType() != MVT::Other)
388 for (SDNode::use_iterator UI = Node->use_begin(),
389 E = Node->use_end(); UI != E; ++UI) {
391 // Make sure to only follow users of our token chain.
392 SDNode *User = UI->getUser();
393 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
394 if (User->getOperand(i) == TheChain)
395 if (SDNode *Result = FindCallEndFromCallStart(User))
401 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
402 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
403 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
404 assert(Node && "Didn't find callseq_start for a call??");
405 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
407 assert(Node->getOperand(0).getValueType() == MVT::Other &&
408 "Node doesn't have a token chain argument!");
409 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
412 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
413 /// see if any uses can reach Dest. If no dest operands can get to dest,
414 /// legalize them, legalize ourself, and return false, otherwise, return true.
416 /// Keep track of the nodes we fine that actually do lead to Dest in
417 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
419 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
420 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
421 if (N == Dest) return true; // N certainly leads to Dest :)
423 // If we've already processed this node and it does lead to Dest, there is no
424 // need to reprocess it.
425 if (NodesLeadingTo.count(N)) return true;
427 // If the first result of this node has been already legalized, then it cannot
429 switch (getTypeAction(N->getValueType(0))) {
431 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
434 if (PromotedNodes.count(SDOperand(N, 0))) return false;
437 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
441 // Okay, this node has not already been legalized. Check and legalize all
442 // operands. If none lead to Dest, then we can legalize this node.
443 bool OperandsLeadToDest = false;
444 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
445 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
446 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
448 if (OperandsLeadToDest) {
449 NodesLeadingTo.insert(N);
453 // Okay, this node looks safe, legalize it and return false.
454 HandleOp(SDOperand(N, 0));
458 /// HandleOp - Legalize, Promote, or Expand the specified operand as
459 /// appropriate for its type.
460 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
461 MVT::ValueType VT = Op.getValueType();
462 switch (getTypeAction(VT)) {
463 default: assert(0 && "Bad type action!");
464 case Legal: (void)LegalizeOp(Op); break;
465 case Promote: (void)PromoteOp(Op); break;
467 if (!MVT::isVector(VT)) {
468 // If this is an illegal scalar, expand it into its two component
471 if (Op.getOpcode() == ISD::TargetConstant)
472 break; // Allow illegal target nodes.
474 } else if (MVT::getVectorNumElements(VT) == 1) {
475 // If this is an illegal single element vector, convert it to a
477 (void)ScalarizeVectorOp(Op);
479 // Otherwise, this is an illegal multiple element vector.
480 // Split it in half and legalize both parts.
482 SplitVectorOp(Op, X, Y);
488 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
489 /// a load from the constant pool.
490 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
491 SelectionDAG &DAG, TargetLowering &TLI) {
494 // If a FP immediate is precise when represented as a float and if the
495 // target can do an extending load from float to double, we put it into
496 // the constant pool as a float, even if it's is statically typed as a
497 // double. This shrinks FP constants and canonicalizes them for targets where
498 // an FP extending load is the same cost as a normal load (such as on the x87
499 // fp stack or PPC FP unit).
500 MVT::ValueType VT = CFP->getValueType(0);
501 ConstantFP *LLVMC = ConstantFP::get(CFP->getValueAPF());
503 if (VT!=MVT::f64 && VT!=MVT::f32)
504 assert(0 && "Invalid type expansion");
505 return DAG.getConstant(LLVMC->getValueAPF().convertToAPInt(),
506 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
509 MVT::ValueType OrigVT = VT;
510 MVT::ValueType SVT = VT;
511 while (SVT != MVT::f32) {
512 SVT = (unsigned)SVT - 1;
513 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
514 // Only do this if the target has a native EXTLOAD instruction from
516 TLI.isLoadXLegal(ISD::EXTLOAD, SVT) &&
517 TLI.ShouldShrinkFPConstant(OrigVT)) {
518 const Type *SType = MVT::getTypeForValueType(SVT);
519 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
525 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
527 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
528 CPIdx, PseudoSourceValue::getConstantPool(),
530 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
531 PseudoSourceValue::getConstantPool(), 0);
535 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
538 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
539 SelectionDAG &DAG, TargetLowering &TLI) {
540 MVT::ValueType VT = Node->getValueType(0);
541 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
542 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
543 "fcopysign expansion only supported for f32 and f64");
544 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
546 // First get the sign bit of second operand.
547 SDOperand Mask1 = (SrcVT == MVT::f64)
548 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
549 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
550 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
551 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
552 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
553 // Shift right or sign-extend it if the two operands have different types.
554 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
556 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
557 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
558 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
559 } else if (SizeDiff < 0)
560 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
562 // Clear the sign bit of first operand.
563 SDOperand Mask2 = (VT == MVT::f64)
564 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
565 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
566 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
567 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
568 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
570 // Or the value with the sign bit.
571 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
575 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
577 SDOperand ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
578 TargetLowering &TLI) {
579 SDOperand Chain = ST->getChain();
580 SDOperand Ptr = ST->getBasePtr();
581 SDOperand Val = ST->getValue();
582 MVT::ValueType VT = Val.getValueType();
583 int Alignment = ST->getAlignment();
584 int SVOffset = ST->getSrcValueOffset();
585 if (MVT::isFloatingPoint(ST->getMemoryVT()) ||
586 MVT::isVector(ST->getMemoryVT())) {
587 // Expand to a bitconvert of the value to the integer type of the
588 // same size, then a (misaligned) int store.
589 MVT::ValueType intVT;
590 if (MVT::is128BitVector(VT) || VT == MVT::ppcf128 || VT == MVT::f128)
592 else if (MVT::is64BitVector(VT) || VT==MVT::f64)
594 else if (VT==MVT::f32)
597 assert(0 && "Unaligned store of unsupported type");
599 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
600 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
601 SVOffset, ST->isVolatile(), Alignment);
603 assert(MVT::isInteger(ST->getMemoryVT()) &&
604 !MVT::isVector(ST->getMemoryVT()) &&
605 "Unaligned store of unknown type.");
606 // Get the half-size VT
607 MVT::ValueType NewStoredVT = ST->getMemoryVT() - 1;
608 int NumBits = MVT::getSizeInBits(NewStoredVT);
609 int IncrementSize = NumBits / 8;
611 // Divide the stored value in two parts.
612 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
614 SDOperand Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
616 // Store the two parts
617 SDOperand Store1, Store2;
618 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
619 ST->getSrcValue(), SVOffset, NewStoredVT,
620 ST->isVolatile(), Alignment);
621 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
622 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
623 Alignment = MinAlign(Alignment, IncrementSize);
624 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
625 ST->getSrcValue(), SVOffset + IncrementSize,
626 NewStoredVT, ST->isVolatile(), Alignment);
628 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
631 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
633 SDOperand ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
634 TargetLowering &TLI) {
635 int SVOffset = LD->getSrcValueOffset();
636 SDOperand Chain = LD->getChain();
637 SDOperand Ptr = LD->getBasePtr();
638 MVT::ValueType VT = LD->getValueType(0);
639 MVT::ValueType LoadedVT = LD->getMemoryVT();
640 if (MVT::isFloatingPoint(VT) || MVT::isVector(VT)) {
641 // Expand to a (misaligned) integer load of the same size,
642 // then bitconvert to floating point or vector.
643 MVT::ValueType intVT;
644 if (MVT::is128BitVector(LoadedVT) ||
645 LoadedVT == MVT::ppcf128 || LoadedVT == MVT::f128)
647 else if (MVT::is64BitVector(LoadedVT) || LoadedVT == MVT::f64)
649 else if (LoadedVT == MVT::f32)
652 assert(0 && "Unaligned load of unsupported type");
654 SDOperand newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
655 SVOffset, LD->isVolatile(),
657 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
658 if (MVT::isFloatingPoint(VT) && LoadedVT != VT)
659 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
661 SDOperand Ops[] = { Result, Chain };
662 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
665 assert(MVT::isInteger(LoadedVT) && !MVT::isVector(LoadedVT) &&
666 "Unaligned load of unsupported type.");
668 // Compute the new VT that is half the size of the old one. This is an
670 unsigned NumBits = MVT::getSizeInBits(LoadedVT);
671 MVT::ValueType NewLoadedVT;
672 NewLoadedVT = MVT::getIntegerType(NumBits/2);
675 unsigned Alignment = LD->getAlignment();
676 unsigned IncrementSize = NumBits / 8;
677 ISD::LoadExtType HiExtType = LD->getExtensionType();
679 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
680 if (HiExtType == ISD::NON_EXTLOAD)
681 HiExtType = ISD::ZEXTLOAD;
683 // Load the value in two parts
685 if (TLI.isLittleEndian()) {
686 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
687 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
688 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
689 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
690 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
691 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
692 MinAlign(Alignment, IncrementSize));
694 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
695 NewLoadedVT,LD->isVolatile(), Alignment);
696 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
697 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
698 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
699 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
700 MinAlign(Alignment, IncrementSize));
703 // aggregate the two parts
704 SDOperand ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
705 SDOperand Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
706 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
708 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
711 SDOperand Ops[] = { Result, TF };
712 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other), Ops, 2);
715 /// UnrollVectorOp - We know that the given vector has a legal type, however
716 /// the operation it performs is not legal and is an operation that we have
717 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
718 /// operating on each element individually.
719 SDOperand SelectionDAGLegalize::UnrollVectorOp(SDOperand Op) {
720 MVT::ValueType VT = Op.getValueType();
721 assert(isTypeLegal(VT) &&
722 "Caller should expand or promote operands that are not legal!");
723 assert(Op.Val->getNumValues() == 1 &&
724 "Can't unroll a vector with multiple results!");
725 unsigned NE = MVT::getVectorNumElements(VT);
726 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
728 SmallVector<SDOperand, 8> Scalars;
729 SmallVector<SDOperand, 4> Operands(Op.getNumOperands());
730 for (unsigned i = 0; i != NE; ++i) {
731 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
732 SDOperand Operand = Op.getOperand(j);
733 MVT::ValueType OperandVT = Operand.getValueType();
734 if (MVT::isVector(OperandVT)) {
735 // A vector operand; extract a single element.
736 MVT::ValueType OperandEltVT = MVT::getVectorElementType(OperandVT);
737 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
740 DAG.getConstant(i, MVT::i32));
742 // A scalar operand; just use it as is.
743 Operands[j] = Operand;
746 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
747 &Operands[0], Operands.size()));
750 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
753 /// GetFPLibCall - Return the right libcall for the given floating point type.
754 static RTLIB::Libcall GetFPLibCall(MVT::ValueType VT,
755 RTLIB::Libcall Call_F32,
756 RTLIB::Libcall Call_F64,
757 RTLIB::Libcall Call_F80,
758 RTLIB::Libcall Call_PPCF128) {
760 VT == MVT::f32 ? Call_F32 :
761 VT == MVT::f64 ? Call_F64 :
762 VT == MVT::f80 ? Call_F80 :
763 VT == MVT::ppcf128 ? Call_PPCF128 :
764 RTLIB::UNKNOWN_LIBCALL;
767 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
768 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
769 /// is necessary to spill the vector being inserted into to memory, perform
770 /// the insert there, and then read the result back.
771 SDOperand SelectionDAGLegalize::
772 PerformInsertVectorEltInMemory(SDOperand Vec, SDOperand Val, SDOperand Idx) {
773 SDOperand Tmp1 = Vec;
774 SDOperand Tmp2 = Val;
775 SDOperand Tmp3 = Idx;
777 // If the target doesn't support this, we have to spill the input vector
778 // to a temporary stack slot, update the element, then reload it. This is
779 // badness. We could also load the value into a vector register (either
780 // with a "move to register" or "extload into register" instruction, then
781 // permute it into place, if the idx is a constant and if the idx is
782 // supported by the target.
783 MVT::ValueType VT = Tmp1.getValueType();
784 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
785 MVT::ValueType IdxVT = Tmp3.getValueType();
786 MVT::ValueType PtrVT = TLI.getPointerTy();
787 SDOperand StackPtr = DAG.CreateStackTemporary(VT);
789 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr.Val);
790 int SPFI = StackPtrFI->getIndex();
793 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
794 PseudoSourceValue::getFixedStack(),
797 // Truncate or zero extend offset to target pointer type.
798 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
799 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
800 // Add the offset to the index.
801 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
802 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
803 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
804 // Store the scalar value.
805 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
806 PseudoSourceValue::getFixedStack(), SPFI, EltVT);
807 // Load the updated vector.
808 return DAG.getLoad(VT, Ch, StackPtr, PseudoSourceValue::getFixedStack(),SPFI);
811 /// LegalizeOp - We know that the specified value has a legal type, and
812 /// that its operands are legal. Now ensure that the operation itself
813 /// is legal, recursively ensuring that the operands' operations remain
815 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
816 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
819 assert(isTypeLegal(Op.getValueType()) &&
820 "Caller should expand or promote operands that are not legal!");
821 SDNode *Node = Op.Val;
823 // If this operation defines any values that cannot be represented in a
824 // register on this target, make sure to expand or promote them.
825 if (Node->getNumValues() > 1) {
826 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
827 if (getTypeAction(Node->getValueType(i)) != Legal) {
828 HandleOp(Op.getValue(i));
829 assert(LegalizedNodes.count(Op) &&
830 "Handling didn't add legal operands!");
831 return LegalizedNodes[Op];
835 // Note that LegalizeOp may be reentered even from single-use nodes, which
836 // means that we always must cache transformed nodes.
837 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
838 if (I != LegalizedNodes.end()) return I->second;
840 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
841 SDOperand Result = Op;
842 bool isCustom = false;
844 switch (Node->getOpcode()) {
845 case ISD::FrameIndex:
846 case ISD::EntryToken:
848 case ISD::BasicBlock:
849 case ISD::TargetFrameIndex:
850 case ISD::TargetJumpTable:
851 case ISD::TargetConstant:
852 case ISD::TargetConstantFP:
853 case ISD::TargetConstantPool:
854 case ISD::TargetGlobalAddress:
855 case ISD::TargetGlobalTLSAddress:
856 case ISD::TargetExternalSymbol:
859 case ISD::MEMOPERAND:
863 // Primitives must all be legal.
864 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
865 "This must be legal!");
868 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
869 // If this is a target node, legalize it by legalizing the operands then
870 // passing it through.
871 SmallVector<SDOperand, 8> Ops;
872 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
873 Ops.push_back(LegalizeOp(Node->getOperand(i)));
875 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
877 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
878 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
879 return Result.getValue(Op.ResNo);
881 // Otherwise this is an unhandled builtin node. splat.
883 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
885 assert(0 && "Do not know how to legalize this operator!");
887 case ISD::GLOBAL_OFFSET_TABLE:
888 case ISD::GlobalAddress:
889 case ISD::GlobalTLSAddress:
890 case ISD::ExternalSymbol:
891 case ISD::ConstantPool:
892 case ISD::JumpTable: // Nothing to do.
893 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
894 default: assert(0 && "This action is not supported yet!");
895 case TargetLowering::Custom:
896 Tmp1 = TLI.LowerOperation(Op, DAG);
897 if (Tmp1.Val) Result = Tmp1;
898 // FALLTHROUGH if the target doesn't want to lower this op after all.
899 case TargetLowering::Legal:
904 case ISD::RETURNADDR:
905 // The only option for these nodes is to custom lower them. If the target
906 // does not custom lower them, then return zero.
907 Tmp1 = TLI.LowerOperation(Op, DAG);
911 Result = DAG.getConstant(0, TLI.getPointerTy());
913 case ISD::FRAME_TO_ARGS_OFFSET: {
914 MVT::ValueType VT = Node->getValueType(0);
915 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
916 default: assert(0 && "This action is not supported yet!");
917 case TargetLowering::Custom:
918 Result = TLI.LowerOperation(Op, DAG);
919 if (Result.Val) break;
921 case TargetLowering::Legal:
922 Result = DAG.getConstant(0, VT);
927 case ISD::EXCEPTIONADDR: {
928 Tmp1 = LegalizeOp(Node->getOperand(0));
929 MVT::ValueType VT = Node->getValueType(0);
930 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
931 default: assert(0 && "This action is not supported yet!");
932 case TargetLowering::Expand: {
933 unsigned Reg = TLI.getExceptionAddressRegister();
934 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
937 case TargetLowering::Custom:
938 Result = TLI.LowerOperation(Op, DAG);
939 if (Result.Val) break;
941 case TargetLowering::Legal: {
942 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
943 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
949 if (Result.Val->getNumValues() == 1) break;
951 assert(Result.Val->getNumValues() == 2 &&
952 "Cannot return more than two values!");
954 // Since we produced two values, make sure to remember that we
955 // legalized both of them.
956 Tmp1 = LegalizeOp(Result);
957 Tmp2 = LegalizeOp(Result.getValue(1));
958 AddLegalizedOperand(Op.getValue(0), Tmp1);
959 AddLegalizedOperand(Op.getValue(1), Tmp2);
960 return Op.ResNo ? Tmp2 : Tmp1;
961 case ISD::EHSELECTION: {
962 Tmp1 = LegalizeOp(Node->getOperand(0));
963 Tmp2 = LegalizeOp(Node->getOperand(1));
964 MVT::ValueType VT = Node->getValueType(0);
965 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
966 default: assert(0 && "This action is not supported yet!");
967 case TargetLowering::Expand: {
968 unsigned Reg = TLI.getExceptionSelectorRegister();
969 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
972 case TargetLowering::Custom:
973 Result = TLI.LowerOperation(Op, DAG);
974 if (Result.Val) break;
976 case TargetLowering::Legal: {
977 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
978 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
984 if (Result.Val->getNumValues() == 1) break;
986 assert(Result.Val->getNumValues() == 2 &&
987 "Cannot return more than two values!");
989 // Since we produced two values, make sure to remember that we
990 // legalized both of them.
991 Tmp1 = LegalizeOp(Result);
992 Tmp2 = LegalizeOp(Result.getValue(1));
993 AddLegalizedOperand(Op.getValue(0), Tmp1);
994 AddLegalizedOperand(Op.getValue(1), Tmp2);
995 return Op.ResNo ? Tmp2 : Tmp1;
996 case ISD::EH_RETURN: {
997 MVT::ValueType VT = Node->getValueType(0);
998 // The only "good" option for this node is to custom lower it.
999 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1000 default: assert(0 && "This action is not supported at all!");
1001 case TargetLowering::Custom:
1002 Result = TLI.LowerOperation(Op, DAG);
1003 if (Result.Val) break;
1005 case TargetLowering::Legal:
1006 // Target does not know, how to lower this, lower to noop
1007 Result = LegalizeOp(Node->getOperand(0));
1012 case ISD::AssertSext:
1013 case ISD::AssertZext:
1014 Tmp1 = LegalizeOp(Node->getOperand(0));
1015 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1017 case ISD::MERGE_VALUES:
1018 // Legalize eliminates MERGE_VALUES nodes.
1019 Result = Node->getOperand(Op.ResNo);
1021 case ISD::CopyFromReg:
1022 Tmp1 = LegalizeOp(Node->getOperand(0));
1023 Result = Op.getValue(0);
1024 if (Node->getNumValues() == 2) {
1025 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1027 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1028 if (Node->getNumOperands() == 3) {
1029 Tmp2 = LegalizeOp(Node->getOperand(2));
1030 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1032 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1034 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1036 // Since CopyFromReg produces two values, make sure to remember that we
1037 // legalized both of them.
1038 AddLegalizedOperand(Op.getValue(0), Result);
1039 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1040 return Result.getValue(Op.ResNo);
1042 MVT::ValueType VT = Op.getValueType();
1043 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1044 default: assert(0 && "This action is not supported yet!");
1045 case TargetLowering::Expand:
1046 if (MVT::isInteger(VT))
1047 Result = DAG.getConstant(0, VT);
1048 else if (MVT::isFloatingPoint(VT))
1049 Result = DAG.getConstantFP(APFloat(APInt(MVT::getSizeInBits(VT), 0)),
1052 assert(0 && "Unknown value type!");
1054 case TargetLowering::Legal:
1060 case ISD::INTRINSIC_W_CHAIN:
1061 case ISD::INTRINSIC_WO_CHAIN:
1062 case ISD::INTRINSIC_VOID: {
1063 SmallVector<SDOperand, 8> Ops;
1064 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1065 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1066 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1068 // Allow the target to custom lower its intrinsics if it wants to.
1069 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1070 TargetLowering::Custom) {
1071 Tmp3 = TLI.LowerOperation(Result, DAG);
1072 if (Tmp3.Val) Result = Tmp3;
1075 if (Result.Val->getNumValues() == 1) break;
1077 // Must have return value and chain result.
1078 assert(Result.Val->getNumValues() == 2 &&
1079 "Cannot return more than two values!");
1081 // Since loads produce two values, make sure to remember that we
1082 // legalized both of them.
1083 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1084 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1085 return Result.getValue(Op.ResNo);
1089 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
1090 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1092 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
1093 case TargetLowering::Promote:
1094 default: assert(0 && "This action is not supported yet!");
1095 case TargetLowering::Expand: {
1096 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1097 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1098 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
1100 if (MMI && (useDEBUG_LOC || useLABEL)) {
1101 const std::string &FName =
1102 cast<StringSDNode>(Node->getOperand(3))->getValue();
1103 const std::string &DirName =
1104 cast<StringSDNode>(Node->getOperand(4))->getValue();
1105 unsigned SrcFile = MMI->RecordSource(DirName, FName);
1107 SmallVector<SDOperand, 8> Ops;
1108 Ops.push_back(Tmp1); // chain
1109 SDOperand LineOp = Node->getOperand(1);
1110 SDOperand ColOp = Node->getOperand(2);
1113 Ops.push_back(LineOp); // line #
1114 Ops.push_back(ColOp); // col #
1115 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
1116 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
1118 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
1119 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
1120 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1121 Ops.push_back(DAG.getConstant(ID, MVT::i32));
1122 Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
1123 Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
1126 Result = Tmp1; // chain
1130 case TargetLowering::Legal:
1131 if (Tmp1 != Node->getOperand(0) ||
1132 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
1133 SmallVector<SDOperand, 8> Ops;
1134 Ops.push_back(Tmp1);
1135 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
1136 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1137 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1139 // Otherwise promote them.
1140 Ops.push_back(PromoteOp(Node->getOperand(1)));
1141 Ops.push_back(PromoteOp(Node->getOperand(2)));
1143 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1144 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1145 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1152 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1153 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1154 default: assert(0 && "This action is not supported yet!");
1155 case TargetLowering::Legal:
1156 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1157 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1158 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1159 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1161 case TargetLowering::Expand:
1162 Result = LegalizeOp(Node->getOperand(0));
1167 case ISD::DEBUG_LOC:
1168 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1169 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1170 default: assert(0 && "This action is not supported yet!");
1171 case TargetLowering::Legal:
1172 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1173 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1174 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1175 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1176 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1182 assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
1183 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
1184 default: assert(0 && "This action is not supported yet!");
1185 case TargetLowering::Legal:
1186 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1187 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
1188 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
1189 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1191 case TargetLowering::Expand:
1192 Result = LegalizeOp(Node->getOperand(0));
1198 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1199 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1200 default: assert(0 && "This action is not supported yet!");
1201 case TargetLowering::Legal:
1202 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1204 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1205 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1208 case TargetLowering::Expand:
1210 Result = LegalizeOp(Node->getOperand(0));
1215 case ISD::MEMBARRIER: {
1216 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1217 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1218 default: assert(0 && "This action is not supported yet!");
1219 case TargetLowering::Legal: {
1221 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1222 for (int x = 1; x < 6; ++x) {
1223 Ops[x] = Node->getOperand(x);
1224 if (!isTypeLegal(Ops[x].getValueType()))
1225 Ops[x] = PromoteOp(Ops[x]);
1227 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1230 case TargetLowering::Expand:
1231 //There is no libgcc call for this op
1232 Result = Node->getOperand(0); // Noop
1238 case ISD::ATOMIC_LCS: {
1239 unsigned int num_operands = 4;
1240 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1242 for (unsigned int x = 0; x < num_operands; ++x)
1243 Ops[x] = LegalizeOp(Node->getOperand(x));
1244 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1246 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1247 default: assert(0 && "This action is not supported yet!");
1248 case TargetLowering::Custom:
1249 Result = TLI.LowerOperation(Result, DAG);
1251 case TargetLowering::Legal:
1254 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1255 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1256 return Result.getValue(Op.ResNo);
1258 case ISD::ATOMIC_LAS:
1259 case ISD::ATOMIC_LSS:
1260 case ISD::ATOMIC_LOAD_AND:
1261 case ISD::ATOMIC_LOAD_OR:
1262 case ISD::ATOMIC_LOAD_XOR:
1263 case ISD::ATOMIC_LOAD_MIN:
1264 case ISD::ATOMIC_LOAD_MAX:
1265 case ISD::ATOMIC_LOAD_UMIN:
1266 case ISD::ATOMIC_LOAD_UMAX:
1267 case ISD::ATOMIC_SWAP: {
1268 unsigned int num_operands = 3;
1269 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1271 for (unsigned int x = 0; x < num_operands; ++x)
1272 Ops[x] = LegalizeOp(Node->getOperand(x));
1273 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1275 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1276 default: assert(0 && "This action is not supported yet!");
1277 case TargetLowering::Custom:
1278 Result = TLI.LowerOperation(Result, DAG);
1280 case TargetLowering::Expand:
1281 Result = SDOperand(TLI.ExpandOperationResult(Op.Val, DAG),0);
1283 case TargetLowering::Legal:
1286 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1287 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1288 return Result.getValue(Op.ResNo);
1290 case ISD::Constant: {
1291 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1293 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1295 // We know we don't need to expand constants here, constants only have one
1296 // value and we check that it is fine above.
1298 if (opAction == TargetLowering::Custom) {
1299 Tmp1 = TLI.LowerOperation(Result, DAG);
1305 case ISD::ConstantFP: {
1306 // Spill FP immediates to the constant pool if the target cannot directly
1307 // codegen them. Targets often have some immediate values that can be
1308 // efficiently generated into an FP register without a load. We explicitly
1309 // leave these constants as ConstantFP nodes for the target to deal with.
1310 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1312 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1313 default: assert(0 && "This action is not supported yet!");
1314 case TargetLowering::Legal:
1316 case TargetLowering::Custom:
1317 Tmp3 = TLI.LowerOperation(Result, DAG);
1323 case TargetLowering::Expand: {
1324 // Check to see if this FP immediate is already legal.
1325 bool isLegal = false;
1326 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1327 E = TLI.legal_fpimm_end(); I != E; ++I) {
1328 if (CFP->isExactlyValue(*I)) {
1333 // If this is a legal constant, turn it into a TargetConstantFP node.
1336 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1341 case ISD::TokenFactor:
1342 if (Node->getNumOperands() == 2) {
1343 Tmp1 = LegalizeOp(Node->getOperand(0));
1344 Tmp2 = LegalizeOp(Node->getOperand(1));
1345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1346 } else if (Node->getNumOperands() == 3) {
1347 Tmp1 = LegalizeOp(Node->getOperand(0));
1348 Tmp2 = LegalizeOp(Node->getOperand(1));
1349 Tmp3 = LegalizeOp(Node->getOperand(2));
1350 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1352 SmallVector<SDOperand, 8> Ops;
1353 // Legalize the operands.
1354 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1355 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1356 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1360 case ISD::FORMAL_ARGUMENTS:
1362 // The only option for this is to custom lower it.
1363 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1364 assert(Tmp3.Val && "Target didn't custom lower this node!");
1365 // A call within a calling sequence must be legalized to something
1366 // other than the normal CALLSEQ_END. Violating this gets Legalize
1367 // into an infinite loop.
1368 assert ((!IsLegalizingCall ||
1369 Node->getOpcode() != ISD::CALL ||
1370 Tmp3.Val->getOpcode() != ISD::CALLSEQ_END) &&
1371 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1373 // The number of incoming and outgoing values should match; unless the final
1374 // outgoing value is a flag.
1375 assert((Tmp3.Val->getNumValues() == Result.Val->getNumValues() ||
1376 (Tmp3.Val->getNumValues() == Result.Val->getNumValues() + 1 &&
1377 Tmp3.Val->getValueType(Tmp3.Val->getNumValues() - 1) ==
1379 "Lowering call/formal_arguments produced unexpected # results!");
1381 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1382 // remember that we legalized all of them, so it doesn't get relegalized.
1383 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
1384 if (Tmp3.Val->getValueType(i) == MVT::Flag)
1386 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1389 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
1392 case ISD::EXTRACT_SUBREG: {
1393 Tmp1 = LegalizeOp(Node->getOperand(0));
1394 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1395 assert(idx && "Operand must be a constant");
1396 Tmp2 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1397 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1400 case ISD::INSERT_SUBREG: {
1401 Tmp1 = LegalizeOp(Node->getOperand(0));
1402 Tmp2 = LegalizeOp(Node->getOperand(1));
1403 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1404 assert(idx && "Operand must be a constant");
1405 Tmp3 = DAG.getTargetConstant(idx->getValue(), idx->getValueType(0));
1406 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1409 case ISD::BUILD_VECTOR:
1410 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1411 default: assert(0 && "This action is not supported yet!");
1412 case TargetLowering::Custom:
1413 Tmp3 = TLI.LowerOperation(Result, DAG);
1419 case TargetLowering::Expand:
1420 Result = ExpandBUILD_VECTOR(Result.Val);
1424 case ISD::INSERT_VECTOR_ELT:
1425 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1426 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1428 // The type of the value to insert may not be legal, even though the vector
1429 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1431 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1432 default: assert(0 && "Cannot expand insert element operand");
1433 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1434 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1438 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1439 Node->getValueType(0))) {
1440 default: assert(0 && "This action is not supported yet!");
1441 case TargetLowering::Legal:
1443 case TargetLowering::Custom:
1444 Tmp4 = TLI.LowerOperation(Result, DAG);
1450 case TargetLowering::Expand: {
1451 // If the insert index is a constant, codegen this as a scalar_to_vector,
1452 // then a shuffle that inserts it into the right position in the vector.
1453 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1454 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1455 // match the element type of the vector being created.
1456 if (Tmp2.getValueType() ==
1457 MVT::getVectorElementType(Op.getValueType())) {
1458 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1459 Tmp1.getValueType(), Tmp2);
1461 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1462 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1463 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1465 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1466 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1467 // elt 0 of the RHS.
1468 SmallVector<SDOperand, 8> ShufOps;
1469 for (unsigned i = 0; i != NumElts; ++i) {
1470 if (i != InsertPos->getValue())
1471 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1473 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1475 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1476 &ShufOps[0], ShufOps.size());
1478 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1479 Tmp1, ScVec, ShufMask);
1480 Result = LegalizeOp(Result);
1484 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1489 case ISD::SCALAR_TO_VECTOR:
1490 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1491 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1495 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1496 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1497 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1498 Node->getValueType(0))) {
1499 default: assert(0 && "This action is not supported yet!");
1500 case TargetLowering::Legal:
1502 case TargetLowering::Custom:
1503 Tmp3 = TLI.LowerOperation(Result, DAG);
1509 case TargetLowering::Expand:
1510 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1514 case ISD::VECTOR_SHUFFLE:
1515 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1516 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1517 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1519 // Allow targets to custom lower the SHUFFLEs they support.
1520 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1521 default: assert(0 && "Unknown operation action!");
1522 case TargetLowering::Legal:
1523 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1524 "vector shuffle should not be created if not legal!");
1526 case TargetLowering::Custom:
1527 Tmp3 = TLI.LowerOperation(Result, DAG);
1533 case TargetLowering::Expand: {
1534 MVT::ValueType VT = Node->getValueType(0);
1535 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1536 MVT::ValueType PtrVT = TLI.getPointerTy();
1537 SDOperand Mask = Node->getOperand(2);
1538 unsigned NumElems = Mask.getNumOperands();
1539 SmallVector<SDOperand,8> Ops;
1540 for (unsigned i = 0; i != NumElems; ++i) {
1541 SDOperand Arg = Mask.getOperand(i);
1542 if (Arg.getOpcode() == ISD::UNDEF) {
1543 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1545 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1546 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1548 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1549 DAG.getConstant(Idx, PtrVT)));
1551 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1552 DAG.getConstant(Idx - NumElems, PtrVT)));
1555 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1558 case TargetLowering::Promote: {
1559 // Change base type to a different vector type.
1560 MVT::ValueType OVT = Node->getValueType(0);
1561 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1563 // Cast the two input vectors.
1564 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1565 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1567 // Convert the shuffle mask to the right # elements.
1568 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1569 assert(Tmp3.Val && "Shuffle not legal?");
1570 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1571 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1577 case ISD::EXTRACT_VECTOR_ELT:
1578 Tmp1 = Node->getOperand(0);
1579 Tmp2 = LegalizeOp(Node->getOperand(1));
1580 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1581 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1584 case ISD::EXTRACT_SUBVECTOR:
1585 Tmp1 = Node->getOperand(0);
1586 Tmp2 = LegalizeOp(Node->getOperand(1));
1587 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1588 Result = ExpandEXTRACT_SUBVECTOR(Result);
1591 case ISD::CALLSEQ_START: {
1592 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1594 // Recursively Legalize all of the inputs of the call end that do not lead
1595 // to this call start. This ensures that any libcalls that need be inserted
1596 // are inserted *before* the CALLSEQ_START.
1597 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1598 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1599 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1603 // Now that we legalized all of the inputs (which may have inserted
1604 // libcalls) create the new CALLSEQ_START node.
1605 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1607 // Merge in the last call, to ensure that this call start after the last
1609 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1610 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1611 Tmp1 = LegalizeOp(Tmp1);
1614 // Do not try to legalize the target-specific arguments (#1+).
1615 if (Tmp1 != Node->getOperand(0)) {
1616 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1618 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1621 // Remember that the CALLSEQ_START is legalized.
1622 AddLegalizedOperand(Op.getValue(0), Result);
1623 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1624 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1626 // Now that the callseq_start and all of the non-call nodes above this call
1627 // sequence have been legalized, legalize the call itself. During this
1628 // process, no libcalls can/will be inserted, guaranteeing that no calls
1630 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1631 SDOperand InCallSEQ = LastCALLSEQ_END;
1632 // Note that we are selecting this call!
1633 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1634 IsLegalizingCall = true;
1636 // Legalize the call, starting from the CALLSEQ_END.
1637 LegalizeOp(LastCALLSEQ_END);
1638 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1641 case ISD::CALLSEQ_END:
1642 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1643 // will cause this node to be legalized as well as handling libcalls right.
1644 if (LastCALLSEQ_END.Val != Node) {
1645 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1646 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1647 assert(I != LegalizedNodes.end() &&
1648 "Legalizing the call start should have legalized this node!");
1652 // Otherwise, the call start has been legalized and everything is going
1653 // according to plan. Just legalize ourselves normally here.
1654 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1655 // Do not try to legalize the target-specific arguments (#1+), except for
1656 // an optional flag input.
1657 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1658 if (Tmp1 != Node->getOperand(0)) {
1659 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1661 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1664 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1665 if (Tmp1 != Node->getOperand(0) ||
1666 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1667 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1670 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1673 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1674 // This finishes up call legalization.
1675 IsLegalizingCall = false;
1677 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1678 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1679 if (Node->getNumValues() == 2)
1680 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1681 return Result.getValue(Op.ResNo);
1682 case ISD::DYNAMIC_STACKALLOC: {
1683 MVT::ValueType VT = Node->getValueType(0);
1684 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1685 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1686 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1689 Tmp1 = Result.getValue(0);
1690 Tmp2 = Result.getValue(1);
1691 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1692 default: assert(0 && "This action is not supported yet!");
1693 case TargetLowering::Expand: {
1694 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1695 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1696 " not tell us which reg is the stack pointer!");
1697 SDOperand Chain = Tmp1.getOperand(0);
1699 // Chain the dynamic stack allocation so that it doesn't modify the stack
1700 // pointer when other instructions are using the stack.
1701 Chain = DAG.getCALLSEQ_START(Chain,
1702 DAG.getConstant(0, TLI.getPointerTy()));
1704 SDOperand Size = Tmp2.getOperand(1);
1705 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1706 Chain = SP.getValue(1);
1707 unsigned Align = cast<ConstantSDNode>(Tmp3)->getValue();
1708 unsigned StackAlign =
1709 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1710 if (Align > StackAlign)
1711 SP = DAG.getNode(ISD::AND, VT, SP,
1712 DAG.getConstant(-(uint64_t)Align, VT));
1713 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1714 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1717 DAG.getCALLSEQ_END(Chain,
1718 DAG.getConstant(0, TLI.getPointerTy()),
1719 DAG.getConstant(0, TLI.getPointerTy()),
1722 Tmp1 = LegalizeOp(Tmp1);
1723 Tmp2 = LegalizeOp(Tmp2);
1726 case TargetLowering::Custom:
1727 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1729 Tmp1 = LegalizeOp(Tmp3);
1730 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1733 case TargetLowering::Legal:
1736 // Since this op produce two values, make sure to remember that we
1737 // legalized both of them.
1738 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1739 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1740 return Op.ResNo ? Tmp2 : Tmp1;
1742 case ISD::INLINEASM: {
1743 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1744 bool Changed = false;
1745 // Legalize all of the operands of the inline asm, in case they are nodes
1746 // that need to be expanded or something. Note we skip the asm string and
1747 // all of the TargetConstant flags.
1748 SDOperand Op = LegalizeOp(Ops[0]);
1749 Changed = Op != Ops[0];
1752 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1753 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1754 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1755 for (++i; NumVals; ++i, --NumVals) {
1756 SDOperand Op = LegalizeOp(Ops[i]);
1765 Op = LegalizeOp(Ops.back());
1766 Changed |= Op != Ops.back();
1771 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1773 // INLINE asm returns a chain and flag, make sure to add both to the map.
1774 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1775 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1776 return Result.getValue(Op.ResNo);
1779 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1780 // Ensure that libcalls are emitted before a branch.
1781 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1782 Tmp1 = LegalizeOp(Tmp1);
1783 LastCALLSEQ_END = DAG.getEntryNode();
1785 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1788 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1789 // Ensure that libcalls are emitted before a branch.
1790 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1791 Tmp1 = LegalizeOp(Tmp1);
1792 LastCALLSEQ_END = DAG.getEntryNode();
1794 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1795 default: assert(0 && "Indirect target must be legal type (pointer)!");
1797 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1800 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1803 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1804 // Ensure that libcalls are emitted before a branch.
1805 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1806 Tmp1 = LegalizeOp(Tmp1);
1807 LastCALLSEQ_END = DAG.getEntryNode();
1809 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1810 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1812 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1813 default: assert(0 && "This action is not supported yet!");
1814 case TargetLowering::Legal: break;
1815 case TargetLowering::Custom:
1816 Tmp1 = TLI.LowerOperation(Result, DAG);
1817 if (Tmp1.Val) Result = Tmp1;
1819 case TargetLowering::Expand: {
1820 SDOperand Chain = Result.getOperand(0);
1821 SDOperand Table = Result.getOperand(1);
1822 SDOperand Index = Result.getOperand(2);
1824 MVT::ValueType PTy = TLI.getPointerTy();
1825 MachineFunction &MF = DAG.getMachineFunction();
1826 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1827 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1828 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1831 switch (EntrySize) {
1832 default: assert(0 && "Size of jump table not supported yet."); break;
1833 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr,
1834 PseudoSourceValue::getJumpTable(), 0); break;
1835 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr,
1836 PseudoSourceValue::getJumpTable(), 0); break;
1840 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1841 // For PIC, the sequence is:
1842 // BRIND(load(Jumptable + index) + RelocBase)
1843 // RelocBase can be JumpTable, GOT or some sort of global base.
1844 if (PTy != MVT::i32)
1845 Addr = DAG.getNode(ISD::SIGN_EXTEND, PTy, Addr);
1846 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
1847 TLI.getPICJumpTableRelocBase(Table, DAG));
1849 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1854 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1855 // Ensure that libcalls are emitted before a return.
1856 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1857 Tmp1 = LegalizeOp(Tmp1);
1858 LastCALLSEQ_END = DAG.getEntryNode();
1860 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1861 case Expand: assert(0 && "It's impossible to expand bools");
1863 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1866 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1868 // The top bits of the promoted condition are not necessarily zero, ensure
1869 // that the value is properly zero extended.
1870 unsigned BitWidth = Tmp2.getValueSizeInBits();
1871 if (!DAG.MaskedValueIsZero(Tmp2,
1872 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
1873 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1878 // Basic block destination (Op#2) is always legal.
1879 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1881 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1882 default: assert(0 && "This action is not supported yet!");
1883 case TargetLowering::Legal: break;
1884 case TargetLowering::Custom:
1885 Tmp1 = TLI.LowerOperation(Result, DAG);
1886 if (Tmp1.Val) Result = Tmp1;
1888 case TargetLowering::Expand:
1889 // Expand brcond's setcc into its constituent parts and create a BR_CC
1891 if (Tmp2.getOpcode() == ISD::SETCC) {
1892 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1893 Tmp2.getOperand(0), Tmp2.getOperand(1),
1894 Node->getOperand(2));
1896 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1897 DAG.getCondCode(ISD::SETNE), Tmp2,
1898 DAG.getConstant(0, Tmp2.getValueType()),
1899 Node->getOperand(2));
1905 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1906 // Ensure that libcalls are emitted before a branch.
1907 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1908 Tmp1 = LegalizeOp(Tmp1);
1909 Tmp2 = Node->getOperand(2); // LHS
1910 Tmp3 = Node->getOperand(3); // RHS
1911 Tmp4 = Node->getOperand(1); // CC
1913 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1914 LastCALLSEQ_END = DAG.getEntryNode();
1916 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1917 // the LHS is a legal SETCC itself. In this case, we need to compare
1918 // the result against zero to select between true and false values.
1919 if (Tmp3.Val == 0) {
1920 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1921 Tmp4 = DAG.getCondCode(ISD::SETNE);
1924 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1925 Node->getOperand(4));
1927 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1928 default: assert(0 && "Unexpected action for BR_CC!");
1929 case TargetLowering::Legal: break;
1930 case TargetLowering::Custom:
1931 Tmp4 = TLI.LowerOperation(Result, DAG);
1932 if (Tmp4.Val) Result = Tmp4;
1937 LoadSDNode *LD = cast<LoadSDNode>(Node);
1938 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1939 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1941 ISD::LoadExtType ExtType = LD->getExtensionType();
1942 if (ExtType == ISD::NON_EXTLOAD) {
1943 MVT::ValueType VT = Node->getValueType(0);
1944 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1945 Tmp3 = Result.getValue(0);
1946 Tmp4 = Result.getValue(1);
1948 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1949 default: assert(0 && "This action is not supported yet!");
1950 case TargetLowering::Legal:
1951 // If this is an unaligned load and the target doesn't support it,
1953 if (!TLI.allowsUnalignedMemoryAccesses()) {
1954 unsigned ABIAlignment = TLI.getTargetData()->
1955 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
1956 if (LD->getAlignment() < ABIAlignment){
1957 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
1959 Tmp3 = Result.getOperand(0);
1960 Tmp4 = Result.getOperand(1);
1961 Tmp3 = LegalizeOp(Tmp3);
1962 Tmp4 = LegalizeOp(Tmp4);
1966 case TargetLowering::Custom:
1967 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1969 Tmp3 = LegalizeOp(Tmp1);
1970 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1973 case TargetLowering::Promote: {
1974 // Only promote a load of vector type to another.
1975 assert(MVT::isVector(VT) && "Cannot promote this load!");
1976 // Change base type to a different vector type.
1977 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1979 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1980 LD->getSrcValueOffset(),
1981 LD->isVolatile(), LD->getAlignment());
1982 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1983 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1987 // Since loads produce two values, make sure to remember that we
1988 // legalized both of them.
1989 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1990 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1991 return Op.ResNo ? Tmp4 : Tmp3;
1993 MVT::ValueType SrcVT = LD->getMemoryVT();
1994 unsigned SrcWidth = MVT::getSizeInBits(SrcVT);
1995 int SVOffset = LD->getSrcValueOffset();
1996 unsigned Alignment = LD->getAlignment();
1997 bool isVolatile = LD->isVolatile();
1999 if (SrcWidth != MVT::getStoreSizeInBits(SrcVT) &&
2000 // Some targets pretend to have an i1 loading operation, and actually
2001 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2002 // bits are guaranteed to be zero; it helps the optimizers understand
2003 // that these bits are zero. It is also useful for EXTLOAD, since it
2004 // tells the optimizers that those bits are undefined. It would be
2005 // nice to have an effective generic way of getting these benefits...
2006 // Until such a way is found, don't insist on promoting i1 here.
2007 (SrcVT != MVT::i1 ||
2008 TLI.getLoadXAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2009 // Promote to a byte-sized load if not loading an integral number of
2010 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2011 unsigned NewWidth = MVT::getStoreSizeInBits(SrcVT);
2012 MVT::ValueType NVT = MVT::getIntegerType(NewWidth);
2015 // The extra bits are guaranteed to be zero, since we stored them that
2016 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2018 ISD::LoadExtType NewExtType =
2019 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2021 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2022 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2023 NVT, isVolatile, Alignment);
2025 Ch = Result.getValue(1); // The chain.
2027 if (ExtType == ISD::SEXTLOAD)
2028 // Having the top bits zero doesn't help when sign extending.
2029 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2030 Result, DAG.getValueType(SrcVT));
2031 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2032 // All the top bits are guaranteed to be zero - inform the optimizers.
2033 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2034 DAG.getValueType(SrcVT));
2036 Tmp1 = LegalizeOp(Result);
2037 Tmp2 = LegalizeOp(Ch);
2038 } else if (SrcWidth & (SrcWidth - 1)) {
2039 // If not loading a power-of-2 number of bits, expand as two loads.
2040 assert(MVT::isExtendedVT(SrcVT) && !MVT::isVector(SrcVT) &&
2041 "Unsupported extload!");
2042 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2043 assert(RoundWidth < SrcWidth);
2044 unsigned ExtraWidth = SrcWidth - RoundWidth;
2045 assert(ExtraWidth < RoundWidth);
2046 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2047 "Load size not an integral number of bytes!");
2048 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2049 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2050 SDOperand Lo, Hi, Ch;
2051 unsigned IncrementSize;
2053 if (TLI.isLittleEndian()) {
2054 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2055 // Load the bottom RoundWidth bits.
2056 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2057 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2060 // Load the remaining ExtraWidth bits.
2061 IncrementSize = RoundWidth / 8;
2062 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2063 DAG.getIntPtrConstant(IncrementSize));
2064 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2065 LD->getSrcValue(), SVOffset + IncrementSize,
2066 ExtraVT, isVolatile,
2067 MinAlign(Alignment, IncrementSize));
2069 // Build a factor node to remember that this load is independent of the
2071 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2074 // Move the top bits to the right place.
2075 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2076 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2078 // Join the hi and lo parts.
2079 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2081 // Big endian - avoid unaligned loads.
2082 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2083 // Load the top RoundWidth bits.
2084 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2085 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2088 // Load the remaining ExtraWidth bits.
2089 IncrementSize = RoundWidth / 8;
2090 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2091 DAG.getIntPtrConstant(IncrementSize));
2092 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2093 LD->getSrcValue(), SVOffset + IncrementSize,
2094 ExtraVT, isVolatile,
2095 MinAlign(Alignment, IncrementSize));
2097 // Build a factor node to remember that this load is independent of the
2099 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2102 // Move the top bits to the right place.
2103 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2104 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2106 // Join the hi and lo parts.
2107 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2110 Tmp1 = LegalizeOp(Result);
2111 Tmp2 = LegalizeOp(Ch);
2113 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
2114 default: assert(0 && "This action is not supported yet!");
2115 case TargetLowering::Custom:
2118 case TargetLowering::Legal:
2119 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2120 Tmp1 = Result.getValue(0);
2121 Tmp2 = Result.getValue(1);
2124 Tmp3 = TLI.LowerOperation(Result, DAG);
2126 Tmp1 = LegalizeOp(Tmp3);
2127 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2130 // If this is an unaligned load and the target doesn't support it,
2132 if (!TLI.allowsUnalignedMemoryAccesses()) {
2133 unsigned ABIAlignment = TLI.getTargetData()->
2134 getABITypeAlignment(MVT::getTypeForValueType(LD->getMemoryVT()));
2135 if (LD->getAlignment() < ABIAlignment){
2136 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.Val), DAG,
2138 Tmp1 = Result.getOperand(0);
2139 Tmp2 = Result.getOperand(1);
2140 Tmp1 = LegalizeOp(Tmp1);
2141 Tmp2 = LegalizeOp(Tmp2);
2146 case TargetLowering::Expand:
2147 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2148 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2149 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2150 LD->getSrcValueOffset(),
2151 LD->isVolatile(), LD->getAlignment());
2152 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2153 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2154 Tmp2 = LegalizeOp(Load.getValue(1));
2157 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2158 // Turn the unsupported load into an EXTLOAD followed by an explicit
2159 // zero/sign extend inreg.
2160 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2161 Tmp1, Tmp2, LD->getSrcValue(),
2162 LD->getSrcValueOffset(), SrcVT,
2163 LD->isVolatile(), LD->getAlignment());
2165 if (ExtType == ISD::SEXTLOAD)
2166 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2167 Result, DAG.getValueType(SrcVT));
2169 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2170 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2171 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2176 // Since loads produce two values, make sure to remember that we legalized
2178 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2179 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2180 return Op.ResNo ? Tmp2 : Tmp1;
2183 case ISD::EXTRACT_ELEMENT: {
2184 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
2185 switch (getTypeAction(OpTy)) {
2186 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2188 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
2190 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2191 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
2192 TLI.getShiftAmountTy()));
2193 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2196 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2197 Node->getOperand(0));
2201 // Get both the low and high parts.
2202 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2203 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
2204 Result = Tmp2; // 1 -> Hi
2206 Result = Tmp1; // 0 -> Lo
2212 case ISD::CopyToReg:
2213 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2215 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2216 "Register type must be legal!");
2217 // Legalize the incoming value (must be a legal type).
2218 Tmp2 = LegalizeOp(Node->getOperand(2));
2219 if (Node->getNumValues() == 1) {
2220 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2222 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2223 if (Node->getNumOperands() == 4) {
2224 Tmp3 = LegalizeOp(Node->getOperand(3));
2225 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2228 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2231 // Since this produces two values, make sure to remember that we legalized
2233 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2234 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2240 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2242 // Ensure that libcalls are emitted before a return.
2243 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2244 Tmp1 = LegalizeOp(Tmp1);
2245 LastCALLSEQ_END = DAG.getEntryNode();
2247 switch (Node->getNumOperands()) {
2249 Tmp2 = Node->getOperand(1);
2250 Tmp3 = Node->getOperand(2); // Signness
2251 switch (getTypeAction(Tmp2.getValueType())) {
2253 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2256 if (!MVT::isVector(Tmp2.getValueType())) {
2258 ExpandOp(Tmp2, Lo, Hi);
2260 // Big endian systems want the hi reg first.
2261 if (TLI.isBigEndian())
2265 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2267 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2268 Result = LegalizeOp(Result);
2270 SDNode *InVal = Tmp2.Val;
2271 int InIx = Tmp2.ResNo;
2272 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
2273 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
2275 // Figure out if there is a simple type corresponding to this Vector
2276 // type. If so, convert to the vector type.
2277 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2278 if (TLI.isTypeLegal(TVT)) {
2279 // Turn this into a return of the vector type.
2280 Tmp2 = LegalizeOp(Tmp2);
2281 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2282 } else if (NumElems == 1) {
2283 // Turn this into a return of the scalar type.
2284 Tmp2 = ScalarizeVectorOp(Tmp2);
2285 Tmp2 = LegalizeOp(Tmp2);
2286 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2288 // FIXME: Returns of gcc generic vectors smaller than a legal type
2289 // should be returned in integer registers!
2291 // The scalarized value type may not be legal, e.g. it might require
2292 // promotion or expansion. Relegalize the return.
2293 Result = LegalizeOp(Result);
2295 // FIXME: Returns of gcc generic vectors larger than a legal vector
2296 // type should be returned by reference!
2298 SplitVectorOp(Tmp2, Lo, Hi);
2299 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2300 Result = LegalizeOp(Result);
2305 Tmp2 = PromoteOp(Node->getOperand(1));
2306 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2307 Result = LegalizeOp(Result);
2312 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2314 default: { // ret <values>
2315 SmallVector<SDOperand, 8> NewValues;
2316 NewValues.push_back(Tmp1);
2317 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2318 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2320 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2321 NewValues.push_back(Node->getOperand(i+1));
2325 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
2326 "FIXME: TODO: implement returning non-legal vector types!");
2327 ExpandOp(Node->getOperand(i), Lo, Hi);
2328 NewValues.push_back(Lo);
2329 NewValues.push_back(Node->getOperand(i+1));
2331 NewValues.push_back(Hi);
2332 NewValues.push_back(Node->getOperand(i+1));
2337 assert(0 && "Can't promote multiple return value yet!");
2340 if (NewValues.size() == Node->getNumOperands())
2341 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2343 Result = DAG.getNode(ISD::RET, MVT::Other,
2344 &NewValues[0], NewValues.size());
2349 if (Result.getOpcode() == ISD::RET) {
2350 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2351 default: assert(0 && "This action is not supported yet!");
2352 case TargetLowering::Legal: break;
2353 case TargetLowering::Custom:
2354 Tmp1 = TLI.LowerOperation(Result, DAG);
2355 if (Tmp1.Val) Result = Tmp1;
2361 StoreSDNode *ST = cast<StoreSDNode>(Node);
2362 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2363 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2364 int SVOffset = ST->getSrcValueOffset();
2365 unsigned Alignment = ST->getAlignment();
2366 bool isVolatile = ST->isVolatile();
2368 if (!ST->isTruncatingStore()) {
2369 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2370 // FIXME: We shouldn't do this for TargetConstantFP's.
2371 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2372 // to phase ordering between legalized code and the dag combiner. This
2373 // probably means that we need to integrate dag combiner and legalizer
2375 // We generally can't do this one for long doubles.
2376 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2377 if (CFP->getValueType(0) == MVT::f32 &&
2378 getTypeAction(MVT::i32) == Legal) {
2379 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2380 convertToAPInt().zextOrTrunc(32),
2382 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2383 SVOffset, isVolatile, Alignment);
2385 } else if (CFP->getValueType(0) == MVT::f64) {
2386 // If this target supports 64-bit registers, do a single 64-bit store.
2387 if (getTypeAction(MVT::i64) == Legal) {
2388 Tmp3 = DAG.getConstant(CFP->getValueAPF().convertToAPInt().
2389 zextOrTrunc(64), MVT::i64);
2390 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2391 SVOffset, isVolatile, Alignment);
2393 } else if (getTypeAction(MVT::i32) == Legal) {
2394 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2395 // stores. If the target supports neither 32- nor 64-bits, this
2396 // xform is certainly not worth it.
2397 const APInt &IntVal =CFP->getValueAPF().convertToAPInt();
2398 SDOperand Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2399 SDOperand Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2400 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2402 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2403 SVOffset, isVolatile, Alignment);
2404 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2405 DAG.getIntPtrConstant(4));
2406 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2407 isVolatile, MinAlign(Alignment, 4U));
2409 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2415 switch (getTypeAction(ST->getMemoryVT())) {
2417 Tmp3 = LegalizeOp(ST->getValue());
2418 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2421 MVT::ValueType VT = Tmp3.getValueType();
2422 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2423 default: assert(0 && "This action is not supported yet!");
2424 case TargetLowering::Legal:
2425 // If this is an unaligned store and the target doesn't support it,
2427 if (!TLI.allowsUnalignedMemoryAccesses()) {
2428 unsigned ABIAlignment = TLI.getTargetData()->
2429 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2430 if (ST->getAlignment() < ABIAlignment)
2431 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2435 case TargetLowering::Custom:
2436 Tmp1 = TLI.LowerOperation(Result, DAG);
2437 if (Tmp1.Val) Result = Tmp1;
2439 case TargetLowering::Promote:
2440 assert(MVT::isVector(VT) && "Unknown legal promote case!");
2441 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2442 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2443 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2444 ST->getSrcValue(), SVOffset, isVolatile,
2451 // Truncate the value and store the result.
2452 Tmp3 = PromoteOp(ST->getValue());
2453 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2454 SVOffset, ST->getMemoryVT(),
2455 isVolatile, Alignment);
2459 unsigned IncrementSize = 0;
2462 // If this is a vector type, then we have to calculate the increment as
2463 // the product of the element size in bytes, and the number of elements
2464 // in the high half of the vector.
2465 if (MVT::isVector(ST->getValue().getValueType())) {
2466 SDNode *InVal = ST->getValue().Val;
2467 int InIx = ST->getValue().ResNo;
2468 MVT::ValueType InVT = InVal->getValueType(InIx);
2469 unsigned NumElems = MVT::getVectorNumElements(InVT);
2470 MVT::ValueType EVT = MVT::getVectorElementType(InVT);
2472 // Figure out if there is a simple type corresponding to this Vector
2473 // type. If so, convert to the vector type.
2474 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2475 if (TLI.isTypeLegal(TVT)) {
2476 // Turn this into a normal store of the vector type.
2477 Tmp3 = LegalizeOp(ST->getValue());
2478 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2479 SVOffset, isVolatile, Alignment);
2480 Result = LegalizeOp(Result);
2482 } else if (NumElems == 1) {
2483 // Turn this into a normal store of the scalar type.
2484 Tmp3 = ScalarizeVectorOp(ST->getValue());
2485 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2486 SVOffset, isVolatile, Alignment);
2487 // The scalarized value type may not be legal, e.g. it might require
2488 // promotion or expansion. Relegalize the scalar store.
2489 Result = LegalizeOp(Result);
2492 SplitVectorOp(ST->getValue(), Lo, Hi);
2493 IncrementSize = MVT::getVectorNumElements(Lo.Val->getValueType(0)) *
2494 MVT::getSizeInBits(EVT)/8;
2497 ExpandOp(ST->getValue(), Lo, Hi);
2498 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
2500 if (TLI.isBigEndian())
2504 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2505 SVOffset, isVolatile, Alignment);
2507 if (Hi.Val == NULL) {
2508 // Must be int <-> float one-to-one expansion.
2513 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2514 DAG.getIntPtrConstant(IncrementSize));
2515 assert(isTypeLegal(Tmp2.getValueType()) &&
2516 "Pointers must be legal!");
2517 SVOffset += IncrementSize;
2518 Alignment = MinAlign(Alignment, IncrementSize);
2519 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2520 SVOffset, isVolatile, Alignment);
2521 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2525 switch (getTypeAction(ST->getValue().getValueType())) {
2527 Tmp3 = LegalizeOp(ST->getValue());
2530 // We can promote the value, the truncstore will still take care of it.
2531 Tmp3 = PromoteOp(ST->getValue());
2534 // Just store the low part. This may become a non-trunc store, so make
2535 // sure to use getTruncStore, not UpdateNodeOperands below.
2536 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2537 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2538 SVOffset, MVT::i8, isVolatile, Alignment);
2541 MVT::ValueType StVT = ST->getMemoryVT();
2542 unsigned StWidth = MVT::getSizeInBits(StVT);
2544 if (StWidth != MVT::getStoreSizeInBits(StVT)) {
2545 // Promote to a byte-sized store with upper bits zero if not
2546 // storing an integral number of bytes. For example, promote
2547 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2548 MVT::ValueType NVT = MVT::getIntegerType(MVT::getStoreSizeInBits(StVT));
2549 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2550 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2551 SVOffset, NVT, isVolatile, Alignment);
2552 } else if (StWidth & (StWidth - 1)) {
2553 // If not storing a power-of-2 number of bits, expand as two stores.
2554 assert(MVT::isExtendedVT(StVT) && !MVT::isVector(StVT) &&
2555 "Unsupported truncstore!");
2556 unsigned RoundWidth = 1 << Log2_32(StWidth);
2557 assert(RoundWidth < StWidth);
2558 unsigned ExtraWidth = StWidth - RoundWidth;
2559 assert(ExtraWidth < RoundWidth);
2560 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2561 "Store size not an integral number of bytes!");
2562 MVT::ValueType RoundVT = MVT::getIntegerType(RoundWidth);
2563 MVT::ValueType ExtraVT = MVT::getIntegerType(ExtraWidth);
2565 unsigned IncrementSize;
2567 if (TLI.isLittleEndian()) {
2568 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2569 // Store the bottom RoundWidth bits.
2570 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2572 isVolatile, Alignment);
2574 // Store the remaining ExtraWidth bits.
2575 IncrementSize = RoundWidth / 8;
2576 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2577 DAG.getIntPtrConstant(IncrementSize));
2578 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2579 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2580 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2581 SVOffset + IncrementSize, ExtraVT, isVolatile,
2582 MinAlign(Alignment, IncrementSize));
2584 // Big endian - avoid unaligned stores.
2585 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2586 // Store the top RoundWidth bits.
2587 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2588 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2589 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2590 RoundVT, isVolatile, Alignment);
2592 // Store the remaining ExtraWidth bits.
2593 IncrementSize = RoundWidth / 8;
2594 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2595 DAG.getIntPtrConstant(IncrementSize));
2596 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2597 SVOffset + IncrementSize, ExtraVT, isVolatile,
2598 MinAlign(Alignment, IncrementSize));
2601 // The order of the stores doesn't matter.
2602 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2604 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2605 Tmp2 != ST->getBasePtr())
2606 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2609 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2610 default: assert(0 && "This action is not supported yet!");
2611 case TargetLowering::Legal:
2612 // If this is an unaligned store and the target doesn't support it,
2614 if (!TLI.allowsUnalignedMemoryAccesses()) {
2615 unsigned ABIAlignment = TLI.getTargetData()->
2616 getABITypeAlignment(MVT::getTypeForValueType(ST->getMemoryVT()));
2617 if (ST->getAlignment() < ABIAlignment)
2618 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.Val), DAG,
2622 case TargetLowering::Custom:
2623 Result = TLI.LowerOperation(Result, DAG);
2626 // TRUNCSTORE:i16 i32 -> STORE i16
2627 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2628 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2629 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2630 isVolatile, Alignment);
2638 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2639 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2641 case ISD::STACKSAVE:
2642 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2643 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2644 Tmp1 = Result.getValue(0);
2645 Tmp2 = Result.getValue(1);
2647 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2648 default: assert(0 && "This action is not supported yet!");
2649 case TargetLowering::Legal: break;
2650 case TargetLowering::Custom:
2651 Tmp3 = TLI.LowerOperation(Result, DAG);
2653 Tmp1 = LegalizeOp(Tmp3);
2654 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2657 case TargetLowering::Expand:
2658 // Expand to CopyFromReg if the target set
2659 // StackPointerRegisterToSaveRestore.
2660 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2661 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2662 Node->getValueType(0));
2663 Tmp2 = Tmp1.getValue(1);
2665 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2666 Tmp2 = Node->getOperand(0);
2671 // Since stacksave produce two values, make sure to remember that we
2672 // legalized both of them.
2673 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2674 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2675 return Op.ResNo ? Tmp2 : Tmp1;
2677 case ISD::STACKRESTORE:
2678 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2679 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2680 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2682 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2683 default: assert(0 && "This action is not supported yet!");
2684 case TargetLowering::Legal: break;
2685 case TargetLowering::Custom:
2686 Tmp1 = TLI.LowerOperation(Result, DAG);
2687 if (Tmp1.Val) Result = Tmp1;
2689 case TargetLowering::Expand:
2690 // Expand to CopyToReg if the target set
2691 // StackPointerRegisterToSaveRestore.
2692 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2693 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2701 case ISD::READCYCLECOUNTER:
2702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2703 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2704 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2705 Node->getValueType(0))) {
2706 default: assert(0 && "This action is not supported yet!");
2707 case TargetLowering::Legal:
2708 Tmp1 = Result.getValue(0);
2709 Tmp2 = Result.getValue(1);
2711 case TargetLowering::Custom:
2712 Result = TLI.LowerOperation(Result, DAG);
2713 Tmp1 = LegalizeOp(Result.getValue(0));
2714 Tmp2 = LegalizeOp(Result.getValue(1));
2718 // Since rdcc produce two values, make sure to remember that we legalized
2720 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2721 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2725 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2726 case Expand: assert(0 && "It's impossible to expand bools");
2728 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2731 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2732 // Make sure the condition is either zero or one.
2733 unsigned BitWidth = Tmp1.getValueSizeInBits();
2734 if (!DAG.MaskedValueIsZero(Tmp1,
2735 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2736 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2740 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2741 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2743 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2745 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2746 default: assert(0 && "This action is not supported yet!");
2747 case TargetLowering::Legal: break;
2748 case TargetLowering::Custom: {
2749 Tmp1 = TLI.LowerOperation(Result, DAG);
2750 if (Tmp1.Val) Result = Tmp1;
2753 case TargetLowering::Expand:
2754 if (Tmp1.getOpcode() == ISD::SETCC) {
2755 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2757 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2759 Result = DAG.getSelectCC(Tmp1,
2760 DAG.getConstant(0, Tmp1.getValueType()),
2761 Tmp2, Tmp3, ISD::SETNE);
2764 case TargetLowering::Promote: {
2765 MVT::ValueType NVT =
2766 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2767 unsigned ExtOp, TruncOp;
2768 if (MVT::isVector(Tmp2.getValueType())) {
2769 ExtOp = ISD::BIT_CONVERT;
2770 TruncOp = ISD::BIT_CONVERT;
2771 } else if (MVT::isInteger(Tmp2.getValueType())) {
2772 ExtOp = ISD::ANY_EXTEND;
2773 TruncOp = ISD::TRUNCATE;
2775 ExtOp = ISD::FP_EXTEND;
2776 TruncOp = ISD::FP_ROUND;
2778 // Promote each of the values to the new type.
2779 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2780 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2781 // Perform the larger operation, then round down.
2782 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2783 if (TruncOp != ISD::FP_ROUND)
2784 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2786 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
2787 DAG.getIntPtrConstant(0));
2792 case ISD::SELECT_CC: {
2793 Tmp1 = Node->getOperand(0); // LHS
2794 Tmp2 = Node->getOperand(1); // RHS
2795 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2796 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2797 SDOperand CC = Node->getOperand(4);
2799 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2801 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2802 // the LHS is a legal SETCC itself. In this case, we need to compare
2803 // the result against zero to select between true and false values.
2804 if (Tmp2.Val == 0) {
2805 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2806 CC = DAG.getCondCode(ISD::SETNE);
2808 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2810 // Everything is legal, see if we should expand this op or something.
2811 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2812 default: assert(0 && "This action is not supported yet!");
2813 case TargetLowering::Legal: break;
2814 case TargetLowering::Custom:
2815 Tmp1 = TLI.LowerOperation(Result, DAG);
2816 if (Tmp1.Val) Result = Tmp1;
2822 Tmp1 = Node->getOperand(0);
2823 Tmp2 = Node->getOperand(1);
2824 Tmp3 = Node->getOperand(2);
2825 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2827 // If we had to Expand the SetCC operands into a SELECT node, then it may
2828 // not always be possible to return a true LHS & RHS. In this case, just
2829 // return the value we legalized, returned in the LHS
2830 if (Tmp2.Val == 0) {
2835 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2836 default: assert(0 && "Cannot handle this action for SETCC yet!");
2837 case TargetLowering::Custom:
2840 case TargetLowering::Legal:
2841 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2843 Tmp4 = TLI.LowerOperation(Result, DAG);
2844 if (Tmp4.Val) Result = Tmp4;
2847 case TargetLowering::Promote: {
2848 // First step, figure out the appropriate operation to use.
2849 // Allow SETCC to not be supported for all legal data types
2850 // Mostly this targets FP
2851 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2852 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2854 // Scan for the appropriate larger type to use.
2856 NewInTy = (MVT::ValueType)(NewInTy+1);
2858 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2859 "Fell off of the edge of the integer world");
2860 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2861 "Fell off of the edge of the floating point world");
2863 // If the target supports SETCC of this type, use it.
2864 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2867 if (MVT::isInteger(NewInTy))
2868 assert(0 && "Cannot promote Legal Integer SETCC yet");
2870 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2871 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2873 Tmp1 = LegalizeOp(Tmp1);
2874 Tmp2 = LegalizeOp(Tmp2);
2875 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2876 Result = LegalizeOp(Result);
2879 case TargetLowering::Expand:
2880 // Expand a setcc node into a select_cc of the same condition, lhs, and
2881 // rhs that selects between const 1 (true) and const 0 (false).
2882 MVT::ValueType VT = Node->getValueType(0);
2883 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2884 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2890 case ISD::SHL_PARTS:
2891 case ISD::SRA_PARTS:
2892 case ISD::SRL_PARTS: {
2893 SmallVector<SDOperand, 8> Ops;
2894 bool Changed = false;
2895 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2896 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2897 Changed |= Ops.back() != Node->getOperand(i);
2900 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2902 switch (TLI.getOperationAction(Node->getOpcode(),
2903 Node->getValueType(0))) {
2904 default: assert(0 && "This action is not supported yet!");
2905 case TargetLowering::Legal: break;
2906 case TargetLowering::Custom:
2907 Tmp1 = TLI.LowerOperation(Result, DAG);
2909 SDOperand Tmp2, RetVal(0, 0);
2910 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2911 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2912 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2916 assert(RetVal.Val && "Illegal result number");
2922 // Since these produce multiple values, make sure to remember that we
2923 // legalized all of them.
2924 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2925 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2926 return Result.getValue(Op.ResNo);
2948 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2949 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2950 case Expand: assert(0 && "Not possible");
2952 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2955 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2959 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2961 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2962 default: assert(0 && "BinOp legalize operation not supported");
2963 case TargetLowering::Legal: break;
2964 case TargetLowering::Custom:
2965 Tmp1 = TLI.LowerOperation(Result, DAG);
2966 if (Tmp1.Val) Result = Tmp1;
2968 case TargetLowering::Expand: {
2969 MVT::ValueType VT = Op.getValueType();
2971 // See if multiply or divide can be lowered using two-result operations.
2972 SDVTList VTs = DAG.getVTList(VT, VT);
2973 if (Node->getOpcode() == ISD::MUL) {
2974 // We just need the low half of the multiply; try both the signed
2975 // and unsigned forms. If the target supports both SMUL_LOHI and
2976 // UMUL_LOHI, form a preference by checking which forms of plain
2977 // MULH it supports.
2978 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
2979 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
2980 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
2981 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
2982 unsigned OpToUse = 0;
2983 if (HasSMUL_LOHI && !HasMULHS) {
2984 OpToUse = ISD::SMUL_LOHI;
2985 } else if (HasUMUL_LOHI && !HasMULHU) {
2986 OpToUse = ISD::UMUL_LOHI;
2987 } else if (HasSMUL_LOHI) {
2988 OpToUse = ISD::SMUL_LOHI;
2989 } else if (HasUMUL_LOHI) {
2990 OpToUse = ISD::UMUL_LOHI;
2993 Result = SDOperand(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).Val, 0);
2997 if (Node->getOpcode() == ISD::MULHS &&
2998 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
2999 Result = SDOperand(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3002 if (Node->getOpcode() == ISD::MULHU &&
3003 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3004 Result = SDOperand(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).Val, 1);
3007 if (Node->getOpcode() == ISD::SDIV &&
3008 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3009 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3012 if (Node->getOpcode() == ISD::UDIV &&
3013 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3014 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 0);
3018 // Check to see if we have a libcall for this operator.
3019 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3020 bool isSigned = false;
3021 switch (Node->getOpcode()) {
3024 if (VT == MVT::i32) {
3025 LC = Node->getOpcode() == ISD::UDIV
3026 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3027 isSigned = Node->getOpcode() == ISD::SDIV;
3031 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3032 RTLIB::POW_PPCF128);
3036 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3038 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3042 assert(MVT::isVector(Node->getValueType(0)) &&
3043 "Cannot expand this binary operator!");
3044 // Expand the operation into a bunch of nasty scalar code.
3045 Result = LegalizeOp(UnrollVectorOp(Op));
3048 case TargetLowering::Promote: {
3049 switch (Node->getOpcode()) {
3050 default: assert(0 && "Do not know how to promote this BinOp!");
3054 MVT::ValueType OVT = Node->getValueType(0);
3055 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3056 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
3057 // Bit convert each of the values to the new type.
3058 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3059 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3060 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3061 // Bit convert the result back the original type.
3062 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3070 case ISD::SMUL_LOHI:
3071 case ISD::UMUL_LOHI:
3074 // These nodes will only be produced by target-specific lowering, so
3075 // they shouldn't be here if they aren't legal.
3076 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3077 "This must be legal!");
3079 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3080 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3081 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3084 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3085 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3086 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3087 case Expand: assert(0 && "Not possible");
3089 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3092 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3096 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3098 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3099 default: assert(0 && "Operation not supported");
3100 case TargetLowering::Custom:
3101 Tmp1 = TLI.LowerOperation(Result, DAG);
3102 if (Tmp1.Val) Result = Tmp1;
3104 case TargetLowering::Legal: break;
3105 case TargetLowering::Expand: {
3106 // If this target supports fabs/fneg natively and select is cheap,
3107 // do this efficiently.
3108 if (!TLI.isSelectExpensive() &&
3109 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3110 TargetLowering::Legal &&
3111 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3112 TargetLowering::Legal) {
3113 // Get the sign bit of the RHS.
3114 MVT::ValueType IVT =
3115 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3116 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3117 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3118 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3119 // Get the absolute value of the result.
3120 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3121 // Select between the nabs and abs value based on the sign bit of
3123 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3124 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3127 Result = LegalizeOp(Result);
3131 // Otherwise, do bitwise ops!
3132 MVT::ValueType NVT =
3133 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3134 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3135 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3136 Result = LegalizeOp(Result);
3144 Tmp1 = LegalizeOp(Node->getOperand(0));
3145 Tmp2 = LegalizeOp(Node->getOperand(1));
3146 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3147 // Since this produces two values, make sure to remember that we legalized
3149 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3150 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3155 Tmp1 = LegalizeOp(Node->getOperand(0));
3156 Tmp2 = LegalizeOp(Node->getOperand(1));
3157 Tmp3 = LegalizeOp(Node->getOperand(2));
3158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3159 // Since this produces two values, make sure to remember that we legalized
3161 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
3162 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
3165 case ISD::BUILD_PAIR: {
3166 MVT::ValueType PairTy = Node->getValueType(0);
3167 // TODO: handle the case where the Lo and Hi operands are not of legal type
3168 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3169 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3170 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3171 case TargetLowering::Promote:
3172 case TargetLowering::Custom:
3173 assert(0 && "Cannot promote/custom this yet!");
3174 case TargetLowering::Legal:
3175 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3176 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3178 case TargetLowering::Expand:
3179 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3180 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3181 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3182 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
3183 TLI.getShiftAmountTy()));
3184 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3193 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3194 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3196 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3197 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3198 case TargetLowering::Custom:
3201 case TargetLowering::Legal:
3202 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3204 Tmp1 = TLI.LowerOperation(Result, DAG);
3205 if (Tmp1.Val) Result = Tmp1;
3208 case TargetLowering::Expand: {
3209 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3210 bool isSigned = DivOpc == ISD::SDIV;
3211 MVT::ValueType VT = Node->getValueType(0);
3213 // See if remainder can be lowered using two-result operations.
3214 SDVTList VTs = DAG.getVTList(VT, VT);
3215 if (Node->getOpcode() == ISD::SREM &&
3216 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3217 Result = SDOperand(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3220 if (Node->getOpcode() == ISD::UREM &&
3221 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3222 Result = SDOperand(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).Val, 1);
3226 if (MVT::isInteger(VT)) {
3227 if (TLI.getOperationAction(DivOpc, VT) ==
3228 TargetLowering::Legal) {
3230 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3231 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3232 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3233 } else if (MVT::isVector(VT)) {
3234 Result = LegalizeOp(UnrollVectorOp(Op));
3236 assert(VT == MVT::i32 &&
3237 "Cannot expand this binary operator!");
3238 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3239 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3241 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3244 assert(MVT::isFloatingPoint(VT) &&
3245 "remainder op must have integer or floating-point type");
3246 if (MVT::isVector(VT)) {
3247 Result = LegalizeOp(UnrollVectorOp(Op));
3249 // Floating point mod -> fmod libcall.
3250 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3251 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3253 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3261 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3262 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3264 MVT::ValueType VT = Node->getValueType(0);
3265 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3266 default: assert(0 && "This action is not supported yet!");
3267 case TargetLowering::Custom:
3270 case TargetLowering::Legal:
3271 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3272 Result = Result.getValue(0);
3273 Tmp1 = Result.getValue(1);
3276 Tmp2 = TLI.LowerOperation(Result, DAG);
3278 Result = LegalizeOp(Tmp2);
3279 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3283 case TargetLowering::Expand: {
3284 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3285 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3286 // Increment the pointer, VAList, to the next vaarg
3287 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3288 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3289 TLI.getPointerTy()));
3290 // Store the incremented VAList to the legalized pointer
3291 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3292 // Load the actual argument out of the pointer VAList
3293 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3294 Tmp1 = LegalizeOp(Result.getValue(1));
3295 Result = LegalizeOp(Result);
3299 // Since VAARG produces two values, make sure to remember that we
3300 // legalized both of them.
3301 AddLegalizedOperand(SDOperand(Node, 0), Result);
3302 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3303 return Op.ResNo ? Tmp1 : Result;
3307 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3308 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3309 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3311 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3312 default: assert(0 && "This action is not supported yet!");
3313 case TargetLowering::Custom:
3316 case TargetLowering::Legal:
3317 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3318 Node->getOperand(3), Node->getOperand(4));
3320 Tmp1 = TLI.LowerOperation(Result, DAG);
3321 if (Tmp1.Val) Result = Tmp1;
3324 case TargetLowering::Expand:
3325 // This defaults to loading a pointer from the input and storing it to the
3326 // output, returning the chain.
3327 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3328 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3329 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3330 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3336 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3337 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3339 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3340 default: assert(0 && "This action is not supported yet!");
3341 case TargetLowering::Custom:
3344 case TargetLowering::Legal:
3345 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3347 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3348 if (Tmp1.Val) Result = Tmp1;
3351 case TargetLowering::Expand:
3352 Result = Tmp1; // Default to a no-op, return the chain
3358 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3359 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3363 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3364 default: assert(0 && "This action is not supported yet!");
3365 case TargetLowering::Legal: break;
3366 case TargetLowering::Custom:
3367 Tmp1 = TLI.LowerOperation(Result, DAG);
3368 if (Tmp1.Val) Result = Tmp1;
3375 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3376 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3377 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3378 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3380 assert(0 && "ROTL/ROTR legalize operation not supported");
3382 case TargetLowering::Legal:
3384 case TargetLowering::Custom:
3385 Tmp1 = TLI.LowerOperation(Result, DAG);
3386 if (Tmp1.Val) Result = Tmp1;
3388 case TargetLowering::Promote:
3389 assert(0 && "Do not know how to promote ROTL/ROTR");
3391 case TargetLowering::Expand:
3392 assert(0 && "Do not know how to expand ROTL/ROTR");
3398 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3399 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3400 case TargetLowering::Custom:
3401 assert(0 && "Cannot custom legalize this yet!");
3402 case TargetLowering::Legal:
3403 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3405 case TargetLowering::Promote: {
3406 MVT::ValueType OVT = Tmp1.getValueType();
3407 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3408 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
3410 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3411 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3412 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3413 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3416 case TargetLowering::Expand:
3417 Result = ExpandBSWAP(Tmp1);
3425 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3426 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3427 case TargetLowering::Custom:
3428 case TargetLowering::Legal:
3429 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3430 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3431 TargetLowering::Custom) {
3432 Tmp1 = TLI.LowerOperation(Result, DAG);
3438 case TargetLowering::Promote: {
3439 MVT::ValueType OVT = Tmp1.getValueType();
3440 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3442 // Zero extend the argument.
3443 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3444 // Perform the larger operation, then subtract if needed.
3445 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3446 switch (Node->getOpcode()) {
3451 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3452 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3453 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3455 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3456 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
3459 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3460 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3461 DAG.getConstant(MVT::getSizeInBits(NVT) -
3462 MVT::getSizeInBits(OVT), NVT));
3467 case TargetLowering::Expand:
3468 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3479 Tmp1 = LegalizeOp(Node->getOperand(0));
3480 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3481 case TargetLowering::Promote:
3482 case TargetLowering::Custom:
3485 case TargetLowering::Legal:
3486 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3488 Tmp1 = TLI.LowerOperation(Result, DAG);
3489 if (Tmp1.Val) Result = Tmp1;
3492 case TargetLowering::Expand:
3493 switch (Node->getOpcode()) {
3494 default: assert(0 && "Unreachable!");
3496 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3497 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3498 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3501 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3502 MVT::ValueType VT = Node->getValueType(0);
3503 Tmp2 = DAG.getConstantFP(0.0, VT);
3504 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3506 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3507 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3513 MVT::ValueType VT = Node->getValueType(0);
3515 // Expand unsupported unary vector operators by unrolling them.
3516 if (MVT::isVector(VT)) {
3517 Result = LegalizeOp(UnrollVectorOp(Op));
3521 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3522 switch(Node->getOpcode()) {
3524 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3525 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3528 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3529 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3532 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3533 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3535 default: assert(0 && "Unreachable!");
3538 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3546 MVT::ValueType VT = Node->getValueType(0);
3548 // Expand unsupported unary vector operators by unrolling them.
3549 if (MVT::isVector(VT)) {
3550 Result = LegalizeOp(UnrollVectorOp(Op));
3554 // We always lower FPOWI into a libcall. No target support for it yet.
3555 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3556 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3558 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3561 case ISD::BIT_CONVERT:
3562 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3563 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3564 Node->getValueType(0));
3565 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
3566 // The input has to be a vector type, we have to either scalarize it, pack
3567 // it, or convert it based on whether the input vector type is legal.
3568 SDNode *InVal = Node->getOperand(0).Val;
3569 int InIx = Node->getOperand(0).ResNo;
3570 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(InIx));
3571 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(InIx));
3573 // Figure out if there is a simple type corresponding to this Vector
3574 // type. If so, convert to the vector type.
3575 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3576 if (TLI.isTypeLegal(TVT)) {
3577 // Turn this into a bit convert of the vector input.
3578 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3579 LegalizeOp(Node->getOperand(0)));
3581 } else if (NumElems == 1) {
3582 // Turn this into a bit convert of the scalar input.
3583 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3584 ScalarizeVectorOp(Node->getOperand(0)));
3587 // FIXME: UNIMP! Store then reload
3588 assert(0 && "Cast from unsupported vector type not implemented yet!");
3591 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3592 Node->getOperand(0).getValueType())) {
3593 default: assert(0 && "Unknown operation action!");
3594 case TargetLowering::Expand:
3595 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3596 Node->getValueType(0));
3598 case TargetLowering::Legal:
3599 Tmp1 = LegalizeOp(Node->getOperand(0));
3600 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3606 // Conversion operators. The source and destination have different types.
3607 case ISD::SINT_TO_FP:
3608 case ISD::UINT_TO_FP: {
3609 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
3610 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3612 switch (TLI.getOperationAction(Node->getOpcode(),
3613 Node->getOperand(0).getValueType())) {
3614 default: assert(0 && "Unknown operation action!");
3615 case TargetLowering::Custom:
3618 case TargetLowering::Legal:
3619 Tmp1 = LegalizeOp(Node->getOperand(0));
3620 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3622 Tmp1 = TLI.LowerOperation(Result, DAG);
3623 if (Tmp1.Val) Result = Tmp1;
3626 case TargetLowering::Expand:
3627 Result = ExpandLegalINT_TO_FP(isSigned,
3628 LegalizeOp(Node->getOperand(0)),
3629 Node->getValueType(0));
3631 case TargetLowering::Promote:
3632 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
3633 Node->getValueType(0),
3639 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
3640 Node->getValueType(0), Node->getOperand(0));
3643 Tmp1 = PromoteOp(Node->getOperand(0));
3645 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
3646 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
3648 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
3649 Node->getOperand(0).getValueType());
3651 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3652 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
3658 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3660 Tmp1 = LegalizeOp(Node->getOperand(0));
3661 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3664 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3666 // Since the result is legal, we should just be able to truncate the low
3667 // part of the source.
3668 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
3671 Result = PromoteOp(Node->getOperand(0));
3672 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
3677 case ISD::FP_TO_SINT:
3678 case ISD::FP_TO_UINT:
3679 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3681 Tmp1 = LegalizeOp(Node->getOperand(0));
3683 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
3684 default: assert(0 && "Unknown operation action!");
3685 case TargetLowering::Custom:
3688 case TargetLowering::Legal:
3689 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3691 Tmp1 = TLI.LowerOperation(Result, DAG);
3692 if (Tmp1.Val) Result = Tmp1;
3695 case TargetLowering::Promote:
3696 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
3697 Node->getOpcode() == ISD::FP_TO_SINT);
3699 case TargetLowering::Expand:
3700 if (Node->getOpcode() == ISD::FP_TO_UINT) {
3701 SDOperand True, False;
3702 MVT::ValueType VT = Node->getOperand(0).getValueType();
3703 MVT::ValueType NVT = Node->getValueType(0);
3704 const uint64_t zero[] = {0, 0};
3705 APFloat apf = APFloat(APInt(MVT::getSizeInBits(VT), 2, zero));
3706 APInt x = APInt::getSignBit(MVT::getSizeInBits(NVT));
3707 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3708 Tmp2 = DAG.getConstantFP(apf, VT);
3709 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
3710 Node->getOperand(0), Tmp2, ISD::SETLT);
3711 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
3712 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
3713 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
3715 False = DAG.getNode(ISD::XOR, NVT, False,
3716 DAG.getConstant(x, NVT));
3717 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
3720 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
3726 MVT::ValueType VT = Op.getValueType();
3727 MVT::ValueType OVT = Node->getOperand(0).getValueType();
3728 // Convert ppcf128 to i32
3729 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
3730 if (Node->getOpcode() == ISD::FP_TO_SINT) {
3731 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
3732 Node->getOperand(0), DAG.getValueType(MVT::f64));
3733 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
3734 DAG.getIntPtrConstant(1));
3735 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
3737 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
3738 APFloat apf = APFloat(APInt(128, 2, TwoE31));
3739 Tmp2 = DAG.getConstantFP(apf, OVT);
3740 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
3741 // FIXME: generated code sucks.
3742 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
3743 DAG.getNode(ISD::ADD, MVT::i32,
3744 DAG.getNode(ISD::FP_TO_SINT, VT,
3745 DAG.getNode(ISD::FSUB, OVT,
3746 Node->getOperand(0), Tmp2)),
3747 DAG.getConstant(0x80000000, MVT::i32)),
3748 DAG.getNode(ISD::FP_TO_SINT, VT,
3749 Node->getOperand(0)),
3750 DAG.getCondCode(ISD::SETGE));
3754 // Convert f32 / f64 to i32 / i64 / i128.
3755 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3756 switch (Node->getOpcode()) {
3757 case ISD::FP_TO_SINT: {
3758 if (VT == MVT::i32) {
3759 if (OVT == MVT::f32)
3760 LC = RTLIB::FPTOSINT_F32_I32;
3761 else if (OVT == MVT::f64)
3762 LC = RTLIB::FPTOSINT_F64_I32;
3764 assert(0 && "Unexpected i32-to-fp conversion!");
3765 } else if (VT == MVT::i64) {
3766 if (OVT == MVT::f32)
3767 LC = RTLIB::FPTOSINT_F32_I64;
3768 else if (OVT == MVT::f64)
3769 LC = RTLIB::FPTOSINT_F64_I64;
3770 else if (OVT == MVT::f80)
3771 LC = RTLIB::FPTOSINT_F80_I64;
3772 else if (OVT == MVT::ppcf128)
3773 LC = RTLIB::FPTOSINT_PPCF128_I64;
3775 assert(0 && "Unexpected i64-to-fp conversion!");
3776 } else if (VT == MVT::i128) {
3777 if (OVT == MVT::f32)
3778 LC = RTLIB::FPTOSINT_F32_I128;
3779 else if (OVT == MVT::f64)
3780 LC = RTLIB::FPTOSINT_F64_I128;
3781 else if (OVT == MVT::f80)
3782 LC = RTLIB::FPTOSINT_F80_I128;
3783 else if (OVT == MVT::ppcf128)
3784 LC = RTLIB::FPTOSINT_PPCF128_I128;
3786 assert(0 && "Unexpected i128-to-fp conversion!");
3788 assert(0 && "Unexpectd int-to-fp conversion!");
3792 case ISD::FP_TO_UINT: {
3793 if (VT == MVT::i32) {
3794 if (OVT == MVT::f32)
3795 LC = RTLIB::FPTOUINT_F32_I32;
3796 else if (OVT == MVT::f64)
3797 LC = RTLIB::FPTOUINT_F64_I32;
3798 else if (OVT == MVT::f80)
3799 LC = RTLIB::FPTOUINT_F80_I32;
3801 assert(0 && "Unexpected i32-to-fp conversion!");
3802 } else if (VT == MVT::i64) {
3803 if (OVT == MVT::f32)
3804 LC = RTLIB::FPTOUINT_F32_I64;
3805 else if (OVT == MVT::f64)
3806 LC = RTLIB::FPTOUINT_F64_I64;
3807 else if (OVT == MVT::f80)
3808 LC = RTLIB::FPTOUINT_F80_I64;
3809 else if (OVT == MVT::ppcf128)
3810 LC = RTLIB::FPTOUINT_PPCF128_I64;
3812 assert(0 && "Unexpected i64-to-fp conversion!");
3813 } else if (VT == MVT::i128) {
3814 if (OVT == MVT::f32)
3815 LC = RTLIB::FPTOUINT_F32_I128;
3816 else if (OVT == MVT::f64)
3817 LC = RTLIB::FPTOUINT_F64_I128;
3818 else if (OVT == MVT::f80)
3819 LC = RTLIB::FPTOUINT_F80_I128;
3820 else if (OVT == MVT::ppcf128)
3821 LC = RTLIB::FPTOUINT_PPCF128_I128;
3823 assert(0 && "Unexpected i128-to-fp conversion!");
3825 assert(0 && "Unexpectd int-to-fp conversion!");
3829 default: assert(0 && "Unreachable!");
3832 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3836 Tmp1 = PromoteOp(Node->getOperand(0));
3837 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3838 Result = LegalizeOp(Result);
3843 case ISD::FP_EXTEND: {
3844 MVT::ValueType DstVT = Op.getValueType();
3845 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3846 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3847 // The only other way we can lower this is to turn it into a STORE,
3848 // LOAD pair, targetting a temporary location (a stack slot).
3849 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
3852 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3853 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3855 Tmp1 = LegalizeOp(Node->getOperand(0));
3856 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3859 Tmp1 = PromoteOp(Node->getOperand(0));
3860 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
3865 case ISD::FP_ROUND: {
3866 MVT::ValueType DstVT = Op.getValueType();
3867 MVT::ValueType SrcVT = Op.getOperand(0).getValueType();
3868 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
3869 if (SrcVT == MVT::ppcf128) {
3871 ExpandOp(Node->getOperand(0), Lo, Result);
3872 // Round it the rest of the way (e.g. to f32) if needed.
3873 if (DstVT!=MVT::f64)
3874 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
3877 // The only other way we can lower this is to turn it into a STORE,
3878 // LOAD pair, targetting a temporary location (a stack slot).
3879 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
3882 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3883 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3885 Tmp1 = LegalizeOp(Node->getOperand(0));
3886 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3889 Tmp1 = PromoteOp(Node->getOperand(0));
3890 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
3891 Node->getOperand(1));
3896 case ISD::ANY_EXTEND:
3897 case ISD::ZERO_EXTEND:
3898 case ISD::SIGN_EXTEND:
3899 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3900 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3902 Tmp1 = LegalizeOp(Node->getOperand(0));
3903 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3904 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3905 TargetLowering::Custom) {
3906 Tmp1 = TLI.LowerOperation(Result, DAG);
3907 if (Tmp1.Val) Result = Tmp1;
3911 switch (Node->getOpcode()) {
3912 case ISD::ANY_EXTEND:
3913 Tmp1 = PromoteOp(Node->getOperand(0));
3914 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3916 case ISD::ZERO_EXTEND:
3917 Result = PromoteOp(Node->getOperand(0));
3918 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3919 Result = DAG.getZeroExtendInReg(Result,
3920 Node->getOperand(0).getValueType());
3922 case ISD::SIGN_EXTEND:
3923 Result = PromoteOp(Node->getOperand(0));
3924 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3925 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3927 DAG.getValueType(Node->getOperand(0).getValueType()));
3932 case ISD::FP_ROUND_INREG:
3933 case ISD::SIGN_EXTEND_INREG: {
3934 Tmp1 = LegalizeOp(Node->getOperand(0));
3935 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3937 // If this operation is not supported, convert it to a shl/shr or load/store
3939 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3940 default: assert(0 && "This action not supported for this op yet!");
3941 case TargetLowering::Legal:
3942 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3944 case TargetLowering::Expand:
3945 // If this is an integer extend and shifts are supported, do that.
3946 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3947 // NOTE: we could fall back on load/store here too for targets without
3948 // SAR. However, it is doubtful that any exist.
3949 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3950 MVT::getSizeInBits(ExtraVT);
3951 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3952 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3953 Node->getOperand(0), ShiftCst);
3954 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3956 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3957 // The only way we can lower this is to turn it into a TRUNCSTORE,
3958 // EXTLOAD pair, targetting a temporary location (a stack slot).
3960 // NOTE: there is a choice here between constantly creating new stack
3961 // slots and always reusing the same one. We currently always create
3962 // new ones, as reuse may inhibit scheduling.
3963 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
3964 Node->getValueType(0));
3966 assert(0 && "Unknown op");
3972 case ISD::TRAMPOLINE: {
3974 for (unsigned i = 0; i != 6; ++i)
3975 Ops[i] = LegalizeOp(Node->getOperand(i));
3976 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
3977 // The only option for this node is to custom lower it.
3978 Result = TLI.LowerOperation(Result, DAG);
3979 assert(Result.Val && "Should always custom lower!");
3981 // Since trampoline produces two values, make sure to remember that we
3982 // legalized both of them.
3983 Tmp1 = LegalizeOp(Result.getValue(1));
3984 Result = LegalizeOp(Result);
3985 AddLegalizedOperand(SDOperand(Node, 0), Result);
3986 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
3987 return Op.ResNo ? Tmp1 : Result;
3989 case ISD::FLT_ROUNDS_: {
3990 MVT::ValueType VT = Node->getValueType(0);
3991 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
3992 default: assert(0 && "This action not supported for this op yet!");
3993 case TargetLowering::Custom:
3994 Result = TLI.LowerOperation(Op, DAG);
3995 if (Result.Val) break;
3997 case TargetLowering::Legal:
3998 // If this operation is not supported, lower it to constant 1
3999 Result = DAG.getConstant(1, VT);
4004 MVT::ValueType VT = Node->getValueType(0);
4005 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4006 default: assert(0 && "This action not supported for this op yet!");
4007 case TargetLowering::Legal:
4008 Tmp1 = LegalizeOp(Node->getOperand(0));
4009 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4011 case TargetLowering::Custom:
4012 Result = TLI.LowerOperation(Op, DAG);
4013 if (Result.Val) break;
4015 case TargetLowering::Expand:
4016 // If this operation is not supported, lower it to 'abort()' call
4017 Tmp1 = LegalizeOp(Node->getOperand(0));
4018 TargetLowering::ArgListTy Args;
4019 std::pair<SDOperand,SDOperand> CallResult =
4020 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4021 false, false, false, CallingConv::C, false,
4022 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4024 Result = CallResult.second;
4031 assert(Result.getValueType() == Op.getValueType() &&
4032 "Bad legalization!");
4034 // Make sure that the generated code is itself legal.
4036 Result = LegalizeOp(Result);
4038 // Note that LegalizeOp may be reentered even from single-use nodes, which
4039 // means that we always must cache transformed nodes.
4040 AddLegalizedOperand(Op, Result);
4044 /// PromoteOp - Given an operation that produces a value in an invalid type,
4045 /// promote it to compute the value into a larger type. The produced value will
4046 /// have the correct bits for the low portion of the register, but no guarantee
4047 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4048 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
4049 MVT::ValueType VT = Op.getValueType();
4050 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4051 assert(getTypeAction(VT) == Promote &&
4052 "Caller should expand or legalize operands that are not promotable!");
4053 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
4054 "Cannot promote to smaller type!");
4056 SDOperand Tmp1, Tmp2, Tmp3;
4058 SDNode *Node = Op.Val;
4060 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
4061 if (I != PromotedNodes.end()) return I->second;
4063 switch (Node->getOpcode()) {
4064 case ISD::CopyFromReg:
4065 assert(0 && "CopyFromReg must be legal!");
4068 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4070 assert(0 && "Do not know how to promote this operator!");
4073 Result = DAG.getNode(ISD::UNDEF, NVT);
4077 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4079 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4080 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4082 case ISD::ConstantFP:
4083 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4084 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4088 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4089 && "SetCC type is not legal??");
4090 Result = DAG.getNode(ISD::SETCC,
4091 TLI.getSetCCResultType(Node->getOperand(0)),
4092 Node->getOperand(0), Node->getOperand(1),
4093 Node->getOperand(2));
4097 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4099 Result = LegalizeOp(Node->getOperand(0));
4100 assert(Result.getValueType() >= NVT &&
4101 "This truncation doesn't make sense!");
4102 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
4103 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4106 // The truncation is not required, because we don't guarantee anything
4107 // about high bits anyway.
4108 Result = PromoteOp(Node->getOperand(0));
4111 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4112 // Truncate the low part of the expanded value to the result type
4113 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4116 case ISD::SIGN_EXTEND:
4117 case ISD::ZERO_EXTEND:
4118 case ISD::ANY_EXTEND:
4119 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4120 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4122 // Input is legal? Just do extend all the way to the larger type.
4123 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4126 // Promote the reg if it's smaller.
4127 Result = PromoteOp(Node->getOperand(0));
4128 // The high bits are not guaranteed to be anything. Insert an extend.
4129 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4130 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4131 DAG.getValueType(Node->getOperand(0).getValueType()));
4132 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4133 Result = DAG.getZeroExtendInReg(Result,
4134 Node->getOperand(0).getValueType());
4138 case ISD::BIT_CONVERT:
4139 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4140 Node->getValueType(0));
4141 Result = PromoteOp(Result);
4144 case ISD::FP_EXTEND:
4145 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4147 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4148 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4149 case Promote: assert(0 && "Unreachable with 2 FP types!");
4151 if (Node->getConstantOperandVal(1) == 0) {
4152 // Input is legal? Do an FP_ROUND_INREG.
4153 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4154 DAG.getValueType(VT));
4156 // Just remove the truncate, it isn't affecting the value.
4157 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4158 Node->getOperand(1));
4163 case ISD::SINT_TO_FP:
4164 case ISD::UINT_TO_FP:
4165 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4167 // No extra round required here.
4168 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4172 Result = PromoteOp(Node->getOperand(0));
4173 if (Node->getOpcode() == ISD::SINT_TO_FP)
4174 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4176 DAG.getValueType(Node->getOperand(0).getValueType()));
4178 Result = DAG.getZeroExtendInReg(Result,
4179 Node->getOperand(0).getValueType());
4180 // No extra round required here.
4181 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4184 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4185 Node->getOperand(0));
4186 // Round if we cannot tolerate excess precision.
4187 if (NoExcessFPPrecision)
4188 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4189 DAG.getValueType(VT));
4194 case ISD::SIGN_EXTEND_INREG:
4195 Result = PromoteOp(Node->getOperand(0));
4196 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4197 Node->getOperand(1));
4199 case ISD::FP_TO_SINT:
4200 case ISD::FP_TO_UINT:
4201 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4204 Tmp1 = Node->getOperand(0);
4207 // The input result is prerounded, so we don't have to do anything
4209 Tmp1 = PromoteOp(Node->getOperand(0));
4212 // If we're promoting a UINT to a larger size, check to see if the new node
4213 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4214 // we can use that instead. This allows us to generate better code for
4215 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4216 // legal, such as PowerPC.
4217 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4218 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4219 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4220 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4221 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4223 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4229 Tmp1 = PromoteOp(Node->getOperand(0));
4230 assert(Tmp1.getValueType() == NVT);
4231 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4232 // NOTE: we do not have to do any extra rounding here for
4233 // NoExcessFPPrecision, because we know the input will have the appropriate
4234 // precision, and these operations don't modify precision at all.
4240 Tmp1 = PromoteOp(Node->getOperand(0));
4241 assert(Tmp1.getValueType() == NVT);
4242 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4243 if (NoExcessFPPrecision)
4244 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4245 DAG.getValueType(VT));
4249 // Promote f32 powi to f64 powi. Note that this could insert a libcall
4250 // directly as well, which may be better.
4251 Tmp1 = PromoteOp(Node->getOperand(0));
4252 assert(Tmp1.getValueType() == NVT);
4253 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
4254 if (NoExcessFPPrecision)
4255 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4256 DAG.getValueType(VT));
4260 case ISD::ATOMIC_LCS: {
4261 Tmp2 = PromoteOp(Node->getOperand(2));
4262 Tmp3 = PromoteOp(Node->getOperand(3));
4263 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4264 Node->getOperand(1), Tmp2, Tmp3,
4265 cast<AtomicSDNode>(Node)->getVT());
4266 // Remember that we legalized the chain.
4267 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4270 case ISD::ATOMIC_LAS:
4271 case ISD::ATOMIC_LSS:
4272 case ISD::ATOMIC_LOAD_AND:
4273 case ISD::ATOMIC_LOAD_OR:
4274 case ISD::ATOMIC_LOAD_XOR:
4275 case ISD::ATOMIC_LOAD_MIN:
4276 case ISD::ATOMIC_LOAD_MAX:
4277 case ISD::ATOMIC_LOAD_UMIN:
4278 case ISD::ATOMIC_LOAD_UMAX:
4279 case ISD::ATOMIC_SWAP: {
4280 Tmp2 = PromoteOp(Node->getOperand(2));
4281 Result = DAG.getAtomic(Node->getOpcode(), Node->getOperand(0),
4282 Node->getOperand(1), Tmp2,
4283 cast<AtomicSDNode>(Node)->getVT());
4284 // Remember that we legalized the chain.
4285 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4295 // The input may have strange things in the top bits of the registers, but
4296 // these operations don't care. They may have weird bits going out, but
4297 // that too is okay if they are integer operations.
4298 Tmp1 = PromoteOp(Node->getOperand(0));
4299 Tmp2 = PromoteOp(Node->getOperand(1));
4300 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4301 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4306 Tmp1 = PromoteOp(Node->getOperand(0));
4307 Tmp2 = PromoteOp(Node->getOperand(1));
4308 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4309 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4311 // Floating point operations will give excess precision that we may not be
4312 // able to tolerate. If we DO allow excess precision, just leave it,
4313 // otherwise excise it.
4314 // FIXME: Why would we need to round FP ops more than integer ones?
4315 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4316 if (NoExcessFPPrecision)
4317 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4318 DAG.getValueType(VT));
4323 // These operators require that their input be sign extended.
4324 Tmp1 = PromoteOp(Node->getOperand(0));
4325 Tmp2 = PromoteOp(Node->getOperand(1));
4326 if (MVT::isInteger(NVT)) {
4327 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4328 DAG.getValueType(VT));
4329 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4330 DAG.getValueType(VT));
4332 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4334 // Perform FP_ROUND: this is probably overly pessimistic.
4335 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
4336 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4337 DAG.getValueType(VT));
4341 case ISD::FCOPYSIGN:
4342 // These operators require that their input be fp extended.
4343 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4344 case Expand: assert(0 && "not implemented");
4345 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4346 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4348 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4349 case Expand: assert(0 && "not implemented");
4350 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4351 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4353 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4355 // Perform FP_ROUND: this is probably overly pessimistic.
4356 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4357 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4358 DAG.getValueType(VT));
4363 // These operators require that their input be zero extended.
4364 Tmp1 = PromoteOp(Node->getOperand(0));
4365 Tmp2 = PromoteOp(Node->getOperand(1));
4366 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
4367 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4368 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4369 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4373 Tmp1 = PromoteOp(Node->getOperand(0));
4374 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4377 // The input value must be properly sign extended.
4378 Tmp1 = PromoteOp(Node->getOperand(0));
4379 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4380 DAG.getValueType(VT));
4381 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4384 // The input value must be properly zero extended.
4385 Tmp1 = PromoteOp(Node->getOperand(0));
4386 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4387 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4391 Tmp1 = Node->getOperand(0); // Get the chain.
4392 Tmp2 = Node->getOperand(1); // Get the pointer.
4393 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4394 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4395 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
4397 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4398 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4399 // Increment the pointer, VAList, to the next vaarg
4400 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4401 DAG.getConstant(MVT::getSizeInBits(VT)/8,
4402 TLI.getPointerTy()));
4403 // Store the incremented VAList to the legalized pointer
4404 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4405 // Load the actual argument out of the pointer VAList
4406 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4408 // Remember that we legalized the chain.
4409 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4413 LoadSDNode *LD = cast<LoadSDNode>(Node);
4414 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4415 ? ISD::EXTLOAD : LD->getExtensionType();
4416 Result = DAG.getExtLoad(ExtType, NVT,
4417 LD->getChain(), LD->getBasePtr(),
4418 LD->getSrcValue(), LD->getSrcValueOffset(),
4421 LD->getAlignment());
4422 // Remember that we legalized the chain.
4423 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4427 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4428 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4429 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
4431 case ISD::SELECT_CC:
4432 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4433 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4434 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4435 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4438 Tmp1 = Node->getOperand(0);
4439 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4440 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4441 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4442 DAG.getConstant(MVT::getSizeInBits(NVT) -
4443 MVT::getSizeInBits(VT),
4444 TLI.getShiftAmountTy()));
4449 // Zero extend the argument
4450 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4451 // Perform the larger operation, then subtract if needed.
4452 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4453 switch(Node->getOpcode()) {
4458 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4459 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4460 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
4462 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4463 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
4466 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4467 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4468 DAG.getConstant(MVT::getSizeInBits(NVT) -
4469 MVT::getSizeInBits(VT), NVT));
4473 case ISD::EXTRACT_SUBVECTOR:
4474 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4476 case ISD::EXTRACT_VECTOR_ELT:
4477 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4481 assert(Result.Val && "Didn't set a result!");
4483 // Make sure the result is itself legal.
4484 Result = LegalizeOp(Result);
4486 // Remember that we promoted this!
4487 AddPromotedOperand(Op, Result);
4491 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
4492 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
4493 /// based on the vector type. The return type of this matches the element type
4494 /// of the vector, which may not be legal for the target.
4495 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
4496 // We know that operand #0 is the Vec vector. If the index is a constant
4497 // or if the invec is a supported hardware type, we can use it. Otherwise,
4498 // lower to a store then an indexed load.
4499 SDOperand Vec = Op.getOperand(0);
4500 SDOperand Idx = Op.getOperand(1);
4502 MVT::ValueType TVT = Vec.getValueType();
4503 unsigned NumElems = MVT::getVectorNumElements(TVT);
4505 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
4506 default: assert(0 && "This action is not supported yet!");
4507 case TargetLowering::Custom: {
4508 Vec = LegalizeOp(Vec);
4509 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4510 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
4515 case TargetLowering::Legal:
4516 if (isTypeLegal(TVT)) {
4517 Vec = LegalizeOp(Vec);
4518 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4522 case TargetLowering::Expand:
4526 if (NumElems == 1) {
4527 // This must be an access of the only element. Return it.
4528 Op = ScalarizeVectorOp(Vec);
4529 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
4530 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
4531 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4533 SplitVectorOp(Vec, Lo, Hi);
4534 if (CIdx->getValue() < NumLoElts) {
4538 Idx = DAG.getConstant(CIdx->getValue() - NumLoElts,
4539 Idx.getValueType());
4542 // It's now an extract from the appropriate high or low part. Recurse.
4543 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4544 Op = ExpandEXTRACT_VECTOR_ELT(Op);
4546 // Store the value to a temporary stack slot, then LOAD the scalar
4547 // element back out.
4548 SDOperand StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
4549 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
4551 // Add the offset to the index.
4552 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
4553 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
4554 DAG.getConstant(EltSize, Idx.getValueType()));
4556 if (MVT::getSizeInBits(Idx.getValueType()) >
4557 MVT::getSizeInBits(TLI.getPointerTy()))
4558 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
4560 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
4562 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
4564 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
4569 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
4570 /// we assume the operation can be split if it is not already legal.
4571 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
4572 // We know that operand #0 is the Vec vector. For now we assume the index
4573 // is a constant and that the extracted result is a supported hardware type.
4574 SDOperand Vec = Op.getOperand(0);
4575 SDOperand Idx = LegalizeOp(Op.getOperand(1));
4577 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
4579 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
4580 // This must be an access of the desired vector length. Return it.
4584 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
4586 SplitVectorOp(Vec, Lo, Hi);
4587 if (CIdx->getValue() < NumElems/2) {
4591 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
4594 // It's now an extract from the appropriate high or low part. Recurse.
4595 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
4596 return ExpandEXTRACT_SUBVECTOR(Op);
4599 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
4600 /// with condition CC on the current target. This usually involves legalizing
4601 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
4602 /// there may be no choice but to create a new SetCC node to represent the
4603 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
4604 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
4605 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
4608 SDOperand Tmp1, Tmp2, Tmp3, Result;
4610 switch (getTypeAction(LHS.getValueType())) {
4612 Tmp1 = LegalizeOp(LHS); // LHS
4613 Tmp2 = LegalizeOp(RHS); // RHS
4616 Tmp1 = PromoteOp(LHS); // LHS
4617 Tmp2 = PromoteOp(RHS); // RHS
4619 // If this is an FP compare, the operands have already been extended.
4620 if (MVT::isInteger(LHS.getValueType())) {
4621 MVT::ValueType VT = LHS.getValueType();
4622 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4624 // Otherwise, we have to insert explicit sign or zero extends. Note
4625 // that we could insert sign extends for ALL conditions, but zero extend
4626 // is cheaper on many machines (an AND instead of two shifts), so prefer
4628 switch (cast<CondCodeSDNode>(CC)->get()) {
4629 default: assert(0 && "Unknown integer comparison!");
4636 // ALL of these operations will work if we either sign or zero extend
4637 // the operands (including the unsigned comparisons!). Zero extend is
4638 // usually a simpler/cheaper operation, so prefer it.
4639 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4640 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4646 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4647 DAG.getValueType(VT));
4648 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4649 DAG.getValueType(VT));
4655 MVT::ValueType VT = LHS.getValueType();
4656 if (VT == MVT::f32 || VT == MVT::f64) {
4657 // Expand into one or more soft-fp libcall(s).
4658 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
4659 switch (cast<CondCodeSDNode>(CC)->get()) {
4662 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4666 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
4670 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4674 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4678 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4682 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4685 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4688 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
4691 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
4692 switch (cast<CondCodeSDNode>(CC)->get()) {
4694 // SETONE = SETOLT | SETOGT
4695 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4698 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
4701 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
4704 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
4707 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
4710 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
4712 default: assert(0 && "Unsupported FP setcc!");
4717 Tmp1 = ExpandLibCall(LC1,
4718 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4719 false /*sign irrelevant*/, Dummy);
4720 Tmp2 = DAG.getConstant(0, MVT::i32);
4721 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
4722 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
4723 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
4725 LHS = ExpandLibCall(LC2,
4726 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
4727 false /*sign irrelevant*/, Dummy);
4728 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
4729 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
4730 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4738 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
4739 ExpandOp(LHS, LHSLo, LHSHi);
4740 ExpandOp(RHS, RHSLo, RHSHi);
4741 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
4743 if (VT==MVT::ppcf128) {
4744 // FIXME: This generated code sucks. We want to generate
4745 // FCMP crN, hi1, hi2
4747 // FCMP crN, lo1, lo2
4748 // The following can be improved, but not that much.
4749 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETEQ);
4750 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
4751 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4752 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, ISD::SETNE);
4753 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
4754 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
4755 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
4764 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
4765 if (RHSCST->isAllOnesValue()) {
4766 // Comparison to -1.
4767 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
4772 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
4773 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
4774 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
4775 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
4778 // If this is a comparison of the sign bit, just look at the top part.
4780 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
4781 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
4782 CST->isNullValue()) || // X < 0
4783 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
4784 CST->isAllOnesValue())) { // X > -1
4790 // FIXME: This generated code sucks.
4791 ISD::CondCode LowCC;
4793 default: assert(0 && "Unknown integer setcc!");
4795 case ISD::SETULT: LowCC = ISD::SETULT; break;
4797 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
4799 case ISD::SETULE: LowCC = ISD::SETULE; break;
4801 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
4804 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
4805 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
4806 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
4808 // NOTE: on targets without efficient SELECT of bools, we can always use
4809 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
4810 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
4811 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
4812 LowCC, false, DagCombineInfo);
4814 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
4815 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4816 CCCode, false, DagCombineInfo);
4818 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
4821 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
4822 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
4823 if ((Tmp1C && Tmp1C->isNullValue()) ||
4824 (Tmp2C && Tmp2C->isNullValue() &&
4825 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
4826 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
4827 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
4828 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
4829 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
4830 // low part is known false, returns high part.
4831 // For LE / GE, if high part is known false, ignore the low part.
4832 // For LT / GT, if high part is known true, ignore the low part.
4836 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4837 ISD::SETEQ, false, DagCombineInfo);
4839 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
4841 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
4842 Result, Tmp1, Tmp2));
4853 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
4854 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
4855 /// a load from the stack slot to DestVT, extending it if needed.
4856 /// The resultant code need not be legal.
4857 SDOperand SelectionDAGLegalize::EmitStackConvert(SDOperand SrcOp,
4858 MVT::ValueType SlotVT,
4859 MVT::ValueType DestVT) {
4860 // Create the stack frame object.
4861 SDOperand FIPtr = DAG.CreateStackTemporary(SlotVT);
4863 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
4864 int SPFI = StackPtrFI->getIndex();
4866 unsigned SrcSize = MVT::getSizeInBits(SrcOp.getValueType());
4867 unsigned SlotSize = MVT::getSizeInBits(SlotVT);
4868 unsigned DestSize = MVT::getSizeInBits(DestVT);
4870 // Emit a store to the stack slot. Use a truncstore if the input value is
4871 // later than DestVT.
4873 if (SrcSize > SlotSize)
4874 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
4875 PseudoSourceValue::getFixedStack(),
4878 assert(SrcSize == SlotSize && "Invalid store");
4879 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
4880 PseudoSourceValue::getFixedStack(),
4884 // Result is a load from the stack slot.
4885 if (SlotSize == DestSize)
4886 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
4888 assert(SlotSize < DestSize && "Unknown extension!");
4889 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT);
4892 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
4893 // Create a vector sized/aligned stack slot, store the value to element #0,
4894 // then load the whole vector back out.
4895 SDOperand StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
4897 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
4898 int SPFI = StackPtrFI->getIndex();
4900 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
4901 PseudoSourceValue::getFixedStack(), SPFI);
4902 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
4903 PseudoSourceValue::getFixedStack(), SPFI);
4907 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
4908 /// support the operation, but do support the resultant vector type.
4909 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
4911 // If the only non-undef value is the low element, turn this into a
4912 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
4913 unsigned NumElems = Node->getNumOperands();
4914 bool isOnlyLowElement = true;
4915 SDOperand SplatValue = Node->getOperand(0);
4917 // FIXME: it would be far nicer to change this into map<SDOperand,uint64_t>
4918 // and use a bitmask instead of a list of elements.
4919 std::map<SDOperand, std::vector<unsigned> > Values;
4920 Values[SplatValue].push_back(0);
4921 bool isConstant = true;
4922 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
4923 SplatValue.getOpcode() != ISD::UNDEF)
4926 for (unsigned i = 1; i < NumElems; ++i) {
4927 SDOperand V = Node->getOperand(i);
4928 Values[V].push_back(i);
4929 if (V.getOpcode() != ISD::UNDEF)
4930 isOnlyLowElement = false;
4931 if (SplatValue != V)
4932 SplatValue = SDOperand(0,0);
4934 // If this isn't a constant element or an undef, we can't use a constant
4936 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
4937 V.getOpcode() != ISD::UNDEF)
4941 if (isOnlyLowElement) {
4942 // If the low element is an undef too, then this whole things is an undef.
4943 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
4944 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
4945 // Otherwise, turn this into a scalar_to_vector node.
4946 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4947 Node->getOperand(0));
4950 // If all elements are constants, create a load from the constant pool.
4952 MVT::ValueType VT = Node->getValueType(0);
4953 std::vector<Constant*> CV;
4954 for (unsigned i = 0, e = NumElems; i != e; ++i) {
4955 if (ConstantFPSDNode *V =
4956 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
4957 CV.push_back(ConstantFP::get(V->getValueAPF()));
4958 } else if (ConstantSDNode *V =
4959 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
4960 CV.push_back(ConstantInt::get(V->getAPIntValue()));
4962 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
4964 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
4965 CV.push_back(UndefValue::get(OpNTy));
4968 Constant *CP = ConstantVector::get(CV);
4969 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
4970 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
4971 PseudoSourceValue::getConstantPool(), 0);
4974 if (SplatValue.Val) { // Splat of one value?
4975 // Build the shuffle constant vector: <0, 0, 0, 0>
4976 MVT::ValueType MaskVT =
4977 MVT::getIntVectorWithNumElements(NumElems);
4978 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4979 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4980 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4981 &ZeroVec[0], ZeroVec.size());
4983 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4984 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4985 // Get the splatted value into the low element of a vector register.
4986 SDOperand LowValVec =
4987 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4989 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4990 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4991 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4996 // If there are only two unique elements, we may be able to turn this into a
4998 if (Values.size() == 2) {
4999 // Get the two values in deterministic order.
5000 SDOperand Val1 = Node->getOperand(1);
5002 std::map<SDOperand, std::vector<unsigned> >::iterator MI = Values.begin();
5003 if (MI->first != Val1)
5006 Val2 = (++MI)->first;
5008 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5009 // vector shuffle has the undef vector on the RHS.
5010 if (Val1.getOpcode() == ISD::UNDEF)
5011 std::swap(Val1, Val2);
5013 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5014 MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5015 MVT::ValueType MaskEltVT = MVT::getVectorElementType(MaskVT);
5016 std::vector<SDOperand> MaskVec(NumElems);
5018 // Set elements of the shuffle mask for Val1.
5019 std::vector<unsigned> &Val1Elts = Values[Val1];
5020 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5021 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5023 // Set elements of the shuffle mask for Val2.
5024 std::vector<unsigned> &Val2Elts = Values[Val2];
5025 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5026 if (Val2.getOpcode() != ISD::UNDEF)
5027 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5029 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5031 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5032 &MaskVec[0], MaskVec.size());
5034 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5035 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5036 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5037 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5038 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5039 SDOperand Ops[] = { Val1, Val2, ShuffleMask };
5041 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5042 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5046 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5047 // aligned object on the stack, store each element into it, then load
5048 // the result as a vector.
5049 MVT::ValueType VT = Node->getValueType(0);
5050 // Create the stack frame object.
5051 SDOperand FIPtr = DAG.CreateStackTemporary(VT);
5053 // Emit a store of each element to the stack slot.
5054 SmallVector<SDOperand, 8> Stores;
5055 unsigned TypeByteSize =
5056 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
5057 // Store (in the right endianness) the elements to memory.
5058 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5059 // Ignore undef elements.
5060 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5062 unsigned Offset = TypeByteSize*i;
5064 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5065 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5067 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5071 SDOperand StoreChain;
5072 if (!Stores.empty()) // Not all undef elements?
5073 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5074 &Stores[0], Stores.size());
5076 StoreChain = DAG.getEntryNode();
5078 // Result is a load from the stack slot.
5079 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5082 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5083 SDOperand Op, SDOperand Amt,
5084 SDOperand &Lo, SDOperand &Hi) {
5085 // Expand the subcomponents.
5086 SDOperand LHSL, LHSH;
5087 ExpandOp(Op, LHSL, LHSH);
5089 SDOperand Ops[] = { LHSL, LHSH, Amt };
5090 MVT::ValueType VT = LHSL.getValueType();
5091 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5092 Hi = Lo.getValue(1);
5096 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5097 /// smaller elements. If we can't find a way that is more efficient than a
5098 /// libcall on this target, return false. Otherwise, return true with the
5099 /// low-parts expanded into Lo and Hi.
5100 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
5101 SDOperand &Lo, SDOperand &Hi) {
5102 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5103 "This is not a shift!");
5105 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
5106 SDOperand ShAmt = LegalizeOp(Amt);
5107 MVT::ValueType ShTy = ShAmt.getValueType();
5108 unsigned ShBits = MVT::getSizeInBits(ShTy);
5109 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
5110 unsigned NVTBits = MVT::getSizeInBits(NVT);
5112 // Handle the case when Amt is an immediate.
5113 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
5114 unsigned Cst = CN->getValue();
5115 // Expand the incoming operand to be shifted, so that we have its parts
5117 ExpandOp(Op, InL, InH);
5121 Lo = DAG.getConstant(0, NVT);
5122 Hi = DAG.getConstant(0, NVT);
5123 } else if (Cst > NVTBits) {
5124 Lo = DAG.getConstant(0, NVT);
5125 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5126 } else if (Cst == NVTBits) {
5127 Lo = DAG.getConstant(0, NVT);
5130 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5131 Hi = DAG.getNode(ISD::OR, NVT,
5132 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5133 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5138 Lo = DAG.getConstant(0, NVT);
5139 Hi = DAG.getConstant(0, NVT);
5140 } else if (Cst > NVTBits) {
5141 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5142 Hi = DAG.getConstant(0, NVT);
5143 } else if (Cst == NVTBits) {
5145 Hi = DAG.getConstant(0, NVT);
5147 Lo = DAG.getNode(ISD::OR, NVT,
5148 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5149 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5150 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5155 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5156 DAG.getConstant(NVTBits-1, ShTy));
5157 } else if (Cst > NVTBits) {
5158 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5159 DAG.getConstant(Cst-NVTBits, ShTy));
5160 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5161 DAG.getConstant(NVTBits-1, ShTy));
5162 } else if (Cst == NVTBits) {
5164 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5165 DAG.getConstant(NVTBits-1, ShTy));
5167 Lo = DAG.getNode(ISD::OR, NVT,
5168 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5169 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5170 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5176 // Okay, the shift amount isn't constant. However, if we can tell that it is
5177 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5178 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5179 APInt KnownZero, KnownOne;
5180 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5182 // If we know that if any of the high bits of the shift amount are one, then
5183 // we can do this as a couple of simple shifts.
5184 if (KnownOne.intersects(Mask)) {
5185 // Mask out the high bit, which we know is set.
5186 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5187 DAG.getConstant(~Mask, Amt.getValueType()));
5189 // Expand the incoming operand to be shifted, so that we have its parts
5191 ExpandOp(Op, InL, InH);
5194 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5195 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5198 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5199 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5202 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5203 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5204 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5209 // If we know that the high bits of the shift amount are all zero, then we can
5210 // do this as a couple of simple shifts.
5211 if ((KnownZero & Mask) == Mask) {
5213 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5214 DAG.getConstant(NVTBits, Amt.getValueType()),
5217 // Expand the incoming operand to be shifted, so that we have its parts
5219 ExpandOp(Op, InL, InH);
5222 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5223 Hi = DAG.getNode(ISD::OR, NVT,
5224 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5225 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5228 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5229 Lo = DAG.getNode(ISD::OR, NVT,
5230 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5231 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5234 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5235 Lo = DAG.getNode(ISD::OR, NVT,
5236 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5237 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5246 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5247 // does not fit into a register, return the lo part and set the hi part to the
5248 // by-reg argument. If it does fit into a single register, return the result
5249 // and leave the Hi part unset.
5250 SDOperand SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5251 bool isSigned, SDOperand &Hi) {
5252 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5253 // The input chain to this libcall is the entry node of the function.
5254 // Legalizing the call will automatically add the previous call to the
5256 SDOperand InChain = DAG.getEntryNode();
5258 TargetLowering::ArgListTy Args;
5259 TargetLowering::ArgListEntry Entry;
5260 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5261 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
5262 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
5263 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5264 Entry.isSExt = isSigned;
5265 Entry.isZExt = !isSigned;
5266 Args.push_back(Entry);
5268 SDOperand Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5269 TLI.getPointerTy());
5271 // Splice the libcall in wherever FindInputOutputChains tells us to.
5272 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
5273 std::pair<SDOperand,SDOperand> CallInfo =
5274 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, CallingConv::C,
5275 false, Callee, Args, DAG);
5277 // Legalize the call sequence, starting with the chain. This will advance
5278 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5279 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5280 LegalizeOp(CallInfo.second);
5282 switch (getTypeAction(CallInfo.first.getValueType())) {
5283 default: assert(0 && "Unknown thing");
5285 Result = CallInfo.first;
5288 ExpandOp(CallInfo.first, Result, Hi);
5295 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5297 SDOperand SelectionDAGLegalize::
5298 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
5299 MVT::ValueType SourceVT = Source.getValueType();
5300 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5302 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5303 if (!isSigned && SourceVT != MVT::i32) {
5304 // The integer value loaded will be incorrectly if the 'sign bit' of the
5305 // incoming integer is set. To handle this, we dynamically test to see if
5306 // it is set, and, if so, add a fudge factor.
5310 ExpandOp(Source, Lo, Hi);
5311 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5313 // The comparison for the sign bit will use the entire operand.
5317 // If this is unsigned, and not supported, first perform the conversion to
5318 // signed, then adjust the result if the sign bit is set.
5319 SDOperand SignedConv = ExpandIntToFP(true, DestTy, Source);
5321 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5322 DAG.getConstant(0, Hi.getValueType()),
5324 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5325 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5326 SignSet, Four, Zero);
5327 uint64_t FF = 0x5f800000ULL;
5328 if (TLI.isLittleEndian()) FF <<= 32;
5329 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5331 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5332 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5333 SDOperand FudgeInReg;
5334 if (DestTy == MVT::f32)
5335 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5336 PseudoSourceValue::getConstantPool(), 0);
5337 else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
5338 // FIXME: Avoid the extend by construction the right constantpool?
5339 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
5341 PseudoSourceValue::getConstantPool(), 0,
5344 assert(0 && "Unexpected conversion");
5346 MVT::ValueType SCVT = SignedConv.getValueType();
5347 if (SCVT != DestTy) {
5348 // Destination type needs to be expanded as well. The FADD now we are
5349 // constructing will be expanded into a libcall.
5350 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
5351 assert(MVT::getSizeInBits(SCVT) * 2 == MVT::getSizeInBits(DestTy));
5352 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
5353 SignedConv, SignedConv.getValue(1));
5355 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
5357 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
5360 // Check to see if the target has a custom way to lower this. If so, use it.
5361 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
5362 default: assert(0 && "This action not implemented for this operation!");
5363 case TargetLowering::Legal:
5364 case TargetLowering::Expand:
5365 break; // This case is handled below.
5366 case TargetLowering::Custom: {
5367 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
5370 return LegalizeOp(NV);
5371 break; // The target decided this was legal after all
5375 // Expand the source, then glue it back together for the call. We must expand
5376 // the source in case it is shared (this pass of legalize must traverse it).
5378 SDOperand SrcLo, SrcHi;
5379 ExpandOp(Source, SrcLo, SrcHi);
5380 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
5384 if (SourceVT == MVT::i32) {
5385 if (DestTy == MVT::f32)
5386 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5388 assert(DestTy == MVT::f64 && "Unknown fp value type!");
5389 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5391 } else if (SourceVT == MVT::i64) {
5392 if (DestTy == MVT::f32)
5393 LC = RTLIB::SINTTOFP_I64_F32;
5394 else if (DestTy == MVT::f64)
5395 LC = RTLIB::SINTTOFP_I64_F64;
5396 else if (DestTy == MVT::f80)
5397 LC = RTLIB::SINTTOFP_I64_F80;
5399 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5400 LC = RTLIB::SINTTOFP_I64_PPCF128;
5402 } else if (SourceVT == MVT::i128) {
5403 if (DestTy == MVT::f32)
5404 LC = RTLIB::SINTTOFP_I128_F32;
5405 else if (DestTy == MVT::f64)
5406 LC = RTLIB::SINTTOFP_I128_F64;
5407 else if (DestTy == MVT::f80)
5408 LC = RTLIB::SINTTOFP_I128_F80;
5410 assert(DestTy == MVT::ppcf128 && "Unknown fp value type!");
5411 LC = RTLIB::SINTTOFP_I128_PPCF128;
5414 assert(0 && "Unknown int value type");
5417 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
5418 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
5420 SDOperand Result = ExpandLibCall(LC, Source.Val, isSigned, HiPart);
5421 if (Result.getValueType() != DestTy && HiPart.Val)
5422 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
5426 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
5427 /// INT_TO_FP operation of the specified operand when the target requests that
5428 /// we expand it. At this point, we know that the result and operand types are
5429 /// legal for the target.
5430 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
5432 MVT::ValueType DestVT) {
5433 if (Op0.getValueType() == MVT::i32) {
5434 // simple 32-bit [signed|unsigned] integer to float/double expansion
5436 // Get the stack frame index of a 8 byte buffer.
5437 SDOperand StackSlot = DAG.CreateStackTemporary(MVT::f64);
5439 // word offset constant for Hi/Lo address computation
5440 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
5441 // set up Hi and Lo (into buffer) address based on endian
5442 SDOperand Hi = StackSlot;
5443 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
5444 if (TLI.isLittleEndian())
5447 // if signed map to unsigned space
5448 SDOperand Op0Mapped;
5450 // constant used to invert sign bit (signed to unsigned mapping)
5451 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
5452 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
5456 // store the lo of the constructed double - based on integer input
5457 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
5458 Op0Mapped, Lo, NULL, 0);
5459 // initial hi portion of constructed double
5460 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
5461 // store the hi of the constructed double - biased exponent
5462 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
5463 // load the constructed double
5464 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
5465 // FP constant to bias correct the final result
5466 SDOperand Bias = DAG.getConstantFP(isSigned ?
5467 BitsToDouble(0x4330000080000000ULL)
5468 : BitsToDouble(0x4330000000000000ULL),
5470 // subtract the bias
5471 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
5474 // handle final rounding
5475 if (DestVT == MVT::f64) {
5478 } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
5479 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
5480 DAG.getIntPtrConstant(0));
5481 } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
5482 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
5486 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
5487 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
5489 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
5490 DAG.getConstant(0, Op0.getValueType()),
5492 SDOperand Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5493 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5494 SignSet, Four, Zero);
5496 // If the sign bit of the integer is set, the large number will be treated
5497 // as a negative number. To counteract this, the dynamic code adds an
5498 // offset depending on the data type.
5500 switch (Op0.getValueType()) {
5501 default: assert(0 && "Unsupported integer type!");
5502 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
5503 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
5504 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
5505 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
5507 if (TLI.isLittleEndian()) FF <<= 32;
5508 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5510 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5511 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5512 SDOperand FudgeInReg;
5513 if (DestVT == MVT::f32)
5514 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5515 PseudoSourceValue::getConstantPool(), 0);
5518 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
5519 DAG.getEntryNode(), CPIdx,
5520 PseudoSourceValue::getConstantPool(), 0,
5524 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
5527 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
5528 /// *INT_TO_FP operation of the specified operand when the target requests that
5529 /// we promote it. At this point, we know that the result and operand types are
5530 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
5531 /// operation that takes a larger input.
5532 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
5533 MVT::ValueType DestVT,
5535 // First step, figure out the appropriate *INT_TO_FP operation to use.
5536 MVT::ValueType NewInTy = LegalOp.getValueType();
5538 unsigned OpToUse = 0;
5540 // Scan for the appropriate larger type to use.
5542 NewInTy = (MVT::ValueType)(NewInTy+1);
5543 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
5545 // If the target supports SINT_TO_FP of this type, use it.
5546 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
5548 case TargetLowering::Legal:
5549 if (!TLI.isTypeLegal(NewInTy))
5550 break; // Can't use this datatype.
5552 case TargetLowering::Custom:
5553 OpToUse = ISD::SINT_TO_FP;
5557 if (isSigned) continue;
5559 // If the target supports UINT_TO_FP of this type, use it.
5560 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
5562 case TargetLowering::Legal:
5563 if (!TLI.isTypeLegal(NewInTy))
5564 break; // Can't use this datatype.
5566 case TargetLowering::Custom:
5567 OpToUse = ISD::UINT_TO_FP;
5572 // Otherwise, try a larger type.
5575 // Okay, we found the operation and type to use. Zero extend our input to the
5576 // desired type then run the operation on it.
5577 return DAG.getNode(OpToUse, DestVT,
5578 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
5582 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
5583 /// FP_TO_*INT operation of the specified operand when the target requests that
5584 /// we promote it. At this point, we know that the result and operand types are
5585 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
5586 /// operation that returns a larger result.
5587 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
5588 MVT::ValueType DestVT,
5590 // First step, figure out the appropriate FP_TO*INT operation to use.
5591 MVT::ValueType NewOutTy = DestVT;
5593 unsigned OpToUse = 0;
5595 // Scan for the appropriate larger type to use.
5597 NewOutTy = (MVT::ValueType)(NewOutTy+1);
5598 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
5600 // If the target supports FP_TO_SINT returning this type, use it.
5601 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
5603 case TargetLowering::Legal:
5604 if (!TLI.isTypeLegal(NewOutTy))
5605 break; // Can't use this datatype.
5607 case TargetLowering::Custom:
5608 OpToUse = ISD::FP_TO_SINT;
5613 // If the target supports FP_TO_UINT of this type, use it.
5614 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
5616 case TargetLowering::Legal:
5617 if (!TLI.isTypeLegal(NewOutTy))
5618 break; // Can't use this datatype.
5620 case TargetLowering::Custom:
5621 OpToUse = ISD::FP_TO_UINT;
5626 // Otherwise, try a larger type.
5630 // Okay, we found the operation and type to use.
5631 SDOperand Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
5633 // If the operation produces an invalid type, it must be custom lowered. Use
5634 // the target lowering hooks to expand it. Just keep the low part of the
5635 // expanded operation, we know that we're truncating anyway.
5636 if (getTypeAction(NewOutTy) == Expand) {
5637 Operation = SDOperand(TLI.ExpandOperationResult(Operation.Val, DAG), 0);
5638 assert(Operation.Val && "Didn't return anything");
5641 // Truncate the result of the extended FP_TO_*INT operation to the desired
5643 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
5646 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
5648 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
5649 MVT::ValueType VT = Op.getValueType();
5650 MVT::ValueType SHVT = TLI.getShiftAmountTy();
5651 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
5653 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
5655 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5656 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5657 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
5659 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5660 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5661 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5662 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5663 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
5664 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
5665 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5666 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5667 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5669 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
5670 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
5671 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
5672 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
5673 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
5674 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
5675 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
5676 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
5677 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
5678 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
5679 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
5680 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
5681 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
5682 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
5683 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
5684 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
5685 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
5686 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
5687 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
5688 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
5689 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
5693 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
5695 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
5697 default: assert(0 && "Cannot expand this yet!");
5699 static const uint64_t mask[6] = {
5700 0x5555555555555555ULL, 0x3333333333333333ULL,
5701 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
5702 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
5704 MVT::ValueType VT = Op.getValueType();
5705 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5706 unsigned len = MVT::getSizeInBits(VT);
5707 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5708 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
5709 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
5710 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5711 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
5712 DAG.getNode(ISD::AND, VT,
5713 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
5718 // for now, we do this:
5719 // x = x | (x >> 1);
5720 // x = x | (x >> 2);
5722 // x = x | (x >>16);
5723 // x = x | (x >>32); // for 64-bit input
5724 // return popcount(~x);
5726 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
5727 MVT::ValueType VT = Op.getValueType();
5728 MVT::ValueType ShVT = TLI.getShiftAmountTy();
5729 unsigned len = MVT::getSizeInBits(VT);
5730 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
5731 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
5732 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
5734 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
5735 return DAG.getNode(ISD::CTPOP, VT, Op);
5738 // for now, we use: { return popcount(~x & (x - 1)); }
5739 // unless the target has ctlz but not ctpop, in which case we use:
5740 // { return 32 - nlz(~x & (x-1)); }
5741 // see also http://www.hackersdelight.org/HDcode/ntz.cc
5742 MVT::ValueType VT = Op.getValueType();
5743 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
5744 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
5745 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
5746 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
5747 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
5748 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
5749 TLI.isOperationLegal(ISD::CTLZ, VT))
5750 return DAG.getNode(ISD::SUB, VT,
5751 DAG.getConstant(MVT::getSizeInBits(VT), VT),
5752 DAG.getNode(ISD::CTLZ, VT, Tmp3));
5753 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
5758 /// ExpandOp - Expand the specified SDOperand into its two component pieces
5759 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
5760 /// LegalizeNodes map is filled in for any results that are not expanded, the
5761 /// ExpandedNodes map is filled in for any results that are expanded, and the
5762 /// Lo/Hi values are returned.
5763 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
5764 MVT::ValueType VT = Op.getValueType();
5765 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
5766 SDNode *Node = Op.Val;
5767 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
5768 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
5769 MVT::isVector(VT)) &&
5770 "Cannot expand to FP value or to larger int value!");
5772 // See if we already expanded it.
5773 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5774 = ExpandedNodes.find(Op);
5775 if (I != ExpandedNodes.end()) {
5776 Lo = I->second.first;
5777 Hi = I->second.second;
5781 switch (Node->getOpcode()) {
5782 case ISD::CopyFromReg:
5783 assert(0 && "CopyFromReg must be legal!");
5784 case ISD::FP_ROUND_INREG:
5785 if (VT == MVT::ppcf128 &&
5786 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
5787 TargetLowering::Custom) {
5788 SDOperand SrcLo, SrcHi, Src;
5789 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
5790 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
5791 SDOperand Result = TLI.LowerOperation(
5792 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
5793 assert(Result.Val->getOpcode() == ISD::BUILD_PAIR);
5794 Lo = Result.Val->getOperand(0);
5795 Hi = Result.Val->getOperand(1);
5801 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
5803 assert(0 && "Do not know how to expand this operator!");
5805 case ISD::EXTRACT_ELEMENT:
5806 ExpandOp(Node->getOperand(0), Lo, Hi);
5807 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
5808 return ExpandOp(Hi, Lo, Hi);
5809 return ExpandOp(Lo, Lo, Hi);
5810 case ISD::EXTRACT_VECTOR_ELT:
5811 assert(VT==MVT::i64 && "Do not know how to expand this operator!");
5812 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
5813 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
5814 return ExpandOp(Lo, Lo, Hi);
5816 NVT = TLI.getTypeToExpandTo(VT);
5817 Lo = DAG.getNode(ISD::UNDEF, NVT);
5818 Hi = DAG.getNode(ISD::UNDEF, NVT);
5820 case ISD::Constant: {
5821 unsigned NVTBits = MVT::getSizeInBits(NVT);
5822 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
5823 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
5824 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
5827 case ISD::ConstantFP: {
5828 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
5829 if (CFP->getValueType(0) == MVT::ppcf128) {
5830 APInt api = CFP->getValueAPF().convertToAPInt();
5831 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
5833 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
5837 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
5838 if (getTypeAction(Lo.getValueType()) == Expand)
5839 ExpandOp(Lo, Lo, Hi);
5842 case ISD::BUILD_PAIR:
5843 // Return the operands.
5844 Lo = Node->getOperand(0);
5845 Hi = Node->getOperand(1);
5848 case ISD::MERGE_VALUES:
5849 if (Node->getNumValues() == 1) {
5850 ExpandOp(Op.getOperand(0), Lo, Hi);
5853 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
5854 assert(Op.ResNo == 0 && Node->getNumValues() == 2 &&
5855 Op.getValue(1).getValueType() == MVT::Other &&
5856 "unhandled MERGE_VALUES");
5857 ExpandOp(Op.getOperand(0), Lo, Hi);
5858 // Remember that we legalized the chain.
5859 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
5862 case ISD::SIGN_EXTEND_INREG:
5863 ExpandOp(Node->getOperand(0), Lo, Hi);
5864 // sext_inreg the low part if needed.
5865 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
5867 // The high part gets the sign extension from the lo-part. This handles
5868 // things like sextinreg V:i64 from i8.
5869 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
5870 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
5871 TLI.getShiftAmountTy()));
5875 ExpandOp(Node->getOperand(0), Lo, Hi);
5876 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
5877 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
5883 ExpandOp(Node->getOperand(0), Lo, Hi);
5884 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
5885 DAG.getNode(ISD::CTPOP, NVT, Lo),
5886 DAG.getNode(ISD::CTPOP, NVT, Hi));
5887 Hi = DAG.getConstant(0, NVT);
5891 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
5892 ExpandOp(Node->getOperand(0), Lo, Hi);
5893 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5894 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
5895 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
5897 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
5898 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
5900 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
5901 Hi = DAG.getConstant(0, NVT);
5906 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
5907 ExpandOp(Node->getOperand(0), Lo, Hi);
5908 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
5909 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
5910 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
5912 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
5913 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
5915 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
5916 Hi = DAG.getConstant(0, NVT);
5921 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
5922 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
5923 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
5924 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
5926 // Remember that we legalized the chain.
5927 Hi = LegalizeOp(Hi);
5928 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
5929 if (TLI.isBigEndian())
5935 LoadSDNode *LD = cast<LoadSDNode>(Node);
5936 SDOperand Ch = LD->getChain(); // Legalize the chain.
5937 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
5938 ISD::LoadExtType ExtType = LD->getExtensionType();
5939 int SVOffset = LD->getSrcValueOffset();
5940 unsigned Alignment = LD->getAlignment();
5941 bool isVolatile = LD->isVolatile();
5943 if (ExtType == ISD::NON_EXTLOAD) {
5944 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5945 isVolatile, Alignment);
5946 if (VT == MVT::f32 || VT == MVT::f64) {
5947 // f32->i32 or f64->i64 one to one expansion.
5948 // Remember that we legalized the chain.
5949 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5950 // Recursively expand the new load.
5951 if (getTypeAction(NVT) == Expand)
5952 ExpandOp(Lo, Lo, Hi);
5956 // Increment the pointer to the other half.
5957 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
5958 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5959 DAG.getIntPtrConstant(IncrementSize));
5960 SVOffset += IncrementSize;
5961 Alignment = MinAlign(Alignment, IncrementSize);
5962 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
5963 isVolatile, Alignment);
5965 // Build a factor node to remember that this load is independent of the
5967 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5970 // Remember that we legalized the chain.
5971 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5972 if (TLI.isBigEndian())
5975 MVT::ValueType EVT = LD->getMemoryVT();
5977 if ((VT == MVT::f64 && EVT == MVT::f32) ||
5978 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
5979 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
5980 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
5981 SVOffset, isVolatile, Alignment);
5982 // Remember that we legalized the chain.
5983 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
5984 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
5989 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
5990 SVOffset, isVolatile, Alignment);
5992 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
5993 SVOffset, EVT, isVolatile,
5996 // Remember that we legalized the chain.
5997 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
5999 if (ExtType == ISD::SEXTLOAD) {
6000 // The high part is obtained by SRA'ing all but one of the bits of the
6002 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6003 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6004 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6005 } else if (ExtType == ISD::ZEXTLOAD) {
6006 // The high part is just a zero.
6007 Hi = DAG.getConstant(0, NVT);
6008 } else /* if (ExtType == ISD::EXTLOAD) */ {
6009 // The high part is undefined.
6010 Hi = DAG.getNode(ISD::UNDEF, NVT);
6017 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6018 SDOperand LL, LH, RL, RH;
6019 ExpandOp(Node->getOperand(0), LL, LH);
6020 ExpandOp(Node->getOperand(1), RL, RH);
6021 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6022 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6026 SDOperand LL, LH, RL, RH;
6027 ExpandOp(Node->getOperand(1), LL, LH);
6028 ExpandOp(Node->getOperand(2), RL, RH);
6029 if (getTypeAction(NVT) == Expand)
6030 NVT = TLI.getTypeToExpandTo(NVT);
6031 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6033 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6036 case ISD::SELECT_CC: {
6037 SDOperand TL, TH, FL, FH;
6038 ExpandOp(Node->getOperand(2), TL, TH);
6039 ExpandOp(Node->getOperand(3), FL, FH);
6040 if (getTypeAction(NVT) == Expand)
6041 NVT = TLI.getTypeToExpandTo(NVT);
6042 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6043 Node->getOperand(1), TL, FL, Node->getOperand(4));
6045 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6046 Node->getOperand(1), TH, FH, Node->getOperand(4));
6049 case ISD::ANY_EXTEND:
6050 // The low part is any extension of the input (which degenerates to a copy).
6051 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6052 // The high part is undefined.
6053 Hi = DAG.getNode(ISD::UNDEF, NVT);
6055 case ISD::SIGN_EXTEND: {
6056 // The low part is just a sign extension of the input (which degenerates to
6058 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6060 // The high part is obtained by SRA'ing all but one of the bits of the lo
6062 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
6063 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6064 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6067 case ISD::ZERO_EXTEND:
6068 // The low part is just a zero extension of the input (which degenerates to
6070 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6072 // The high part is just a zero.
6073 Hi = DAG.getConstant(0, NVT);
6076 case ISD::TRUNCATE: {
6077 // The input value must be larger than this value. Expand *it*.
6079 ExpandOp(Node->getOperand(0), NewLo, Hi);
6081 // The low part is now either the right size, or it is closer. If not the
6082 // right size, make an illegal truncate so we recursively expand it.
6083 if (NewLo.getValueType() != Node->getValueType(0))
6084 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6085 ExpandOp(NewLo, Lo, Hi);
6089 case ISD::BIT_CONVERT: {
6091 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6092 // If the target wants to, allow it to lower this itself.
6093 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6094 case Expand: assert(0 && "cannot expand FP!");
6095 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6096 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6098 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6101 // f32 / f64 must be expanded to i32 / i64.
6102 if (VT == MVT::f32 || VT == MVT::f64) {
6103 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6104 if (getTypeAction(NVT) == Expand)
6105 ExpandOp(Lo, Lo, Hi);
6109 // If source operand will be expanded to the same type as VT, i.e.
6110 // i64 <- f64, i32 <- f32, expand the source operand instead.
6111 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
6112 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6113 ExpandOp(Node->getOperand(0), Lo, Hi);
6117 // Turn this into a load/store pair by default.
6119 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6121 ExpandOp(Tmp, Lo, Hi);
6125 case ISD::READCYCLECOUNTER: {
6126 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6127 TargetLowering::Custom &&
6128 "Must custom expand ReadCycleCounter");
6129 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6130 assert(Tmp.Val && "Node must be custom expanded!");
6131 ExpandOp(Tmp.getValue(0), Lo, Hi);
6132 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6133 LegalizeOp(Tmp.getValue(1)));
6137 case ISD::ATOMIC_LCS: {
6138 SDOperand Tmp = TLI.LowerOperation(Op, DAG);
6139 assert(Tmp.Val && "Node must be custom expanded!");
6140 ExpandOp(Tmp.getValue(0), Lo, Hi);
6141 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
6142 LegalizeOp(Tmp.getValue(1)));
6148 // These operators cannot be expanded directly, emit them as calls to
6149 // library functions.
6150 case ISD::FP_TO_SINT: {
6151 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6153 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6154 case Expand: assert(0 && "cannot expand FP!");
6155 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6156 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6159 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6161 // Now that the custom expander is done, expand the result, which is still
6164 ExpandOp(Op, Lo, Hi);
6169 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6170 if (VT == MVT::i64) {
6171 if (Node->getOperand(0).getValueType() == MVT::f32)
6172 LC = RTLIB::FPTOSINT_F32_I64;
6173 else if (Node->getOperand(0).getValueType() == MVT::f64)
6174 LC = RTLIB::FPTOSINT_F64_I64;
6175 else if (Node->getOperand(0).getValueType() == MVT::f80)
6176 LC = RTLIB::FPTOSINT_F80_I64;
6177 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6178 LC = RTLIB::FPTOSINT_PPCF128_I64;
6179 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6180 } else if (VT == MVT::i128) {
6181 if (Node->getOperand(0).getValueType() == MVT::f32)
6182 LC = RTLIB::FPTOSINT_F32_I128;
6183 else if (Node->getOperand(0).getValueType() == MVT::f64)
6184 LC = RTLIB::FPTOSINT_F64_I128;
6185 else if (Node->getOperand(0).getValueType() == MVT::f80)
6186 LC = RTLIB::FPTOSINT_F80_I128;
6187 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6188 LC = RTLIB::FPTOSINT_PPCF128_I128;
6189 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6191 assert(0 && "Unexpected uint-to-fp conversion!");
6196 case ISD::FP_TO_UINT: {
6197 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6199 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6200 case Expand: assert(0 && "cannot expand FP!");
6201 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6202 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6205 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6207 // Now that the custom expander is done, expand the result.
6209 ExpandOp(Op, Lo, Hi);
6214 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6215 if (VT == MVT::i64) {
6216 if (Node->getOperand(0).getValueType() == MVT::f32)
6217 LC = RTLIB::FPTOUINT_F32_I64;
6218 else if (Node->getOperand(0).getValueType() == MVT::f64)
6219 LC = RTLIB::FPTOUINT_F64_I64;
6220 else if (Node->getOperand(0).getValueType() == MVT::f80)
6221 LC = RTLIB::FPTOUINT_F80_I64;
6222 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6223 LC = RTLIB::FPTOUINT_PPCF128_I64;
6224 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6225 } else if (VT == MVT::i128) {
6226 if (Node->getOperand(0).getValueType() == MVT::f32)
6227 LC = RTLIB::FPTOUINT_F32_I128;
6228 else if (Node->getOperand(0).getValueType() == MVT::f64)
6229 LC = RTLIB::FPTOUINT_F64_I128;
6230 else if (Node->getOperand(0).getValueType() == MVT::f80)
6231 LC = RTLIB::FPTOUINT_F80_I128;
6232 else if (Node->getOperand(0).getValueType() == MVT::ppcf128)
6233 LC = RTLIB::FPTOUINT_PPCF128_I128;
6234 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6236 assert(0 && "Unexpected uint-to-fp conversion!");
6242 // If the target wants custom lowering, do so.
6243 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6244 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6245 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6246 Op = TLI.LowerOperation(Op, DAG);
6248 // Now that the custom expander is done, expand the result, which is
6250 ExpandOp(Op, Lo, Hi);
6255 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6256 // this X << 1 as X+X.
6257 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6258 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6259 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6260 SDOperand LoOps[2], HiOps[3];
6261 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6262 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6263 LoOps[1] = LoOps[0];
6264 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6266 HiOps[1] = HiOps[0];
6267 HiOps[2] = Lo.getValue(1);
6268 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6273 // If we can emit an efficient shift operation, do so now.
6274 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6277 // If this target supports SHL_PARTS, use it.
6278 TargetLowering::LegalizeAction Action =
6279 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6280 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6281 Action == TargetLowering::Custom) {
6282 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6286 // Otherwise, emit a libcall.
6287 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6292 // If the target wants custom lowering, do so.
6293 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6294 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6295 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6296 Op = TLI.LowerOperation(Op, DAG);
6298 // Now that the custom expander is done, expand the result, which is
6300 ExpandOp(Op, Lo, Hi);
6305 // If we can emit an efficient shift operation, do so now.
6306 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6309 // If this target supports SRA_PARTS, use it.
6310 TargetLowering::LegalizeAction Action =
6311 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6312 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6313 Action == TargetLowering::Custom) {
6314 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6318 // Otherwise, emit a libcall.
6319 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6324 // If the target wants custom lowering, do so.
6325 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
6326 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6327 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6328 Op = TLI.LowerOperation(Op, DAG);
6330 // Now that the custom expander is done, expand the result, which is
6332 ExpandOp(Op, Lo, Hi);
6337 // If we can emit an efficient shift operation, do so now.
6338 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6341 // If this target supports SRL_PARTS, use it.
6342 TargetLowering::LegalizeAction Action =
6343 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6344 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6345 Action == TargetLowering::Custom) {
6346 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6350 // Otherwise, emit a libcall.
6351 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6357 // If the target wants to custom expand this, let them.
6358 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6359 TargetLowering::Custom) {
6360 Op = TLI.LowerOperation(Op, DAG);
6362 ExpandOp(Op, Lo, Hi);
6367 // Expand the subcomponents.
6368 SDOperand LHSL, LHSH, RHSL, RHSH;
6369 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6370 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6371 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6372 SDOperand LoOps[2], HiOps[3];
6377 if (Node->getOpcode() == ISD::ADD) {
6378 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6379 HiOps[2] = Lo.getValue(1);
6380 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6382 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6383 HiOps[2] = Lo.getValue(1);
6384 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6391 // Expand the subcomponents.
6392 SDOperand LHSL, LHSH, RHSL, RHSH;
6393 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6394 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6395 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6396 SDOperand LoOps[2] = { LHSL, RHSL };
6397 SDOperand HiOps[3] = { LHSH, RHSH };
6399 if (Node->getOpcode() == ISD::ADDC) {
6400 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6401 HiOps[2] = Lo.getValue(1);
6402 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6404 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
6405 HiOps[2] = Lo.getValue(1);
6406 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
6408 // Remember that we legalized the flag.
6409 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6414 // Expand the subcomponents.
6415 SDOperand LHSL, LHSH, RHSL, RHSH;
6416 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6417 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6418 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
6419 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
6420 SDOperand HiOps[3] = { LHSH, RHSH };
6422 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
6423 HiOps[2] = Lo.getValue(1);
6424 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
6426 // Remember that we legalized the flag.
6427 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
6431 // If the target wants to custom expand this, let them.
6432 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
6433 SDOperand New = TLI.LowerOperation(Op, DAG);
6435 ExpandOp(New, Lo, Hi);
6440 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
6441 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
6442 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
6443 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
6444 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
6445 SDOperand LL, LH, RL, RH;
6446 ExpandOp(Node->getOperand(0), LL, LH);
6447 ExpandOp(Node->getOperand(1), RL, RH);
6448 unsigned OuterBitSize = Op.getValueSizeInBits();
6449 unsigned InnerBitSize = RH.getValueSizeInBits();
6450 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
6451 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
6452 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
6453 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
6454 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
6455 // The inputs are both zero-extended.
6457 // We can emit a umul_lohi.
6458 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6459 Hi = SDOperand(Lo.Val, 1);
6463 // We can emit a mulhu+mul.
6464 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6465 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6469 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
6470 // The input values are both sign-extended.
6472 // We can emit a smul_lohi.
6473 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
6474 Hi = SDOperand(Lo.Val, 1);
6478 // We can emit a mulhs+mul.
6479 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6480 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
6485 // Lo,Hi = umul LHS, RHS.
6486 SDOperand UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
6487 DAG.getVTList(NVT, NVT), LL, RL);
6489 Hi = UMulLOHI.getValue(1);
6490 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6491 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6492 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6493 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6497 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
6498 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
6499 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
6500 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
6501 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
6502 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
6507 // If nothing else, we can make a libcall.
6508 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
6512 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
6515 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
6518 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
6521 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
6525 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
6528 RTLIB::ADD_PPCF128),
6532 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
6535 RTLIB::SUB_PPCF128),
6539 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
6542 RTLIB::MUL_PPCF128),
6546 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
6549 RTLIB::DIV_PPCF128),
6552 case ISD::FP_EXTEND:
6553 if (VT == MVT::ppcf128) {
6554 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
6555 Node->getOperand(0).getValueType()==MVT::f64);
6556 const uint64_t zero = 0;
6557 if (Node->getOperand(0).getValueType()==MVT::f32)
6558 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
6560 Hi = Node->getOperand(0);
6561 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6564 Lo = ExpandLibCall(RTLIB::FPEXT_F32_F64, Node, true, Hi);
6567 Lo = ExpandLibCall(RTLIB::FPROUND_F64_F32, Node, true, Hi);
6570 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::POWI_F32,
6573 RTLIB::POWI_PPCF128),
6579 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
6580 switch(Node->getOpcode()) {
6582 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
6583 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
6586 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
6587 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
6590 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
6591 RTLIB::COS_F80, RTLIB::COS_PPCF128);
6593 default: assert(0 && "Unreachable!");
6595 Lo = ExpandLibCall(LC, Node, false, Hi);
6599 if (VT == MVT::ppcf128) {
6601 ExpandOp(Node->getOperand(0), Lo, Tmp);
6602 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
6603 // lo = hi==fabs(hi) ? lo : -lo;
6604 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
6605 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
6606 DAG.getCondCode(ISD::SETEQ));
6609 SDOperand Mask = (VT == MVT::f64)
6610 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
6611 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
6612 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6613 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6614 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
6615 if (getTypeAction(NVT) == Expand)
6616 ExpandOp(Lo, Lo, Hi);
6620 if (VT == MVT::ppcf128) {
6621 ExpandOp(Node->getOperand(0), Lo, Hi);
6622 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
6623 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
6626 SDOperand Mask = (VT == MVT::f64)
6627 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
6628 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
6629 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
6630 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6631 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
6632 if (getTypeAction(NVT) == Expand)
6633 ExpandOp(Lo, Lo, Hi);
6636 case ISD::FCOPYSIGN: {
6637 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
6638 if (getTypeAction(NVT) == Expand)
6639 ExpandOp(Lo, Lo, Hi);
6642 case ISD::SINT_TO_FP:
6643 case ISD::UINT_TO_FP: {
6644 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
6645 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
6647 // Promote the operand if needed. Do this before checking for
6648 // ppcf128 so conversions of i16 and i8 work.
6649 if (getTypeAction(SrcVT) == Promote) {
6650 SDOperand Tmp = PromoteOp(Node->getOperand(0));
6652 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
6653 DAG.getValueType(SrcVT))
6654 : DAG.getZeroExtendInReg(Tmp, SrcVT);
6655 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
6656 SrcVT = Node->getOperand(0).getValueType();
6659 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
6660 static const uint64_t zero = 0;
6662 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6663 Node->getOperand(0)));
6664 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6666 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
6667 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
6668 Node->getOperand(0)));
6669 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
6670 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6671 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
6672 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6673 DAG.getConstant(0, MVT::i32),
6674 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6676 APFloat(APInt(128, 2, TwoE32)),
6679 DAG.getCondCode(ISD::SETLT)),
6684 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
6685 // si64->ppcf128 done by libcall, below
6686 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
6687 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
6689 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
6690 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
6691 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
6692 DAG.getConstant(0, MVT::i64),
6693 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
6695 APFloat(APInt(128, 2, TwoE64)),
6698 DAG.getCondCode(ISD::SETLT)),
6703 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
6704 Node->getOperand(0));
6705 if (getTypeAction(Lo.getValueType()) == Expand)
6706 // float to i32 etc. can be 'expanded' to a single node.
6707 ExpandOp(Lo, Lo, Hi);
6712 // Make sure the resultant values have been legalized themselves, unless this
6713 // is a type that requires multi-step expansion.
6714 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
6715 Lo = LegalizeOp(Lo);
6717 // Don't legalize the high part if it is expanded to a single node.
6718 Hi = LegalizeOp(Hi);
6721 // Remember in a map if the values will be reused later.
6722 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
6723 assert(isNew && "Value already expanded?!?");
6726 /// SplitVectorOp - Given an operand of vector type, break it down into
6727 /// two smaller values, still of vector type.
6728 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
6730 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
6731 SDNode *Node = Op.Val;
6732 unsigned NumElements = MVT::getVectorNumElements(Op.getValueType());
6733 assert(NumElements > 1 && "Cannot split a single element vector!");
6735 MVT::ValueType NewEltVT = MVT::getVectorElementType(Op.getValueType());
6737 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
6738 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
6740 MVT::ValueType NewVT_Lo = MVT::getVectorType(NewEltVT, NewNumElts_Lo);
6741 MVT::ValueType NewVT_Hi = MVT::getVectorType(NewEltVT, NewNumElts_Hi);
6743 // See if we already split it.
6744 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
6745 = SplitNodes.find(Op);
6746 if (I != SplitNodes.end()) {
6747 Lo = I->second.first;
6748 Hi = I->second.second;
6752 switch (Node->getOpcode()) {
6757 assert(0 && "Unhandled operation in SplitVectorOp!");
6759 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
6760 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
6762 case ISD::BUILD_PAIR:
6763 Lo = Node->getOperand(0);
6764 Hi = Node->getOperand(1);
6766 case ISD::INSERT_VECTOR_ELT: {
6767 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
6768 SplitVectorOp(Node->getOperand(0), Lo, Hi);
6769 unsigned Index = Idx->getValue();
6770 SDOperand ScalarOp = Node->getOperand(1);
6771 if (Index < NewNumElts_Lo)
6772 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
6773 DAG.getIntPtrConstant(Index));
6775 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
6776 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
6779 SDOperand Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
6780 Node->getOperand(1),
6781 Node->getOperand(2));
6782 SplitVectorOp(Tmp, Lo, Hi);
6785 case ISD::VECTOR_SHUFFLE: {
6786 // Build the low part.
6787 SDOperand Mask = Node->getOperand(2);
6788 SmallVector<SDOperand, 8> Ops;
6789 MVT::ValueType PtrVT = TLI.getPointerTy();
6791 // Insert all of the elements from the input that are needed. We use
6792 // buildvector of extractelement here because the input vectors will have
6793 // to be legalized, so this makes the code simpler.
6794 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
6795 SDOperand IdxNode = Mask.getOperand(i);
6796 if (IdxNode.getOpcode() == ISD::UNDEF) {
6797 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6800 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6801 SDOperand InVec = Node->getOperand(0);
6802 if (Idx >= NumElements) {
6803 InVec = Node->getOperand(1);
6806 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6807 DAG.getConstant(Idx, PtrVT)));
6809 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6812 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
6813 SDOperand IdxNode = Mask.getOperand(i);
6814 if (IdxNode.getOpcode() == ISD::UNDEF) {
6815 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
6818 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getValue();
6819 SDOperand InVec = Node->getOperand(0);
6820 if (Idx >= NumElements) {
6821 InVec = Node->getOperand(1);
6824 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
6825 DAG.getConstant(Idx, PtrVT)));
6827 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
6830 case ISD::BUILD_VECTOR: {
6831 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6832 Node->op_begin()+NewNumElts_Lo);
6833 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
6835 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
6837 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
6840 case ISD::CONCAT_VECTORS: {
6841 // FIXME: Handle non-power-of-two vectors?
6842 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
6843 if (NewNumSubvectors == 1) {
6844 Lo = Node->getOperand(0);
6845 Hi = Node->getOperand(1);
6847 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
6848 Node->op_begin()+NewNumSubvectors);
6849 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
6851 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
6853 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
6858 SDOperand Cond = Node->getOperand(0);
6860 SDOperand LL, LH, RL, RH;
6861 SplitVectorOp(Node->getOperand(1), LL, LH);
6862 SplitVectorOp(Node->getOperand(2), RL, RH);
6864 if (MVT::isVector(Cond.getValueType())) {
6865 // Handle a vector merge.
6867 SplitVectorOp(Cond, CL, CH);
6868 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
6869 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
6871 // Handle a simple select with vector operands.
6872 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
6873 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
6893 SDOperand LL, LH, RL, RH;
6894 SplitVectorOp(Node->getOperand(0), LL, LH);
6895 SplitVectorOp(Node->getOperand(1), RL, RH);
6897 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
6898 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
6903 SplitVectorOp(Node->getOperand(0), L, H);
6905 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
6906 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
6917 case ISD::FP_TO_SINT:
6918 case ISD::FP_TO_UINT:
6919 case ISD::SINT_TO_FP:
6920 case ISD::UINT_TO_FP: {
6922 SplitVectorOp(Node->getOperand(0), L, H);
6924 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
6925 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
6929 LoadSDNode *LD = cast<LoadSDNode>(Node);
6930 SDOperand Ch = LD->getChain();
6931 SDOperand Ptr = LD->getBasePtr();
6932 const Value *SV = LD->getSrcValue();
6933 int SVOffset = LD->getSrcValueOffset();
6934 unsigned Alignment = LD->getAlignment();
6935 bool isVolatile = LD->isVolatile();
6937 Lo = DAG.getLoad(NewVT_Lo, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6938 unsigned IncrementSize = NewNumElts_Lo * MVT::getSizeInBits(NewEltVT)/8;
6939 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6940 DAG.getIntPtrConstant(IncrementSize));
6941 SVOffset += IncrementSize;
6942 Alignment = MinAlign(Alignment, IncrementSize);
6943 Hi = DAG.getLoad(NewVT_Hi, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
6945 // Build a factor node to remember that this load is independent of the
6947 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6950 // Remember that we legalized the chain.
6951 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6954 case ISD::BIT_CONVERT: {
6955 // We know the result is a vector. The input may be either a vector or a
6957 SDOperand InOp = Node->getOperand(0);
6958 if (!MVT::isVector(InOp.getValueType()) ||
6959 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
6960 // The input is a scalar or single-element vector.
6961 // Lower to a store/load so that it can be split.
6962 // FIXME: this could be improved probably.
6963 SDOperand Ptr = DAG.CreateStackTemporary(InOp.getValueType());
6964 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(Ptr.Val);
6966 SDOperand St = DAG.getStore(DAG.getEntryNode(),
6968 PseudoSourceValue::getFixedStack(),
6970 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
6971 PseudoSourceValue::getFixedStack(),
6974 // Split the vector and convert each of the pieces now.
6975 SplitVectorOp(InOp, Lo, Hi);
6976 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
6977 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
6982 // Remember in a map if the values will be reused later.
6984 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
6985 assert(isNew && "Value already split?!?");
6989 /// ScalarizeVectorOp - Given an operand of single-element vector type
6990 /// (e.g. v1f32), convert it into the equivalent operation that returns a
6991 /// scalar (e.g. f32) value.
6992 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
6993 assert(MVT::isVector(Op.getValueType()) &&
6994 "Bad ScalarizeVectorOp invocation!");
6995 SDNode *Node = Op.Val;
6996 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
6997 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
6999 // See if we already scalarized it.
7000 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
7001 if (I != ScalarizedNodes.end()) return I->second;
7004 switch (Node->getOpcode()) {
7007 Node->dump(&DAG); cerr << "\n";
7009 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7026 Result = DAG.getNode(Node->getOpcode(),
7028 ScalarizeVectorOp(Node->getOperand(0)),
7029 ScalarizeVectorOp(Node->getOperand(1)));
7036 Result = DAG.getNode(Node->getOpcode(),
7038 ScalarizeVectorOp(Node->getOperand(0)));
7041 Result = DAG.getNode(Node->getOpcode(),
7043 ScalarizeVectorOp(Node->getOperand(0)),
7044 Node->getOperand(1));
7047 LoadSDNode *LD = cast<LoadSDNode>(Node);
7048 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7049 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7051 const Value *SV = LD->getSrcValue();
7052 int SVOffset = LD->getSrcValueOffset();
7053 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
7054 LD->isVolatile(), LD->getAlignment());
7056 // Remember that we legalized the chain.
7057 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7060 case ISD::BUILD_VECTOR:
7061 Result = Node->getOperand(0);
7063 case ISD::INSERT_VECTOR_ELT:
7064 // Returning the inserted scalar element.
7065 Result = Node->getOperand(1);
7067 case ISD::CONCAT_VECTORS:
7068 assert(Node->getOperand(0).getValueType() == NewVT &&
7069 "Concat of non-legal vectors not yet supported!");
7070 Result = Node->getOperand(0);
7072 case ISD::VECTOR_SHUFFLE: {
7073 // Figure out if the scalar is the LHS or RHS and return it.
7074 SDOperand EltNum = Node->getOperand(2).getOperand(0);
7075 if (cast<ConstantSDNode>(EltNum)->getValue())
7076 Result = ScalarizeVectorOp(Node->getOperand(1));
7078 Result = ScalarizeVectorOp(Node->getOperand(0));
7081 case ISD::EXTRACT_SUBVECTOR:
7082 Result = Node->getOperand(0);
7083 assert(Result.getValueType() == NewVT);
7085 case ISD::BIT_CONVERT:
7086 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
7089 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7090 ScalarizeVectorOp(Op.getOperand(1)),
7091 ScalarizeVectorOp(Op.getOperand(2)));
7095 if (TLI.isTypeLegal(NewVT))
7096 Result = LegalizeOp(Result);
7097 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7098 assert(isNew && "Value already scalarized?");
7103 // SelectionDAG::Legalize - This is the entry point for the file.
7105 void SelectionDAG::Legalize() {
7106 if (ViewLegalizeDAGs) viewGraph();
7108 /// run - This is the main entry point to this class.
7110 SelectionDAGLegalize(*this).LegalizeDAG();