1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/PseudoSourceValue.h"
20 #include "llvm/Target/TargetFrameInfo.h"
21 #include "llvm/Target/TargetLowering.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Target/TargetSubtarget.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/DerivedTypes.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/ADT/DenseMap.h"
33 #include "llvm/ADT/SmallVector.h"
34 #include "llvm/ADT/SmallPtrSet.h"
38 //===----------------------------------------------------------------------===//
39 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
40 /// hacks on it until the target machine can handle it. This involves
41 /// eliminating value sizes the machine cannot handle (promoting small sizes to
42 /// large sizes or splitting up large values into small values) as well as
43 /// eliminating operations the machine cannot handle.
45 /// This code also does a small amount of optimization and recognition of idioms
46 /// as part of its processing. For example, if a target does not support a
47 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
48 /// will attempt merge setcc and brc instructions into brcc's.
51 class VISIBILITY_HIDDEN SelectionDAGLegalize {
54 bool TypesNeedLegalizing;
56 // Libcall insertion helpers.
58 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
59 /// legalized. We use this to ensure that calls are properly serialized
60 /// against each other, including inserted libcalls.
61 SDValue LastCALLSEQ_END;
63 /// IsLegalizingCall - This member is used *only* for purposes of providing
64 /// helpful assertions that a libcall isn't created while another call is
65 /// being legalized (which could lead to non-serialized call sequences).
66 bool IsLegalizingCall;
69 Legal, // The target natively supports this operation.
70 Promote, // This operation should be executed in a larger type.
71 Expand // Try to expand this to other ops, otherwise use a libcall.
74 /// ValueTypeActions - This is a bitvector that contains two bits for each
75 /// value type, where the two bits correspond to the LegalizeAction enum.
76 /// This can be queried with "getTypeAction(VT)".
77 TargetLowering::ValueTypeActionImpl ValueTypeActions;
79 /// LegalizedNodes - For nodes that are of legal width, and that have more
80 /// than one use, this map indicates what regularized operand to use. This
81 /// allows us to avoid legalizing the same thing more than once.
82 DenseMap<SDValue, SDValue> LegalizedNodes;
84 /// PromotedNodes - For nodes that are below legal width, and that have more
85 /// than one use, this map indicates what promoted value to use. This allows
86 /// us to avoid promoting the same thing more than once.
87 DenseMap<SDValue, SDValue> PromotedNodes;
89 /// ExpandedNodes - For nodes that need to be expanded this map indicates
90 /// which operands are the expanded version of the input. This allows
91 /// us to avoid expanding the same node more than once.
92 DenseMap<SDValue, std::pair<SDValue, SDValue> > ExpandedNodes;
94 /// SplitNodes - For vector nodes that need to be split, this map indicates
95 /// which operands are the split version of the input. This allows us
96 /// to avoid splitting the same node more than once.
97 std::map<SDValue, std::pair<SDValue, SDValue> > SplitNodes;
99 /// ScalarizedNodes - For nodes that need to be converted from vector types to
100 /// scalar types, this contains the mapping of ones we have already
101 /// processed to the result.
102 std::map<SDValue, SDValue> ScalarizedNodes;
104 /// WidenNodes - For nodes that need to be widened from one vector type to
105 /// another, this contains the mapping of those that we have already widen.
106 /// This allows us to avoid widening more than once.
107 std::map<SDValue, SDValue> WidenNodes;
109 void AddLegalizedOperand(SDValue From, SDValue To) {
110 LegalizedNodes.insert(std::make_pair(From, To));
111 // If someone requests legalization of the new node, return itself.
113 LegalizedNodes.insert(std::make_pair(To, To));
115 void AddPromotedOperand(SDValue From, SDValue To) {
116 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
117 assert(isNew && "Got into the map somehow?");
119 // If someone requests legalization of the new node, return itself.
120 LegalizedNodes.insert(std::make_pair(To, To));
122 void AddWidenedOperand(SDValue From, SDValue To) {
123 bool isNew = WidenNodes.insert(std::make_pair(From, To)).second;
124 assert(isNew && "Got into the map somehow?");
126 // If someone requests legalization of the new node, return itself.
127 LegalizedNodes.insert(std::make_pair(To, To));
131 explicit SelectionDAGLegalize(SelectionDAG &DAG, bool TypesNeedLegalizing);
133 /// getTypeAction - Return how we should legalize values of this type, either
134 /// it is already legal or we need to expand it into multiple registers of
135 /// smaller integer type, or we need to promote it to a larger type.
136 LegalizeAction getTypeAction(MVT VT) const {
137 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
140 /// isTypeLegal - Return true if this type is legal on this target.
142 bool isTypeLegal(MVT VT) const {
143 return getTypeAction(VT) == Legal;
149 /// HandleOp - Legalize, Promote, or Expand the specified operand as
150 /// appropriate for its type.
151 void HandleOp(SDValue Op);
153 /// LegalizeOp - We know that the specified value has a legal type.
154 /// Recursively ensure that the operands have legal types, then return the
156 SDValue LegalizeOp(SDValue O);
158 /// UnrollVectorOp - We know that the given vector has a legal type, however
159 /// the operation it performs is not legal and is an operation that we have
160 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
161 /// operating on each element individually.
162 SDValue UnrollVectorOp(SDValue O);
164 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
165 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
166 /// is necessary to spill the vector being inserted into to memory, perform
167 /// the insert there, and then read the result back.
168 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
171 /// PromoteOp - Given an operation that produces a value in an invalid type,
172 /// promote it to compute the value into a larger type. The produced value
173 /// will have the correct bits for the low portion of the register, but no
174 /// guarantee is made about the top bits: it may be zero, sign-extended, or
176 SDValue PromoteOp(SDValue O);
178 /// ExpandOp - Expand the specified SDValue into its two component pieces
179 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
180 /// the LegalizedNodes map is filled in for any results that are not expanded,
181 /// the ExpandedNodes map is filled in for any results that are expanded, and
182 /// the Lo/Hi values are returned. This applies to integer types and Vector
184 void ExpandOp(SDValue O, SDValue &Lo, SDValue &Hi);
186 /// WidenVectorOp - Widen a vector operation to a wider type given by WidenVT
187 /// (e.g., v3i32 to v4i32). The produced value will have the correct value
188 /// for the existing elements but no guarantee is made about the new elements
189 /// at the end of the vector: it may be zero, ones, or garbage. This is useful
190 /// when we have an instruction operating on an illegal vector type and we
191 /// want to widen it to do the computation on a legal wider vector type.
192 SDValue WidenVectorOp(SDValue Op, MVT WidenVT);
194 /// SplitVectorOp - Given an operand of vector type, break it down into
195 /// two smaller values.
196 void SplitVectorOp(SDValue O, SDValue &Lo, SDValue &Hi);
198 /// ScalarizeVectorOp - Given an operand of single-element vector type
199 /// (e.g. v1f32), convert it into the equivalent operation that returns a
200 /// scalar (e.g. f32) value.
201 SDValue ScalarizeVectorOp(SDValue O);
203 /// Useful 16 element vector type that is used to pass operands for widening.
204 typedef SmallVector<SDValue, 16> SDValueVector;
206 /// LoadWidenVectorOp - Load a vector for a wider type. Returns true if
207 /// the LdChain contains a single load and false if it contains a token
208 /// factor for multiple loads. It takes
209 /// Result: location to return the result
210 /// LdChain: location to return the load chain
211 /// Op: load operation to widen
212 /// NVT: widen vector result type we want for the load
213 bool LoadWidenVectorOp(SDValue& Result, SDValue& LdChain,
214 SDValue Op, MVT NVT);
216 /// Helper genWidenVectorLoads - Helper function to generate a set of
217 /// loads to load a vector with a resulting wider type. It takes
218 /// LdChain: list of chains for the load we have generated
219 /// Chain: incoming chain for the ld vector
220 /// BasePtr: base pointer to load from
221 /// SV: memory disambiguation source value
222 /// SVOffset: memory disambiugation offset
223 /// Alignment: alignment of the memory
224 /// isVolatile: volatile load
225 /// LdWidth: width of memory that we want to load
226 /// ResType: the wider result result type for the resulting loaded vector
227 SDValue genWidenVectorLoads(SDValueVector& LdChain, SDValue Chain,
228 SDValue BasePtr, const Value *SV,
229 int SVOffset, unsigned Alignment,
230 bool isVolatile, unsigned LdWidth,
233 /// StoreWidenVectorOp - Stores a widen vector into non widen memory
234 /// location. It takes
235 /// ST: store node that we want to replace
236 /// Chain: incoming store chain
237 /// BasePtr: base address of where we want to store into
238 SDValue StoreWidenVectorOp(StoreSDNode *ST, SDValue Chain,
241 /// Helper genWidenVectorStores - Helper function to generate a set of
242 /// stores to store a widen vector into non widen memory
244 // StChain: list of chains for the stores we have generated
245 // Chain: incoming chain for the ld vector
246 // BasePtr: base pointer to load from
247 // SV: memory disambiguation source value
248 // SVOffset: memory disambiugation offset
249 // Alignment: alignment of the memory
250 // isVolatile: volatile lod
251 // ValOp: value to store
252 // StWidth: width of memory that we want to store
253 void genWidenVectorStores(SDValueVector& StChain, SDValue Chain,
254 SDValue BasePtr, const Value *SV,
255 int SVOffset, unsigned Alignment,
256 bool isVolatile, SDValue ValOp,
259 /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
260 /// specified mask and type. Targets can specify exactly which masks they
261 /// support and the code generator is tasked with not creating illegal masks.
263 /// Note that this will also return true for shuffles that are promoted to a
266 /// If this is a legal shuffle, this method returns the (possibly promoted)
267 /// build_vector Mask. If it's not a legal shuffle, it returns null.
268 SDNode *isShuffleLegal(MVT VT, SDValue Mask) const;
270 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
271 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
273 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC);
274 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC);
275 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC) {
276 LegalizeSetCCOperands(LHS, RHS, CC);
277 LegalizeSetCCCondCode(VT, LHS, RHS, CC);
280 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned,
282 SDValue ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source);
284 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT);
285 SDValue ExpandBUILD_VECTOR(SDNode *Node);
286 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
287 SDValue LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op);
288 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT);
289 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned);
290 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned);
292 SDValue ExpandBSWAP(SDValue Op);
293 SDValue ExpandBitCount(unsigned Opc, SDValue Op);
294 bool ExpandShift(unsigned Opc, SDValue Op, SDValue Amt,
295 SDValue &Lo, SDValue &Hi);
296 void ExpandShiftParts(unsigned NodeOp, SDValue Op, SDValue Amt,
297 SDValue &Lo, SDValue &Hi);
299 SDValue ExpandEXTRACT_SUBVECTOR(SDValue Op);
300 SDValue ExpandEXTRACT_VECTOR_ELT(SDValue Op);
302 // Returns the legalized (truncated or extended) shift amount.
303 SDValue LegalizeShiftAmount(SDValue ShiftAmt);
307 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
308 /// specified mask and type. Targets can specify exactly which masks they
309 /// support and the code generator is tasked with not creating illegal masks.
311 /// Note that this will also return true for shuffles that are promoted to a
313 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDValue Mask) const {
314 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
316 case TargetLowering::Legal:
317 case TargetLowering::Custom:
319 case TargetLowering::Promote: {
320 // If this is promoted to a different type, convert the shuffle mask and
321 // ask if it is legal in the promoted type!
322 MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
323 MVT EltVT = NVT.getVectorElementType();
325 // If we changed # elements, change the shuffle mask.
326 unsigned NumEltsGrowth =
327 NVT.getVectorNumElements() / VT.getVectorNumElements();
328 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
329 if (NumEltsGrowth > 1) {
330 // Renumber the elements.
331 SmallVector<SDValue, 8> Ops;
332 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
333 SDValue InOp = Mask.getOperand(i);
334 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
335 if (InOp.getOpcode() == ISD::UNDEF)
336 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
338 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getZExtValue();
339 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
343 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
349 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.getNode() : 0;
352 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, bool types)
353 : TLI(dag.getTargetLoweringInfo()), DAG(dag), TypesNeedLegalizing(types),
354 ValueTypeActions(TLI.getValueTypeActions()) {
355 assert(MVT::LAST_VALUETYPE <= 32 &&
356 "Too many value types for ValueTypeActions to hold!");
359 void SelectionDAGLegalize::LegalizeDAG() {
360 LastCALLSEQ_END = DAG.getEntryNode();
361 IsLegalizingCall = false;
363 // The legalize process is inherently a bottom-up recursive process (users
364 // legalize their uses before themselves). Given infinite stack space, we
365 // could just start legalizing on the root and traverse the whole graph. In
366 // practice however, this causes us to run out of stack space on large basic
367 // blocks. To avoid this problem, compute an ordering of the nodes where each
368 // node is only legalized after all of its operands are legalized.
369 DAG.AssignTopologicalOrder();
370 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
371 E = prior(DAG.allnodes_end()); I != next(E); ++I)
372 HandleOp(SDValue(I, 0));
374 // Finally, it's possible the root changed. Get the new root.
375 SDValue OldRoot = DAG.getRoot();
376 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
377 DAG.setRoot(LegalizedNodes[OldRoot]);
379 ExpandedNodes.clear();
380 LegalizedNodes.clear();
381 PromotedNodes.clear();
383 ScalarizedNodes.clear();
386 // Remove dead nodes now.
387 DAG.RemoveDeadNodes();
391 /// FindCallEndFromCallStart - Given a chained node that is part of a call
392 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
393 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
394 if (Node->getOpcode() == ISD::CALLSEQ_END)
396 if (Node->use_empty())
397 return 0; // No CallSeqEnd
399 // The chain is usually at the end.
400 SDValue TheChain(Node, Node->getNumValues()-1);
401 if (TheChain.getValueType() != MVT::Other) {
402 // Sometimes it's at the beginning.
403 TheChain = SDValue(Node, 0);
404 if (TheChain.getValueType() != MVT::Other) {
405 // Otherwise, hunt for it.
406 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
407 if (Node->getValueType(i) == MVT::Other) {
408 TheChain = SDValue(Node, i);
412 // Otherwise, we walked into a node without a chain.
413 if (TheChain.getValueType() != MVT::Other)
418 for (SDNode::use_iterator UI = Node->use_begin(),
419 E = Node->use_end(); UI != E; ++UI) {
421 // Make sure to only follow users of our token chain.
423 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
424 if (User->getOperand(i) == TheChain)
425 if (SDNode *Result = FindCallEndFromCallStart(User))
431 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
432 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
433 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
434 assert(Node && "Didn't find callseq_start for a call??");
435 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
437 assert(Node->getOperand(0).getValueType() == MVT::Other &&
438 "Node doesn't have a token chain argument!");
439 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
442 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
443 /// see if any uses can reach Dest. If no dest operands can get to dest,
444 /// legalize them, legalize ourself, and return false, otherwise, return true.
446 /// Keep track of the nodes we fine that actually do lead to Dest in
447 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
449 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
450 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
451 if (N == Dest) return true; // N certainly leads to Dest :)
453 // If we've already processed this node and it does lead to Dest, there is no
454 // need to reprocess it.
455 if (NodesLeadingTo.count(N)) return true;
457 // If the first result of this node has been already legalized, then it cannot
459 switch (getTypeAction(N->getValueType(0))) {
461 if (LegalizedNodes.count(SDValue(N, 0))) return false;
464 if (PromotedNodes.count(SDValue(N, 0))) return false;
467 if (ExpandedNodes.count(SDValue(N, 0))) return false;
471 // Okay, this node has not already been legalized. Check and legalize all
472 // operands. If none lead to Dest, then we can legalize this node.
473 bool OperandsLeadToDest = false;
474 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
475 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
476 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
478 if (OperandsLeadToDest) {
479 NodesLeadingTo.insert(N);
483 // Okay, this node looks safe, legalize it and return false.
484 HandleOp(SDValue(N, 0));
488 /// HandleOp - Legalize, Promote, Widen, or Expand the specified operand as
489 /// appropriate for its type.
490 void SelectionDAGLegalize::HandleOp(SDValue Op) {
491 MVT VT = Op.getValueType();
492 // If the type legalizer was run then we should never see any illegal result
493 // types here except for target constants (the type legalizer does not touch
494 // those) or for build vector used as a mask for a vector shuffle.
495 // FIXME: We can removed the BUILD_VECTOR case when we fix PR2957.
496 assert((TypesNeedLegalizing || getTypeAction(VT) == Legal ||
497 Op.getOpcode() == ISD::TargetConstant ||
498 Op.getOpcode() == ISD::BUILD_VECTOR) &&
499 "Illegal type introduced after type legalization?");
500 switch (getTypeAction(VT)) {
501 default: assert(0 && "Bad type action!");
502 case Legal: (void)LegalizeOp(Op); break;
504 if (!VT.isVector()) {
509 // See if we can widen otherwise use Expand to either scalarize or split
510 MVT WidenVT = TLI.getWidenVectorType(VT);
511 if (WidenVT != MVT::Other) {
512 (void) WidenVectorOp(Op, WidenVT);
515 // else fall thru to expand since we can't widen the vector
518 if (!VT.isVector()) {
519 // If this is an illegal scalar, expand it into its two component
522 if (Op.getOpcode() == ISD::TargetConstant)
523 break; // Allow illegal target nodes.
525 } else if (VT.getVectorNumElements() == 1) {
526 // If this is an illegal single element vector, convert it to a
528 (void)ScalarizeVectorOp(Op);
530 // This is an illegal multiple element vector.
531 // Split it in half and legalize both parts.
533 SplitVectorOp(Op, X, Y);
539 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
540 /// a load from the constant pool.
541 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
542 SelectionDAG &DAG, TargetLowering &TLI) {
545 // If a FP immediate is precise when represented as a float and if the
546 // target can do an extending load from float to double, we put it into
547 // the constant pool as a float, even if it's is statically typed as a
548 // double. This shrinks FP constants and canonicalizes them for targets where
549 // an FP extending load is the same cost as a normal load (such as on the x87
550 // fp stack or PPC FP unit).
551 MVT VT = CFP->getValueType(0);
552 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
554 if (VT!=MVT::f64 && VT!=MVT::f32)
555 assert(0 && "Invalid type expansion");
556 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
557 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
562 while (SVT != MVT::f32) {
563 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
564 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
565 // Only do this if the target has a native EXTLOAD instruction from
567 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
568 TLI.ShouldShrinkFPConstant(OrigVT)) {
569 const Type *SType = SVT.getTypeForMVT();
570 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
576 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
577 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
579 return DAG.getExtLoad(ISD::EXTLOAD, OrigVT, DAG.getEntryNode(),
580 CPIdx, PseudoSourceValue::getConstantPool(),
581 0, VT, false, Alignment);
582 return DAG.getLoad(OrigVT, DAG.getEntryNode(), CPIdx,
583 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
587 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
590 SDValue ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT NVT,
591 SelectionDAG &DAG, TargetLowering &TLI) {
592 MVT VT = Node->getValueType(0);
593 MVT SrcVT = Node->getOperand(1).getValueType();
594 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
595 "fcopysign expansion only supported for f32 and f64");
596 MVT SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
598 // First get the sign bit of second operand.
599 SDValue Mask1 = (SrcVT == MVT::f64)
600 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
601 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
602 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
603 SDValue SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
604 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
605 // Shift right or sign-extend it if the two operands have different types.
606 int SizeDiff = SrcNVT.getSizeInBits() - NVT.getSizeInBits();
608 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
609 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
610 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
611 } else if (SizeDiff < 0) {
612 SignBit = DAG.getNode(ISD::ZERO_EXTEND, NVT, SignBit);
613 SignBit = DAG.getNode(ISD::SHL, NVT, SignBit,
614 DAG.getConstant(-SizeDiff, TLI.getShiftAmountTy()));
617 // Clear the sign bit of first operand.
618 SDValue Mask2 = (VT == MVT::f64)
619 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
620 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
621 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
622 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
623 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
625 // Or the value with the sign bit.
626 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
630 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
632 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
633 TargetLowering &TLI) {
634 SDValue Chain = ST->getChain();
635 SDValue Ptr = ST->getBasePtr();
636 SDValue Val = ST->getValue();
637 MVT VT = Val.getValueType();
638 int Alignment = ST->getAlignment();
639 int SVOffset = ST->getSrcValueOffset();
640 if (ST->getMemoryVT().isFloatingPoint() ||
641 ST->getMemoryVT().isVector()) {
642 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
643 if (TLI.isTypeLegal(intVT)) {
644 // Expand to a bitconvert of the value to the integer type of the
645 // same size, then a (misaligned) int store.
646 // FIXME: Does not handle truncating floating point stores!
647 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, intVT, Val);
648 return DAG.getStore(Chain, Result, Ptr, ST->getSrcValue(),
649 SVOffset, ST->isVolatile(), Alignment);
651 // Do a (aligned) store to a stack slot, then copy from the stack slot
652 // to the final destination using (unaligned) integer loads and stores.
653 MVT StoredVT = ST->getMemoryVT();
655 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
656 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
657 unsigned RegBytes = RegVT.getSizeInBits() / 8;
658 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
660 // Make sure the stack slot is also aligned for the register type.
661 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
663 // Perform the original store, only redirected to the stack slot.
664 SDValue Store = DAG.getTruncStore(Chain, Val, StackPtr, NULL, 0,StoredVT);
665 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
666 SmallVector<SDValue, 8> Stores;
669 // Do all but one copies using the full register width.
670 for (unsigned i = 1; i < NumRegs; i++) {
671 // Load one integer register's worth from the stack slot.
672 SDValue Load = DAG.getLoad(RegVT, Store, StackPtr, NULL, 0);
673 // Store it to the final location. Remember the store.
674 Stores.push_back(DAG.getStore(Load.getValue(1), Load, Ptr,
675 ST->getSrcValue(), SVOffset + Offset,
677 MinAlign(ST->getAlignment(), Offset)));
678 // Increment the pointers.
680 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
682 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
685 // The last store may be partial. Do a truncating store. On big-endian
686 // machines this requires an extending load from the stack slot to ensure
687 // that the bits are in the right place.
688 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
690 // Load from the stack slot.
691 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Store, StackPtr,
694 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, Ptr,
695 ST->getSrcValue(), SVOffset + Offset,
696 MemVT, ST->isVolatile(),
697 MinAlign(ST->getAlignment(), Offset)));
698 // The order of the stores doesn't matter - say it with a TokenFactor.
699 return DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
703 assert(ST->getMemoryVT().isInteger() &&
704 !ST->getMemoryVT().isVector() &&
705 "Unaligned store of unknown type.");
706 // Get the half-size VT
708 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
709 int NumBits = NewStoredVT.getSizeInBits();
710 int IncrementSize = NumBits / 8;
712 // Divide the stored value in two parts.
713 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
715 SDValue Hi = DAG.getNode(ISD::SRL, VT, Val, ShiftAmount);
717 // Store the two parts
718 SDValue Store1, Store2;
719 Store1 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Lo:Hi, Ptr,
720 ST->getSrcValue(), SVOffset, NewStoredVT,
721 ST->isVolatile(), Alignment);
722 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
723 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
724 Alignment = MinAlign(Alignment, IncrementSize);
725 Store2 = DAG.getTruncStore(Chain, TLI.isLittleEndian()?Hi:Lo, Ptr,
726 ST->getSrcValue(), SVOffset + IncrementSize,
727 NewStoredVT, ST->isVolatile(), Alignment);
729 return DAG.getNode(ISD::TokenFactor, MVT::Other, Store1, Store2);
732 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
734 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
735 TargetLowering &TLI) {
736 int SVOffset = LD->getSrcValueOffset();
737 SDValue Chain = LD->getChain();
738 SDValue Ptr = LD->getBasePtr();
739 MVT VT = LD->getValueType(0);
740 MVT LoadedVT = LD->getMemoryVT();
741 if (VT.isFloatingPoint() || VT.isVector()) {
742 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
743 if (TLI.isTypeLegal(intVT)) {
744 // Expand to a (misaligned) integer load of the same size,
745 // then bitconvert to floating point or vector.
746 SDValue newLoad = DAG.getLoad(intVT, Chain, Ptr, LD->getSrcValue(),
747 SVOffset, LD->isVolatile(),
749 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, LoadedVT, newLoad);
750 if (VT.isFloatingPoint() && LoadedVT != VT)
751 Result = DAG.getNode(ISD::FP_EXTEND, VT, Result);
753 SDValue Ops[] = { Result, Chain };
754 return DAG.getMergeValues(Ops, 2);
756 // Copy the value to a (aligned) stack slot using (unaligned) integer
757 // loads and stores, then do a (aligned) load from the stack slot.
758 MVT RegVT = TLI.getRegisterType(intVT);
759 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
760 unsigned RegBytes = RegVT.getSizeInBits() / 8;
761 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
763 // Make sure the stack slot is also aligned for the register type.
764 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
766 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
767 SmallVector<SDValue, 8> Stores;
768 SDValue StackPtr = StackBase;
771 // Do all but one copies using the full register width.
772 for (unsigned i = 1; i < NumRegs; i++) {
773 // Load one integer register's worth from the original location.
774 SDValue Load = DAG.getLoad(RegVT, Chain, Ptr, LD->getSrcValue(),
775 SVOffset + Offset, LD->isVolatile(),
776 MinAlign(LD->getAlignment(), Offset));
777 // Follow the load with a store to the stack slot. Remember the store.
778 Stores.push_back(DAG.getStore(Load.getValue(1), Load, StackPtr,
780 // Increment the pointers.
782 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, Increment);
783 StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
787 // The last copy may be partial. Do an extending load.
788 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
789 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, RegVT, Chain, Ptr,
790 LD->getSrcValue(), SVOffset + Offset,
791 MemVT, LD->isVolatile(),
792 MinAlign(LD->getAlignment(), Offset));
793 // Follow the load with a store to the stack slot. Remember the store.
794 // On big-endian machines this requires a truncating store to ensure
795 // that the bits end up in the right place.
796 Stores.push_back(DAG.getTruncStore(Load.getValue(1), Load, StackPtr,
799 // The order of the stores doesn't matter - say it with a TokenFactor.
800 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],
803 // Finally, perform the original load only redirected to the stack slot.
804 Load = DAG.getExtLoad(LD->getExtensionType(), VT, TF, StackBase,
807 // Callers expect a MERGE_VALUES node.
808 SDValue Ops[] = { Load, TF };
809 return DAG.getMergeValues(Ops, 2);
812 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
813 "Unaligned load of unsupported type.");
815 // Compute the new VT that is half the size of the old one. This is an
817 unsigned NumBits = LoadedVT.getSizeInBits();
819 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
822 unsigned Alignment = LD->getAlignment();
823 unsigned IncrementSize = NumBits / 8;
824 ISD::LoadExtType HiExtType = LD->getExtensionType();
826 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
827 if (HiExtType == ISD::NON_EXTLOAD)
828 HiExtType = ISD::ZEXTLOAD;
830 // Load the value in two parts
832 if (TLI.isLittleEndian()) {
833 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
834 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
835 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
836 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
837 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(),
838 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
839 MinAlign(Alignment, IncrementSize));
841 Hi = DAG.getExtLoad(HiExtType, VT, Chain, Ptr, LD->getSrcValue(), SVOffset,
842 NewLoadedVT,LD->isVolatile(), Alignment);
843 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
844 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
845 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, VT, Chain, Ptr, LD->getSrcValue(),
846 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
847 MinAlign(Alignment, IncrementSize));
850 // aggregate the two parts
851 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
852 SDValue Result = DAG.getNode(ISD::SHL, VT, Hi, ShiftAmount);
853 Result = DAG.getNode(ISD::OR, VT, Result, Lo);
855 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
858 SDValue Ops[] = { Result, TF };
859 return DAG.getMergeValues(Ops, 2);
862 /// UnrollVectorOp - We know that the given vector has a legal type, however
863 /// the operation it performs is not legal and is an operation that we have
864 /// no way of lowering. "Unroll" the vector, splitting out the scalars and
865 /// operating on each element individually.
866 SDValue SelectionDAGLegalize::UnrollVectorOp(SDValue Op) {
867 MVT VT = Op.getValueType();
868 assert(isTypeLegal(VT) &&
869 "Caller should expand or promote operands that are not legal!");
870 assert(Op.getNode()->getNumValues() == 1 &&
871 "Can't unroll a vector with multiple results!");
872 unsigned NE = VT.getVectorNumElements();
873 MVT EltVT = VT.getVectorElementType();
875 SmallVector<SDValue, 8> Scalars;
876 SmallVector<SDValue, 4> Operands(Op.getNumOperands());
877 for (unsigned i = 0; i != NE; ++i) {
878 for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
879 SDValue Operand = Op.getOperand(j);
880 MVT OperandVT = Operand.getValueType();
881 if (OperandVT.isVector()) {
882 // A vector operand; extract a single element.
883 MVT OperandEltVT = OperandVT.getVectorElementType();
884 Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT,
887 DAG.getConstant(i, MVT::i32));
889 // A scalar operand; just use it as is.
890 Operands[j] = Operand;
894 switch (Op.getOpcode()) {
896 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT,
897 &Operands[0], Operands.size()));
902 Scalars.push_back(DAG.getNode(Op.getOpcode(), EltVT, Operands[0],
903 LegalizeShiftAmount(Operands[1])));
908 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Scalars[0], Scalars.size());
911 /// GetFPLibCall - Return the right libcall for the given floating point type.
912 static RTLIB::Libcall GetFPLibCall(MVT VT,
913 RTLIB::Libcall Call_F32,
914 RTLIB::Libcall Call_F64,
915 RTLIB::Libcall Call_F80,
916 RTLIB::Libcall Call_PPCF128) {
918 VT == MVT::f32 ? Call_F32 :
919 VT == MVT::f64 ? Call_F64 :
920 VT == MVT::f80 ? Call_F80 :
921 VT == MVT::ppcf128 ? Call_PPCF128 :
922 RTLIB::UNKNOWN_LIBCALL;
925 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
926 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
927 /// is necessary to spill the vector being inserted into to memory, perform
928 /// the insert there, and then read the result back.
929 SDValue SelectionDAGLegalize::
930 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx) {
935 // If the target doesn't support this, we have to spill the input vector
936 // to a temporary stack slot, update the element, then reload it. This is
937 // badness. We could also load the value into a vector register (either
938 // with a "move to register" or "extload into register" instruction, then
939 // permute it into place, if the idx is a constant and if the idx is
940 // supported by the target.
941 MVT VT = Tmp1.getValueType();
942 MVT EltVT = VT.getVectorElementType();
943 MVT IdxVT = Tmp3.getValueType();
944 MVT PtrVT = TLI.getPointerTy();
945 SDValue StackPtr = DAG.CreateStackTemporary(VT);
947 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
950 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr,
951 PseudoSourceValue::getFixedStack(SPFI), 0);
953 // Truncate or zero extend offset to target pointer type.
954 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
955 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
956 // Add the offset to the index.
957 unsigned EltSize = EltVT.getSizeInBits()/8;
958 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
959 SDValue StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
960 // Store the scalar value.
961 Ch = DAG.getTruncStore(Ch, Tmp2, StackPtr2,
962 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
963 // Load the updated vector.
964 return DAG.getLoad(VT, Ch, StackPtr,
965 PseudoSourceValue::getFixedStack(SPFI), 0);
968 SDValue SelectionDAGLegalize::LegalizeShiftAmount(SDValue ShiftAmt) {
969 if (TLI.getShiftAmountTy().bitsLT(ShiftAmt.getValueType()))
970 return DAG.getNode(ISD::TRUNCATE, TLI.getShiftAmountTy(), ShiftAmt);
972 if (TLI.getShiftAmountTy().bitsGT(ShiftAmt.getValueType()))
973 return DAG.getNode(ISD::ANY_EXTEND, TLI.getShiftAmountTy(), ShiftAmt);
979 /// LegalizeOp - We know that the specified value has a legal type, and
980 /// that its operands are legal. Now ensure that the operation itself
981 /// is legal, recursively ensuring that the operands' operations remain
983 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
984 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
987 assert(isTypeLegal(Op.getValueType()) &&
988 "Caller should expand or promote operands that are not legal!");
989 SDNode *Node = Op.getNode();
991 // If this operation defines any values that cannot be represented in a
992 // register on this target, make sure to expand or promote them.
993 if (Node->getNumValues() > 1) {
994 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
995 if (getTypeAction(Node->getValueType(i)) != Legal) {
996 HandleOp(Op.getValue(i));
997 assert(LegalizedNodes.count(Op) &&
998 "Handling didn't add legal operands!");
999 return LegalizedNodes[Op];
1003 // Note that LegalizeOp may be reentered even from single-use nodes, which
1004 // means that we always must cache transformed nodes.
1005 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1006 if (I != LegalizedNodes.end()) return I->second;
1008 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
1009 SDValue Result = Op;
1010 bool isCustom = false;
1012 switch (Node->getOpcode()) {
1013 case ISD::FrameIndex:
1014 case ISD::EntryToken:
1016 case ISD::BasicBlock:
1017 case ISD::TargetFrameIndex:
1018 case ISD::TargetJumpTable:
1019 case ISD::TargetConstant:
1020 case ISD::TargetConstantFP:
1021 case ISD::TargetConstantPool:
1022 case ISD::TargetGlobalAddress:
1023 case ISD::TargetGlobalTLSAddress:
1024 case ISD::TargetExternalSymbol:
1025 case ISD::VALUETYPE:
1027 case ISD::MEMOPERAND:
1029 case ISD::ARG_FLAGS:
1030 // Primitives must all be legal.
1031 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
1032 "This must be legal!");
1035 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
1036 // If this is a target node, legalize it by legalizing the operands then
1037 // passing it through.
1038 SmallVector<SDValue, 8> Ops;
1039 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1040 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1042 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
1044 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
1045 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
1046 return Result.getValue(Op.getResNo());
1048 // Otherwise this is an unhandled builtin node. splat.
1050 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
1052 assert(0 && "Do not know how to legalize this operator!");
1054 case ISD::GLOBAL_OFFSET_TABLE:
1055 case ISD::GlobalAddress:
1056 case ISD::GlobalTLSAddress:
1057 case ISD::ExternalSymbol:
1058 case ISD::ConstantPool:
1059 case ISD::JumpTable: // Nothing to do.
1060 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1061 default: assert(0 && "This action is not supported yet!");
1062 case TargetLowering::Custom:
1063 Tmp1 = TLI.LowerOperation(Op, DAG);
1064 if (Tmp1.getNode()) Result = Tmp1;
1065 // FALLTHROUGH if the target doesn't want to lower this op after all.
1066 case TargetLowering::Legal:
1070 case ISD::FRAMEADDR:
1071 case ISD::RETURNADDR:
1072 // The only option for these nodes is to custom lower them. If the target
1073 // does not custom lower them, then return zero.
1074 Tmp1 = TLI.LowerOperation(Op, DAG);
1078 Result = DAG.getConstant(0, TLI.getPointerTy());
1080 case ISD::FRAME_TO_ARGS_OFFSET: {
1081 MVT VT = Node->getValueType(0);
1082 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1083 default: assert(0 && "This action is not supported yet!");
1084 case TargetLowering::Custom:
1085 Result = TLI.LowerOperation(Op, DAG);
1086 if (Result.getNode()) break;
1088 case TargetLowering::Legal:
1089 Result = DAG.getConstant(0, VT);
1094 case ISD::EXCEPTIONADDR: {
1095 Tmp1 = LegalizeOp(Node->getOperand(0));
1096 MVT VT = Node->getValueType(0);
1097 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1098 default: assert(0 && "This action is not supported yet!");
1099 case TargetLowering::Expand: {
1100 unsigned Reg = TLI.getExceptionAddressRegister();
1101 Result = DAG.getCopyFromReg(Tmp1, Reg, VT);
1104 case TargetLowering::Custom:
1105 Result = TLI.LowerOperation(Op, DAG);
1106 if (Result.getNode()) break;
1108 case TargetLowering::Legal: {
1109 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp1 };
1110 Result = DAG.getMergeValues(Ops, 2);
1115 if (Result.getNode()->getNumValues() == 1) break;
1117 assert(Result.getNode()->getNumValues() == 2 &&
1118 "Cannot return more than two values!");
1120 // Since we produced two values, make sure to remember that we
1121 // legalized both of them.
1122 Tmp1 = LegalizeOp(Result);
1123 Tmp2 = LegalizeOp(Result.getValue(1));
1124 AddLegalizedOperand(Op.getValue(0), Tmp1);
1125 AddLegalizedOperand(Op.getValue(1), Tmp2);
1126 return Op.getResNo() ? Tmp2 : Tmp1;
1127 case ISD::EHSELECTION: {
1128 Tmp1 = LegalizeOp(Node->getOperand(0));
1129 Tmp2 = LegalizeOp(Node->getOperand(1));
1130 MVT VT = Node->getValueType(0);
1131 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1132 default: assert(0 && "This action is not supported yet!");
1133 case TargetLowering::Expand: {
1134 unsigned Reg = TLI.getExceptionSelectorRegister();
1135 Result = DAG.getCopyFromReg(Tmp2, Reg, VT);
1138 case TargetLowering::Custom:
1139 Result = TLI.LowerOperation(Op, DAG);
1140 if (Result.getNode()) break;
1142 case TargetLowering::Legal: {
1143 SDValue Ops[] = { DAG.getConstant(0, VT), Tmp2 };
1144 Result = DAG.getMergeValues(Ops, 2);
1149 if (Result.getNode()->getNumValues() == 1) break;
1151 assert(Result.getNode()->getNumValues() == 2 &&
1152 "Cannot return more than two values!");
1154 // Since we produced two values, make sure to remember that we
1155 // legalized both of them.
1156 Tmp1 = LegalizeOp(Result);
1157 Tmp2 = LegalizeOp(Result.getValue(1));
1158 AddLegalizedOperand(Op.getValue(0), Tmp1);
1159 AddLegalizedOperand(Op.getValue(1), Tmp2);
1160 return Op.getResNo() ? Tmp2 : Tmp1;
1161 case ISD::EH_RETURN: {
1162 MVT VT = Node->getValueType(0);
1163 // The only "good" option for this node is to custom lower it.
1164 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1165 default: assert(0 && "This action is not supported at all!");
1166 case TargetLowering::Custom:
1167 Result = TLI.LowerOperation(Op, DAG);
1168 if (Result.getNode()) break;
1170 case TargetLowering::Legal:
1171 // Target does not know, how to lower this, lower to noop
1172 Result = LegalizeOp(Node->getOperand(0));
1177 case ISD::AssertSext:
1178 case ISD::AssertZext:
1179 Tmp1 = LegalizeOp(Node->getOperand(0));
1180 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1182 case ISD::MERGE_VALUES:
1183 // Legalize eliminates MERGE_VALUES nodes.
1184 Result = Node->getOperand(Op.getResNo());
1186 case ISD::CopyFromReg:
1187 Tmp1 = LegalizeOp(Node->getOperand(0));
1188 Result = Op.getValue(0);
1189 if (Node->getNumValues() == 2) {
1190 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1192 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
1193 if (Node->getNumOperands() == 3) {
1194 Tmp2 = LegalizeOp(Node->getOperand(2));
1195 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1197 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1199 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
1201 // Since CopyFromReg produces two values, make sure to remember that we
1202 // legalized both of them.
1203 AddLegalizedOperand(Op.getValue(0), Result);
1204 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1205 return Result.getValue(Op.getResNo());
1207 MVT VT = Op.getValueType();
1208 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
1209 default: assert(0 && "This action is not supported yet!");
1210 case TargetLowering::Expand:
1212 Result = DAG.getConstant(0, VT);
1213 else if (VT.isFloatingPoint())
1214 Result = DAG.getConstantFP(APFloat(APInt(VT.getSizeInBits(), 0)),
1217 assert(0 && "Unknown value type!");
1219 case TargetLowering::Legal:
1225 case ISD::INTRINSIC_W_CHAIN:
1226 case ISD::INTRINSIC_WO_CHAIN:
1227 case ISD::INTRINSIC_VOID: {
1228 SmallVector<SDValue, 8> Ops;
1229 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1230 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1231 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1233 // Allow the target to custom lower its intrinsics if it wants to.
1234 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
1235 TargetLowering::Custom) {
1236 Tmp3 = TLI.LowerOperation(Result, DAG);
1237 if (Tmp3.getNode()) Result = Tmp3;
1240 if (Result.getNode()->getNumValues() == 1) break;
1242 // Must have return value and chain result.
1243 assert(Result.getNode()->getNumValues() == 2 &&
1244 "Cannot return more than two values!");
1246 // Since loads produce two values, make sure to remember that we
1247 // legalized both of them.
1248 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1249 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1250 return Result.getValue(Op.getResNo());
1253 case ISD::DBG_STOPPOINT:
1254 assert(Node->getNumOperands() == 1 && "Invalid DBG_STOPPOINT node!");
1255 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
1257 switch (TLI.getOperationAction(ISD::DBG_STOPPOINT, MVT::Other)) {
1258 case TargetLowering::Promote:
1259 default: assert(0 && "This action is not supported yet!");
1260 case TargetLowering::Expand: {
1261 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
1262 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
1263 bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
1265 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1266 if (MMI && (useDEBUG_LOC || useLABEL)) {
1267 const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
1268 unsigned SrcFile = MMI->RecordSource(CompileUnit);
1270 unsigned Line = DSP->getLine();
1271 unsigned Col = DSP->getColumn();
1274 SDValue Ops[] = { Tmp1, DAG.getConstant(Line, MVT::i32),
1275 DAG.getConstant(Col, MVT::i32),
1276 DAG.getConstant(SrcFile, MVT::i32) };
1277 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops, 4);
1279 unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
1280 Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
1283 Result = Tmp1; // chain
1287 case TargetLowering::Legal: {
1288 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1289 if (Action == Legal && Tmp1 == Node->getOperand(0))
1292 SmallVector<SDValue, 8> Ops;
1293 Ops.push_back(Tmp1);
1294 if (Action == Legal) {
1295 Ops.push_back(Node->getOperand(1)); // line # must be legal.
1296 Ops.push_back(Node->getOperand(2)); // col # must be legal.
1298 // Otherwise promote them.
1299 Ops.push_back(PromoteOp(Node->getOperand(1)));
1300 Ops.push_back(PromoteOp(Node->getOperand(2)));
1302 Ops.push_back(Node->getOperand(3)); // filename must be legal.
1303 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
1304 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1311 assert(Node->getNumOperands() == 3 && "Invalid DECLARE node!");
1312 switch (TLI.getOperationAction(ISD::DECLARE, MVT::Other)) {
1313 default: assert(0 && "This action is not supported yet!");
1314 case TargetLowering::Legal:
1315 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1316 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1317 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the variable.
1318 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1320 case TargetLowering::Expand:
1321 Result = LegalizeOp(Node->getOperand(0));
1326 case ISD::DEBUG_LOC:
1327 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
1328 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
1329 default: assert(0 && "This action is not supported yet!");
1330 case TargetLowering::Legal: {
1331 LegalizeAction Action = getTypeAction(Node->getOperand(1).getValueType());
1332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1333 if (Action == Legal && Tmp1 == Node->getOperand(0))
1335 if (Action == Legal) {
1336 Tmp2 = Node->getOperand(1);
1337 Tmp3 = Node->getOperand(2);
1338 Tmp4 = Node->getOperand(3);
1340 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
1341 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
1342 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1350 case ISD::DBG_LABEL:
1352 assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
1353 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1354 default: assert(0 && "This action is not supported yet!");
1355 case TargetLowering::Legal:
1356 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1357 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1359 case TargetLowering::Expand:
1360 Result = LegalizeOp(Node->getOperand(0));
1366 assert(Node->getNumOperands() == 4 && "Invalid Prefetch node!");
1367 switch (TLI.getOperationAction(ISD::PREFETCH, MVT::Other)) {
1368 default: assert(0 && "This action is not supported yet!");
1369 case TargetLowering::Legal:
1370 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1371 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the address.
1372 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the rw specifier.
1373 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize locality specifier.
1374 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
1376 case TargetLowering::Expand:
1378 Result = LegalizeOp(Node->getOperand(0));
1383 case ISD::MEMBARRIER: {
1384 assert(Node->getNumOperands() == 6 && "Invalid MemBarrier node!");
1385 switch (TLI.getOperationAction(ISD::MEMBARRIER, MVT::Other)) {
1386 default: assert(0 && "This action is not supported yet!");
1387 case TargetLowering::Legal: {
1389 Ops[0] = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1390 for (int x = 1; x < 6; ++x) {
1391 Ops[x] = Node->getOperand(x);
1392 if (!isTypeLegal(Ops[x].getValueType()))
1393 Ops[x] = PromoteOp(Ops[x]);
1395 Result = DAG.UpdateNodeOperands(Result, &Ops[0], 6);
1398 case TargetLowering::Expand:
1399 //There is no libgcc call for this op
1400 Result = Node->getOperand(0); // Noop
1406 case ISD::ATOMIC_CMP_SWAP_8:
1407 case ISD::ATOMIC_CMP_SWAP_16:
1408 case ISD::ATOMIC_CMP_SWAP_32:
1409 case ISD::ATOMIC_CMP_SWAP_64: {
1410 unsigned int num_operands = 4;
1411 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1413 for (unsigned int x = 0; x < num_operands; ++x)
1414 Ops[x] = LegalizeOp(Node->getOperand(x));
1415 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1417 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1418 default: assert(0 && "This action is not supported yet!");
1419 case TargetLowering::Custom:
1420 Result = TLI.LowerOperation(Result, DAG);
1422 case TargetLowering::Legal:
1425 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1426 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1427 return Result.getValue(Op.getResNo());
1429 case ISD::ATOMIC_LOAD_ADD_8:
1430 case ISD::ATOMIC_LOAD_SUB_8:
1431 case ISD::ATOMIC_LOAD_AND_8:
1432 case ISD::ATOMIC_LOAD_OR_8:
1433 case ISD::ATOMIC_LOAD_XOR_8:
1434 case ISD::ATOMIC_LOAD_NAND_8:
1435 case ISD::ATOMIC_LOAD_MIN_8:
1436 case ISD::ATOMIC_LOAD_MAX_8:
1437 case ISD::ATOMIC_LOAD_UMIN_8:
1438 case ISD::ATOMIC_LOAD_UMAX_8:
1439 case ISD::ATOMIC_SWAP_8:
1440 case ISD::ATOMIC_LOAD_ADD_16:
1441 case ISD::ATOMIC_LOAD_SUB_16:
1442 case ISD::ATOMIC_LOAD_AND_16:
1443 case ISD::ATOMIC_LOAD_OR_16:
1444 case ISD::ATOMIC_LOAD_XOR_16:
1445 case ISD::ATOMIC_LOAD_NAND_16:
1446 case ISD::ATOMIC_LOAD_MIN_16:
1447 case ISD::ATOMIC_LOAD_MAX_16:
1448 case ISD::ATOMIC_LOAD_UMIN_16:
1449 case ISD::ATOMIC_LOAD_UMAX_16:
1450 case ISD::ATOMIC_SWAP_16:
1451 case ISD::ATOMIC_LOAD_ADD_32:
1452 case ISD::ATOMIC_LOAD_SUB_32:
1453 case ISD::ATOMIC_LOAD_AND_32:
1454 case ISD::ATOMIC_LOAD_OR_32:
1455 case ISD::ATOMIC_LOAD_XOR_32:
1456 case ISD::ATOMIC_LOAD_NAND_32:
1457 case ISD::ATOMIC_LOAD_MIN_32:
1458 case ISD::ATOMIC_LOAD_MAX_32:
1459 case ISD::ATOMIC_LOAD_UMIN_32:
1460 case ISD::ATOMIC_LOAD_UMAX_32:
1461 case ISD::ATOMIC_SWAP_32:
1462 case ISD::ATOMIC_LOAD_ADD_64:
1463 case ISD::ATOMIC_LOAD_SUB_64:
1464 case ISD::ATOMIC_LOAD_AND_64:
1465 case ISD::ATOMIC_LOAD_OR_64:
1466 case ISD::ATOMIC_LOAD_XOR_64:
1467 case ISD::ATOMIC_LOAD_NAND_64:
1468 case ISD::ATOMIC_LOAD_MIN_64:
1469 case ISD::ATOMIC_LOAD_MAX_64:
1470 case ISD::ATOMIC_LOAD_UMIN_64:
1471 case ISD::ATOMIC_LOAD_UMAX_64:
1472 case ISD::ATOMIC_SWAP_64: {
1473 unsigned int num_operands = 3;
1474 assert(Node->getNumOperands() == num_operands && "Invalid Atomic node!");
1476 for (unsigned int x = 0; x < num_operands; ++x)
1477 Ops[x] = LegalizeOp(Node->getOperand(x));
1478 Result = DAG.UpdateNodeOperands(Result, &Ops[0], num_operands);
1480 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
1481 default: assert(0 && "This action is not supported yet!");
1482 case TargetLowering::Custom:
1483 Result = TLI.LowerOperation(Result, DAG);
1485 case TargetLowering::Legal:
1488 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1489 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1490 return Result.getValue(Op.getResNo());
1492 case ISD::Constant: {
1493 ConstantSDNode *CN = cast<ConstantSDNode>(Node);
1495 TLI.getOperationAction(ISD::Constant, CN->getValueType(0));
1497 // We know we don't need to expand constants here, constants only have one
1498 // value and we check that it is fine above.
1500 if (opAction == TargetLowering::Custom) {
1501 Tmp1 = TLI.LowerOperation(Result, DAG);
1507 case ISD::ConstantFP: {
1508 // Spill FP immediates to the constant pool if the target cannot directly
1509 // codegen them. Targets often have some immediate values that can be
1510 // efficiently generated into an FP register without a load. We explicitly
1511 // leave these constants as ConstantFP nodes for the target to deal with.
1512 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
1514 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
1515 default: assert(0 && "This action is not supported yet!");
1516 case TargetLowering::Legal:
1518 case TargetLowering::Custom:
1519 Tmp3 = TLI.LowerOperation(Result, DAG);
1520 if (Tmp3.getNode()) {
1525 case TargetLowering::Expand: {
1526 // Check to see if this FP immediate is already legal.
1527 bool isLegal = false;
1528 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
1529 E = TLI.legal_fpimm_end(); I != E; ++I) {
1530 if (CFP->isExactlyValue(*I)) {
1535 // If this is a legal constant, turn it into a TargetConstantFP node.
1538 Result = ExpandConstantFP(CFP, true, DAG, TLI);
1543 case ISD::TokenFactor:
1544 if (Node->getNumOperands() == 2) {
1545 Tmp1 = LegalizeOp(Node->getOperand(0));
1546 Tmp2 = LegalizeOp(Node->getOperand(1));
1547 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1548 } else if (Node->getNumOperands() == 3) {
1549 Tmp1 = LegalizeOp(Node->getOperand(0));
1550 Tmp2 = LegalizeOp(Node->getOperand(1));
1551 Tmp3 = LegalizeOp(Node->getOperand(2));
1552 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1554 SmallVector<SDValue, 8> Ops;
1555 // Legalize the operands.
1556 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1557 Ops.push_back(LegalizeOp(Node->getOperand(i)));
1558 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1562 case ISD::FORMAL_ARGUMENTS:
1564 // The only option for this is to custom lower it.
1565 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
1566 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
1567 // A call within a calling sequence must be legalized to something
1568 // other than the normal CALLSEQ_END. Violating this gets Legalize
1569 // into an infinite loop.
1570 assert ((!IsLegalizingCall ||
1571 Node->getOpcode() != ISD::CALL ||
1572 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
1573 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
1575 // The number of incoming and outgoing values should match; unless the final
1576 // outgoing value is a flag.
1577 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
1578 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
1579 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
1581 "Lowering call/formal_arguments produced unexpected # results!");
1583 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
1584 // remember that we legalized all of them, so it doesn't get relegalized.
1585 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
1586 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
1588 Tmp1 = LegalizeOp(Tmp3.getValue(i));
1589 if (Op.getResNo() == i)
1591 AddLegalizedOperand(SDValue(Node, i), Tmp1);
1594 case ISD::EXTRACT_SUBREG: {
1595 Tmp1 = LegalizeOp(Node->getOperand(0));
1596 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(1));
1597 assert(idx && "Operand must be a constant");
1598 Tmp2 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1599 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1602 case ISD::INSERT_SUBREG: {
1603 Tmp1 = LegalizeOp(Node->getOperand(0));
1604 Tmp2 = LegalizeOp(Node->getOperand(1));
1605 ConstantSDNode *idx = dyn_cast<ConstantSDNode>(Node->getOperand(2));
1606 assert(idx && "Operand must be a constant");
1607 Tmp3 = DAG.getTargetConstant(idx->getAPIntValue(), idx->getValueType(0));
1608 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1611 case ISD::BUILD_VECTOR:
1612 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1613 default: assert(0 && "This action is not supported yet!");
1614 case TargetLowering::Custom:
1615 Tmp3 = TLI.LowerOperation(Result, DAG);
1616 if (Tmp3.getNode()) {
1621 case TargetLowering::Expand:
1622 Result = ExpandBUILD_VECTOR(Result.getNode());
1626 case ISD::INSERT_VECTOR_ELT:
1627 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
1628 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
1630 // The type of the value to insert may not be legal, even though the vector
1631 // type is legal. Legalize/Promote accordingly. We do not handle Expand
1633 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1634 default: assert(0 && "Cannot expand insert element operand");
1635 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
1636 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
1638 // FIXME: An alternative would be to check to see if the target is not
1639 // going to custom lower this operation, we could bitcast to half elt
1640 // width and perform two inserts at that width, if that is legal.
1641 Tmp2 = Node->getOperand(1);
1644 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1646 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
1647 Node->getValueType(0))) {
1648 default: assert(0 && "This action is not supported yet!");
1649 case TargetLowering::Legal:
1651 case TargetLowering::Custom:
1652 Tmp4 = TLI.LowerOperation(Result, DAG);
1653 if (Tmp4.getNode()) {
1658 case TargetLowering::Promote:
1659 // Fall thru for vector case
1660 case TargetLowering::Expand: {
1661 // If the insert index is a constant, codegen this as a scalar_to_vector,
1662 // then a shuffle that inserts it into the right position in the vector.
1663 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
1664 // SCALAR_TO_VECTOR requires that the type of the value being inserted
1665 // match the element type of the vector being created.
1666 if (Tmp2.getValueType() ==
1667 Op.getValueType().getVectorElementType()) {
1668 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
1669 Tmp1.getValueType(), Tmp2);
1671 unsigned NumElts = Tmp1.getValueType().getVectorNumElements();
1673 MVT::getIntVectorWithNumElements(NumElts);
1674 MVT ShufMaskEltVT = ShufMaskVT.getVectorElementType();
1676 // We generate a shuffle of InVec and ScVec, so the shuffle mask
1677 // should be 0,1,2,3,4,5... with the appropriate element replaced with
1678 // elt 0 of the RHS.
1679 SmallVector<SDValue, 8> ShufOps;
1680 for (unsigned i = 0; i != NumElts; ++i) {
1681 if (i != InsertPos->getZExtValue())
1682 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1684 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1686 SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1687 &ShufOps[0], ShufOps.size());
1689 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1690 Tmp1, ScVec, ShufMask);
1691 Result = LegalizeOp(Result);
1695 Result = PerformInsertVectorEltInMemory(Tmp1, Tmp2, Tmp3);
1700 case ISD::SCALAR_TO_VECTOR:
1701 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1702 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1706 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1707 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1708 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1709 Node->getValueType(0))) {
1710 default: assert(0 && "This action is not supported yet!");
1711 case TargetLowering::Legal:
1713 case TargetLowering::Custom:
1714 Tmp3 = TLI.LowerOperation(Result, DAG);
1715 if (Tmp3.getNode()) {
1720 case TargetLowering::Expand:
1721 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1725 case ISD::VECTOR_SHUFFLE:
1726 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1727 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1728 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1730 // Allow targets to custom lower the SHUFFLEs they support.
1731 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1732 default: assert(0 && "Unknown operation action!");
1733 case TargetLowering::Legal:
1734 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1735 "vector shuffle should not be created if not legal!");
1737 case TargetLowering::Custom:
1738 Tmp3 = TLI.LowerOperation(Result, DAG);
1739 if (Tmp3.getNode()) {
1744 case TargetLowering::Expand: {
1745 MVT VT = Node->getValueType(0);
1746 MVT EltVT = VT.getVectorElementType();
1747 MVT PtrVT = TLI.getPointerTy();
1748 SDValue Mask = Node->getOperand(2);
1749 unsigned NumElems = Mask.getNumOperands();
1750 SmallVector<SDValue,8> Ops;
1751 for (unsigned i = 0; i != NumElems; ++i) {
1752 SDValue Arg = Mask.getOperand(i);
1753 if (Arg.getOpcode() == ISD::UNDEF) {
1754 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1756 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1757 unsigned Idx = cast<ConstantSDNode>(Arg)->getZExtValue();
1759 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1760 DAG.getConstant(Idx, PtrVT)));
1762 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1763 DAG.getConstant(Idx - NumElems, PtrVT)));
1766 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1769 case TargetLowering::Promote: {
1770 // Change base type to a different vector type.
1771 MVT OVT = Node->getValueType(0);
1772 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1774 // Cast the two input vectors.
1775 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1776 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1778 // Convert the shuffle mask to the right # elements.
1779 Tmp3 = SDValue(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1780 assert(Tmp3.getNode() && "Shuffle not legal?");
1781 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1782 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1788 case ISD::EXTRACT_VECTOR_ELT:
1789 Tmp1 = Node->getOperand(0);
1790 Tmp2 = LegalizeOp(Node->getOperand(1));
1791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1792 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1795 case ISD::EXTRACT_SUBVECTOR:
1796 Tmp1 = Node->getOperand(0);
1797 Tmp2 = LegalizeOp(Node->getOperand(1));
1798 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1799 Result = ExpandEXTRACT_SUBVECTOR(Result);
1802 case ISD::CONCAT_VECTORS: {
1803 // Use extract/insert/build vector for now. We might try to be
1804 // more clever later.
1805 MVT PtrVT = TLI.getPointerTy();
1806 SmallVector<SDValue, 8> Ops;
1807 unsigned NumOperands = Node->getNumOperands();
1808 for (unsigned i=0; i < NumOperands; ++i) {
1809 SDValue SubOp = Node->getOperand(i);
1810 MVT VVT = SubOp.getNode()->getValueType(0);
1811 MVT EltVT = VVT.getVectorElementType();
1812 unsigned NumSubElem = VVT.getVectorNumElements();
1813 for (unsigned j=0; j < NumSubElem; ++j) {
1814 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, SubOp,
1815 DAG.getConstant(j, PtrVT)));
1818 return LegalizeOp(DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
1819 &Ops[0], Ops.size()));
1822 case ISD::CALLSEQ_START: {
1823 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1825 // Recursively Legalize all of the inputs of the call end that do not lead
1826 // to this call start. This ensures that any libcalls that need be inserted
1827 // are inserted *before* the CALLSEQ_START.
1828 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1829 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1830 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1834 // Now that we legalized all of the inputs (which may have inserted
1835 // libcalls) create the new CALLSEQ_START node.
1836 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1838 // Merge in the last call, to ensure that this call start after the last
1840 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1841 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1842 Tmp1 = LegalizeOp(Tmp1);
1845 // Do not try to legalize the target-specific arguments (#1+).
1846 if (Tmp1 != Node->getOperand(0)) {
1847 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1849 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1852 // Remember that the CALLSEQ_START is legalized.
1853 AddLegalizedOperand(Op.getValue(0), Result);
1854 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1855 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1857 // Now that the callseq_start and all of the non-call nodes above this call
1858 // sequence have been legalized, legalize the call itself. During this
1859 // process, no libcalls can/will be inserted, guaranteeing that no calls
1861 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1862 // Note that we are selecting this call!
1863 LastCALLSEQ_END = SDValue(CallEnd, 0);
1864 IsLegalizingCall = true;
1866 // Legalize the call, starting from the CALLSEQ_END.
1867 LegalizeOp(LastCALLSEQ_END);
1868 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1871 case ISD::CALLSEQ_END:
1872 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1873 // will cause this node to be legalized as well as handling libcalls right.
1874 if (LastCALLSEQ_END.getNode() != Node) {
1875 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1876 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1877 assert(I != LegalizedNodes.end() &&
1878 "Legalizing the call start should have legalized this node!");
1882 // Otherwise, the call start has been legalized and everything is going
1883 // according to plan. Just legalize ourselves normally here.
1884 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1885 // Do not try to legalize the target-specific arguments (#1+), except for
1886 // an optional flag input.
1887 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1888 if (Tmp1 != Node->getOperand(0)) {
1889 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1891 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1894 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1895 if (Tmp1 != Node->getOperand(0) ||
1896 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1897 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1900 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1903 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1904 // This finishes up call legalization.
1905 IsLegalizingCall = false;
1907 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1908 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1909 if (Node->getNumValues() == 2)
1910 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1911 return Result.getValue(Op.getResNo());
1912 case ISD::DYNAMIC_STACKALLOC: {
1913 MVT VT = Node->getValueType(0);
1914 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1915 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1916 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1917 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1919 Tmp1 = Result.getValue(0);
1920 Tmp2 = Result.getValue(1);
1921 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1922 default: assert(0 && "This action is not supported yet!");
1923 case TargetLowering::Expand: {
1924 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1925 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1926 " not tell us which reg is the stack pointer!");
1927 SDValue Chain = Tmp1.getOperand(0);
1929 // Chain the dynamic stack allocation so that it doesn't modify the stack
1930 // pointer when other instructions are using the stack.
1931 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1933 SDValue Size = Tmp2.getOperand(1);
1934 SDValue SP = DAG.getCopyFromReg(Chain, SPReg, VT);
1935 Chain = SP.getValue(1);
1936 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1937 unsigned StackAlign =
1938 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1939 if (Align > StackAlign)
1940 SP = DAG.getNode(ISD::AND, VT, SP,
1941 DAG.getConstant(-(uint64_t)Align, VT));
1942 Tmp1 = DAG.getNode(ISD::SUB, VT, SP, Size); // Value
1943 Chain = DAG.getCopyToReg(Chain, SPReg, Tmp1); // Output chain
1945 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1946 DAG.getIntPtrConstant(0, true), SDValue());
1948 Tmp1 = LegalizeOp(Tmp1);
1949 Tmp2 = LegalizeOp(Tmp2);
1952 case TargetLowering::Custom:
1953 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1954 if (Tmp3.getNode()) {
1955 Tmp1 = LegalizeOp(Tmp3);
1956 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1959 case TargetLowering::Legal:
1962 // Since this op produce two values, make sure to remember that we
1963 // legalized both of them.
1964 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1965 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1966 return Op.getResNo() ? Tmp2 : Tmp1;
1968 case ISD::INLINEASM: {
1969 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1970 bool Changed = false;
1971 // Legalize all of the operands of the inline asm, in case they are nodes
1972 // that need to be expanded or something. Note we skip the asm string and
1973 // all of the TargetConstant flags.
1974 SDValue Op = LegalizeOp(Ops[0]);
1975 Changed = Op != Ops[0];
1978 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1979 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1980 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getZExtValue() >> 3;
1981 for (++i; NumVals; ++i, --NumVals) {
1982 SDValue Op = LegalizeOp(Ops[i]);
1991 Op = LegalizeOp(Ops.back());
1992 Changed |= Op != Ops.back();
1997 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1999 // INLINE asm returns a chain and flag, make sure to add both to the map.
2000 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2001 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2002 return Result.getValue(Op.getResNo());
2005 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2006 // Ensure that libcalls are emitted before a branch.
2007 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2008 Tmp1 = LegalizeOp(Tmp1);
2009 LastCALLSEQ_END = DAG.getEntryNode();
2011 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2014 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2015 // Ensure that libcalls are emitted before a branch.
2016 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2017 Tmp1 = LegalizeOp(Tmp1);
2018 LastCALLSEQ_END = DAG.getEntryNode();
2020 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2021 default: assert(0 && "Indirect target must be legal type (pointer)!");
2023 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2026 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2029 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2030 // Ensure that libcalls are emitted before a branch.
2031 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2032 Tmp1 = LegalizeOp(Tmp1);
2033 LastCALLSEQ_END = DAG.getEntryNode();
2035 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
2036 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2038 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
2039 default: assert(0 && "This action is not supported yet!");
2040 case TargetLowering::Legal: break;
2041 case TargetLowering::Custom:
2042 Tmp1 = TLI.LowerOperation(Result, DAG);
2043 if (Tmp1.getNode()) Result = Tmp1;
2045 case TargetLowering::Expand: {
2046 SDValue Chain = Result.getOperand(0);
2047 SDValue Table = Result.getOperand(1);
2048 SDValue Index = Result.getOperand(2);
2050 MVT PTy = TLI.getPointerTy();
2051 MachineFunction &MF = DAG.getMachineFunction();
2052 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2053 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
2054 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
2056 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2057 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, PTy, Chain, Addr,
2058 PseudoSourceValue::getJumpTable(), 0, MemVT);
2060 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2061 // For PIC, the sequence is:
2062 // BRIND(load(Jumptable + index) + RelocBase)
2063 // RelocBase can be JumpTable, GOT or some sort of global base.
2064 Addr = DAG.getNode(ISD::ADD, PTy, Addr,
2065 TLI.getPICJumpTableRelocBase(Table, DAG));
2067 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
2072 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2073 // Ensure that libcalls are emitted before a return.
2074 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2075 Tmp1 = LegalizeOp(Tmp1);
2076 LastCALLSEQ_END = DAG.getEntryNode();
2078 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2079 case Expand: assert(0 && "It's impossible to expand bools");
2081 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
2084 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
2086 // The top bits of the promoted condition are not necessarily zero, ensure
2087 // that the value is properly zero extended.
2088 unsigned BitWidth = Tmp2.getValueSizeInBits();
2089 if (!DAG.MaskedValueIsZero(Tmp2,
2090 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2091 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
2096 // Basic block destination (Op#2) is always legal.
2097 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2099 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
2100 default: assert(0 && "This action is not supported yet!");
2101 case TargetLowering::Legal: break;
2102 case TargetLowering::Custom:
2103 Tmp1 = TLI.LowerOperation(Result, DAG);
2104 if (Tmp1.getNode()) Result = Tmp1;
2106 case TargetLowering::Expand:
2107 // Expand brcond's setcc into its constituent parts and create a BR_CC
2109 if (Tmp2.getOpcode() == ISD::SETCC) {
2110 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
2111 Tmp2.getOperand(0), Tmp2.getOperand(1),
2112 Node->getOperand(2));
2114 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
2115 DAG.getCondCode(ISD::SETNE), Tmp2,
2116 DAG.getConstant(0, Tmp2.getValueType()),
2117 Node->getOperand(2));
2123 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2124 // Ensure that libcalls are emitted before a branch.
2125 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2126 Tmp1 = LegalizeOp(Tmp1);
2127 Tmp2 = Node->getOperand(2); // LHS
2128 Tmp3 = Node->getOperand(3); // RHS
2129 Tmp4 = Node->getOperand(1); // CC
2131 LegalizeSetCC(TLI.getSetCCResultType(Tmp2), Tmp2, Tmp3, Tmp4);
2132 LastCALLSEQ_END = DAG.getEntryNode();
2134 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
2135 // the LHS is a legal SETCC itself. In this case, we need to compare
2136 // the result against zero to select between true and false values.
2137 if (Tmp3.getNode() == 0) {
2138 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2139 Tmp4 = DAG.getCondCode(ISD::SETNE);
2142 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
2143 Node->getOperand(4));
2145 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
2146 default: assert(0 && "Unexpected action for BR_CC!");
2147 case TargetLowering::Legal: break;
2148 case TargetLowering::Custom:
2149 Tmp4 = TLI.LowerOperation(Result, DAG);
2150 if (Tmp4.getNode()) Result = Tmp4;
2155 LoadSDNode *LD = cast<LoadSDNode>(Node);
2156 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
2157 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
2159 ISD::LoadExtType ExtType = LD->getExtensionType();
2160 if (ExtType == ISD::NON_EXTLOAD) {
2161 MVT VT = Node->getValueType(0);
2162 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2163 Tmp3 = Result.getValue(0);
2164 Tmp4 = Result.getValue(1);
2166 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
2167 default: assert(0 && "This action is not supported yet!");
2168 case TargetLowering::Legal:
2169 // If this is an unaligned load and the target doesn't support it,
2171 if (!TLI.allowsUnalignedMemoryAccesses()) {
2172 unsigned ABIAlignment = TLI.getTargetData()->
2173 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2174 if (LD->getAlignment() < ABIAlignment){
2175 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2177 Tmp3 = Result.getOperand(0);
2178 Tmp4 = Result.getOperand(1);
2179 Tmp3 = LegalizeOp(Tmp3);
2180 Tmp4 = LegalizeOp(Tmp4);
2184 case TargetLowering::Custom:
2185 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
2186 if (Tmp1.getNode()) {
2187 Tmp3 = LegalizeOp(Tmp1);
2188 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2191 case TargetLowering::Promote: {
2192 // Only promote a load of vector type to another.
2193 assert(VT.isVector() && "Cannot promote this load!");
2194 // Change base type to a different vector type.
2195 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
2197 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
2198 LD->getSrcValueOffset(),
2199 LD->isVolatile(), LD->getAlignment());
2200 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
2201 Tmp4 = LegalizeOp(Tmp1.getValue(1));
2205 // Since loads produce two values, make sure to remember that we
2206 // legalized both of them.
2207 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
2208 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
2209 return Op.getResNo() ? Tmp4 : Tmp3;
2211 MVT SrcVT = LD->getMemoryVT();
2212 unsigned SrcWidth = SrcVT.getSizeInBits();
2213 int SVOffset = LD->getSrcValueOffset();
2214 unsigned Alignment = LD->getAlignment();
2215 bool isVolatile = LD->isVolatile();
2217 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
2218 // Some targets pretend to have an i1 loading operation, and actually
2219 // load an i8. This trick is correct for ZEXTLOAD because the top 7
2220 // bits are guaranteed to be zero; it helps the optimizers understand
2221 // that these bits are zero. It is also useful for EXTLOAD, since it
2222 // tells the optimizers that those bits are undefined. It would be
2223 // nice to have an effective generic way of getting these benefits...
2224 // Until such a way is found, don't insist on promoting i1 here.
2225 (SrcVT != MVT::i1 ||
2226 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
2227 // Promote to a byte-sized load if not loading an integral number of
2228 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
2229 unsigned NewWidth = SrcVT.getStoreSizeInBits();
2230 MVT NVT = MVT::getIntegerVT(NewWidth);
2233 // The extra bits are guaranteed to be zero, since we stored them that
2234 // way. A zext load from NVT thus automatically gives zext from SrcVT.
2236 ISD::LoadExtType NewExtType =
2237 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
2239 Result = DAG.getExtLoad(NewExtType, Node->getValueType(0),
2240 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
2241 NVT, isVolatile, Alignment);
2243 Ch = Result.getValue(1); // The chain.
2245 if (ExtType == ISD::SEXTLOAD)
2246 // Having the top bits zero doesn't help when sign extending.
2247 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2248 Result, DAG.getValueType(SrcVT));
2249 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
2250 // All the top bits are guaranteed to be zero - inform the optimizers.
2251 Result = DAG.getNode(ISD::AssertZext, Result.getValueType(), Result,
2252 DAG.getValueType(SrcVT));
2254 Tmp1 = LegalizeOp(Result);
2255 Tmp2 = LegalizeOp(Ch);
2256 } else if (SrcWidth & (SrcWidth - 1)) {
2257 // If not loading a power-of-2 number of bits, expand as two loads.
2258 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
2259 "Unsupported extload!");
2260 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
2261 assert(RoundWidth < SrcWidth);
2262 unsigned ExtraWidth = SrcWidth - RoundWidth;
2263 assert(ExtraWidth < RoundWidth);
2264 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2265 "Load size not an integral number of bytes!");
2266 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2267 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2269 unsigned IncrementSize;
2271 if (TLI.isLittleEndian()) {
2272 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
2273 // Load the bottom RoundWidth bits.
2274 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2275 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2278 // Load the remaining ExtraWidth bits.
2279 IncrementSize = RoundWidth / 8;
2280 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2281 DAG.getIntPtrConstant(IncrementSize));
2282 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2283 LD->getSrcValue(), SVOffset + IncrementSize,
2284 ExtraVT, isVolatile,
2285 MinAlign(Alignment, IncrementSize));
2287 // Build a factor node to remember that this load is independent of the
2289 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2292 // Move the top bits to the right place.
2293 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2294 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2296 // Join the hi and lo parts.
2297 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2299 // Big endian - avoid unaligned loads.
2300 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
2301 // Load the top RoundWidth bits.
2302 Hi = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
2303 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
2306 // Load the remaining ExtraWidth bits.
2307 IncrementSize = RoundWidth / 8;
2308 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2309 DAG.getIntPtrConstant(IncrementSize));
2310 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, Node->getValueType(0), Tmp1, Tmp2,
2311 LD->getSrcValue(), SVOffset + IncrementSize,
2312 ExtraVT, isVolatile,
2313 MinAlign(Alignment, IncrementSize));
2315 // Build a factor node to remember that this load is independent of the
2317 Ch = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
2320 // Move the top bits to the right place.
2321 Hi = DAG.getNode(ISD::SHL, Hi.getValueType(), Hi,
2322 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2324 // Join the hi and lo parts.
2325 Result = DAG.getNode(ISD::OR, Node->getValueType(0), Lo, Hi);
2328 Tmp1 = LegalizeOp(Result);
2329 Tmp2 = LegalizeOp(Ch);
2331 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
2332 default: assert(0 && "This action is not supported yet!");
2333 case TargetLowering::Custom:
2336 case TargetLowering::Legal:
2337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
2338 Tmp1 = Result.getValue(0);
2339 Tmp2 = Result.getValue(1);
2342 Tmp3 = TLI.LowerOperation(Result, DAG);
2343 if (Tmp3.getNode()) {
2344 Tmp1 = LegalizeOp(Tmp3);
2345 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2348 // If this is an unaligned load and the target doesn't support it,
2350 if (!TLI.allowsUnalignedMemoryAccesses()) {
2351 unsigned ABIAlignment = TLI.getTargetData()->
2352 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
2353 if (LD->getAlignment() < ABIAlignment){
2354 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
2356 Tmp1 = Result.getOperand(0);
2357 Tmp2 = Result.getOperand(1);
2358 Tmp1 = LegalizeOp(Tmp1);
2359 Tmp2 = LegalizeOp(Tmp2);
2364 case TargetLowering::Expand:
2365 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
2366 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
2367 SDValue Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
2368 LD->getSrcValueOffset(),
2369 LD->isVolatile(), LD->getAlignment());
2370 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
2371 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
2372 Tmp2 = LegalizeOp(Load.getValue(1));
2375 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
2376 // Turn the unsupported load into an EXTLOAD followed by an explicit
2377 // zero/sign extend inreg.
2378 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2379 Tmp1, Tmp2, LD->getSrcValue(),
2380 LD->getSrcValueOffset(), SrcVT,
2381 LD->isVolatile(), LD->getAlignment());
2383 if (ExtType == ISD::SEXTLOAD)
2384 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2385 Result, DAG.getValueType(SrcVT));
2387 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
2388 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
2389 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
2394 // Since loads produce two values, make sure to remember that we legalized
2396 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2397 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2398 return Op.getResNo() ? Tmp2 : Tmp1;
2401 case ISD::EXTRACT_ELEMENT: {
2402 MVT OpTy = Node->getOperand(0).getValueType();
2403 switch (getTypeAction(OpTy)) {
2404 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
2406 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2408 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
2409 DAG.getConstant(OpTy.getSizeInBits()/2,
2410 TLI.getShiftAmountTy()));
2411 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
2414 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
2415 Node->getOperand(0));
2419 // Get both the low and high parts.
2420 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2421 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
2422 Result = Tmp2; // 1 -> Hi
2424 Result = Tmp1; // 0 -> Lo
2430 case ISD::CopyToReg:
2431 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2433 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
2434 "Register type must be legal!");
2435 // Legalize the incoming value (must be a legal type).
2436 Tmp2 = LegalizeOp(Node->getOperand(2));
2437 if (Node->getNumValues() == 1) {
2438 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
2440 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
2441 if (Node->getNumOperands() == 4) {
2442 Tmp3 = LegalizeOp(Node->getOperand(3));
2443 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
2446 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
2449 // Since this produces two values, make sure to remember that we legalized
2451 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
2452 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
2458 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2460 // Ensure that libcalls are emitted before a return.
2461 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
2462 Tmp1 = LegalizeOp(Tmp1);
2463 LastCALLSEQ_END = DAG.getEntryNode();
2465 switch (Node->getNumOperands()) {
2467 Tmp2 = Node->getOperand(1);
2468 Tmp3 = Node->getOperand(2); // Signness
2469 switch (getTypeAction(Tmp2.getValueType())) {
2471 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
2474 if (!Tmp2.getValueType().isVector()) {
2476 ExpandOp(Tmp2, Lo, Hi);
2478 // Big endian systems want the hi reg first.
2479 if (TLI.isBigEndian())
2483 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2485 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
2486 Result = LegalizeOp(Result);
2488 SDNode *InVal = Tmp2.getNode();
2489 int InIx = Tmp2.getResNo();
2490 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
2491 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
2493 // Figure out if there is a simple type corresponding to this Vector
2494 // type. If so, convert to the vector type.
2495 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2496 if (TLI.isTypeLegal(TVT)) {
2497 // Turn this into a return of the vector type.
2498 Tmp2 = LegalizeOp(Tmp2);
2499 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2500 } else if (NumElems == 1) {
2501 // Turn this into a return of the scalar type.
2502 Tmp2 = ScalarizeVectorOp(Tmp2);
2503 Tmp2 = LegalizeOp(Tmp2);
2504 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2506 // FIXME: Returns of gcc generic vectors smaller than a legal type
2507 // should be returned in integer registers!
2509 // The scalarized value type may not be legal, e.g. it might require
2510 // promotion or expansion. Relegalize the return.
2511 Result = LegalizeOp(Result);
2513 // FIXME: Returns of gcc generic vectors larger than a legal vector
2514 // type should be returned by reference!
2516 SplitVectorOp(Tmp2, Lo, Hi);
2517 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
2518 Result = LegalizeOp(Result);
2523 Tmp2 = PromoteOp(Node->getOperand(1));
2524 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2525 Result = LegalizeOp(Result);
2530 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2532 default: { // ret <values>
2533 SmallVector<SDValue, 8> NewValues;
2534 NewValues.push_back(Tmp1);
2535 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
2536 switch (getTypeAction(Node->getOperand(i).getValueType())) {
2538 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
2539 NewValues.push_back(Node->getOperand(i+1));
2543 assert(!Node->getOperand(i).getValueType().isExtended() &&
2544 "FIXME: TODO: implement returning non-legal vector types!");
2545 ExpandOp(Node->getOperand(i), Lo, Hi);
2546 NewValues.push_back(Lo);
2547 NewValues.push_back(Node->getOperand(i+1));
2549 NewValues.push_back(Hi);
2550 NewValues.push_back(Node->getOperand(i+1));
2555 assert(0 && "Can't promote multiple return value yet!");
2558 if (NewValues.size() == Node->getNumOperands())
2559 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
2561 Result = DAG.getNode(ISD::RET, MVT::Other,
2562 &NewValues[0], NewValues.size());
2567 if (Result.getOpcode() == ISD::RET) {
2568 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
2569 default: assert(0 && "This action is not supported yet!");
2570 case TargetLowering::Legal: break;
2571 case TargetLowering::Custom:
2572 Tmp1 = TLI.LowerOperation(Result, DAG);
2573 if (Tmp1.getNode()) Result = Tmp1;
2579 StoreSDNode *ST = cast<StoreSDNode>(Node);
2580 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
2581 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
2582 int SVOffset = ST->getSrcValueOffset();
2583 unsigned Alignment = ST->getAlignment();
2584 bool isVolatile = ST->isVolatile();
2586 if (!ST->isTruncatingStore()) {
2587 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
2588 // FIXME: We shouldn't do this for TargetConstantFP's.
2589 // FIXME: move this to the DAG Combiner! Note that we can't regress due
2590 // to phase ordering between legalized code and the dag combiner. This
2591 // probably means that we need to integrate dag combiner and legalizer
2593 // We generally can't do this one for long doubles.
2594 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
2595 if (CFP->getValueType(0) == MVT::f32 &&
2596 getTypeAction(MVT::i32) == Legal) {
2597 Tmp3 = DAG.getConstant(CFP->getValueAPF().
2598 bitcastToAPInt().zextOrTrunc(32),
2600 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2601 SVOffset, isVolatile, Alignment);
2603 } else if (CFP->getValueType(0) == MVT::f64) {
2604 // If this target supports 64-bit registers, do a single 64-bit store.
2605 if (getTypeAction(MVT::i64) == Legal) {
2606 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
2607 zextOrTrunc(64), MVT::i64);
2608 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2609 SVOffset, isVolatile, Alignment);
2611 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
2612 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
2613 // stores. If the target supports neither 32- nor 64-bits, this
2614 // xform is certainly not worth it.
2615 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
2616 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
2617 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
2618 if (TLI.isBigEndian()) std::swap(Lo, Hi);
2620 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2621 SVOffset, isVolatile, Alignment);
2622 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2623 DAG.getIntPtrConstant(4));
2624 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
2625 isVolatile, MinAlign(Alignment, 4U));
2627 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2633 switch (getTypeAction(ST->getMemoryVT())) {
2635 Tmp3 = LegalizeOp(ST->getValue());
2636 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2639 MVT VT = Tmp3.getValueType();
2640 switch (TLI.getOperationAction(ISD::STORE, VT)) {
2641 default: assert(0 && "This action is not supported yet!");
2642 case TargetLowering::Legal:
2643 // If this is an unaligned store and the target doesn't support it,
2645 if (!TLI.allowsUnalignedMemoryAccesses()) {
2646 unsigned ABIAlignment = TLI.getTargetData()->
2647 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2648 if (ST->getAlignment() < ABIAlignment)
2649 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2653 case TargetLowering::Custom:
2654 Tmp1 = TLI.LowerOperation(Result, DAG);
2655 if (Tmp1.getNode()) Result = Tmp1;
2657 case TargetLowering::Promote:
2658 assert(VT.isVector() && "Unknown legal promote case!");
2659 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
2660 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
2661 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
2662 ST->getSrcValue(), SVOffset, isVolatile,
2669 if (!ST->getMemoryVT().isVector()) {
2670 // Truncate the value and store the result.
2671 Tmp3 = PromoteOp(ST->getValue());
2672 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2673 SVOffset, ST->getMemoryVT(),
2674 isVolatile, Alignment);
2677 // Fall thru to expand for vector
2679 unsigned IncrementSize = 0;
2682 // If this is a vector type, then we have to calculate the increment as
2683 // the product of the element size in bytes, and the number of elements
2684 // in the high half of the vector.
2685 if (ST->getValue().getValueType().isVector()) {
2686 SDNode *InVal = ST->getValue().getNode();
2687 int InIx = ST->getValue().getResNo();
2688 MVT InVT = InVal->getValueType(InIx);
2689 unsigned NumElems = InVT.getVectorNumElements();
2690 MVT EVT = InVT.getVectorElementType();
2692 // Figure out if there is a simple type corresponding to this Vector
2693 // type. If so, convert to the vector type.
2694 MVT TVT = MVT::getVectorVT(EVT, NumElems);
2695 if (TLI.isTypeLegal(TVT)) {
2696 // Turn this into a normal store of the vector type.
2697 Tmp3 = LegalizeOp(ST->getValue());
2698 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2699 SVOffset, isVolatile, Alignment);
2700 Result = LegalizeOp(Result);
2702 } else if (NumElems == 1) {
2703 // Turn this into a normal store of the scalar type.
2704 Tmp3 = ScalarizeVectorOp(ST->getValue());
2705 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2706 SVOffset, isVolatile, Alignment);
2707 // The scalarized value type may not be legal, e.g. it might require
2708 // promotion or expansion. Relegalize the scalar store.
2709 Result = LegalizeOp(Result);
2712 // Check if we have widen this node with another value
2713 std::map<SDValue, SDValue>::iterator I =
2714 WidenNodes.find(ST->getValue());
2715 if (I != WidenNodes.end()) {
2716 Result = StoreWidenVectorOp(ST, Tmp1, Tmp2);
2720 SplitVectorOp(ST->getValue(), Lo, Hi);
2721 IncrementSize = Lo.getNode()->getValueType(0).getVectorNumElements() *
2722 EVT.getSizeInBits()/8;
2726 ExpandOp(ST->getValue(), Lo, Hi);
2727 IncrementSize = Hi.getNode() ? Hi.getValueType().getSizeInBits()/8 : 0;
2729 if (Hi.getNode() && TLI.isBigEndian())
2733 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
2734 SVOffset, isVolatile, Alignment);
2736 if (Hi.getNode() == NULL) {
2737 // Must be int <-> float one-to-one expansion.
2742 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2743 DAG.getIntPtrConstant(IncrementSize));
2744 assert(isTypeLegal(Tmp2.getValueType()) &&
2745 "Pointers must be legal!");
2746 SVOffset += IncrementSize;
2747 Alignment = MinAlign(Alignment, IncrementSize);
2748 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2749 SVOffset, isVolatile, Alignment);
2750 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2755 switch (getTypeAction(ST->getValue().getValueType())) {
2757 Tmp3 = LegalizeOp(ST->getValue());
2760 if (!ST->getValue().getValueType().isVector()) {
2761 // We can promote the value, the truncstore will still take care of it.
2762 Tmp3 = PromoteOp(ST->getValue());
2765 // Vector case falls through to expand
2767 // Just store the low part. This may become a non-trunc store, so make
2768 // sure to use getTruncStore, not UpdateNodeOperands below.
2769 ExpandOp(ST->getValue(), Tmp3, Tmp4);
2770 return DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2771 SVOffset, MVT::i8, isVolatile, Alignment);
2774 MVT StVT = ST->getMemoryVT();
2775 unsigned StWidth = StVT.getSizeInBits();
2777 if (StWidth != StVT.getStoreSizeInBits()) {
2778 // Promote to a byte-sized store with upper bits zero if not
2779 // storing an integral number of bytes. For example, promote
2780 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
2781 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
2782 Tmp3 = DAG.getZeroExtendInReg(Tmp3, StVT);
2783 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2784 SVOffset, NVT, isVolatile, Alignment);
2785 } else if (StWidth & (StWidth - 1)) {
2786 // If not storing a power-of-2 number of bits, expand as two stores.
2787 assert(StVT.isExtended() && !StVT.isVector() &&
2788 "Unsupported truncstore!");
2789 unsigned RoundWidth = 1 << Log2_32(StWidth);
2790 assert(RoundWidth < StWidth);
2791 unsigned ExtraWidth = StWidth - RoundWidth;
2792 assert(ExtraWidth < RoundWidth);
2793 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
2794 "Store size not an integral number of bytes!");
2795 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
2796 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
2798 unsigned IncrementSize;
2800 if (TLI.isLittleEndian()) {
2801 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
2802 // Store the bottom RoundWidth bits.
2803 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2805 isVolatile, Alignment);
2807 // Store the remaining ExtraWidth bits.
2808 IncrementSize = RoundWidth / 8;
2809 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2810 DAG.getIntPtrConstant(IncrementSize));
2811 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2812 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
2813 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
2814 SVOffset + IncrementSize, ExtraVT, isVolatile,
2815 MinAlign(Alignment, IncrementSize));
2817 // Big endian - avoid unaligned stores.
2818 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
2819 // Store the top RoundWidth bits.
2820 Hi = DAG.getNode(ISD::SRL, Tmp3.getValueType(), Tmp3,
2821 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
2822 Hi = DAG.getTruncStore(Tmp1, Hi, Tmp2, ST->getSrcValue(), SVOffset,
2823 RoundVT, isVolatile, Alignment);
2825 // Store the remaining ExtraWidth bits.
2826 IncrementSize = RoundWidth / 8;
2827 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
2828 DAG.getIntPtrConstant(IncrementSize));
2829 Lo = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
2830 SVOffset + IncrementSize, ExtraVT, isVolatile,
2831 MinAlign(Alignment, IncrementSize));
2834 // The order of the stores doesn't matter.
2835 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
2837 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
2838 Tmp2 != ST->getBasePtr())
2839 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
2842 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
2843 default: assert(0 && "This action is not supported yet!");
2844 case TargetLowering::Legal:
2845 // If this is an unaligned store and the target doesn't support it,
2847 if (!TLI.allowsUnalignedMemoryAccesses()) {
2848 unsigned ABIAlignment = TLI.getTargetData()->
2849 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
2850 if (ST->getAlignment() < ABIAlignment)
2851 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
2855 case TargetLowering::Custom:
2856 Result = TLI.LowerOperation(Result, DAG);
2859 // TRUNCSTORE:i16 i32 -> STORE i16
2860 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
2861 Tmp3 = DAG.getNode(ISD::TRUNCATE, StVT, Tmp3);
2862 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(), SVOffset,
2863 isVolatile, Alignment);
2871 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2872 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2874 case ISD::STACKSAVE:
2875 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2876 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2877 Tmp1 = Result.getValue(0);
2878 Tmp2 = Result.getValue(1);
2880 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
2881 default: assert(0 && "This action is not supported yet!");
2882 case TargetLowering::Legal: break;
2883 case TargetLowering::Custom:
2884 Tmp3 = TLI.LowerOperation(Result, DAG);
2885 if (Tmp3.getNode()) {
2886 Tmp1 = LegalizeOp(Tmp3);
2887 Tmp2 = LegalizeOp(Tmp3.getValue(1));
2890 case TargetLowering::Expand:
2891 // Expand to CopyFromReg if the target set
2892 // StackPointerRegisterToSaveRestore.
2893 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2894 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
2895 Node->getValueType(0));
2896 Tmp2 = Tmp1.getValue(1);
2898 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
2899 Tmp2 = Node->getOperand(0);
2904 // Since stacksave produce two values, make sure to remember that we
2905 // legalized both of them.
2906 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2907 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2908 return Op.getResNo() ? Tmp2 : Tmp1;
2910 case ISD::STACKRESTORE:
2911 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2912 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2913 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2915 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
2916 default: assert(0 && "This action is not supported yet!");
2917 case TargetLowering::Legal: break;
2918 case TargetLowering::Custom:
2919 Tmp1 = TLI.LowerOperation(Result, DAG);
2920 if (Tmp1.getNode()) Result = Tmp1;
2922 case TargetLowering::Expand:
2923 // Expand to CopyToReg if the target set
2924 // StackPointerRegisterToSaveRestore.
2925 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2926 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
2934 case ISD::READCYCLECOUNTER:
2935 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
2936 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2937 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
2938 Node->getValueType(0))) {
2939 default: assert(0 && "This action is not supported yet!");
2940 case TargetLowering::Legal:
2941 Tmp1 = Result.getValue(0);
2942 Tmp2 = Result.getValue(1);
2944 case TargetLowering::Custom:
2945 Result = TLI.LowerOperation(Result, DAG);
2946 Tmp1 = LegalizeOp(Result.getValue(0));
2947 Tmp2 = LegalizeOp(Result.getValue(1));
2951 // Since rdcc produce two values, make sure to remember that we legalized
2953 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
2954 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
2958 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2959 case Expand: assert(0 && "It's impossible to expand bools");
2961 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2964 assert(!Node->getOperand(0).getValueType().isVector() && "not possible");
2965 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2966 // Make sure the condition is either zero or one.
2967 unsigned BitWidth = Tmp1.getValueSizeInBits();
2968 if (!DAG.MaskedValueIsZero(Tmp1,
2969 APInt::getHighBitsSet(BitWidth, BitWidth-1)))
2970 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2974 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2975 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2977 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2979 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2980 default: assert(0 && "This action is not supported yet!");
2981 case TargetLowering::Legal: break;
2982 case TargetLowering::Custom: {
2983 Tmp1 = TLI.LowerOperation(Result, DAG);
2984 if (Tmp1.getNode()) Result = Tmp1;
2987 case TargetLowering::Expand:
2988 if (Tmp1.getOpcode() == ISD::SETCC) {
2989 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2991 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2993 Result = DAG.getSelectCC(Tmp1,
2994 DAG.getConstant(0, Tmp1.getValueType()),
2995 Tmp2, Tmp3, ISD::SETNE);
2998 case TargetLowering::Promote: {
3000 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
3001 unsigned ExtOp, TruncOp;
3002 if (Tmp2.getValueType().isVector()) {
3003 ExtOp = ISD::BIT_CONVERT;
3004 TruncOp = ISD::BIT_CONVERT;
3005 } else if (Tmp2.getValueType().isInteger()) {
3006 ExtOp = ISD::ANY_EXTEND;
3007 TruncOp = ISD::TRUNCATE;
3009 ExtOp = ISD::FP_EXTEND;
3010 TruncOp = ISD::FP_ROUND;
3012 // Promote each of the values to the new type.
3013 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
3014 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
3015 // Perform the larger operation, then round down.
3016 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
3017 if (TruncOp != ISD::FP_ROUND)
3018 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
3020 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result,
3021 DAG.getIntPtrConstant(0));
3026 case ISD::SELECT_CC: {
3027 Tmp1 = Node->getOperand(0); // LHS
3028 Tmp2 = Node->getOperand(1); // RHS
3029 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
3030 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
3031 SDValue CC = Node->getOperand(4);
3033 LegalizeSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2, CC);
3035 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
3036 // the LHS is a legal SETCC itself. In this case, we need to compare
3037 // the result against zero to select between true and false values.
3038 if (Tmp2.getNode() == 0) {
3039 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3040 CC = DAG.getCondCode(ISD::SETNE);
3042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
3044 // Everything is legal, see if we should expand this op or something.
3045 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
3046 default: assert(0 && "This action is not supported yet!");
3047 case TargetLowering::Legal: break;
3048 case TargetLowering::Custom:
3049 Tmp1 = TLI.LowerOperation(Result, DAG);
3050 if (Tmp1.getNode()) Result = Tmp1;
3056 Tmp1 = Node->getOperand(0);
3057 Tmp2 = Node->getOperand(1);
3058 Tmp3 = Node->getOperand(2);
3059 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3);
3061 // If we had to Expand the SetCC operands into a SELECT node, then it may
3062 // not always be possible to return a true LHS & RHS. In this case, just
3063 // return the value we legalized, returned in the LHS
3064 if (Tmp2.getNode() == 0) {
3069 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
3070 default: assert(0 && "Cannot handle this action for SETCC yet!");
3071 case TargetLowering::Custom:
3074 case TargetLowering::Legal:
3075 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3077 Tmp4 = TLI.LowerOperation(Result, DAG);
3078 if (Tmp4.getNode()) Result = Tmp4;
3081 case TargetLowering::Promote: {
3082 // First step, figure out the appropriate operation to use.
3083 // Allow SETCC to not be supported for all legal data types
3084 // Mostly this targets FP
3085 MVT NewInTy = Node->getOperand(0).getValueType();
3086 MVT OldVT = NewInTy; OldVT = OldVT;
3088 // Scan for the appropriate larger type to use.
3090 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3092 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3093 "Fell off of the edge of the integer world");
3094 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3095 "Fell off of the edge of the floating point world");
3097 // If the target supports SETCC of this type, use it.
3098 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
3101 if (NewInTy.isInteger())
3102 assert(0 && "Cannot promote Legal Integer SETCC yet");
3104 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
3105 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
3107 Tmp1 = LegalizeOp(Tmp1);
3108 Tmp2 = LegalizeOp(Tmp2);
3109 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3110 Result = LegalizeOp(Result);
3113 case TargetLowering::Expand:
3114 // Expand a setcc node into a select_cc of the same condition, lhs, and
3115 // rhs that selects between const 1 (true) and const 0 (false).
3116 MVT VT = Node->getValueType(0);
3117 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
3118 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
3124 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3125 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3126 SDValue CC = Node->getOperand(2);
3128 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, CC);
3130 // Everything is legal, see if we should expand this op or something.
3131 switch (TLI.getOperationAction(ISD::VSETCC, Tmp1.getValueType())) {
3132 default: assert(0 && "This action is not supported yet!");
3133 case TargetLowering::Legal: break;
3134 case TargetLowering::Custom:
3135 Tmp1 = TLI.LowerOperation(Result, DAG);
3136 if (Tmp1.getNode()) Result = Tmp1;
3138 case TargetLowering::Expand: {
3139 // Unroll into a nasty set of scalar code for now.
3140 MVT VT = Node->getValueType(0);
3141 unsigned NumElems = VT.getVectorNumElements();
3142 MVT EltVT = VT.getVectorElementType();
3143 MVT TmpEltVT = Tmp1.getValueType().getVectorElementType();
3144 SmallVector<SDValue, 8> Ops(NumElems);
3145 for (unsigned i = 0; i < NumElems; ++i) {
3146 SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3147 Tmp1, DAG.getIntPtrConstant(i));
3148 Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
3149 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
3150 Tmp2, DAG.getIntPtrConstant(i)),
3152 Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
3153 DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
3154 DAG.getConstant(0, EltVT));
3156 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
3163 case ISD::SHL_PARTS:
3164 case ISD::SRA_PARTS:
3165 case ISD::SRL_PARTS: {
3166 SmallVector<SDValue, 8> Ops;
3167 bool Changed = false;
3168 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3169 Ops.push_back(LegalizeOp(Node->getOperand(i)));
3170 Changed |= Ops.back() != Node->getOperand(i);
3173 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
3175 switch (TLI.getOperationAction(Node->getOpcode(),
3176 Node->getValueType(0))) {
3177 default: assert(0 && "This action is not supported yet!");
3178 case TargetLowering::Legal: break;
3179 case TargetLowering::Custom:
3180 Tmp1 = TLI.LowerOperation(Result, DAG);
3181 if (Tmp1.getNode()) {
3182 SDValue Tmp2, RetVal(0, 0);
3183 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
3184 Tmp2 = LegalizeOp(Tmp1.getValue(i));
3185 AddLegalizedOperand(SDValue(Node, i), Tmp2);
3186 if (i == Op.getResNo())
3189 assert(RetVal.getNode() && "Illegal result number");
3195 // Since these produce multiple values, make sure to remember that we
3196 // legalized all of them.
3197 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3198 AddLegalizedOperand(SDValue(Node, i), Result.getValue(i));
3199 return Result.getValue(Op.getResNo());
3221 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3222 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3223 case Expand: assert(0 && "Not possible");
3225 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3228 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3232 if ((Node->getOpcode() == ISD::SHL ||
3233 Node->getOpcode() == ISD::SRL ||
3234 Node->getOpcode() == ISD::SRA) &&
3235 !Node->getValueType(0).isVector()) {
3236 Tmp2 = LegalizeShiftAmount(Tmp2);
3239 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3241 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3242 default: assert(0 && "BinOp legalize operation not supported");
3243 case TargetLowering::Legal: break;
3244 case TargetLowering::Custom:
3245 Tmp1 = TLI.LowerOperation(Result, DAG);
3246 if (Tmp1.getNode()) {
3250 // Fall through if the custom lower can't deal with the operation
3251 case TargetLowering::Expand: {
3252 MVT VT = Op.getValueType();
3254 // See if multiply or divide can be lowered using two-result operations.
3255 SDVTList VTs = DAG.getVTList(VT, VT);
3256 if (Node->getOpcode() == ISD::MUL) {
3257 // We just need the low half of the multiply; try both the signed
3258 // and unsigned forms. If the target supports both SMUL_LOHI and
3259 // UMUL_LOHI, form a preference by checking which forms of plain
3260 // MULH it supports.
3261 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, VT);
3262 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, VT);
3263 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, VT);
3264 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, VT);
3265 unsigned OpToUse = 0;
3266 if (HasSMUL_LOHI && !HasMULHS) {
3267 OpToUse = ISD::SMUL_LOHI;
3268 } else if (HasUMUL_LOHI && !HasMULHU) {
3269 OpToUse = ISD::UMUL_LOHI;
3270 } else if (HasSMUL_LOHI) {
3271 OpToUse = ISD::SMUL_LOHI;
3272 } else if (HasUMUL_LOHI) {
3273 OpToUse = ISD::UMUL_LOHI;
3276 Result = SDValue(DAG.getNode(OpToUse, VTs, Tmp1, Tmp2).getNode(), 0);
3280 if (Node->getOpcode() == ISD::MULHS &&
3281 TLI.isOperationLegal(ISD::SMUL_LOHI, VT)) {
3282 Result = SDValue(DAG.getNode(ISD::SMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3286 if (Node->getOpcode() == ISD::MULHU &&
3287 TLI.isOperationLegal(ISD::UMUL_LOHI, VT)) {
3288 Result = SDValue(DAG.getNode(ISD::UMUL_LOHI, VTs, Tmp1, Tmp2).getNode(),
3292 if (Node->getOpcode() == ISD::SDIV &&
3293 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3294 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(),
3298 if (Node->getOpcode() == ISD::UDIV &&
3299 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3300 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(),
3305 // Check to see if we have a libcall for this operator.
3306 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3307 bool isSigned = false;
3308 switch (Node->getOpcode()) {
3311 if (VT == MVT::i32) {
3312 LC = Node->getOpcode() == ISD::UDIV
3313 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
3314 isSigned = Node->getOpcode() == ISD::SDIV;
3319 LC = RTLIB::MUL_I32;
3322 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
3323 RTLIB::POW_PPCF128);
3327 if (LC != RTLIB::UNKNOWN_LIBCALL) {
3329 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3333 assert(Node->getValueType(0).isVector() &&
3334 "Cannot expand this binary operator!");
3335 // Expand the operation into a bunch of nasty scalar code.
3336 Result = LegalizeOp(UnrollVectorOp(Op));
3339 case TargetLowering::Promote: {
3340 switch (Node->getOpcode()) {
3341 default: assert(0 && "Do not know how to promote this BinOp!");
3345 MVT OVT = Node->getValueType(0);
3346 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3347 assert(OVT.isVector() && "Cannot promote this BinOp!");
3348 // Bit convert each of the values to the new type.
3349 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
3350 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
3351 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3352 // Bit convert the result back the original type.
3353 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
3361 case ISD::SMUL_LOHI:
3362 case ISD::UMUL_LOHI:
3365 // These nodes will only be produced by target-specific lowering, so
3366 // they shouldn't be here if they aren't legal.
3367 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
3368 "This must be legal!");
3370 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3371 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3372 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3375 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
3376 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3377 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3378 case Expand: assert(0 && "Not possible");
3380 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
3383 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
3387 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3389 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3390 default: assert(0 && "Operation not supported");
3391 case TargetLowering::Custom:
3392 Tmp1 = TLI.LowerOperation(Result, DAG);
3393 if (Tmp1.getNode()) Result = Tmp1;
3395 case TargetLowering::Legal: break;
3396 case TargetLowering::Expand: {
3397 // If this target supports fabs/fneg natively and select is cheap,
3398 // do this efficiently.
3399 if (!TLI.isSelectExpensive() &&
3400 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
3401 TargetLowering::Legal &&
3402 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
3403 TargetLowering::Legal) {
3404 // Get the sign bit of the RHS.
3406 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
3407 SDValue SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
3408 SignBit = DAG.getSetCC(TLI.getSetCCResultType(SignBit),
3409 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
3410 // Get the absolute value of the result.
3411 SDValue AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
3412 // Select between the nabs and abs value based on the sign bit of
3414 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
3415 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
3418 Result = LegalizeOp(Result);
3422 // Otherwise, do bitwise ops!
3424 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
3425 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
3426 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
3427 Result = LegalizeOp(Result);
3435 Tmp1 = LegalizeOp(Node->getOperand(0));
3436 Tmp2 = LegalizeOp(Node->getOperand(1));
3437 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3438 Tmp3 = Result.getValue(0);
3439 Tmp4 = Result.getValue(1);
3441 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3442 default: assert(0 && "This action is not supported yet!");
3443 case TargetLowering::Legal:
3445 case TargetLowering::Custom:
3446 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3447 if (Tmp1.getNode() != NULL) {
3448 Tmp3 = LegalizeOp(Tmp1);
3449 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3453 // Since this produces two values, make sure to remember that we legalized
3455 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3456 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3457 return Op.getResNo() ? Tmp4 : Tmp3;
3461 Tmp1 = LegalizeOp(Node->getOperand(0));
3462 Tmp2 = LegalizeOp(Node->getOperand(1));
3463 Tmp3 = LegalizeOp(Node->getOperand(2));
3464 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
3465 Tmp3 = Result.getValue(0);
3466 Tmp4 = Result.getValue(1);
3468 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3469 default: assert(0 && "This action is not supported yet!");
3470 case TargetLowering::Legal:
3472 case TargetLowering::Custom:
3473 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
3474 if (Tmp1.getNode() != NULL) {
3475 Tmp3 = LegalizeOp(Tmp1);
3476 Tmp4 = LegalizeOp(Tmp1.getValue(1));
3480 // Since this produces two values, make sure to remember that we legalized
3482 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
3483 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
3484 return Op.getResNo() ? Tmp4 : Tmp3;
3486 case ISD::BUILD_PAIR: {
3487 MVT PairTy = Node->getValueType(0);
3488 // TODO: handle the case where the Lo and Hi operands are not of legal type
3489 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
3490 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
3491 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
3492 case TargetLowering::Promote:
3493 case TargetLowering::Custom:
3494 assert(0 && "Cannot promote/custom this yet!");
3495 case TargetLowering::Legal:
3496 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
3497 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
3499 case TargetLowering::Expand:
3500 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
3501 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
3502 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
3503 DAG.getConstant(PairTy.getSizeInBits()/2,
3504 TLI.getShiftAmountTy()));
3505 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
3514 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3515 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3517 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3518 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
3519 case TargetLowering::Custom:
3522 case TargetLowering::Legal:
3523 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3525 Tmp1 = TLI.LowerOperation(Result, DAG);
3526 if (Tmp1.getNode()) Result = Tmp1;
3529 case TargetLowering::Expand: {
3530 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
3531 bool isSigned = DivOpc == ISD::SDIV;
3532 MVT VT = Node->getValueType(0);
3534 // See if remainder can be lowered using two-result operations.
3535 SDVTList VTs = DAG.getVTList(VT, VT);
3536 if (Node->getOpcode() == ISD::SREM &&
3537 TLI.isOperationLegal(ISD::SDIVREM, VT)) {
3538 Result = SDValue(DAG.getNode(ISD::SDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3541 if (Node->getOpcode() == ISD::UREM &&
3542 TLI.isOperationLegal(ISD::UDIVREM, VT)) {
3543 Result = SDValue(DAG.getNode(ISD::UDIVREM, VTs, Tmp1, Tmp2).getNode(), 1);
3547 if (VT.isInteger()) {
3548 if (TLI.getOperationAction(DivOpc, VT) ==
3549 TargetLowering::Legal) {
3551 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
3552 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
3553 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
3554 } else if (VT.isVector()) {
3555 Result = LegalizeOp(UnrollVectorOp(Op));
3557 assert(VT == MVT::i32 &&
3558 "Cannot expand this binary operator!");
3559 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
3560 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
3562 Result = ExpandLibCall(LC, Node, isSigned, Dummy);
3565 assert(VT.isFloatingPoint() &&
3566 "remainder op must have integer or floating-point type");
3567 if (VT.isVector()) {
3568 Result = LegalizeOp(UnrollVectorOp(Op));
3570 // Floating point mod -> fmod libcall.
3571 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::REM_F32, RTLIB::REM_F64,
3572 RTLIB::REM_F80, RTLIB::REM_PPCF128);
3574 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3582 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3583 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3585 MVT VT = Node->getValueType(0);
3586 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
3587 default: assert(0 && "This action is not supported yet!");
3588 case TargetLowering::Custom:
3591 case TargetLowering::Legal:
3592 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3593 Result = Result.getValue(0);
3594 Tmp1 = Result.getValue(1);
3597 Tmp2 = TLI.LowerOperation(Result, DAG);
3598 if (Tmp2.getNode()) {
3599 Result = LegalizeOp(Tmp2);
3600 Tmp1 = LegalizeOp(Tmp2.getValue(1));
3604 case TargetLowering::Expand: {
3605 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3606 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
3607 // Increment the pointer, VAList, to the next vaarg
3608 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3609 DAG.getConstant(TLI.getTargetData()->getABITypeSize(VT.getTypeForMVT()),
3610 TLI.getPointerTy()));
3611 // Store the incremented VAList to the legalized pointer
3612 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
3613 // Load the actual argument out of the pointer VAList
3614 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
3615 Tmp1 = LegalizeOp(Result.getValue(1));
3616 Result = LegalizeOp(Result);
3620 // Since VAARG produces two values, make sure to remember that we
3621 // legalized both of them.
3622 AddLegalizedOperand(SDValue(Node, 0), Result);
3623 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
3624 return Op.getResNo() ? Tmp1 : Result;
3628 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3629 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
3630 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
3632 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
3633 default: assert(0 && "This action is not supported yet!");
3634 case TargetLowering::Custom:
3637 case TargetLowering::Legal:
3638 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
3639 Node->getOperand(3), Node->getOperand(4));
3641 Tmp1 = TLI.LowerOperation(Result, DAG);
3642 if (Tmp1.getNode()) Result = Tmp1;
3645 case TargetLowering::Expand:
3646 // This defaults to loading a pointer from the input and storing it to the
3647 // output, returning the chain.
3648 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3649 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3650 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, VS, 0);
3651 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, VD, 0);
3657 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3658 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3660 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
3661 default: assert(0 && "This action is not supported yet!");
3662 case TargetLowering::Custom:
3665 case TargetLowering::Legal:
3666 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3668 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
3669 if (Tmp1.getNode()) Result = Tmp1;
3672 case TargetLowering::Expand:
3673 Result = Tmp1; // Default to a no-op, return the chain
3679 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
3680 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
3682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
3684 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
3685 default: assert(0 && "This action is not supported yet!");
3686 case TargetLowering::Legal: break;
3687 case TargetLowering::Custom:
3688 Tmp1 = TLI.LowerOperation(Result, DAG);
3689 if (Tmp1.getNode()) Result = Tmp1;
3696 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
3697 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
3698 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
3699 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3701 assert(0 && "ROTL/ROTR legalize operation not supported");
3703 case TargetLowering::Legal:
3705 case TargetLowering::Custom:
3706 Tmp1 = TLI.LowerOperation(Result, DAG);
3707 if (Tmp1.getNode()) Result = Tmp1;
3709 case TargetLowering::Promote:
3710 assert(0 && "Do not know how to promote ROTL/ROTR");
3712 case TargetLowering::Expand:
3713 assert(0 && "Do not know how to expand ROTL/ROTR");
3719 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3720 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3721 case TargetLowering::Custom:
3722 assert(0 && "Cannot custom legalize this yet!");
3723 case TargetLowering::Legal:
3724 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3726 case TargetLowering::Promote: {
3727 MVT OVT = Tmp1.getValueType();
3728 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3729 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3731 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3732 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3733 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3734 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3737 case TargetLowering::Expand:
3738 Result = ExpandBSWAP(Tmp1);
3746 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
3747 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3748 case TargetLowering::Custom:
3749 case TargetLowering::Legal:
3750 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3751 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3752 TargetLowering::Custom) {
3753 Tmp1 = TLI.LowerOperation(Result, DAG);
3754 if (Tmp1.getNode()) {
3759 case TargetLowering::Promote: {
3760 MVT OVT = Tmp1.getValueType();
3761 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3763 // Zero extend the argument.
3764 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3765 // Perform the larger operation, then subtract if needed.
3766 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
3767 switch (Node->getOpcode()) {
3772 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3773 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
3774 DAG.getConstant(NVT.getSizeInBits(), NVT),
3776 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3777 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3780 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3781 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3782 DAG.getConstant(NVT.getSizeInBits() -
3783 OVT.getSizeInBits(), NVT));
3788 case TargetLowering::Expand:
3789 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
3809 case ISD::FNEARBYINT:
3810 Tmp1 = LegalizeOp(Node->getOperand(0));
3811 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
3812 case TargetLowering::Promote:
3813 case TargetLowering::Custom:
3816 case TargetLowering::Legal:
3817 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3819 Tmp1 = TLI.LowerOperation(Result, DAG);
3820 if (Tmp1.getNode()) Result = Tmp1;
3823 case TargetLowering::Expand:
3824 switch (Node->getOpcode()) {
3825 default: assert(0 && "Unreachable!");
3827 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3828 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3829 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
3832 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3833 MVT VT = Node->getValueType(0);
3834 Tmp2 = DAG.getConstantFP(0.0, VT);
3835 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
3837 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
3838 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
3853 case ISD::FNEARBYINT: {
3854 MVT VT = Node->getValueType(0);
3856 // Expand unsupported unary vector operators by unrolling them.
3857 if (VT.isVector()) {
3858 Result = LegalizeOp(UnrollVectorOp(Op));
3862 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3863 switch(Node->getOpcode()) {
3865 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3866 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
3869 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
3870 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
3873 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
3874 RTLIB::COS_F80, RTLIB::COS_PPCF128);
3877 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
3878 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
3881 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3882 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
3885 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3886 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
3889 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
3890 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
3893 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3894 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
3897 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3898 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
3901 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3902 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
3905 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3906 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
3909 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
3910 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
3912 case ISD::FNEARBYINT:
3913 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
3914 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
3917 default: assert(0 && "Unreachable!");
3920 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3928 MVT VT = Node->getValueType(0);
3930 // Expand unsupported unary vector operators by unrolling them.
3931 if (VT.isVector()) {
3932 Result = LegalizeOp(UnrollVectorOp(Op));
3936 // We always lower FPOWI into a libcall. No target support for it yet.
3937 RTLIB::Libcall LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64,
3938 RTLIB::POWI_F80, RTLIB::POWI_PPCF128);
3940 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
3943 case ISD::BIT_CONVERT:
3944 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
3945 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3946 Node->getValueType(0));
3947 } else if (Op.getOperand(0).getValueType().isVector()) {
3948 // The input has to be a vector type, we have to either scalarize it, pack
3949 // it, or convert it based on whether the input vector type is legal.
3950 SDNode *InVal = Node->getOperand(0).getNode();
3951 int InIx = Node->getOperand(0).getResNo();
3952 unsigned NumElems = InVal->getValueType(InIx).getVectorNumElements();
3953 MVT EVT = InVal->getValueType(InIx).getVectorElementType();
3955 // Figure out if there is a simple type corresponding to this Vector
3956 // type. If so, convert to the vector type.
3957 MVT TVT = MVT::getVectorVT(EVT, NumElems);
3958 if (TLI.isTypeLegal(TVT)) {
3959 // Turn this into a bit convert of the vector input.
3960 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3961 LegalizeOp(Node->getOperand(0)));
3963 } else if (NumElems == 1) {
3964 // Turn this into a bit convert of the scalar input.
3965 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
3966 ScalarizeVectorOp(Node->getOperand(0)));
3969 // FIXME: UNIMP! Store then reload
3970 assert(0 && "Cast from unsupported vector type not implemented yet!");
3973 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
3974 Node->getOperand(0).getValueType())) {
3975 default: assert(0 && "Unknown operation action!");
3976 case TargetLowering::Expand:
3977 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3978 Node->getValueType(0));
3980 case TargetLowering::Legal:
3981 Tmp1 = LegalizeOp(Node->getOperand(0));
3982 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3987 case ISD::CONVERT_RNDSAT: {
3988 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
3990 default: assert(0 && "Unknown cvt code!");
4001 SDValue DTyOp = Node->getOperand(1);
4002 SDValue STyOp = Node->getOperand(2);
4003 SDValue RndOp = Node->getOperand(3);
4004 SDValue SatOp = Node->getOperand(4);
4005 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4006 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4008 Tmp1 = LegalizeOp(Node->getOperand(0));
4009 Result = DAG.UpdateNodeOperands(Result, Tmp1, DTyOp, STyOp,
4011 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4012 TargetLowering::Custom) {
4013 Tmp1 = TLI.LowerOperation(Result, DAG);
4014 if (Tmp1.getNode()) Result = Tmp1;
4018 Result = PromoteOp(Node->getOperand(0));
4019 // For FP, make Op1 a i32
4021 Result = DAG.getConvertRndSat(Op.getValueType(), Result,
4022 DTyOp, STyOp, RndOp, SatOp, CvtCode);
4027 } // end switch CvtCode
4030 // Conversion operators. The source and destination have different types.
4031 case ISD::SINT_TO_FP:
4032 case ISD::UINT_TO_FP: {
4033 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
4034 Result = LegalizeINT_TO_FP(Result, isSigned,
4035 Node->getValueType(0), Node->getOperand(0));
4039 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4041 Tmp1 = LegalizeOp(Node->getOperand(0));
4042 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
4043 default: assert(0 && "Unknown TRUNCATE legalization operation action!");
4044 case TargetLowering::Custom:
4047 case TargetLowering::Legal:
4048 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4050 Tmp1 = TLI.LowerOperation(Result, DAG);
4051 if (Tmp1.getNode()) Result = Tmp1;
4054 case TargetLowering::Expand:
4055 assert(Result.getValueType().isVector() && "must be vector type");
4056 // Unroll the truncate. We should do better.
4057 Result = LegalizeOp(UnrollVectorOp(Result));
4061 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4063 // Since the result is legal, we should just be able to truncate the low
4064 // part of the source.
4065 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
4068 Result = PromoteOp(Node->getOperand(0));
4069 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
4074 case ISD::FP_TO_SINT:
4075 case ISD::FP_TO_UINT:
4076 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4078 Tmp1 = LegalizeOp(Node->getOperand(0));
4080 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
4081 default: assert(0 && "Unknown operation action!");
4082 case TargetLowering::Custom:
4085 case TargetLowering::Legal:
4086 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4088 Tmp1 = TLI.LowerOperation(Result, DAG);
4089 if (Tmp1.getNode()) Result = Tmp1;
4092 case TargetLowering::Promote:
4093 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
4094 Node->getOpcode() == ISD::FP_TO_SINT);
4096 case TargetLowering::Expand:
4097 if (Node->getOpcode() == ISD::FP_TO_UINT) {
4098 SDValue True, False;
4099 MVT VT = Node->getOperand(0).getValueType();
4100 MVT NVT = Node->getValueType(0);
4101 const uint64_t zero[] = {0, 0};
4102 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
4103 APInt x = APInt::getSignBit(NVT.getSizeInBits());
4104 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
4105 Tmp2 = DAG.getConstantFP(apf, VT);
4106 Tmp3 = DAG.getSetCC(TLI.getSetCCResultType(Node->getOperand(0)),
4107 Node->getOperand(0), Tmp2, ISD::SETLT);
4108 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
4109 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
4110 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
4112 False = DAG.getNode(ISD::XOR, NVT, False,
4113 DAG.getConstant(x, NVT));
4114 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
4117 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
4123 MVT VT = Op.getValueType();
4124 MVT OVT = Node->getOperand(0).getValueType();
4125 // Convert ppcf128 to i32
4126 if (OVT == MVT::ppcf128 && VT == MVT::i32) {
4127 if (Node->getOpcode() == ISD::FP_TO_SINT) {
4128 Result = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128,
4129 Node->getOperand(0), DAG.getValueType(MVT::f64));
4130 Result = DAG.getNode(ISD::FP_ROUND, MVT::f64, Result,
4131 DAG.getIntPtrConstant(1));
4132 Result = DAG.getNode(ISD::FP_TO_SINT, VT, Result);
4134 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
4135 APFloat apf = APFloat(APInt(128, 2, TwoE31));
4136 Tmp2 = DAG.getConstantFP(apf, OVT);
4137 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
4138 // FIXME: generated code sucks.
4139 Result = DAG.getNode(ISD::SELECT_CC, VT, Node->getOperand(0), Tmp2,
4140 DAG.getNode(ISD::ADD, MVT::i32,
4141 DAG.getNode(ISD::FP_TO_SINT, VT,
4142 DAG.getNode(ISD::FSUB, OVT,
4143 Node->getOperand(0), Tmp2)),
4144 DAG.getConstant(0x80000000, MVT::i32)),
4145 DAG.getNode(ISD::FP_TO_SINT, VT,
4146 Node->getOperand(0)),
4147 DAG.getCondCode(ISD::SETGE));
4151 // Convert f32 / f64 to i32 / i64 / i128.
4152 RTLIB::Libcall LC = (Node->getOpcode() == ISD::FP_TO_SINT) ?
4153 RTLIB::getFPTOSINT(OVT, VT) : RTLIB::getFPTOUINT(OVT, VT);
4154 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpectd fp-to-int conversion!");
4156 Result = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Dummy);
4160 Tmp1 = PromoteOp(Node->getOperand(0));
4161 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
4162 Result = LegalizeOp(Result);
4167 case ISD::FP_EXTEND: {
4168 MVT DstVT = Op.getValueType();
4169 MVT SrcVT = Op.getOperand(0).getValueType();
4170 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4171 // The only other way we can lower this is to turn it into a STORE,
4172 // LOAD pair, targetting a temporary location (a stack slot).
4173 Result = EmitStackConvert(Node->getOperand(0), SrcVT, DstVT);
4176 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4177 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4179 Tmp1 = LegalizeOp(Node->getOperand(0));
4180 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4183 Tmp1 = PromoteOp(Node->getOperand(0));
4184 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Tmp1);
4189 case ISD::FP_ROUND: {
4190 MVT DstVT = Op.getValueType();
4191 MVT SrcVT = Op.getOperand(0).getValueType();
4192 if (TLI.getConvertAction(SrcVT, DstVT) == TargetLowering::Expand) {
4193 if (SrcVT == MVT::ppcf128) {
4195 ExpandOp(Node->getOperand(0), Lo, Result);
4196 // Round it the rest of the way (e.g. to f32) if needed.
4197 if (DstVT!=MVT::f64)
4198 Result = DAG.getNode(ISD::FP_ROUND, DstVT, Result, Op.getOperand(1));
4201 // The only other way we can lower this is to turn it into a STORE,
4202 // LOAD pair, targetting a temporary location (a stack slot).
4203 Result = EmitStackConvert(Node->getOperand(0), DstVT, DstVT);
4206 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4207 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4209 Tmp1 = LegalizeOp(Node->getOperand(0));
4210 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4213 Tmp1 = PromoteOp(Node->getOperand(0));
4214 Result = DAG.getNode(ISD::FP_ROUND, Op.getValueType(), Tmp1,
4215 Node->getOperand(1));
4220 case ISD::ANY_EXTEND:
4221 case ISD::ZERO_EXTEND:
4222 case ISD::SIGN_EXTEND:
4223 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4224 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
4226 Tmp1 = LegalizeOp(Node->getOperand(0));
4227 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4228 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
4229 TargetLowering::Custom) {
4230 Tmp1 = TLI.LowerOperation(Result, DAG);
4231 if (Tmp1.getNode()) Result = Tmp1;
4235 switch (Node->getOpcode()) {
4236 case ISD::ANY_EXTEND:
4237 Tmp1 = PromoteOp(Node->getOperand(0));
4238 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
4240 case ISD::ZERO_EXTEND:
4241 Result = PromoteOp(Node->getOperand(0));
4242 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4243 Result = DAG.getZeroExtendInReg(Result,
4244 Node->getOperand(0).getValueType());
4246 case ISD::SIGN_EXTEND:
4247 Result = PromoteOp(Node->getOperand(0));
4248 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
4249 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4251 DAG.getValueType(Node->getOperand(0).getValueType()));
4256 case ISD::FP_ROUND_INREG:
4257 case ISD::SIGN_EXTEND_INREG: {
4258 Tmp1 = LegalizeOp(Node->getOperand(0));
4259 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
4261 // If this operation is not supported, convert it to a shl/shr or load/store
4263 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
4264 default: assert(0 && "This action not supported for this op yet!");
4265 case TargetLowering::Legal:
4266 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
4268 case TargetLowering::Expand:
4269 // If this is an integer extend and shifts are supported, do that.
4270 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
4271 // NOTE: we could fall back on load/store here too for targets without
4272 // SAR. However, it is doubtful that any exist.
4273 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
4274 ExtraVT.getSizeInBits();
4275 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
4276 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
4277 Node->getOperand(0), ShiftCst);
4278 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
4280 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
4281 // The only way we can lower this is to turn it into a TRUNCSTORE,
4282 // EXTLOAD pair, targetting a temporary location (a stack slot).
4284 // NOTE: there is a choice here between constantly creating new stack
4285 // slots and always reusing the same one. We currently always create
4286 // new ones, as reuse may inhibit scheduling.
4287 Result = EmitStackConvert(Node->getOperand(0), ExtraVT,
4288 Node->getValueType(0));
4290 assert(0 && "Unknown op");
4296 case ISD::TRAMPOLINE: {
4298 for (unsigned i = 0; i != 6; ++i)
4299 Ops[i] = LegalizeOp(Node->getOperand(i));
4300 Result = DAG.UpdateNodeOperands(Result, Ops, 6);
4301 // The only option for this node is to custom lower it.
4302 Result = TLI.LowerOperation(Result, DAG);
4303 assert(Result.getNode() && "Should always custom lower!");
4305 // Since trampoline produces two values, make sure to remember that we
4306 // legalized both of them.
4307 Tmp1 = LegalizeOp(Result.getValue(1));
4308 Result = LegalizeOp(Result);
4309 AddLegalizedOperand(SDValue(Node, 0), Result);
4310 AddLegalizedOperand(SDValue(Node, 1), Tmp1);
4311 return Op.getResNo() ? Tmp1 : Result;
4313 case ISD::FLT_ROUNDS_: {
4314 MVT VT = Node->getValueType(0);
4315 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4316 default: assert(0 && "This action not supported for this op yet!");
4317 case TargetLowering::Custom:
4318 Result = TLI.LowerOperation(Op, DAG);
4319 if (Result.getNode()) break;
4321 case TargetLowering::Legal:
4322 // If this operation is not supported, lower it to constant 1
4323 Result = DAG.getConstant(1, VT);
4329 MVT VT = Node->getValueType(0);
4330 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4331 default: assert(0 && "This action not supported for this op yet!");
4332 case TargetLowering::Legal:
4333 Tmp1 = LegalizeOp(Node->getOperand(0));
4334 Result = DAG.UpdateNodeOperands(Result, Tmp1);
4336 case TargetLowering::Custom:
4337 Result = TLI.LowerOperation(Op, DAG);
4338 if (Result.getNode()) break;
4340 case TargetLowering::Expand:
4341 // If this operation is not supported, lower it to 'abort()' call
4342 Tmp1 = LegalizeOp(Node->getOperand(0));
4343 TargetLowering::ArgListTy Args;
4344 std::pair<SDValue,SDValue> CallResult =
4345 TLI.LowerCallTo(Tmp1, Type::VoidTy,
4346 false, false, false, false, CallingConv::C, false,
4347 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
4349 Result = CallResult.second;
4357 MVT VT = Node->getValueType(0);
4358 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4359 default: assert(0 && "This action not supported for this op yet!");
4360 case TargetLowering::Custom:
4361 Result = TLI.LowerOperation(Op, DAG);
4362 if (Result.getNode()) break;
4364 case TargetLowering::Legal: {
4365 SDValue LHS = LegalizeOp(Node->getOperand(0));
4366 SDValue RHS = LegalizeOp(Node->getOperand(1));
4368 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
4369 ISD::ADD : ISD::SUB, LHS.getValueType(),
4371 MVT OType = Node->getValueType(1);
4373 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
4375 // LHSSign -> LHS >= 0
4376 // RHSSign -> RHS >= 0
4377 // SumSign -> Sum >= 0
4380 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
4382 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
4384 SDValue LHSSign = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
4385 SDValue RHSSign = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);
4386 SDValue SignsMatch = DAG.getSetCC(OType, LHSSign, RHSSign,
4387 Node->getOpcode() == ISD::SADDO ?
4388 ISD::SETEQ : ISD::SETNE);
4390 SDValue SumSign = DAG.getSetCC(OType, Sum, Zero, ISD::SETGE);
4391 SDValue SumSignNE = DAG.getSetCC(OType, LHSSign, SumSign, ISD::SETNE);
4393 SDValue Cmp = DAG.getNode(ISD::AND, OType, SignsMatch, SumSignNE);
4395 MVT ValueVTs[] = { LHS.getValueType(), OType };
4396 SDValue Ops[] = { Sum, Cmp };
4398 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4400 SDNode *RNode = Result.getNode();
4401 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4402 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4411 MVT VT = Node->getValueType(0);
4412 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4413 default: assert(0 && "This action not supported for this op yet!");
4414 case TargetLowering::Custom:
4415 Result = TLI.LowerOperation(Op, DAG);
4416 if (Result.getNode()) break;
4418 case TargetLowering::Legal: {
4419 SDValue LHS = LegalizeOp(Node->getOperand(0));
4420 SDValue RHS = LegalizeOp(Node->getOperand(1));
4422 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
4423 ISD::ADD : ISD::SUB, LHS.getValueType(),
4425 MVT OType = Node->getValueType(1);
4426 SDValue Cmp = DAG.getSetCC(OType, Sum, LHS,
4427 Node->getOpcode () == ISD::UADDO ?
4428 ISD::SETULT : ISD::SETUGT);
4430 MVT ValueVTs[] = { LHS.getValueType(), OType };
4431 SDValue Ops[] = { Sum, Cmp };
4433 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(&ValueVTs[0], 2),
4435 SDNode *RNode = Result.getNode();
4436 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), SDValue(RNode, 0));
4437 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), SDValue(RNode, 1));
4446 MVT VT = Node->getValueType(0);
4447 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
4448 default: assert(0 && "This action is not supported at all!");
4449 case TargetLowering::Custom:
4450 Result = TLI.LowerOperation(Op, DAG);
4451 if (Result.getNode()) break;
4453 case TargetLowering::Legal:
4454 // FIXME: According to Hacker's Delight, this can be implemented in
4455 // target independent lowering, but it would be inefficient, since it
4456 // requires a division + a branch.
4457 assert(0 && "Target independent lowering is not supported for SMULO/UMULO!");
4465 assert(Result.getValueType() == Op.getValueType() &&
4466 "Bad legalization!");
4468 // Make sure that the generated code is itself legal.
4470 Result = LegalizeOp(Result);
4472 // Note that LegalizeOp may be reentered even from single-use nodes, which
4473 // means that we always must cache transformed nodes.
4474 AddLegalizedOperand(Op, Result);
4478 /// PromoteOp - Given an operation that produces a value in an invalid type,
4479 /// promote it to compute the value into a larger type. The produced value will
4480 /// have the correct bits for the low portion of the register, but no guarantee
4481 /// is made about the top bits: it may be zero, sign-extended, or garbage.
4482 SDValue SelectionDAGLegalize::PromoteOp(SDValue Op) {
4483 MVT VT = Op.getValueType();
4484 MVT NVT = TLI.getTypeToTransformTo(VT);
4485 assert(getTypeAction(VT) == Promote &&
4486 "Caller should expand or legalize operands that are not promotable!");
4487 assert(NVT.bitsGT(VT) && NVT.isInteger() == VT.isInteger() &&
4488 "Cannot promote to smaller type!");
4490 SDValue Tmp1, Tmp2, Tmp3;
4492 SDNode *Node = Op.getNode();
4494 DenseMap<SDValue, SDValue>::iterator I = PromotedNodes.find(Op);
4495 if (I != PromotedNodes.end()) return I->second;
4497 switch (Node->getOpcode()) {
4498 case ISD::CopyFromReg:
4499 assert(0 && "CopyFromReg must be legal!");
4502 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4504 assert(0 && "Do not know how to promote this operator!");
4507 Result = DAG.getNode(ISD::UNDEF, NVT);
4511 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
4513 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
4514 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
4516 case ISD::ConstantFP:
4517 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
4518 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
4522 assert(isTypeLegal(TLI.getSetCCResultType(Node->getOperand(0)))
4523 && "SetCC type is not legal??");
4524 Result = DAG.getNode(ISD::SETCC,
4525 TLI.getSetCCResultType(Node->getOperand(0)),
4526 Node->getOperand(0), Node->getOperand(1),
4527 Node->getOperand(2));
4531 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4533 Result = LegalizeOp(Node->getOperand(0));
4534 assert(Result.getValueType().bitsGE(NVT) &&
4535 "This truncation doesn't make sense!");
4536 if (Result.getValueType().bitsGT(NVT)) // Truncate to NVT instead of VT
4537 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
4540 // The truncation is not required, because we don't guarantee anything
4541 // about high bits anyway.
4542 Result = PromoteOp(Node->getOperand(0));
4545 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
4546 // Truncate the low part of the expanded value to the result type
4547 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
4550 case ISD::SIGN_EXTEND:
4551 case ISD::ZERO_EXTEND:
4552 case ISD::ANY_EXTEND:
4553 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4554 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
4556 // Input is legal? Just do extend all the way to the larger type.
4557 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4560 // Promote the reg if it's smaller.
4561 Result = PromoteOp(Node->getOperand(0));
4562 // The high bits are not guaranteed to be anything. Insert an extend.
4563 if (Node->getOpcode() == ISD::SIGN_EXTEND)
4564 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4565 DAG.getValueType(Node->getOperand(0).getValueType()));
4566 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
4567 Result = DAG.getZeroExtendInReg(Result,
4568 Node->getOperand(0).getValueType());
4572 case ISD::CONVERT_RNDSAT: {
4573 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
4574 assert ((CvtCode == ISD::CVT_SS || CvtCode == ISD::CVT_SU ||
4575 CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
4576 CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
4577 "can only promote integers");
4578 Result = DAG.getConvertRndSat(NVT, Node->getOperand(0),
4579 Node->getOperand(1), Node->getOperand(2),
4580 Node->getOperand(3), Node->getOperand(4),
4585 case ISD::BIT_CONVERT:
4586 Result = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
4587 Node->getValueType(0));
4588 Result = PromoteOp(Result);
4591 case ISD::FP_EXTEND:
4592 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
4594 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4595 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
4596 case Promote: assert(0 && "Unreachable with 2 FP types!");
4598 if (Node->getConstantOperandVal(1) == 0) {
4599 // Input is legal? Do an FP_ROUND_INREG.
4600 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
4601 DAG.getValueType(VT));
4603 // Just remove the truncate, it isn't affecting the value.
4604 Result = DAG.getNode(ISD::FP_ROUND, NVT, Node->getOperand(0),
4605 Node->getOperand(1));
4610 case ISD::SINT_TO_FP:
4611 case ISD::UINT_TO_FP:
4612 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4614 // No extra round required here.
4615 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
4619 Result = PromoteOp(Node->getOperand(0));
4620 if (Node->getOpcode() == ISD::SINT_TO_FP)
4621 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
4623 DAG.getValueType(Node->getOperand(0).getValueType()));
4625 Result = DAG.getZeroExtendInReg(Result,
4626 Node->getOperand(0).getValueType());
4627 // No extra round required here.
4628 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
4631 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
4632 Node->getOperand(0));
4633 // Round if we cannot tolerate excess precision.
4634 if (NoExcessFPPrecision)
4635 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4636 DAG.getValueType(VT));
4641 case ISD::SIGN_EXTEND_INREG:
4642 Result = PromoteOp(Node->getOperand(0));
4643 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
4644 Node->getOperand(1));
4646 case ISD::FP_TO_SINT:
4647 case ISD::FP_TO_UINT:
4648 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4651 Tmp1 = Node->getOperand(0);
4654 // The input result is prerounded, so we don't have to do anything
4656 Tmp1 = PromoteOp(Node->getOperand(0));
4659 // If we're promoting a UINT to a larger size, check to see if the new node
4660 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
4661 // we can use that instead. This allows us to generate better code for
4662 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
4663 // legal, such as PowerPC.
4664 if (Node->getOpcode() == ISD::FP_TO_UINT &&
4665 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
4666 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
4667 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
4668 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
4670 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4676 Tmp1 = PromoteOp(Node->getOperand(0));
4677 assert(Tmp1.getValueType() == NVT);
4678 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4679 // NOTE: we do not have to do any extra rounding here for
4680 // NoExcessFPPrecision, because we know the input will have the appropriate
4681 // precision, and these operations don't modify precision at all.
4696 case ISD::FNEARBYINT:
4697 Tmp1 = PromoteOp(Node->getOperand(0));
4698 assert(Tmp1.getValueType() == NVT);
4699 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4700 if (NoExcessFPPrecision)
4701 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4702 DAG.getValueType(VT));
4707 // Promote f32 pow(i) to f64 pow(i). Note that this could insert a libcall
4708 // directly as well, which may be better.
4709 Tmp1 = PromoteOp(Node->getOperand(0));
4710 Tmp2 = Node->getOperand(1);
4711 if (Node->getOpcode() == ISD::FPOW)
4712 Tmp2 = PromoteOp(Tmp2);
4713 assert(Tmp1.getValueType() == NVT);
4714 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4715 if (NoExcessFPPrecision)
4716 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4717 DAG.getValueType(VT));
4721 case ISD::ATOMIC_CMP_SWAP_8:
4722 case ISD::ATOMIC_CMP_SWAP_16:
4723 case ISD::ATOMIC_CMP_SWAP_32:
4724 case ISD::ATOMIC_CMP_SWAP_64: {
4725 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4726 Tmp2 = PromoteOp(Node->getOperand(2));
4727 Tmp3 = PromoteOp(Node->getOperand(3));
4728 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4729 AtomNode->getBasePtr(), Tmp2, Tmp3,
4730 AtomNode->getSrcValue(),
4731 AtomNode->getAlignment());
4732 // Remember that we legalized the chain.
4733 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4736 case ISD::ATOMIC_LOAD_ADD_8:
4737 case ISD::ATOMIC_LOAD_SUB_8:
4738 case ISD::ATOMIC_LOAD_AND_8:
4739 case ISD::ATOMIC_LOAD_OR_8:
4740 case ISD::ATOMIC_LOAD_XOR_8:
4741 case ISD::ATOMIC_LOAD_NAND_8:
4742 case ISD::ATOMIC_LOAD_MIN_8:
4743 case ISD::ATOMIC_LOAD_MAX_8:
4744 case ISD::ATOMIC_LOAD_UMIN_8:
4745 case ISD::ATOMIC_LOAD_UMAX_8:
4746 case ISD::ATOMIC_SWAP_8:
4747 case ISD::ATOMIC_LOAD_ADD_16:
4748 case ISD::ATOMIC_LOAD_SUB_16:
4749 case ISD::ATOMIC_LOAD_AND_16:
4750 case ISD::ATOMIC_LOAD_OR_16:
4751 case ISD::ATOMIC_LOAD_XOR_16:
4752 case ISD::ATOMIC_LOAD_NAND_16:
4753 case ISD::ATOMIC_LOAD_MIN_16:
4754 case ISD::ATOMIC_LOAD_MAX_16:
4755 case ISD::ATOMIC_LOAD_UMIN_16:
4756 case ISD::ATOMIC_LOAD_UMAX_16:
4757 case ISD::ATOMIC_SWAP_16:
4758 case ISD::ATOMIC_LOAD_ADD_32:
4759 case ISD::ATOMIC_LOAD_SUB_32:
4760 case ISD::ATOMIC_LOAD_AND_32:
4761 case ISD::ATOMIC_LOAD_OR_32:
4762 case ISD::ATOMIC_LOAD_XOR_32:
4763 case ISD::ATOMIC_LOAD_NAND_32:
4764 case ISD::ATOMIC_LOAD_MIN_32:
4765 case ISD::ATOMIC_LOAD_MAX_32:
4766 case ISD::ATOMIC_LOAD_UMIN_32:
4767 case ISD::ATOMIC_LOAD_UMAX_32:
4768 case ISD::ATOMIC_SWAP_32:
4769 case ISD::ATOMIC_LOAD_ADD_64:
4770 case ISD::ATOMIC_LOAD_SUB_64:
4771 case ISD::ATOMIC_LOAD_AND_64:
4772 case ISD::ATOMIC_LOAD_OR_64:
4773 case ISD::ATOMIC_LOAD_XOR_64:
4774 case ISD::ATOMIC_LOAD_NAND_64:
4775 case ISD::ATOMIC_LOAD_MIN_64:
4776 case ISD::ATOMIC_LOAD_MAX_64:
4777 case ISD::ATOMIC_LOAD_UMIN_64:
4778 case ISD::ATOMIC_LOAD_UMAX_64:
4779 case ISD::ATOMIC_SWAP_64: {
4780 AtomicSDNode* AtomNode = cast<AtomicSDNode>(Node);
4781 Tmp2 = PromoteOp(Node->getOperand(2));
4782 Result = DAG.getAtomic(Node->getOpcode(), AtomNode->getChain(),
4783 AtomNode->getBasePtr(), Tmp2,
4784 AtomNode->getSrcValue(),
4785 AtomNode->getAlignment());
4786 // Remember that we legalized the chain.
4787 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4797 // The input may have strange things in the top bits of the registers, but
4798 // these operations don't care. They may have weird bits going out, but
4799 // that too is okay if they are integer operations.
4800 Tmp1 = PromoteOp(Node->getOperand(0));
4801 Tmp2 = PromoteOp(Node->getOperand(1));
4802 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4803 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4808 Tmp1 = PromoteOp(Node->getOperand(0));
4809 Tmp2 = PromoteOp(Node->getOperand(1));
4810 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
4811 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4813 // Floating point operations will give excess precision that we may not be
4814 // able to tolerate. If we DO allow excess precision, just leave it,
4815 // otherwise excise it.
4816 // FIXME: Why would we need to round FP ops more than integer ones?
4817 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
4818 if (NoExcessFPPrecision)
4819 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4820 DAG.getValueType(VT));
4825 // These operators require that their input be sign extended.
4826 Tmp1 = PromoteOp(Node->getOperand(0));
4827 Tmp2 = PromoteOp(Node->getOperand(1));
4828 if (NVT.isInteger()) {
4829 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4830 DAG.getValueType(VT));
4831 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
4832 DAG.getValueType(VT));
4834 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4836 // Perform FP_ROUND: this is probably overly pessimistic.
4837 if (NVT.isFloatingPoint() && NoExcessFPPrecision)
4838 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4839 DAG.getValueType(VT));
4843 case ISD::FCOPYSIGN:
4844 // These operators require that their input be fp extended.
4845 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4846 case Expand: assert(0 && "not implemented");
4847 case Legal: Tmp1 = LegalizeOp(Node->getOperand(0)); break;
4848 case Promote: Tmp1 = PromoteOp(Node->getOperand(0)); break;
4850 switch (getTypeAction(Node->getOperand(1).getValueType())) {
4851 case Expand: assert(0 && "not implemented");
4852 case Legal: Tmp2 = LegalizeOp(Node->getOperand(1)); break;
4853 case Promote: Tmp2 = PromoteOp(Node->getOperand(1)); break;
4855 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4857 // Perform FP_ROUND: this is probably overly pessimistic.
4858 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
4859 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
4860 DAG.getValueType(VT));
4865 // These operators require that their input be zero extended.
4866 Tmp1 = PromoteOp(Node->getOperand(0));
4867 Tmp2 = PromoteOp(Node->getOperand(1));
4868 assert(NVT.isInteger() && "Operators don't apply to FP!");
4869 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4870 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
4871 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
4875 Tmp1 = PromoteOp(Node->getOperand(0));
4876 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
4879 // The input value must be properly sign extended.
4880 Tmp1 = PromoteOp(Node->getOperand(0));
4881 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
4882 DAG.getValueType(VT));
4883 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
4886 // The input value must be properly zero extended.
4887 Tmp1 = PromoteOp(Node->getOperand(0));
4888 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
4889 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
4893 Tmp1 = Node->getOperand(0); // Get the chain.
4894 Tmp2 = Node->getOperand(1); // Get the pointer.
4895 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
4896 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
4897 Result = TLI.LowerOperation(Tmp3, DAG);
4899 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
4900 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2, V, 0);
4901 // Increment the pointer, VAList, to the next vaarg
4902 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
4903 DAG.getConstant(VT.getSizeInBits()/8,
4904 TLI.getPointerTy()));
4905 // Store the incremented VAList to the legalized pointer
4906 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, V, 0);
4907 // Load the actual argument out of the pointer VAList
4908 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
4910 // Remember that we legalized the chain.
4911 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4915 LoadSDNode *LD = cast<LoadSDNode>(Node);
4916 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
4917 ? ISD::EXTLOAD : LD->getExtensionType();
4918 Result = DAG.getExtLoad(ExtType, NVT,
4919 LD->getChain(), LD->getBasePtr(),
4920 LD->getSrcValue(), LD->getSrcValueOffset(),
4923 LD->getAlignment());
4924 // Remember that we legalized the chain.
4925 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4929 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
4930 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
4932 MVT VT2 = Tmp2.getValueType();
4933 assert(VT2 == Tmp3.getValueType()
4934 && "PromoteOp SELECT: Operands 2 and 3 ValueTypes don't match");
4935 // Ensure that the resulting node is at least the same size as the operands'
4936 // value types, because we cannot assume that TLI.getSetCCValueType() is
4938 Result = DAG.getNode(ISD::SELECT, VT2, Node->getOperand(0), Tmp2, Tmp3);
4941 case ISD::SELECT_CC:
4942 Tmp2 = PromoteOp(Node->getOperand(2)); // True
4943 Tmp3 = PromoteOp(Node->getOperand(3)); // False
4944 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4945 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
4948 Tmp1 = Node->getOperand(0);
4949 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
4950 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
4951 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
4952 DAG.getConstant(NVT.getSizeInBits() -
4954 TLI.getShiftAmountTy()));
4959 // Zero extend the argument
4960 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4961 // Perform the larger operation, then subtract if needed.
4962 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
4963 switch(Node->getOpcode()) {
4968 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
4969 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(Tmp1), Tmp1,
4970 DAG.getConstant(NVT.getSizeInBits(), NVT),
4972 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
4973 DAG.getConstant(VT.getSizeInBits(), NVT), Tmp1);
4976 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
4977 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
4978 DAG.getConstant(NVT.getSizeInBits() -
4979 VT.getSizeInBits(), NVT));
4983 case ISD::EXTRACT_SUBVECTOR:
4984 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
4986 case ISD::EXTRACT_VECTOR_ELT:
4987 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
4991 assert(Result.getNode() && "Didn't set a result!");
4993 // Make sure the result is itself legal.
4994 Result = LegalizeOp(Result);
4996 // Remember that we promoted this!
4997 AddPromotedOperand(Op, Result);
5001 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
5002 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
5003 /// based on the vector type. The return type of this matches the element type
5004 /// of the vector, which may not be legal for the target.
5005 SDValue SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDValue Op) {
5006 // We know that operand #0 is the Vec vector. If the index is a constant
5007 // or if the invec is a supported hardware type, we can use it. Otherwise,
5008 // lower to a store then an indexed load.
5009 SDValue Vec = Op.getOperand(0);
5010 SDValue Idx = Op.getOperand(1);
5012 MVT TVT = Vec.getValueType();
5013 unsigned NumElems = TVT.getVectorNumElements();
5015 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
5016 default: assert(0 && "This action is not supported yet!");
5017 case TargetLowering::Custom: {
5018 Vec = LegalizeOp(Vec);
5019 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5020 SDValue Tmp3 = TLI.LowerOperation(Op, DAG);
5025 case TargetLowering::Legal:
5026 if (isTypeLegal(TVT)) {
5027 Vec = LegalizeOp(Vec);
5028 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5032 case TargetLowering::Promote:
5033 assert(TVT.isVector() && "not vector type");
5034 // fall thru to expand since vectors are by default are promote
5035 case TargetLowering::Expand:
5039 if (NumElems == 1) {
5040 // This must be an access of the only element. Return it.
5041 Op = ScalarizeVectorOp(Vec);
5042 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
5043 unsigned NumLoElts = 1 << Log2_32(NumElems-1);
5044 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5046 SplitVectorOp(Vec, Lo, Hi);
5047 if (CIdx->getZExtValue() < NumLoElts) {
5051 Idx = DAG.getConstant(CIdx->getZExtValue() - NumLoElts,
5052 Idx.getValueType());
5055 // It's now an extract from the appropriate high or low part. Recurse.
5056 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5057 Op = ExpandEXTRACT_VECTOR_ELT(Op);
5059 // Store the value to a temporary stack slot, then LOAD the scalar
5060 // element back out.
5061 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
5062 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
5064 // Add the offset to the index.
5065 unsigned EltSize = Op.getValueType().getSizeInBits()/8;
5066 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
5067 DAG.getConstant(EltSize, Idx.getValueType()));
5069 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
5070 Idx = DAG.getNode(ISD::TRUNCATE, TLI.getPointerTy(), Idx);
5072 Idx = DAG.getNode(ISD::ZERO_EXTEND, TLI.getPointerTy(), Idx);
5074 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
5076 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
5081 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
5082 /// we assume the operation can be split if it is not already legal.
5083 SDValue SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDValue Op) {
5084 // We know that operand #0 is the Vec vector. For now we assume the index
5085 // is a constant and that the extracted result is a supported hardware type.
5086 SDValue Vec = Op.getOperand(0);
5087 SDValue Idx = LegalizeOp(Op.getOperand(1));
5089 unsigned NumElems = Vec.getValueType().getVectorNumElements();
5091 if (NumElems == Op.getValueType().getVectorNumElements()) {
5092 // This must be an access of the desired vector length. Return it.
5096 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
5098 SplitVectorOp(Vec, Lo, Hi);
5099 if (CIdx->getZExtValue() < NumElems/2) {
5103 Idx = DAG.getConstant(CIdx->getZExtValue() - NumElems/2,
5104 Idx.getValueType());
5107 // It's now an extract from the appropriate high or low part. Recurse.
5108 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
5109 return ExpandEXTRACT_SUBVECTOR(Op);
5112 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
5113 /// with condition CC on the current target. This usually involves legalizing
5114 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
5115 /// there may be no choice but to create a new SetCC node to represent the
5116 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
5117 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
5118 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
5121 SDValue Tmp1, Tmp2, Tmp3, Result;
5123 switch (getTypeAction(LHS.getValueType())) {
5125 Tmp1 = LegalizeOp(LHS); // LHS
5126 Tmp2 = LegalizeOp(RHS); // RHS
5129 Tmp1 = PromoteOp(LHS); // LHS
5130 Tmp2 = PromoteOp(RHS); // RHS
5132 // If this is an FP compare, the operands have already been extended.
5133 if (LHS.getValueType().isInteger()) {
5134 MVT VT = LHS.getValueType();
5135 MVT NVT = TLI.getTypeToTransformTo(VT);
5137 // Otherwise, we have to insert explicit sign or zero extends. Note
5138 // that we could insert sign extends for ALL conditions, but zero extend
5139 // is cheaper on many machines (an AND instead of two shifts), so prefer
5141 switch (cast<CondCodeSDNode>(CC)->get()) {
5142 default: assert(0 && "Unknown integer comparison!");
5149 // ALL of these operations will work if we either sign or zero extend
5150 // the operands (including the unsigned comparisons!). Zero extend is
5151 // usually a simpler/cheaper operation, so prefer it.
5152 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
5153 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
5159 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
5160 DAG.getValueType(VT));
5161 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
5162 DAG.getValueType(VT));
5163 Tmp1 = LegalizeOp(Tmp1); // Relegalize new nodes.
5164 Tmp2 = LegalizeOp(Tmp2); // Relegalize new nodes.
5170 MVT VT = LHS.getValueType();
5171 if (VT == MVT::f32 || VT == MVT::f64) {
5172 // Expand into one or more soft-fp libcall(s).
5173 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
5174 switch (cast<CondCodeSDNode>(CC)->get()) {
5177 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5181 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
5185 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5189 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5193 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5197 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5200 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5203 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
5206 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
5207 switch (cast<CondCodeSDNode>(CC)->get()) {
5209 // SETONE = SETOLT | SETOGT
5210 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5213 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
5216 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
5219 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
5222 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
5225 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
5227 default: assert(0 && "Unsupported FP setcc!");
5232 SDValue Ops[2] = { LHS, RHS };
5233 Tmp1 = ExpandLibCall(LC1, DAG.getMergeValues(Ops, 2).getNode(),
5234 false /*sign irrelevant*/, Dummy);
5235 Tmp2 = DAG.getConstant(0, MVT::i32);
5236 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
5237 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
5238 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Tmp1), Tmp1, Tmp2,
5240 LHS = ExpandLibCall(LC2, DAG.getMergeValues(Ops, 2).getNode(),
5241 false /*sign irrelevant*/, Dummy);
5242 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHS), LHS, Tmp2,
5243 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
5244 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5247 LHS = LegalizeOp(Tmp1);
5252 SDValue LHSLo, LHSHi, RHSLo, RHSHi;
5253 ExpandOp(LHS, LHSLo, LHSHi);
5254 ExpandOp(RHS, RHSLo, RHSHi);
5255 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5257 if (VT==MVT::ppcf128) {
5258 // FIXME: This generated code sucks. We want to generate
5259 // FCMPU crN, hi1, hi2
5261 // FCMPU crN, lo1, lo2
5262 // The following can be improved, but not that much.
5263 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5265 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, CCCode);
5266 Tmp3 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5267 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5269 Tmp2 = DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi, CCCode);
5270 Tmp1 = DAG.getNode(ISD::AND, Tmp1.getValueType(), Tmp1, Tmp2);
5271 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp3);
5280 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
5281 if (RHSCST->isAllOnesValue()) {
5282 // Comparison to -1.
5283 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
5288 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
5289 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
5290 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
5291 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
5294 // If this is a comparison of the sign bit, just look at the top part.
5296 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
5297 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
5298 CST->isNullValue()) || // X < 0
5299 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
5300 CST->isAllOnesValue())) { // X > -1
5306 // FIXME: This generated code sucks.
5307 ISD::CondCode LowCC;
5309 default: assert(0 && "Unknown integer setcc!");
5311 case ISD::SETULT: LowCC = ISD::SETULT; break;
5313 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
5315 case ISD::SETULE: LowCC = ISD::SETULE; break;
5317 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
5320 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
5321 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
5322 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
5324 // NOTE: on targets without efficient SELECT of bools, we can always use
5325 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
5326 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
5327 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo,
5328 LowCC, false, DagCombineInfo);
5329 if (!Tmp1.getNode())
5330 Tmp1 = DAG.getSetCC(TLI.getSetCCResultType(LHSLo), LHSLo, RHSLo, LowCC);
5331 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5332 CCCode, false, DagCombineInfo);
5333 if (!Tmp2.getNode())
5334 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(LHSHi), LHSHi,
5337 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
5338 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.getNode());
5339 if ((Tmp1C && Tmp1C->isNullValue()) ||
5340 (Tmp2C && Tmp2C->isNullValue() &&
5341 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
5342 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
5343 (Tmp2C && Tmp2C->getAPIntValue() == 1 &&
5344 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
5345 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
5346 // low part is known false, returns high part.
5347 // For LE / GE, if high part is known false, ignore the low part.
5348 // For LT / GT, if high part is known true, ignore the low part.
5352 Result = TLI.SimplifySetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5353 ISD::SETEQ, false, DagCombineInfo);
5354 if (!Result.getNode())
5355 Result=DAG.getSetCC(TLI.getSetCCResultType(LHSHi), LHSHi, RHSHi,
5357 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
5358 Result, Tmp1, Tmp2));
5369 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
5370 /// condition code CC on the current target. This routine assumes LHS and rHS
5371 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
5372 /// illegal condition code into AND / OR of multiple SETCC values.
5373 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
5374 SDValue &LHS, SDValue &RHS,
5376 MVT OpVT = LHS.getValueType();
5377 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
5378 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
5379 default: assert(0 && "Unknown condition code action!");
5380 case TargetLowering::Legal:
5383 case TargetLowering::Expand: {
5384 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
5387 default: assert(0 && "Don't know how to expand this condition!"); abort();
5388 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
5389 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5390 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5391 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
5392 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5393 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
5394 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5395 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5396 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5397 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5398 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5399 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
5400 // FIXME: Implement more expansions.
5403 SDValue SetCC1 = DAG.getSetCC(VT, LHS, RHS, CC1);
5404 SDValue SetCC2 = DAG.getSetCC(VT, LHS, RHS, CC2);
5405 LHS = DAG.getNode(Opc, VT, SetCC1, SetCC2);
5413 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
5414 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
5415 /// a load from the stack slot to DestVT, extending it if needed.
5416 /// The resultant code need not be legal.
5417 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
5420 // Create the stack frame object.
5421 unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(
5422 SrcOp.getValueType().getTypeForMVT());
5423 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
5425 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
5426 int SPFI = StackPtrFI->getIndex();
5428 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
5429 unsigned SlotSize = SlotVT.getSizeInBits();
5430 unsigned DestSize = DestVT.getSizeInBits();
5431 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(
5432 DestVT.getTypeForMVT());
5434 // Emit a store to the stack slot. Use a truncstore if the input value is
5435 // later than DestVT.
5438 if (SrcSize > SlotSize)
5439 Store = DAG.getTruncStore(DAG.getEntryNode(), SrcOp, FIPtr,
5440 PseudoSourceValue::getFixedStack(SPFI), 0,
5441 SlotVT, false, SrcAlign);
5443 assert(SrcSize == SlotSize && "Invalid store");
5444 Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr,
5445 PseudoSourceValue::getFixedStack(SPFI), 0,
5449 // Result is a load from the stack slot.
5450 if (SlotSize == DestSize)
5451 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0, false, DestAlign);
5453 assert(SlotSize < DestSize && "Unknown extension!");
5454 return DAG.getExtLoad(ISD::EXTLOAD, DestVT, Store, FIPtr, NULL, 0, SlotVT,
5458 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
5459 // Create a vector sized/aligned stack slot, store the value to element #0,
5460 // then load the whole vector back out.
5461 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
5463 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
5464 int SPFI = StackPtrFI->getIndex();
5466 SDValue Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
5467 PseudoSourceValue::getFixedStack(SPFI), 0);
5468 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,
5469 PseudoSourceValue::getFixedStack(SPFI), 0);
5473 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
5474 /// support the operation, but do support the resultant vector type.
5475 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
5477 // If the only non-undef value is the low element, turn this into a
5478 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
5479 unsigned NumElems = Node->getNumOperands();
5480 bool isOnlyLowElement = true;
5481 SDValue SplatValue = Node->getOperand(0);
5483 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
5484 // and use a bitmask instead of a list of elements.
5485 std::map<SDValue, std::vector<unsigned> > Values;
5486 Values[SplatValue].push_back(0);
5487 bool isConstant = true;
5488 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
5489 SplatValue.getOpcode() != ISD::UNDEF)
5492 for (unsigned i = 1; i < NumElems; ++i) {
5493 SDValue V = Node->getOperand(i);
5494 Values[V].push_back(i);
5495 if (V.getOpcode() != ISD::UNDEF)
5496 isOnlyLowElement = false;
5497 if (SplatValue != V)
5498 SplatValue = SDValue(0,0);
5500 // If this isn't a constant element or an undef, we can't use a constant
5502 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
5503 V.getOpcode() != ISD::UNDEF)
5507 if (isOnlyLowElement) {
5508 // If the low element is an undef too, then this whole things is an undef.
5509 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
5510 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
5511 // Otherwise, turn this into a scalar_to_vector node.
5512 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
5513 Node->getOperand(0));
5516 // If all elements are constants, create a load from the constant pool.
5518 MVT VT = Node->getValueType(0);
5519 std::vector<Constant*> CV;
5520 for (unsigned i = 0, e = NumElems; i != e; ++i) {
5521 if (ConstantFPSDNode *V =
5522 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
5523 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
5524 } else if (ConstantSDNode *V =
5525 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
5526 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
5528 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
5530 Node->getOperand(0).getValueType().getTypeForMVT();
5531 CV.push_back(UndefValue::get(OpNTy));
5534 Constant *CP = ConstantVector::get(CV);
5535 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
5536 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5537 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
5538 PseudoSourceValue::getConstantPool(), 0,
5542 if (SplatValue.getNode()) { // Splat of one value?
5543 // Build the shuffle constant vector: <0, 0, 0, 0>
5544 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5545 SDValue Zero = DAG.getConstant(0, MaskVT.getVectorElementType());
5546 std::vector<SDValue> ZeroVec(NumElems, Zero);
5547 SDValue SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5548 &ZeroVec[0], ZeroVec.size());
5550 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
5551 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
5552 // Get the splatted value into the low element of a vector register.
5554 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
5556 // Return shuffle(LowValVec, undef, <0,0,0,0>)
5557 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
5558 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
5563 // If there are only two unique elements, we may be able to turn this into a
5565 if (Values.size() == 2) {
5566 // Get the two values in deterministic order.
5567 SDValue Val1 = Node->getOperand(1);
5569 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
5570 if (MI->first != Val1)
5573 Val2 = (++MI)->first;
5575 // If Val1 is an undef, make sure end ends up as Val2, to ensure that our
5576 // vector shuffle has the undef vector on the RHS.
5577 if (Val1.getOpcode() == ISD::UNDEF)
5578 std::swap(Val1, Val2);
5580 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
5581 MVT MaskVT = MVT::getIntVectorWithNumElements(NumElems);
5582 MVT MaskEltVT = MaskVT.getVectorElementType();
5583 std::vector<SDValue> MaskVec(NumElems);
5585 // Set elements of the shuffle mask for Val1.
5586 std::vector<unsigned> &Val1Elts = Values[Val1];
5587 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
5588 MaskVec[Val1Elts[i]] = DAG.getConstant(0, MaskEltVT);
5590 // Set elements of the shuffle mask for Val2.
5591 std::vector<unsigned> &Val2Elts = Values[Val2];
5592 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
5593 if (Val2.getOpcode() != ISD::UNDEF)
5594 MaskVec[Val2Elts[i]] = DAG.getConstant(NumElems, MaskEltVT);
5596 MaskVec[Val2Elts[i]] = DAG.getNode(ISD::UNDEF, MaskEltVT);
5598 SDValue ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
5599 &MaskVec[0], MaskVec.size());
5601 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
5602 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
5603 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
5604 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val1);
5605 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), Val2);
5606 SDValue Ops[] = { Val1, Val2, ShuffleMask };
5608 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
5609 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops, 3);
5613 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
5614 // aligned object on the stack, store each element into it, then load
5615 // the result as a vector.
5616 MVT VT = Node->getValueType(0);
5617 // Create the stack frame object.
5618 SDValue FIPtr = DAG.CreateStackTemporary(VT);
5620 // Emit a store of each element to the stack slot.
5621 SmallVector<SDValue, 8> Stores;
5622 unsigned TypeByteSize = Node->getOperand(0).getValueType().getSizeInBits()/8;
5623 // Store (in the right endianness) the elements to memory.
5624 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5625 // Ignore undef elements.
5626 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
5628 unsigned Offset = TypeByteSize*i;
5630 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
5631 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
5633 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
5638 if (!Stores.empty()) // Not all undef elements?
5639 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
5640 &Stores[0], Stores.size());
5642 StoreChain = DAG.getEntryNode();
5644 // Result is a load from the stack slot.
5645 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
5648 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
5649 SDValue Op, SDValue Amt,
5650 SDValue &Lo, SDValue &Hi) {
5651 // Expand the subcomponents.
5653 ExpandOp(Op, LHSL, LHSH);
5655 SDValue Ops[] = { LHSL, LHSH, Amt };
5656 MVT VT = LHSL.getValueType();
5657 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
5658 Hi = Lo.getValue(1);
5662 /// ExpandShift - Try to find a clever way to expand this shift operation out to
5663 /// smaller elements. If we can't find a way that is more efficient than a
5664 /// libcall on this target, return false. Otherwise, return true with the
5665 /// low-parts expanded into Lo and Hi.
5666 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDValue Op,SDValue Amt,
5667 SDValue &Lo, SDValue &Hi) {
5668 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
5669 "This is not a shift!");
5671 MVT NVT = TLI.getTypeToTransformTo(Op.getValueType());
5672 SDValue ShAmt = LegalizeOp(Amt);
5673 MVT ShTy = ShAmt.getValueType();
5674 unsigned ShBits = ShTy.getSizeInBits();
5675 unsigned VTBits = Op.getValueType().getSizeInBits();
5676 unsigned NVTBits = NVT.getSizeInBits();
5678 // Handle the case when Amt is an immediate.
5679 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.getNode())) {
5680 unsigned Cst = CN->getZExtValue();
5681 // Expand the incoming operand to be shifted, so that we have its parts
5683 ExpandOp(Op, InL, InH);
5687 Lo = DAG.getConstant(0, NVT);
5688 Hi = DAG.getConstant(0, NVT);
5689 } else if (Cst > NVTBits) {
5690 Lo = DAG.getConstant(0, NVT);
5691 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
5692 } else if (Cst == NVTBits) {
5693 Lo = DAG.getConstant(0, NVT);
5696 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
5697 Hi = DAG.getNode(ISD::OR, NVT,
5698 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
5699 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
5704 Lo = DAG.getConstant(0, NVT);
5705 Hi = DAG.getConstant(0, NVT);
5706 } else if (Cst > NVTBits) {
5707 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
5708 Hi = DAG.getConstant(0, NVT);
5709 } else if (Cst == NVTBits) {
5711 Hi = DAG.getConstant(0, NVT);
5713 Lo = DAG.getNode(ISD::OR, NVT,
5714 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5715 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5716 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
5721 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
5722 DAG.getConstant(NVTBits-1, ShTy));
5723 } else if (Cst > NVTBits) {
5724 Lo = DAG.getNode(ISD::SRA, NVT, InH,
5725 DAG.getConstant(Cst-NVTBits, ShTy));
5726 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5727 DAG.getConstant(NVTBits-1, ShTy));
5728 } else if (Cst == NVTBits) {
5730 Hi = DAG.getNode(ISD::SRA, NVT, InH,
5731 DAG.getConstant(NVTBits-1, ShTy));
5733 Lo = DAG.getNode(ISD::OR, NVT,
5734 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
5735 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
5736 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
5742 // Okay, the shift amount isn't constant. However, if we can tell that it is
5743 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
5744 APInt Mask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
5745 APInt KnownZero, KnownOne;
5746 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
5748 // If we know that if any of the high bits of the shift amount are one, then
5749 // we can do this as a couple of simple shifts.
5750 if (KnownOne.intersects(Mask)) {
5751 // Mask out the high bit, which we know is set.
5752 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
5753 DAG.getConstant(~Mask, Amt.getValueType()));
5755 // Expand the incoming operand to be shifted, so that we have its parts
5757 ExpandOp(Op, InL, InH);
5760 Lo = DAG.getConstant(0, NVT); // Low part is zero.
5761 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
5764 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
5765 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
5768 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
5769 DAG.getConstant(NVTBits-1, Amt.getValueType()));
5770 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
5775 // If we know that the high bits of the shift amount are all zero, then we can
5776 // do this as a couple of simple shifts.
5777 if ((KnownZero & Mask) == Mask) {
5779 SDValue Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
5780 DAG.getConstant(NVTBits, Amt.getValueType()),
5783 // Expand the incoming operand to be shifted, so that we have its parts
5785 ExpandOp(Op, InL, InH);
5788 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
5789 Hi = DAG.getNode(ISD::OR, NVT,
5790 DAG.getNode(ISD::SHL, NVT, InH, Amt),
5791 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
5794 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
5795 Lo = DAG.getNode(ISD::OR, NVT,
5796 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5797 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5800 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
5801 Lo = DAG.getNode(ISD::OR, NVT,
5802 DAG.getNode(ISD::SRL, NVT, InL, Amt),
5803 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
5812 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
5813 // does not fit into a register, return the lo part and set the hi part to the
5814 // by-reg argument. If it does fit into a single register, return the result
5815 // and leave the Hi part unset.
5816 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
5817 bool isSigned, SDValue &Hi) {
5818 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
5819 // The input chain to this libcall is the entry node of the function.
5820 // Legalizing the call will automatically add the previous call to the
5822 SDValue InChain = DAG.getEntryNode();
5824 TargetLowering::ArgListTy Args;
5825 TargetLowering::ArgListEntry Entry;
5826 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
5827 MVT ArgVT = Node->getOperand(i).getValueType();
5828 const Type *ArgTy = ArgVT.getTypeForMVT();
5829 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
5830 Entry.isSExt = isSigned;
5831 Entry.isZExt = !isSigned;
5832 Args.push_back(Entry);
5834 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
5835 TLI.getPointerTy());
5837 // Splice the libcall in wherever FindInputOutputChains tells us to.
5838 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
5839 std::pair<SDValue,SDValue> CallInfo =
5840 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
5841 CallingConv::C, false, Callee, Args, DAG);
5843 // Legalize the call sequence, starting with the chain. This will advance
5844 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
5845 // was added by LowerCallTo (guaranteeing proper serialization of calls).
5846 LegalizeOp(CallInfo.second);
5848 switch (getTypeAction(CallInfo.first.getValueType())) {
5849 default: assert(0 && "Unknown thing");
5851 Result = CallInfo.first;
5854 ExpandOp(CallInfo.first, Result, Hi);
5860 /// LegalizeINT_TO_FP - Legalize a [US]INT_TO_FP operation.
5862 SDValue SelectionDAGLegalize::
5863 LegalizeINT_TO_FP(SDValue Result, bool isSigned, MVT DestTy, SDValue Op) {
5864 bool isCustom = false;
5866 switch (getTypeAction(Op.getValueType())) {
5868 switch (TLI.getOperationAction(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5869 Op.getValueType())) {
5870 default: assert(0 && "Unknown operation action!");
5871 case TargetLowering::Custom:
5874 case TargetLowering::Legal:
5875 Tmp1 = LegalizeOp(Op);
5876 if (Result.getNode())
5877 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5879 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5882 Tmp1 = TLI.LowerOperation(Result, DAG);
5883 if (Tmp1.getNode()) Result = Tmp1;
5886 case TargetLowering::Expand:
5887 Result = ExpandLegalINT_TO_FP(isSigned, LegalizeOp(Op), DestTy);
5889 case TargetLowering::Promote:
5890 Result = PromoteLegalINT_TO_FP(LegalizeOp(Op), DestTy, isSigned);
5895 Result = ExpandIntToFP(isSigned, DestTy, Op);
5898 Tmp1 = PromoteOp(Op);
5900 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
5901 Tmp1, DAG.getValueType(Op.getValueType()));
5903 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
5906 if (Result.getNode())
5907 Result = DAG.UpdateNodeOperands(Result, Tmp1);
5909 Result = DAG.getNode(isSigned ? ISD::SINT_TO_FP : ISD::UINT_TO_FP,
5911 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
5917 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
5919 SDValue SelectionDAGLegalize::
5920 ExpandIntToFP(bool isSigned, MVT DestTy, SDValue Source) {
5921 MVT SourceVT = Source.getValueType();
5922 bool ExpandSource = getTypeAction(SourceVT) == Expand;
5924 // Expand unsupported int-to-fp vector casts by unrolling them.
5925 if (DestTy.isVector()) {
5927 return LegalizeOp(UnrollVectorOp(Source));
5928 MVT DestEltTy = DestTy.getVectorElementType();
5929 if (DestTy.getVectorNumElements() == 1) {
5930 SDValue Scalar = ScalarizeVectorOp(Source);
5931 SDValue Result = LegalizeINT_TO_FP(SDValue(), isSigned,
5933 return DAG.getNode(ISD::BUILD_VECTOR, DestTy, Result);
5936 SplitVectorOp(Source, Lo, Hi);
5937 MVT SplitDestTy = MVT::getVectorVT(DestEltTy,
5938 DestTy.getVectorNumElements() / 2);
5939 SDValue LoResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Lo);
5940 SDValue HiResult = LegalizeINT_TO_FP(SDValue(), isSigned, SplitDestTy, Hi);
5941 return LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, DestTy, LoResult,
5945 // Special case for i32 source to take advantage of UINTTOFP_I32_F32, etc.
5946 if (!isSigned && SourceVT != MVT::i32) {
5947 // The integer value loaded will be incorrectly if the 'sign bit' of the
5948 // incoming integer is set. To handle this, we dynamically test to see if
5949 // it is set, and, if so, add a fudge factor.
5953 ExpandOp(Source, Lo, Hi);
5954 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, Lo, Hi);
5956 // The comparison for the sign bit will use the entire operand.
5960 // Check to see if the target has a custom way to lower this. If so, use
5961 // it. (Note we've already expanded the operand in this case.)
5962 switch (TLI.getOperationAction(ISD::UINT_TO_FP, SourceVT)) {
5963 default: assert(0 && "This action not implemented for this operation!");
5964 case TargetLowering::Legal:
5965 case TargetLowering::Expand:
5966 break; // This case is handled below.
5967 case TargetLowering::Custom: {
5968 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::UINT_TO_FP, DestTy,
5971 return LegalizeOp(NV);
5972 break; // The target decided this was legal after all
5976 // If this is unsigned, and not supported, first perform the conversion to
5977 // signed, then adjust the result if the sign bit is set.
5978 SDValue SignedConv = ExpandIntToFP(true, DestTy, Source);
5980 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Hi), Hi,
5981 DAG.getConstant(0, Hi.getValueType()),
5983 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
5984 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
5985 SignSet, Four, Zero);
5986 uint64_t FF = 0x5f800000ULL;
5987 if (TLI.isLittleEndian()) FF <<= 32;
5988 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
5990 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
5991 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
5992 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
5993 Alignment = std::min(Alignment, 4u);
5995 if (DestTy == MVT::f32)
5996 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
5997 PseudoSourceValue::getConstantPool(), 0,
5999 else if (DestTy.bitsGT(MVT::f32))
6000 // FIXME: Avoid the extend by construction the right constantpool?
6001 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
6003 PseudoSourceValue::getConstantPool(), 0,
6004 MVT::f32, false, Alignment);
6006 assert(0 && "Unexpected conversion");
6008 MVT SCVT = SignedConv.getValueType();
6009 if (SCVT != DestTy) {
6010 // Destination type needs to be expanded as well. The FADD now we are
6011 // constructing will be expanded into a libcall.
6012 if (SCVT.getSizeInBits() != DestTy.getSizeInBits()) {
6013 assert(SCVT.getSizeInBits() * 2 == DestTy.getSizeInBits());
6014 SignedConv = DAG.getNode(ISD::BUILD_PAIR, DestTy,
6015 SignedConv, SignedConv.getValue(1));
6017 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
6019 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
6022 // Check to see if the target has a custom way to lower this. If so, use it.
6023 switch (TLI.getOperationAction(ISD::SINT_TO_FP, SourceVT)) {
6024 default: assert(0 && "This action not implemented for this operation!");
6025 case TargetLowering::Legal:
6026 case TargetLowering::Expand:
6027 break; // This case is handled below.
6028 case TargetLowering::Custom: {
6029 SDValue NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
6032 return LegalizeOp(NV);
6033 break; // The target decided this was legal after all
6037 // Expand the source, then glue it back together for the call. We must expand
6038 // the source in case it is shared (this pass of legalize must traverse it).
6040 SDValue SrcLo, SrcHi;
6041 ExpandOp(Source, SrcLo, SrcHi);
6042 Source = DAG.getNode(ISD::BUILD_PAIR, SourceVT, SrcLo, SrcHi);
6045 RTLIB::Libcall LC = isSigned ?
6046 RTLIB::getSINTTOFP(SourceVT, DestTy) :
6047 RTLIB::getUINTTOFP(SourceVT, DestTy);
6048 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unknown int value type");
6050 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
6052 SDValue Result = ExpandLibCall(LC, Source.getNode(), isSigned, HiPart);
6053 if (Result.getValueType() != DestTy && HiPart.getNode())
6054 Result = DAG.getNode(ISD::BUILD_PAIR, DestTy, Result, HiPart);
6058 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
6059 /// INT_TO_FP operation of the specified operand when the target requests that
6060 /// we expand it. At this point, we know that the result and operand types are
6061 /// legal for the target.
6062 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
6065 if (Op0.getValueType() == MVT::i32) {
6066 // simple 32-bit [signed|unsigned] integer to float/double expansion
6068 // Get the stack frame index of a 8 byte buffer.
6069 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
6071 // word offset constant for Hi/Lo address computation
6072 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
6073 // set up Hi and Lo (into buffer) address based on endian
6074 SDValue Hi = StackSlot;
6075 SDValue Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
6076 if (TLI.isLittleEndian())
6079 // if signed map to unsigned space
6082 // constant used to invert sign bit (signed to unsigned mapping)
6083 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
6084 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
6088 // store the lo of the constructed double - based on integer input
6089 SDValue Store1 = DAG.getStore(DAG.getEntryNode(),
6090 Op0Mapped, Lo, NULL, 0);
6091 // initial hi portion of constructed double
6092 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
6093 // store the hi of the constructed double - biased exponent
6094 SDValue Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
6095 // load the constructed double
6096 SDValue Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
6097 // FP constant to bias correct the final result
6098 SDValue Bias = DAG.getConstantFP(isSigned ?
6099 BitsToDouble(0x4330000080000000ULL)
6100 : BitsToDouble(0x4330000000000000ULL),
6102 // subtract the bias
6103 SDValue Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
6106 // handle final rounding
6107 if (DestVT == MVT::f64) {
6110 } else if (DestVT.bitsLT(MVT::f64)) {
6111 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub,
6112 DAG.getIntPtrConstant(0));
6113 } else if (DestVT.bitsGT(MVT::f64)) {
6114 Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
6118 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
6119 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
6121 SDValue SignSet = DAG.getSetCC(TLI.getSetCCResultType(Op0), Op0,
6122 DAG.getConstant(0, Op0.getValueType()),
6124 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
6125 SDValue CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
6126 SignSet, Four, Zero);
6128 // If the sign bit of the integer is set, the large number will be treated
6129 // as a negative number. To counteract this, the dynamic code adds an
6130 // offset depending on the data type.
6132 switch (Op0.getValueType().getSimpleVT()) {
6133 default: assert(0 && "Unsupported integer type!");
6134 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
6135 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
6136 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
6137 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
6139 if (TLI.isLittleEndian()) FF <<= 32;
6140 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
6142 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
6143 unsigned Alignment = 1 << cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
6144 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
6145 Alignment = std::min(Alignment, 4u);
6147 if (DestVT == MVT::f32)
6148 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
6149 PseudoSourceValue::getConstantPool(), 0,
6153 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, DestVT,
6154 DAG.getEntryNode(), CPIdx,
6155 PseudoSourceValue::getConstantPool(), 0,
6156 MVT::f32, false, Alignment));
6159 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
6162 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
6163 /// *INT_TO_FP operation of the specified operand when the target requests that
6164 /// we promote it. At this point, we know that the result and operand types are
6165 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
6166 /// operation that takes a larger input.
6167 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
6170 // First step, figure out the appropriate *INT_TO_FP operation to use.
6171 MVT NewInTy = LegalOp.getValueType();
6173 unsigned OpToUse = 0;
6175 // Scan for the appropriate larger type to use.
6177 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
6178 assert(NewInTy.isInteger() && "Ran out of possibilities!");
6180 // If the target supports SINT_TO_FP of this type, use it.
6181 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
6183 case TargetLowering::Legal:
6184 if (!TLI.isTypeLegal(NewInTy))
6185 break; // Can't use this datatype.
6187 case TargetLowering::Custom:
6188 OpToUse = ISD::SINT_TO_FP;
6192 if (isSigned) continue;
6194 // If the target supports UINT_TO_FP of this type, use it.
6195 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
6197 case TargetLowering::Legal:
6198 if (!TLI.isTypeLegal(NewInTy))
6199 break; // Can't use this datatype.
6201 case TargetLowering::Custom:
6202 OpToUse = ISD::UINT_TO_FP;
6207 // Otherwise, try a larger type.
6210 // Okay, we found the operation and type to use. Zero extend our input to the
6211 // desired type then run the operation on it.
6212 return DAG.getNode(OpToUse, DestVT,
6213 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
6217 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
6218 /// FP_TO_*INT operation of the specified operand when the target requests that
6219 /// we promote it. At this point, we know that the result and operand types are
6220 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
6221 /// operation that returns a larger result.
6222 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
6225 // First step, figure out the appropriate FP_TO*INT operation to use.
6226 MVT NewOutTy = DestVT;
6228 unsigned OpToUse = 0;
6230 // Scan for the appropriate larger type to use.
6232 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
6233 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
6235 // If the target supports FP_TO_SINT returning this type, use it.
6236 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
6238 case TargetLowering::Legal:
6239 if (!TLI.isTypeLegal(NewOutTy))
6240 break; // Can't use this datatype.
6242 case TargetLowering::Custom:
6243 OpToUse = ISD::FP_TO_SINT;
6248 // If the target supports FP_TO_UINT of this type, use it.
6249 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
6251 case TargetLowering::Legal:
6252 if (!TLI.isTypeLegal(NewOutTy))
6253 break; // Can't use this datatype.
6255 case TargetLowering::Custom:
6256 OpToUse = ISD::FP_TO_UINT;
6261 // Otherwise, try a larger type.
6265 // Okay, we found the operation and type to use.
6266 SDValue Operation = DAG.getNode(OpToUse, NewOutTy, LegalOp);
6268 // If the operation produces an invalid type, it must be custom lowered. Use
6269 // the target lowering hooks to expand it. Just keep the low part of the
6270 // expanded operation, we know that we're truncating anyway.
6271 if (getTypeAction(NewOutTy) == Expand) {
6272 SmallVector<SDValue, 2> Results;
6273 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
6274 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
6275 Operation = Results[0];
6278 // Truncate the result of the extended FP_TO_*INT operation to the desired
6280 return DAG.getNode(ISD::TRUNCATE, DestVT, Operation);
6283 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
6285 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op) {
6286 MVT VT = Op.getValueType();
6287 MVT SHVT = TLI.getShiftAmountTy();
6288 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
6289 switch (VT.getSimpleVT()) {
6290 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
6292 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6293 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6294 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
6296 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6297 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6298 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6299 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6300 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
6301 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
6302 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6303 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6304 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6306 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
6307 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
6308 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
6309 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
6310 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
6311 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
6312 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
6313 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
6314 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
6315 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
6316 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
6317 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
6318 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
6319 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
6320 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
6321 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
6322 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
6323 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
6324 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
6325 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
6326 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
6330 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
6332 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op) {
6334 default: assert(0 && "Cannot expand this yet!");
6336 static const uint64_t mask[6] = {
6337 0x5555555555555555ULL, 0x3333333333333333ULL,
6338 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
6339 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
6341 MVT VT = Op.getValueType();
6342 MVT ShVT = TLI.getShiftAmountTy();
6343 unsigned len = VT.getSizeInBits();
6344 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6345 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
6346 SDValue Tmp2 = DAG.getConstant(mask[i], VT);
6347 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6348 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
6349 DAG.getNode(ISD::AND, VT,
6350 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
6355 // for now, we do this:
6356 // x = x | (x >> 1);
6357 // x = x | (x >> 2);
6359 // x = x | (x >>16);
6360 // x = x | (x >>32); // for 64-bit input
6361 // return popcount(~x);
6363 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
6364 MVT VT = Op.getValueType();
6365 MVT ShVT = TLI.getShiftAmountTy();
6366 unsigned len = VT.getSizeInBits();
6367 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
6368 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
6369 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
6371 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
6372 return DAG.getNode(ISD::CTPOP, VT, Op);
6375 // for now, we use: { return popcount(~x & (x - 1)); }
6376 // unless the target has ctlz but not ctpop, in which case we use:
6377 // { return 32 - nlz(~x & (x-1)); }
6378 // see also http://www.hackersdelight.org/HDcode/ntz.cc
6379 MVT VT = Op.getValueType();
6380 SDValue Tmp2 = DAG.getConstant(~0ULL, VT);
6381 SDValue Tmp3 = DAG.getNode(ISD::AND, VT,
6382 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
6383 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
6384 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
6385 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
6386 TLI.isOperationLegal(ISD::CTLZ, VT))
6387 return DAG.getNode(ISD::SUB, VT,
6388 DAG.getConstant(VT.getSizeInBits(), VT),
6389 DAG.getNode(ISD::CTLZ, VT, Tmp3));
6390 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
6395 /// ExpandOp - Expand the specified SDValue into its two component pieces
6396 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
6397 /// LegalizedNodes map is filled in for any results that are not expanded, the
6398 /// ExpandedNodes map is filled in for any results that are expanded, and the
6399 /// Lo/Hi values are returned.
6400 void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
6401 MVT VT = Op.getValueType();
6402 MVT NVT = TLI.getTypeToTransformTo(VT);
6403 SDNode *Node = Op.getNode();
6404 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
6405 assert(((NVT.isInteger() && NVT.bitsLT(VT)) || VT.isFloatingPoint() ||
6406 VT.isVector()) && "Cannot expand to FP value or to larger int value!");
6408 // See if we already expanded it.
6409 DenseMap<SDValue, std::pair<SDValue, SDValue> >::iterator I
6410 = ExpandedNodes.find(Op);
6411 if (I != ExpandedNodes.end()) {
6412 Lo = I->second.first;
6413 Hi = I->second.second;
6417 switch (Node->getOpcode()) {
6418 case ISD::CopyFromReg:
6419 assert(0 && "CopyFromReg must be legal!");
6420 case ISD::FP_ROUND_INREG:
6421 if (VT == MVT::ppcf128 &&
6422 TLI.getOperationAction(ISD::FP_ROUND_INREG, VT) ==
6423 TargetLowering::Custom) {
6424 SDValue SrcLo, SrcHi, Src;
6425 ExpandOp(Op.getOperand(0), SrcLo, SrcHi);
6426 Src = DAG.getNode(ISD::BUILD_PAIR, VT, SrcLo, SrcHi);
6427 SDValue Result = TLI.LowerOperation(
6428 DAG.getNode(ISD::FP_ROUND_INREG, VT, Src, Op.getOperand(1)), DAG);
6429 assert(Result.getNode()->getOpcode() == ISD::BUILD_PAIR);
6430 Lo = Result.getNode()->getOperand(0);
6431 Hi = Result.getNode()->getOperand(1);
6437 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
6439 assert(0 && "Do not know how to expand this operator!");
6441 case ISD::EXTRACT_ELEMENT:
6442 ExpandOp(Node->getOperand(0), Lo, Hi);
6443 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue())
6444 return ExpandOp(Hi, Lo, Hi);
6445 return ExpandOp(Lo, Lo, Hi);
6446 case ISD::EXTRACT_VECTOR_ELT:
6447 // ExpandEXTRACT_VECTOR_ELT tolerates invalid result types.
6448 Lo = ExpandEXTRACT_VECTOR_ELT(Op);
6449 return ExpandOp(Lo, Lo, Hi);
6451 Lo = DAG.getNode(ISD::UNDEF, NVT);
6452 Hi = DAG.getNode(ISD::UNDEF, NVT);
6454 case ISD::Constant: {
6455 unsigned NVTBits = NVT.getSizeInBits();
6456 const APInt &Cst = cast<ConstantSDNode>(Node)->getAPIntValue();
6457 Lo = DAG.getConstant(APInt(Cst).trunc(NVTBits), NVT);
6458 Hi = DAG.getConstant(Cst.lshr(NVTBits).trunc(NVTBits), NVT);
6461 case ISD::ConstantFP: {
6462 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
6463 if (CFP->getValueType(0) == MVT::ppcf128) {
6464 APInt api = CFP->getValueAPF().bitcastToAPInt();
6465 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[1])),
6467 Hi = DAG.getConstantFP(APFloat(APInt(64, 1, &api.getRawData()[0])),
6471 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
6472 if (getTypeAction(Lo.getValueType()) == Expand)
6473 ExpandOp(Lo, Lo, Hi);
6476 case ISD::BUILD_PAIR:
6477 // Return the operands.
6478 Lo = Node->getOperand(0);
6479 Hi = Node->getOperand(1);
6482 case ISD::MERGE_VALUES:
6483 if (Node->getNumValues() == 1) {
6484 ExpandOp(Op.getOperand(0), Lo, Hi);
6487 // FIXME: For now only expand i64,chain = MERGE_VALUES (x, y)
6488 assert(Op.getResNo() == 0 && Node->getNumValues() == 2 &&
6489 Op.getValue(1).getValueType() == MVT::Other &&
6490 "unhandled MERGE_VALUES");
6491 ExpandOp(Op.getOperand(0), Lo, Hi);
6492 // Remember that we legalized the chain.
6493 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Op.getOperand(1)));
6496 case ISD::SIGN_EXTEND_INREG:
6497 ExpandOp(Node->getOperand(0), Lo, Hi);
6498 // sext_inreg the low part if needed.
6499 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
6501 // The high part gets the sign extension from the lo-part. This handles
6502 // things like sextinreg V:i64 from i8.
6503 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6504 DAG.getConstant(NVT.getSizeInBits()-1,
6505 TLI.getShiftAmountTy()));
6509 ExpandOp(Node->getOperand(0), Lo, Hi);
6510 SDValue TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
6511 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
6517 ExpandOp(Node->getOperand(0), Lo, Hi);
6518 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
6519 DAG.getNode(ISD::CTPOP, NVT, Lo),
6520 DAG.getNode(ISD::CTPOP, NVT, Hi));
6521 Hi = DAG.getConstant(0, NVT);
6525 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
6526 ExpandOp(Node->getOperand(0), Lo, Hi);
6527 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6528 SDValue HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
6529 SDValue TopNotZero = DAG.getSetCC(TLI.getSetCCResultType(HLZ), HLZ, BitsC,
6531 SDValue LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
6532 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
6534 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
6535 Hi = DAG.getConstant(0, NVT);
6540 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
6541 ExpandOp(Node->getOperand(0), Lo, Hi);
6542 SDValue BitsC = DAG.getConstant(NVT.getSizeInBits(), NVT);
6543 SDValue LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
6544 SDValue BotNotZero = DAG.getSetCC(TLI.getSetCCResultType(LTZ), LTZ, BitsC,
6546 SDValue HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
6547 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
6549 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
6550 Hi = DAG.getConstant(0, NVT);
6555 SDValue Ch = Node->getOperand(0); // Legalize the chain.
6556 SDValue Ptr = Node->getOperand(1); // Legalize the pointer.
6557 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
6558 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
6560 // Remember that we legalized the chain.
6561 Hi = LegalizeOp(Hi);
6562 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
6563 if (TLI.isBigEndian())
6569 LoadSDNode *LD = cast<LoadSDNode>(Node);
6570 SDValue Ch = LD->getChain(); // Legalize the chain.
6571 SDValue Ptr = LD->getBasePtr(); // Legalize the pointer.
6572 ISD::LoadExtType ExtType = LD->getExtensionType();
6573 const Value *SV = LD->getSrcValue();
6574 int SVOffset = LD->getSrcValueOffset();
6575 unsigned Alignment = LD->getAlignment();
6576 bool isVolatile = LD->isVolatile();
6578 if (ExtType == ISD::NON_EXTLOAD) {
6579 Lo = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6580 isVolatile, Alignment);
6581 if (VT == MVT::f32 || VT == MVT::f64) {
6582 // f32->i32 or f64->i64 one to one expansion.
6583 // Remember that we legalized the chain.
6584 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6585 // Recursively expand the new load.
6586 if (getTypeAction(NVT) == Expand)
6587 ExpandOp(Lo, Lo, Hi);
6591 // Increment the pointer to the other half.
6592 unsigned IncrementSize = Lo.getValueType().getSizeInBits()/8;
6593 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
6594 DAG.getIntPtrConstant(IncrementSize));
6595 SVOffset += IncrementSize;
6596 Alignment = MinAlign(Alignment, IncrementSize);
6597 Hi = DAG.getLoad(NVT, Ch, Ptr, SV, SVOffset,
6598 isVolatile, Alignment);
6600 // Build a factor node to remember that this load is independent of the
6602 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
6605 // Remember that we legalized the chain.
6606 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
6607 if (TLI.isBigEndian())
6610 MVT EVT = LD->getMemoryVT();
6612 if ((VT == MVT::f64 && EVT == MVT::f32) ||
6613 (VT == MVT::ppcf128 && (EVT==MVT::f64 || EVT==MVT::f32))) {
6614 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
6615 SDValue Load = DAG.getLoad(EVT, Ch, Ptr, SV,
6616 SVOffset, isVolatile, Alignment);
6617 // Remember that we legalized the chain.
6618 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Load.getValue(1)));
6619 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
6624 Lo = DAG.getLoad(NVT, Ch, Ptr, SV,
6625 SVOffset, isVolatile, Alignment);
6627 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, SV,
6628 SVOffset, EVT, isVolatile,
6631 // Remember that we legalized the chain.
6632 AddLegalizedOperand(SDValue(Node, 1), LegalizeOp(Lo.getValue(1)));
6634 if (ExtType == ISD::SEXTLOAD) {
6635 // The high part is obtained by SRA'ing all but one of the bits of the
6637 unsigned LoSize = Lo.getValueType().getSizeInBits();
6638 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6639 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6640 } else if (ExtType == ISD::ZEXTLOAD) {
6641 // The high part is just a zero.
6642 Hi = DAG.getConstant(0, NVT);
6643 } else /* if (ExtType == ISD::EXTLOAD) */ {
6644 // The high part is undefined.
6645 Hi = DAG.getNode(ISD::UNDEF, NVT);
6652 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
6653 SDValue LL, LH, RL, RH;
6654 ExpandOp(Node->getOperand(0), LL, LH);
6655 ExpandOp(Node->getOperand(1), RL, RH);
6656 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
6657 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
6661 SDValue LL, LH, RL, RH;
6662 ExpandOp(Node->getOperand(1), LL, LH);
6663 ExpandOp(Node->getOperand(2), RL, RH);
6664 if (getTypeAction(NVT) == Expand)
6665 NVT = TLI.getTypeToExpandTo(NVT);
6666 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
6668 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
6671 case ISD::SELECT_CC: {
6672 SDValue TL, TH, FL, FH;
6673 ExpandOp(Node->getOperand(2), TL, TH);
6674 ExpandOp(Node->getOperand(3), FL, FH);
6675 if (getTypeAction(NVT) == Expand)
6676 NVT = TLI.getTypeToExpandTo(NVT);
6677 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6678 Node->getOperand(1), TL, FL, Node->getOperand(4));
6680 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
6681 Node->getOperand(1), TH, FH, Node->getOperand(4));
6684 case ISD::ANY_EXTEND:
6685 // The low part is any extension of the input (which degenerates to a copy).
6686 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
6687 // The high part is undefined.
6688 Hi = DAG.getNode(ISD::UNDEF, NVT);
6690 case ISD::SIGN_EXTEND: {
6691 // The low part is just a sign extension of the input (which degenerates to
6693 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
6695 // The high part is obtained by SRA'ing all but one of the bits of the lo
6697 unsigned LoSize = Lo.getValueType().getSizeInBits();
6698 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
6699 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
6702 case ISD::ZERO_EXTEND:
6703 // The low part is just a zero extension of the input (which degenerates to
6705 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
6707 // The high part is just a zero.
6708 Hi = DAG.getConstant(0, NVT);
6711 case ISD::TRUNCATE: {
6712 // The input value must be larger than this value. Expand *it*.
6714 ExpandOp(Node->getOperand(0), NewLo, Hi);
6716 // The low part is now either the right size, or it is closer. If not the
6717 // right size, make an illegal truncate so we recursively expand it.
6718 if (NewLo.getValueType() != Node->getValueType(0))
6719 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
6720 ExpandOp(NewLo, Lo, Hi);
6724 case ISD::BIT_CONVERT: {
6726 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
6727 // If the target wants to, allow it to lower this itself.
6728 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6729 case Expand: assert(0 && "cannot expand FP!");
6730 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
6731 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
6733 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
6736 // f32 / f64 must be expanded to i32 / i64.
6737 if (VT == MVT::f32 || VT == MVT::f64) {
6738 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
6739 if (getTypeAction(NVT) == Expand)
6740 ExpandOp(Lo, Lo, Hi);
6744 // If source operand will be expanded to the same type as VT, i.e.
6745 // i64 <- f64, i32 <- f32, expand the source operand instead.
6746 MVT VT0 = Node->getOperand(0).getValueType();
6747 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
6748 ExpandOp(Node->getOperand(0), Lo, Hi);
6752 // Turn this into a load/store pair by default.
6753 if (Tmp.getNode() == 0)
6754 Tmp = EmitStackConvert(Node->getOperand(0), VT, VT);
6756 ExpandOp(Tmp, Lo, Hi);
6760 case ISD::READCYCLECOUNTER: {
6761 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
6762 TargetLowering::Custom &&
6763 "Must custom expand ReadCycleCounter");
6764 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6765 assert(Tmp.getNode() && "Node must be custom expanded!");
6766 ExpandOp(Tmp.getValue(0), Lo, Hi);
6767 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6768 LegalizeOp(Tmp.getValue(1)));
6772 case ISD::ATOMIC_CMP_SWAP_64: {
6773 // This operation does not need a loop.
6774 SDValue Tmp = TLI.LowerOperation(Op, DAG);
6775 assert(Tmp.getNode() && "Node must be custom expanded!");
6776 ExpandOp(Tmp.getValue(0), Lo, Hi);
6777 AddLegalizedOperand(SDValue(Node, 1), // Remember we legalized the chain.
6778 LegalizeOp(Tmp.getValue(1)));
6782 case ISD::ATOMIC_LOAD_ADD_64:
6783 case ISD::ATOMIC_LOAD_SUB_64:
6784 case ISD::ATOMIC_LOAD_AND_64:
6785 case ISD::ATOMIC_LOAD_OR_64:
6786 case ISD::ATOMIC_LOAD_XOR_64:
6787 case ISD::ATOMIC_LOAD_NAND_64:
6788 case ISD::ATOMIC_SWAP_64: {
6789 // These operations require a loop to be generated. We can't do that yet,
6790 // so substitute a target-dependent pseudo and expand that later.
6791 SDValue In2Lo, In2Hi, In2;
6792 ExpandOp(Op.getOperand(2), In2Lo, In2Hi);
6793 In2 = DAG.getNode(ISD::BUILD_PAIR, VT, In2Lo, In2Hi);
6794 AtomicSDNode* Anode = cast<AtomicSDNode>(Node);
6796 DAG.getAtomic(Op.getOpcode(), Op.getOperand(0), Op.getOperand(1), In2,
6797 Anode->getSrcValue(), Anode->getAlignment());
6798 SDValue Result = TLI.LowerOperation(Replace, DAG);
6799 ExpandOp(Result.getValue(0), Lo, Hi);
6800 // Remember that we legalized the chain.
6801 AddLegalizedOperand(SDValue(Node,1), LegalizeOp(Result.getValue(1)));
6805 // These operators cannot be expanded directly, emit them as calls to
6806 // library functions.
6807 case ISD::FP_TO_SINT: {
6808 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
6810 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6811 case Expand: assert(0 && "cannot expand FP!");
6812 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6813 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6816 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
6818 // Now that the custom expander is done, expand the result, which is still
6821 ExpandOp(Op, Lo, Hi);
6826 RTLIB::Libcall LC = RTLIB::getFPTOSINT(Node->getOperand(0).getValueType(),
6828 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected uint-to-fp conversion!");
6829 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6833 case ISD::FP_TO_UINT: {
6834 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
6836 switch (getTypeAction(Node->getOperand(0).getValueType())) {
6837 case Expand: assert(0 && "cannot expand FP!");
6838 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
6839 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
6842 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
6844 // Now that the custom expander is done, expand the result.
6846 ExpandOp(Op, Lo, Hi);
6851 RTLIB::Libcall LC = RTLIB::getFPTOUINT(Node->getOperand(0).getValueType(),
6853 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
6854 Lo = ExpandLibCall(LC, Node, false/*sign irrelevant*/, Hi);
6859 // If the target wants custom lowering, do so.
6860 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6861 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
6862 SDValue Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
6863 Op = TLI.LowerOperation(Op, DAG);
6865 // Now that the custom expander is done, expand the result, which is
6867 ExpandOp(Op, Lo, Hi);
6872 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
6873 // this X << 1 as X+X.
6874 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
6875 if (ShAmt->getAPIntValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
6876 TLI.isOperationLegal(ISD::ADDE, NVT)) {
6877 SDValue LoOps[2], HiOps[3];
6878 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
6879 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
6880 LoOps[1] = LoOps[0];
6881 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
6883 HiOps[1] = HiOps[0];
6884 HiOps[2] = Lo.getValue(1);
6885 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
6890 // If we can emit an efficient shift operation, do so now.
6891 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6894 // If this target supports SHL_PARTS, use it.
6895 TargetLowering::LegalizeAction Action =
6896 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
6897 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6898 Action == TargetLowering::Custom) {
6899 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6903 // Otherwise, emit a libcall.
6904 Lo = ExpandLibCall(RTLIB::SHL_I64, Node, false/*left shift=unsigned*/, Hi);
6909 // If the target wants custom lowering, do so.
6910 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6911 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
6912 SDValue Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
6913 Op = TLI.LowerOperation(Op, DAG);
6915 // Now that the custom expander is done, expand the result, which is
6917 ExpandOp(Op, Lo, Hi);
6922 // If we can emit an efficient shift operation, do so now.
6923 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
6926 // If this target supports SRA_PARTS, use it.
6927 TargetLowering::LegalizeAction Action =
6928 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
6929 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6930 Action == TargetLowering::Custom) {
6931 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6935 // Otherwise, emit a libcall.
6936 Lo = ExpandLibCall(RTLIB::SRA_I64, Node, true/*ashr is signed*/, Hi);
6941 // If the target wants custom lowering, do so.
6942 SDValue ShiftAmt = LegalizeOp(Node->getOperand(1));
6943 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
6944 SDValue Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
6945 Op = TLI.LowerOperation(Op, DAG);
6947 // Now that the custom expander is done, expand the result, which is
6949 ExpandOp(Op, Lo, Hi);
6954 // If we can emit an efficient shift operation, do so now.
6955 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
6958 // If this target supports SRL_PARTS, use it.
6959 TargetLowering::LegalizeAction Action =
6960 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
6961 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
6962 Action == TargetLowering::Custom) {
6963 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
6967 // Otherwise, emit a libcall.
6968 Lo = ExpandLibCall(RTLIB::SRL_I64, Node, false/*lshr is unsigned*/, Hi);
6974 // If the target wants to custom expand this, let them.
6975 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
6976 TargetLowering::Custom) {
6977 SDValue Result = TLI.LowerOperation(Op, DAG);
6978 if (Result.getNode()) {
6979 ExpandOp(Result, Lo, Hi);
6983 // Expand the subcomponents.
6984 SDValue LHSL, LHSH, RHSL, RHSH;
6985 ExpandOp(Node->getOperand(0), LHSL, LHSH);
6986 ExpandOp(Node->getOperand(1), RHSL, RHSH);
6987 SDValue LoOps[2], HiOps[3];
6993 //cascaded check to see if any smaller size has a a carry flag.
6994 unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
6995 bool hasCarry = false;
6996 for (unsigned BitSize = NVT.getSizeInBits(); BitSize != 0; BitSize /= 2) {
6997 MVT AVT = MVT::getIntegerVT(BitSize);
6998 if (TLI.isOperationLegal(OpV, AVT)) {
7005 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7006 if (Node->getOpcode() == ISD::ADD) {
7007 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
7008 HiOps[2] = Lo.getValue(1);
7009 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
7011 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
7012 HiOps[2] = Lo.getValue(1);
7013 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
7017 if (Node->getOpcode() == ISD::ADD) {
7018 Lo = DAG.getNode(ISD::ADD, NVT, LoOps, 2);
7019 Hi = DAG.getNode(ISD::ADD, NVT, HiOps, 2);
7020 SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
7021 Lo, LoOps[0], ISD::SETULT);
7022 SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
7023 DAG.getConstant(1, NVT),
7024 DAG.getConstant(0, NVT));
7025 SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
7026 Lo, LoOps[1], ISD::SETULT);
7027 SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
7028 DAG.getConstant(1, NVT),
7030 Hi = DAG.getNode(ISD::ADD, NVT, Hi, Carry2);
7032 Lo = DAG.getNode(ISD::SUB, NVT, LoOps, 2);
7033 Hi = DAG.getNode(ISD::SUB, NVT, HiOps, 2);
7034 SDValue Cmp = DAG.getSetCC(NVT, LoOps[0], LoOps[1], ISD::SETULT);
7035 SDValue Borrow = DAG.getNode(ISD::SELECT, NVT, Cmp,
7036 DAG.getConstant(1, NVT),
7037 DAG.getConstant(0, NVT));
7038 Hi = DAG.getNode(ISD::SUB, NVT, Hi, Borrow);
7046 // Expand the subcomponents.
7047 SDValue LHSL, LHSH, RHSL, RHSH;
7048 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7049 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7050 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7051 SDValue LoOps[2] = { LHSL, RHSL };
7052 SDValue HiOps[3] = { LHSH, RHSH };
7054 if (Node->getOpcode() == ISD::ADDC) {
7055 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
7056 HiOps[2] = Lo.getValue(1);
7057 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
7059 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
7060 HiOps[2] = Lo.getValue(1);
7061 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
7063 // Remember that we legalized the flag.
7064 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7069 // Expand the subcomponents.
7070 SDValue LHSL, LHSH, RHSL, RHSH;
7071 ExpandOp(Node->getOperand(0), LHSL, LHSH);
7072 ExpandOp(Node->getOperand(1), RHSL, RHSH);
7073 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
7074 SDValue LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
7075 SDValue HiOps[3] = { LHSH, RHSH };
7077 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
7078 HiOps[2] = Lo.getValue(1);
7079 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
7081 // Remember that we legalized the flag.
7082 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
7086 // If the target wants to custom expand this, let them.
7087 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
7088 SDValue New = TLI.LowerOperation(Op, DAG);
7089 if (New.getNode()) {
7090 ExpandOp(New, Lo, Hi);
7095 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
7096 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
7097 bool HasSMUL_LOHI = TLI.isOperationLegal(ISD::SMUL_LOHI, NVT);
7098 bool HasUMUL_LOHI = TLI.isOperationLegal(ISD::UMUL_LOHI, NVT);
7099 if (HasMULHU || HasMULHS || HasUMUL_LOHI || HasSMUL_LOHI) {
7100 SDValue LL, LH, RL, RH;
7101 ExpandOp(Node->getOperand(0), LL, LH);
7102 ExpandOp(Node->getOperand(1), RL, RH);
7103 unsigned OuterBitSize = Op.getValueSizeInBits();
7104 unsigned InnerBitSize = RH.getValueSizeInBits();
7105 unsigned LHSSB = DAG.ComputeNumSignBits(Op.getOperand(0));
7106 unsigned RHSSB = DAG.ComputeNumSignBits(Op.getOperand(1));
7107 APInt HighMask = APInt::getHighBitsSet(OuterBitSize, InnerBitSize);
7108 if (DAG.MaskedValueIsZero(Node->getOperand(0), HighMask) &&
7109 DAG.MaskedValueIsZero(Node->getOperand(1), HighMask)) {
7110 // The inputs are both zero-extended.
7112 // We can emit a umul_lohi.
7113 Lo = DAG.getNode(ISD::UMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7114 Hi = SDValue(Lo.getNode(), 1);
7118 // We can emit a mulhu+mul.
7119 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7120 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7124 if (LHSSB > InnerBitSize && RHSSB > InnerBitSize) {
7125 // The input values are both sign-extended.
7127 // We can emit a smul_lohi.
7128 Lo = DAG.getNode(ISD::SMUL_LOHI, DAG.getVTList(NVT, NVT), LL, RL);
7129 Hi = SDValue(Lo.getNode(), 1);
7133 // We can emit a mulhs+mul.
7134 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7135 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
7140 // Lo,Hi = umul LHS, RHS.
7141 SDValue UMulLOHI = DAG.getNode(ISD::UMUL_LOHI,
7142 DAG.getVTList(NVT, NVT), LL, RL);
7144 Hi = UMulLOHI.getValue(1);
7145 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7146 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7147 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7148 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7152 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
7153 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
7154 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
7155 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
7156 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
7157 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
7162 // If nothing else, we can make a libcall.
7163 Lo = ExpandLibCall(RTLIB::MUL_I64, Node, false/*sign irrelevant*/, Hi);
7167 Lo = ExpandLibCall(RTLIB::SDIV_I64, Node, true, Hi);
7170 Lo = ExpandLibCall(RTLIB::UDIV_I64, Node, true, Hi);
7173 Lo = ExpandLibCall(RTLIB::SREM_I64, Node, true, Hi);
7176 Lo = ExpandLibCall(RTLIB::UREM_I64, Node, true, Hi);
7180 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::ADD_F32,
7183 RTLIB::ADD_PPCF128),
7187 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::SUB_F32,
7190 RTLIB::SUB_PPCF128),
7194 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::MUL_F32,
7197 RTLIB::MUL_PPCF128),
7201 Lo = ExpandLibCall(GetFPLibCall(VT, RTLIB::DIV_F32,
7204 RTLIB::DIV_PPCF128),
7207 case ISD::FP_EXTEND: {
7208 if (VT == MVT::ppcf128) {
7209 assert(Node->getOperand(0).getValueType()==MVT::f32 ||
7210 Node->getOperand(0).getValueType()==MVT::f64);
7211 const uint64_t zero = 0;
7212 if (Node->getOperand(0).getValueType()==MVT::f32)
7213 Hi = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Node->getOperand(0));
7215 Hi = Node->getOperand(0);
7216 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7219 RTLIB::Libcall LC = RTLIB::getFPEXT(Node->getOperand(0).getValueType(), VT);
7220 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
7221 Lo = ExpandLibCall(LC, Node, true, Hi);
7224 case ISD::FP_ROUND: {
7225 RTLIB::Libcall LC = RTLIB::getFPROUND(Node->getOperand(0).getValueType(),
7227 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
7228 Lo = ExpandLibCall(LC, Node, true, Hi);
7243 case ISD::FNEARBYINT:
7246 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
7247 switch(Node->getOpcode()) {
7249 LC = GetFPLibCall(VT, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
7250 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128);
7253 LC = GetFPLibCall(VT, RTLIB::SIN_F32, RTLIB::SIN_F64,
7254 RTLIB::SIN_F80, RTLIB::SIN_PPCF128);
7257 LC = GetFPLibCall(VT, RTLIB::COS_F32, RTLIB::COS_F64,
7258 RTLIB::COS_F80, RTLIB::COS_PPCF128);
7261 LC = GetFPLibCall(VT, RTLIB::LOG_F32, RTLIB::LOG_F64,
7262 RTLIB::LOG_F80, RTLIB::LOG_PPCF128);
7265 LC = GetFPLibCall(VT, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
7266 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128);
7269 LC = GetFPLibCall(VT, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
7270 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128);
7273 LC = GetFPLibCall(VT, RTLIB::EXP_F32, RTLIB::EXP_F64,
7274 RTLIB::EXP_F80, RTLIB::EXP_PPCF128);
7277 LC = GetFPLibCall(VT, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
7278 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128);
7281 LC = GetFPLibCall(VT, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
7282 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128);
7285 LC = GetFPLibCall(VT, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
7286 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128);
7289 LC = GetFPLibCall(VT, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
7290 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128);
7293 LC = GetFPLibCall(VT, RTLIB::RINT_F32, RTLIB::RINT_F64,
7294 RTLIB::RINT_F80, RTLIB::RINT_PPCF128);
7296 case ISD::FNEARBYINT:
7297 LC = GetFPLibCall(VT, RTLIB::NEARBYINT_F32, RTLIB::NEARBYINT_F64,
7298 RTLIB::NEARBYINT_F80, RTLIB::NEARBYINT_PPCF128);
7301 LC = GetFPLibCall(VT, RTLIB::POW_F32, RTLIB::POW_F64, RTLIB::POW_F80,
7302 RTLIB::POW_PPCF128);
7305 LC = GetFPLibCall(VT, RTLIB::POWI_F32, RTLIB::POWI_F64, RTLIB::POWI_F80,
7306 RTLIB::POWI_PPCF128);
7308 default: assert(0 && "Unreachable!");
7310 Lo = ExpandLibCall(LC, Node, false, Hi);
7314 if (VT == MVT::ppcf128) {
7316 ExpandOp(Node->getOperand(0), Lo, Tmp);
7317 Hi = DAG.getNode(ISD::FABS, NVT, Tmp);
7318 // lo = hi==fabs(hi) ? lo : -lo;
7319 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Hi, Tmp,
7320 Lo, DAG.getNode(ISD::FNEG, NVT, Lo),
7321 DAG.getCondCode(ISD::SETEQ));
7324 SDValue Mask = (VT == MVT::f64)
7325 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
7326 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
7327 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7328 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7329 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
7330 if (getTypeAction(NVT) == Expand)
7331 ExpandOp(Lo, Lo, Hi);
7335 if (VT == MVT::ppcf128) {
7336 ExpandOp(Node->getOperand(0), Lo, Hi);
7337 Lo = DAG.getNode(ISD::FNEG, MVT::f64, Lo);
7338 Hi = DAG.getNode(ISD::FNEG, MVT::f64, Hi);
7341 SDValue Mask = (VT == MVT::f64)
7342 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
7343 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
7344 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
7345 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
7346 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
7347 if (getTypeAction(NVT) == Expand)
7348 ExpandOp(Lo, Lo, Hi);
7351 case ISD::FCOPYSIGN: {
7352 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
7353 if (getTypeAction(NVT) == Expand)
7354 ExpandOp(Lo, Lo, Hi);
7357 case ISD::SINT_TO_FP:
7358 case ISD::UINT_TO_FP: {
7359 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
7360 MVT SrcVT = Node->getOperand(0).getValueType();
7362 // Promote the operand if needed. Do this before checking for
7363 // ppcf128 so conversions of i16 and i8 work.
7364 if (getTypeAction(SrcVT) == Promote) {
7365 SDValue Tmp = PromoteOp(Node->getOperand(0));
7367 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
7368 DAG.getValueType(SrcVT))
7369 : DAG.getZeroExtendInReg(Tmp, SrcVT);
7370 Node = DAG.UpdateNodeOperands(Op, Tmp).getNode();
7371 SrcVT = Node->getOperand(0).getValueType();
7374 if (VT == MVT::ppcf128 && SrcVT == MVT::i32) {
7375 static const uint64_t zero = 0;
7377 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7378 Node->getOperand(0)));
7379 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7381 static const uint64_t TwoE32[] = { 0x41f0000000000000LL, 0 };
7382 Hi = LegalizeOp(DAG.getNode(ISD::SINT_TO_FP, MVT::f64,
7383 Node->getOperand(0)));
7384 Lo = DAG.getConstantFP(APFloat(APInt(64, 1, &zero)), MVT::f64);
7385 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7386 // X>=0 ? {(f64)x, 0} : {(f64)x, 0} + 2^32
7387 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7388 DAG.getConstant(0, MVT::i32),
7389 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7391 APFloat(APInt(128, 2, TwoE32)),
7394 DAG.getCondCode(ISD::SETLT)),
7399 if (VT == MVT::ppcf128 && SrcVT == MVT::i64 && !isSigned) {
7400 // si64->ppcf128 done by libcall, below
7401 static const uint64_t TwoE64[] = { 0x43f0000000000000LL, 0 };
7402 ExpandOp(DAG.getNode(ISD::SINT_TO_FP, MVT::ppcf128, Node->getOperand(0)),
7404 Hi = DAG.getNode(ISD::BUILD_PAIR, VT, Lo, Hi);
7405 // x>=0 ? (ppcf128)(i64)x : (ppcf128)(i64)x + 2^64
7406 ExpandOp(DAG.getNode(ISD::SELECT_CC, MVT::ppcf128, Node->getOperand(0),
7407 DAG.getConstant(0, MVT::i64),
7408 DAG.getNode(ISD::FADD, MVT::ppcf128, Hi,
7410 APFloat(APInt(128, 2, TwoE64)),
7413 DAG.getCondCode(ISD::SETLT)),
7418 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
7419 Node->getOperand(0));
7420 if (getTypeAction(Lo.getValueType()) == Expand)
7421 // float to i32 etc. can be 'expanded' to a single node.
7422 ExpandOp(Lo, Lo, Hi);
7427 // Make sure the resultant values have been legalized themselves, unless this
7428 // is a type that requires multi-step expansion.
7429 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
7430 Lo = LegalizeOp(Lo);
7432 // Don't legalize the high part if it is expanded to a single node.
7433 Hi = LegalizeOp(Hi);
7436 // Remember in a map if the values will be reused later.
7438 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7439 assert(isNew && "Value already expanded?!?");
7443 /// SplitVectorOp - Given an operand of vector type, break it down into
7444 /// two smaller values, still of vector type.
7445 void SelectionDAGLegalize::SplitVectorOp(SDValue Op, SDValue &Lo,
7447 assert(Op.getValueType().isVector() && "Cannot split non-vector type!");
7448 SDNode *Node = Op.getNode();
7449 unsigned NumElements = Op.getValueType().getVectorNumElements();
7450 assert(NumElements > 1 && "Cannot split a single element vector!");
7452 MVT NewEltVT = Op.getValueType().getVectorElementType();
7454 unsigned NewNumElts_Lo = 1 << Log2_32(NumElements-1);
7455 unsigned NewNumElts_Hi = NumElements - NewNumElts_Lo;
7457 MVT NewVT_Lo = MVT::getVectorVT(NewEltVT, NewNumElts_Lo);
7458 MVT NewVT_Hi = MVT::getVectorVT(NewEltVT, NewNumElts_Hi);
7460 // See if we already split it.
7461 std::map<SDValue, std::pair<SDValue, SDValue> >::iterator I
7462 = SplitNodes.find(Op);
7463 if (I != SplitNodes.end()) {
7464 Lo = I->second.first;
7465 Hi = I->second.second;
7469 switch (Node->getOpcode()) {
7474 assert(0 && "Unhandled operation in SplitVectorOp!");
7476 Lo = DAG.getNode(ISD::UNDEF, NewVT_Lo);
7477 Hi = DAG.getNode(ISD::UNDEF, NewVT_Hi);
7479 case ISD::BUILD_PAIR:
7480 Lo = Node->getOperand(0);
7481 Hi = Node->getOperand(1);
7483 case ISD::INSERT_VECTOR_ELT: {
7484 if (ConstantSDNode *Idx = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
7485 SplitVectorOp(Node->getOperand(0), Lo, Hi);
7486 unsigned Index = Idx->getZExtValue();
7487 SDValue ScalarOp = Node->getOperand(1);
7488 if (Index < NewNumElts_Lo)
7489 Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Lo, Lo, ScalarOp,
7490 DAG.getIntPtrConstant(Index));
7492 Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT_Hi, Hi, ScalarOp,
7493 DAG.getIntPtrConstant(Index - NewNumElts_Lo));
7496 SDValue Tmp = PerformInsertVectorEltInMemory(Node->getOperand(0),
7497 Node->getOperand(1),
7498 Node->getOperand(2));
7499 SplitVectorOp(Tmp, Lo, Hi);
7502 case ISD::VECTOR_SHUFFLE: {
7503 // Build the low part.
7504 SDValue Mask = Node->getOperand(2);
7505 SmallVector<SDValue, 8> Ops;
7506 MVT PtrVT = TLI.getPointerTy();
7508 // Insert all of the elements from the input that are needed. We use
7509 // buildvector of extractelement here because the input vectors will have
7510 // to be legalized, so this makes the code simpler.
7511 for (unsigned i = 0; i != NewNumElts_Lo; ++i) {
7512 SDValue IdxNode = Mask.getOperand(i);
7513 if (IdxNode.getOpcode() == ISD::UNDEF) {
7514 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7517 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7518 SDValue InVec = Node->getOperand(0);
7519 if (Idx >= NumElements) {
7520 InVec = Node->getOperand(1);
7523 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7524 DAG.getConstant(Idx, PtrVT)));
7526 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &Ops[0], Ops.size());
7529 for (unsigned i = NewNumElts_Lo; i != NumElements; ++i) {
7530 SDValue IdxNode = Mask.getOperand(i);
7531 if (IdxNode.getOpcode() == ISD::UNDEF) {
7532 Ops.push_back(DAG.getNode(ISD::UNDEF, NewEltVT));
7535 unsigned Idx = cast<ConstantSDNode>(IdxNode)->getZExtValue();
7536 SDValue InVec = Node->getOperand(0);
7537 if (Idx >= NumElements) {
7538 InVec = Node->getOperand(1);
7541 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewEltVT, InVec,
7542 DAG.getConstant(Idx, PtrVT)));
7544 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &Ops[0], Ops.size());
7547 case ISD::BUILD_VECTOR: {
7548 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7549 Node->op_begin()+NewNumElts_Lo);
7550 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Lo, &LoOps[0], LoOps.size());
7552 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumElts_Lo,
7554 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT_Hi, &HiOps[0], HiOps.size());
7557 case ISD::CONCAT_VECTORS: {
7558 // FIXME: Handle non-power-of-two vectors?
7559 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
7560 if (NewNumSubvectors == 1) {
7561 Lo = Node->getOperand(0);
7562 Hi = Node->getOperand(1);
7564 SmallVector<SDValue, 8> LoOps(Node->op_begin(),
7565 Node->op_begin()+NewNumSubvectors);
7566 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Lo, &LoOps[0], LoOps.size());
7568 SmallVector<SDValue, 8> HiOps(Node->op_begin()+NewNumSubvectors,
7570 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT_Hi, &HiOps[0], HiOps.size());
7574 case ISD::EXTRACT_SUBVECTOR: {
7575 SDValue Vec = Op.getOperand(0);
7576 SDValue Idx = Op.getOperand(1);
7577 MVT IdxVT = Idx.getValueType();
7579 Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Lo, Vec, Idx);
7580 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
7582 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec,
7583 DAG.getConstant(CIdx->getZExtValue() + NewNumElts_Lo,
7586 Idx = DAG.getNode(ISD::ADD, IdxVT, Idx,
7587 DAG.getConstant(NewNumElts_Lo, IdxVT));
7588 Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, NewVT_Hi, Vec, Idx);
7593 SDValue Cond = Node->getOperand(0);
7595 SDValue LL, LH, RL, RH;
7596 SplitVectorOp(Node->getOperand(1), LL, LH);
7597 SplitVectorOp(Node->getOperand(2), RL, RH);
7599 if (Cond.getValueType().isVector()) {
7600 // Handle a vector merge.
7602 SplitVectorOp(Cond, CL, CH);
7603 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, CL, LL, RL);
7604 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, CH, LH, RH);
7606 // Handle a simple select with vector operands.
7607 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, Cond, LL, RL);
7608 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, Cond, LH, RH);
7612 case ISD::SELECT_CC: {
7613 SDValue CondLHS = Node->getOperand(0);
7614 SDValue CondRHS = Node->getOperand(1);
7615 SDValue CondCode = Node->getOperand(4);
7617 SDValue LL, LH, RL, RH;
7618 SplitVectorOp(Node->getOperand(2), LL, LH);
7619 SplitVectorOp(Node->getOperand(3), RL, RH);
7621 // Handle a simple select with vector operands.
7622 Lo = DAG.getNode(ISD::SELECT_CC, NewVT_Lo, CondLHS, CondRHS,
7624 Hi = DAG.getNode(ISD::SELECT_CC, NewVT_Hi, CondLHS, CondRHS,
7629 SDValue LL, LH, RL, RH;
7630 SplitVectorOp(Node->getOperand(0), LL, LH);
7631 SplitVectorOp(Node->getOperand(1), RL, RH);
7632 Lo = DAG.getNode(ISD::VSETCC, NewVT_Lo, LL, RL, Node->getOperand(2));
7633 Hi = DAG.getNode(ISD::VSETCC, NewVT_Hi, LH, RH, Node->getOperand(2));
7655 SDValue LL, LH, RL, RH;
7656 SplitVectorOp(Node->getOperand(0), LL, LH);
7657 SplitVectorOp(Node->getOperand(1), RL, RH);
7659 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, LL, RL);
7660 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, LH, RH);
7666 SplitVectorOp(Node->getOperand(0), L, H);
7668 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L, Node->getOperand(1));
7669 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H, Node->getOperand(1));
7685 case ISD::FP_TO_SINT:
7686 case ISD::FP_TO_UINT:
7687 case ISD::SINT_TO_FP:
7688 case ISD::UINT_TO_FP:
7690 case ISD::ANY_EXTEND:
7691 case ISD::SIGN_EXTEND:
7692 case ISD::ZERO_EXTEND:
7693 case ISD::FP_EXTEND: {
7695 SplitVectorOp(Node->getOperand(0), L, H);
7697 Lo = DAG.getNode(Node->getOpcode(), NewVT_Lo, L);
7698 Hi = DAG.getNode(Node->getOpcode(), NewVT_Hi, H);
7701 case ISD::CONVERT_RNDSAT: {
7702 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
7704 SplitVectorOp(Node->getOperand(0), L, H);
7705 SDValue DTyOpL = DAG.getValueType(NewVT_Lo);
7706 SDValue DTyOpH = DAG.getValueType(NewVT_Hi);
7707 SDValue STyOpL = DAG.getValueType(L.getValueType());
7708 SDValue STyOpH = DAG.getValueType(H.getValueType());
7710 SDValue RndOp = Node->getOperand(3);
7711 SDValue SatOp = Node->getOperand(4);
7713 Lo = DAG.getConvertRndSat(NewVT_Lo, L, DTyOpL, STyOpL,
7714 RndOp, SatOp, CvtCode);
7715 Hi = DAG.getConvertRndSat(NewVT_Hi, H, DTyOpH, STyOpH,
7716 RndOp, SatOp, CvtCode);
7720 LoadSDNode *LD = cast<LoadSDNode>(Node);
7721 SDValue Ch = LD->getChain();
7722 SDValue Ptr = LD->getBasePtr();
7723 ISD::LoadExtType ExtType = LD->getExtensionType();
7724 const Value *SV = LD->getSrcValue();
7725 int SVOffset = LD->getSrcValueOffset();
7726 MVT MemoryVT = LD->getMemoryVT();
7727 unsigned Alignment = LD->getAlignment();
7728 bool isVolatile = LD->isVolatile();
7730 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7731 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7733 MVT MemNewEltVT = MemoryVT.getVectorElementType();
7734 MVT MemNewVT_Lo = MVT::getVectorVT(MemNewEltVT, NewNumElts_Lo);
7735 MVT MemNewVT_Hi = MVT::getVectorVT(MemNewEltVT, NewNumElts_Hi);
7737 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType,
7738 NewVT_Lo, Ch, Ptr, Offset,
7739 SV, SVOffset, MemNewVT_Lo, isVolatile, Alignment);
7740 unsigned IncrementSize = NewNumElts_Lo * MemNewEltVT.getSizeInBits()/8;
7741 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
7742 DAG.getIntPtrConstant(IncrementSize));
7743 SVOffset += IncrementSize;
7744 Alignment = MinAlign(Alignment, IncrementSize);
7745 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType,
7746 NewVT_Hi, Ch, Ptr, Offset,
7747 SV, SVOffset, MemNewVT_Hi, isVolatile, Alignment);
7749 // Build a factor node to remember that this load is independent of the
7751 SDValue TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
7754 // Remember that we legalized the chain.
7755 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
7758 case ISD::BIT_CONVERT: {
7759 // We know the result is a vector. The input may be either a vector or a
7761 SDValue InOp = Node->getOperand(0);
7762 if (!InOp.getValueType().isVector() ||
7763 InOp.getValueType().getVectorNumElements() == 1) {
7764 // The input is a scalar or single-element vector.
7765 // Lower to a store/load so that it can be split.
7766 // FIXME: this could be improved probably.
7767 unsigned LdAlign = TLI.getTargetData()->getPrefTypeAlignment(
7768 Op.getValueType().getTypeForMVT());
7769 SDValue Ptr = DAG.CreateStackTemporary(InOp.getValueType(), LdAlign);
7770 int FI = cast<FrameIndexSDNode>(Ptr.getNode())->getIndex();
7772 SDValue St = DAG.getStore(DAG.getEntryNode(),
7774 PseudoSourceValue::getFixedStack(FI), 0);
7775 InOp = DAG.getLoad(Op.getValueType(), St, Ptr,
7776 PseudoSourceValue::getFixedStack(FI), 0);
7778 // Split the vector and convert each of the pieces now.
7779 SplitVectorOp(InOp, Lo, Hi);
7780 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT_Lo, Lo);
7781 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT_Hi, Hi);
7786 // Remember in a map if the values will be reused later.
7788 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
7789 assert(isNew && "Value already split?!?");
7794 /// ScalarizeVectorOp - Given an operand of single-element vector type
7795 /// (e.g. v1f32), convert it into the equivalent operation that returns a
7796 /// scalar (e.g. f32) value.
7797 SDValue SelectionDAGLegalize::ScalarizeVectorOp(SDValue Op) {
7798 assert(Op.getValueType().isVector() && "Bad ScalarizeVectorOp invocation!");
7799 SDNode *Node = Op.getNode();
7800 MVT NewVT = Op.getValueType().getVectorElementType();
7801 assert(Op.getValueType().getVectorNumElements() == 1);
7803 // See if we already scalarized it.
7804 std::map<SDValue, SDValue>::iterator I = ScalarizedNodes.find(Op);
7805 if (I != ScalarizedNodes.end()) return I->second;
7808 switch (Node->getOpcode()) {
7811 Node->dump(&DAG); cerr << "\n";
7813 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
7830 Result = DAG.getNode(Node->getOpcode(),
7832 ScalarizeVectorOp(Node->getOperand(0)),
7833 ScalarizeVectorOp(Node->getOperand(1)));
7845 case ISD::FP_TO_SINT:
7846 case ISD::FP_TO_UINT:
7847 case ISD::SINT_TO_FP:
7848 case ISD::UINT_TO_FP:
7849 case ISD::SIGN_EXTEND:
7850 case ISD::ZERO_EXTEND:
7851 case ISD::ANY_EXTEND:
7853 case ISD::FP_EXTEND:
7854 Result = DAG.getNode(Node->getOpcode(),
7856 ScalarizeVectorOp(Node->getOperand(0)));
7858 case ISD::CONVERT_RNDSAT: {
7859 SDValue Op0 = ScalarizeVectorOp(Node->getOperand(0));
7860 Result = DAG.getConvertRndSat(NewVT, Op0,
7861 DAG.getValueType(NewVT),
7862 DAG.getValueType(Op0.getValueType()),
7863 Node->getOperand(3),
7864 Node->getOperand(4),
7865 cast<CvtRndSatSDNode>(Node)->getCvtCode());
7870 Result = DAG.getNode(Node->getOpcode(),
7872 ScalarizeVectorOp(Node->getOperand(0)),
7873 Node->getOperand(1));
7876 LoadSDNode *LD = cast<LoadSDNode>(Node);
7877 SDValue Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
7878 SDValue Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
7879 ISD::LoadExtType ExtType = LD->getExtensionType();
7880 const Value *SV = LD->getSrcValue();
7881 int SVOffset = LD->getSrcValueOffset();
7882 MVT MemoryVT = LD->getMemoryVT();
7883 unsigned Alignment = LD->getAlignment();
7884 bool isVolatile = LD->isVolatile();
7886 assert(LD->isUnindexed() && "Indexed vector loads are not supported yet!");
7887 SDValue Offset = DAG.getNode(ISD::UNDEF, Ptr.getValueType());
7889 Result = DAG.getLoad(ISD::UNINDEXED, ExtType,
7890 NewVT, Ch, Ptr, Offset, SV, SVOffset,
7891 MemoryVT.getVectorElementType(),
7892 isVolatile, Alignment);
7894 // Remember that we legalized the chain.
7895 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
7898 case ISD::BUILD_VECTOR:
7899 Result = Node->getOperand(0);
7901 case ISD::INSERT_VECTOR_ELT:
7902 // Returning the inserted scalar element.
7903 Result = Node->getOperand(1);
7905 case ISD::CONCAT_VECTORS:
7906 assert(Node->getOperand(0).getValueType() == NewVT &&
7907 "Concat of non-legal vectors not yet supported!");
7908 Result = Node->getOperand(0);
7910 case ISD::VECTOR_SHUFFLE: {
7911 // Figure out if the scalar is the LHS or RHS and return it.
7912 SDValue EltNum = Node->getOperand(2).getOperand(0);
7913 if (cast<ConstantSDNode>(EltNum)->getZExtValue())
7914 Result = ScalarizeVectorOp(Node->getOperand(1));
7916 Result = ScalarizeVectorOp(Node->getOperand(0));
7919 case ISD::EXTRACT_SUBVECTOR:
7920 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, NewVT, Node->getOperand(0),
7921 Node->getOperand(1));
7923 case ISD::BIT_CONVERT: {
7924 SDValue Op0 = Op.getOperand(0);
7925 if (Op0.getValueType().getVectorNumElements() == 1)
7926 Op0 = ScalarizeVectorOp(Op0);
7927 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op0);
7931 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
7932 ScalarizeVectorOp(Op.getOperand(1)),
7933 ScalarizeVectorOp(Op.getOperand(2)));
7935 case ISD::SELECT_CC:
7936 Result = DAG.getNode(ISD::SELECT_CC, NewVT, Node->getOperand(0),
7937 Node->getOperand(1),
7938 ScalarizeVectorOp(Op.getOperand(2)),
7939 ScalarizeVectorOp(Op.getOperand(3)),
7940 Node->getOperand(4));
7943 SDValue Op0 = ScalarizeVectorOp(Op.getOperand(0));
7944 SDValue Op1 = ScalarizeVectorOp(Op.getOperand(1));
7945 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(Op0), Op0, Op1,
7947 Result = DAG.getNode(ISD::SELECT, NewVT, Result,
7948 DAG.getConstant(-1ULL, NewVT),
7949 DAG.getConstant(0ULL, NewVT));
7954 if (TLI.isTypeLegal(NewVT))
7955 Result = LegalizeOp(Result);
7956 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
7957 assert(isNew && "Value already scalarized?");
7963 SDValue SelectionDAGLegalize::WidenVectorOp(SDValue Op, MVT WidenVT) {
7964 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(Op);
7965 if (I != WidenNodes.end()) return I->second;
7967 MVT VT = Op.getValueType();
7968 assert(VT.isVector() && "Cannot widen non-vector type!");
7971 SDNode *Node = Op.getNode();
7972 MVT EVT = VT.getVectorElementType();
7974 unsigned NumElts = VT.getVectorNumElements();
7975 unsigned NewNumElts = WidenVT.getVectorNumElements();
7976 assert(NewNumElts > NumElts && "Cannot widen to smaller type!");
7977 assert(NewNumElts < 17);
7979 // When widen is called, it is assumed that it is more efficient to use a
7980 // wide type. The default action is to widen to operation to a wider legal
7981 // vector type and then do the operation if it is legal by calling LegalizeOp
7982 // again. If there is no vector equivalent, we will unroll the operation, do
7983 // it, and rebuild the vector. If most of the operations are vectorizible to
7984 // the legal type, the resulting code will be more efficient. If this is not
7985 // the case, the resulting code will preform badly as we end up generating
7986 // code to pack/unpack the results. It is the function that calls widen
7987 // that is responsible for seeing this doesn't happen.
7988 switch (Node->getOpcode()) {
7993 assert(0 && "Unexpected operation in WidenVectorOp!");
7995 case ISD::CopyFromReg:
7996 assert(0 && "CopyFromReg doesn't need widening!");
7998 case ISD::ConstantFP:
7999 // To build a vector of these elements, clients should call BuildVector
8000 // and with each element instead of creating a node with a vector type
8001 assert(0 && "Unexpected operation in WidenVectorOp!");
8003 // Variable Arguments with vector types doesn't make any sense to me
8004 assert(0 && "Unexpected operation in WidenVectorOp!");
8007 Result = DAG.getNode(ISD::UNDEF, WidenVT);
8009 case ISD::BUILD_VECTOR: {
8010 // Build a vector with undefined for the new nodes
8011 SDValueVector NewOps(Node->op_begin(), Node->op_end());
8012 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8013 NewOps.push_back(DAG.getNode(ISD::UNDEF,EVT));
8015 Result = DAG.getNode(ISD::BUILD_VECTOR, WidenVT, &NewOps[0], NewOps.size());
8018 case ISD::INSERT_VECTOR_ELT: {
8019 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8020 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, WidenVT, Tmp1,
8021 Node->getOperand(1), Node->getOperand(2));
8024 case ISD::VECTOR_SHUFFLE: {
8025 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8026 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8027 // VECTOR_SHUFFLE 3rd operand must be a constant build vector that is
8028 // used as permutation array. We build the vector here instead of widening
8029 // because we don't want to legalize and have it turned to something else.
8030 SDValue PermOp = Node->getOperand(2);
8031 SDValueVector NewOps;
8032 MVT PVT = PermOp.getValueType().getVectorElementType();
8033 for (unsigned i = 0; i < NumElts; ++i) {
8034 if (PermOp.getOperand(i).getOpcode() == ISD::UNDEF) {
8035 NewOps.push_back(PermOp.getOperand(i));
8038 cast<ConstantSDNode>(PermOp.getOperand(i))->getZExtValue();
8039 if (Idx < NumElts) {
8040 NewOps.push_back(PermOp.getOperand(i));
8043 NewOps.push_back(DAG.getConstant(Idx + NewNumElts - NumElts,
8044 PermOp.getOperand(i).getValueType()));
8048 for (unsigned i = NumElts; i < NewNumElts; ++i) {
8049 NewOps.push_back(DAG.getNode(ISD::UNDEF,PVT));
8052 SDValue Tmp3 = DAG.getNode(ISD::BUILD_VECTOR,
8053 MVT::getVectorVT(PVT, NewOps.size()),
8054 &NewOps[0], NewOps.size());
8056 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, WidenVT, Tmp1, Tmp2, Tmp3);
8060 // If the load widen returns true, we can use a single load for the
8061 // vector. Otherwise, it is returning a token factor for multiple
8064 if (LoadWidenVectorOp(Result, TFOp, Op, WidenVT))
8065 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(1)));
8067 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TFOp.getValue(0)));
8071 case ISD::BIT_CONVERT: {
8072 SDValue Tmp1 = Node->getOperand(0);
8073 // Converts between two different types so we need to determine
8074 // the correct widen type for the input operand.
8075 MVT InVT = Tmp1.getValueType();
8076 unsigned WidenSize = WidenVT.getSizeInBits();
8077 if (InVT.isVector()) {
8078 MVT InEltVT = InVT.getVectorElementType();
8079 unsigned InEltSize = InEltVT.getSizeInBits();
8080 assert(WidenSize % InEltSize == 0 &&
8081 "can not widen bit convert that are not multiple of element type");
8082 MVT NewInWidenVT = MVT::getVectorVT(InEltVT, WidenSize / InEltSize);
8083 Tmp1 = WidenVectorOp(Tmp1, NewInWidenVT);
8084 assert(Tmp1.getValueType().getSizeInBits() == WidenVT.getSizeInBits());
8085 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Tmp1);
8087 // If the result size is a multiple of the input size, widen the input
8088 // and then convert.
8089 unsigned InSize = InVT.getSizeInBits();
8090 assert(WidenSize % InSize == 0 &&
8091 "can not widen bit convert that are not multiple of element type");
8092 unsigned NewNumElts = WidenSize / InSize;
8093 SmallVector<SDValue, 16> Ops(NewNumElts);
8094 SDValue UndefVal = DAG.getNode(ISD::UNDEF, InVT);
8096 for (unsigned i = 1; i < NewNumElts; ++i)
8099 MVT NewInVT = MVT::getVectorVT(InVT, NewNumElts);
8100 Result = DAG.getNode(ISD::BUILD_VECTOR, NewInVT, &Ops[0], NewNumElts);
8101 Result = DAG.getNode(ISD::BIT_CONVERT, WidenVT, Result);
8106 case ISD::SINT_TO_FP:
8107 case ISD::UINT_TO_FP:
8108 case ISD::FP_TO_SINT:
8109 case ISD::FP_TO_UINT:
8110 case ISD::FP_ROUND: {
8111 SDValue Tmp1 = Node->getOperand(0);
8112 // Converts between two different types so we need to determine
8113 // the correct widen type for the input operand.
8114 MVT TVT = Tmp1.getValueType();
8115 assert(TVT.isVector() && "can not widen non vector type");
8116 MVT TEVT = TVT.getVectorElementType();
8117 MVT TWidenVT = MVT::getVectorVT(TEVT, NewNumElts);
8118 Tmp1 = WidenVectorOp(Tmp1, TWidenVT);
8119 assert(Tmp1.getValueType().getVectorNumElements() == NewNumElts);
8120 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8124 case ISD::FP_EXTEND:
8125 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
8127 case ISD::SIGN_EXTEND:
8128 case ISD::ZERO_EXTEND:
8129 case ISD::ANY_EXTEND:
8130 case ISD::SIGN_EXTEND_INREG:
8139 // Unary op widening
8141 Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8142 assert(Tmp1.getValueType() == WidenVT);
8143 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1);
8146 case ISD::CONVERT_RNDSAT: {
8147 SDValue RndOp = Node->getOperand(3);
8148 SDValue SatOp = Node->getOperand(4);
8149 SDValue SrcOp = Node->getOperand(0);
8151 // Converts between two different types so we need to determine
8152 // the correct widen type for the input operand.
8153 MVT SVT = SrcOp.getValueType();
8154 assert(SVT.isVector() && "can not widen non vector type");
8155 MVT SEVT = SVT.getVectorElementType();
8156 MVT SWidenVT = MVT::getVectorVT(SEVT, NewNumElts);
8158 SrcOp = WidenVectorOp(SrcOp, SWidenVT);
8159 assert(SrcOp.getValueType() == WidenVT);
8160 SDValue DTyOp = DAG.getValueType(WidenVT);
8161 SDValue STyOp = DAG.getValueType(SrcOp.getValueType());
8162 ISD::CvtCode CvtCode = cast<CvtRndSatSDNode>(Node)->getCvtCode();
8164 Result = DAG.getConvertRndSat(WidenVT, SrcOp, DTyOp, STyOp,
8165 RndOp, SatOp, CvtCode);
8185 case ISD::FCOPYSIGN:
8189 // Binary op widening
8190 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8191 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), WidenVT);
8192 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8193 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2);
8200 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8201 assert(Tmp1.getValueType() == WidenVT);
8202 SDValue ShOp = Node->getOperand(1);
8203 MVT ShVT = ShOp.getValueType();
8204 MVT NewShVT = MVT::getVectorVT(ShVT.getVectorElementType(),
8205 WidenVT.getVectorNumElements());
8206 ShOp = WidenVectorOp(ShOp, NewShVT);
8207 assert(ShOp.getValueType() == NewShVT);
8208 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, ShOp);
8212 case ISD::EXTRACT_VECTOR_ELT: {
8213 SDValue Tmp1 = WidenVectorOp(Node->getOperand(0), WidenVT);
8214 assert(Tmp1.getValueType() == WidenVT);
8215 Result = DAG.getNode(Node->getOpcode(), EVT, Tmp1, Node->getOperand(1));
8218 case ISD::CONCAT_VECTORS: {
8219 // We concurrently support only widen on a multiple of the incoming vector.
8220 // We could widen on a multiple of the incoming operand if necessary.
8221 unsigned NumConcat = NewNumElts / NumElts;
8222 assert(NewNumElts % NumElts == 0 && "Can widen only a multiple of vector");
8223 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8224 SmallVector<SDValue, 8> MOps;
8226 for (unsigned i = 1; i != NumConcat; ++i) {
8227 MOps.push_back(UndefVal);
8229 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8230 &MOps[0], MOps.size()));
8233 case ISD::EXTRACT_SUBVECTOR: {
8234 SDValue Tmp1 = Node->getOperand(0);
8235 SDValue Idx = Node->getOperand(1);
8236 ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
8237 if (CIdx && CIdx->getZExtValue() == 0) {
8238 // Since we are access the start of the vector, the incoming
8239 // vector type might be the proper.
8240 MVT Tmp1VT = Tmp1.getValueType();
8241 if (Tmp1VT == WidenVT)
8244 unsigned Tmp1VTNumElts = Tmp1VT.getVectorNumElements();
8245 if (Tmp1VTNumElts < NewNumElts)
8246 Result = WidenVectorOp(Tmp1, WidenVT);
8248 Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, WidenVT, Tmp1, Idx);
8250 } else if (NewNumElts % NumElts == 0) {
8251 // Widen the extracted subvector.
8252 unsigned NumConcat = NewNumElts / NumElts;
8253 SDValue UndefVal = DAG.getNode(ISD::UNDEF, VT);
8254 SmallVector<SDValue, 8> MOps;
8256 for (unsigned i = 1; i != NumConcat; ++i) {
8257 MOps.push_back(UndefVal);
8259 Result = LegalizeOp(DAG.getNode(ISD::CONCAT_VECTORS, WidenVT,
8260 &MOps[0], MOps.size()));
8262 assert(0 && "can not widen extract subvector");
8263 // This could be implemented using insert and build vector but I would
8264 // like to see when this happens.
8270 // Determine new condition widen type and widen
8271 SDValue Cond1 = Node->getOperand(0);
8272 MVT CondVT = Cond1.getValueType();
8273 assert(CondVT.isVector() && "can not widen non vector type");
8274 MVT CondEVT = CondVT.getVectorElementType();
8275 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8276 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8277 assert(Cond1.getValueType() == CondWidenVT && "Condition not widen");
8279 SDValue Tmp1 = WidenVectorOp(Node->getOperand(1), WidenVT);
8280 SDValue Tmp2 = WidenVectorOp(Node->getOperand(2), WidenVT);
8281 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT);
8282 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Tmp1, Tmp2);
8286 case ISD::SELECT_CC: {
8287 // Determine new condition widen type and widen
8288 SDValue Cond1 = Node->getOperand(0);
8289 SDValue Cond2 = Node->getOperand(1);
8290 MVT CondVT = Cond1.getValueType();
8291 assert(CondVT.isVector() && "can not widen non vector type");
8292 assert(CondVT == Cond2.getValueType() && "mismatch lhs/rhs");
8293 MVT CondEVT = CondVT.getVectorElementType();
8294 MVT CondWidenVT = MVT::getVectorVT(CondEVT, NewNumElts);
8295 Cond1 = WidenVectorOp(Cond1, CondWidenVT);
8296 Cond2 = WidenVectorOp(Cond2, CondWidenVT);
8297 assert(Cond1.getValueType() == CondWidenVT &&
8298 Cond2.getValueType() == CondWidenVT && "condition not widen");
8300 SDValue Tmp1 = WidenVectorOp(Node->getOperand(2), WidenVT);
8301 SDValue Tmp2 = WidenVectorOp(Node->getOperand(3), WidenVT);
8302 assert(Tmp1.getValueType() == WidenVT && Tmp2.getValueType() == WidenVT &&
8303 "operands not widen");
8304 Result = DAG.getNode(Node->getOpcode(), WidenVT, Cond1, Cond2, Tmp1,
8305 Tmp2, Node->getOperand(4));
8309 // Determine widen for the operand
8310 SDValue Tmp1 = Node->getOperand(0);
8311 MVT TmpVT = Tmp1.getValueType();
8312 assert(TmpVT.isVector() && "can not widen non vector type");
8313 MVT TmpEVT = TmpVT.getVectorElementType();
8314 MVT TmpWidenVT = MVT::getVectorVT(TmpEVT, NewNumElts);
8315 Tmp1 = WidenVectorOp(Tmp1, TmpWidenVT);
8316 SDValue Tmp2 = WidenVectorOp(Node->getOperand(1), TmpWidenVT);
8317 Result = DAG.getNode(Node->getOpcode(), WidenVT, Tmp1, Tmp2,
8318 Node->getOperand(2));
8321 case ISD::ATOMIC_CMP_SWAP_8:
8322 case ISD::ATOMIC_CMP_SWAP_16:
8323 case ISD::ATOMIC_CMP_SWAP_32:
8324 case ISD::ATOMIC_CMP_SWAP_64:
8325 case ISD::ATOMIC_LOAD_ADD_8:
8326 case ISD::ATOMIC_LOAD_SUB_8:
8327 case ISD::ATOMIC_LOAD_AND_8:
8328 case ISD::ATOMIC_LOAD_OR_8:
8329 case ISD::ATOMIC_LOAD_XOR_8:
8330 case ISD::ATOMIC_LOAD_NAND_8:
8331 case ISD::ATOMIC_LOAD_MIN_8:
8332 case ISD::ATOMIC_LOAD_MAX_8:
8333 case ISD::ATOMIC_LOAD_UMIN_8:
8334 case ISD::ATOMIC_LOAD_UMAX_8:
8335 case ISD::ATOMIC_SWAP_8:
8336 case ISD::ATOMIC_LOAD_ADD_16:
8337 case ISD::ATOMIC_LOAD_SUB_16:
8338 case ISD::ATOMIC_LOAD_AND_16:
8339 case ISD::ATOMIC_LOAD_OR_16:
8340 case ISD::ATOMIC_LOAD_XOR_16:
8341 case ISD::ATOMIC_LOAD_NAND_16:
8342 case ISD::ATOMIC_LOAD_MIN_16:
8343 case ISD::ATOMIC_LOAD_MAX_16:
8344 case ISD::ATOMIC_LOAD_UMIN_16:
8345 case ISD::ATOMIC_LOAD_UMAX_16:
8346 case ISD::ATOMIC_SWAP_16:
8347 case ISD::ATOMIC_LOAD_ADD_32:
8348 case ISD::ATOMIC_LOAD_SUB_32:
8349 case ISD::ATOMIC_LOAD_AND_32:
8350 case ISD::ATOMIC_LOAD_OR_32:
8351 case ISD::ATOMIC_LOAD_XOR_32:
8352 case ISD::ATOMIC_LOAD_NAND_32:
8353 case ISD::ATOMIC_LOAD_MIN_32:
8354 case ISD::ATOMIC_LOAD_MAX_32:
8355 case ISD::ATOMIC_LOAD_UMIN_32:
8356 case ISD::ATOMIC_LOAD_UMAX_32:
8357 case ISD::ATOMIC_SWAP_32:
8358 case ISD::ATOMIC_LOAD_ADD_64:
8359 case ISD::ATOMIC_LOAD_SUB_64:
8360 case ISD::ATOMIC_LOAD_AND_64:
8361 case ISD::ATOMIC_LOAD_OR_64:
8362 case ISD::ATOMIC_LOAD_XOR_64:
8363 case ISD::ATOMIC_LOAD_NAND_64:
8364 case ISD::ATOMIC_LOAD_MIN_64:
8365 case ISD::ATOMIC_LOAD_MAX_64:
8366 case ISD::ATOMIC_LOAD_UMIN_64:
8367 case ISD::ATOMIC_LOAD_UMAX_64:
8368 case ISD::ATOMIC_SWAP_64: {
8369 // For now, we assume that using vectors for these operations don't make
8370 // much sense so we just split it. We return an empty result
8372 SplitVectorOp(Op, X, Y);
8377 } // end switch (Node->getOpcode())
8379 assert(Result.getNode() && "Didn't set a result!");
8381 Result = LegalizeOp(Result);
8383 AddWidenedOperand(Op, Result);
8387 // Utility function to find a legal vector type and its associated element
8388 // type from a preferred width and whose vector type must be the same size
8390 // TLI: Target lowering used to determine legal types
8391 // Width: Preferred width of element type
8392 // VVT: Vector value type whose size we must match.
8393 // Returns VecEVT and EVT - the vector type and its associated element type
8394 static void FindWidenVecType(TargetLowering &TLI, unsigned Width, MVT VVT,
8395 MVT& EVT, MVT& VecEVT) {
8396 // We start with the preferred width, make it a power of 2 and see if
8397 // we can find a vector type of that width. If not, we reduce it by
8398 // another power of 2. If we have widen the type, a vector of bytes should
8400 assert(TLI.isTypeLegal(VVT));
8401 unsigned EWidth = Width + 1;
8404 EWidth = (1 << Log2_32(EWidth-1));
8405 EVT = MVT::getIntegerVT(EWidth);
8406 unsigned NumEVT = VVT.getSizeInBits()/EWidth;
8407 VecEVT = MVT::getVectorVT(EVT, NumEVT);
8408 } while (!TLI.isTypeLegal(VecEVT) ||
8409 VVT.getSizeInBits() != VecEVT.getSizeInBits());
8412 SDValue SelectionDAGLegalize::genWidenVectorLoads(SDValueVector& LdChain,
8421 // We assume that we have good rules to handle loading power of two loads so
8422 // we break down the operations to power of 2 loads. The strategy is to
8423 // load the largest power of 2 that we can easily transform to a legal vector
8424 // and then insert into that vector, and the cast the result into the legal
8425 // vector that we want. This avoids unnecessary stack converts.
8426 // TODO: If the Ldwidth is legal, alignment is the same as the LdWidth, and
8427 // the load is nonvolatile, we an use a wider load for the value.
8428 // Find a vector length we can load a large chunk
8431 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8432 EVTWidth = EVT.getSizeInBits();
8434 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV, SVOffset,
8435 isVolatile, Alignment);
8436 SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, VecEVT, LdOp);
8437 LdChain.push_back(LdOp.getValue(1));
8439 // Check if we can load the element with one instruction
8440 if (LdWidth == EVTWidth) {
8441 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8444 // The vector element order is endianness dependent.
8446 LdWidth -= EVTWidth;
8447 unsigned Offset = 0;
8449 while (LdWidth > 0) {
8450 unsigned Increment = EVTWidth / 8;
8451 Offset += Increment;
8452 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8453 DAG.getIntPtrConstant(Increment));
8455 if (LdWidth < EVTWidth) {
8456 // Our current type we are using is too large, use a smaller size by
8457 // using a smaller power of 2
8458 unsigned oEVTWidth = EVTWidth;
8459 FindWidenVecType(TLI, LdWidth, ResType, EVT, VecEVT);
8460 EVTWidth = EVT.getSizeInBits();
8461 // Readjust position and vector position based on new load type
8462 Idx = Idx * (oEVTWidth/EVTWidth);
8463 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8466 SDValue LdOp = DAG.getLoad(EVT, Chain, BasePtr, SV,
8467 SVOffset+Offset, isVolatile,
8468 MinAlign(Alignment, Offset));
8469 LdChain.push_back(LdOp.getValue(1));
8470 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, VecEVT, VecOp, LdOp,
8471 DAG.getIntPtrConstant(Idx++));
8473 LdWidth -= EVTWidth;
8476 return DAG.getNode(ISD::BIT_CONVERT, ResType, VecOp);
8479 bool SelectionDAGLegalize::LoadWidenVectorOp(SDValue& Result,
8483 // TODO: Add support for ConcatVec and the ability to load many vector
8484 // types (e.g., v4i8). This will not work when a vector register
8485 // to memory mapping is strange (e.g., vector elements are not
8486 // stored in some sequential order).
8488 // It must be true that the widen vector type is bigger than where
8489 // we need to load from.
8490 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode());
8491 MVT LdVT = LD->getMemoryVT();
8492 assert(LdVT.isVector() && NVT.isVector());
8493 assert(LdVT.getVectorElementType() == NVT.getVectorElementType());
8496 SDValue Chain = LD->getChain();
8497 SDValue BasePtr = LD->getBasePtr();
8498 int SVOffset = LD->getSrcValueOffset();
8499 unsigned Alignment = LD->getAlignment();
8500 bool isVolatile = LD->isVolatile();
8501 const Value *SV = LD->getSrcValue();
8502 unsigned int LdWidth = LdVT.getSizeInBits();
8504 // Load value as a large register
8505 SDValueVector LdChain;
8506 Result = genWidenVectorLoads(LdChain, Chain, BasePtr, SV, SVOffset,
8507 Alignment, isVolatile, LdWidth, NVT);
8509 if (LdChain.size() == 1) {
8514 TFOp=DAG.getNode(ISD::TokenFactor, MVT::Other, &LdChain[0], LdChain.size());
8520 void SelectionDAGLegalize::genWidenVectorStores(SDValueVector& StChain,
8529 // Breaks the stores into a series of power of 2 width stores. For any
8530 // width, we convert the vector to the vector of element size that we
8531 // want to store. This avoids requiring a stack convert.
8533 // Find a width of the element type we can store with
8534 MVT VVT = ValOp.getValueType();
8537 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8538 EVTWidth = EVT.getSizeInBits();
8540 SDValue VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, ValOp);
8541 SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8542 DAG.getIntPtrConstant(0));
8543 SDValue StOp = DAG.getStore(Chain, EOp, BasePtr, SV, SVOffset,
8544 isVolatile, Alignment);
8545 StChain.push_back(StOp);
8547 // Check if we are done
8548 if (StWidth == EVTWidth) {
8553 StWidth -= EVTWidth;
8554 unsigned Offset = 0;
8556 while (StWidth > 0) {
8557 unsigned Increment = EVTWidth / 8;
8558 Offset += Increment;
8559 BasePtr = DAG.getNode(ISD::ADD, BasePtr.getValueType(), BasePtr,
8560 DAG.getIntPtrConstant(Increment));
8562 if (StWidth < EVTWidth) {
8563 // Our current type we are using is too large, use a smaller size by
8564 // using a smaller power of 2
8565 unsigned oEVTWidth = EVTWidth;
8566 FindWidenVecType(TLI, StWidth, VVT, EVT, VecEVT);
8567 EVTWidth = EVT.getSizeInBits();
8568 // Readjust position and vector position based on new load type
8569 Idx = Idx * (oEVTWidth/EVTWidth);
8570 VecOp = DAG.getNode(ISD::BIT_CONVERT, VecEVT, VecOp);
8573 EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EVT, VecOp,
8574 DAG.getIntPtrConstant(Idx++));
8575 StChain.push_back(DAG.getStore(Chain, EOp, BasePtr, SV,
8576 SVOffset + Offset, isVolatile,
8577 MinAlign(Alignment, Offset)));
8578 StWidth -= EVTWidth;
8583 SDValue SelectionDAGLegalize::StoreWidenVectorOp(StoreSDNode *ST,
8586 // TODO: It might be cleaner if we can use SplitVector and have more legal
8587 // vector types that can be stored into memory (e.g., v4xi8 can
8588 // be stored as a word). This will not work when a vector register
8589 // to memory mapping is strange (e.g., vector elements are not
8590 // stored in some sequential order).
8592 MVT StVT = ST->getMemoryVT();
8593 SDValue ValOp = ST->getValue();
8595 // Check if we have widen this node with another value
8596 std::map<SDValue, SDValue>::iterator I = WidenNodes.find(ValOp);
8597 if (I != WidenNodes.end())
8600 MVT VVT = ValOp.getValueType();
8602 // It must be true that we the widen vector type is bigger than where
8603 // we need to store.
8604 assert(StVT.isVector() && VVT.isVector());
8605 assert(StVT.getSizeInBits() < VVT.getSizeInBits());
8606 assert(StVT.getVectorElementType() == VVT.getVectorElementType());
8609 SDValueVector StChain;
8610 genWidenVectorStores(StChain, Chain, BasePtr, ST->getSrcValue(),
8611 ST->getSrcValueOffset(), ST->getAlignment(),
8612 ST->isVolatile(), ValOp, StVT.getSizeInBits());
8613 if (StChain.size() == 1)
8616 return DAG.getNode(ISD::TokenFactor, MVT::Other,&StChain[0],StChain.size());
8620 // SelectionDAG::Legalize - This is the entry point for the file.
8622 void SelectionDAG::Legalize(bool TypesNeedLegalizing) {
8623 /// run - This is the main entry point to this class.
8625 SelectionDAGLegalize(*this, TypesNeedLegalizing).LegalizeDAG();