1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Analysis/DebugInfo.h"
15 #include "llvm/CodeGen/Analysis.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetFrameLowering.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetData.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/DerivedTypes.h"
26 #include "llvm/LLVMContext.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/Support/raw_ostream.h"
31 #include "llvm/ADT/DenseMap.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/SmallPtrSet.h"
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize {
50 const TargetMachine &TM;
51 const TargetLowering &TLI;
54 // Libcall insertion helpers.
56 /// LastCALLSEQ - This keeps track of the CALLSEQ_END node that has been
57 /// legalized. We use this to ensure that calls are properly serialized
58 /// against each other, including inserted libcalls.
59 SmallVector<SDValue, 8> LastCALLSEQ;
62 Legal, // The target natively supports this operation.
63 Promote, // This operation should be executed in a larger type.
64 Expand // Try to expand this to other ops, otherwise use a libcall.
67 /// ValueTypeActions - This is a bitvector that contains two bits for each
68 /// value type, where the two bits correspond to the LegalizeAction enum.
69 /// This can be queried with "getTypeAction(VT)".
70 TargetLowering::ValueTypeActionImpl ValueTypeActions;
72 /// LegalizedNodes - For nodes that are of legal width, and that have more
73 /// than one use, this map indicates what regularized operand to use. This
74 /// allows us to avoid legalizing the same thing more than once.
75 DenseMap<SDValue, SDValue> LegalizedNodes;
77 void AddLegalizedOperand(SDValue From, SDValue To) {
78 LegalizedNodes.insert(std::make_pair(From, To));
79 // If someone requests legalization of the new node, return itself.
81 LegalizedNodes.insert(std::make_pair(To, To));
83 // Transfer SDDbgValues.
84 DAG.TransferDbgValues(From, To);
88 explicit SelectionDAGLegalize(SelectionDAG &DAG);
90 /// getTypeAction - Return how we should legalize values of this type, either
91 /// it is already legal or we need to expand it into multiple registers of
92 /// smaller integer type, or we need to promote it to a larger type.
93 LegalizeAction getTypeAction(EVT VT) const {
94 return (LegalizeAction)TLI.getTypeAction(*DAG.getContext(), VT);
97 /// isTypeLegal - Return true if this type is legal on this target.
99 bool isTypeLegal(EVT VT) const {
100 return getTypeAction(VT) == Legal;
106 /// LegalizeOp - Return a legal replacement for the given operation, with
107 /// all legal operands.
108 SDValue LegalizeOp(SDValue O);
110 SDValue OptimizeFloatStore(StoreSDNode *ST);
112 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
113 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
114 /// is necessary to spill the vector being inserted into to memory, perform
115 /// the insert there, and then read the result back.
116 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
117 SDValue Idx, DebugLoc dl);
118 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
119 SDValue Idx, DebugLoc dl);
121 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
122 /// performs the same shuffe in terms of order or result bytes, but on a type
123 /// whose vector element type is narrower than the original shuffle type.
124 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
125 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
126 SDValue N1, SDValue N2,
127 SmallVectorImpl<int> &Mask) const;
129 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
130 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
132 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
135 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
136 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops,
137 unsigned NumOps, bool isSigned, DebugLoc dl);
139 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC,
140 SDNode *Node, bool isSigned);
141 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
142 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
143 RTLIB::Libcall Call_PPCF128);
144 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
145 RTLIB::Libcall Call_I8,
146 RTLIB::Libcall Call_I16,
147 RTLIB::Libcall Call_I32,
148 RTLIB::Libcall Call_I64,
149 RTLIB::Libcall Call_I128);
150 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results);
152 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
153 SDValue ExpandBUILD_VECTOR(SDNode *Node);
154 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
155 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
156 SmallVectorImpl<SDValue> &Results);
157 SDValue ExpandFCOPYSIGN(SDNode *Node);
158 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
160 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
162 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
165 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
166 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
168 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
169 SDValue ExpandInsertToVectorThroughStack(SDValue Op);
170 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
172 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node);
174 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
175 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
177 SDValue getLastCALLSEQ() { return LastCALLSEQ.back(); }
178 void setLastCALLSEQ(const SDValue s) { LastCALLSEQ.back() = s; }
179 void pushLastCALLSEQ(SDValue s) {
180 LastCALLSEQ.push_back(s);
182 void popLastCALLSEQ() {
183 LastCALLSEQ.pop_back();
188 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
189 /// performs the same shuffe in terms of order or result bytes, but on a type
190 /// whose vector element type is narrower than the original shuffle type.
191 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
193 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
194 SDValue N1, SDValue N2,
195 SmallVectorImpl<int> &Mask) const {
196 unsigned NumMaskElts = VT.getVectorNumElements();
197 unsigned NumDestElts = NVT.getVectorNumElements();
198 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
200 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
202 if (NumEltsGrowth == 1)
203 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
205 SmallVector<int, 8> NewMask;
206 for (unsigned i = 0; i != NumMaskElts; ++i) {
208 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
210 NewMask.push_back(-1);
212 NewMask.push_back(Idx * NumEltsGrowth + j);
215 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
216 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
217 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
220 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
221 : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
223 ValueTypeActions(TLI.getValueTypeActions()) {
224 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
225 "Too many value types for ValueTypeActions to hold!");
228 void SelectionDAGLegalize::LegalizeDAG() {
229 pushLastCALLSEQ(DAG.getEntryNode());
231 // The legalize process is inherently a bottom-up recursive process (users
232 // legalize their uses before themselves). Given infinite stack space, we
233 // could just start legalizing on the root and traverse the whole graph. In
234 // practice however, this causes us to run out of stack space on large basic
235 // blocks. To avoid this problem, compute an ordering of the nodes where each
236 // node is only legalized after all of its operands are legalized.
237 DAG.AssignTopologicalOrder();
238 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
239 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I)
240 LegalizeOp(SDValue(I, 0));
242 // Finally, it's possible the root changed. Get the new root.
243 SDValue OldRoot = DAG.getRoot();
244 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
245 DAG.setRoot(LegalizedNodes[OldRoot]);
247 LegalizedNodes.clear();
249 // Remove dead nodes now.
250 DAG.RemoveDeadNodes();
254 /// FindCallEndFromCallStart - Given a chained node that is part of a call
255 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
256 static SDNode *FindCallEndFromCallStart(SDNode *Node, int depth = 0) {
257 int next_depth = depth;
258 if (Node->getOpcode() == ISD::CALLSEQ_START)
259 next_depth = depth + 1;
260 if (Node->getOpcode() == ISD::CALLSEQ_END) {
261 assert(depth > 0 && "negative depth!");
265 next_depth = depth - 1;
267 if (Node->use_empty())
268 return 0; // No CallSeqEnd
270 // The chain is usually at the end.
271 SDValue TheChain(Node, Node->getNumValues()-1);
272 if (TheChain.getValueType() != MVT::Other) {
273 // Sometimes it's at the beginning.
274 TheChain = SDValue(Node, 0);
275 if (TheChain.getValueType() != MVT::Other) {
276 // Otherwise, hunt for it.
277 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
278 if (Node->getValueType(i) == MVT::Other) {
279 TheChain = SDValue(Node, i);
283 // Otherwise, we walked into a node without a chain.
284 if (TheChain.getValueType() != MVT::Other)
289 for (SDNode::use_iterator UI = Node->use_begin(),
290 E = Node->use_end(); UI != E; ++UI) {
292 // Make sure to only follow users of our token chain.
294 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
295 if (User->getOperand(i) == TheChain)
296 if (SDNode *Result = FindCallEndFromCallStart(User, next_depth))
302 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
303 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
304 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
306 assert(Node && "Didn't find callseq_start for a call??");
307 while (Node->getOpcode() != ISD::CALLSEQ_START || nested) {
308 Node = Node->getOperand(0).getNode();
309 assert(Node->getOperand(0).getValueType() == MVT::Other &&
310 "Node doesn't have a token chain argument!");
311 switch (Node->getOpcode()) {
314 case ISD::CALLSEQ_START:
317 Node = Node->getOperand(0).getNode();
320 case ISD::CALLSEQ_END:
325 return (Node->getOpcode() == ISD::CALLSEQ_START) ? Node : 0;
328 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
329 /// see if any uses can reach Dest. If no dest operands can get to dest,
330 /// legalize them, legalize ourself, and return false, otherwise, return true.
332 /// Keep track of the nodes we fine that actually do lead to Dest in
333 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
335 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
336 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
337 if (N == Dest) return true; // N certainly leads to Dest :)
339 // If we've already processed this node and it does lead to Dest, there is no
340 // need to reprocess it.
341 if (NodesLeadingTo.count(N)) return true;
343 // If the first result of this node has been already legalized, then it cannot
345 if (LegalizedNodes.count(SDValue(N, 0))) return false;
347 // Okay, this node has not already been legalized. Check and legalize all
348 // operands. If none lead to Dest, then we can legalize this node.
349 bool OperandsLeadToDest = false;
350 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
351 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
352 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest,
355 if (OperandsLeadToDest) {
356 NodesLeadingTo.insert(N);
360 // Okay, this node looks safe, legalize it and return false.
361 LegalizeOp(SDValue(N, 0));
365 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
366 /// a load from the constant pool.
367 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
368 SelectionDAG &DAG, const TargetLowering &TLI) {
370 DebugLoc dl = CFP->getDebugLoc();
372 // If a FP immediate is precise when represented as a float and if the
373 // target can do an extending load from float to double, we put it into
374 // the constant pool as a float, even if it's is statically typed as a
375 // double. This shrinks FP constants and canonicalizes them for targets where
376 // an FP extending load is the same cost as a normal load (such as on the x87
377 // fp stack or PPC FP unit).
378 EVT VT = CFP->getValueType(0);
379 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
381 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
382 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
383 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
388 while (SVT != MVT::f32) {
389 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
390 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) &&
391 // Only do this if the target has a native EXTLOAD instruction from
393 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
394 TLI.ShouldShrinkFPConstant(OrigVT)) {
395 const Type *SType = SVT.getTypeForEVT(*DAG.getContext());
396 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
402 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
403 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
405 return DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT,
407 CPIdx, MachinePointerInfo::getConstantPool(),
408 VT, false, false, Alignment);
409 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
410 MachinePointerInfo::getConstantPool(), false, false,
414 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
416 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
417 const TargetLowering &TLI) {
418 SDValue Chain = ST->getChain();
419 SDValue Ptr = ST->getBasePtr();
420 SDValue Val = ST->getValue();
421 EVT VT = Val.getValueType();
422 int Alignment = ST->getAlignment();
423 DebugLoc dl = ST->getDebugLoc();
424 if (ST->getMemoryVT().isFloatingPoint() ||
425 ST->getMemoryVT().isVector()) {
426 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
427 if (TLI.isTypeLegal(intVT)) {
428 // Expand to a bitconvert of the value to the integer type of the
429 // same size, then a (misaligned) int store.
430 // FIXME: Does not handle truncating floating point stores!
431 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val);
432 return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(),
433 ST->isVolatile(), ST->isNonTemporal(), Alignment);
435 // Do a (aligned) store to a stack slot, then copy from the stack slot
436 // to the final destination using (unaligned) integer loads and stores.
437 EVT StoredVT = ST->getMemoryVT();
439 TLI.getRegisterType(*DAG.getContext(),
440 EVT::getIntegerVT(*DAG.getContext(),
441 StoredVT.getSizeInBits()));
442 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
443 unsigned RegBytes = RegVT.getSizeInBits() / 8;
444 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
446 // Make sure the stack slot is also aligned for the register type.
447 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
449 // Perform the original store, only redirected to the stack slot.
450 SDValue Store = DAG.getTruncStore(Chain, dl,
451 Val, StackPtr, MachinePointerInfo(),
452 StoredVT, false, false, 0);
453 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
454 SmallVector<SDValue, 8> Stores;
457 // Do all but one copies using the full register width.
458 for (unsigned i = 1; i < NumRegs; i++) {
459 // Load one integer register's worth from the stack slot.
460 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr,
461 MachinePointerInfo(),
463 // Store it to the final location. Remember the store.
464 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
465 ST->getPointerInfo().getWithOffset(Offset),
466 ST->isVolatile(), ST->isNonTemporal(),
467 MinAlign(ST->getAlignment(), Offset)));
468 // Increment the pointers.
470 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
472 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
475 // The last store may be partial. Do a truncating store. On big-endian
476 // machines this requires an extending load from the stack slot to ensure
477 // that the bits are in the right place.
478 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
479 8 * (StoredBytes - Offset));
481 // Load from the stack slot.
482 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
483 MachinePointerInfo(),
484 MemVT, false, false, 0);
486 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
488 .getWithOffset(Offset),
489 MemVT, ST->isVolatile(),
491 MinAlign(ST->getAlignment(), Offset)));
492 // The order of the stores doesn't matter - say it with a TokenFactor.
493 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
496 assert(ST->getMemoryVT().isInteger() &&
497 !ST->getMemoryVT().isVector() &&
498 "Unaligned store of unknown type.");
499 // Get the half-size VT
500 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext());
501 int NumBits = NewStoredVT.getSizeInBits();
502 int IncrementSize = NumBits / 8;
504 // Divide the stored value in two parts.
505 SDValue ShiftAmount = DAG.getConstant(NumBits,
506 TLI.getShiftAmountTy(Val.getValueType()));
508 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
510 // Store the two parts
511 SDValue Store1, Store2;
512 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
513 ST->getPointerInfo(), NewStoredVT,
514 ST->isVolatile(), ST->isNonTemporal(), Alignment);
515 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
516 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
517 Alignment = MinAlign(Alignment, IncrementSize);
518 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
519 ST->getPointerInfo().getWithOffset(IncrementSize),
520 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(),
523 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
526 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
528 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
529 const TargetLowering &TLI) {
530 SDValue Chain = LD->getChain();
531 SDValue Ptr = LD->getBasePtr();
532 EVT VT = LD->getValueType(0);
533 EVT LoadedVT = LD->getMemoryVT();
534 DebugLoc dl = LD->getDebugLoc();
535 if (VT.isFloatingPoint() || VT.isVector()) {
536 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits());
537 if (TLI.isTypeLegal(intVT)) {
538 // Expand to a (misaligned) integer load of the same size,
539 // then bitconvert to floating point or vector.
540 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(),
542 LD->isNonTemporal(), LD->getAlignment());
543 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad);
544 if (VT.isFloatingPoint() && LoadedVT != VT)
545 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
547 SDValue Ops[] = { Result, Chain };
548 return DAG.getMergeValues(Ops, 2, dl);
551 // Copy the value to a (aligned) stack slot using (unaligned) integer
552 // loads and stores, then do a (aligned) load from the stack slot.
553 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT);
554 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
555 unsigned RegBytes = RegVT.getSizeInBits() / 8;
556 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
558 // Make sure the stack slot is also aligned for the register type.
559 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
561 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
562 SmallVector<SDValue, 8> Stores;
563 SDValue StackPtr = StackBase;
566 // Do all but one copies using the full register width.
567 for (unsigned i = 1; i < NumRegs; i++) {
568 // Load one integer register's worth from the original location.
569 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr,
570 LD->getPointerInfo().getWithOffset(Offset),
571 LD->isVolatile(), LD->isNonTemporal(),
572 MinAlign(LD->getAlignment(), Offset));
573 // Follow the load with a store to the stack slot. Remember the store.
574 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
575 MachinePointerInfo(), false, false, 0));
576 // Increment the pointers.
578 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
579 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
583 // The last copy may be partial. Do an extending load.
584 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(),
585 8 * (LoadedBytes - Offset));
586 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
587 LD->getPointerInfo().getWithOffset(Offset),
588 MemVT, LD->isVolatile(),
590 MinAlign(LD->getAlignment(), Offset));
591 // Follow the load with a store to the stack slot. Remember the store.
592 // On big-endian machines this requires a truncating store to ensure
593 // that the bits end up in the right place.
594 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
595 MachinePointerInfo(), MemVT,
598 // The order of the stores doesn't matter - say it with a TokenFactor.
599 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
602 // Finally, perform the original load only redirected to the stack slot.
603 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
604 MachinePointerInfo(), LoadedVT, false, false, 0);
606 // Callers expect a MERGE_VALUES node.
607 SDValue Ops[] = { Load, TF };
608 return DAG.getMergeValues(Ops, 2, dl);
610 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
611 "Unaligned load of unsupported type.");
613 // Compute the new VT that is half the size of the old one. This is an
615 unsigned NumBits = LoadedVT.getSizeInBits();
617 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2);
620 unsigned Alignment = LD->getAlignment();
621 unsigned IncrementSize = NumBits / 8;
622 ISD::LoadExtType HiExtType = LD->getExtensionType();
624 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
625 if (HiExtType == ISD::NON_EXTLOAD)
626 HiExtType = ISD::ZEXTLOAD;
628 // Load the value in two parts
630 if (TLI.isLittleEndian()) {
631 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
632 NewLoadedVT, LD->isVolatile(),
633 LD->isNonTemporal(), Alignment);
634 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
635 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
636 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
637 LD->getPointerInfo().getWithOffset(IncrementSize),
638 NewLoadedVT, LD->isVolatile(),
639 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
641 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
642 NewLoadedVT, LD->isVolatile(),
643 LD->isNonTemporal(), Alignment);
644 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
645 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
646 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
647 LD->getPointerInfo().getWithOffset(IncrementSize),
648 NewLoadedVT, LD->isVolatile(),
649 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize));
652 // aggregate the two parts
653 SDValue ShiftAmount = DAG.getConstant(NumBits,
654 TLI.getShiftAmountTy(Hi.getValueType()));
655 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
656 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
658 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
661 SDValue Ops[] = { Result, TF };
662 return DAG.getMergeValues(Ops, 2, dl);
665 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
666 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
667 /// is necessary to spill the vector being inserted into to memory, perform
668 /// the insert there, and then read the result back.
669 SDValue SelectionDAGLegalize::
670 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
676 // If the target doesn't support this, we have to spill the input vector
677 // to a temporary stack slot, update the element, then reload it. This is
678 // badness. We could also load the value into a vector register (either
679 // with a "move to register" or "extload into register" instruction, then
680 // permute it into place, if the idx is a constant and if the idx is
681 // supported by the target.
682 EVT VT = Tmp1.getValueType();
683 EVT EltVT = VT.getVectorElementType();
684 EVT IdxVT = Tmp3.getValueType();
685 EVT PtrVT = TLI.getPointerTy();
686 SDValue StackPtr = DAG.CreateStackTemporary(VT);
688 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
691 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
692 MachinePointerInfo::getFixedStack(SPFI),
695 // Truncate or zero extend offset to target pointer type.
696 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
697 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
698 // Add the offset to the index.
699 unsigned EltSize = EltVT.getSizeInBits()/8;
700 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
701 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
702 // Store the scalar value.
703 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT,
705 // Load the updated vector.
706 return DAG.getLoad(VT, dl, Ch, StackPtr,
707 MachinePointerInfo::getFixedStack(SPFI), false, false, 0);
711 SDValue SelectionDAGLegalize::
712 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
713 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
714 // SCALAR_TO_VECTOR requires that the type of the value being inserted
715 // match the element type of the vector being created, except for
716 // integers in which case the inserted value can be over width.
717 EVT EltVT = Vec.getValueType().getVectorElementType();
718 if (Val.getValueType() == EltVT ||
719 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
720 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
721 Vec.getValueType(), Val);
723 unsigned NumElts = Vec.getValueType().getVectorNumElements();
724 // We generate a shuffle of InVec and ScVec, so the shuffle mask
725 // should be 0,1,2,3,4,5... with the appropriate element replaced with
727 SmallVector<int, 8> ShufOps;
728 for (unsigned i = 0; i != NumElts; ++i)
729 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
731 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
735 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
738 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
739 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
740 // FIXME: We shouldn't do this for TargetConstantFP's.
741 // FIXME: move this to the DAG Combiner! Note that we can't regress due
742 // to phase ordering between legalized code and the dag combiner. This
743 // probably means that we need to integrate dag combiner and legalizer
745 // We generally can't do this one for long doubles.
746 SDValue Tmp1 = ST->getChain();
747 SDValue Tmp2 = ST->getBasePtr();
749 unsigned Alignment = ST->getAlignment();
750 bool isVolatile = ST->isVolatile();
751 bool isNonTemporal = ST->isNonTemporal();
752 DebugLoc dl = ST->getDebugLoc();
753 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
754 if (CFP->getValueType(0) == MVT::f32 &&
755 getTypeAction(MVT::i32) == Legal) {
756 Tmp3 = DAG.getConstant(CFP->getValueAPF().
757 bitcastToAPInt().zextOrTrunc(32),
759 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
760 isVolatile, isNonTemporal, Alignment);
763 if (CFP->getValueType(0) == MVT::f64) {
764 // If this target supports 64-bit registers, do a single 64-bit store.
765 if (getTypeAction(MVT::i64) == Legal) {
766 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
767 zextOrTrunc(64), MVT::i64);
768 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
769 isVolatile, isNonTemporal, Alignment);
772 if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
773 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
774 // stores. If the target supports neither 32- nor 64-bits, this
775 // xform is certainly not worth it.
776 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
777 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32);
778 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
779 if (TLI.isBigEndian()) std::swap(Lo, Hi);
781 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getPointerInfo(), isVolatile,
782 isNonTemporal, Alignment);
783 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
784 DAG.getIntPtrConstant(4));
785 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2,
786 ST->getPointerInfo().getWithOffset(4),
787 isVolatile, isNonTemporal, MinAlign(Alignment, 4U));
789 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
793 return SDValue(0, 0);
796 /// LegalizeOp - Return a legal replacement for the given operation, with
797 /// all legal operands.
798 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
799 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
802 SDNode *Node = Op.getNode();
803 DebugLoc dl = Node->getDebugLoc();
805 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
806 assert(getTypeAction(Node->getValueType(i)) == Legal &&
807 "Unexpected illegal type!");
809 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
810 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
811 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
812 "Unexpected illegal type!");
814 // Note that LegalizeOp may be reentered even from single-use nodes, which
815 // means that we always must cache transformed nodes.
816 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
817 if (I != LegalizedNodes.end()) return I->second;
819 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
821 bool isCustom = false;
823 // Figure out the correct action; the way to query this varies by opcode
824 TargetLowering::LegalizeAction Action = TargetLowering::Legal;
825 bool SimpleFinishLegalizing = true;
826 switch (Node->getOpcode()) {
827 case ISD::INTRINSIC_W_CHAIN:
828 case ISD::INTRINSIC_WO_CHAIN:
829 case ISD::INTRINSIC_VOID:
832 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
834 case ISD::SINT_TO_FP:
835 case ISD::UINT_TO_FP:
836 case ISD::EXTRACT_VECTOR_ELT:
837 Action = TLI.getOperationAction(Node->getOpcode(),
838 Node->getOperand(0).getValueType());
840 case ISD::FP_ROUND_INREG:
841 case ISD::SIGN_EXTEND_INREG: {
842 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
843 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
849 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
850 Node->getOpcode() == ISD::SETCC ? 2 : 1;
851 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
852 EVT OpVT = Node->getOperand(CompareOperand).getValueType();
853 ISD::CondCode CCCode =
854 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
855 Action = TLI.getCondCodeAction(CCCode, OpVT);
856 if (Action == TargetLowering::Legal) {
857 if (Node->getOpcode() == ISD::SELECT_CC)
858 Action = TLI.getOperationAction(Node->getOpcode(),
859 Node->getValueType(0));
861 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
867 // FIXME: Model these properly. LOAD and STORE are complicated, and
868 // STORE expects the unlegalized operand in some cases.
869 SimpleFinishLegalizing = false;
871 case ISD::CALLSEQ_START:
872 case ISD::CALLSEQ_END:
873 // FIXME: This shouldn't be necessary. These nodes have special properties
874 // dealing with the recursive nature of legalization. Removing this
875 // special case should be done as part of making LegalizeDAG non-recursive.
876 SimpleFinishLegalizing = false;
878 case ISD::EXTRACT_ELEMENT:
879 case ISD::FLT_ROUNDS_:
887 case ISD::MERGE_VALUES:
889 case ISD::FRAME_TO_ARGS_OFFSET:
890 case ISD::EH_SJLJ_SETJMP:
891 case ISD::EH_SJLJ_LONGJMP:
892 case ISD::EH_SJLJ_DISPATCHSETUP:
893 // These operations lie about being legal: when they claim to be legal,
894 // they should actually be expanded.
895 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
896 if (Action == TargetLowering::Legal)
897 Action = TargetLowering::Expand;
899 case ISD::TRAMPOLINE:
901 case ISD::RETURNADDR:
902 // These operations lie about being legal: when they claim to be legal,
903 // they should actually be custom-lowered.
904 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
905 if (Action == TargetLowering::Legal)
906 Action = TargetLowering::Custom;
908 case ISD::BUILD_VECTOR:
909 // A weird case: legalization for BUILD_VECTOR never legalizes the
911 // FIXME: This really sucks... changing it isn't semantically incorrect,
912 // but it massively pessimizes the code for floating-point BUILD_VECTORs
913 // because ConstantFP operands get legalized into constant pool loads
914 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
915 // though, because BUILD_VECTORS usually get lowered into other nodes
916 // which get legalized properly.
917 SimpleFinishLegalizing = false;
920 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
921 Action = TargetLowering::Legal;
923 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
928 if (SimpleFinishLegalizing) {
929 SmallVector<SDValue, 8> Ops, ResultVals;
930 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
931 Ops.push_back(LegalizeOp(Node->getOperand(i)));
932 switch (Node->getOpcode()) {
939 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
940 // Branches tweak the chain to include LastCALLSEQ
941 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
943 Ops[0] = LegalizeOp(Ops[0]);
944 setLastCALLSEQ(DAG.getEntryNode());
951 // Legalizing shifts/rotates requires adjusting the shift amount
952 // to the appropriate width.
953 if (!Ops[1].getValueType().isVector())
954 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
960 // Legalizing shifts/rotates requires adjusting the shift amount
961 // to the appropriate width.
962 if (!Ops[2].getValueType().isVector())
963 Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
968 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), Ops.data(),
971 case TargetLowering::Legal:
972 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
973 ResultVals.push_back(Result.getValue(i));
975 case TargetLowering::Custom:
976 // FIXME: The handling for custom lowering with multiple results is
978 Tmp1 = TLI.LowerOperation(Result, DAG);
979 if (Tmp1.getNode()) {
980 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
982 ResultVals.push_back(Tmp1);
984 ResultVals.push_back(Tmp1.getValue(i));
990 case TargetLowering::Expand:
991 ExpandNode(Result.getNode(), ResultVals);
993 case TargetLowering::Promote:
994 PromoteNode(Result.getNode(), ResultVals);
997 if (!ResultVals.empty()) {
998 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
999 if (ResultVals[i] != SDValue(Node, i))
1000 ResultVals[i] = LegalizeOp(ResultVals[i]);
1001 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
1003 return ResultVals[Op.getResNo()];
1007 switch (Node->getOpcode()) {
1014 assert(0 && "Do not know how to legalize this operator!");
1016 case ISD::BUILD_VECTOR:
1017 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
1018 default: assert(0 && "This action is not supported yet!");
1019 case TargetLowering::Custom:
1020 Tmp3 = TLI.LowerOperation(Result, DAG);
1021 if (Tmp3.getNode()) {
1026 case TargetLowering::Expand:
1027 Result = ExpandBUILD_VECTOR(Result.getNode());
1031 case ISD::CALLSEQ_START: {
1032 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1033 assert(CallEnd && "didn't find CALLSEQ_END!");
1035 // Recursively Legalize all of the inputs of the call end that do not lead
1036 // to this call start. This ensures that any libcalls that need be inserted
1037 // are inserted *before* the CALLSEQ_START.
1038 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1039 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1040 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1044 // Now that we have legalized all of the inputs (which may have inserted
1045 // libcalls), create the new CALLSEQ_START node.
1046 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1048 // Merge in the last call to ensure that this call starts after the last
1050 if (getLastCALLSEQ().getOpcode() != ISD::EntryToken) {
1051 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1052 Tmp1, getLastCALLSEQ());
1053 Tmp1 = LegalizeOp(Tmp1);
1056 // Do not try to legalize the target-specific arguments (#1+).
1057 if (Tmp1 != Node->getOperand(0)) {
1058 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1060 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(), &Ops[0],
1061 Ops.size()), Result.getResNo());
1064 // Remember that the CALLSEQ_START is legalized.
1065 AddLegalizedOperand(Op.getValue(0), Result);
1066 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1067 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1069 // Now that the callseq_start and all of the non-call nodes above this call
1070 // sequence have been legalized, legalize the call itself. During this
1071 // process, no libcalls can/will be inserted, guaranteeing that no calls
1073 // Note that we are selecting this call!
1074 setLastCALLSEQ(SDValue(CallEnd, 0));
1076 // Legalize the call, starting from the CALLSEQ_END.
1077 LegalizeOp(getLastCALLSEQ());
1080 case ISD::CALLSEQ_END:
1082 SDNode *myCALLSEQ_BEGIN = FindCallStartFromCallEnd(Node);
1084 // If the CALLSEQ_START node hasn't been legalized first, legalize it.
1085 // This will cause this node to be legalized as well as handling libcalls
1087 if (getLastCALLSEQ().getNode() != Node) {
1088 LegalizeOp(SDValue(myCALLSEQ_BEGIN, 0));
1089 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1090 assert(I != LegalizedNodes.end() &&
1091 "Legalizing the call start should have legalized this node!");
1095 pushLastCALLSEQ(SDValue(myCALLSEQ_BEGIN, 0));
1098 // Otherwise, the call start has been legalized and everything is going
1099 // according to plan. Just legalize ourselves normally here.
1100 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1101 // Do not try to legalize the target-specific arguments (#1+), except for
1102 // an optional flag input.
1103 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Glue){
1104 if (Tmp1 != Node->getOperand(0)) {
1105 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1107 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1108 &Ops[0], Ops.size()),
1112 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1113 if (Tmp1 != Node->getOperand(0) ||
1114 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1115 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1118 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1119 &Ops[0], Ops.size()),
1123 // This finishes up call legalization.
1126 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1127 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1128 if (Node->getNumValues() == 2)
1129 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1130 return Result.getValue(Op.getResNo());
1132 LoadSDNode *LD = cast<LoadSDNode>(Node);
1133 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1134 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1136 ISD::LoadExtType ExtType = LD->getExtensionType();
1137 if (ExtType == ISD::NON_EXTLOAD) {
1138 EVT VT = Node->getValueType(0);
1139 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1140 Tmp1, Tmp2, LD->getOffset()),
1142 Tmp3 = Result.getValue(0);
1143 Tmp4 = Result.getValue(1);
1145 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1146 default: assert(0 && "This action is not supported yet!");
1147 case TargetLowering::Legal:
1148 // If this is an unaligned load and the target doesn't support it,
1150 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1151 const Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1152 unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
1153 if (LD->getAlignment() < ABIAlignment){
1154 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1156 Tmp3 = Result.getOperand(0);
1157 Tmp4 = Result.getOperand(1);
1158 Tmp3 = LegalizeOp(Tmp3);
1159 Tmp4 = LegalizeOp(Tmp4);
1163 case TargetLowering::Custom:
1164 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1165 if (Tmp1.getNode()) {
1166 Tmp3 = LegalizeOp(Tmp1);
1167 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1170 case TargetLowering::Promote: {
1171 // Only promote a load of vector type to another.
1172 assert(VT.isVector() && "Cannot promote this load!");
1173 // Change base type to a different vector type.
1174 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1176 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
1177 LD->isVolatile(), LD->isNonTemporal(),
1178 LD->getAlignment());
1179 Tmp3 = LegalizeOp(DAG.getNode(ISD::BITCAST, dl, VT, Tmp1));
1180 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1184 // Since loads produce two values, make sure to remember that we
1185 // legalized both of them.
1186 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1187 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1188 return Op.getResNo() ? Tmp4 : Tmp3;
1191 EVT SrcVT = LD->getMemoryVT();
1192 unsigned SrcWidth = SrcVT.getSizeInBits();
1193 unsigned Alignment = LD->getAlignment();
1194 bool isVolatile = LD->isVolatile();
1195 bool isNonTemporal = LD->isNonTemporal();
1197 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1198 // Some targets pretend to have an i1 loading operation, and actually
1199 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1200 // bits are guaranteed to be zero; it helps the optimizers understand
1201 // that these bits are zero. It is also useful for EXTLOAD, since it
1202 // tells the optimizers that those bits are undefined. It would be
1203 // nice to have an effective generic way of getting these benefits...
1204 // Until such a way is found, don't insist on promoting i1 here.
1205 (SrcVT != MVT::i1 ||
1206 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1207 // Promote to a byte-sized load if not loading an integral number of
1208 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1209 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1210 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
1213 // The extra bits are guaranteed to be zero, since we stored them that
1214 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1216 ISD::LoadExtType NewExtType =
1217 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1219 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1220 Tmp1, Tmp2, LD->getPointerInfo(),
1221 NVT, isVolatile, isNonTemporal, Alignment);
1223 Ch = Result.getValue(1); // The chain.
1225 if (ExtType == ISD::SEXTLOAD)
1226 // Having the top bits zero doesn't help when sign extending.
1227 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1228 Result.getValueType(),
1229 Result, DAG.getValueType(SrcVT));
1230 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1231 // All the top bits are guaranteed to be zero - inform the optimizers.
1232 Result = DAG.getNode(ISD::AssertZext, dl,
1233 Result.getValueType(), Result,
1234 DAG.getValueType(SrcVT));
1236 Tmp1 = LegalizeOp(Result);
1237 Tmp2 = LegalizeOp(Ch);
1238 } else if (SrcWidth & (SrcWidth - 1)) {
1239 // If not loading a power-of-2 number of bits, expand as two loads.
1240 assert(!SrcVT.isVector() && "Unsupported extload!");
1241 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1242 assert(RoundWidth < SrcWidth);
1243 unsigned ExtraWidth = SrcWidth - RoundWidth;
1244 assert(ExtraWidth < RoundWidth);
1245 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1246 "Load size not an integral number of bytes!");
1247 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1248 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1250 unsigned IncrementSize;
1252 if (TLI.isLittleEndian()) {
1253 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1254 // Load the bottom RoundWidth bits.
1255 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
1257 LD->getPointerInfo(), RoundVT, isVolatile,
1258 isNonTemporal, Alignment);
1260 // Load the remaining ExtraWidth bits.
1261 IncrementSize = RoundWidth / 8;
1262 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1263 DAG.getIntPtrConstant(IncrementSize));
1264 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1265 LD->getPointerInfo().getWithOffset(IncrementSize),
1266 ExtraVT, isVolatile, isNonTemporal,
1267 MinAlign(Alignment, IncrementSize));
1269 // Build a factor node to remember that this load is independent of
1271 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1274 // Move the top bits to the right place.
1275 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1276 DAG.getConstant(RoundWidth,
1277 TLI.getShiftAmountTy(Hi.getValueType())));
1279 // Join the hi and lo parts.
1280 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1282 // Big endian - avoid unaligned loads.
1283 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1284 // Load the top RoundWidth bits.
1285 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1286 LD->getPointerInfo(), RoundVT, isVolatile,
1287 isNonTemporal, Alignment);
1289 // Load the remaining ExtraWidth bits.
1290 IncrementSize = RoundWidth / 8;
1291 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1292 DAG.getIntPtrConstant(IncrementSize));
1293 Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
1294 dl, Node->getValueType(0), Tmp1, Tmp2,
1295 LD->getPointerInfo().getWithOffset(IncrementSize),
1296 ExtraVT, isVolatile, isNonTemporal,
1297 MinAlign(Alignment, IncrementSize));
1299 // Build a factor node to remember that this load is independent of
1301 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1304 // Move the top bits to the right place.
1305 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1306 DAG.getConstant(ExtraWidth,
1307 TLI.getShiftAmountTy(Hi.getValueType())));
1309 // Join the hi and lo parts.
1310 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1313 Tmp1 = LegalizeOp(Result);
1314 Tmp2 = LegalizeOp(Ch);
1316 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1317 default: assert(0 && "This action is not supported yet!");
1318 case TargetLowering::Custom:
1321 case TargetLowering::Legal:
1322 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1323 Tmp1, Tmp2, LD->getOffset()),
1325 Tmp1 = Result.getValue(0);
1326 Tmp2 = Result.getValue(1);
1329 Tmp3 = TLI.LowerOperation(Result, DAG);
1330 if (Tmp3.getNode()) {
1331 Tmp1 = LegalizeOp(Tmp3);
1332 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1335 // If this is an unaligned load and the target doesn't support it,
1337 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
1339 LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
1340 unsigned ABIAlignment =
1341 TLI.getTargetData()->getABITypeAlignment(Ty);
1342 if (LD->getAlignment() < ABIAlignment){
1343 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
1345 Tmp1 = Result.getOperand(0);
1346 Tmp2 = Result.getOperand(1);
1347 Tmp1 = LegalizeOp(Tmp1);
1348 Tmp2 = LegalizeOp(Tmp2);
1353 case TargetLowering::Expand:
1354 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && isTypeLegal(SrcVT)) {
1355 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
1356 LD->getPointerInfo(),
1357 LD->isVolatile(), LD->isNonTemporal(),
1358 LD->getAlignment());
1362 ExtendOp = (SrcVT.isFloatingPoint() ?
1363 ISD::FP_EXTEND : ISD::ANY_EXTEND);
1365 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
1366 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
1367 default: llvm_unreachable("Unexpected extend load type!");
1369 Result = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
1370 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1371 Tmp2 = LegalizeOp(Load.getValue(1));
1375 // If this is a promoted vector load, and the vector element types are
1376 // legal, then scalarize it.
1377 if (ExtType == ISD::EXTLOAD && SrcVT.isVector() &&
1378 isTypeLegal(Node->getValueType(0).getScalarType())) {
1379 SmallVector<SDValue, 8> LoadVals;
1380 SmallVector<SDValue, 8> LoadChains;
1381 unsigned NumElem = SrcVT.getVectorNumElements();
1382 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1384 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1385 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1386 DAG.getIntPtrConstant(Stride));
1387 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1388 Node->getValueType(0).getScalarType(),
1389 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1390 SrcVT.getScalarType(),
1391 LD->isVolatile(), LD->isNonTemporal(),
1392 LD->getAlignment());
1394 LoadVals.push_back(ScalarLoad.getValue(0));
1395 LoadChains.push_back(ScalarLoad.getValue(1));
1397 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1398 &LoadChains[0], LoadChains.size());
1399 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1400 Node->getValueType(0), &LoadVals[0], LoadVals.size());
1402 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1403 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1407 // If this is a promoted vector load, and the vector element types are
1408 // illegal, create the promoted vector from bitcasted segments.
1409 if (ExtType == ISD::EXTLOAD && SrcVT.isVector()) {
1410 EVT MemElemTy = Node->getValueType(0).getScalarType();
1411 EVT SrcSclrTy = SrcVT.getScalarType();
1412 unsigned SizeRatio =
1413 (MemElemTy.getSizeInBits() / SrcSclrTy.getSizeInBits());
1415 SmallVector<SDValue, 8> LoadVals;
1416 SmallVector<SDValue, 8> LoadChains;
1417 unsigned NumElem = SrcVT.getVectorNumElements();
1418 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
1420 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1421 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1422 DAG.getIntPtrConstant(Stride));
1423 SDValue ScalarLoad = DAG.getExtLoad(ISD::EXTLOAD, dl,
1424 SrcVT.getScalarType(),
1425 Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
1426 SrcVT.getScalarType(),
1427 LD->isVolatile(), LD->isNonTemporal(),
1428 LD->getAlignment());
1429 if (TLI.isBigEndian()) {
1430 // MSB (which is garbage, comes first)
1431 LoadVals.push_back(ScalarLoad.getValue(0));
1432 for (unsigned i = 0; i<SizeRatio-1; ++i)
1433 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1435 // LSB (which is data, comes first)
1436 for (unsigned i = 0; i<SizeRatio-1; ++i)
1437 LoadVals.push_back(DAG.getUNDEF(SrcVT.getScalarType()));
1438 LoadVals.push_back(ScalarLoad.getValue(0));
1440 LoadChains.push_back(ScalarLoad.getValue(1));
1443 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1444 &LoadChains[0], LoadChains.size());
1445 EVT TempWideVector = EVT::getVectorVT(*DAG.getContext(),
1446 SrcVT.getScalarType(), NumElem*SizeRatio);
1447 SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
1448 TempWideVector, &LoadVals[0], LoadVals.size());
1450 // Cast to the correct type
1451 ValRes = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), ValRes);
1453 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1454 Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
1459 // FIXME: This does not work for vectors on most targets. Sign- and
1460 // zero-extend operations are currently folded into extending loads,
1461 // whether they are legal or not, and then we end up here without any
1462 // support for legalizing them.
1463 assert(ExtType != ISD::EXTLOAD &&
1464 "EXTLOAD should always be supported!");
1465 // Turn the unsupported load into an EXTLOAD followed by an explicit
1466 // zero/sign extend inreg.
1467 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1468 Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
1469 LD->isVolatile(), LD->isNonTemporal(),
1470 LD->getAlignment());
1472 if (ExtType == ISD::SEXTLOAD)
1473 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1474 Result.getValueType(),
1475 Result, DAG.getValueType(SrcVT));
1477 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
1478 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1479 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1484 // Since loads produce two values, make sure to remember that we legalized
1486 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1487 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1488 return Op.getResNo() ? Tmp2 : Tmp1;
1491 StoreSDNode *ST = cast<StoreSDNode>(Node);
1492 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1493 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1494 unsigned Alignment = ST->getAlignment();
1495 bool isVolatile = ST->isVolatile();
1496 bool isNonTemporal = ST->isNonTemporal();
1498 if (!ST->isTruncatingStore()) {
1499 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1500 Result = SDValue(OptStore, 0);
1505 Tmp3 = LegalizeOp(ST->getValue());
1506 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1511 EVT VT = Tmp3.getValueType();
1512 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1513 default: assert(0 && "This action is not supported yet!");
1514 case TargetLowering::Legal:
1515 // If this is an unaligned store and the target doesn't support it,
1517 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1518 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1519 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1520 if (ST->getAlignment() < ABIAlignment)
1521 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1525 case TargetLowering::Custom:
1526 Tmp1 = TLI.LowerOperation(Result, DAG);
1527 if (Tmp1.getNode()) Result = Tmp1;
1529 case TargetLowering::Promote:
1530 assert(VT.isVector() && "Unknown legal promote case!");
1531 Tmp3 = DAG.getNode(ISD::BITCAST, dl,
1532 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1533 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1534 ST->getPointerInfo(), isVolatile,
1535 isNonTemporal, Alignment);
1541 Tmp3 = LegalizeOp(ST->getValue());
1543 EVT StVT = ST->getMemoryVT();
1544 unsigned StWidth = StVT.getSizeInBits();
1546 if (StWidth != StVT.getStoreSizeInBits()) {
1547 // Promote to a byte-sized store with upper bits zero if not
1548 // storing an integral number of bytes. For example, promote
1549 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1550 EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
1551 StVT.getStoreSizeInBits());
1552 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1553 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1554 NVT, isVolatile, isNonTemporal, Alignment);
1555 } else if (StWidth & (StWidth - 1)) {
1556 // If not storing a power-of-2 number of bits, expand as two stores.
1557 assert(!StVT.isVector() && "Unsupported truncstore!");
1558 unsigned RoundWidth = 1 << Log2_32(StWidth);
1559 assert(RoundWidth < StWidth);
1560 unsigned ExtraWidth = StWidth - RoundWidth;
1561 assert(ExtraWidth < RoundWidth);
1562 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1563 "Store size not an integral number of bytes!");
1564 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
1565 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
1567 unsigned IncrementSize;
1569 if (TLI.isLittleEndian()) {
1570 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1571 // Store the bottom RoundWidth bits.
1572 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1574 isVolatile, isNonTemporal, Alignment);
1576 // Store the remaining ExtraWidth bits.
1577 IncrementSize = RoundWidth / 8;
1578 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1579 DAG.getIntPtrConstant(IncrementSize));
1580 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1581 DAG.getConstant(RoundWidth,
1582 TLI.getShiftAmountTy(Tmp3.getValueType())));
1583 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
1584 ST->getPointerInfo().getWithOffset(IncrementSize),
1585 ExtraVT, isVolatile, isNonTemporal,
1586 MinAlign(Alignment, IncrementSize));
1588 // Big endian - avoid unaligned stores.
1589 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1590 // Store the top RoundWidth bits.
1591 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1592 DAG.getConstant(ExtraWidth,
1593 TLI.getShiftAmountTy(Tmp3.getValueType())));
1594 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
1595 RoundVT, isVolatile, isNonTemporal, Alignment);
1597 // Store the remaining ExtraWidth bits.
1598 IncrementSize = RoundWidth / 8;
1599 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1600 DAG.getIntPtrConstant(IncrementSize));
1601 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
1602 ST->getPointerInfo().getWithOffset(IncrementSize),
1603 ExtraVT, isVolatile, isNonTemporal,
1604 MinAlign(Alignment, IncrementSize));
1607 // The order of the stores doesn't matter.
1608 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1610 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1611 Tmp2 != ST->getBasePtr())
1612 Result = SDValue(DAG.UpdateNodeOperands(Result.getNode(),
1617 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1618 default: assert(0 && "This action is not supported yet!");
1619 case TargetLowering::Legal:
1620 // If this is an unaligned store and the target doesn't support it,
1622 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
1623 const Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
1624 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
1625 if (ST->getAlignment() < ABIAlignment)
1626 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()),
1630 case TargetLowering::Custom:
1631 Result = TLI.LowerOperation(Result, DAG);
1635 EVT WideScalarVT = Tmp3.getValueType().getScalarType();
1636 EVT NarrowScalarVT = StVT.getScalarType();
1638 // The Store type is illegal, must scalarize the vector store.
1639 SmallVector<SDValue, 8> Stores;
1640 bool ScalarLegal = isTypeLegal(WideScalarVT);
1641 if (!isTypeLegal(StVT) && StVT.isVector() && ScalarLegal) {
1642 unsigned NumElem = StVT.getVectorNumElements();
1644 unsigned ScalarSize = StVT.getScalarType().getSizeInBits();
1645 // Round odd types to the next pow of two.
1646 if (!isPowerOf2_32(ScalarSize))
1647 ScalarSize = NextPowerOf2(ScalarSize);
1648 // Types smaller than 8 bits are promoted to 8 bits.
1649 ScalarSize = std::max<unsigned>(ScalarSize, 8);
1651 unsigned Stride = ScalarSize/8;
1652 assert(isPowerOf2_32(Stride) && "Stride must be a power of two");
1654 for (unsigned Idx=0; Idx<NumElem; Idx++) {
1655 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1656 WideScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
1659 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), ScalarSize);
1661 Ex = DAG.getNode(ISD::TRUNCATE, dl, NVT, Ex);
1662 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1663 DAG.getIntPtrConstant(Stride));
1664 SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
1665 ST->getPointerInfo().getWithOffset(Idx*Stride),
1666 isVolatile, isNonTemporal, Alignment);
1667 Stores.push_back(Store);
1669 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1670 &Stores[0], Stores.size());
1674 // The Store type is illegal, must scalarize the vector store.
1675 // However, the scalar type is illegal. Must bitcast the result
1676 // and store it in smaller parts.
1677 if (!isTypeLegal(StVT) && StVT.isVector()) {
1678 unsigned WideNumElem = StVT.getVectorNumElements();
1679 unsigned Stride = NarrowScalarVT.getSizeInBits()/8;
1681 unsigned SizeRatio =
1682 (WideScalarVT.getSizeInBits() / NarrowScalarVT.getSizeInBits());
1684 EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(), NarrowScalarVT,
1685 SizeRatio*WideNumElem);
1687 // Cast the wide elem vector to wider vec with smaller elem type.
1688 // Example <2 x i64> -> <4 x i32>
1689 Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
1691 for (unsigned Idx=0; Idx<WideNumElem*SizeRatio; Idx++) {
1693 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
1694 NarrowScalarVT, Tmp3, DAG.getIntPtrConstant(Idx));
1696 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1697 DAG.getIntPtrConstant(Stride));
1699 // Store if, this element is:
1700 // - First element on big endian, or
1701 // - Last element on little endian
1702 if (( TLI.isBigEndian() && (Idx%SizeRatio == 0)) ||
1703 ((!TLI.isBigEndian() && (Idx%SizeRatio == SizeRatio-1)))) {
1704 SDValue Store = DAG.getStore(Tmp1, dl, Ex, Tmp2,
1705 ST->getPointerInfo().getWithOffset(Idx*Stride),
1706 isVolatile, isNonTemporal, Alignment);
1707 Stores.push_back(Store);
1710 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1711 &Stores[0], Stores.size());
1716 // TRUNCSTORE:i16 i32 -> STORE i16
1717 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1718 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1719 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
1720 isVolatile, isNonTemporal, Alignment);
1728 assert(Result.getValueType() == Op.getValueType() &&
1729 "Bad legalization!");
1731 // Make sure that the generated code is itself legal.
1733 Result = LegalizeOp(Result);
1735 // Note that LegalizeOp may be reentered even from single-use nodes, which
1736 // means that we always must cache transformed nodes.
1737 AddLegalizedOperand(Op, Result);
1741 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1742 SDValue Vec = Op.getOperand(0);
1743 SDValue Idx = Op.getOperand(1);
1744 DebugLoc dl = Op.getDebugLoc();
1745 // Store the value to a temporary stack slot, then LOAD the returned part.
1746 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1747 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
1748 MachinePointerInfo(), false, false, 0);
1750 // Add the offset to the index.
1752 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1753 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1754 DAG.getConstant(EltSize, Idx.getValueType()));
1756 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1757 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1759 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1761 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1763 if (Op.getValueType().isVector())
1764 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(),
1766 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1767 MachinePointerInfo(),
1768 Vec.getValueType().getVectorElementType(),
1772 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) {
1773 assert(Op.getValueType().isVector() && "Non-vector insert subvector!");
1775 SDValue Vec = Op.getOperand(0);
1776 SDValue Part = Op.getOperand(1);
1777 SDValue Idx = Op.getOperand(2);
1778 DebugLoc dl = Op.getDebugLoc();
1780 // Store the value to a temporary stack slot, then LOAD the returned part.
1782 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1783 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
1784 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1786 // First store the whole vector.
1787 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo,
1790 // Then store the inserted part.
1792 // Add the offset to the index.
1794 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1796 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1797 DAG.getConstant(EltSize, Idx.getValueType()));
1799 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1800 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1802 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1804 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
1807 // Store the subvector.
1808 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr,
1809 MachinePointerInfo(), false, false, 0);
1811 // Finally, load the updated vector.
1812 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo,
1816 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1817 // We can't handle this case efficiently. Allocate a sufficiently
1818 // aligned object on the stack, store each element into it, then load
1819 // the result as a vector.
1820 // Create the stack frame object.
1821 EVT VT = Node->getValueType(0);
1822 EVT EltVT = VT.getVectorElementType();
1823 DebugLoc dl = Node->getDebugLoc();
1824 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1825 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1826 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI);
1828 // Emit a store of each element to the stack slot.
1829 SmallVector<SDValue, 8> Stores;
1830 unsigned TypeByteSize = EltVT.getSizeInBits() / 8;
1831 // Store (in the right endianness) the elements to memory.
1832 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1833 // Ignore undef elements.
1834 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1836 unsigned Offset = TypeByteSize*i;
1838 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1839 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1841 // If the destination vector element type is narrower than the source
1842 // element type, only store the bits necessary.
1843 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) {
1844 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
1845 Node->getOperand(i), Idx,
1846 PtrInfo.getWithOffset(Offset),
1847 EltVT, false, false, 0));
1849 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
1850 Node->getOperand(i), Idx,
1851 PtrInfo.getWithOffset(Offset),
1856 if (!Stores.empty()) // Not all undef elements?
1857 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1858 &Stores[0], Stores.size());
1860 StoreChain = DAG.getEntryNode();
1862 // Result is a load from the stack slot.
1863 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, false, false, 0);
1866 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1867 DebugLoc dl = Node->getDebugLoc();
1868 SDValue Tmp1 = Node->getOperand(0);
1869 SDValue Tmp2 = Node->getOperand(1);
1871 // Get the sign bit of the RHS. First obtain a value that has the same
1872 // sign as the sign bit, i.e. negative if and only if the sign bit is 1.
1874 EVT FloatVT = Tmp2.getValueType();
1875 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits());
1876 if (isTypeLegal(IVT)) {
1877 // Convert to an integer with the same sign bit.
1878 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2);
1880 // Store the float to memory, then load the sign part out as an integer.
1881 MVT LoadTy = TLI.getPointerTy();
1882 // First create a temporary that is aligned for both the load and store.
1883 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy);
1884 // Then store the float to it.
1886 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(),
1888 if (TLI.isBigEndian()) {
1889 assert(FloatVT.isByteSized() && "Unsupported floating point type!");
1890 // Load out a legal integer with the same sign bit as the float.
1891 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(),
1893 } else { // Little endian
1894 SDValue LoadPtr = StackPtr;
1895 // The float may be wider than the integer we are going to load. Advance
1896 // the pointer so that the loaded integer will contain the sign bit.
1897 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits();
1898 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8;
1899 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(),
1900 LoadPtr, DAG.getIntPtrConstant(ByteOffset));
1901 // Load a legal integer containing the sign bit.
1902 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(),
1904 // Move the sign bit to the top bit of the loaded integer.
1905 unsigned BitShift = LoadTy.getSizeInBits() -
1906 (FloatVT.getSizeInBits() - 8 * ByteOffset);
1907 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?");
1909 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit,
1910 DAG.getConstant(BitShift,
1911 TLI.getShiftAmountTy(SignBit.getValueType())));
1914 // Now get the sign bit proper, by seeing whether the value is negative.
1915 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1916 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1918 // Get the absolute value of the result.
1919 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1920 // Select between the nabs and abs value based on the sign bit of
1922 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1923 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1927 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1928 SmallVectorImpl<SDValue> &Results) {
1929 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1930 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1931 " not tell us which reg is the stack pointer!");
1932 DebugLoc dl = Node->getDebugLoc();
1933 EVT VT = Node->getValueType(0);
1934 SDValue Tmp1 = SDValue(Node, 0);
1935 SDValue Tmp2 = SDValue(Node, 1);
1936 SDValue Tmp3 = Node->getOperand(2);
1937 SDValue Chain = Tmp1.getOperand(0);
1939 // Chain the dynamic stack allocation so that it doesn't modify the stack
1940 // pointer when other instructions are using the stack.
1941 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1943 SDValue Size = Tmp2.getOperand(1);
1944 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1945 Chain = SP.getValue(1);
1946 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1947 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
1948 if (Align > StackAlign)
1949 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1950 DAG.getConstant(-(uint64_t)Align, VT));
1951 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1952 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1954 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1955 DAG.getIntPtrConstant(0, true), SDValue());
1957 Results.push_back(Tmp1);
1958 Results.push_back(Tmp2);
1961 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1962 /// condition code CC on the current target. This routine expands SETCC with
1963 /// illegal condition code into AND / OR of multiple SETCC values.
1964 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1965 SDValue &LHS, SDValue &RHS,
1968 EVT OpVT = LHS.getValueType();
1969 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1970 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1971 default: assert(0 && "Unknown condition code action!");
1972 case TargetLowering::Legal:
1975 case TargetLowering::Expand: {
1976 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1979 default: assert(0 && "Don't know how to expand this condition!");
1980 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1981 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1982 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1983 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1984 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1985 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1986 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1987 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1988 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1989 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1990 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1991 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1992 // FIXME: Implement more expansions.
1995 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1996 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1997 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
2005 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
2006 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
2007 /// a load from the stack slot to DestVT, extending it if needed.
2008 /// The resultant code need not be legal.
2009 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
2013 // Create the stack frame object.
2015 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
2016 getTypeForEVT(*DAG.getContext()));
2017 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
2019 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
2020 int SPFI = StackPtrFI->getIndex();
2021 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI);
2023 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
2024 unsigned SlotSize = SlotVT.getSizeInBits();
2025 unsigned DestSize = DestVT.getSizeInBits();
2026 const Type *DestType = DestVT.getTypeForEVT(*DAG.getContext());
2027 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType);
2029 // Emit a store to the stack slot. Use a truncstore if the input value is
2030 // later than DestVT.
2033 if (SrcSize > SlotSize)
2034 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2035 PtrInfo, SlotVT, false, false, SrcAlign);
2037 assert(SrcSize == SlotSize && "Invalid store");
2038 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
2039 PtrInfo, false, false, SrcAlign);
2042 // Result is a load from the stack slot.
2043 if (SlotSize == DestSize)
2044 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo,
2045 false, false, DestAlign);
2047 assert(SlotSize < DestSize && "Unknown extension!");
2048 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr,
2049 PtrInfo, SlotVT, false, false, DestAlign);
2052 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
2053 DebugLoc dl = Node->getDebugLoc();
2054 // Create a vector sized/aligned stack slot, store the value to element #0,
2055 // then load the whole vector back out.
2056 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
2058 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
2059 int SPFI = StackPtrFI->getIndex();
2061 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
2063 MachinePointerInfo::getFixedStack(SPFI),
2064 Node->getValueType(0).getVectorElementType(),
2066 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
2067 MachinePointerInfo::getFixedStack(SPFI),
2072 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
2073 /// support the operation, but do support the resultant vector type.
2074 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
2075 unsigned NumElems = Node->getNumOperands();
2076 SDValue Value1, Value2;
2077 DebugLoc dl = Node->getDebugLoc();
2078 EVT VT = Node->getValueType(0);
2079 EVT OpVT = Node->getOperand(0).getValueType();
2080 EVT EltVT = VT.getVectorElementType();
2082 // If the only non-undef value is the low element, turn this into a
2083 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
2084 bool isOnlyLowElement = true;
2085 bool MoreThanTwoValues = false;
2086 bool isConstant = true;
2087 for (unsigned i = 0; i < NumElems; ++i) {
2088 SDValue V = Node->getOperand(i);
2089 if (V.getOpcode() == ISD::UNDEF)
2092 isOnlyLowElement = false;
2093 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
2096 if (!Value1.getNode()) {
2098 } else if (!Value2.getNode()) {
2101 } else if (V != Value1 && V != Value2) {
2102 MoreThanTwoValues = true;
2106 if (!Value1.getNode())
2107 return DAG.getUNDEF(VT);
2109 if (isOnlyLowElement)
2110 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
2112 // If all elements are constants, create a load from the constant pool.
2114 std::vector<Constant*> CV;
2115 for (unsigned i = 0, e = NumElems; i != e; ++i) {
2116 if (ConstantFPSDNode *V =
2117 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
2118 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
2119 } else if (ConstantSDNode *V =
2120 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
2122 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
2124 // If OpVT and EltVT don't match, EltVT is not legal and the
2125 // element values have been promoted/truncated earlier. Undo this;
2126 // we don't want a v16i8 to become a v16i32 for example.
2127 const ConstantInt *CI = V->getConstantIntValue();
2128 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()),
2129 CI->getZExtValue()));
2132 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
2133 const Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext());
2134 CV.push_back(UndefValue::get(OpNTy));
2137 Constant *CP = ConstantVector::get(CV);
2138 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
2139 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2140 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
2141 MachinePointerInfo::getConstantPool(),
2142 false, false, Alignment);
2145 if (!MoreThanTwoValues) {
2146 SmallVector<int, 8> ShuffleVec(NumElems, -1);
2147 for (unsigned i = 0; i < NumElems; ++i) {
2148 SDValue V = Node->getOperand(i);
2149 if (V.getOpcode() == ISD::UNDEF)
2151 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
2153 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
2154 // Get the splatted value into the low element of a vector register.
2155 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
2157 if (Value2.getNode())
2158 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
2160 Vec2 = DAG.getUNDEF(VT);
2162 // Return shuffle(LowValVec, undef, <0,0,0,0>)
2163 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2167 // Otherwise, we can't handle this case efficiently.
2168 return ExpandVectorBuildThroughStack(Node);
2171 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2172 // does not fit into a register, return the lo part and set the hi part to the
2173 // by-reg argument. If it does fit into a single register, return the result
2174 // and leave the Hi part unset.
2175 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2177 // The input chain to this libcall is the entry node of the function.
2178 // Legalizing the call will automatically add the previous call to the
2180 SDValue InChain = DAG.getEntryNode();
2182 TargetLowering::ArgListTy Args;
2183 TargetLowering::ArgListEntry Entry;
2184 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2185 EVT ArgVT = Node->getOperand(i).getValueType();
2186 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2187 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2188 Entry.isSExt = isSigned;
2189 Entry.isZExt = !isSigned;
2190 Args.push_back(Entry);
2192 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2193 TLI.getPointerTy());
2195 // Splice the libcall in wherever FindInputOutputChains tells us to.
2196 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2198 // isTailCall may be true since the callee does not reference caller stack
2199 // frame. Check if it's in the right position.
2200 bool isTailCall = isInTailCallPosition(DAG, Node, TLI);
2201 std::pair<SDValue, SDValue> CallInfo =
2202 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2203 0, TLI.getLibcallCallingConv(LC), isTailCall,
2204 /*isReturnValueUsed=*/true,
2205 Callee, Args, DAG, Node->getDebugLoc());
2207 if (!CallInfo.second.getNode())
2208 // It's a tailcall, return the chain (which is the DAG root).
2209 return DAG.getRoot();
2211 // Legalize the call sequence, starting with the chain. This will advance
2212 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2213 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2214 LegalizeOp(CallInfo.second);
2215 return CallInfo.first;
2218 /// ExpandLibCall - Generate a libcall taking the given operands as arguments
2219 /// and returning a result of type RetVT.
2220 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
2221 const SDValue *Ops, unsigned NumOps,
2222 bool isSigned, DebugLoc dl) {
2223 TargetLowering::ArgListTy Args;
2224 Args.reserve(NumOps);
2226 TargetLowering::ArgListEntry Entry;
2227 for (unsigned i = 0; i != NumOps; ++i) {
2228 Entry.Node = Ops[i];
2229 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
2230 Entry.isSExt = isSigned;
2231 Entry.isZExt = !isSigned;
2232 Args.push_back(Entry);
2234 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2235 TLI.getPointerTy());
2237 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2238 std::pair<SDValue,SDValue> CallInfo =
2239 TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
2240 false, 0, TLI.getLibcallCallingConv(LC), false,
2241 /*isReturnValueUsed=*/true,
2242 Callee, Args, DAG, dl);
2244 // Legalize the call sequence, starting with the chain. This will advance
2245 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2246 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2247 LegalizeOp(CallInfo.second);
2249 return CallInfo.first;
2252 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to
2253 // ExpandLibCall except that the first operand is the in-chain.
2254 std::pair<SDValue, SDValue>
2255 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
2258 SDValue InChain = Node->getOperand(0);
2260 TargetLowering::ArgListTy Args;
2261 TargetLowering::ArgListEntry Entry;
2262 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) {
2263 EVT ArgVT = Node->getOperand(i).getValueType();
2264 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2265 Entry.Node = Node->getOperand(i);
2267 Entry.isSExt = isSigned;
2268 Entry.isZExt = !isSigned;
2269 Args.push_back(Entry);
2271 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2272 TLI.getPointerTy());
2274 // Splice the libcall in wherever FindInputOutputChains tells us to.
2275 const Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext());
2276 std::pair<SDValue, SDValue> CallInfo =
2277 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2278 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2279 /*isReturnValueUsed=*/true,
2280 Callee, Args, DAG, Node->getDebugLoc());
2282 // Legalize the call sequence, starting with the chain. This will advance
2283 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2284 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2285 LegalizeOp(CallInfo.second);
2289 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2290 RTLIB::Libcall Call_F32,
2291 RTLIB::Libcall Call_F64,
2292 RTLIB::Libcall Call_F80,
2293 RTLIB::Libcall Call_PPCF128) {
2295 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2296 default: assert(0 && "Unexpected request for libcall!");
2297 case MVT::f32: LC = Call_F32; break;
2298 case MVT::f64: LC = Call_F64; break;
2299 case MVT::f80: LC = Call_F80; break;
2300 case MVT::ppcf128: LC = Call_PPCF128; break;
2302 return ExpandLibCall(LC, Node, false);
2305 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2306 RTLIB::Libcall Call_I8,
2307 RTLIB::Libcall Call_I16,
2308 RTLIB::Libcall Call_I32,
2309 RTLIB::Libcall Call_I64,
2310 RTLIB::Libcall Call_I128) {
2312 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2313 default: assert(0 && "Unexpected request for libcall!");
2314 case MVT::i8: LC = Call_I8; break;
2315 case MVT::i16: LC = Call_I16; break;
2316 case MVT::i32: LC = Call_I32; break;
2317 case MVT::i64: LC = Call_I64; break;
2318 case MVT::i128: LC = Call_I128; break;
2320 return ExpandLibCall(LC, Node, isSigned);
2323 /// isDivRemLibcallAvailable - Return true if divmod libcall is available.
2324 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned,
2325 const TargetLowering &TLI) {
2327 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2328 default: assert(0 && "Unexpected request for libcall!");
2329 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2330 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2331 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2332 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2333 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2336 return TLI.getLibcallName(LC) != 0;
2339 /// UseDivRem - Only issue divrem libcall if both quotient and remainder are
2341 static bool UseDivRem(SDNode *Node, bool isSigned, bool isDIV) {
2342 unsigned OtherOpcode = 0;
2344 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV;
2346 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV;
2348 SDValue Op0 = Node->getOperand(0);
2349 SDValue Op1 = Node->getOperand(1);
2350 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(),
2351 UE = Op0.getNode()->use_end(); UI != UE; ++UI) {
2355 if (User->getOpcode() == OtherOpcode &&
2356 User->getOperand(0) == Op0 &&
2357 User->getOperand(1) == Op1)
2363 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem
2366 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
2367 SmallVectorImpl<SDValue> &Results) {
2368 unsigned Opcode = Node->getOpcode();
2369 bool isSigned = Opcode == ISD::SDIVREM;
2372 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
2373 default: assert(0 && "Unexpected request for libcall!");
2374 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
2375 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
2376 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
2377 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
2378 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break;
2381 // The input chain to this libcall is the entry node of the function.
2382 // Legalizing the call will automatically add the previous call to the
2384 SDValue InChain = DAG.getEntryNode();
2386 EVT RetVT = Node->getValueType(0);
2387 const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
2389 TargetLowering::ArgListTy Args;
2390 TargetLowering::ArgListEntry Entry;
2391 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2392 EVT ArgVT = Node->getOperand(i).getValueType();
2393 const Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
2394 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2395 Entry.isSExt = isSigned;
2396 Entry.isZExt = !isSigned;
2397 Args.push_back(Entry);
2400 // Also pass the return address of the remainder.
2401 SDValue FIPtr = DAG.CreateStackTemporary(RetVT);
2403 Entry.Ty = RetTy->getPointerTo();
2404 Entry.isSExt = isSigned;
2405 Entry.isZExt = !isSigned;
2406 Args.push_back(Entry);
2408 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2409 TLI.getPointerTy());
2411 // Splice the libcall in wherever FindInputOutputChains tells us to.
2412 DebugLoc dl = Node->getDebugLoc();
2413 std::pair<SDValue, SDValue> CallInfo =
2414 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2415 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
2416 /*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
2418 // Legalize the call sequence, starting with the chain. This will advance
2419 // the LastCALLSEQ to the legalized version of the CALLSEQ_END node that
2420 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2421 LegalizeOp(CallInfo.second);
2423 // Remainder is loaded back from the stack frame.
2424 SDValue Rem = DAG.getLoad(RetVT, dl, getLastCALLSEQ(), FIPtr,
2425 MachinePointerInfo(), false, false, 0);
2426 Results.push_back(CallInfo.first);
2427 Results.push_back(Rem);
2430 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2431 /// INT_TO_FP operation of the specified operand when the target requests that
2432 /// we expand it. At this point, we know that the result and operand types are
2433 /// legal for the target.
2434 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2438 if (Op0.getValueType() == MVT::i32) {
2439 // simple 32-bit [signed|unsigned] integer to float/double expansion
2441 // Get the stack frame index of a 8 byte buffer.
2442 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2444 // word offset constant for Hi/Lo address computation
2445 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2446 // set up Hi and Lo (into buffer) address based on endian
2447 SDValue Hi = StackSlot;
2448 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2449 TLI.getPointerTy(), StackSlot, WordOff);
2450 if (TLI.isLittleEndian())
2453 // if signed map to unsigned space
2456 // constant used to invert sign bit (signed to unsigned mapping)
2457 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2458 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2462 // store the lo of the constructed double - based on integer input
2463 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2464 Op0Mapped, Lo, MachinePointerInfo(),
2466 // initial hi portion of constructed double
2467 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2468 // store the hi of the constructed double - biased exponent
2469 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi,
2470 MachinePointerInfo(),
2472 // load the constructed double
2473 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot,
2474 MachinePointerInfo(), false, false, 0);
2475 // FP constant to bias correct the final result
2476 SDValue Bias = DAG.getConstantFP(isSigned ?
2477 BitsToDouble(0x4330000080000000ULL) :
2478 BitsToDouble(0x4330000000000000ULL),
2480 // subtract the bias
2481 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2484 // handle final rounding
2485 if (DestVT == MVT::f64) {
2488 } else if (DestVT.bitsLT(MVT::f64)) {
2489 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2490 DAG.getIntPtrConstant(0));
2491 } else if (DestVT.bitsGT(MVT::f64)) {
2492 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2496 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2497 // Code below here assumes !isSigned without checking again.
2499 // Implementation of unsigned i64 to f64 following the algorithm in
2500 // __floatundidf in compiler_rt. This implementation has the advantage
2501 // of performing rounding correctly, both in the default rounding mode
2502 // and in all alternate rounding modes.
2503 // TODO: Generalize this for use with other types.
2504 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
2506 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64);
2507 SDValue TwoP84PlusTwoP52 =
2508 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64);
2510 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64);
2512 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32);
2513 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0,
2514 DAG.getConstant(32, MVT::i64));
2515 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52);
2516 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84);
2517 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr);
2518 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr);
2519 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt,
2521 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub);
2524 // Implementation of unsigned i64 to f32.
2525 // TODO: Generalize this for use with other types.
2526 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
2527 // For unsigned conversions, convert them to signed conversions using the
2528 // algorithm from the x86_64 __floatundidf in compiler_rt.
2530 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
2532 SDValue ShiftConst =
2533 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType()));
2534 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
2535 SDValue AndConst = DAG.getConstant(1, MVT::i64);
2536 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
2537 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr);
2539 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or);
2540 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt);
2542 // TODO: This really should be implemented using a branch rather than a
2543 // select. We happen to get lucky and machinesink does the right
2544 // thing most of the time. This would be a good candidate for a
2545 //pseudo-op, or, even better, for whole-function isel.
2546 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2547 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT);
2548 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast);
2551 // Otherwise, implement the fully general conversion.
2553 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2554 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64));
2555 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And,
2556 DAG.getConstant(UINT64_C(0x800), MVT::i64));
2557 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0,
2558 DAG.getConstant(UINT64_C(0x7ff), MVT::i64));
2559 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2560 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE);
2561 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0);
2562 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64),
2563 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64),
2565 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0);
2566 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType());
2568 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2,
2569 DAG.getConstant(32, SHVT));
2570 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh);
2571 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc);
2573 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64);
2574 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt);
2575 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2);
2576 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo);
2577 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2);
2578 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd,
2579 DAG.getIntPtrConstant(0));
2582 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2584 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2585 Op0, DAG.getConstant(0, Op0.getValueType()),
2587 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2588 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2589 SignSet, Four, Zero);
2591 // If the sign bit of the integer is set, the large number will be treated
2592 // as a negative number. To counteract this, the dynamic code adds an
2593 // offset depending on the data type.
2595 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
2596 default: assert(0 && "Unsupported integer type!");
2597 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2598 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2599 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2600 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2602 if (TLI.isLittleEndian()) FF <<= 32;
2603 Constant *FudgeFactor = ConstantInt::get(
2604 Type::getInt64Ty(*DAG.getContext()), FF);
2606 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2607 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2608 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2609 Alignment = std::min(Alignment, 4u);
2611 if (DestVT == MVT::f32)
2612 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2613 MachinePointerInfo::getConstantPool(),
2614 false, false, Alignment);
2617 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2618 DAG.getEntryNode(), CPIdx,
2619 MachinePointerInfo::getConstantPool(),
2620 MVT::f32, false, false, Alignment));
2623 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2626 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2627 /// *INT_TO_FP operation of the specified operand when the target requests that
2628 /// we promote it. At this point, we know that the result and operand types are
2629 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2630 /// operation that takes a larger input.
2631 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2635 // First step, figure out the appropriate *INT_TO_FP operation to use.
2636 EVT NewInTy = LegalOp.getValueType();
2638 unsigned OpToUse = 0;
2640 // Scan for the appropriate larger type to use.
2642 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
2643 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2645 // If the target supports SINT_TO_FP of this type, use it.
2646 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2647 OpToUse = ISD::SINT_TO_FP;
2650 if (isSigned) continue;
2652 // If the target supports UINT_TO_FP of this type, use it.
2653 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2654 OpToUse = ISD::UINT_TO_FP;
2658 // Otherwise, try a larger type.
2661 // Okay, we found the operation and type to use. Zero extend our input to the
2662 // desired type then run the operation on it.
2663 return DAG.getNode(OpToUse, dl, DestVT,
2664 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2665 dl, NewInTy, LegalOp));
2668 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2669 /// FP_TO_*INT operation of the specified operand when the target requests that
2670 /// we promote it. At this point, we know that the result and operand types are
2671 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2672 /// operation that returns a larger result.
2673 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2677 // First step, figure out the appropriate FP_TO*INT operation to use.
2678 EVT NewOutTy = DestVT;
2680 unsigned OpToUse = 0;
2682 // Scan for the appropriate larger type to use.
2684 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
2685 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2687 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2688 OpToUse = ISD::FP_TO_SINT;
2692 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2693 OpToUse = ISD::FP_TO_UINT;
2697 // Otherwise, try a larger type.
2701 // Okay, we found the operation and type to use.
2702 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2704 // Truncate the result of the extended FP_TO_*INT operation to the desired
2706 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2709 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2711 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2712 EVT VT = Op.getValueType();
2713 EVT SHVT = TLI.getShiftAmountTy(VT);
2714 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2715 switch (VT.getSimpleVT().SimpleTy) {
2716 default: assert(0 && "Unhandled Expand type in BSWAP!");
2718 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2719 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2720 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2722 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2723 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2724 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2725 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2726 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2727 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2728 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2729 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2730 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2732 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2733 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2734 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2735 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2736 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2737 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2738 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2739 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2740 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2741 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2742 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2743 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2744 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2745 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2746 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2747 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2748 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2749 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2750 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2751 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2752 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2756 /// SplatByte - Distribute ByteVal over NumBits bits.
2757 // FIXME: Move this helper to a common place.
2758 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) {
2759 APInt Val = APInt(NumBits, ByteVal);
2761 for (unsigned i = NumBits; i > 8; i >>= 1) {
2762 Val = (Val << Shift) | Val;
2768 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2770 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2773 default: assert(0 && "Cannot expand this yet!");
2775 EVT VT = Op.getValueType();
2776 EVT ShVT = TLI.getShiftAmountTy(VT);
2777 unsigned Len = VT.getSizeInBits();
2779 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2780 "CTPOP not implemented for this type.");
2782 // This is the "best" algorithm from
2783 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel
2785 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT);
2786 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT);
2787 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT);
2788 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT);
2790 // v = v - ((v >> 1) & 0x55555555...)
2791 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2792 DAG.getNode(ISD::AND, dl, VT,
2793 DAG.getNode(ISD::SRL, dl, VT, Op,
2794 DAG.getConstant(1, ShVT)),
2796 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)
2797 Op = DAG.getNode(ISD::ADD, dl, VT,
2798 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2799 DAG.getNode(ISD::AND, dl, VT,
2800 DAG.getNode(ISD::SRL, dl, VT, Op,
2801 DAG.getConstant(2, ShVT)),
2803 // v = (v + (v >> 4)) & 0x0F0F0F0F...
2804 Op = DAG.getNode(ISD::AND, dl, VT,
2805 DAG.getNode(ISD::ADD, dl, VT, Op,
2806 DAG.getNode(ISD::SRL, dl, VT, Op,
2807 DAG.getConstant(4, ShVT))),
2809 // v = (v * 0x01010101...) >> (Len - 8)
2810 Op = DAG.getNode(ISD::SRL, dl, VT,
2811 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2812 DAG.getConstant(Len - 8, ShVT));
2817 // for now, we do this:
2818 // x = x | (x >> 1);
2819 // x = x | (x >> 2);
2821 // x = x | (x >>16);
2822 // x = x | (x >>32); // for 64-bit input
2823 // return popcount(~x);
2825 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2826 EVT VT = Op.getValueType();
2827 EVT ShVT = TLI.getShiftAmountTy(VT);
2828 unsigned len = VT.getSizeInBits();
2829 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2830 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2831 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2832 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2834 Op = DAG.getNOT(dl, Op, VT);
2835 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2838 // for now, we use: { return popcount(~x & (x - 1)); }
2839 // unless the target has ctlz but not ctpop, in which case we use:
2840 // { return 32 - nlz(~x & (x-1)); }
2841 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2842 EVT VT = Op.getValueType();
2843 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2844 DAG.getNOT(dl, Op, VT),
2845 DAG.getNode(ISD::SUB, dl, VT, Op,
2846 DAG.getConstant(1, VT)));
2847 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2848 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2849 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2850 return DAG.getNode(ISD::SUB, dl, VT,
2851 DAG.getConstant(VT.getSizeInBits(), VT),
2852 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2853 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2858 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) {
2859 unsigned Opc = Node->getOpcode();
2860 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2865 llvm_unreachable("Unhandled atomic intrinsic Expand!");
2867 case ISD::ATOMIC_SWAP:
2868 switch (VT.SimpleTy) {
2869 default: llvm_unreachable("Unexpected value type for atomic!");
2870 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break;
2871 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break;
2872 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break;
2873 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break;
2876 case ISD::ATOMIC_CMP_SWAP:
2877 switch (VT.SimpleTy) {
2878 default: llvm_unreachable("Unexpected value type for atomic!");
2879 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break;
2880 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break;
2881 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break;
2882 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break;
2885 case ISD::ATOMIC_LOAD_ADD:
2886 switch (VT.SimpleTy) {
2887 default: llvm_unreachable("Unexpected value type for atomic!");
2888 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break;
2889 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break;
2890 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break;
2891 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break;
2894 case ISD::ATOMIC_LOAD_SUB:
2895 switch (VT.SimpleTy) {
2896 default: llvm_unreachable("Unexpected value type for atomic!");
2897 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break;
2898 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break;
2899 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break;
2900 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break;
2903 case ISD::ATOMIC_LOAD_AND:
2904 switch (VT.SimpleTy) {
2905 default: llvm_unreachable("Unexpected value type for atomic!");
2906 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break;
2907 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break;
2908 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break;
2909 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break;
2912 case ISD::ATOMIC_LOAD_OR:
2913 switch (VT.SimpleTy) {
2914 default: llvm_unreachable("Unexpected value type for atomic!");
2915 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break;
2916 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break;
2917 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break;
2918 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break;
2921 case ISD::ATOMIC_LOAD_XOR:
2922 switch (VT.SimpleTy) {
2923 default: llvm_unreachable("Unexpected value type for atomic!");
2924 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break;
2925 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break;
2926 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break;
2927 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break;
2930 case ISD::ATOMIC_LOAD_NAND:
2931 switch (VT.SimpleTy) {
2932 default: llvm_unreachable("Unexpected value type for atomic!");
2933 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break;
2934 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break;
2935 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break;
2936 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break;
2941 return ExpandChainLibCall(LC, Node, false);
2944 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2945 SmallVectorImpl<SDValue> &Results) {
2946 DebugLoc dl = Node->getDebugLoc();
2947 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2948 switch (Node->getOpcode()) {
2952 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2953 Results.push_back(Tmp1);
2956 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2958 case ISD::FRAMEADDR:
2959 case ISD::RETURNADDR:
2960 case ISD::FRAME_TO_ARGS_OFFSET:
2961 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2963 case ISD::FLT_ROUNDS_:
2964 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2966 case ISD::EH_RETURN:
2970 case ISD::EH_SJLJ_LONGJMP:
2971 case ISD::EH_SJLJ_DISPATCHSETUP:
2972 // If the target didn't expand these, there's nothing to do, so just
2973 // preserve the chain and be done.
2974 Results.push_back(Node->getOperand(0));
2976 case ISD::EH_SJLJ_SETJMP:
2977 // If the target didn't expand this, just return 'zero' and preserve the
2979 Results.push_back(DAG.getConstant(0, MVT::i32));
2980 Results.push_back(Node->getOperand(0));
2982 case ISD::MEMBARRIER: {
2983 // If the target didn't lower this, lower it to '__sync_synchronize()' call
2984 TargetLowering::ArgListTy Args;
2985 std::pair<SDValue, SDValue> CallResult =
2986 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
2987 false, false, false, false, 0, CallingConv::C,
2988 /*isTailCall=*/false,
2989 /*isReturnValueUsed=*/true,
2990 DAG.getExternalSymbol("__sync_synchronize",
2991 TLI.getPointerTy()),
2993 Results.push_back(CallResult.second);
2996 // By default, atomic intrinsics are marked Legal and lowered. Targets
2997 // which don't support them directly, however, may want libcalls, in which
2998 // case they mark them Expand, and we get here.
2999 case ISD::ATOMIC_SWAP:
3000 case ISD::ATOMIC_LOAD_ADD:
3001 case ISD::ATOMIC_LOAD_SUB:
3002 case ISD::ATOMIC_LOAD_AND:
3003 case ISD::ATOMIC_LOAD_OR:
3004 case ISD::ATOMIC_LOAD_XOR:
3005 case ISD::ATOMIC_LOAD_NAND:
3006 case ISD::ATOMIC_LOAD_MIN:
3007 case ISD::ATOMIC_LOAD_MAX:
3008 case ISD::ATOMIC_LOAD_UMIN:
3009 case ISD::ATOMIC_LOAD_UMAX:
3010 case ISD::ATOMIC_CMP_SWAP: {
3011 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node);
3012 Results.push_back(Tmp.first);
3013 Results.push_back(Tmp.second);
3016 case ISD::DYNAMIC_STACKALLOC:
3017 ExpandDYNAMIC_STACKALLOC(Node, Results);
3019 case ISD::MERGE_VALUES:
3020 for (unsigned i = 0; i < Node->getNumValues(); i++)
3021 Results.push_back(Node->getOperand(i));
3024 EVT VT = Node->getValueType(0);
3026 Results.push_back(DAG.getConstant(0, VT));
3028 assert(VT.isFloatingPoint() && "Unknown value type!");
3029 Results.push_back(DAG.getConstantFP(0, VT));
3034 // If this operation is not supported, lower it to 'abort()' call
3035 TargetLowering::ArgListTy Args;
3036 std::pair<SDValue, SDValue> CallResult =
3037 TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
3038 false, false, false, false, 0, CallingConv::C,
3039 /*isTailCall=*/false,
3040 /*isReturnValueUsed=*/true,
3041 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
3043 Results.push_back(CallResult.second);
3048 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
3049 Node->getValueType(0), dl);
3050 Results.push_back(Tmp1);
3052 case ISD::FP_EXTEND:
3053 Tmp1 = EmitStackConvert(Node->getOperand(0),
3054 Node->getOperand(0).getValueType(),
3055 Node->getValueType(0), dl);
3056 Results.push_back(Tmp1);
3058 case ISD::SIGN_EXTEND_INREG: {
3059 // NOTE: we could fall back on load/store here too for targets without
3060 // SAR. However, it is doubtful that any exist.
3061 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3062 EVT VT = Node->getValueType(0);
3063 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
3066 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
3067 ExtraVT.getScalarType().getSizeInBits();
3068 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy);
3069 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
3070 Node->getOperand(0), ShiftCst);
3071 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
3072 Results.push_back(Tmp1);
3075 case ISD::FP_ROUND_INREG: {
3076 // The only way we can lower this is to turn it into a TRUNCSTORE,
3077 // EXTLOAD pair, targeting a temporary location (a stack slot).
3079 // NOTE: there is a choice here between constantly creating new stack
3080 // slots and always reusing the same one. We currently always create
3081 // new ones, as reuse may inhibit scheduling.
3082 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3083 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
3084 Node->getValueType(0), dl);
3085 Results.push_back(Tmp1);
3088 case ISD::SINT_TO_FP:
3089 case ISD::UINT_TO_FP:
3090 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
3091 Node->getOperand(0), Node->getValueType(0), dl);
3092 Results.push_back(Tmp1);
3094 case ISD::FP_TO_UINT: {
3095 SDValue True, False;
3096 EVT VT = Node->getOperand(0).getValueType();
3097 EVT NVT = Node->getValueType(0);
3098 APFloat apf(APInt::getNullValue(VT.getSizeInBits()));
3099 APInt x = APInt::getSignBit(NVT.getSizeInBits());
3100 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
3101 Tmp1 = DAG.getConstantFP(apf, VT);
3102 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
3103 Node->getOperand(0),
3105 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
3106 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
3107 DAG.getNode(ISD::FSUB, dl, VT,
3108 Node->getOperand(0), Tmp1));
3109 False = DAG.getNode(ISD::XOR, dl, NVT, False,
3110 DAG.getConstant(x, NVT));
3111 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
3112 Results.push_back(Tmp1);
3116 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
3117 EVT VT = Node->getValueType(0);
3118 Tmp1 = Node->getOperand(0);
3119 Tmp2 = Node->getOperand(1);
3120 unsigned Align = Node->getConstantOperandVal(3);
3122 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2,
3123 MachinePointerInfo(V), false, false, 0);
3124 SDValue VAList = VAListLoad;
3126 if (Align > TLI.getMinStackArgumentAlignment()) {
3127 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2");
3129 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3130 DAG.getConstant(Align - 1,
3131 TLI.getPointerTy()));
3133 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList,
3134 DAG.getConstant(-(int64_t)Align,
3135 TLI.getPointerTy()));
3138 // Increment the pointer, VAList, to the next vaarg
3139 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
3140 DAG.getConstant(TLI.getTargetData()->
3141 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
3142 TLI.getPointerTy()));
3143 // Store the incremented VAList to the legalized pointer
3144 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2,
3145 MachinePointerInfo(V), false, false, 0);
3146 // Load the actual argument out of the pointer VAList
3147 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3149 Results.push_back(Results[0].getValue(1));
3153 // This defaults to loading a pointer from the input and storing it to the
3154 // output, returning the chain.
3155 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
3156 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
3157 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
3158 Node->getOperand(2), MachinePointerInfo(VS),
3160 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1),
3161 MachinePointerInfo(VD), false, false, 0);
3162 Results.push_back(Tmp1);
3165 case ISD::EXTRACT_VECTOR_ELT:
3166 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
3167 // This must be an access of the only element. Return it.
3168 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0),
3169 Node->getOperand(0));
3171 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
3172 Results.push_back(Tmp1);
3174 case ISD::EXTRACT_SUBVECTOR:
3175 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
3177 case ISD::INSERT_SUBVECTOR:
3178 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0)));
3180 case ISD::CONCAT_VECTORS: {
3181 Results.push_back(ExpandVectorBuildThroughStack(Node));
3184 case ISD::SCALAR_TO_VECTOR:
3185 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
3187 case ISD::INSERT_VECTOR_ELT:
3188 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
3189 Node->getOperand(1),
3190 Node->getOperand(2), dl));
3192 case ISD::VECTOR_SHUFFLE: {
3193 SmallVector<int, 8> Mask;
3194 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3196 EVT VT = Node->getValueType(0);
3197 EVT EltVT = VT.getVectorElementType();
3198 if (getTypeAction(EltVT) == Promote)
3199 EltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT);
3200 unsigned NumElems = VT.getVectorNumElements();
3201 SmallVector<SDValue, 8> Ops;
3202 for (unsigned i = 0; i != NumElems; ++i) {
3204 Ops.push_back(DAG.getUNDEF(EltVT));
3207 unsigned Idx = Mask[i];
3209 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3210 Node->getOperand(0),
3211 DAG.getIntPtrConstant(Idx)));
3213 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3214 Node->getOperand(1),
3215 DAG.getIntPtrConstant(Idx - NumElems)));
3217 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3218 Results.push_back(Tmp1);
3221 case ISD::EXTRACT_ELEMENT: {
3222 EVT OpTy = Node->getOperand(0).getValueType();
3223 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
3225 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
3226 DAG.getConstant(OpTy.getSizeInBits()/2,
3227 TLI.getShiftAmountTy(Node->getOperand(0).getValueType())));
3228 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
3231 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
3232 Node->getOperand(0));
3234 Results.push_back(Tmp1);
3237 case ISD::STACKSAVE:
3238 // Expand to CopyFromReg if the target set
3239 // StackPointerRegisterToSaveRestore.
3240 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3241 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
3242 Node->getValueType(0)));
3243 Results.push_back(Results[0].getValue(1));
3245 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
3246 Results.push_back(Node->getOperand(0));
3249 case ISD::STACKRESTORE:
3250 // Expand to CopyToReg if the target set
3251 // StackPointerRegisterToSaveRestore.
3252 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
3253 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
3254 Node->getOperand(1)));
3256 Results.push_back(Node->getOperand(0));
3259 case ISD::FCOPYSIGN:
3260 Results.push_back(ExpandFCOPYSIGN(Node));
3263 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
3264 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
3265 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
3266 Node->getOperand(0));
3267 Results.push_back(Tmp1);
3270 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
3271 EVT VT = Node->getValueType(0);
3272 Tmp1 = Node->getOperand(0);
3273 Tmp2 = DAG.getConstantFP(0.0, VT);
3274 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3275 Tmp1, Tmp2, ISD::SETUGT);
3276 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3277 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3278 Results.push_back(Tmp1);
3282 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
3283 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
3286 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
3287 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
3290 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
3291 RTLIB::COS_F80, RTLIB::COS_PPCF128));
3294 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
3295 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
3298 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
3299 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
3302 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
3303 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
3306 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
3307 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
3310 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
3311 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
3314 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
3315 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
3318 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
3319 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
3322 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
3323 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
3326 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
3327 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
3329 case ISD::FNEARBYINT:
3330 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
3331 RTLIB::NEARBYINT_F64,
3332 RTLIB::NEARBYINT_F80,
3333 RTLIB::NEARBYINT_PPCF128));
3336 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
3337 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
3340 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
3341 RTLIB::POW_F80, RTLIB::POW_PPCF128));
3344 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
3345 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
3348 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
3349 RTLIB::REM_F80, RTLIB::REM_PPCF128));
3352 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64,
3353 RTLIB::FMA_F80, RTLIB::FMA_PPCF128));
3355 case ISD::FP16_TO_FP32:
3356 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false));
3358 case ISD::FP32_TO_FP16:
3359 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false));
3361 case ISD::ConstantFP: {
3362 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
3363 // Check to see if this FP immediate is already legal.
3364 // If this is a legal constant, turn it into a TargetConstantFP node.
3365 if (TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0)))
3366 Results.push_back(SDValue(Node, 0));
3368 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
3371 case ISD::EHSELECTION: {
3372 unsigned Reg = TLI.getExceptionSelectorRegister();
3373 assert(Reg && "Can't expand to unknown register!");
3374 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
3375 Node->getValueType(0)));
3376 Results.push_back(Results[0].getValue(1));
3379 case ISD::EXCEPTIONADDR: {
3380 unsigned Reg = TLI.getExceptionAddressRegister();
3381 assert(Reg && "Can't expand to unknown register!");
3382 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
3383 Node->getValueType(0)));
3384 Results.push_back(Results[0].getValue(1));
3388 EVT VT = Node->getValueType(0);
3389 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3390 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3391 "Don't know how to expand this subtraction!");
3392 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3393 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3394 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
3395 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3400 EVT VT = Node->getValueType(0);
3401 SDVTList VTs = DAG.getVTList(VT, VT);
3402 bool isSigned = Node->getOpcode() == ISD::SREM;
3403 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
3404 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3405 Tmp2 = Node->getOperand(0);
3406 Tmp3 = Node->getOperand(1);
3407 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3408 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3409 UseDivRem(Node, isSigned, false))) {
3410 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
3411 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3413 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3414 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3415 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3416 } else if (isSigned)
3417 Tmp1 = ExpandIntLibCall(Node, true,
3419 RTLIB::SREM_I16, RTLIB::SREM_I32,
3420 RTLIB::SREM_I64, RTLIB::SREM_I128);
3422 Tmp1 = ExpandIntLibCall(Node, false,
3424 RTLIB::UREM_I16, RTLIB::UREM_I32,
3425 RTLIB::UREM_I64, RTLIB::UREM_I128);
3426 Results.push_back(Tmp1);
3431 bool isSigned = Node->getOpcode() == ISD::SDIV;
3432 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
3433 EVT VT = Node->getValueType(0);
3434 SDVTList VTs = DAG.getVTList(VT, VT);
3435 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3436 (isDivRemLibcallAvailable(Node, isSigned, TLI) &&
3437 UseDivRem(Node, isSigned, true)))
3438 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
3439 Node->getOperand(1));
3441 Tmp1 = ExpandIntLibCall(Node, true,
3443 RTLIB::SDIV_I16, RTLIB::SDIV_I32,
3444 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
3446 Tmp1 = ExpandIntLibCall(Node, false,
3448 RTLIB::UDIV_I16, RTLIB::UDIV_I32,
3449 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
3450 Results.push_back(Tmp1);
3455 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
3457 EVT VT = Node->getValueType(0);
3458 SDVTList VTs = DAG.getVTList(VT, VT);
3459 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3460 "If this wasn't legal, it shouldn't have been created!");
3461 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
3462 Node->getOperand(1));
3463 Results.push_back(Tmp1.getValue(1));
3468 // Expand into divrem libcall
3469 ExpandDivRemLibCall(Node, Results);
3472 EVT VT = Node->getValueType(0);
3473 SDVTList VTs = DAG.getVTList(VT, VT);
3474 // See if multiply or divide can be lowered using two-result operations.
3475 // We just need the low half of the multiply; try both the signed
3476 // and unsigned forms. If the target supports both SMUL_LOHI and
3477 // UMUL_LOHI, form a preference by checking which forms of plain
3478 // MULH it supports.
3479 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3480 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3481 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3482 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3483 unsigned OpToUse = 0;
3484 if (HasSMUL_LOHI && !HasMULHS) {
3485 OpToUse = ISD::SMUL_LOHI;
3486 } else if (HasUMUL_LOHI && !HasMULHU) {
3487 OpToUse = ISD::UMUL_LOHI;
3488 } else if (HasSMUL_LOHI) {
3489 OpToUse = ISD::SMUL_LOHI;
3490 } else if (HasUMUL_LOHI) {
3491 OpToUse = ISD::UMUL_LOHI;
3494 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
3495 Node->getOperand(1)));
3498 Tmp1 = ExpandIntLibCall(Node, false,
3500 RTLIB::MUL_I16, RTLIB::MUL_I32,
3501 RTLIB::MUL_I64, RTLIB::MUL_I128);
3502 Results.push_back(Tmp1);
3507 SDValue LHS = Node->getOperand(0);
3508 SDValue RHS = Node->getOperand(1);
3509 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
3510 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3512 Results.push_back(Sum);
3513 EVT OType = Node->getValueType(1);
3515 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
3517 // LHSSign -> LHS >= 0
3518 // RHSSign -> RHS >= 0
3519 // SumSign -> Sum >= 0
3522 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
3524 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
3526 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
3527 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
3528 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
3529 Node->getOpcode() == ISD::SADDO ?
3530 ISD::SETEQ : ISD::SETNE);
3532 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
3533 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
3535 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
3536 Results.push_back(Cmp);
3541 SDValue LHS = Node->getOperand(0);
3542 SDValue RHS = Node->getOperand(1);
3543 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
3544 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
3546 Results.push_back(Sum);
3547 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
3548 Node->getOpcode () == ISD::UADDO ?
3549 ISD::SETULT : ISD::SETUGT));
3554 EVT VT = Node->getValueType(0);
3555 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3556 SDValue LHS = Node->getOperand(0);
3557 SDValue RHS = Node->getOperand(1);
3560 static const unsigned Ops[2][3] =
3561 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
3562 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
3563 bool isSigned = Node->getOpcode() == ISD::SMULO;
3564 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3565 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3566 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3567 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3568 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3570 TopHalf = BottomHalf.getValue(1);
3571 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(),
3572 VT.getSizeInBits() * 2))) {
3573 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
3574 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
3575 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
3576 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3577 DAG.getIntPtrConstant(0));
3578 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3579 DAG.getIntPtrConstant(1));
3581 // We can fall back to a libcall with an illegal type for the MUL if we
3582 // have a libcall big enough.
3583 // Also, we can fall back to a division in some cases, but that's a big
3584 // performance hit in the general case.
3585 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
3586 if (WideVT == MVT::i16)
3587 LC = RTLIB::MUL_I16;
3588 else if (WideVT == MVT::i32)
3589 LC = RTLIB::MUL_I32;
3590 else if (WideVT == MVT::i64)
3591 LC = RTLIB::MUL_I64;
3592 else if (WideVT == MVT::i128)
3593 LC = RTLIB::MUL_I128;
3594 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!");
3596 // The high part is obtained by SRA'ing all but one of the bits of low
3598 unsigned LoSize = VT.getSizeInBits();
3599 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3600 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3601 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3602 DAG.getConstant(LoSize-1, TLI.getPointerTy()));
3604 // Here we're passing the 2 arguments explicitly as 4 arguments that are
3605 // pre-lowered to the correct types. This all depends upon WideVT not
3606 // being a legal type for the architecture and thus has to be split to
3608 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS };
3609 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl);
3610 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3611 DAG.getIntPtrConstant(0));
3612 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3613 DAG.getIntPtrConstant(1));
3617 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3618 TLI.getShiftAmountTy(BottomHalf.getValueType()));
3619 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3620 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3623 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3624 DAG.getConstant(0, VT), ISD::SETNE);
3626 Results.push_back(BottomHalf);
3627 Results.push_back(TopHalf);
3630 case ISD::BUILD_PAIR: {
3631 EVT PairTy = Node->getValueType(0);
3632 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
3633 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
3634 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
3635 DAG.getConstant(PairTy.getSizeInBits()/2,
3636 TLI.getShiftAmountTy(PairTy)));
3637 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
3641 Tmp1 = Node->getOperand(0);
3642 Tmp2 = Node->getOperand(1);
3643 Tmp3 = Node->getOperand(2);
3644 if (Tmp1.getOpcode() == ISD::SETCC) {
3645 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
3647 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
3649 Tmp1 = DAG.getSelectCC(dl, Tmp1,
3650 DAG.getConstant(0, Tmp1.getValueType()),
3651 Tmp2, Tmp3, ISD::SETNE);
3653 Results.push_back(Tmp1);
3656 SDValue Chain = Node->getOperand(0);
3657 SDValue Table = Node->getOperand(1);
3658 SDValue Index = Node->getOperand(2);
3660 EVT PTy = TLI.getPointerTy();
3662 const TargetData &TD = *TLI.getTargetData();
3663 unsigned EntrySize =
3664 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD);
3666 Index = DAG.getNode(ISD::MUL, dl, PTy,
3667 Index, DAG.getConstant(EntrySize, PTy));
3668 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3670 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8);
3671 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3672 MachinePointerInfo::getJumpTable(), MemVT,
3675 if (TM.getRelocationModel() == Reloc::PIC_) {
3676 // For PIC, the sequence is:
3677 // BRIND(load(Jumptable + index) + RelocBase)
3678 // RelocBase can be JumpTable, GOT or some sort of global base.
3679 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3680 TLI.getPICJumpTableRelocBase(Table, DAG));
3682 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3683 Results.push_back(Tmp1);
3687 // Expand brcond's setcc into its constituent parts and create a BR_CC
3689 Tmp1 = Node->getOperand(0);
3690 Tmp2 = Node->getOperand(1);
3691 if (Tmp2.getOpcode() == ISD::SETCC) {
3692 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3693 Tmp1, Tmp2.getOperand(2),
3694 Tmp2.getOperand(0), Tmp2.getOperand(1),
3695 Node->getOperand(2));
3697 // We test only the i1 bit. Skip the AND if UNDEF.
3698 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 :
3699 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2,
3700 DAG.getConstant(1, Tmp2.getValueType()));
3701 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3702 DAG.getCondCode(ISD::SETNE), Tmp3,
3703 DAG.getConstant(0, Tmp3.getValueType()),
3704 Node->getOperand(2));
3706 Results.push_back(Tmp1);
3709 Tmp1 = Node->getOperand(0);
3710 Tmp2 = Node->getOperand(1);
3711 Tmp3 = Node->getOperand(2);
3712 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
3714 // If we expanded the SETCC into an AND/OR, return the new node
3715 if (Tmp2.getNode() == 0) {
3716 Results.push_back(Tmp1);
3720 // Otherwise, SETCC for the given comparison type must be completely
3721 // illegal; expand it into a SELECT_CC.
3722 EVT VT = Node->getValueType(0);
3723 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3724 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
3725 Results.push_back(Tmp1);
3728 case ISD::SELECT_CC: {
3729 Tmp1 = Node->getOperand(0); // LHS
3730 Tmp2 = Node->getOperand(1); // RHS
3731 Tmp3 = Node->getOperand(2); // True
3732 Tmp4 = Node->getOperand(3); // False
3733 SDValue CC = Node->getOperand(4);
3735 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
3736 Tmp1, Tmp2, CC, dl);
3738 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
3739 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3740 CC = DAG.getCondCode(ISD::SETNE);
3741 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
3743 Results.push_back(Tmp1);
3747 Tmp1 = Node->getOperand(0); // Chain
3748 Tmp2 = Node->getOperand(2); // LHS
3749 Tmp3 = Node->getOperand(3); // RHS
3750 Tmp4 = Node->getOperand(1); // CC
3752 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
3753 Tmp2, Tmp3, Tmp4, dl);
3754 assert(LastCALLSEQ.size() == 1 && "branch inside CALLSEQ_BEGIN/END?");
3755 setLastCALLSEQ(DAG.getEntryNode());
3757 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
3758 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
3759 Tmp4 = DAG.getCondCode(ISD::SETNE);
3760 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
3761 Tmp3, Node->getOperand(4));
3762 Results.push_back(Tmp1);
3765 case ISD::GLOBAL_OFFSET_TABLE:
3766 case ISD::GlobalAddress:
3767 case ISD::GlobalTLSAddress:
3768 case ISD::ExternalSymbol:
3769 case ISD::ConstantPool:
3770 case ISD::JumpTable:
3771 case ISD::INTRINSIC_W_CHAIN:
3772 case ISD::INTRINSIC_WO_CHAIN:
3773 case ISD::INTRINSIC_VOID:
3774 // FIXME: Custom lowering for these operations shouldn't return null!
3775 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3776 Results.push_back(SDValue(Node, i));
3780 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3781 SmallVectorImpl<SDValue> &Results) {
3782 EVT OVT = Node->getValueType(0);
3783 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3784 Node->getOpcode() == ISD::SINT_TO_FP ||
3785 Node->getOpcode() == ISD::SETCC) {
3786 OVT = Node->getOperand(0).getValueType();
3788 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3789 DebugLoc dl = Node->getDebugLoc();
3790 SDValue Tmp1, Tmp2, Tmp3;
3791 switch (Node->getOpcode()) {
3795 // Zero extend the argument.
3796 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3797 // Perform the larger operation.
3798 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1);
3799 if (Node->getOpcode() == ISD::CTTZ) {
3800 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3801 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT),
3802 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3804 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3805 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3806 } else if (Node->getOpcode() == ISD::CTLZ) {
3807 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3808 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3809 DAG.getConstant(NVT.getSizeInBits() -
3810 OVT.getSizeInBits(), NVT));
3812 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1));
3815 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3816 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3817 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3818 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3819 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
3820 Results.push_back(Tmp1);
3823 case ISD::FP_TO_UINT:
3824 case ISD::FP_TO_SINT:
3825 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3826 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3827 Results.push_back(Tmp1);
3829 case ISD::UINT_TO_FP:
3830 case ISD::SINT_TO_FP:
3831 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3832 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3833 Results.push_back(Tmp1);
3838 unsigned ExtOp, TruncOp;
3839 if (OVT.isVector()) {
3840 ExtOp = ISD::BITCAST;
3841 TruncOp = ISD::BITCAST;
3843 assert(OVT.isInteger() && "Cannot promote logic operation");
3844 ExtOp = ISD::ANY_EXTEND;
3845 TruncOp = ISD::TRUNCATE;
3847 // Promote each of the values to the new type.
3848 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3849 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3850 // Perform the larger operation, then convert back
3851 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3852 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1));
3856 unsigned ExtOp, TruncOp;
3857 if (Node->getValueType(0).isVector()) {
3858 ExtOp = ISD::BITCAST;
3859 TruncOp = ISD::BITCAST;
3860 } else if (Node->getValueType(0).isInteger()) {
3861 ExtOp = ISD::ANY_EXTEND;
3862 TruncOp = ISD::TRUNCATE;
3864 ExtOp = ISD::FP_EXTEND;
3865 TruncOp = ISD::FP_ROUND;
3867 Tmp1 = Node->getOperand(0);
3868 // Promote each of the values to the new type.
3869 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3870 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3871 // Perform the larger operation, then round down.
3872 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3873 if (TruncOp != ISD::FP_ROUND)
3874 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3876 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3877 DAG.getIntPtrConstant(0));
3878 Results.push_back(Tmp1);
3881 case ISD::VECTOR_SHUFFLE: {
3882 SmallVector<int, 8> Mask;
3883 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3885 // Cast the two input vectors.
3886 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0));
3887 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1));
3889 // Convert the shuffle mask to the right # elements.
3890 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3891 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1);
3892 Results.push_back(Tmp1);
3896 unsigned ExtOp = ISD::FP_EXTEND;
3897 if (NVT.isInteger()) {
3898 ISD::CondCode CCCode =
3899 cast<CondCodeSDNode>(Node->getOperand(2))->get();
3900 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3902 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0));
3903 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3904 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3905 Tmp1, Tmp2, Node->getOperand(2)));
3911 // SelectionDAG::Legalize - This is the entry point for the file.
3913 void SelectionDAG::Legalize() {
3914 /// run - This is the main entry point to this class.
3916 SelectionDAGLegalize(*this).LegalizeDAG();