1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetOptions.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/CommandLine.h"
30 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
31 cl::desc("Pop up a window to show dags before legalize"));
33 static const bool ViewLegalizeDAGs = 0;
36 //===----------------------------------------------------------------------===//
37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
38 /// hacks on it until the target machine can handle it. This involves
39 /// eliminating value sizes the machine cannot handle (promoting small sizes to
40 /// large sizes or splitting up large values into small values) as well as
41 /// eliminating operations the machine cannot handle.
43 /// This code also does a small amount of optimization and recognition of idioms
44 /// as part of its processing. For example, if a target does not support a
45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
46 /// will attempt merge setcc and brc instructions into brcc's.
49 class SelectionDAGLegalize {
53 // Libcall insertion helpers.
55 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
56 /// legalized. We use this to ensure that calls are properly serialized
57 /// against each other, including inserted libcalls.
58 SDOperand LastCALLSEQ_END;
60 /// IsLegalizingCall - This member is used *only* for purposes of providing
61 /// helpful assertions that a libcall isn't created while another call is
62 /// being legalized (which could lead to non-serialized call sequences).
63 bool IsLegalizingCall;
66 Legal, // The target natively supports this operation.
67 Promote, // This operation should be executed in a larger type.
68 Expand, // Try to expand this to other ops, otherwise use a libcall.
71 /// ValueTypeActions - This is a bitvector that contains two bits for each
72 /// value type, where the two bits correspond to the LegalizeAction enum.
73 /// This can be queried with "getTypeAction(VT)".
74 TargetLowering::ValueTypeActionImpl ValueTypeActions;
76 /// LegalizedNodes - For nodes that are of legal width, and that have more
77 /// than one use, this map indicates what regularized operand to use. This
78 /// allows us to avoid legalizing the same thing more than once.
79 std::map<SDOperand, SDOperand> LegalizedNodes;
81 /// PromotedNodes - For nodes that are below legal width, and that have more
82 /// than one use, this map indicates what promoted value to use. This allows
83 /// us to avoid promoting the same thing more than once.
84 std::map<SDOperand, SDOperand> PromotedNodes;
86 /// ExpandedNodes - For nodes that need to be expanded this map indicates
87 /// which which operands are the expanded version of the input. This allows
88 /// us to avoid expanding the same node more than once.
89 std::map<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
91 /// SplitNodes - For vector nodes that need to be split, this map indicates
92 /// which which operands are the split version of the input. This allows us
93 /// to avoid splitting the same node more than once.
94 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
96 /// PackedNodes - For nodes that need to be packed from MVT::Vector types to
97 /// concrete packed types, this contains the mapping of ones we have already
98 /// processed to the result.
99 std::map<SDOperand, SDOperand> PackedNodes;
101 void AddLegalizedOperand(SDOperand From, SDOperand To) {
102 LegalizedNodes.insert(std::make_pair(From, To));
103 // If someone requests legalization of the new node, return itself.
105 LegalizedNodes.insert(std::make_pair(To, To));
107 void AddPromotedOperand(SDOperand From, SDOperand To) {
108 bool isNew = PromotedNodes.insert(std::make_pair(From, To)).second;
109 assert(isNew && "Got into the map somehow?");
110 // If someone requests legalization of the new node, return itself.
111 LegalizedNodes.insert(std::make_pair(To, To));
116 SelectionDAGLegalize(SelectionDAG &DAG);
118 /// getTypeAction - Return how we should legalize values of this type, either
119 /// it is already legal or we need to expand it into multiple registers of
120 /// smaller integer type, or we need to promote it to a larger type.
121 LegalizeAction getTypeAction(MVT::ValueType VT) const {
122 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
125 /// isTypeLegal - Return true if this type is legal on this target.
127 bool isTypeLegal(MVT::ValueType VT) const {
128 return getTypeAction(VT) == Legal;
134 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
135 /// appropriate for its type.
136 void HandleOp(SDOperand Op);
138 /// LegalizeOp - We know that the specified value has a legal type.
139 /// Recursively ensure that the operands have legal types, then return the
141 SDOperand LegalizeOp(SDOperand O);
143 /// PromoteOp - Given an operation that produces a value in an invalid type,
144 /// promote it to compute the value into a larger type. The produced value
145 /// will have the correct bits for the low portion of the register, but no
146 /// guarantee is made about the top bits: it may be zero, sign-extended, or
148 SDOperand PromoteOp(SDOperand O);
150 /// ExpandOp - Expand the specified SDOperand into its two component pieces
151 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
152 /// the LegalizeNodes map is filled in for any results that are not expanded,
153 /// the ExpandedNodes map is filled in for any results that are expanded, and
154 /// the Lo/Hi values are returned. This applies to integer types and Vector
156 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
158 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
159 /// two smaller values of MVT::Vector type.
160 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
162 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
163 /// equivalent operation that returns a packed value (e.g. MVT::V4F32). When
164 /// this is called, we know that PackedVT is the right type for the result and
165 /// we know that this type is legal for the target.
166 SDOperand PackVectorOp(SDOperand O, MVT::ValueType PackedVT);
168 /// isShuffleLegal - Return true if a vector shuffle is legal with the
169 /// specified mask and type. Targets can specify exactly which masks they
170 /// support and the code generator is tasked with not creating illegal masks.
172 /// Note that this will also return true for shuffles that are promoted to a
175 /// If this is a legal shuffle, this method returns the (possibly promoted)
176 /// build_vector Mask. If it's not a legal shuffle, it returns null.
177 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
179 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest);
181 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
183 SDOperand CreateStackTemporary(MVT::ValueType VT);
185 SDOperand ExpandLibCall(const char *Name, SDNode *Node,
187 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
190 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
191 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
192 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
193 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
195 MVT::ValueType DestVT);
196 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
198 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
201 SDOperand ExpandBSWAP(SDOperand Op);
202 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
203 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
204 SDOperand &Lo, SDOperand &Hi);
205 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
206 SDOperand &Lo, SDOperand &Hi);
208 SDOperand LowerVEXTRACT_VECTOR_ELT(SDOperand Op);
209 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
211 SDOperand getIntPtrConstant(uint64_t Val) {
212 return DAG.getConstant(Val, TLI.getPointerTy());
217 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
218 /// specified mask and type. Targets can specify exactly which masks they
219 /// support and the code generator is tasked with not creating illegal masks.
221 /// Note that this will also return true for shuffles that are promoted to a
223 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
224 SDOperand Mask) const {
225 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
227 case TargetLowering::Legal:
228 case TargetLowering::Custom:
230 case TargetLowering::Promote: {
231 // If this is promoted to a different type, convert the shuffle mask and
232 // ask if it is legal in the promoted type!
233 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
235 // If we changed # elements, change the shuffle mask.
236 unsigned NumEltsGrowth =
237 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
238 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
239 if (NumEltsGrowth > 1) {
240 // Renumber the elements.
241 std::vector<SDOperand> Ops;
242 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
243 SDOperand InOp = Mask.getOperand(i);
244 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
245 if (InOp.getOpcode() == ISD::UNDEF)
246 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
248 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
249 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
253 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, Ops);
259 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
262 /// getScalarizedOpcode - Return the scalar opcode that corresponds to the
263 /// specified vector opcode.
264 static unsigned getScalarizedOpcode(unsigned VecOp, MVT::ValueType VT) {
266 default: assert(0 && "Don't know how to scalarize this opcode!");
267 case ISD::VADD: return MVT::isInteger(VT) ? ISD::ADD : ISD::FADD;
268 case ISD::VSUB: return MVT::isInteger(VT) ? ISD::SUB : ISD::FSUB;
269 case ISD::VMUL: return MVT::isInteger(VT) ? ISD::MUL : ISD::FMUL;
270 case ISD::VSDIV: return MVT::isInteger(VT) ? ISD::SDIV: ISD::FDIV;
271 case ISD::VUDIV: return MVT::isInteger(VT) ? ISD::UDIV: ISD::FDIV;
272 case ISD::VAND: return MVT::isInteger(VT) ? ISD::AND : 0;
273 case ISD::VOR: return MVT::isInteger(VT) ? ISD::OR : 0;
274 case ISD::VXOR: return MVT::isInteger(VT) ? ISD::XOR : 0;
278 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
279 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
280 ValueTypeActions(TLI.getValueTypeActions()) {
281 assert(MVT::LAST_VALUETYPE <= 32 &&
282 "Too many value types for ValueTypeActions to hold!");
285 /// ComputeTopDownOrdering - Add the specified node to the Order list if it has
286 /// not been visited yet and if all of its operands have already been visited.
287 static void ComputeTopDownOrdering(SDNode *N, std::vector<SDNode*> &Order,
288 std::map<SDNode*, unsigned> &Visited) {
289 if (++Visited[N] != N->getNumOperands())
290 return; // Haven't visited all operands yet
294 if (N->hasOneUse()) { // Tail recurse in common case.
295 ComputeTopDownOrdering(*N->use_begin(), Order, Visited);
299 // Now that we have N in, add anything that uses it if all of their operands
301 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end(); UI != E;++UI)
302 ComputeTopDownOrdering(*UI, Order, Visited);
306 void SelectionDAGLegalize::LegalizeDAG() {
307 LastCALLSEQ_END = DAG.getEntryNode();
308 IsLegalizingCall = false;
310 // The legalize process is inherently a bottom-up recursive process (users
311 // legalize their uses before themselves). Given infinite stack space, we
312 // could just start legalizing on the root and traverse the whole graph. In
313 // practice however, this causes us to run out of stack space on large basic
314 // blocks. To avoid this problem, compute an ordering of the nodes where each
315 // node is only legalized after all of its operands are legalized.
316 std::map<SDNode*, unsigned> Visited;
317 std::vector<SDNode*> Order;
319 // Compute ordering from all of the leaves in the graphs, those (like the
320 // entry node) that have no operands.
321 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
322 E = DAG.allnodes_end(); I != E; ++I) {
323 if (I->getNumOperands() == 0) {
325 ComputeTopDownOrdering(I, Order, Visited);
329 assert(Order.size() == Visited.size() &&
331 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
332 "Error: DAG is cyclic!");
335 for (unsigned i = 0, e = Order.size(); i != e; ++i)
336 HandleOp(SDOperand(Order[i], 0));
338 // Finally, it's possible the root changed. Get the new root.
339 SDOperand OldRoot = DAG.getRoot();
340 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
341 DAG.setRoot(LegalizedNodes[OldRoot]);
343 ExpandedNodes.clear();
344 LegalizedNodes.clear();
345 PromotedNodes.clear();
349 // Remove dead nodes now.
350 DAG.RemoveDeadNodes(OldRoot.Val);
354 /// FindCallEndFromCallStart - Given a chained node that is part of a call
355 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
356 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
357 if (Node->getOpcode() == ISD::CALLSEQ_END)
359 if (Node->use_empty())
360 return 0; // No CallSeqEnd
362 // The chain is usually at the end.
363 SDOperand TheChain(Node, Node->getNumValues()-1);
364 if (TheChain.getValueType() != MVT::Other) {
365 // Sometimes it's at the beginning.
366 TheChain = SDOperand(Node, 0);
367 if (TheChain.getValueType() != MVT::Other) {
368 // Otherwise, hunt for it.
369 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
370 if (Node->getValueType(i) == MVT::Other) {
371 TheChain = SDOperand(Node, i);
375 // Otherwise, we walked into a node without a chain.
376 if (TheChain.getValueType() != MVT::Other)
381 for (SDNode::use_iterator UI = Node->use_begin(),
382 E = Node->use_end(); UI != E; ++UI) {
384 // Make sure to only follow users of our token chain.
386 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
387 if (User->getOperand(i) == TheChain)
388 if (SDNode *Result = FindCallEndFromCallStart(User))
394 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
395 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
396 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
397 assert(Node && "Didn't find callseq_start for a call??");
398 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
400 assert(Node->getOperand(0).getValueType() == MVT::Other &&
401 "Node doesn't have a token chain argument!");
402 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
405 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
406 /// see if any uses can reach Dest. If no dest operands can get to dest,
407 /// legalize them, legalize ourself, and return false, otherwise, return true.
408 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N,
410 if (N == Dest) return true; // N certainly leads to Dest :)
412 // If the first result of this node has been already legalized, then it cannot
414 switch (getTypeAction(N->getValueType(0))) {
416 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
419 if (PromotedNodes.count(SDOperand(N, 0))) return false;
422 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
426 // Okay, this node has not already been legalized. Check and legalize all
427 // operands. If none lead to Dest, then we can legalize this node.
428 bool OperandsLeadToDest = false;
429 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
430 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
431 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest);
433 if (OperandsLeadToDest) return true;
435 // Okay, this node looks safe, legalize it and return false.
436 HandleOp(SDOperand(N, 0));
440 /// HandleOp - Legalize, Promote, Expand or Pack the specified operand as
441 /// appropriate for its type.
442 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
443 switch (getTypeAction(Op.getValueType())) {
444 default: assert(0 && "Bad type action!");
445 case Legal: LegalizeOp(Op); break;
446 case Promote: PromoteOp(Op); break;
448 if (Op.getValueType() != MVT::Vector) {
453 unsigned NumOps = N->getNumOperands();
454 unsigned NumElements =
455 cast<ConstantSDNode>(N->getOperand(NumOps-2))->getValue();
456 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(NumOps-1))->getVT();
457 MVT::ValueType PackedVT = getVectorType(EVT, NumElements);
458 if (PackedVT != MVT::Other && TLI.isTypeLegal(PackedVT)) {
459 // In the common case, this is a legal vector type, convert it to the
460 // packed operation and type now.
461 PackVectorOp(Op, PackedVT);
462 } else if (NumElements == 1) {
463 // Otherwise, if this is a single element vector, convert it to a
465 PackVectorOp(Op, EVT);
467 // Otherwise, this is a multiple element vector that isn't supported.
468 // Split it in half and legalize both parts.
470 SplitVectorOp(Op, X, Y);
478 /// LegalizeOp - We know that the specified value has a legal type.
479 /// Recursively ensure that the operands have legal types, then return the
481 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
482 assert(isTypeLegal(Op.getValueType()) &&
483 "Caller should expand or promote operands that are not legal!");
484 SDNode *Node = Op.Val;
486 // If this operation defines any values that cannot be represented in a
487 // register on this target, make sure to expand or promote them.
488 if (Node->getNumValues() > 1) {
489 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
490 if (getTypeAction(Node->getValueType(i)) != Legal) {
491 HandleOp(Op.getValue(i));
492 assert(LegalizedNodes.count(Op) &&
493 "Handling didn't add legal operands!");
494 return LegalizedNodes[Op];
498 // Note that LegalizeOp may be reentered even from single-use nodes, which
499 // means that we always must cache transformed nodes.
500 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
501 if (I != LegalizedNodes.end()) return I->second;
503 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
504 SDOperand Result = Op;
505 bool isCustom = false;
507 switch (Node->getOpcode()) {
508 case ISD::FrameIndex:
509 case ISD::EntryToken:
511 case ISD::BasicBlock:
512 case ISD::TargetFrameIndex:
513 case ISD::TargetJumpTable:
514 case ISD::TargetConstant:
515 case ISD::TargetConstantFP:
516 case ISD::TargetConstantPool:
517 case ISD::TargetGlobalAddress:
518 case ISD::TargetExternalSymbol:
523 // Primitives must all be legal.
524 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
525 "This must be legal!");
528 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
529 // If this is a target node, legalize it by legalizing the operands then
530 // passing it through.
531 std::vector<SDOperand> Ops;
532 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
533 Ops.push_back(LegalizeOp(Node->getOperand(i)));
535 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops);
537 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
538 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
539 return Result.getValue(Op.ResNo);
541 // Otherwise this is an unhandled builtin node. splat.
542 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
543 assert(0 && "Do not know how to legalize this operator!");
545 case ISD::GlobalAddress:
546 case ISD::ExternalSymbol:
547 case ISD::ConstantPool:
548 case ISD::JumpTable: // Nothing to do.
549 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
550 default: assert(0 && "This action is not supported yet!");
551 case TargetLowering::Custom:
552 Tmp1 = TLI.LowerOperation(Op, DAG);
553 if (Tmp1.Val) Result = Tmp1;
554 // FALLTHROUGH if the target doesn't want to lower this op after all.
555 case TargetLowering::Legal:
559 case ISD::AssertSext:
560 case ISD::AssertZext:
561 Tmp1 = LegalizeOp(Node->getOperand(0));
562 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
564 case ISD::MERGE_VALUES:
565 // Legalize eliminates MERGE_VALUES nodes.
566 Result = Node->getOperand(Op.ResNo);
568 case ISD::CopyFromReg:
569 Tmp1 = LegalizeOp(Node->getOperand(0));
570 Result = Op.getValue(0);
571 if (Node->getNumValues() == 2) {
572 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
574 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
575 if (Node->getNumOperands() == 3) {
576 Tmp2 = LegalizeOp(Node->getOperand(2));
577 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
579 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
581 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
583 // Since CopyFromReg produces two values, make sure to remember that we
584 // legalized both of them.
585 AddLegalizedOperand(Op.getValue(0), Result);
586 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
587 return Result.getValue(Op.ResNo);
589 MVT::ValueType VT = Op.getValueType();
590 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
591 default: assert(0 && "This action is not supported yet!");
592 case TargetLowering::Expand:
593 if (MVT::isInteger(VT))
594 Result = DAG.getConstant(0, VT);
595 else if (MVT::isFloatingPoint(VT))
596 Result = DAG.getConstantFP(0, VT);
598 assert(0 && "Unknown value type!");
600 case TargetLowering::Legal:
606 case ISD::INTRINSIC_W_CHAIN:
607 case ISD::INTRINSIC_WO_CHAIN:
608 case ISD::INTRINSIC_VOID: {
609 std::vector<SDOperand> Ops;
610 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
611 Ops.push_back(LegalizeOp(Node->getOperand(i)));
612 Result = DAG.UpdateNodeOperands(Result, Ops);
614 // Allow the target to custom lower its intrinsics if it wants to.
615 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
616 TargetLowering::Custom) {
617 Tmp3 = TLI.LowerOperation(Result, DAG);
618 if (Tmp3.Val) Result = Tmp3;
621 if (Result.Val->getNumValues() == 1) break;
623 // Must have return value and chain result.
624 assert(Result.Val->getNumValues() == 2 &&
625 "Cannot return more than two values!");
627 // Since loads produce two values, make sure to remember that we
628 // legalized both of them.
629 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
630 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
631 return Result.getValue(Op.ResNo);
635 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
636 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
638 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
639 case TargetLowering::Promote:
640 default: assert(0 && "This action is not supported yet!");
641 case TargetLowering::Expand: {
642 MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
643 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
644 bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
646 if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
647 const std::string &FName =
648 cast<StringSDNode>(Node->getOperand(3))->getValue();
649 const std::string &DirName =
650 cast<StringSDNode>(Node->getOperand(4))->getValue();
651 unsigned SrcFile = DebugInfo->RecordSource(DirName, FName);
653 std::vector<SDOperand> Ops;
654 Ops.push_back(Tmp1); // chain
655 SDOperand LineOp = Node->getOperand(1);
656 SDOperand ColOp = Node->getOperand(2);
659 Ops.push_back(LineOp); // line #
660 Ops.push_back(ColOp); // col #
661 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
662 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
664 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
665 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
666 unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
667 Ops.push_back(DAG.getConstant(ID, MVT::i32));
668 Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
671 Result = Tmp1; // chain
675 case TargetLowering::Legal:
676 if (Tmp1 != Node->getOperand(0) ||
677 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
678 std::vector<SDOperand> Ops;
680 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
681 Ops.push_back(Node->getOperand(1)); // line # must be legal.
682 Ops.push_back(Node->getOperand(2)); // col # must be legal.
684 // Otherwise promote them.
685 Ops.push_back(PromoteOp(Node->getOperand(1)));
686 Ops.push_back(PromoteOp(Node->getOperand(2)));
688 Ops.push_back(Node->getOperand(3)); // filename must be legal.
689 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
690 Result = DAG.UpdateNodeOperands(Result, Ops);
697 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
698 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
699 default: assert(0 && "This action is not supported yet!");
700 case TargetLowering::Legal:
701 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
702 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
703 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
704 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
705 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
710 case ISD::DEBUG_LABEL:
711 assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
712 switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
713 default: assert(0 && "This action is not supported yet!");
714 case TargetLowering::Legal:
715 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
716 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
717 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
723 // We know we don't need to expand constants here, constants only have one
724 // value and we check that it is fine above.
726 // FIXME: Maybe we should handle things like targets that don't support full
727 // 32-bit immediates?
729 case ISD::ConstantFP: {
730 // Spill FP immediates to the constant pool if the target cannot directly
731 // codegen them. Targets often have some immediate values that can be
732 // efficiently generated into an FP register without a load. We explicitly
733 // leave these constants as ConstantFP nodes for the target to deal with.
734 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
736 // Check to see if this FP immediate is already legal.
737 bool isLegal = false;
738 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
739 E = TLI.legal_fpimm_end(); I != E; ++I)
740 if (CFP->isExactlyValue(*I)) {
745 // If this is a legal constant, turn it into a TargetConstantFP node.
747 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
751 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
752 default: assert(0 && "This action is not supported yet!");
753 case TargetLowering::Custom:
754 Tmp3 = TLI.LowerOperation(Result, DAG);
760 case TargetLowering::Expand:
761 // Otherwise we need to spill the constant to memory.
764 // If a FP immediate is precise when represented as a float and if the
765 // target can do an extending load from float to double, we put it into
766 // the constant pool as a float, even if it's is statically typed as a
768 MVT::ValueType VT = CFP->getValueType(0);
769 bool isDouble = VT == MVT::f64;
770 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
771 Type::FloatTy, CFP->getValue());
772 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
773 // Only do this if the target has a native EXTLOAD instruction from
775 TLI.isOperationLegal(ISD::EXTLOAD, MVT::f32)) {
776 LLVMC = cast<ConstantFP>(ConstantExpr::getCast(LLVMC, Type::FloatTy));
781 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
783 Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
784 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
786 Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
787 DAG.getSrcValue(NULL));
792 case ISD::TokenFactor:
793 if (Node->getNumOperands() == 2) {
794 Tmp1 = LegalizeOp(Node->getOperand(0));
795 Tmp2 = LegalizeOp(Node->getOperand(1));
796 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
797 } else if (Node->getNumOperands() == 3) {
798 Tmp1 = LegalizeOp(Node->getOperand(0));
799 Tmp2 = LegalizeOp(Node->getOperand(1));
800 Tmp3 = LegalizeOp(Node->getOperand(2));
801 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
803 std::vector<SDOperand> Ops;
804 // Legalize the operands.
805 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
806 Ops.push_back(LegalizeOp(Node->getOperand(i)));
807 Result = DAG.UpdateNodeOperands(Result, Ops);
811 case ISD::FORMAL_ARGUMENTS:
813 // The only option for this is to custom lower it.
814 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
815 assert(Tmp3.Val && "Target didn't custom lower this node!");
816 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
817 "Lowering call/formal_arguments produced unexpected # results!");
819 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
820 // remember that we legalized all of them, so it doesn't get relegalized.
821 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
822 Tmp1 = LegalizeOp(Tmp3.getValue(i));
825 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
829 case ISD::BUILD_VECTOR:
830 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
831 default: assert(0 && "This action is not supported yet!");
832 case TargetLowering::Custom:
833 Tmp3 = TLI.LowerOperation(Result, DAG);
839 case TargetLowering::Expand:
840 Result = ExpandBUILD_VECTOR(Result.Val);
844 case ISD::INSERT_VECTOR_ELT:
845 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
846 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
847 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
848 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
850 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
851 Node->getValueType(0))) {
852 default: assert(0 && "This action is not supported yet!");
853 case TargetLowering::Legal:
855 case TargetLowering::Custom:
856 Tmp3 = TLI.LowerOperation(Result, DAG);
862 case TargetLowering::Expand: {
863 // If the insert index is a constant, codegen this as a scalar_to_vector,
864 // then a shuffle that inserts it into the right position in the vector.
865 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
866 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
867 Tmp1.getValueType(), Tmp2);
869 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
870 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
871 MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
873 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
874 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
876 std::vector<SDOperand> ShufOps;
877 for (unsigned i = 0; i != NumElts; ++i) {
878 if (i != InsertPos->getValue())
879 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
881 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
883 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,ShufOps);
885 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
886 Tmp1, ScVec, ShufMask);
887 Result = LegalizeOp(Result);
891 // If the target doesn't support this, we have to spill the input vector
892 // to a temporary stack slot, update the element, then reload it. This is
893 // badness. We could also load the value into a vector register (either
894 // with a "move to register" or "extload into register" instruction, then
895 // permute it into place, if the idx is a constant and if the idx is
896 // supported by the target.
897 MVT::ValueType VT = Tmp1.getValueType();
898 MVT::ValueType EltVT = Tmp2.getValueType();
899 MVT::ValueType IdxVT = Tmp3.getValueType();
900 MVT::ValueType PtrVT = TLI.getPointerTy();
901 SDOperand StackPtr = CreateStackTemporary(VT);
903 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
904 Tmp1, StackPtr, DAG.getSrcValue(NULL));
906 // Truncate or zero extend offset to target pointer type.
907 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
908 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
909 // Add the offset to the index.
910 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
911 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
912 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
913 // Store the scalar value.
914 Ch = DAG.getNode(ISD::STORE, MVT::Other, Ch,
915 Tmp2, StackPtr2, DAG.getSrcValue(NULL));
916 // Load the updated vector.
917 Result = DAG.getLoad(VT, Ch, StackPtr, DAG.getSrcValue(NULL));
922 case ISD::SCALAR_TO_VECTOR:
923 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
924 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
928 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
929 Result = DAG.UpdateNodeOperands(Result, Tmp1);
930 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
931 Node->getValueType(0))) {
932 default: assert(0 && "This action is not supported yet!");
933 case TargetLowering::Legal:
935 case TargetLowering::Custom:
936 Tmp3 = TLI.LowerOperation(Result, DAG);
942 case TargetLowering::Expand:
943 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
947 case ISD::VECTOR_SHUFFLE:
948 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
949 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
950 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
952 // Allow targets to custom lower the SHUFFLEs they support.
953 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
954 default: assert(0 && "Unknown operation action!");
955 case TargetLowering::Legal:
956 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
957 "vector shuffle should not be created if not legal!");
959 case TargetLowering::Custom:
960 Tmp3 = TLI.LowerOperation(Result, DAG);
966 case TargetLowering::Expand: {
967 MVT::ValueType VT = Node->getValueType(0);
968 MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
969 MVT::ValueType PtrVT = TLI.getPointerTy();
970 SDOperand Mask = Node->getOperand(2);
971 unsigned NumElems = Mask.getNumOperands();
972 std::vector<SDOperand> Ops;
973 for (unsigned i = 0; i != NumElems; ++i) {
974 SDOperand Arg = Mask.getOperand(i);
975 if (Arg.getOpcode() == ISD::UNDEF) {
976 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
978 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
979 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
981 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
982 DAG.getConstant(Idx, PtrVT)));
984 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
985 DAG.getConstant(Idx - NumElems, PtrVT)));
988 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
991 case TargetLowering::Promote: {
992 // Change base type to a different vector type.
993 MVT::ValueType OVT = Node->getValueType(0);
994 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
996 // Cast the two input vectors.
997 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
998 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1000 // Convert the shuffle mask to the right # elements.
1001 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1002 assert(Tmp3.Val && "Shuffle not legal?");
1003 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1004 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1010 case ISD::EXTRACT_VECTOR_ELT:
1011 Tmp1 = LegalizeOp(Node->getOperand(0));
1012 Tmp2 = LegalizeOp(Node->getOperand(1));
1013 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1015 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT,
1016 Tmp1.getValueType())) {
1017 default: assert(0 && "This action is not supported yet!");
1018 case TargetLowering::Legal:
1020 case TargetLowering::Custom:
1021 Tmp3 = TLI.LowerOperation(Result, DAG);
1027 case TargetLowering::Expand:
1028 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1033 case ISD::VEXTRACT_VECTOR_ELT:
1034 Result = LegalizeOp(LowerVEXTRACT_VECTOR_ELT(Op));
1037 case ISD::CALLSEQ_START: {
1038 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1040 // Recursively Legalize all of the inputs of the call end that do not lead
1041 // to this call start. This ensures that any libcalls that need be inserted
1042 // are inserted *before* the CALLSEQ_START.
1043 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1044 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node);
1046 // Now that we legalized all of the inputs (which may have inserted
1047 // libcalls) create the new CALLSEQ_START node.
1048 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1050 // Merge in the last call, to ensure that this call start after the last
1052 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1053 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1054 Tmp1 = LegalizeOp(Tmp1);
1057 // Do not try to legalize the target-specific arguments (#1+).
1058 if (Tmp1 != Node->getOperand(0)) {
1059 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1061 Result = DAG.UpdateNodeOperands(Result, Ops);
1064 // Remember that the CALLSEQ_START is legalized.
1065 AddLegalizedOperand(Op.getValue(0), Result);
1066 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1067 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1069 // Now that the callseq_start and all of the non-call nodes above this call
1070 // sequence have been legalized, legalize the call itself. During this
1071 // process, no libcalls can/will be inserted, guaranteeing that no calls
1073 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1074 SDOperand InCallSEQ = LastCALLSEQ_END;
1075 // Note that we are selecting this call!
1076 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1077 IsLegalizingCall = true;
1079 // Legalize the call, starting from the CALLSEQ_END.
1080 LegalizeOp(LastCALLSEQ_END);
1081 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1084 case ISD::CALLSEQ_END:
1085 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1086 // will cause this node to be legalized as well as handling libcalls right.
1087 if (LastCALLSEQ_END.Val != Node) {
1088 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1089 std::map<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1090 assert(I != LegalizedNodes.end() &&
1091 "Legalizing the call start should have legalized this node!");
1095 // Otherwise, the call start has been legalized and everything is going
1096 // according to plan. Just legalize ourselves normally here.
1097 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1098 // Do not try to legalize the target-specific arguments (#1+), except for
1099 // an optional flag input.
1100 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1101 if (Tmp1 != Node->getOperand(0)) {
1102 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1104 Result = DAG.UpdateNodeOperands(Result, Ops);
1107 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1108 if (Tmp1 != Node->getOperand(0) ||
1109 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1110 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1113 Result = DAG.UpdateNodeOperands(Result, Ops);
1116 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1117 // This finishes up call legalization.
1118 IsLegalizingCall = false;
1120 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1121 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1122 if (Node->getNumValues() == 2)
1123 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1124 return Result.getValue(Op.ResNo);
1125 case ISD::DYNAMIC_STACKALLOC: {
1126 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1127 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1128 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1129 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1131 Tmp1 = Result.getValue(0);
1132 Tmp2 = Result.getValue(1);
1133 switch (TLI.getOperationAction(Node->getOpcode(),
1134 Node->getValueType(0))) {
1135 default: assert(0 && "This action is not supported yet!");
1136 case TargetLowering::Expand: {
1137 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1138 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1139 " not tell us which reg is the stack pointer!");
1140 SDOperand Chain = Tmp1.getOperand(0);
1141 SDOperand Size = Tmp2.getOperand(1);
1142 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1143 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1144 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1145 Tmp1 = LegalizeOp(Tmp1);
1146 Tmp2 = LegalizeOp(Tmp2);
1149 case TargetLowering::Custom:
1150 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1152 Tmp1 = LegalizeOp(Tmp3);
1153 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1156 case TargetLowering::Legal:
1159 // Since this op produce two values, make sure to remember that we
1160 // legalized both of them.
1161 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1162 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1163 return Op.ResNo ? Tmp2 : Tmp1;
1165 case ISD::INLINEASM:
1166 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize Chain.
1167 Tmp2 = Node->getOperand(Node->getNumOperands()-1);
1168 if (Tmp2.getValueType() == MVT::Flag) // Legalize Flag if it exists.
1169 Tmp2 = Tmp3 = SDOperand(0, 0);
1171 Tmp3 = LegalizeOp(Tmp2);
1173 if (Tmp1 != Node->getOperand(0) || Tmp2 != Tmp3) {
1174 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end());
1176 if (Tmp3.Val) Ops.back() = Tmp3;
1177 Result = DAG.UpdateNodeOperands(Result, Ops);
1180 // INLINE asm returns a chain and flag, make sure to add both to the map.
1181 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1182 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1183 return Result.getValue(Op.ResNo);
1185 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1186 // Ensure that libcalls are emitted before a branch.
1187 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1188 Tmp1 = LegalizeOp(Tmp1);
1189 LastCALLSEQ_END = DAG.getEntryNode();
1191 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1194 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1195 // Ensure that libcalls are emitted before a branch.
1196 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1197 Tmp1 = LegalizeOp(Tmp1);
1198 LastCALLSEQ_END = DAG.getEntryNode();
1200 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1201 default: assert(0 && "Indirect target must be legal type (pointer)!");
1203 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1206 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1209 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1210 // Ensure that libcalls are emitted before a return.
1211 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1212 Tmp1 = LegalizeOp(Tmp1);
1213 LastCALLSEQ_END = DAG.getEntryNode();
1215 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1216 case Expand: assert(0 && "It's impossible to expand bools");
1218 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1221 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1225 // Basic block destination (Op#2) is always legal.
1226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1228 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1229 default: assert(0 && "This action is not supported yet!");
1230 case TargetLowering::Legal: break;
1231 case TargetLowering::Custom:
1232 Tmp1 = TLI.LowerOperation(Result, DAG);
1233 if (Tmp1.Val) Result = Tmp1;
1235 case TargetLowering::Expand:
1236 // Expand brcond's setcc into its constituent parts and create a BR_CC
1238 if (Tmp2.getOpcode() == ISD::SETCC) {
1239 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1240 Tmp2.getOperand(0), Tmp2.getOperand(1),
1241 Node->getOperand(2));
1243 // Make sure the condition is either zero or one. It may have been
1244 // promoted from something else.
1245 unsigned NumBits = MVT::getSizeInBits(Tmp2.getValueType());
1246 if (!TLI.MaskedValueIsZero(Tmp2, (~0ULL >> (64-NumBits))^1))
1247 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1249 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1250 DAG.getCondCode(ISD::SETNE), Tmp2,
1251 DAG.getConstant(0, Tmp2.getValueType()),
1252 Node->getOperand(2));
1258 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1259 // Ensure that libcalls are emitted before a branch.
1260 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1261 Tmp1 = LegalizeOp(Tmp1);
1262 LastCALLSEQ_END = DAG.getEntryNode();
1264 Tmp2 = Node->getOperand(2); // LHS
1265 Tmp3 = Node->getOperand(3); // RHS
1266 Tmp4 = Node->getOperand(1); // CC
1268 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1270 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1271 // the LHS is a legal SETCC itself. In this case, we need to compare
1272 // the result against zero to select between true and false values.
1273 if (Tmp3.Val == 0) {
1274 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1275 Tmp4 = DAG.getCondCode(ISD::SETNE);
1278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1279 Node->getOperand(4));
1281 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1282 default: assert(0 && "Unexpected action for BR_CC!");
1283 case TargetLowering::Legal: break;
1284 case TargetLowering::Custom:
1285 Tmp4 = TLI.LowerOperation(Result, DAG);
1286 if (Tmp4.Val) Result = Tmp4;
1291 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1292 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1294 MVT::ValueType VT = Node->getValueType(0);
1295 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1296 Tmp3 = Result.getValue(0);
1297 Tmp4 = Result.getValue(1);
1299 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1300 default: assert(0 && "This action is not supported yet!");
1301 case TargetLowering::Legal: break;
1302 case TargetLowering::Custom:
1303 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1305 Tmp3 = LegalizeOp(Tmp1);
1306 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1309 case TargetLowering::Promote: {
1310 // Only promote a load of vector type to another.
1311 assert(MVT::isVector(VT) && "Cannot promote this load!");
1312 // Change base type to a different vector type.
1313 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1315 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, Node->getOperand(2));
1316 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1317 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1321 // Since loads produce two values, make sure to remember that we
1322 // legalized both of them.
1323 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1324 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1325 return Op.ResNo ? Tmp4 : Tmp3;
1329 case ISD::ZEXTLOAD: {
1330 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1331 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1333 MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
1334 switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
1335 default: assert(0 && "This action is not supported yet!");
1336 case TargetLowering::Promote:
1337 assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
1338 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1339 DAG.getValueType(MVT::i8));
1340 Tmp1 = Result.getValue(0);
1341 Tmp2 = Result.getValue(1);
1343 case TargetLowering::Custom:
1346 case TargetLowering::Legal:
1347 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2),
1348 Node->getOperand(3));
1349 Tmp1 = Result.getValue(0);
1350 Tmp2 = Result.getValue(1);
1353 Tmp3 = TLI.LowerOperation(Tmp3, DAG);
1355 Tmp1 = LegalizeOp(Tmp3);
1356 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1360 case TargetLowering::Expand:
1361 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1362 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1363 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, Node->getOperand(2));
1364 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1365 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1366 Tmp2 = LegalizeOp(Load.getValue(1));
1369 assert(Node->getOpcode() != ISD::EXTLOAD &&
1370 "EXTLOAD should always be supported!");
1371 // Turn the unsupported load into an EXTLOAD followed by an explicit
1372 // zero/sign extend inreg.
1373 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1374 Tmp1, Tmp2, Node->getOperand(2), SrcVT);
1376 if (Node->getOpcode() == ISD::SEXTLOAD)
1377 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1378 Result, DAG.getValueType(SrcVT));
1380 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1381 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1382 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1385 // Since loads produce two values, make sure to remember that we legalized
1387 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1388 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1389 return Op.ResNo ? Tmp2 : Tmp1;
1391 case ISD::EXTRACT_ELEMENT: {
1392 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1393 switch (getTypeAction(OpTy)) {
1394 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1396 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1398 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1399 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1400 TLI.getShiftAmountTy()));
1401 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1404 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1405 Node->getOperand(0));
1409 // Get both the low and high parts.
1410 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1411 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1412 Result = Tmp2; // 1 -> Hi
1414 Result = Tmp1; // 0 -> Lo
1420 case ISD::CopyToReg:
1421 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1423 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1424 "Register type must be legal!");
1425 // Legalize the incoming value (must be a legal type).
1426 Tmp2 = LegalizeOp(Node->getOperand(2));
1427 if (Node->getNumValues() == 1) {
1428 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1430 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1431 if (Node->getNumOperands() == 4) {
1432 Tmp3 = LegalizeOp(Node->getOperand(3));
1433 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1436 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1439 // Since this produces two values, make sure to remember that we legalized
1441 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1442 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1448 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1450 // Ensure that libcalls are emitted before a return.
1451 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1452 Tmp1 = LegalizeOp(Tmp1);
1453 LastCALLSEQ_END = DAG.getEntryNode();
1455 switch (Node->getNumOperands()) {
1457 Tmp2 = Node->getOperand(1);
1458 switch (getTypeAction(Tmp2.getValueType())) {
1460 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2));
1463 if (Tmp2.getValueType() != MVT::Vector) {
1465 ExpandOp(Tmp2, Lo, Hi);
1466 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1468 SDNode *InVal = Tmp2.Val;
1470 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1471 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1473 // Figure out if there is a Packed type corresponding to this Vector
1474 // type. If so, convert to the packed type.
1475 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1476 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1477 // Turn this into a return of the packed type.
1478 Tmp2 = PackVectorOp(Tmp2, TVT);
1479 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1480 } else if (NumElems == 1) {
1481 // Turn this into a return of the scalar type.
1482 Tmp2 = PackVectorOp(Tmp2, EVT);
1483 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1485 // FIXME: Returns of gcc generic vectors smaller than a legal type
1486 // should be returned in integer registers!
1488 // The scalarized value type may not be legal, e.g. it might require
1489 // promotion or expansion. Relegalize the return.
1490 Result = LegalizeOp(Result);
1492 // FIXME: Returns of gcc generic vectors larger than a legal vector
1493 // type should be returned by reference!
1495 SplitVectorOp(Tmp2, Lo, Hi);
1496 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Hi);
1497 Result = LegalizeOp(Result);
1502 Tmp2 = PromoteOp(Node->getOperand(1));
1503 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1504 Result = LegalizeOp(Result);
1509 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1511 default: { // ret <values>
1512 std::vector<SDOperand> NewValues;
1513 NewValues.push_back(Tmp1);
1514 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
1515 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1517 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1521 assert(Node->getOperand(i).getValueType() != MVT::Vector &&
1522 "FIXME: TODO: implement returning non-legal vector types!");
1523 ExpandOp(Node->getOperand(i), Lo, Hi);
1524 NewValues.push_back(Lo);
1525 NewValues.push_back(Hi);
1529 assert(0 && "Can't promote multiple return value yet!");
1532 if (NewValues.size() == Node->getNumOperands())
1533 Result = DAG.UpdateNodeOperands(Result, NewValues);
1535 Result = DAG.getNode(ISD::RET, MVT::Other, NewValues);
1540 if (Result.getOpcode() == ISD::RET) {
1541 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1542 default: assert(0 && "This action is not supported yet!");
1543 case TargetLowering::Legal: break;
1544 case TargetLowering::Custom:
1545 Tmp1 = TLI.LowerOperation(Result, DAG);
1546 if (Tmp1.Val) Result = Tmp1;
1552 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1553 Tmp2 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1555 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1556 // FIXME: We shouldn't do this for TargetConstantFP's.
1557 // FIXME: move this to the DAG Combiner!
1558 if (ConstantFPSDNode *CFP =dyn_cast<ConstantFPSDNode>(Node->getOperand(1))){
1559 if (CFP->getValueType(0) == MVT::f32) {
1560 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1562 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1563 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1565 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1566 Node->getOperand(3));
1570 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1572 Tmp3 = LegalizeOp(Node->getOperand(1));
1573 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1574 Node->getOperand(3));
1576 MVT::ValueType VT = Tmp3.getValueType();
1577 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1578 default: assert(0 && "This action is not supported yet!");
1579 case TargetLowering::Legal: break;
1580 case TargetLowering::Custom:
1581 Tmp1 = TLI.LowerOperation(Result, DAG);
1582 if (Tmp1.Val) Result = Tmp1;
1584 case TargetLowering::Promote:
1585 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1586 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1587 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1588 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1589 Node->getOperand(3));
1595 // Truncate the value and store the result.
1596 Tmp3 = PromoteOp(Node->getOperand(1));
1597 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp3, Tmp2,
1598 Node->getOperand(3),
1599 DAG.getValueType(Node->getOperand(1).getValueType()));
1603 unsigned IncrementSize = 0;
1606 // If this is a vector type, then we have to calculate the increment as
1607 // the product of the element size in bytes, and the number of elements
1608 // in the high half of the vector.
1609 if (Node->getOperand(1).getValueType() == MVT::Vector) {
1610 SDNode *InVal = Node->getOperand(1).Val;
1612 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
1613 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
1615 // Figure out if there is a Packed type corresponding to this Vector
1616 // type. If so, convert to the packed type.
1617 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1618 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
1619 // Turn this into a normal store of the packed type.
1620 Tmp3 = PackVectorOp(Node->getOperand(1), TVT);
1621 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1622 Node->getOperand(3));
1623 Result = LegalizeOp(Result);
1625 } else if (NumElems == 1) {
1626 // Turn this into a normal store of the scalar type.
1627 Tmp3 = PackVectorOp(Node->getOperand(1), EVT);
1628 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1629 Node->getOperand(3));
1630 // The scalarized value type may not be legal, e.g. it might require
1631 // promotion or expansion. Relegalize the scalar store.
1632 Result = LegalizeOp(Result);
1635 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1636 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1639 ExpandOp(Node->getOperand(1), Lo, Hi);
1640 IncrementSize = MVT::getSizeInBits(Hi.getValueType())/8;
1642 if (!TLI.isLittleEndian())
1646 Lo = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Lo, Tmp2,
1647 Node->getOperand(3));
1648 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1649 getIntPtrConstant(IncrementSize));
1650 assert(isTypeLegal(Tmp2.getValueType()) &&
1651 "Pointers must be legal!");
1652 // FIXME: This sets the srcvalue of both halves to be the same, which is
1654 Hi = DAG.getNode(ISD::STORE, MVT::Other, Tmp1, Hi, Tmp2,
1655 Node->getOperand(3));
1656 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1662 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1663 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1665 case ISD::STACKSAVE:
1666 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1667 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1668 Tmp1 = Result.getValue(0);
1669 Tmp2 = Result.getValue(1);
1671 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1672 default: assert(0 && "This action is not supported yet!");
1673 case TargetLowering::Legal: break;
1674 case TargetLowering::Custom:
1675 Tmp3 = TLI.LowerOperation(Result, DAG);
1677 Tmp1 = LegalizeOp(Tmp3);
1678 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1681 case TargetLowering::Expand:
1682 // Expand to CopyFromReg if the target set
1683 // StackPointerRegisterToSaveRestore.
1684 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1685 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1686 Node->getValueType(0));
1687 Tmp2 = Tmp1.getValue(1);
1689 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1690 Tmp2 = Node->getOperand(0);
1695 // Since stacksave produce two values, make sure to remember that we
1696 // legalized both of them.
1697 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1698 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1699 return Op.ResNo ? Tmp2 : Tmp1;
1701 case ISD::STACKRESTORE:
1702 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1703 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1704 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1706 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1707 default: assert(0 && "This action is not supported yet!");
1708 case TargetLowering::Legal: break;
1709 case TargetLowering::Custom:
1710 Tmp1 = TLI.LowerOperation(Result, DAG);
1711 if (Tmp1.Val) Result = Tmp1;
1713 case TargetLowering::Expand:
1714 // Expand to CopyToReg if the target set
1715 // StackPointerRegisterToSaveRestore.
1716 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1717 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1725 case ISD::READCYCLECOUNTER:
1726 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1727 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1729 // Since rdcc produce two values, make sure to remember that we legalized
1731 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1732 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1735 case ISD::TRUNCSTORE: {
1736 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1737 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the pointer.
1739 assert(isTypeLegal(Node->getOperand(1).getValueType()) &&
1740 "Cannot handle illegal TRUNCSTORE yet!");
1741 Tmp2 = LegalizeOp(Node->getOperand(1));
1743 // The only promote case we handle is TRUNCSTORE:i1 X into
1744 // -> TRUNCSTORE:i8 (and X, 1)
1745 if (cast<VTSDNode>(Node->getOperand(4))->getVT() == MVT::i1 &&
1746 TLI.getOperationAction(ISD::TRUNCSTORE, MVT::i1) ==
1747 TargetLowering::Promote) {
1748 // Promote the bool to a mask then store.
1749 Tmp2 = DAG.getNode(ISD::AND, Tmp2.getValueType(), Tmp2,
1750 DAG.getConstant(1, Tmp2.getValueType()));
1751 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Tmp1, Tmp2, Tmp3,
1752 Node->getOperand(3), DAG.getValueType(MVT::i8));
1754 } else if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1) ||
1755 Tmp3 != Node->getOperand(2)) {
1756 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
1757 Node->getOperand(3), Node->getOperand(4));
1760 MVT::ValueType StVT = cast<VTSDNode>(Result.Val->getOperand(4))->getVT();
1761 switch (TLI.getOperationAction(Result.Val->getOpcode(), StVT)) {
1762 default: assert(0 && "This action is not supported yet!");
1763 case TargetLowering::Legal: break;
1764 case TargetLowering::Custom:
1765 Tmp1 = TLI.LowerOperation(Result, DAG);
1766 if (Tmp1.Val) Result = Tmp1;
1772 switch (getTypeAction(Node->getOperand(0).getValueType())) {
1773 case Expand: assert(0 && "It's impossible to expand bools");
1775 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
1778 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
1781 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
1782 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
1784 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1786 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
1787 default: assert(0 && "This action is not supported yet!");
1788 case TargetLowering::Legal: break;
1789 case TargetLowering::Custom: {
1790 Tmp1 = TLI.LowerOperation(Result, DAG);
1791 if (Tmp1.Val) Result = Tmp1;
1794 case TargetLowering::Expand:
1795 if (Tmp1.getOpcode() == ISD::SETCC) {
1796 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
1798 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
1800 // Make sure the condition is either zero or one. It may have been
1801 // promoted from something else.
1802 unsigned NumBits = MVT::getSizeInBits(Tmp1.getValueType());
1803 if (!TLI.MaskedValueIsZero(Tmp1, (~0ULL >> (64-NumBits))^1))
1804 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
1805 Result = DAG.getSelectCC(Tmp1,
1806 DAG.getConstant(0, Tmp1.getValueType()),
1807 Tmp2, Tmp3, ISD::SETNE);
1810 case TargetLowering::Promote: {
1811 MVT::ValueType NVT =
1812 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
1813 unsigned ExtOp, TruncOp;
1814 if (MVT::isVector(Tmp2.getValueType())) {
1815 ExtOp = ISD::BIT_CONVERT;
1816 TruncOp = ISD::BIT_CONVERT;
1817 } else if (MVT::isInteger(Tmp2.getValueType())) {
1818 ExtOp = ISD::ANY_EXTEND;
1819 TruncOp = ISD::TRUNCATE;
1821 ExtOp = ISD::FP_EXTEND;
1822 TruncOp = ISD::FP_ROUND;
1824 // Promote each of the values to the new type.
1825 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
1826 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
1827 // Perform the larger operation, then round down.
1828 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
1829 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
1834 case ISD::SELECT_CC: {
1835 Tmp1 = Node->getOperand(0); // LHS
1836 Tmp2 = Node->getOperand(1); // RHS
1837 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1838 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1839 SDOperand CC = Node->getOperand(4);
1841 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
1843 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1844 // the LHS is a legal SETCC itself. In this case, we need to compare
1845 // the result against zero to select between true and false values.
1846 if (Tmp2.Val == 0) {
1847 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1848 CC = DAG.getCondCode(ISD::SETNE);
1850 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1852 // Everything is legal, see if we should expand this op or something.
1853 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1854 default: assert(0 && "This action is not supported yet!");
1855 case TargetLowering::Legal: break;
1856 case TargetLowering::Custom:
1857 Tmp1 = TLI.LowerOperation(Result, DAG);
1858 if (Tmp1.Val) Result = Tmp1;
1864 Tmp1 = Node->getOperand(0);
1865 Tmp2 = Node->getOperand(1);
1866 Tmp3 = Node->getOperand(2);
1867 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
1869 // If we had to Expand the SetCC operands into a SELECT node, then it may
1870 // not always be possible to return a true LHS & RHS. In this case, just
1871 // return the value we legalized, returned in the LHS
1872 if (Tmp2.Val == 0) {
1877 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1878 default: assert(0 && "Cannot handle this action for SETCC yet!");
1879 case TargetLowering::Custom:
1882 case TargetLowering::Legal:
1883 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1885 Tmp3 = TLI.LowerOperation(Result, DAG);
1886 if (Tmp3.Val) Result = Tmp3;
1889 case TargetLowering::Promote: {
1890 // First step, figure out the appropriate operation to use.
1891 // Allow SETCC to not be supported for all legal data types
1892 // Mostly this targets FP
1893 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
1894 MVT::ValueType OldVT = NewInTy;
1896 // Scan for the appropriate larger type to use.
1898 NewInTy = (MVT::ValueType)(NewInTy+1);
1900 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
1901 "Fell off of the edge of the integer world");
1902 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
1903 "Fell off of the edge of the floating point world");
1905 // If the target supports SETCC of this type, use it.
1906 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
1909 if (MVT::isInteger(NewInTy))
1910 assert(0 && "Cannot promote Legal Integer SETCC yet");
1912 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
1913 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
1915 Tmp1 = LegalizeOp(Tmp1);
1916 Tmp2 = LegalizeOp(Tmp2);
1917 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1918 Result = LegalizeOp(Result);
1921 case TargetLowering::Expand:
1922 // Expand a setcc node into a select_cc of the same condition, lhs, and
1923 // rhs that selects between const 1 (true) and const 0 (false).
1924 MVT::ValueType VT = Node->getValueType(0);
1925 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
1926 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1927 Node->getOperand(2));
1933 case ISD::MEMMOVE: {
1934 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
1935 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
1937 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
1938 switch (getTypeAction(Node->getOperand(2).getValueType())) {
1939 case Expand: assert(0 && "Cannot expand a byte!");
1941 Tmp3 = LegalizeOp(Node->getOperand(2));
1944 Tmp3 = PromoteOp(Node->getOperand(2));
1948 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
1952 switch (getTypeAction(Node->getOperand(3).getValueType())) {
1954 // Length is too big, just take the lo-part of the length.
1956 ExpandOp(Node->getOperand(3), HiPart, Tmp4);
1960 Tmp4 = LegalizeOp(Node->getOperand(3));
1963 Tmp4 = PromoteOp(Node->getOperand(3));
1968 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
1969 case Expand: assert(0 && "Cannot expand this yet!");
1971 Tmp5 = LegalizeOp(Node->getOperand(4));
1974 Tmp5 = PromoteOp(Node->getOperand(4));
1978 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
1979 default: assert(0 && "This action not implemented for this operation!");
1980 case TargetLowering::Custom:
1983 case TargetLowering::Legal:
1984 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
1986 Tmp1 = TLI.LowerOperation(Result, DAG);
1987 if (Tmp1.Val) Result = Tmp1;
1990 case TargetLowering::Expand: {
1991 // Otherwise, the target does not support this operation. Lower the
1992 // operation to an explicit libcall as appropriate.
1993 MVT::ValueType IntPtr = TLI.getPointerTy();
1994 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
1995 std::vector<std::pair<SDOperand, const Type*> > Args;
1997 const char *FnName = 0;
1998 if (Node->getOpcode() == ISD::MEMSET) {
1999 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2000 // Extend the (previously legalized) ubyte argument to be an int value
2002 if (Tmp3.getValueType() > MVT::i32)
2003 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2005 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2006 Args.push_back(std::make_pair(Tmp3, Type::IntTy));
2007 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2010 } else if (Node->getOpcode() == ISD::MEMCPY ||
2011 Node->getOpcode() == ISD::MEMMOVE) {
2012 Args.push_back(std::make_pair(Tmp2, IntPtrTy));
2013 Args.push_back(std::make_pair(Tmp3, IntPtrTy));
2014 Args.push_back(std::make_pair(Tmp4, IntPtrTy));
2015 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2017 assert(0 && "Unknown op!");
2020 std::pair<SDOperand,SDOperand> CallResult =
2021 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, CallingConv::C, false,
2022 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2023 Result = CallResult.second;
2030 case ISD::SHL_PARTS:
2031 case ISD::SRA_PARTS:
2032 case ISD::SRL_PARTS: {
2033 std::vector<SDOperand> Ops;
2034 bool Changed = false;
2035 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2036 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2037 Changed |= Ops.back() != Node->getOperand(i);
2040 Result = DAG.UpdateNodeOperands(Result, Ops);
2042 switch (TLI.getOperationAction(Node->getOpcode(),
2043 Node->getValueType(0))) {
2044 default: assert(0 && "This action is not supported yet!");
2045 case TargetLowering::Legal: break;
2046 case TargetLowering::Custom:
2047 Tmp1 = TLI.LowerOperation(Result, DAG);
2049 SDOperand Tmp2, RetVal(0, 0);
2050 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2051 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2052 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2056 assert(RetVal.Val && "Illegal result number");
2062 // Since these produce multiple values, make sure to remember that we
2063 // legalized all of them.
2064 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2065 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2066 return Result.getValue(Op.ResNo);
2087 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2088 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2089 case Expand: assert(0 && "Not possible");
2091 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2094 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2100 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2101 default: assert(0 && "BinOp legalize operation not supported");
2102 case TargetLowering::Legal: break;
2103 case TargetLowering::Custom:
2104 Tmp1 = TLI.LowerOperation(Result, DAG);
2105 if (Tmp1.Val) Result = Tmp1;
2107 case TargetLowering::Expand: {
2108 assert(MVT::isVector(Node->getValueType(0)) &&
2109 "Cannot expand this binary operator!");
2110 // Expand the operation into a bunch of nasty scalar code.
2111 std::vector<SDOperand> Ops;
2112 MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
2113 MVT::ValueType PtrVT = TLI.getPointerTy();
2114 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2116 SDOperand Idx = DAG.getConstant(i, PtrVT);
2117 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2118 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2119 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2121 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0), Ops);
2124 case TargetLowering::Promote: {
2125 switch (Node->getOpcode()) {
2126 default: assert(0 && "Do not know how to promote this BinOp!");
2130 MVT::ValueType OVT = Node->getValueType(0);
2131 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2132 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2133 // Bit convert each of the values to the new type.
2134 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2135 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2136 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2137 // Bit convert the result back the original type.
2138 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2146 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2147 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2148 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2149 case Expand: assert(0 && "Not possible");
2151 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2154 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2158 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2160 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2161 default: assert(0 && "Operation not supported");
2162 case TargetLowering::Custom:
2163 Tmp1 = TLI.LowerOperation(Result, DAG);
2164 if (Tmp1.Val) Result = Tmp1;
2166 case TargetLowering::Legal: break;
2167 case TargetLowering::Expand:
2168 // If this target supports fabs/fneg natively, do this efficiently.
2169 if (TLI.isOperationLegal(ISD::FABS, Tmp1.getValueType()) &&
2170 TLI.isOperationLegal(ISD::FNEG, Tmp1.getValueType())) {
2171 // Get the sign bit of the RHS.
2172 MVT::ValueType IVT =
2173 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2174 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2175 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2176 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2177 // Get the absolute value of the result.
2178 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2179 // Select between the nabs and abs value based on the sign bit of
2181 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2182 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2185 Result = LegalizeOp(Result);
2189 // Otherwise, do bitwise ops!
2191 // copysign -> copysignf/copysign libcall.
2193 if (Node->getValueType(0) == MVT::f32) {
2194 FnName = "copysignf";
2195 if (Tmp2.getValueType() != MVT::f32) // Force operands to match type.
2196 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2197 DAG.getNode(ISD::FP_ROUND, MVT::f32, Tmp2));
2199 FnName = "copysign";
2200 if (Tmp2.getValueType() != MVT::f64) // Force operands to match type.
2201 Result = DAG.UpdateNodeOperands(Result, Tmp1,
2202 DAG.getNode(ISD::FP_EXTEND, MVT::f64, Tmp2));
2205 Result = ExpandLibCall(FnName, Node, Dummy);
2212 Tmp1 = LegalizeOp(Node->getOperand(0));
2213 Tmp2 = LegalizeOp(Node->getOperand(1));
2214 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2215 // Since this produces two values, make sure to remember that we legalized
2217 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2218 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2223 Tmp1 = LegalizeOp(Node->getOperand(0));
2224 Tmp2 = LegalizeOp(Node->getOperand(1));
2225 Tmp3 = LegalizeOp(Node->getOperand(2));
2226 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2227 // Since this produces two values, make sure to remember that we legalized
2229 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2230 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2233 case ISD::BUILD_PAIR: {
2234 MVT::ValueType PairTy = Node->getValueType(0);
2235 // TODO: handle the case where the Lo and Hi operands are not of legal type
2236 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2237 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2238 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2239 case TargetLowering::Promote:
2240 case TargetLowering::Custom:
2241 assert(0 && "Cannot promote/custom this yet!");
2242 case TargetLowering::Legal:
2243 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2244 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2246 case TargetLowering::Expand:
2247 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2248 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2249 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2250 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2251 TLI.getShiftAmountTy()));
2252 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2261 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2262 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2264 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2265 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2266 case TargetLowering::Custom:
2269 case TargetLowering::Legal:
2270 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2272 Tmp1 = TLI.LowerOperation(Result, DAG);
2273 if (Tmp1.Val) Result = Tmp1;
2276 case TargetLowering::Expand:
2277 if (MVT::isInteger(Node->getValueType(0))) {
2279 MVT::ValueType VT = Node->getValueType(0);
2280 unsigned Opc = Node->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
2281 Result = DAG.getNode(Opc, VT, Tmp1, Tmp2);
2282 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2283 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2285 // Floating point mod -> fmod libcall.
2286 const char *FnName = Node->getValueType(0) == MVT::f32 ? "fmodf":"fmod";
2288 Result = ExpandLibCall(FnName, Node, Dummy);
2294 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2295 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2297 MVT::ValueType VT = Node->getValueType(0);
2298 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2299 default: assert(0 && "This action is not supported yet!");
2300 case TargetLowering::Custom:
2303 case TargetLowering::Legal:
2304 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2305 Result = Result.getValue(0);
2306 Tmp1 = Result.getValue(1);
2309 Tmp2 = TLI.LowerOperation(Result, DAG);
2311 Result = LegalizeOp(Tmp2);
2312 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2316 case TargetLowering::Expand: {
2317 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2318 Node->getOperand(2));
2319 // Increment the pointer, VAList, to the next vaarg
2320 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2321 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2322 TLI.getPointerTy()));
2323 // Store the incremented VAList to the legalized pointer
2324 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
2325 Node->getOperand(2));
2326 // Load the actual argument out of the pointer VAList
2327 Result = DAG.getLoad(VT, Tmp3, VAList, DAG.getSrcValue(0));
2328 Tmp1 = LegalizeOp(Result.getValue(1));
2329 Result = LegalizeOp(Result);
2333 // Since VAARG produces two values, make sure to remember that we
2334 // legalized both of them.
2335 AddLegalizedOperand(SDOperand(Node, 0), Result);
2336 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2337 return Op.ResNo ? Tmp1 : Result;
2341 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2342 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2343 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2345 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2346 default: assert(0 && "This action is not supported yet!");
2347 case TargetLowering::Custom:
2350 case TargetLowering::Legal:
2351 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2352 Node->getOperand(3), Node->getOperand(4));
2354 Tmp1 = TLI.LowerOperation(Result, DAG);
2355 if (Tmp1.Val) Result = Tmp1;
2358 case TargetLowering::Expand:
2359 // This defaults to loading a pointer from the input and storing it to the
2360 // output, returning the chain.
2361 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, Node->getOperand(3));
2362 Result = DAG.getNode(ISD::STORE, MVT::Other, Tmp4.getValue(1), Tmp4, Tmp2,
2363 Node->getOperand(4));
2369 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2370 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2372 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2373 default: assert(0 && "This action is not supported yet!");
2374 case TargetLowering::Custom:
2377 case TargetLowering::Legal:
2378 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2380 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2381 if (Tmp1.Val) Result = Tmp1;
2384 case TargetLowering::Expand:
2385 Result = Tmp1; // Default to a no-op, return the chain
2391 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2392 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2394 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2396 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2397 default: assert(0 && "This action is not supported yet!");
2398 case TargetLowering::Legal: break;
2399 case TargetLowering::Custom:
2400 Tmp1 = TLI.LowerOperation(Result, DAG);
2401 if (Tmp1.Val) Result = Tmp1;
2408 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2409 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2411 assert(TLI.isOperationLegal(Node->getOpcode(), Node->getValueType(0)) &&
2412 "Cannot handle this yet!");
2413 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2417 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2418 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2419 case TargetLowering::Custom:
2420 assert(0 && "Cannot custom legalize this yet!");
2421 case TargetLowering::Legal:
2422 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2424 case TargetLowering::Promote: {
2425 MVT::ValueType OVT = Tmp1.getValueType();
2426 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2427 unsigned DiffBits = getSizeInBits(NVT) - getSizeInBits(OVT);
2429 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2430 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2431 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2432 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2435 case TargetLowering::Expand:
2436 Result = ExpandBSWAP(Tmp1);
2444 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2445 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2446 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2447 case TargetLowering::Legal:
2448 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2450 case TargetLowering::Promote: {
2451 MVT::ValueType OVT = Tmp1.getValueType();
2452 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2454 // Zero extend the argument.
2455 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2456 // Perform the larger operation, then subtract if needed.
2457 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2458 switch (Node->getOpcode()) {
2463 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2464 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2465 DAG.getConstant(getSizeInBits(NVT), NVT),
2467 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2468 DAG.getConstant(getSizeInBits(OVT),NVT), Tmp1);
2471 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2472 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2473 DAG.getConstant(getSizeInBits(NVT) -
2474 getSizeInBits(OVT), NVT));
2479 case TargetLowering::Expand:
2480 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2491 Tmp1 = LegalizeOp(Node->getOperand(0));
2492 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2493 case TargetLowering::Promote:
2494 case TargetLowering::Custom:
2497 case TargetLowering::Legal:
2498 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2500 Tmp1 = TLI.LowerOperation(Result, DAG);
2501 if (Tmp1.Val) Result = Tmp1;
2504 case TargetLowering::Expand:
2505 switch (Node->getOpcode()) {
2506 default: assert(0 && "Unreachable!");
2508 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2509 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2510 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2513 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2514 MVT::ValueType VT = Node->getValueType(0);
2515 Tmp2 = DAG.getConstantFP(0.0, VT);
2516 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2517 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2518 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2524 MVT::ValueType VT = Node->getValueType(0);
2525 const char *FnName = 0;
2526 switch(Node->getOpcode()) {
2527 case ISD::FSQRT: FnName = VT == MVT::f32 ? "sqrtf" : "sqrt"; break;
2528 case ISD::FSIN: FnName = VT == MVT::f32 ? "sinf" : "sin"; break;
2529 case ISD::FCOS: FnName = VT == MVT::f32 ? "cosf" : "cos"; break;
2530 default: assert(0 && "Unreachable!");
2533 Result = ExpandLibCall(FnName, Node, Dummy);
2541 case ISD::BIT_CONVERT:
2542 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2543 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2545 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2546 Node->getOperand(0).getValueType())) {
2547 default: assert(0 && "Unknown operation action!");
2548 case TargetLowering::Expand:
2549 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2551 case TargetLowering::Legal:
2552 Tmp1 = LegalizeOp(Node->getOperand(0));
2553 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2558 case ISD::VBIT_CONVERT: {
2559 assert(Op.getOperand(0).getValueType() == MVT::Vector &&
2560 "Can only have VBIT_CONVERT where input or output is MVT::Vector!");
2562 // The input has to be a vector type, we have to either scalarize it, pack
2563 // it, or convert it based on whether the input vector type is legal.
2564 SDNode *InVal = Node->getOperand(0).Val;
2566 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
2567 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
2569 // Figure out if there is a Packed type corresponding to this Vector
2570 // type. If so, convert to the packed type.
2571 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2572 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
2573 // Turn this into a bit convert of the packed input.
2574 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2575 PackVectorOp(Node->getOperand(0), TVT));
2577 } else if (NumElems == 1) {
2578 // Turn this into a bit convert of the scalar input.
2579 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2580 PackVectorOp(Node->getOperand(0), EVT));
2583 // FIXME: UNIMP! Store then reload
2584 assert(0 && "Cast from unsupported vector type not implemented yet!");
2588 // Conversion operators. The source and destination have different types.
2589 case ISD::SINT_TO_FP:
2590 case ISD::UINT_TO_FP: {
2591 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2592 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2594 switch (TLI.getOperationAction(Node->getOpcode(),
2595 Node->getOperand(0).getValueType())) {
2596 default: assert(0 && "Unknown operation action!");
2597 case TargetLowering::Custom:
2600 case TargetLowering::Legal:
2601 Tmp1 = LegalizeOp(Node->getOperand(0));
2602 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2604 Tmp1 = TLI.LowerOperation(Result, DAG);
2605 if (Tmp1.Val) Result = Tmp1;
2608 case TargetLowering::Expand:
2609 Result = ExpandLegalINT_TO_FP(isSigned,
2610 LegalizeOp(Node->getOperand(0)),
2611 Node->getValueType(0));
2613 case TargetLowering::Promote:
2614 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2615 Node->getValueType(0),
2621 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2622 Node->getValueType(0), Node->getOperand(0));
2625 Tmp1 = PromoteOp(Node->getOperand(0));
2627 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2628 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2630 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2631 Node->getOperand(0).getValueType());
2633 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2634 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2640 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2642 Tmp1 = LegalizeOp(Node->getOperand(0));
2643 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2646 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2648 // Since the result is legal, we should just be able to truncate the low
2649 // part of the source.
2650 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2653 Result = PromoteOp(Node->getOperand(0));
2654 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2659 case ISD::FP_TO_SINT:
2660 case ISD::FP_TO_UINT:
2661 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2663 Tmp1 = LegalizeOp(Node->getOperand(0));
2665 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2666 default: assert(0 && "Unknown operation action!");
2667 case TargetLowering::Custom:
2670 case TargetLowering::Legal:
2671 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2673 Tmp1 = TLI.LowerOperation(Result, DAG);
2674 if (Tmp1.Val) Result = Tmp1;
2677 case TargetLowering::Promote:
2678 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2679 Node->getOpcode() == ISD::FP_TO_SINT);
2681 case TargetLowering::Expand:
2682 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2683 SDOperand True, False;
2684 MVT::ValueType VT = Node->getOperand(0).getValueType();
2685 MVT::ValueType NVT = Node->getValueType(0);
2686 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2687 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2688 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2689 Node->getOperand(0), Tmp2, ISD::SETLT);
2690 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2691 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2692 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2694 False = DAG.getNode(ISD::XOR, NVT, False,
2695 DAG.getConstant(1ULL << ShiftAmt, NVT));
2696 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2699 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2705 assert(0 && "Shouldn't need to expand other operators here!");
2707 Tmp1 = PromoteOp(Node->getOperand(0));
2708 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
2709 Result = LegalizeOp(Result);
2714 case ISD::ANY_EXTEND:
2715 case ISD::ZERO_EXTEND:
2716 case ISD::SIGN_EXTEND:
2717 case ISD::FP_EXTEND:
2719 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2720 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
2722 Tmp1 = LegalizeOp(Node->getOperand(0));
2723 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2726 switch (Node->getOpcode()) {
2727 case ISD::ANY_EXTEND:
2728 Tmp1 = PromoteOp(Node->getOperand(0));
2729 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
2731 case ISD::ZERO_EXTEND:
2732 Result = PromoteOp(Node->getOperand(0));
2733 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2734 Result = DAG.getZeroExtendInReg(Result,
2735 Node->getOperand(0).getValueType());
2737 case ISD::SIGN_EXTEND:
2738 Result = PromoteOp(Node->getOperand(0));
2739 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
2740 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2742 DAG.getValueType(Node->getOperand(0).getValueType()));
2744 case ISD::FP_EXTEND:
2745 Result = PromoteOp(Node->getOperand(0));
2746 if (Result.getValueType() != Op.getValueType())
2747 // Dynamically dead while we have only 2 FP types.
2748 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
2751 Result = PromoteOp(Node->getOperand(0));
2752 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
2757 case ISD::FP_ROUND_INREG:
2758 case ISD::SIGN_EXTEND_INREG: {
2759 Tmp1 = LegalizeOp(Node->getOperand(0));
2760 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2762 // If this operation is not supported, convert it to a shl/shr or load/store
2764 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
2765 default: assert(0 && "This action not supported for this op yet!");
2766 case TargetLowering::Legal:
2767 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
2769 case TargetLowering::Expand:
2770 // If this is an integer extend and shifts are supported, do that.
2771 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2772 // NOTE: we could fall back on load/store here too for targets without
2773 // SAR. However, it is doubtful that any exist.
2774 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
2775 MVT::getSizeInBits(ExtraVT);
2776 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2777 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
2778 Node->getOperand(0), ShiftCst);
2779 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
2781 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
2782 // The only way we can lower this is to turn it into a STORETRUNC,
2783 // EXTLOAD pair, targetting a temporary location (a stack slot).
2785 // NOTE: there is a choice here between constantly creating new stack
2786 // slots and always reusing the same one. We currently always create
2787 // new ones, as reuse may inhibit scheduling.
2788 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
2789 unsigned TySize = (unsigned)TLI.getTargetData()->getTypeSize(Ty);
2790 unsigned Align = TLI.getTargetData()->getTypeAlignment(Ty);
2791 MachineFunction &MF = DAG.getMachineFunction();
2793 MF.getFrameInfo()->CreateStackObject((unsigned)TySize, Align);
2794 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
2795 Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
2796 Node->getOperand(0), StackSlot,
2797 DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
2798 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
2799 Result, StackSlot, DAG.getSrcValue(NULL),
2802 assert(0 && "Unknown op");
2810 assert(Result.getValueType() == Op.getValueType() &&
2811 "Bad legalization!");
2813 // Make sure that the generated code is itself legal.
2815 Result = LegalizeOp(Result);
2817 // Note that LegalizeOp may be reentered even from single-use nodes, which
2818 // means that we always must cache transformed nodes.
2819 AddLegalizedOperand(Op, Result);
2823 /// PromoteOp - Given an operation that produces a value in an invalid type,
2824 /// promote it to compute the value into a larger type. The produced value will
2825 /// have the correct bits for the low portion of the register, but no guarantee
2826 /// is made about the top bits: it may be zero, sign-extended, or garbage.
2827 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
2828 MVT::ValueType VT = Op.getValueType();
2829 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
2830 assert(getTypeAction(VT) == Promote &&
2831 "Caller should expand or legalize operands that are not promotable!");
2832 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
2833 "Cannot promote to smaller type!");
2835 SDOperand Tmp1, Tmp2, Tmp3;
2837 SDNode *Node = Op.Val;
2839 std::map<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
2840 if (I != PromotedNodes.end()) return I->second;
2842 switch (Node->getOpcode()) {
2843 case ISD::CopyFromReg:
2844 assert(0 && "CopyFromReg must be legal!");
2846 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
2847 assert(0 && "Do not know how to promote this operator!");
2850 Result = DAG.getNode(ISD::UNDEF, NVT);
2854 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
2856 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
2857 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
2859 case ISD::ConstantFP:
2860 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
2861 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
2865 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
2866 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
2867 Node->getOperand(1), Node->getOperand(2));
2871 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2873 Result = LegalizeOp(Node->getOperand(0));
2874 assert(Result.getValueType() >= NVT &&
2875 "This truncation doesn't make sense!");
2876 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
2877 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
2880 // The truncation is not required, because we don't guarantee anything
2881 // about high bits anyway.
2882 Result = PromoteOp(Node->getOperand(0));
2885 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2886 // Truncate the low part of the expanded value to the result type
2887 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
2890 case ISD::SIGN_EXTEND:
2891 case ISD::ZERO_EXTEND:
2892 case ISD::ANY_EXTEND:
2893 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2894 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
2896 // Input is legal? Just do extend all the way to the larger type.
2897 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2900 // Promote the reg if it's smaller.
2901 Result = PromoteOp(Node->getOperand(0));
2902 // The high bits are not guaranteed to be anything. Insert an extend.
2903 if (Node->getOpcode() == ISD::SIGN_EXTEND)
2904 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2905 DAG.getValueType(Node->getOperand(0).getValueType()));
2906 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
2907 Result = DAG.getZeroExtendInReg(Result,
2908 Node->getOperand(0).getValueType());
2912 case ISD::BIT_CONVERT:
2913 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2914 Result = PromoteOp(Result);
2917 case ISD::FP_EXTEND:
2918 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
2920 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2921 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
2922 case Promote: assert(0 && "Unreachable with 2 FP types!");
2924 // Input is legal? Do an FP_ROUND_INREG.
2925 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
2926 DAG.getValueType(VT));
2931 case ISD::SINT_TO_FP:
2932 case ISD::UINT_TO_FP:
2933 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2935 // No extra round required here.
2936 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
2940 Result = PromoteOp(Node->getOperand(0));
2941 if (Node->getOpcode() == ISD::SINT_TO_FP)
2942 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
2944 DAG.getValueType(Node->getOperand(0).getValueType()));
2946 Result = DAG.getZeroExtendInReg(Result,
2947 Node->getOperand(0).getValueType());
2948 // No extra round required here.
2949 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
2952 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
2953 Node->getOperand(0));
2954 // Round if we cannot tolerate excess precision.
2955 if (NoExcessFPPrecision)
2956 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
2957 DAG.getValueType(VT));
2962 case ISD::SIGN_EXTEND_INREG:
2963 Result = PromoteOp(Node->getOperand(0));
2964 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
2965 Node->getOperand(1));
2967 case ISD::FP_TO_SINT:
2968 case ISD::FP_TO_UINT:
2969 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2971 Tmp1 = Node->getOperand(0);
2974 // The input result is prerounded, so we don't have to do anything
2976 Tmp1 = PromoteOp(Node->getOperand(0));
2979 assert(0 && "not implemented");
2981 // If we're promoting a UINT to a larger size, check to see if the new node
2982 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
2983 // we can use that instead. This allows us to generate better code for
2984 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
2985 // legal, such as PowerPC.
2986 if (Node->getOpcode() == ISD::FP_TO_UINT &&
2987 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
2988 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
2989 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
2990 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
2992 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
2998 Tmp1 = PromoteOp(Node->getOperand(0));
2999 assert(Tmp1.getValueType() == NVT);
3000 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3001 // NOTE: we do not have to do any extra rounding here for
3002 // NoExcessFPPrecision, because we know the input will have the appropriate
3003 // precision, and these operations don't modify precision at all.
3009 Tmp1 = PromoteOp(Node->getOperand(0));
3010 assert(Tmp1.getValueType() == NVT);
3011 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3012 if (NoExcessFPPrecision)
3013 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3014 DAG.getValueType(VT));
3023 // The input may have strange things in the top bits of the registers, but
3024 // these operations don't care. They may have weird bits going out, but
3025 // that too is okay if they are integer operations.
3026 Tmp1 = PromoteOp(Node->getOperand(0));
3027 Tmp2 = PromoteOp(Node->getOperand(1));
3028 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3029 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3034 Tmp1 = PromoteOp(Node->getOperand(0));
3035 Tmp2 = PromoteOp(Node->getOperand(1));
3036 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3037 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3039 // Floating point operations will give excess precision that we may not be
3040 // able to tolerate. If we DO allow excess precision, just leave it,
3041 // otherwise excise it.
3042 // FIXME: Why would we need to round FP ops more than integer ones?
3043 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3044 if (NoExcessFPPrecision)
3045 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3046 DAG.getValueType(VT));
3051 // These operators require that their input be sign extended.
3052 Tmp1 = PromoteOp(Node->getOperand(0));
3053 Tmp2 = PromoteOp(Node->getOperand(1));
3054 if (MVT::isInteger(NVT)) {
3055 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3056 DAG.getValueType(VT));
3057 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3058 DAG.getValueType(VT));
3060 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3062 // Perform FP_ROUND: this is probably overly pessimistic.
3063 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3064 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3065 DAG.getValueType(VT));
3069 case ISD::FCOPYSIGN:
3070 // These operators require that their input be fp extended.
3071 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3073 Tmp1 = LegalizeOp(Node->getOperand(0));
3076 Tmp1 = PromoteOp(Node->getOperand(0));
3079 assert(0 && "not implemented");
3081 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3083 Tmp2 = LegalizeOp(Node->getOperand(1));
3086 Tmp2 = PromoteOp(Node->getOperand(1));
3089 assert(0 && "not implemented");
3091 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3093 // Perform FP_ROUND: this is probably overly pessimistic.
3094 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3095 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3096 DAG.getValueType(VT));
3101 // These operators require that their input be zero extended.
3102 Tmp1 = PromoteOp(Node->getOperand(0));
3103 Tmp2 = PromoteOp(Node->getOperand(1));
3104 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3105 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3106 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3107 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3111 Tmp1 = PromoteOp(Node->getOperand(0));
3112 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3115 // The input value must be properly sign extended.
3116 Tmp1 = PromoteOp(Node->getOperand(0));
3117 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3118 DAG.getValueType(VT));
3119 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3122 // The input value must be properly zero extended.
3123 Tmp1 = PromoteOp(Node->getOperand(0));
3124 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3125 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3129 Tmp1 = Node->getOperand(0); // Get the chain.
3130 Tmp2 = Node->getOperand(1); // Get the pointer.
3131 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3132 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3133 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3135 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3136 Node->getOperand(2));
3137 // Increment the pointer, VAList, to the next vaarg
3138 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3139 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3140 TLI.getPointerTy()));
3141 // Store the incremented VAList to the legalized pointer
3142 Tmp3 = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), Tmp3, Tmp2,
3143 Node->getOperand(2));
3144 // Load the actual argument out of the pointer VAList
3145 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList,
3146 DAG.getSrcValue(0), VT);
3148 // Remember that we legalized the chain.
3149 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3153 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Node->getOperand(0),
3154 Node->getOperand(1), Node->getOperand(2), VT);
3155 // Remember that we legalized the chain.
3156 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3161 Result = DAG.getExtLoad(Node->getOpcode(), NVT, Node->getOperand(0),
3162 Node->getOperand(1), Node->getOperand(2),
3163 cast<VTSDNode>(Node->getOperand(3))->getVT());
3164 // Remember that we legalized the chain.
3165 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3168 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3169 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3170 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3172 case ISD::SELECT_CC:
3173 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3174 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3175 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3176 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3179 Tmp1 = Node->getOperand(0);
3180 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3181 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3182 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3183 DAG.getConstant(getSizeInBits(NVT) - getSizeInBits(VT),
3184 TLI.getShiftAmountTy()));
3189 // Zero extend the argument
3190 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3191 // Perform the larger operation, then subtract if needed.
3192 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3193 switch(Node->getOpcode()) {
3198 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3199 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3200 DAG.getConstant(getSizeInBits(NVT), NVT), ISD::SETEQ);
3201 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3202 DAG.getConstant(getSizeInBits(VT), NVT), Tmp1);
3205 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3206 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3207 DAG.getConstant(getSizeInBits(NVT) -
3208 getSizeInBits(VT), NVT));
3212 case ISD::VEXTRACT_VECTOR_ELT:
3213 Result = PromoteOp(LowerVEXTRACT_VECTOR_ELT(Op));
3215 case ISD::EXTRACT_VECTOR_ELT:
3216 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3220 assert(Result.Val && "Didn't set a result!");
3222 // Make sure the result is itself legal.
3223 Result = LegalizeOp(Result);
3225 // Remember that we promoted this!
3226 AddPromotedOperand(Op, Result);
3230 /// LowerVEXTRACT_VECTOR_ELT - Lower a VEXTRACT_VECTOR_ELT operation into a
3231 /// EXTRACT_VECTOR_ELT operation, to memory operations, or to scalar code based
3232 /// on the vector type. The return type of this matches the element type of the
3233 /// vector, which may not be legal for the target.
3234 SDOperand SelectionDAGLegalize::LowerVEXTRACT_VECTOR_ELT(SDOperand Op) {
3235 // We know that operand #0 is the Vec vector. If the index is a constant
3236 // or if the invec is a supported hardware type, we can use it. Otherwise,
3237 // lower to a store then an indexed load.
3238 SDOperand Vec = Op.getOperand(0);
3239 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3241 SDNode *InVal = Vec.Val;
3242 unsigned NumElems = cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
3243 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
3245 // Figure out if there is a Packed type corresponding to this Vector
3246 // type. If so, convert to the packed type.
3247 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
3248 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
3249 // Turn this into a packed extract_vector_elt operation.
3250 Vec = PackVectorOp(Vec, TVT);
3251 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, Op.getValueType(), Vec, Idx);
3252 } else if (NumElems == 1) {
3253 // This must be an access of the only element. Return it.
3254 return PackVectorOp(Vec, EVT);
3255 } else if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
3257 SplitVectorOp(Vec, Lo, Hi);
3258 if (CIdx->getValue() < NumElems/2) {
3262 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3265 // It's now an extract from the appropriate high or low part. Recurse.
3266 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3267 return LowerVEXTRACT_VECTOR_ELT(Op);
3269 // Variable index case for extract element.
3270 // FIXME: IMPLEMENT STORE/LOAD lowering. Need alignment of stack slot!!
3271 assert(0 && "unimp!");
3276 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3278 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3279 SDOperand Vector = Op.getOperand(0);
3280 SDOperand Idx = Op.getOperand(1);
3282 // If the target doesn't support this, store the value to a temporary
3283 // stack slot, then LOAD the scalar element back out.
3284 SDOperand StackPtr = CreateStackTemporary(Vector.getValueType());
3285 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3286 Vector, StackPtr, DAG.getSrcValue(NULL));
3288 // Add the offset to the index.
3289 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3290 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3291 DAG.getConstant(EltSize, Idx.getValueType()));
3292 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3294 return DAG.getLoad(Op.getValueType(), Ch, StackPtr, DAG.getSrcValue(NULL));
3298 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3299 /// with condition CC on the current target. This usually involves legalizing
3300 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3301 /// there may be no choice but to create a new SetCC node to represent the
3302 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3303 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3304 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3307 SDOperand Tmp1, Tmp2, Result;
3309 switch (getTypeAction(LHS.getValueType())) {
3311 Tmp1 = LegalizeOp(LHS); // LHS
3312 Tmp2 = LegalizeOp(RHS); // RHS
3315 Tmp1 = PromoteOp(LHS); // LHS
3316 Tmp2 = PromoteOp(RHS); // RHS
3318 // If this is an FP compare, the operands have already been extended.
3319 if (MVT::isInteger(LHS.getValueType())) {
3320 MVT::ValueType VT = LHS.getValueType();
3321 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3323 // Otherwise, we have to insert explicit sign or zero extends. Note
3324 // that we could insert sign extends for ALL conditions, but zero extend
3325 // is cheaper on many machines (an AND instead of two shifts), so prefer
3327 switch (cast<CondCodeSDNode>(CC)->get()) {
3328 default: assert(0 && "Unknown integer comparison!");
3335 // ALL of these operations will work if we either sign or zero extend
3336 // the operands (including the unsigned comparisons!). Zero extend is
3337 // usually a simpler/cheaper operation, so prefer it.
3338 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3339 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3345 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3346 DAG.getValueType(VT));
3347 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3348 DAG.getValueType(VT));
3354 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3355 ExpandOp(LHS, LHSLo, LHSHi);
3356 ExpandOp(RHS, RHSLo, RHSHi);
3357 switch (cast<CondCodeSDNode>(CC)->get()) {
3361 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3362 if (RHSCST->isAllOnesValue()) {
3363 // Comparison to -1.
3364 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3369 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3370 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3371 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3372 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3375 // If this is a comparison of the sign bit, just look at the top part.
3377 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3378 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3379 CST->getValue() == 0) || // X < 0
3380 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3381 CST->isAllOnesValue())) { // X > -1
3387 // FIXME: This generated code sucks.
3388 ISD::CondCode LowCC;
3389 switch (cast<CondCodeSDNode>(CC)->get()) {
3390 default: assert(0 && "Unknown integer setcc!");
3392 case ISD::SETULT: LowCC = ISD::SETULT; break;
3394 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3396 case ISD::SETULE: LowCC = ISD::SETULE; break;
3398 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3401 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3402 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3403 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3405 // NOTE: on targets without efficient SELECT of bools, we can always use
3406 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3407 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3408 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3409 Result = DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3410 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3411 Result, Tmp1, Tmp2));
3420 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3421 /// The resultant code need not be legal. Note that SrcOp is the input operand
3422 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3423 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3425 // Create the stack frame object.
3426 SDOperand FIPtr = CreateStackTemporary(DestVT);
3428 // Emit a store to the stack slot.
3429 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3430 SrcOp, FIPtr, DAG.getSrcValue(NULL));
3431 // Result is a load from the stack slot.
3432 return DAG.getLoad(DestVT, Store, FIPtr, DAG.getSrcValue(0));
3435 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3436 // Create a vector sized/aligned stack slot, store the value to element #0,
3437 // then load the whole vector back out.
3438 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3439 SDOperand Ch = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3440 Node->getOperand(0), StackPtr,
3441 DAG.getSrcValue(NULL));
3442 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr,DAG.getSrcValue(NULL));
3446 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3447 /// support the operation, but do support the resultant packed vector type.
3448 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3450 // If the only non-undef value is the low element, turn this into a
3451 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3452 unsigned NumElems = Node->getNumOperands();
3453 bool isOnlyLowElement = true;
3454 SDOperand SplatValue = Node->getOperand(0);
3455 std::map<SDOperand, std::vector<unsigned> > Values;
3456 Values[SplatValue].push_back(0);
3457 bool isConstant = true;
3458 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3459 SplatValue.getOpcode() != ISD::UNDEF)
3462 for (unsigned i = 1; i < NumElems; ++i) {
3463 SDOperand V = Node->getOperand(i);
3464 Values[V].push_back(i);
3465 if (V.getOpcode() != ISD::UNDEF)
3466 isOnlyLowElement = false;
3467 if (SplatValue != V)
3468 SplatValue = SDOperand(0,0);
3470 // If this isn't a constant element or an undef, we can't use a constant
3472 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3473 V.getOpcode() != ISD::UNDEF)
3477 if (isOnlyLowElement) {
3478 // If the low element is an undef too, then this whole things is an undef.
3479 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3480 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3481 // Otherwise, turn this into a scalar_to_vector node.
3482 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3483 Node->getOperand(0));
3486 // If all elements are constants, create a load from the constant pool.
3488 MVT::ValueType VT = Node->getValueType(0);
3490 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3491 std::vector<Constant*> CV;
3492 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3493 if (ConstantFPSDNode *V =
3494 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3495 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3496 } else if (ConstantSDNode *V =
3497 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3498 CV.push_back(ConstantUInt::get(OpNTy, V->getValue()));
3500 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3501 CV.push_back(UndefValue::get(OpNTy));
3504 Constant *CP = ConstantPacked::get(CV);
3505 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3506 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
3507 DAG.getSrcValue(NULL));
3510 if (SplatValue.Val) { // Splat of one value?
3511 // Build the shuffle constant vector: <0, 0, 0, 0>
3512 MVT::ValueType MaskVT =
3513 MVT::getIntVectorWithNumElements(NumElems);
3514 SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
3515 std::vector<SDOperand> ZeroVec(NumElems, Zero);
3516 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, ZeroVec);
3518 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3519 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
3520 // Get the splatted value into the low element of a vector register.
3521 SDOperand LowValVec =
3522 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
3524 // Return shuffle(LowValVec, undef, <0,0,0,0>)
3525 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
3526 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
3531 // If there are only two unique elements, we may be able to turn this into a
3533 if (Values.size() == 2) {
3534 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
3535 MVT::ValueType MaskVT =
3536 MVT::getIntVectorWithNumElements(NumElems);
3537 std::vector<SDOperand> MaskVec(NumElems);
3539 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3540 E = Values.end(); I != E; ++I) {
3541 for (std::vector<unsigned>::iterator II = I->second.begin(),
3542 EE = I->second.end(); II != EE; ++II)
3543 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
3546 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
3548 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
3549 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
3550 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
3551 std::vector<SDOperand> Ops;
3552 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
3553 E = Values.end(); I != E; ++I) {
3554 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3558 Ops.push_back(ShuffleMask);
3560 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
3561 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), Ops);
3565 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
3566 // aligned object on the stack, store each element into it, then load
3567 // the result as a vector.
3568 MVT::ValueType VT = Node->getValueType(0);
3569 // Create the stack frame object.
3570 SDOperand FIPtr = CreateStackTemporary(VT);
3572 // Emit a store of each element to the stack slot.
3573 std::vector<SDOperand> Stores;
3574 unsigned TypeByteSize =
3575 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
3576 unsigned VectorSize = MVT::getSizeInBits(VT)/8;
3577 // Store (in the right endianness) the elements to memory.
3578 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3579 // Ignore undef elements.
3580 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
3582 unsigned Offset = TypeByteSize*i;
3584 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
3585 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
3587 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3588 Node->getOperand(i), Idx,
3589 DAG.getSrcValue(NULL)));
3592 SDOperand StoreChain;
3593 if (!Stores.empty()) // Not all undef elements?
3594 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
3596 StoreChain = DAG.getEntryNode();
3598 // Result is a load from the stack slot.
3599 return DAG.getLoad(VT, StoreChain, FIPtr, DAG.getSrcValue(0));
3602 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
3603 /// specified value type.
3604 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
3605 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3606 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
3607 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, ByteSize);
3608 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
3611 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
3612 SDOperand Op, SDOperand Amt,
3613 SDOperand &Lo, SDOperand &Hi) {
3614 // Expand the subcomponents.
3615 SDOperand LHSL, LHSH;
3616 ExpandOp(Op, LHSL, LHSH);
3618 std::vector<SDOperand> Ops;
3619 Ops.push_back(LHSL);
3620 Ops.push_back(LHSH);
3622 std::vector<MVT::ValueType> VTs(2, LHSL.getValueType());
3623 Lo = DAG.getNode(NodeOp, VTs, Ops);
3624 Hi = Lo.getValue(1);
3628 /// ExpandShift - Try to find a clever way to expand this shift operation out to
3629 /// smaller elements. If we can't find a way that is more efficient than a
3630 /// libcall on this target, return false. Otherwise, return true with the
3631 /// low-parts expanded into Lo and Hi.
3632 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
3633 SDOperand &Lo, SDOperand &Hi) {
3634 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
3635 "This is not a shift!");
3637 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
3638 SDOperand ShAmt = LegalizeOp(Amt);
3639 MVT::ValueType ShTy = ShAmt.getValueType();
3640 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
3641 unsigned NVTBits = MVT::getSizeInBits(NVT);
3643 // Handle the case when Amt is an immediate. Other cases are currently broken
3644 // and are disabled.
3645 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
3646 unsigned Cst = CN->getValue();
3647 // Expand the incoming operand to be shifted, so that we have its parts
3649 ExpandOp(Op, InL, InH);
3653 Lo = DAG.getConstant(0, NVT);
3654 Hi = DAG.getConstant(0, NVT);
3655 } else if (Cst > NVTBits) {
3656 Lo = DAG.getConstant(0, NVT);
3657 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
3658 } else if (Cst == NVTBits) {
3659 Lo = DAG.getConstant(0, NVT);
3662 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
3663 Hi = DAG.getNode(ISD::OR, NVT,
3664 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
3665 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
3670 Lo = DAG.getConstant(0, NVT);
3671 Hi = DAG.getConstant(0, NVT);
3672 } else if (Cst > NVTBits) {
3673 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
3674 Hi = DAG.getConstant(0, NVT);
3675 } else if (Cst == NVTBits) {
3677 Hi = DAG.getConstant(0, NVT);
3679 Lo = DAG.getNode(ISD::OR, NVT,
3680 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3681 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3682 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
3687 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
3688 DAG.getConstant(NVTBits-1, ShTy));
3689 } else if (Cst > NVTBits) {
3690 Lo = DAG.getNode(ISD::SRA, NVT, InH,
3691 DAG.getConstant(Cst-NVTBits, ShTy));
3692 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3693 DAG.getConstant(NVTBits-1, ShTy));
3694 } else if (Cst == NVTBits) {
3696 Hi = DAG.getNode(ISD::SRA, NVT, InH,
3697 DAG.getConstant(NVTBits-1, ShTy));
3699 Lo = DAG.getNode(ISD::OR, NVT,
3700 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
3701 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
3702 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
3711 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
3712 // does not fit into a register, return the lo part and set the hi part to the
3713 // by-reg argument. If it does fit into a single register, return the result
3714 // and leave the Hi part unset.
3715 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
3717 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
3718 // The input chain to this libcall is the entry node of the function.
3719 // Legalizing the call will automatically add the previous call to the
3721 SDOperand InChain = DAG.getEntryNode();
3723 TargetLowering::ArgListTy Args;
3724 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
3725 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
3726 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
3727 Args.push_back(std::make_pair(Node->getOperand(i), ArgTy));
3729 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
3731 // Splice the libcall in wherever FindInputOutputChains tells us to.
3732 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
3733 std::pair<SDOperand,SDOperand> CallInfo =
3734 TLI.LowerCallTo(InChain, RetTy, false, CallingConv::C, false,
3737 // Legalize the call sequence, starting with the chain. This will advance
3738 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
3739 // was added by LowerCallTo (guaranteeing proper serialization of calls).
3740 LegalizeOp(CallInfo.second);
3742 switch (getTypeAction(CallInfo.first.getValueType())) {
3743 default: assert(0 && "Unknown thing");
3745 Result = CallInfo.first;
3748 ExpandOp(CallInfo.first, Result, Hi);
3755 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation, assuming that the
3756 /// destination type is legal.
3757 SDOperand SelectionDAGLegalize::
3758 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
3759 assert(isTypeLegal(DestTy) && "Destination type is not legal!");
3760 assert(getTypeAction(Source.getValueType()) == Expand &&
3761 "This is not an expansion!");
3762 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
3765 assert(Source.getValueType() == MVT::i64 &&
3766 "This only works for 64-bit -> FP");
3767 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
3768 // incoming integer is set. To handle this, we dynamically test to see if
3769 // it is set, and, if so, add a fudge factor.
3771 ExpandOp(Source, Lo, Hi);
3773 // If this is unsigned, and not supported, first perform the conversion to
3774 // signed, then adjust the result if the sign bit is set.
3775 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
3776 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
3778 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
3779 DAG.getConstant(0, Hi.getValueType()),
3781 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3782 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3783 SignSet, Four, Zero);
3784 uint64_t FF = 0x5f800000ULL;
3785 if (TLI.isLittleEndian()) FF <<= 32;
3786 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3788 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3789 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3790 SDOperand FudgeInReg;
3791 if (DestTy == MVT::f32)
3792 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3793 DAG.getSrcValue(NULL));
3795 assert(DestTy == MVT::f64 && "Unexpected conversion");
3796 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
3797 CPIdx, DAG.getSrcValue(NULL), MVT::f32);
3799 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
3802 // Check to see if the target has a custom way to lower this. If so, use it.
3803 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
3804 default: assert(0 && "This action not implemented for this operation!");
3805 case TargetLowering::Legal:
3806 case TargetLowering::Expand:
3807 break; // This case is handled below.
3808 case TargetLowering::Custom: {
3809 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
3812 return LegalizeOp(NV);
3813 break; // The target decided this was legal after all
3817 // Expand the source, then glue it back together for the call. We must expand
3818 // the source in case it is shared (this pass of legalize must traverse it).
3819 SDOperand SrcLo, SrcHi;
3820 ExpandOp(Source, SrcLo, SrcHi);
3821 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
3823 const char *FnName = 0;
3824 if (DestTy == MVT::f32)
3825 FnName = "__floatdisf";
3827 assert(DestTy == MVT::f64 && "Unknown fp value type!");
3828 FnName = "__floatdidf";
3831 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
3832 SDOperand UnusedHiPart;
3833 return ExpandLibCall(FnName, Source.Val, UnusedHiPart);
3836 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
3837 /// INT_TO_FP operation of the specified operand when the target requests that
3838 /// we expand it. At this point, we know that the result and operand types are
3839 /// legal for the target.
3840 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
3842 MVT::ValueType DestVT) {
3843 if (Op0.getValueType() == MVT::i32) {
3844 // simple 32-bit [signed|unsigned] integer to float/double expansion
3846 // get the stack frame index of a 8 byte buffer
3847 MachineFunction &MF = DAG.getMachineFunction();
3848 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
3849 // get address of 8 byte buffer
3850 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3851 // word offset constant for Hi/Lo address computation
3852 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
3853 // set up Hi and Lo (into buffer) address based on endian
3854 SDOperand Hi = StackSlot;
3855 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
3856 if (TLI.isLittleEndian())
3859 // if signed map to unsigned space
3860 SDOperand Op0Mapped;
3862 // constant used to invert sign bit (signed to unsigned mapping)
3863 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
3864 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
3868 // store the lo of the constructed double - based on integer input
3869 SDOperand Store1 = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
3870 Op0Mapped, Lo, DAG.getSrcValue(NULL));
3871 // initial hi portion of constructed double
3872 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
3873 // store the hi of the constructed double - biased exponent
3874 SDOperand Store2 = DAG.getNode(ISD::STORE, MVT::Other, Store1,
3875 InitialHi, Hi, DAG.getSrcValue(NULL));
3876 // load the constructed double
3877 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot,
3878 DAG.getSrcValue(NULL));
3879 // FP constant to bias correct the final result
3880 SDOperand Bias = DAG.getConstantFP(isSigned ?
3881 BitsToDouble(0x4330000080000000ULL)
3882 : BitsToDouble(0x4330000000000000ULL),
3884 // subtract the bias
3885 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
3888 // handle final rounding
3889 if (DestVT == MVT::f64) {
3893 // if f32 then cast to f32
3894 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
3898 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
3899 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
3901 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
3902 DAG.getConstant(0, Op0.getValueType()),
3904 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
3905 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
3906 SignSet, Four, Zero);
3908 // If the sign bit of the integer is set, the large number will be treated
3909 // as a negative number. To counteract this, the dynamic code adds an
3910 // offset depending on the data type.
3912 switch (Op0.getValueType()) {
3913 default: assert(0 && "Unsupported integer type!");
3914 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
3915 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
3916 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
3917 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
3919 if (TLI.isLittleEndian()) FF <<= 32;
3920 static Constant *FudgeFactor = ConstantUInt::get(Type::ULongTy, FF);
3922 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
3923 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
3924 SDOperand FudgeInReg;
3925 if (DestVT == MVT::f32)
3926 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx,
3927 DAG.getSrcValue(NULL));
3929 assert(DestVT == MVT::f64 && "Unexpected conversion");
3930 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
3931 DAG.getEntryNode(), CPIdx,
3932 DAG.getSrcValue(NULL), MVT::f32));
3935 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
3938 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
3939 /// *INT_TO_FP operation of the specified operand when the target requests that
3940 /// we promote it. At this point, we know that the result and operand types are
3941 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
3942 /// operation that takes a larger input.
3943 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
3944 MVT::ValueType DestVT,
3946 // First step, figure out the appropriate *INT_TO_FP operation to use.
3947 MVT::ValueType NewInTy = LegalOp.getValueType();
3949 unsigned OpToUse = 0;
3951 // Scan for the appropriate larger type to use.
3953 NewInTy = (MVT::ValueType)(NewInTy+1);
3954 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
3956 // If the target supports SINT_TO_FP of this type, use it.
3957 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
3959 case TargetLowering::Legal:
3960 if (!TLI.isTypeLegal(NewInTy))
3961 break; // Can't use this datatype.
3963 case TargetLowering::Custom:
3964 OpToUse = ISD::SINT_TO_FP;
3968 if (isSigned) continue;
3970 // If the target supports UINT_TO_FP of this type, use it.
3971 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
3973 case TargetLowering::Legal:
3974 if (!TLI.isTypeLegal(NewInTy))
3975 break; // Can't use this datatype.
3977 case TargetLowering::Custom:
3978 OpToUse = ISD::UINT_TO_FP;
3983 // Otherwise, try a larger type.
3986 // Okay, we found the operation and type to use. Zero extend our input to the
3987 // desired type then run the operation on it.
3988 return DAG.getNode(OpToUse, DestVT,
3989 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
3993 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
3994 /// FP_TO_*INT operation of the specified operand when the target requests that
3995 /// we promote it. At this point, we know that the result and operand types are
3996 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
3997 /// operation that returns a larger result.
3998 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
3999 MVT::ValueType DestVT,
4001 // First step, figure out the appropriate FP_TO*INT operation to use.
4002 MVT::ValueType NewOutTy = DestVT;
4004 unsigned OpToUse = 0;
4006 // Scan for the appropriate larger type to use.
4008 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4009 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4011 // If the target supports FP_TO_SINT returning this type, use it.
4012 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4014 case TargetLowering::Legal:
4015 if (!TLI.isTypeLegal(NewOutTy))
4016 break; // Can't use this datatype.
4018 case TargetLowering::Custom:
4019 OpToUse = ISD::FP_TO_SINT;
4024 // If the target supports FP_TO_UINT of this type, use it.
4025 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4027 case TargetLowering::Legal:
4028 if (!TLI.isTypeLegal(NewOutTy))
4029 break; // Can't use this datatype.
4031 case TargetLowering::Custom:
4032 OpToUse = ISD::FP_TO_UINT;
4037 // Otherwise, try a larger type.
4040 // Okay, we found the operation and type to use. Truncate the result of the
4041 // extended FP_TO_*INT operation to the desired size.
4042 return DAG.getNode(ISD::TRUNCATE, DestVT,
4043 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4046 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4048 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4049 MVT::ValueType VT = Op.getValueType();
4050 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4051 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4053 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4055 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4056 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4057 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4059 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4060 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4061 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4062 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4063 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4064 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4065 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4066 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4067 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4069 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4070 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4071 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4072 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4073 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4074 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4075 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4076 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4077 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4078 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4079 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4080 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4081 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4082 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4083 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4084 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4085 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4086 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4087 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4088 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4089 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4093 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4095 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4097 default: assert(0 && "Cannot expand this yet!");
4099 static const uint64_t mask[6] = {
4100 0x5555555555555555ULL, 0x3333333333333333ULL,
4101 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4102 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4104 MVT::ValueType VT = Op.getValueType();
4105 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4106 unsigned len = getSizeInBits(VT);
4107 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4108 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4109 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4110 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4111 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4112 DAG.getNode(ISD::AND, VT,
4113 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4118 // for now, we do this:
4119 // x = x | (x >> 1);
4120 // x = x | (x >> 2);
4122 // x = x | (x >>16);
4123 // x = x | (x >>32); // for 64-bit input
4124 // return popcount(~x);
4126 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4127 MVT::ValueType VT = Op.getValueType();
4128 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4129 unsigned len = getSizeInBits(VT);
4130 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4131 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4132 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4134 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4135 return DAG.getNode(ISD::CTPOP, VT, Op);
4138 // for now, we use: { return popcount(~x & (x - 1)); }
4139 // unless the target has ctlz but not ctpop, in which case we use:
4140 // { return 32 - nlz(~x & (x-1)); }
4141 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4142 MVT::ValueType VT = Op.getValueType();
4143 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4144 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4145 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4146 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4147 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4148 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4149 TLI.isOperationLegal(ISD::CTLZ, VT))
4150 return DAG.getNode(ISD::SUB, VT,
4151 DAG.getConstant(getSizeInBits(VT), VT),
4152 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4153 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4158 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4159 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4160 /// LegalizeNodes map is filled in for any results that are not expanded, the
4161 /// ExpandedNodes map is filled in for any results that are expanded, and the
4162 /// Lo/Hi values are returned.
4163 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4164 MVT::ValueType VT = Op.getValueType();
4165 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4166 SDNode *Node = Op.Val;
4167 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4168 assert((MVT::isInteger(VT) || VT == MVT::Vector) &&
4169 "Cannot expand FP values!");
4170 assert(((MVT::isInteger(NVT) && NVT < VT) || VT == MVT::Vector) &&
4171 "Cannot expand to FP value or to larger int value!");
4173 // See if we already expanded it.
4174 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4175 = ExpandedNodes.find(Op);
4176 if (I != ExpandedNodes.end()) {
4177 Lo = I->second.first;
4178 Hi = I->second.second;
4182 switch (Node->getOpcode()) {
4183 case ISD::CopyFromReg:
4184 assert(0 && "CopyFromReg must be legal!");
4186 std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
4187 assert(0 && "Do not know how to expand this operator!");
4190 Lo = DAG.getNode(ISD::UNDEF, NVT);
4191 Hi = DAG.getNode(ISD::UNDEF, NVT);
4193 case ISD::Constant: {
4194 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4195 Lo = DAG.getConstant(Cst, NVT);
4196 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4199 case ISD::BUILD_PAIR:
4200 // Return the operands.
4201 Lo = Node->getOperand(0);
4202 Hi = Node->getOperand(1);
4205 case ISD::SIGN_EXTEND_INREG:
4206 ExpandOp(Node->getOperand(0), Lo, Hi);
4207 // Sign extend the lo-part.
4208 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4209 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4210 TLI.getShiftAmountTy()));
4211 // sext_inreg the low part if needed.
4212 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4216 ExpandOp(Node->getOperand(0), Lo, Hi);
4217 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4218 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4224 ExpandOp(Node->getOperand(0), Lo, Hi);
4225 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4226 DAG.getNode(ISD::CTPOP, NVT, Lo),
4227 DAG.getNode(ISD::CTPOP, NVT, Hi));
4228 Hi = DAG.getConstant(0, NVT);
4232 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4233 ExpandOp(Node->getOperand(0), Lo, Hi);
4234 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4235 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4236 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4238 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4239 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4241 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4242 Hi = DAG.getConstant(0, NVT);
4247 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4248 ExpandOp(Node->getOperand(0), Lo, Hi);
4249 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4250 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4251 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4253 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4254 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4256 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4257 Hi = DAG.getConstant(0, NVT);
4262 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4263 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4264 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4265 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4267 // Remember that we legalized the chain.
4268 Hi = LegalizeOp(Hi);
4269 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4270 if (!TLI.isLittleEndian())
4276 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4277 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4278 Lo = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4280 // Increment the pointer to the other half.
4281 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4282 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4283 getIntPtrConstant(IncrementSize));
4284 // FIXME: This creates a bogus srcvalue!
4285 Hi = DAG.getLoad(NVT, Ch, Ptr, Node->getOperand(2));
4287 // Build a factor node to remember that this load is independent of the
4289 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4292 // Remember that we legalized the chain.
4293 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4294 if (!TLI.isLittleEndian())
4300 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4301 SDOperand LL, LH, RL, RH;
4302 ExpandOp(Node->getOperand(0), LL, LH);
4303 ExpandOp(Node->getOperand(1), RL, RH);
4304 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4305 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4309 SDOperand LL, LH, RL, RH;
4310 ExpandOp(Node->getOperand(1), LL, LH);
4311 ExpandOp(Node->getOperand(2), RL, RH);
4312 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4313 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4316 case ISD::SELECT_CC: {
4317 SDOperand TL, TH, FL, FH;
4318 ExpandOp(Node->getOperand(2), TL, TH);
4319 ExpandOp(Node->getOperand(3), FL, FH);
4320 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4321 Node->getOperand(1), TL, FL, Node->getOperand(4));
4322 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4323 Node->getOperand(1), TH, FH, Node->getOperand(4));
4326 case ISD::SEXTLOAD: {
4327 SDOperand Chain = Node->getOperand(0);
4328 SDOperand Ptr = Node->getOperand(1);
4329 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4332 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4334 Lo = DAG.getExtLoad(ISD::SEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4337 // Remember that we legalized the chain.
4338 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4340 // The high part is obtained by SRA'ing all but one of the bits of the lo
4342 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4343 Hi = DAG.getNode(ISD::SRA, NVT, Lo, DAG.getConstant(LoSize-1,
4344 TLI.getShiftAmountTy()));
4347 case ISD::ZEXTLOAD: {
4348 SDOperand Chain = Node->getOperand(0);
4349 SDOperand Ptr = Node->getOperand(1);
4350 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4353 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4355 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4358 // Remember that we legalized the chain.
4359 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4361 // The high part is just a zero.
4362 Hi = DAG.getConstant(0, NVT);
4365 case ISD::EXTLOAD: {
4366 SDOperand Chain = Node->getOperand(0);
4367 SDOperand Ptr = Node->getOperand(1);
4368 MVT::ValueType EVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
4371 Lo = DAG.getLoad(NVT, Chain, Ptr, Node->getOperand(2));
4373 Lo = DAG.getExtLoad(ISD::EXTLOAD, NVT, Chain, Ptr, Node->getOperand(2),
4376 // Remember that we legalized the chain.
4377 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4379 // The high part is undefined.
4380 Hi = DAG.getNode(ISD::UNDEF, NVT);
4383 case ISD::ANY_EXTEND:
4384 // The low part is any extension of the input (which degenerates to a copy).
4385 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4386 // The high part is undefined.
4387 Hi = DAG.getNode(ISD::UNDEF, NVT);
4389 case ISD::SIGN_EXTEND: {
4390 // The low part is just a sign extension of the input (which degenerates to
4392 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4394 // The high part is obtained by SRA'ing all but one of the bits of the lo
4396 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4397 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4398 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4401 case ISD::ZERO_EXTEND:
4402 // The low part is just a zero extension of the input (which degenerates to
4404 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4406 // The high part is just a zero.
4407 Hi = DAG.getConstant(0, NVT);
4410 case ISD::BIT_CONVERT: {
4411 SDOperand Tmp = ExpandBIT_CONVERT(Node->getValueType(0),
4412 Node->getOperand(0));
4413 ExpandOp(Tmp, Lo, Hi);
4417 case ISD::READCYCLECOUNTER:
4418 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
4419 TargetLowering::Custom &&
4420 "Must custom expand ReadCycleCounter");
4421 Lo = TLI.LowerOperation(Op, DAG);
4422 assert(Lo.Val && "Node must be custom expanded!");
4423 Hi = Lo.getValue(1);
4424 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
4425 LegalizeOp(Lo.getValue(2)));
4428 // These operators cannot be expanded directly, emit them as calls to
4429 // library functions.
4430 case ISD::FP_TO_SINT:
4431 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
4433 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4434 case Expand: assert(0 && "cannot expand FP!");
4435 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4436 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4439 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
4441 // Now that the custom expander is done, expand the result, which is still
4444 ExpandOp(Op, Lo, Hi);
4449 if (Node->getOperand(0).getValueType() == MVT::f32)
4450 Lo = ExpandLibCall("__fixsfdi", Node, Hi);
4452 Lo = ExpandLibCall("__fixdfdi", Node, Hi);
4455 case ISD::FP_TO_UINT:
4456 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
4458 switch (getTypeAction(Node->getOperand(0).getValueType())) {
4459 case Expand: assert(0 && "cannot expand FP!");
4460 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
4461 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
4464 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
4466 // Now that the custom expander is done, expand the result.
4468 ExpandOp(Op, Lo, Hi);
4473 if (Node->getOperand(0).getValueType() == MVT::f32)
4474 Lo = ExpandLibCall("__fixunssfdi", Node, Hi);
4476 Lo = ExpandLibCall("__fixunsdfdi", Node, Hi);
4480 // If the target wants custom lowering, do so.
4481 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4482 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
4483 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
4484 Op = TLI.LowerOperation(Op, DAG);
4486 // Now that the custom expander is done, expand the result, which is
4488 ExpandOp(Op, Lo, Hi);
4493 // If we can emit an efficient shift operation, do so now.
4494 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4497 // If this target supports SHL_PARTS, use it.
4498 TargetLowering::LegalizeAction Action =
4499 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
4500 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4501 Action == TargetLowering::Custom) {
4502 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4506 // Otherwise, emit a libcall.
4507 Lo = ExpandLibCall("__ashldi3", Node, Hi);
4512 // If the target wants custom lowering, do so.
4513 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4514 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
4515 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
4516 Op = TLI.LowerOperation(Op, DAG);
4518 // Now that the custom expander is done, expand the result, which is
4520 ExpandOp(Op, Lo, Hi);
4525 // If we can emit an efficient shift operation, do so now.
4526 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
4529 // If this target supports SRA_PARTS, use it.
4530 TargetLowering::LegalizeAction Action =
4531 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
4532 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4533 Action == TargetLowering::Custom) {
4534 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4538 // Otherwise, emit a libcall.
4539 Lo = ExpandLibCall("__ashrdi3", Node, Hi);
4544 // If the target wants custom lowering, do so.
4545 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
4546 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
4547 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
4548 Op = TLI.LowerOperation(Op, DAG);
4550 // Now that the custom expander is done, expand the result, which is
4552 ExpandOp(Op, Lo, Hi);
4557 // If we can emit an efficient shift operation, do so now.
4558 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
4561 // If this target supports SRL_PARTS, use it.
4562 TargetLowering::LegalizeAction Action =
4563 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
4564 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
4565 Action == TargetLowering::Custom) {
4566 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
4570 // Otherwise, emit a libcall.
4571 Lo = ExpandLibCall("__lshrdi3", Node, Hi);
4577 // If the target wants to custom expand this, let them.
4578 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
4579 TargetLowering::Custom) {
4580 Op = TLI.LowerOperation(Op, DAG);
4582 ExpandOp(Op, Lo, Hi);
4587 // Expand the subcomponents.
4588 SDOperand LHSL, LHSH, RHSL, RHSH;
4589 ExpandOp(Node->getOperand(0), LHSL, LHSH);
4590 ExpandOp(Node->getOperand(1), RHSL, RHSH);
4591 std::vector<MVT::ValueType> VTs;
4592 std::vector<SDOperand> LoOps, HiOps;
4593 VTs.push_back(LHSL.getValueType());
4594 VTs.push_back(MVT::Flag);
4595 LoOps.push_back(LHSL);
4596 LoOps.push_back(RHSL);
4597 HiOps.push_back(LHSH);
4598 HiOps.push_back(RHSH);
4599 if (Node->getOpcode() == ISD::ADD) {
4600 Lo = DAG.getNode(ISD::ADDC, VTs, LoOps);
4601 HiOps.push_back(Lo.getValue(1));
4602 Hi = DAG.getNode(ISD::ADDE, VTs, HiOps);
4604 Lo = DAG.getNode(ISD::SUBC, VTs, LoOps);
4605 HiOps.push_back(Lo.getValue(1));
4606 Hi = DAG.getNode(ISD::SUBE, VTs, HiOps);
4611 if (TLI.isOperationLegal(ISD::MULHU, NVT)) {
4612 SDOperand LL, LH, RL, RH;
4613 ExpandOp(Node->getOperand(0), LL, LH);
4614 ExpandOp(Node->getOperand(1), RL, RH);
4615 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
4616 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
4617 // extended the sign bit of the low half through the upper half, and if so
4618 // emit a MULHS instead of the alternate sequence that is valid for any
4619 // i64 x i64 multiply.
4620 if (TLI.isOperationLegal(ISD::MULHS, NVT) &&
4621 // is RH an extension of the sign bit of RL?
4622 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
4623 RH.getOperand(1).getOpcode() == ISD::Constant &&
4624 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
4625 // is LH an extension of the sign bit of LL?
4626 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
4627 LH.getOperand(1).getOpcode() == ISD::Constant &&
4628 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
4629 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
4631 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
4632 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
4633 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
4634 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
4635 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
4637 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
4639 Lo = ExpandLibCall("__muldi3" , Node, Hi);
4643 case ISD::SDIV: Lo = ExpandLibCall("__divdi3" , Node, Hi); break;
4644 case ISD::UDIV: Lo = ExpandLibCall("__udivdi3", Node, Hi); break;
4645 case ISD::SREM: Lo = ExpandLibCall("__moddi3" , Node, Hi); break;
4646 case ISD::UREM: Lo = ExpandLibCall("__umoddi3", Node, Hi); break;
4649 // Make sure the resultant values have been legalized themselves, unless this
4650 // is a type that requires multi-step expansion.
4651 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
4652 Lo = LegalizeOp(Lo);
4653 Hi = LegalizeOp(Hi);
4656 // Remember in a map if the values will be reused later.
4658 ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4659 assert(isNew && "Value already expanded?!?");
4662 /// SplitVectorOp - Given an operand of MVT::Vector type, break it down into
4663 /// two smaller values of MVT::Vector type.
4664 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
4666 assert(Op.getValueType() == MVT::Vector && "Cannot split non-vector type!");
4667 SDNode *Node = Op.Val;
4668 unsigned NumElements = cast<ConstantSDNode>(*(Node->op_end()-2))->getValue();
4669 assert(NumElements > 1 && "Cannot split a single element vector!");
4670 unsigned NewNumElts = NumElements/2;
4671 SDOperand NewNumEltsNode = DAG.getConstant(NewNumElts, MVT::i32);
4672 SDOperand TypeNode = *(Node->op_end()-1);
4674 // See if we already split it.
4675 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4676 = SplitNodes.find(Op);
4677 if (I != SplitNodes.end()) {
4678 Lo = I->second.first;
4679 Hi = I->second.second;
4683 switch (Node->getOpcode()) {
4684 default: Node->dump(); assert(0 && "Unhandled operation in SplitVectorOp!");
4685 case ISD::VBUILD_VECTOR: {
4686 std::vector<SDOperand> LoOps(Node->op_begin(), Node->op_begin()+NewNumElts);
4687 LoOps.push_back(NewNumEltsNode);
4688 LoOps.push_back(TypeNode);
4689 Lo = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, LoOps);
4691 std::vector<SDOperand> HiOps(Node->op_begin()+NewNumElts, Node->op_end()-2);
4692 HiOps.push_back(NewNumEltsNode);
4693 HiOps.push_back(TypeNode);
4694 Hi = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, HiOps);
4705 SDOperand LL, LH, RL, RH;
4706 SplitVectorOp(Node->getOperand(0), LL, LH);
4707 SplitVectorOp(Node->getOperand(1), RL, RH);
4709 Lo = DAG.getNode(Node->getOpcode(), MVT::Vector, LL, RL,
4710 NewNumEltsNode, TypeNode);
4711 Hi = DAG.getNode(Node->getOpcode(), MVT::Vector, LH, RH,
4712 NewNumEltsNode, TypeNode);
4716 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4717 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4718 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4720 Lo = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4721 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(EVT)/8;
4722 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4723 getIntPtrConstant(IncrementSize));
4724 // FIXME: This creates a bogus srcvalue!
4725 Hi = DAG.getVecLoad(NewNumElts, EVT, Ch, Ptr, Node->getOperand(2));
4727 // Build a factor node to remember that this load is independent of the
4729 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4732 // Remember that we legalized the chain.
4733 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4736 case ISD::VBIT_CONVERT: {
4737 // We know the result is a vector. The input may be either a vector or a
4739 if (Op.getOperand(0).getValueType() != MVT::Vector) {
4740 // Lower to a store/load. FIXME: this could be improved probably.
4741 SDOperand Ptr = CreateStackTemporary(Op.getOperand(0).getValueType());
4743 SDOperand St = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
4744 Op.getOperand(0), Ptr, DAG.getSrcValue(0));
4745 MVT::ValueType EVT = cast<VTSDNode>(TypeNode)->getVT();
4746 St = DAG.getVecLoad(NumElements, EVT, St, Ptr, DAG.getSrcValue(0));
4747 SplitVectorOp(St, Lo, Hi);
4749 // If the input is a vector type, we have to either scalarize it, pack it
4750 // or convert it based on whether the input vector type is legal.
4751 SDNode *InVal = Node->getOperand(0).Val;
4753 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4754 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4756 // If the input is from a single element vector, scalarize the vector,
4757 // then treat like a scalar.
4758 if (NumElems == 1) {
4759 SDOperand Scalar = PackVectorOp(Op.getOperand(0), EVT);
4760 Scalar = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Scalar,
4761 Op.getOperand(1), Op.getOperand(2));
4762 SplitVectorOp(Scalar, Lo, Hi);
4764 // Split the input vector.
4765 SplitVectorOp(Op.getOperand(0), Lo, Hi);
4767 // Convert each of the pieces now.
4768 Lo = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Lo,
4769 NewNumEltsNode, TypeNode);
4770 Hi = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Hi,
4771 NewNumEltsNode, TypeNode);
4778 // Remember in a map if the values will be reused later.
4780 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
4781 assert(isNew && "Value already expanded?!?");
4785 /// PackVectorOp - Given an operand of MVT::Vector type, convert it into the
4786 /// equivalent operation that returns a scalar (e.g. F32) or packed value
4787 /// (e.g. MVT::V4F32). When this is called, we know that PackedVT is the right
4788 /// type for the result.
4789 SDOperand SelectionDAGLegalize::PackVectorOp(SDOperand Op,
4790 MVT::ValueType NewVT) {
4791 assert(Op.getValueType() == MVT::Vector && "Bad PackVectorOp invocation!");
4792 SDNode *Node = Op.Val;
4794 // See if we already packed it.
4795 std::map<SDOperand, SDOperand>::iterator I = PackedNodes.find(Op);
4796 if (I != PackedNodes.end()) return I->second;
4799 switch (Node->getOpcode()) {
4801 Node->dump(); std::cerr << "\n";
4802 assert(0 && "Unknown vector operation in PackVectorOp!");
4811 Result = DAG.getNode(getScalarizedOpcode(Node->getOpcode(), NewVT),
4813 PackVectorOp(Node->getOperand(0), NewVT),
4814 PackVectorOp(Node->getOperand(1), NewVT));
4817 SDOperand Ch = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
4818 SDOperand Ptr = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
4820 Result = DAG.getLoad(NewVT, Ch, Ptr, Node->getOperand(2));
4822 // Remember that we legalized the chain.
4823 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
4826 case ISD::VBUILD_VECTOR:
4827 if (Node->getOperand(0).getValueType() == NewVT) {
4828 // Returning a scalar?
4829 Result = Node->getOperand(0);
4831 // Returning a BUILD_VECTOR?
4833 // If all elements of the build_vector are undefs, return an undef.
4834 bool AllUndef = true;
4835 for (unsigned i = 0, e = Node->getNumOperands()-2; i != e; ++i)
4836 if (Node->getOperand(i).getOpcode() != ISD::UNDEF) {
4841 Result = DAG.getNode(ISD::UNDEF, NewVT);
4843 std::vector<SDOperand> Ops(Node->op_begin(), Node->op_end()-2);
4844 Result = DAG.getNode(ISD::BUILD_VECTOR, NewVT, Ops);
4848 case ISD::VINSERT_VECTOR_ELT:
4849 if (!MVT::isVector(NewVT)) {
4850 // Returning a scalar? Must be the inserted element.
4851 Result = Node->getOperand(1);
4853 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT,
4854 PackVectorOp(Node->getOperand(0), NewVT),
4855 Node->getOperand(1), Node->getOperand(2));
4858 case ISD::VVECTOR_SHUFFLE:
4859 if (!MVT::isVector(NewVT)) {
4860 // Returning a scalar? Figure out if it is the LHS or RHS and return it.
4861 SDOperand EltNum = Node->getOperand(2).getOperand(0);
4862 if (cast<ConstantSDNode>(EltNum)->getValue())
4863 Result = PackVectorOp(Node->getOperand(1), NewVT);
4865 Result = PackVectorOp(Node->getOperand(0), NewVT);
4867 // Otherwise, return a VECTOR_SHUFFLE node. First convert the index
4868 // vector from a VBUILD_VECTOR to a BUILD_VECTOR.
4869 std::vector<SDOperand> BuildVecIdx(Node->getOperand(2).Val->op_begin(),
4870 Node->getOperand(2).Val->op_end()-2);
4871 MVT::ValueType BVT = MVT::getIntVectorWithNumElements(BuildVecIdx.size());
4872 SDOperand BV = DAG.getNode(ISD::BUILD_VECTOR, BVT, BuildVecIdx);
4874 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NewVT,
4875 PackVectorOp(Node->getOperand(0), NewVT),
4876 PackVectorOp(Node->getOperand(1), NewVT), BV);
4879 case ISD::VBIT_CONVERT:
4880 if (Op.getOperand(0).getValueType() != MVT::Vector)
4881 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
4883 // If the input is a vector type, we have to either scalarize it, pack it
4884 // or convert it based on whether the input vector type is legal.
4885 SDNode *InVal = Node->getOperand(0).Val;
4887 cast<ConstantSDNode>(*(InVal->op_end()-2))->getValue();
4888 MVT::ValueType EVT = cast<VTSDNode>(*(InVal->op_end()-1))->getVT();
4890 // Figure out if there is a Packed type corresponding to this Vector
4891 // type. If so, convert to the packed type.
4892 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
4893 if (TVT != MVT::Other && TLI.isTypeLegal(TVT)) {
4894 // Turn this into a bit convert of the packed input.
4895 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4896 PackVectorOp(Node->getOperand(0), TVT));
4898 } else if (NumElems == 1) {
4899 // Turn this into a bit convert of the scalar input.
4900 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT,
4901 PackVectorOp(Node->getOperand(0), EVT));
4905 assert(0 && "Cast from unsupported vector type not implemented yet!");
4910 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
4911 PackVectorOp(Op.getOperand(1), NewVT),
4912 PackVectorOp(Op.getOperand(2), NewVT));
4916 if (TLI.isTypeLegal(NewVT))
4917 Result = LegalizeOp(Result);
4918 bool isNew = PackedNodes.insert(std::make_pair(Op, Result)).second;
4919 assert(isNew && "Value already packed?");
4924 // SelectionDAG::Legalize - This is the entry point for the file.
4926 void SelectionDAG::Legalize() {
4927 if (ViewLegalizeDAGs) viewGraph();
4929 /// run - This is the main entry point to this class.
4931 SelectionDAGLegalize(*this).LegalizeDAG();