1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 CodeGenOpt::Level OptLevel;
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDValue LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDValue, SDValue> LegalizedNodes;
88 void AddLegalizedOperand(SDValue From, SDValue To) {
89 LegalizedNodes.insert(std::make_pair(From, To));
90 // If someone requests legalization of the new node, return itself.
92 LegalizedNodes.insert(std::make_pair(To, To));
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(MVT VT) const {
102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
105 /// isTypeLegal - Return true if this type is legal on this target.
107 bool isTypeLegal(MVT VT) const {
108 return getTypeAction(VT) == Legal;
114 /// LegalizeOp - We know that the specified value has a legal type.
115 /// Recursively ensure that the operands have legal types, then return the
117 SDValue LegalizeOp(SDValue O);
119 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
120 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
121 /// is necessary to spill the vector being inserted into to memory, perform
122 /// the insert there, and then read the result back.
123 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
124 SDValue Idx, DebugLoc dl);
125 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
126 SDValue Idx, DebugLoc dl);
128 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
129 /// performs the same shuffe in terms of order or result bytes, but on a type
130 /// whose vector element type is narrower than the original shuffle type.
131 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
132 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
133 SDValue N1, SDValue N2,
134 SmallVectorImpl<int> &Mask) const;
136 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
137 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
139 void LegalizeSetCCOperands(SDValue &LHS, SDValue &RHS, SDValue &CC,
141 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
143 void LegalizeSetCC(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
145 LegalizeSetCCOperands(LHS, RHS, CC, dl);
146 LegalizeSetCCCondCode(VT, LHS, RHS, CC, dl);
149 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
150 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
151 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
152 RTLIB::Libcall Call_PPCF128);
153 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16,
154 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
155 RTLIB::Libcall Call_I128);
157 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
158 SDValue ExpandBUILD_VECTOR(SDNode *Node);
159 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
160 SDValue ExpandDBG_STOPPOINT(SDNode *Node);
161 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
162 SmallVectorImpl<SDValue> &Results);
163 SDValue ExpandFCOPYSIGN(SDNode *Node);
164 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
166 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
168 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
171 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
172 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
174 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
176 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
177 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
181 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
182 /// performs the same shuffe in terms of order or result bytes, but on a type
183 /// whose vector element type is narrower than the original shuffle type.
184 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
186 SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
187 SDValue N1, SDValue N2,
188 SmallVectorImpl<int> &Mask) const {
189 MVT EltVT = NVT.getVectorElementType();
190 unsigned NumMaskElts = VT.getVectorNumElements();
191 unsigned NumDestElts = NVT.getVectorNumElements();
192 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
194 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
196 if (NumEltsGrowth == 1)
197 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
199 SmallVector<int, 8> NewMask;
200 for (unsigned i = 0; i != NumMaskElts; ++i) {
202 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
204 NewMask.push_back(-1);
206 NewMask.push_back(Idx * NumEltsGrowth + j);
209 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
210 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
211 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
214 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
215 CodeGenOpt::Level ol)
216 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
217 ValueTypeActions(TLI.getValueTypeActions()) {
218 assert(MVT::LAST_VALUETYPE <= 32 &&
219 "Too many value types for ValueTypeActions to hold!");
222 void SelectionDAGLegalize::LegalizeDAG() {
223 LastCALLSEQ_END = DAG.getEntryNode();
224 IsLegalizingCall = false;
226 // The legalize process is inherently a bottom-up recursive process (users
227 // legalize their uses before themselves). Given infinite stack space, we
228 // could just start legalizing on the root and traverse the whole graph. In
229 // practice however, this causes us to run out of stack space on large basic
230 // blocks. To avoid this problem, compute an ordering of the nodes where each
231 // node is only legalized after all of its operands are legalized.
232 DAG.AssignTopologicalOrder();
233 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
234 E = prior(DAG.allnodes_end()); I != next(E); ++I)
235 LegalizeOp(SDValue(I, 0));
237 // Finally, it's possible the root changed. Get the new root.
238 SDValue OldRoot = DAG.getRoot();
239 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
240 DAG.setRoot(LegalizedNodes[OldRoot]);
242 LegalizedNodes.clear();
244 // Remove dead nodes now.
245 DAG.RemoveDeadNodes();
249 /// FindCallEndFromCallStart - Given a chained node that is part of a call
250 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
251 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
252 if (Node->getOpcode() == ISD::CALLSEQ_END)
254 if (Node->use_empty())
255 return 0; // No CallSeqEnd
257 // The chain is usually at the end.
258 SDValue TheChain(Node, Node->getNumValues()-1);
259 if (TheChain.getValueType() != MVT::Other) {
260 // Sometimes it's at the beginning.
261 TheChain = SDValue(Node, 0);
262 if (TheChain.getValueType() != MVT::Other) {
263 // Otherwise, hunt for it.
264 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
265 if (Node->getValueType(i) == MVT::Other) {
266 TheChain = SDValue(Node, i);
270 // Otherwise, we walked into a node without a chain.
271 if (TheChain.getValueType() != MVT::Other)
276 for (SDNode::use_iterator UI = Node->use_begin(),
277 E = Node->use_end(); UI != E; ++UI) {
279 // Make sure to only follow users of our token chain.
281 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
282 if (User->getOperand(i) == TheChain)
283 if (SDNode *Result = FindCallEndFromCallStart(User))
289 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
290 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
291 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
292 assert(Node && "Didn't find callseq_start for a call??");
293 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
295 assert(Node->getOperand(0).getValueType() == MVT::Other &&
296 "Node doesn't have a token chain argument!");
297 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
300 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
301 /// see if any uses can reach Dest. If no dest operands can get to dest,
302 /// legalize them, legalize ourself, and return false, otherwise, return true.
304 /// Keep track of the nodes we fine that actually do lead to Dest in
305 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
307 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
308 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
309 if (N == Dest) return true; // N certainly leads to Dest :)
311 // If we've already processed this node and it does lead to Dest, there is no
312 // need to reprocess it.
313 if (NodesLeadingTo.count(N)) return true;
315 // If the first result of this node has been already legalized, then it cannot
317 if (LegalizedNodes.count(SDValue(N, 0))) return false;
319 // Okay, this node has not already been legalized. Check and legalize all
320 // operands. If none lead to Dest, then we can legalize this node.
321 bool OperandsLeadToDest = false;
322 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
323 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
324 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
326 if (OperandsLeadToDest) {
327 NodesLeadingTo.insert(N);
331 // Okay, this node looks safe, legalize it and return false.
332 LegalizeOp(SDValue(N, 0));
336 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
337 /// a load from the constant pool.
338 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
339 SelectionDAG &DAG, const TargetLowering &TLI) {
341 DebugLoc dl = CFP->getDebugLoc();
343 // If a FP immediate is precise when represented as a float and if the
344 // target can do an extending load from float to double, we put it into
345 // the constant pool as a float, even if it's is statically typed as a
346 // double. This shrinks FP constants and canonicalizes them for targets where
347 // an FP extending load is the same cost as a normal load (such as on the x87
348 // fp stack or PPC FP unit).
349 MVT VT = CFP->getValueType(0);
350 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
352 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
353 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
354 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
359 while (SVT != MVT::f32) {
360 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
361 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
362 // Only do this if the target has a native EXTLOAD instruction from
364 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
365 TLI.ShouldShrinkFPConstant(OrigVT)) {
366 const Type *SType = SVT.getTypeForMVT();
367 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
373 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
374 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
376 return DAG.getExtLoad(ISD::EXTLOAD, dl,
377 OrigVT, DAG.getEntryNode(),
378 CPIdx, PseudoSourceValue::getConstantPool(),
379 0, VT, false, Alignment);
380 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
381 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
384 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
386 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
387 const TargetLowering &TLI) {
388 SDValue Chain = ST->getChain();
389 SDValue Ptr = ST->getBasePtr();
390 SDValue Val = ST->getValue();
391 MVT VT = Val.getValueType();
392 int Alignment = ST->getAlignment();
393 int SVOffset = ST->getSrcValueOffset();
394 DebugLoc dl = ST->getDebugLoc();
395 if (ST->getMemoryVT().isFloatingPoint() ||
396 ST->getMemoryVT().isVector()) {
397 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
398 if (TLI.isTypeLegal(intVT)) {
399 // Expand to a bitconvert of the value to the integer type of the
400 // same size, then a (misaligned) int store.
401 // FIXME: Does not handle truncating floating point stores!
402 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
403 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
404 SVOffset, ST->isVolatile(), Alignment);
406 // Do a (aligned) store to a stack slot, then copy from the stack slot
407 // to the final destination using (unaligned) integer loads and stores.
408 MVT StoredVT = ST->getMemoryVT();
410 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
411 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
412 unsigned RegBytes = RegVT.getSizeInBits() / 8;
413 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
415 // Make sure the stack slot is also aligned for the register type.
416 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
418 // Perform the original store, only redirected to the stack slot.
419 SDValue Store = DAG.getTruncStore(Chain, dl,
420 Val, StackPtr, NULL, 0, StoredVT);
421 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
422 SmallVector<SDValue, 8> Stores;
425 // Do all but one copies using the full register width.
426 for (unsigned i = 1; i < NumRegs; i++) {
427 // Load one integer register's worth from the stack slot.
428 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
429 // Store it to the final location. Remember the store.
430 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
431 ST->getSrcValue(), SVOffset + Offset,
433 MinAlign(ST->getAlignment(), Offset)));
434 // Increment the pointers.
436 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
438 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
441 // The last store may be partial. Do a truncating store. On big-endian
442 // machines this requires an extending load from the stack slot to ensure
443 // that the bits are in the right place.
444 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
446 // Load from the stack slot.
447 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
450 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
451 ST->getSrcValue(), SVOffset + Offset,
452 MemVT, ST->isVolatile(),
453 MinAlign(ST->getAlignment(), Offset)));
454 // The order of the stores doesn't matter - say it with a TokenFactor.
455 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
459 assert(ST->getMemoryVT().isInteger() &&
460 !ST->getMemoryVT().isVector() &&
461 "Unaligned store of unknown type.");
462 // Get the half-size VT
464 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
465 int NumBits = NewStoredVT.getSizeInBits();
466 int IncrementSize = NumBits / 8;
468 // Divide the stored value in two parts.
469 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
471 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
473 // Store the two parts
474 SDValue Store1, Store2;
475 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
476 ST->getSrcValue(), SVOffset, NewStoredVT,
477 ST->isVolatile(), Alignment);
478 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
479 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
480 Alignment = MinAlign(Alignment, IncrementSize);
481 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
482 ST->getSrcValue(), SVOffset + IncrementSize,
483 NewStoredVT, ST->isVolatile(), Alignment);
485 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
488 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
490 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
491 const TargetLowering &TLI) {
492 int SVOffset = LD->getSrcValueOffset();
493 SDValue Chain = LD->getChain();
494 SDValue Ptr = LD->getBasePtr();
495 MVT VT = LD->getValueType(0);
496 MVT LoadedVT = LD->getMemoryVT();
497 DebugLoc dl = LD->getDebugLoc();
498 if (VT.isFloatingPoint() || VT.isVector()) {
499 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
500 if (TLI.isTypeLegal(intVT)) {
501 // Expand to a (misaligned) integer load of the same size,
502 // then bitconvert to floating point or vector.
503 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
504 SVOffset, LD->isVolatile(),
506 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
507 if (VT.isFloatingPoint() && LoadedVT != VT)
508 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
510 SDValue Ops[] = { Result, Chain };
511 return DAG.getMergeValues(Ops, 2, dl);
513 // Copy the value to a (aligned) stack slot using (unaligned) integer
514 // loads and stores, then do a (aligned) load from the stack slot.
515 MVT RegVT = TLI.getRegisterType(intVT);
516 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
517 unsigned RegBytes = RegVT.getSizeInBits() / 8;
518 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
520 // Make sure the stack slot is also aligned for the register type.
521 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
523 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
524 SmallVector<SDValue, 8> Stores;
525 SDValue StackPtr = StackBase;
528 // Do all but one copies using the full register width.
529 for (unsigned i = 1; i < NumRegs; i++) {
530 // Load one integer register's worth from the original location.
531 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
532 SVOffset + Offset, LD->isVolatile(),
533 MinAlign(LD->getAlignment(), Offset));
534 // Follow the load with a store to the stack slot. Remember the store.
535 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
537 // Increment the pointers.
539 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
540 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
544 // The last copy may be partial. Do an extending load.
545 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
546 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
547 LD->getSrcValue(), SVOffset + Offset,
548 MemVT, LD->isVolatile(),
549 MinAlign(LD->getAlignment(), Offset));
550 // Follow the load with a store to the stack slot. Remember the store.
551 // On big-endian machines this requires a truncating store to ensure
552 // that the bits end up in the right place.
553 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
556 // The order of the stores doesn't matter - say it with a TokenFactor.
557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
560 // Finally, perform the original load only redirected to the stack slot.
561 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
564 // Callers expect a MERGE_VALUES node.
565 SDValue Ops[] = { Load, TF };
566 return DAG.getMergeValues(Ops, 2, dl);
569 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
570 "Unaligned load of unsupported type.");
572 // Compute the new VT that is half the size of the old one. This is an
574 unsigned NumBits = LoadedVT.getSizeInBits();
576 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
579 unsigned Alignment = LD->getAlignment();
580 unsigned IncrementSize = NumBits / 8;
581 ISD::LoadExtType HiExtType = LD->getExtensionType();
583 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
584 if (HiExtType == ISD::NON_EXTLOAD)
585 HiExtType = ISD::ZEXTLOAD;
587 // Load the value in two parts
589 if (TLI.isLittleEndian()) {
590 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
591 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
592 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
593 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
594 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
595 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
596 MinAlign(Alignment, IncrementSize));
598 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
599 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
600 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
601 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
602 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
603 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
604 MinAlign(Alignment, IncrementSize));
607 // aggregate the two parts
608 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
609 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
610 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
612 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
615 SDValue Ops[] = { Result, TF };
616 return DAG.getMergeValues(Ops, 2, dl);
619 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
620 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
621 /// is necessary to spill the vector being inserted into to memory, perform
622 /// the insert there, and then read the result back.
623 SDValue SelectionDAGLegalize::
624 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
630 // If the target doesn't support this, we have to spill the input vector
631 // to a temporary stack slot, update the element, then reload it. This is
632 // badness. We could also load the value into a vector register (either
633 // with a "move to register" or "extload into register" instruction, then
634 // permute it into place, if the idx is a constant and if the idx is
635 // supported by the target.
636 MVT VT = Tmp1.getValueType();
637 MVT EltVT = VT.getVectorElementType();
638 MVT IdxVT = Tmp3.getValueType();
639 MVT PtrVT = TLI.getPointerTy();
640 SDValue StackPtr = DAG.CreateStackTemporary(VT);
642 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
645 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
646 PseudoSourceValue::getFixedStack(SPFI), 0);
648 // Truncate or zero extend offset to target pointer type.
649 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
650 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
651 // Add the offset to the index.
652 unsigned EltSize = EltVT.getSizeInBits()/8;
653 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
654 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
655 // Store the scalar value.
656 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
657 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
658 // Load the updated vector.
659 return DAG.getLoad(VT, dl, Ch, StackPtr,
660 PseudoSourceValue::getFixedStack(SPFI), 0);
664 SDValue SelectionDAGLegalize::
665 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
666 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
667 // SCALAR_TO_VECTOR requires that the type of the value being inserted
668 // match the element type of the vector being created, except for
669 // integers in which case the inserted value can be over width.
670 MVT EltVT = Vec.getValueType().getVectorElementType();
671 if (Val.getValueType() == EltVT ||
672 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
673 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
674 Vec.getValueType(), Val);
676 unsigned NumElts = Vec.getValueType().getVectorNumElements();
677 // We generate a shuffle of InVec and ScVec, so the shuffle mask
678 // should be 0,1,2,3,4,5... with the appropriate element replaced with
680 SmallVector<int, 8> ShufOps;
681 for (unsigned i = 0; i != NumElts; ++i)
682 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
684 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
688 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
691 /// LegalizeOp - We know that the specified value has a legal type, and
692 /// that its operands are legal. Now ensure that the operation itself
693 /// is legal, recursively ensuring that the operands' operations remain
695 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
696 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
699 SDNode *Node = Op.getNode();
700 DebugLoc dl = Node->getDebugLoc();
702 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
703 assert(getTypeAction(Node->getValueType(i)) == Legal &&
704 "Unexpected illegal type!");
706 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
707 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
708 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
709 "Unexpected illegal type!");
711 // Note that LegalizeOp may be reentered even from single-use nodes, which
712 // means that we always must cache transformed nodes.
713 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
714 if (I != LegalizedNodes.end()) return I->second;
716 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
718 bool isCustom = false;
720 // Figure out the correct action; the way to query this varies by opcode
721 TargetLowering::LegalizeAction Action;
722 bool SimpleFinishLegalizing = true;
723 switch (Node->getOpcode()) {
724 case ISD::INTRINSIC_W_CHAIN:
725 case ISD::INTRINSIC_WO_CHAIN:
726 case ISD::INTRINSIC_VOID:
729 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
731 case ISD::SINT_TO_FP:
732 case ISD::UINT_TO_FP:
733 case ISD::EXTRACT_VECTOR_ELT:
734 Action = TLI.getOperationAction(Node->getOpcode(),
735 Node->getOperand(0).getValueType());
737 case ISD::FP_ROUND_INREG:
738 case ISD::SIGN_EXTEND_INREG: {
739 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
740 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
746 case ISD::FORMAL_ARGUMENTS:
748 case ISD::CALLSEQ_START:
749 case ISD::CALLSEQ_END:
752 // These instructions have properties that aren't modeled in the
754 SimpleFinishLegalizing = false;
756 case ISD::EXTRACT_ELEMENT:
757 case ISD::FLT_ROUNDS_:
765 case ISD::MERGE_VALUES:
767 case ISD::FRAME_TO_ARGS_OFFSET:
768 // These operations lie about being legal: when they claim to be legal,
769 // they should actually be expanded.
770 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
771 if (Action == TargetLowering::Legal)
772 Action = TargetLowering::Expand;
774 case ISD::TRAMPOLINE:
776 case ISD::RETURNADDR:
777 // These operations lie about being legal: when they claim to be legal,
778 // they should actually be custom-lowered.
779 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
780 if (Action == TargetLowering::Legal)
781 Action = TargetLowering::Custom;
783 case ISD::BUILD_VECTOR:
784 // A weird case: legalization for BUILD_VECTOR never legalizes the
786 // FIXME: This really sucks... changing it isn't semantically incorrect,
787 // but it massively pessimizes the code for floating-point BUILD_VECTORs
788 // because ConstantFP operands get legalized into constant pool loads
789 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
790 // though, because BUILD_VECTORS usually get lowered into other nodes
791 // which get legalized properly.
792 SimpleFinishLegalizing = false;
795 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
796 Action = TargetLowering::Legal;
798 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
803 if (SimpleFinishLegalizing) {
804 SmallVector<SDValue, 8> Ops, ResultVals;
805 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
806 Ops.push_back(LegalizeOp(Node->getOperand(i)));
807 switch (Node->getOpcode()) {
815 // Branches tweak the chain to include LastCALLSEQ_END
816 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
818 Ops[0] = LegalizeOp(Ops[0]);
819 LastCALLSEQ_END = DAG.getEntryNode();
826 // Legalizing shifts/rotates requires adjusting the shift amount
827 // to the appropriate width.
828 if (!Ops[1].getValueType().isVector())
829 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
833 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
836 case TargetLowering::Legal:
837 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
838 ResultVals.push_back(Result.getValue(i));
840 case TargetLowering::Custom:
841 // FIXME: The handling for custom lowering with multiple results is
843 Tmp1 = TLI.LowerOperation(Result, DAG);
844 if (Tmp1.getNode()) {
845 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
847 ResultVals.push_back(Tmp1);
849 ResultVals.push_back(Tmp1.getValue(i));
855 case TargetLowering::Expand:
856 ExpandNode(Result.getNode(), ResultVals);
858 case TargetLowering::Promote:
859 PromoteNode(Result.getNode(), ResultVals);
862 if (!ResultVals.empty()) {
863 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
864 if (ResultVals[i] != SDValue(Node, i))
865 ResultVals[i] = LegalizeOp(ResultVals[i]);
866 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
868 return ResultVals[Op.getResNo()];
872 switch (Node->getOpcode()) {
875 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
877 assert(0 && "Do not know how to legalize this operator!");
879 case ISD::FORMAL_ARGUMENTS:
881 // The only option for this is to custom lower it.
882 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
883 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
884 // A call within a calling sequence must be legalized to something
885 // other than the normal CALLSEQ_END. Violating this gets Legalize
886 // into an infinite loop.
887 assert ((!IsLegalizingCall ||
888 Node->getOpcode() != ISD::CALL ||
889 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
890 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
892 // The number of incoming and outgoing values should match; unless the final
893 // outgoing value is a flag.
894 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
895 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
896 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
898 "Lowering call/formal_arguments produced unexpected # results!");
900 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
901 // remember that we legalized all of them, so it doesn't get relegalized.
902 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
903 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
905 Tmp1 = LegalizeOp(Tmp3.getValue(i));
906 if (Op.getResNo() == i)
908 AddLegalizedOperand(SDValue(Node, i), Tmp1);
911 case ISD::BUILD_VECTOR:
912 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
913 default: assert(0 && "This action is not supported yet!");
914 case TargetLowering::Custom:
915 Tmp3 = TLI.LowerOperation(Result, DAG);
916 if (Tmp3.getNode()) {
921 case TargetLowering::Expand:
922 Result = ExpandBUILD_VECTOR(Result.getNode());
926 case ISD::CALLSEQ_START: {
927 SDNode *CallEnd = FindCallEndFromCallStart(Node);
929 // Recursively Legalize all of the inputs of the call end that do not lead
930 // to this call start. This ensures that any libcalls that need be inserted
931 // are inserted *before* the CALLSEQ_START.
932 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
933 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
934 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
938 // Now that we legalized all of the inputs (which may have inserted
939 // libcalls) create the new CALLSEQ_START node.
940 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
942 // Merge in the last call, to ensure that this call start after the last
944 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
945 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
946 Tmp1, LastCALLSEQ_END);
947 Tmp1 = LegalizeOp(Tmp1);
950 // Do not try to legalize the target-specific arguments (#1+).
951 if (Tmp1 != Node->getOperand(0)) {
952 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
954 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
957 // Remember that the CALLSEQ_START is legalized.
958 AddLegalizedOperand(Op.getValue(0), Result);
959 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
960 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
962 // Now that the callseq_start and all of the non-call nodes above this call
963 // sequence have been legalized, legalize the call itself. During this
964 // process, no libcalls can/will be inserted, guaranteeing that no calls
966 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
967 // Note that we are selecting this call!
968 LastCALLSEQ_END = SDValue(CallEnd, 0);
969 IsLegalizingCall = true;
971 // Legalize the call, starting from the CALLSEQ_END.
972 LegalizeOp(LastCALLSEQ_END);
973 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
976 case ISD::CALLSEQ_END:
977 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
978 // will cause this node to be legalized as well as handling libcalls right.
979 if (LastCALLSEQ_END.getNode() != Node) {
980 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
981 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
982 assert(I != LegalizedNodes.end() &&
983 "Legalizing the call start should have legalized this node!");
987 // Otherwise, the call start has been legalized and everything is going
988 // according to plan. Just legalize ourselves normally here.
989 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
990 // Do not try to legalize the target-specific arguments (#1+), except for
991 // an optional flag input.
992 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
993 if (Tmp1 != Node->getOperand(0)) {
994 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
996 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
999 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1000 if (Tmp1 != Node->getOperand(0) ||
1001 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1002 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1005 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1008 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1009 // This finishes up call legalization.
1010 IsLegalizingCall = false;
1012 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1013 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1014 if (Node->getNumValues() == 2)
1015 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1016 return Result.getValue(Op.getResNo());
1018 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1019 // Ensure that libcalls are emitted before a branch.
1020 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Tmp1, LastCALLSEQ_END);
1021 Tmp1 = LegalizeOp(Tmp1);
1022 Tmp2 = Node->getOperand(2); // LHS
1023 Tmp3 = Node->getOperand(3); // RHS
1024 Tmp4 = Node->getOperand(1); // CC
1026 LegalizeSetCC(TLI.getSetCCResultType(Tmp2.getValueType()),
1027 Tmp2, Tmp3, Tmp4, dl);
1028 LastCALLSEQ_END = DAG.getEntryNode();
1030 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
1031 // the LHS is a legal SETCC itself. In this case, we need to compare
1032 // the result against zero to select between true and false values.
1033 if (Tmp3.getNode() == 0) {
1034 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1035 Tmp4 = DAG.getCondCode(ISD::SETNE);
1038 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1039 Node->getOperand(4));
1041 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1042 default: assert(0 && "Unexpected action for BR_CC!");
1043 case TargetLowering::Legal: break;
1044 case TargetLowering::Custom:
1045 Tmp4 = TLI.LowerOperation(Result, DAG);
1046 if (Tmp4.getNode()) Result = Tmp4;
1051 LoadSDNode *LD = cast<LoadSDNode>(Node);
1052 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1053 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1055 ISD::LoadExtType ExtType = LD->getExtensionType();
1056 if (ExtType == ISD::NON_EXTLOAD) {
1057 MVT VT = Node->getValueType(0);
1058 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1059 Tmp3 = Result.getValue(0);
1060 Tmp4 = Result.getValue(1);
1062 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1063 default: assert(0 && "This action is not supported yet!");
1064 case TargetLowering::Legal:
1065 // If this is an unaligned load and the target doesn't support it,
1067 if (!TLI.allowsUnalignedMemoryAccesses()) {
1068 unsigned ABIAlignment = TLI.getTargetData()->
1069 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1070 if (LD->getAlignment() < ABIAlignment){
1071 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1073 Tmp3 = Result.getOperand(0);
1074 Tmp4 = Result.getOperand(1);
1075 Tmp3 = LegalizeOp(Tmp3);
1076 Tmp4 = LegalizeOp(Tmp4);
1080 case TargetLowering::Custom:
1081 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1082 if (Tmp1.getNode()) {
1083 Tmp3 = LegalizeOp(Tmp1);
1084 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1087 case TargetLowering::Promote: {
1088 // Only promote a load of vector type to another.
1089 assert(VT.isVector() && "Cannot promote this load!");
1090 // Change base type to a different vector type.
1091 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1093 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1094 LD->getSrcValueOffset(),
1095 LD->isVolatile(), LD->getAlignment());
1096 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1097 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1101 // Since loads produce two values, make sure to remember that we
1102 // legalized both of them.
1103 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1104 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1105 return Op.getResNo() ? Tmp4 : Tmp3;
1107 MVT SrcVT = LD->getMemoryVT();
1108 unsigned SrcWidth = SrcVT.getSizeInBits();
1109 int SVOffset = LD->getSrcValueOffset();
1110 unsigned Alignment = LD->getAlignment();
1111 bool isVolatile = LD->isVolatile();
1113 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1114 // Some targets pretend to have an i1 loading operation, and actually
1115 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1116 // bits are guaranteed to be zero; it helps the optimizers understand
1117 // that these bits are zero. It is also useful for EXTLOAD, since it
1118 // tells the optimizers that those bits are undefined. It would be
1119 // nice to have an effective generic way of getting these benefits...
1120 // Until such a way is found, don't insist on promoting i1 here.
1121 (SrcVT != MVT::i1 ||
1122 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1123 // Promote to a byte-sized load if not loading an integral number of
1124 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1125 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1126 MVT NVT = MVT::getIntegerVT(NewWidth);
1129 // The extra bits are guaranteed to be zero, since we stored them that
1130 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1132 ISD::LoadExtType NewExtType =
1133 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1135 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1136 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1137 NVT, isVolatile, Alignment);
1139 Ch = Result.getValue(1); // The chain.
1141 if (ExtType == ISD::SEXTLOAD)
1142 // Having the top bits zero doesn't help when sign extending.
1143 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1144 Result.getValueType(),
1145 Result, DAG.getValueType(SrcVT));
1146 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1147 // All the top bits are guaranteed to be zero - inform the optimizers.
1148 Result = DAG.getNode(ISD::AssertZext, dl,
1149 Result.getValueType(), Result,
1150 DAG.getValueType(SrcVT));
1152 Tmp1 = LegalizeOp(Result);
1153 Tmp2 = LegalizeOp(Ch);
1154 } else if (SrcWidth & (SrcWidth - 1)) {
1155 // If not loading a power-of-2 number of bits, expand as two loads.
1156 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
1157 "Unsupported extload!");
1158 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1159 assert(RoundWidth < SrcWidth);
1160 unsigned ExtraWidth = SrcWidth - RoundWidth;
1161 assert(ExtraWidth < RoundWidth);
1162 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1163 "Load size not an integral number of bytes!");
1164 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1165 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1167 unsigned IncrementSize;
1169 if (TLI.isLittleEndian()) {
1170 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1171 // Load the bottom RoundWidth bits.
1172 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1173 Node->getValueType(0), Tmp1, Tmp2,
1174 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1177 // Load the remaining ExtraWidth bits.
1178 IncrementSize = RoundWidth / 8;
1179 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1180 DAG.getIntPtrConstant(IncrementSize));
1181 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1182 LD->getSrcValue(), SVOffset + IncrementSize,
1183 ExtraVT, isVolatile,
1184 MinAlign(Alignment, IncrementSize));
1186 // Build a factor node to remember that this load is independent of the
1188 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1191 // Move the top bits to the right place.
1192 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1193 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1195 // Join the hi and lo parts.
1196 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1198 // Big endian - avoid unaligned loads.
1199 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1200 // Load the top RoundWidth bits.
1201 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1202 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1205 // Load the remaining ExtraWidth bits.
1206 IncrementSize = RoundWidth / 8;
1207 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1208 DAG.getIntPtrConstant(IncrementSize));
1209 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1210 Node->getValueType(0), Tmp1, Tmp2,
1211 LD->getSrcValue(), SVOffset + IncrementSize,
1212 ExtraVT, isVolatile,
1213 MinAlign(Alignment, IncrementSize));
1215 // Build a factor node to remember that this load is independent of the
1217 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1220 // Move the top bits to the right place.
1221 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1222 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1224 // Join the hi and lo parts.
1225 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1228 Tmp1 = LegalizeOp(Result);
1229 Tmp2 = LegalizeOp(Ch);
1231 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1232 default: assert(0 && "This action is not supported yet!");
1233 case TargetLowering::Custom:
1236 case TargetLowering::Legal:
1237 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1238 Tmp1 = Result.getValue(0);
1239 Tmp2 = Result.getValue(1);
1242 Tmp3 = TLI.LowerOperation(Result, DAG);
1243 if (Tmp3.getNode()) {
1244 Tmp1 = LegalizeOp(Tmp3);
1245 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1248 // If this is an unaligned load and the target doesn't support it,
1250 if (!TLI.allowsUnalignedMemoryAccesses()) {
1251 unsigned ABIAlignment = TLI.getTargetData()->
1252 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1253 if (LD->getAlignment() < ABIAlignment){
1254 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1256 Tmp1 = Result.getOperand(0);
1257 Tmp2 = Result.getOperand(1);
1258 Tmp1 = LegalizeOp(Tmp1);
1259 Tmp2 = LegalizeOp(Tmp2);
1264 case TargetLowering::Expand:
1265 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1266 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1267 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1268 LD->getSrcValueOffset(),
1269 LD->isVolatile(), LD->getAlignment());
1270 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1271 Node->getValueType(0), Load);
1272 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1273 Tmp2 = LegalizeOp(Load.getValue(1));
1276 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1277 // Turn the unsupported load into an EXTLOAD followed by an explicit
1278 // zero/sign extend inreg.
1279 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1280 Tmp1, Tmp2, LD->getSrcValue(),
1281 LD->getSrcValueOffset(), SrcVT,
1282 LD->isVolatile(), LD->getAlignment());
1284 if (ExtType == ISD::SEXTLOAD)
1285 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1286 Result.getValueType(),
1287 Result, DAG.getValueType(SrcVT));
1289 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1290 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1291 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1296 // Since loads produce two values, make sure to remember that we legalized
1298 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1299 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1300 return Op.getResNo() ? Tmp2 : Tmp1;
1304 StoreSDNode *ST = cast<StoreSDNode>(Node);
1305 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1306 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1307 int SVOffset = ST->getSrcValueOffset();
1308 unsigned Alignment = ST->getAlignment();
1309 bool isVolatile = ST->isVolatile();
1311 if (!ST->isTruncatingStore()) {
1312 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1313 // FIXME: We shouldn't do this for TargetConstantFP's.
1314 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1315 // to phase ordering between legalized code and the dag combiner. This
1316 // probably means that we need to integrate dag combiner and legalizer
1318 // We generally can't do this one for long doubles.
1319 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1320 if (CFP->getValueType(0) == MVT::f32 &&
1321 getTypeAction(MVT::i32) == Legal) {
1322 Tmp3 = DAG.getConstant(CFP->getValueAPF().
1323 bitcastToAPInt().zextOrTrunc(32),
1325 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1326 SVOffset, isVolatile, Alignment);
1328 } else if (CFP->getValueType(0) == MVT::f64) {
1329 // If this target supports 64-bit registers, do a single 64-bit store.
1330 if (getTypeAction(MVT::i64) == Legal) {
1331 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
1332 zextOrTrunc(64), MVT::i64);
1333 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1334 SVOffset, isVolatile, Alignment);
1336 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
1337 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
1338 // stores. If the target supports neither 32- nor 64-bits, this
1339 // xform is certainly not worth it.
1340 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
1341 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
1342 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
1343 if (TLI.isBigEndian()) std::swap(Lo, Hi);
1345 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
1346 SVOffset, isVolatile, Alignment);
1347 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1348 DAG.getIntPtrConstant(4));
1349 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
1350 isVolatile, MinAlign(Alignment, 4U));
1352 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1359 Tmp3 = LegalizeOp(ST->getValue());
1360 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1363 MVT VT = Tmp3.getValueType();
1364 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1365 default: assert(0 && "This action is not supported yet!");
1366 case TargetLowering::Legal:
1367 // If this is an unaligned store and the target doesn't support it,
1369 if (!TLI.allowsUnalignedMemoryAccesses()) {
1370 unsigned ABIAlignment = TLI.getTargetData()->
1371 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
1372 if (ST->getAlignment() < ABIAlignment)
1373 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1377 case TargetLowering::Custom:
1378 Tmp1 = TLI.LowerOperation(Result, DAG);
1379 if (Tmp1.getNode()) Result = Tmp1;
1381 case TargetLowering::Promote:
1382 assert(VT.isVector() && "Unknown legal promote case!");
1383 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1384 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1385 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1386 ST->getSrcValue(), SVOffset, isVolatile,
1393 Tmp3 = LegalizeOp(ST->getValue());
1395 MVT StVT = ST->getMemoryVT();
1396 unsigned StWidth = StVT.getSizeInBits();
1398 if (StWidth != StVT.getStoreSizeInBits()) {
1399 // Promote to a byte-sized store with upper bits zero if not
1400 // storing an integral number of bytes. For example, promote
1401 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1402 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
1403 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1404 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1405 SVOffset, NVT, isVolatile, Alignment);
1406 } else if (StWidth & (StWidth - 1)) {
1407 // If not storing a power-of-2 number of bits, expand as two stores.
1408 assert(StVT.isExtended() && !StVT.isVector() &&
1409 "Unsupported truncstore!");
1410 unsigned RoundWidth = 1 << Log2_32(StWidth);
1411 assert(RoundWidth < StWidth);
1412 unsigned ExtraWidth = StWidth - RoundWidth;
1413 assert(ExtraWidth < RoundWidth);
1414 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1415 "Store size not an integral number of bytes!");
1416 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1417 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1419 unsigned IncrementSize;
1421 if (TLI.isLittleEndian()) {
1422 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1423 // Store the bottom RoundWidth bits.
1424 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1426 isVolatile, Alignment);
1428 // Store the remaining ExtraWidth bits.
1429 IncrementSize = RoundWidth / 8;
1430 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1431 DAG.getIntPtrConstant(IncrementSize));
1432 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1433 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1434 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1435 SVOffset + IncrementSize, ExtraVT, isVolatile,
1436 MinAlign(Alignment, IncrementSize));
1438 // Big endian - avoid unaligned stores.
1439 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1440 // Store the top RoundWidth bits.
1441 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1442 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1443 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1444 SVOffset, RoundVT, isVolatile, Alignment);
1446 // Store the remaining ExtraWidth bits.
1447 IncrementSize = RoundWidth / 8;
1448 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1449 DAG.getIntPtrConstant(IncrementSize));
1450 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1451 SVOffset + IncrementSize, ExtraVT, isVolatile,
1452 MinAlign(Alignment, IncrementSize));
1455 // The order of the stores doesn't matter.
1456 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1458 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1459 Tmp2 != ST->getBasePtr())
1460 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1463 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1464 default: assert(0 && "This action is not supported yet!");
1465 case TargetLowering::Legal:
1466 // If this is an unaligned store and the target doesn't support it,
1468 if (!TLI.allowsUnalignedMemoryAccesses()) {
1469 unsigned ABIAlignment = TLI.getTargetData()->
1470 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
1471 if (ST->getAlignment() < ABIAlignment)
1472 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1476 case TargetLowering::Custom:
1477 Result = TLI.LowerOperation(Result, DAG);
1480 // TRUNCSTORE:i16 i32 -> STORE i16
1481 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1482 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1483 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1484 SVOffset, isVolatile, Alignment);
1491 case ISD::SELECT_CC: {
1492 Tmp1 = Node->getOperand(0); // LHS
1493 Tmp2 = Node->getOperand(1); // RHS
1494 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
1495 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
1496 SDValue CC = Node->getOperand(4);
1498 LegalizeSetCC(TLI.getSetCCResultType(Tmp1.getValueType()),
1499 Tmp1, Tmp2, CC, dl);
1501 // If we didn't get both a LHS and RHS back from LegalizeSetCC,
1502 // the LHS is a legal SETCC itself. In this case, we need to compare
1503 // the result against zero to select between true and false values.
1504 if (Tmp2.getNode() == 0) {
1505 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
1506 CC = DAG.getCondCode(ISD::SETNE);
1508 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
1510 // Everything is legal, see if we should expand this op or something.
1511 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
1512 default: assert(0 && "This action is not supported yet!");
1513 case TargetLowering::Legal: break;
1514 case TargetLowering::Custom:
1515 Tmp1 = TLI.LowerOperation(Result, DAG);
1516 if (Tmp1.getNode()) Result = Tmp1;
1522 Tmp1 = Node->getOperand(0);
1523 Tmp2 = Node->getOperand(1);
1524 Tmp3 = Node->getOperand(2);
1525 LegalizeSetCC(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
1527 // If we had to Expand the SetCC operands into a SELECT node, then it may
1528 // not always be possible to return a true LHS & RHS. In this case, just
1529 // return the value we legalized, returned in the LHS
1530 if (Tmp2.getNode() == 0) {
1535 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
1536 default: assert(0 && "Cannot handle this action for SETCC yet!");
1537 case TargetLowering::Custom:
1540 case TargetLowering::Legal:
1541 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1543 Tmp4 = TLI.LowerOperation(Result, DAG);
1544 if (Tmp4.getNode()) Result = Tmp4;
1547 case TargetLowering::Promote: {
1548 // First step, figure out the appropriate operation to use.
1549 // Allow SETCC to not be supported for all legal data types
1550 // Mostly this targets FP
1551 MVT NewInTy = Node->getOperand(0).getValueType();
1552 MVT OldVT = NewInTy; OldVT = OldVT;
1554 // Scan for the appropriate larger type to use.
1556 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
1558 assert(NewInTy.isInteger() == OldVT.isInteger() &&
1559 "Fell off of the edge of the integer world");
1560 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
1561 "Fell off of the edge of the floating point world");
1563 // If the target supports SETCC of this type, use it.
1564 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
1567 if (NewInTy.isInteger())
1568 assert(0 && "Cannot promote Legal Integer SETCC yet");
1570 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
1571 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
1573 Tmp1 = LegalizeOp(Tmp1);
1574 Tmp2 = LegalizeOp(Tmp2);
1575 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1576 Result = LegalizeOp(Result);
1579 case TargetLowering::Expand:
1580 // Expand a setcc node into a select_cc of the same condition, lhs, and
1581 // rhs that selects between const 1 (true) and const 0 (false).
1582 MVT VT = Node->getValueType(0);
1583 Result = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
1584 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
1591 assert(Result.getValueType() == Op.getValueType() &&
1592 "Bad legalization!");
1594 // Make sure that the generated code is itself legal.
1596 Result = LegalizeOp(Result);
1598 // Note that LegalizeOp may be reentered even from single-use nodes, which
1599 // means that we always must cache transformed nodes.
1600 AddLegalizedOperand(Op, Result);
1604 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1605 SDValue Vec = Op.getOperand(0);
1606 SDValue Idx = Op.getOperand(1);
1607 DebugLoc dl = Op.getDebugLoc();
1608 // Store the value to a temporary stack slot, then LOAD the returned part.
1609 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1610 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
1612 // Add the offset to the index.
1614 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1615 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1616 DAG.getConstant(EltSize, Idx.getValueType()));
1618 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1619 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1621 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1623 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1625 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
1628 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1629 DebugLoc dl = Node->getDebugLoc();
1630 SDValue Tmp1 = Node->getOperand(0);
1631 SDValue Tmp2 = Node->getOperand(1);
1632 assert((Tmp2.getValueType() == MVT::f32 ||
1633 Tmp2.getValueType() == MVT::f64) &&
1634 "Ugly special-cased code!");
1635 // Get the sign bit of the RHS.
1637 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1638 if (isTypeLegal(IVT)) {
1639 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1641 assert(isTypeLegal(TLI.getPointerTy()) &&
1642 (TLI.getPointerTy() == MVT::i32 ||
1643 TLI.getPointerTy() == MVT::i64) &&
1644 "Legal type for load?!");
1645 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1646 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1648 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1649 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1650 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1651 LoadPtr, DAG.getIntPtrConstant(4));
1652 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1653 Ch, LoadPtr, NULL, 0, MVT::i32);
1656 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1657 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1659 // Get the absolute value of the result.
1660 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1661 // Select between the nabs and abs value based on the sign bit of
1663 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1664 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1668 SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
1669 DebugLoc dl = Node->getDebugLoc();
1670 DwarfWriter *DW = DAG.getDwarfWriter();
1671 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1673 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1675 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1676 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1677 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1678 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1680 unsigned Line = DSP->getLine();
1681 unsigned Col = DSP->getColumn();
1683 if (OptLevel == CodeGenOpt::None) {
1684 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1685 // won't hurt anything.
1687 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
1688 DAG.getConstant(Line, MVT::i32),
1689 DAG.getConstant(Col, MVT::i32),
1690 DAG.getSrcValue(CU.getGV()));
1692 unsigned ID = DW->RecordSourceLine(Line, Col, CU);
1693 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID);
1697 return Node->getOperand(0);
1700 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1701 SmallVectorImpl<SDValue> &Results) {
1702 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1703 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1704 " not tell us which reg is the stack pointer!");
1705 DebugLoc dl = Node->getDebugLoc();
1706 MVT VT = Node->getValueType(0);
1707 SDValue Tmp1 = SDValue(Node, 0);
1708 SDValue Tmp2 = SDValue(Node, 1);
1709 SDValue Tmp3 = Node->getOperand(2);
1710 SDValue Chain = Tmp1.getOperand(0);
1712 // Chain the dynamic stack allocation so that it doesn't modify the stack
1713 // pointer when other instructions are using the stack.
1714 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1716 SDValue Size = Tmp2.getOperand(1);
1717 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1718 Chain = SP.getValue(1);
1719 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1720 unsigned StackAlign =
1721 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1722 if (Align > StackAlign)
1723 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1724 DAG.getConstant(-(uint64_t)Align, VT));
1725 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1726 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1728 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1729 DAG.getIntPtrConstant(0, true), SDValue());
1731 Results.push_back(Tmp1);
1732 Results.push_back(Tmp2);
1735 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
1736 /// with condition CC on the current target. This usually involves legalizing
1737 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
1738 /// there may be no choice but to create a new SetCC node to represent the
1739 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
1740 /// LHS, and the SDValue returned in RHS has a nil SDNode value.
1741 void SelectionDAGLegalize::LegalizeSetCCOperands(SDValue &LHS,
1745 LHS = LegalizeOp(LHS);
1746 RHS = LegalizeOp(RHS);
1749 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1750 /// condition code CC on the current target. This routine assumes LHS and rHS
1751 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
1752 /// illegal condition code into AND / OR of multiple SETCC values.
1753 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
1754 SDValue &LHS, SDValue &RHS,
1757 MVT OpVT = LHS.getValueType();
1758 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1759 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1760 default: assert(0 && "Unknown condition code action!");
1761 case TargetLowering::Legal:
1764 case TargetLowering::Expand: {
1765 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1768 default: assert(0 && "Don't know how to expand this condition!"); abort();
1769 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1770 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1771 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1772 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1773 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1774 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1775 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1776 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1777 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1778 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1779 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1780 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1781 // FIXME: Implement more expansions.
1784 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1785 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1786 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1794 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1795 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1796 /// a load from the stack slot to DestVT, extending it if needed.
1797 /// The resultant code need not be legal.
1798 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1802 // Create the stack frame object.
1804 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1806 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1808 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1809 int SPFI = StackPtrFI->getIndex();
1810 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1812 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1813 unsigned SlotSize = SlotVT.getSizeInBits();
1814 unsigned DestSize = DestVT.getSizeInBits();
1815 unsigned DestAlign =
1816 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
1818 // Emit a store to the stack slot. Use a truncstore if the input value is
1819 // later than DestVT.
1822 if (SrcSize > SlotSize)
1823 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1824 SV, 0, SlotVT, false, SrcAlign);
1826 assert(SrcSize == SlotSize && "Invalid store");
1827 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1828 SV, 0, false, SrcAlign);
1831 // Result is a load from the stack slot.
1832 if (SlotSize == DestSize)
1833 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
1835 assert(SlotSize < DestSize && "Unknown extension!");
1836 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1840 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1841 DebugLoc dl = Node->getDebugLoc();
1842 // Create a vector sized/aligned stack slot, store the value to element #0,
1843 // then load the whole vector back out.
1844 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1846 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1847 int SPFI = StackPtrFI->getIndex();
1849 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1851 PseudoSourceValue::getFixedStack(SPFI), 0,
1852 Node->getValueType(0).getVectorElementType());
1853 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1854 PseudoSourceValue::getFixedStack(SPFI), 0);
1858 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1859 /// support the operation, but do support the resultant vector type.
1860 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1861 unsigned NumElems = Node->getNumOperands();
1862 SDValue SplatValue = Node->getOperand(0);
1863 DebugLoc dl = Node->getDebugLoc();
1864 MVT VT = Node->getValueType(0);
1865 MVT OpVT = SplatValue.getValueType();
1866 MVT EltVT = VT.getVectorElementType();
1868 // If the only non-undef value is the low element, turn this into a
1869 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1870 bool isOnlyLowElement = true;
1872 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
1873 // and use a bitmask instead of a list of elements.
1874 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.
1875 std::map<SDValue, std::vector<unsigned> > Values;
1876 Values[SplatValue].push_back(0);
1877 bool isConstant = true;
1878 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
1879 SplatValue.getOpcode() != ISD::UNDEF)
1882 for (unsigned i = 1; i < NumElems; ++i) {
1883 SDValue V = Node->getOperand(i);
1884 Values[V].push_back(i);
1885 if (V.getOpcode() != ISD::UNDEF)
1886 isOnlyLowElement = false;
1887 if (SplatValue != V)
1888 SplatValue = SDValue(0, 0);
1890 // If this isn't a constant element or an undef, we can't use a constant
1892 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
1893 V.getOpcode() != ISD::UNDEF)
1897 if (isOnlyLowElement) {
1898 // If the low element is an undef too, then this whole things is an undef.
1899 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
1900 return DAG.getUNDEF(VT);
1901 // Otherwise, turn this into a scalar_to_vector node.
1902 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1905 // If all elements are constants, create a load from the constant pool.
1907 std::vector<Constant*> CV;
1908 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1909 if (ConstantFPSDNode *V =
1910 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1911 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1912 } else if (ConstantSDNode *V =
1913 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1914 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1916 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1917 const Type *OpNTy = OpVT.getTypeForMVT();
1918 CV.push_back(UndefValue::get(OpNTy));
1921 Constant *CP = ConstantVector::get(CV);
1922 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1923 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1924 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1925 PseudoSourceValue::getConstantPool(), 0,
1929 if (SplatValue.getNode()) { // Splat of one value?
1930 // Build the shuffle constant vector: <0, 0, 0, 0>
1931 SmallVector<int, 8> ZeroVec(NumElems, 0);
1933 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
1934 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) {
1935 // Get the splatted value into the low element of a vector register.
1937 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue);
1939 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1940 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT),
1945 // If there are only two unique elements, we may be able to turn this into a
1947 if (Values.size() == 2) {
1948 // Get the two values in deterministic order.
1949 SDValue Val1 = Node->getOperand(1);
1951 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
1952 if (MI->first != Val1)
1955 Val2 = (++MI)->first;
1957 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our
1958 // vector shuffle has the undef vector on the RHS.
1959 if (Val1.getOpcode() == ISD::UNDEF)
1960 std::swap(Val1, Val2);
1962 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
1963 SmallVector<int, 8> ShuffleMask(NumElems, -1);
1965 // Set elements of the shuffle mask for Val1.
1966 std::vector<unsigned> &Val1Elts = Values[Val1];
1967 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
1968 ShuffleMask[Val1Elts[i]] = 0;
1970 // Set elements of the shuffle mask for Val2.
1971 std::vector<unsigned> &Val2Elts = Values[Val2];
1972 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
1973 if (Val2.getOpcode() != ISD::UNDEF)
1974 ShuffleMask[Val2Elts[i]] = NumElems;
1976 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
1977 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) &&
1978 TLI.isShuffleMaskLegal(ShuffleMask, VT)) {
1979 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1);
1980 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2);
1981 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]);
1985 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
1986 // aligned object on the stack, store each element into it, then load
1987 // the result as a vector.
1988 // Create the stack frame object.
1989 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1990 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1991 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1993 // Emit a store of each element to the stack slot.
1994 SmallVector<SDValue, 8> Stores;
1995 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
1996 // Store (in the right endianness) the elements to memory.
1997 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1998 // Ignore undef elements.
1999 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
2001 unsigned Offset = TypeByteSize*i;
2003 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
2004 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
2006 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
2011 if (!Stores.empty()) // Not all undef elements?
2012 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2013 &Stores[0], Stores.size());
2015 StoreChain = DAG.getEntryNode();
2017 // Result is a load from the stack slot.
2018 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
2021 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
2022 // does not fit into a register, return the lo part and set the hi part to the
2023 // by-reg argument. If it does fit into a single register, return the result
2024 // and leave the Hi part unset.
2025 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
2027 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
2028 // The input chain to this libcall is the entry node of the function.
2029 // Legalizing the call will automatically add the previous call to the
2031 SDValue InChain = DAG.getEntryNode();
2033 TargetLowering::ArgListTy Args;
2034 TargetLowering::ArgListEntry Entry;
2035 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2036 MVT ArgVT = Node->getOperand(i).getValueType();
2037 const Type *ArgTy = ArgVT.getTypeForMVT();
2038 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
2039 Entry.isSExt = isSigned;
2040 Entry.isZExt = !isSigned;
2041 Args.push_back(Entry);
2043 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
2044 TLI.getPointerTy());
2046 // Splice the libcall in wherever FindInputOutputChains tells us to.
2047 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
2048 std::pair<SDValue, SDValue> CallInfo =
2049 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
2050 CallingConv::C, false, Callee, Args, DAG,
2051 Node->getDebugLoc());
2053 // Legalize the call sequence, starting with the chain. This will advance
2054 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
2055 // was added by LowerCallTo (guaranteeing proper serialization of calls).
2056 LegalizeOp(CallInfo.second);
2057 return CallInfo.first;
2060 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
2061 RTLIB::Libcall Call_F32,
2062 RTLIB::Libcall Call_F64,
2063 RTLIB::Libcall Call_F80,
2064 RTLIB::Libcall Call_PPCF128) {
2066 switch (Node->getValueType(0).getSimpleVT()) {
2067 default: assert(0 && "Unexpected request for libcall!");
2068 case MVT::f32: LC = Call_F32; break;
2069 case MVT::f64: LC = Call_F64; break;
2070 case MVT::f80: LC = Call_F80; break;
2071 case MVT::ppcf128: LC = Call_PPCF128; break;
2073 return ExpandLibCall(LC, Node, false);
2076 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
2077 RTLIB::Libcall Call_I16,
2078 RTLIB::Libcall Call_I32,
2079 RTLIB::Libcall Call_I64,
2080 RTLIB::Libcall Call_I128) {
2082 switch (Node->getValueType(0).getSimpleVT()) {
2083 default: assert(0 && "Unexpected request for libcall!");
2084 case MVT::i16: LC = Call_I16; break;
2085 case MVT::i32: LC = Call_I32; break;
2086 case MVT::i64: LC = Call_I64; break;
2087 case MVT::i128: LC = Call_I128; break;
2089 return ExpandLibCall(LC, Node, isSigned);
2092 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
2093 /// INT_TO_FP operation of the specified operand when the target requests that
2094 /// we expand it. At this point, we know that the result and operand types are
2095 /// legal for the target.
2096 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
2100 if (Op0.getValueType() == MVT::i32) {
2101 // simple 32-bit [signed|unsigned] integer to float/double expansion
2103 // Get the stack frame index of a 8 byte buffer.
2104 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
2106 // word offset constant for Hi/Lo address computation
2107 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
2108 // set up Hi and Lo (into buffer) address based on endian
2109 SDValue Hi = StackSlot;
2110 SDValue Lo = DAG.getNode(ISD::ADD, dl,
2111 TLI.getPointerTy(), StackSlot, WordOff);
2112 if (TLI.isLittleEndian())
2115 // if signed map to unsigned space
2118 // constant used to invert sign bit (signed to unsigned mapping)
2119 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
2120 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
2124 // store the lo of the constructed double - based on integer input
2125 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
2126 Op0Mapped, Lo, NULL, 0);
2127 // initial hi portion of constructed double
2128 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2129 // store the hi of the constructed double - biased exponent
2130 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
2131 // load the constructed double
2132 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
2133 // FP constant to bias correct the final result
2134 SDValue Bias = DAG.getConstantFP(isSigned ?
2135 BitsToDouble(0x4330000080000000ULL) :
2136 BitsToDouble(0x4330000000000000ULL),
2138 // subtract the bias
2139 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2142 // handle final rounding
2143 if (DestVT == MVT::f64) {
2146 } else if (DestVT.bitsLT(MVT::f64)) {
2147 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2148 DAG.getIntPtrConstant(0));
2149 } else if (DestVT.bitsGT(MVT::f64)) {
2150 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2154 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2155 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2157 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2158 Op0, DAG.getConstant(0, Op0.getValueType()),
2160 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2161 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2162 SignSet, Four, Zero);
2164 // If the sign bit of the integer is set, the large number will be treated
2165 // as a negative number. To counteract this, the dynamic code adds an
2166 // offset depending on the data type.
2168 switch (Op0.getValueType().getSimpleVT()) {
2169 default: assert(0 && "Unsupported integer type!");
2170 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2171 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2172 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2173 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2175 if (TLI.isLittleEndian()) FF <<= 32;
2176 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
2178 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2179 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2180 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2181 Alignment = std::min(Alignment, 4u);
2183 if (DestVT == MVT::f32)
2184 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2185 PseudoSourceValue::getConstantPool(), 0,
2189 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2190 DAG.getEntryNode(), CPIdx,
2191 PseudoSourceValue::getConstantPool(), 0,
2192 MVT::f32, false, Alignment));
2195 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2198 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2199 /// *INT_TO_FP operation of the specified operand when the target requests that
2200 /// we promote it. At this point, we know that the result and operand types are
2201 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2202 /// operation that takes a larger input.
2203 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2207 // First step, figure out the appropriate *INT_TO_FP operation to use.
2208 MVT NewInTy = LegalOp.getValueType();
2210 unsigned OpToUse = 0;
2212 // Scan for the appropriate larger type to use.
2214 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2215 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2217 // If the target supports SINT_TO_FP of this type, use it.
2218 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
2220 case TargetLowering::Legal:
2221 if (!TLI.isTypeLegal(NewInTy))
2222 break; // Can't use this datatype.
2224 case TargetLowering::Custom:
2225 OpToUse = ISD::SINT_TO_FP;
2229 if (isSigned) continue;
2231 // If the target supports UINT_TO_FP of this type, use it.
2232 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
2234 case TargetLowering::Legal:
2235 if (!TLI.isTypeLegal(NewInTy))
2236 break; // Can't use this datatype.
2238 case TargetLowering::Custom:
2239 OpToUse = ISD::UINT_TO_FP;
2244 // Otherwise, try a larger type.
2247 // Okay, we found the operation and type to use. Zero extend our input to the
2248 // desired type then run the operation on it.
2249 return DAG.getNode(OpToUse, dl, DestVT,
2250 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2251 dl, NewInTy, LegalOp));
2254 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2255 /// FP_TO_*INT operation of the specified operand when the target requests that
2256 /// we promote it. At this point, we know that the result and operand types are
2257 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2258 /// operation that returns a larger result.
2259 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2263 // First step, figure out the appropriate FP_TO*INT operation to use.
2264 MVT NewOutTy = DestVT;
2266 unsigned OpToUse = 0;
2268 // Scan for the appropriate larger type to use.
2270 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
2271 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2273 // If the target supports FP_TO_SINT returning this type, use it.
2274 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
2276 case TargetLowering::Legal:
2277 if (!TLI.isTypeLegal(NewOutTy))
2278 break; // Can't use this datatype.
2280 case TargetLowering::Custom:
2281 OpToUse = ISD::FP_TO_SINT;
2286 // If the target supports FP_TO_UINT of this type, use it.
2287 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
2289 case TargetLowering::Legal:
2290 if (!TLI.isTypeLegal(NewOutTy))
2291 break; // Can't use this datatype.
2293 case TargetLowering::Custom:
2294 OpToUse = ISD::FP_TO_UINT;
2299 // Otherwise, try a larger type.
2303 // Okay, we found the operation and type to use.
2304 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2306 // If the operation produces an invalid type, it must be custom lowered. Use
2307 // the target lowering hooks to expand it. Just keep the low part of the
2308 // expanded operation, we know that we're truncating anyway.
2309 if (getTypeAction(NewOutTy) == Expand) {
2310 SmallVector<SDValue, 2> Results;
2311 TLI.ReplaceNodeResults(Operation.getNode(), Results, DAG);
2312 assert(Results.size() == 1 && "Incorrect FP_TO_XINT lowering!");
2313 Operation = Results[0];
2316 // Truncate the result of the extended FP_TO_*INT operation to the desired
2318 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2321 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2323 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2324 MVT VT = Op.getValueType();
2325 MVT SHVT = TLI.getShiftAmountTy();
2326 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2327 switch (VT.getSimpleVT()) {
2328 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
2330 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2331 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2332 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2334 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2335 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2336 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2337 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2338 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2339 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2340 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2341 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2342 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2344 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2345 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2346 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2347 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2348 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2349 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2350 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2351 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2352 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2353 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2354 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2355 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2356 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2357 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2358 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2359 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2360 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2361 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2362 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2363 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2364 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2368 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2370 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2373 default: assert(0 && "Cannot expand this yet!");
2375 static const uint64_t mask[6] = {
2376 0x5555555555555555ULL, 0x3333333333333333ULL,
2377 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2378 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2380 MVT VT = Op.getValueType();
2381 MVT ShVT = TLI.getShiftAmountTy();
2382 unsigned len = VT.getSizeInBits();
2383 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2384 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2385 unsigned EltSize = VT.isVector() ?
2386 VT.getVectorElementType().getSizeInBits() : len;
2387 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2388 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2389 Op = DAG.getNode(ISD::ADD, dl, VT,
2390 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2391 DAG.getNode(ISD::AND, dl, VT,
2392 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2398 // for now, we do this:
2399 // x = x | (x >> 1);
2400 // x = x | (x >> 2);
2402 // x = x | (x >>16);
2403 // x = x | (x >>32); // for 64-bit input
2404 // return popcount(~x);
2406 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2407 MVT VT = Op.getValueType();
2408 MVT ShVT = TLI.getShiftAmountTy();
2409 unsigned len = VT.getSizeInBits();
2410 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2411 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2412 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2413 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2415 Op = DAG.getNOT(dl, Op, VT);
2416 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2419 // for now, we use: { return popcount(~x & (x - 1)); }
2420 // unless the target has ctlz but not ctpop, in which case we use:
2421 // { return 32 - nlz(~x & (x-1)); }
2422 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2423 MVT VT = Op.getValueType();
2424 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2425 DAG.getNOT(dl, Op, VT),
2426 DAG.getNode(ISD::SUB, dl, VT, Op,
2427 DAG.getConstant(1, VT)));
2428 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2429 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2430 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2431 return DAG.getNode(ISD::SUB, dl, VT,
2432 DAG.getConstant(VT.getSizeInBits(), VT),
2433 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2434 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2439 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2440 SmallVectorImpl<SDValue> &Results) {
2441 DebugLoc dl = Node->getDebugLoc();
2442 SDValue Tmp1, Tmp2, Tmp3;
2443 switch (Node->getOpcode()) {
2447 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2448 Results.push_back(Tmp1);
2451 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2453 case ISD::FRAMEADDR:
2454 case ISD::RETURNADDR:
2455 case ISD::FRAME_TO_ARGS_OFFSET:
2456 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2458 case ISD::FLT_ROUNDS_:
2459 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2461 case ISD::EH_RETURN:
2463 case ISD::DBG_LABEL:
2466 case ISD::MEMBARRIER:
2468 Results.push_back(Node->getOperand(0));
2470 case ISD::DBG_STOPPOINT:
2471 Results.push_back(ExpandDBG_STOPPOINT(Node));
2473 case ISD::DYNAMIC_STACKALLOC:
2474 ExpandDYNAMIC_STACKALLOC(Node, Results);
2476 case ISD::MERGE_VALUES:
2477 for (unsigned i = 0; i < Node->getNumValues(); i++)
2478 Results.push_back(Node->getOperand(i));
2481 MVT VT = Node->getValueType(0);
2483 Results.push_back(DAG.getConstant(0, VT));
2484 else if (VT.isFloatingPoint())
2485 Results.push_back(DAG.getConstantFP(0, VT));
2487 assert(0 && "Unknown value type!");
2491 // If this operation is not supported, lower it to 'abort()' call
2492 TargetLowering::ArgListTy Args;
2493 std::pair<SDValue, SDValue> CallResult =
2494 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy,
2495 false, false, false, false, CallingConv::C, false,
2496 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2498 Results.push_back(CallResult.second);
2502 case ISD::BIT_CONVERT:
2503 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2504 Node->getValueType(0), dl);
2505 Results.push_back(Tmp1);
2507 case ISD::FP_EXTEND:
2508 Tmp1 = EmitStackConvert(Node->getOperand(0),
2509 Node->getOperand(0).getValueType(),
2510 Node->getValueType(0), dl);
2511 Results.push_back(Tmp1);
2513 case ISD::SIGN_EXTEND_INREG: {
2514 // NOTE: we could fall back on load/store here too for targets without
2515 // SAR. However, it is doubtful that any exist.
2516 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2517 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
2518 ExtraVT.getSizeInBits();
2519 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2520 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2521 Node->getOperand(0), ShiftCst);
2522 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2523 Results.push_back(Tmp1);
2526 case ISD::FP_ROUND_INREG: {
2527 // The only way we can lower this is to turn it into a TRUNCSTORE,
2528 // EXTLOAD pair, targetting a temporary location (a stack slot).
2530 // NOTE: there is a choice here between constantly creating new stack
2531 // slots and always reusing the same one. We currently always create
2532 // new ones, as reuse may inhibit scheduling.
2533 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2534 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2535 Node->getValueType(0), dl);
2536 Results.push_back(Tmp1);
2539 case ISD::SINT_TO_FP:
2540 case ISD::UINT_TO_FP:
2541 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2542 Node->getOperand(0), Node->getValueType(0), dl);
2543 Results.push_back(Tmp1);
2545 case ISD::FP_TO_UINT: {
2546 SDValue True, False;
2547 MVT VT = Node->getOperand(0).getValueType();
2548 MVT NVT = Node->getValueType(0);
2549 const uint64_t zero[] = {0, 0};
2550 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2551 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2552 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2553 Tmp1 = DAG.getConstantFP(apf, VT);
2554 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2555 Node->getOperand(0),
2557 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2558 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2559 DAG.getNode(ISD::FSUB, dl, VT,
2560 Node->getOperand(0), Tmp1));
2561 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2562 DAG.getConstant(x, NVT));
2563 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2564 Results.push_back(Tmp1);
2568 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2569 MVT VT = Node->getValueType(0);
2570 Tmp1 = Node->getOperand(0);
2571 Tmp2 = Node->getOperand(1);
2572 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
2573 // Increment the pointer, VAList, to the next vaarg
2574 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2575 DAG.getConstant(TLI.getTargetData()->
2576 getTypeAllocSize(VT.getTypeForMVT()),
2577 TLI.getPointerTy()));
2578 // Store the incremented VAList to the legalized pointer
2579 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
2580 // Load the actual argument out of the pointer VAList
2581 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
2582 Results.push_back(Results[0].getValue(1));
2586 // This defaults to loading a pointer from the input and storing it to the
2587 // output, returning the chain.
2588 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2589 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2590 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2591 Node->getOperand(2), VS, 0);
2592 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
2593 Results.push_back(Tmp1);
2596 case ISD::EXTRACT_VECTOR_ELT:
2597 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2598 // This must be an access of the only element. Return it.
2599 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2600 Node->getOperand(0));
2602 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2603 Results.push_back(Tmp1);
2605 case ISD::EXTRACT_SUBVECTOR:
2606 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2608 case ISD::CONCAT_VECTORS: {
2609 // Use extract/insert/build vector for now. We might try to be
2610 // more clever later.
2611 SmallVector<SDValue, 8> Ops;
2612 unsigned NumOperands = Node->getNumOperands();
2613 for (unsigned i=0; i < NumOperands; ++i) {
2614 SDValue SubOp = Node->getOperand(i);
2615 MVT VVT = SubOp.getNode()->getValueType(0);
2616 MVT EltVT = VVT.getVectorElementType();
2617 unsigned NumSubElem = VVT.getVectorNumElements();
2618 for (unsigned j=0; j < NumSubElem; ++j) {
2619 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
2620 DAG.getIntPtrConstant(j)));
2623 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
2624 &Ops[0], Ops.size());
2625 Results.push_back(Tmp1);
2628 case ISD::SCALAR_TO_VECTOR:
2629 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2631 case ISD::INSERT_VECTOR_ELT:
2632 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2633 Node->getOperand(1),
2634 Node->getOperand(2), dl));
2636 case ISD::VECTOR_SHUFFLE: {
2637 SmallVector<int, 8> Mask;
2638 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2640 MVT VT = Node->getValueType(0);
2641 MVT EltVT = VT.getVectorElementType();
2642 unsigned NumElems = VT.getVectorNumElements();
2643 SmallVector<SDValue, 8> Ops;
2644 for (unsigned i = 0; i != NumElems; ++i) {
2646 Ops.push_back(DAG.getUNDEF(EltVT));
2649 unsigned Idx = Mask[i];
2651 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2652 Node->getOperand(0),
2653 DAG.getIntPtrConstant(Idx)));
2655 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2656 Node->getOperand(1),
2657 DAG.getIntPtrConstant(Idx - NumElems)));
2659 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2660 Results.push_back(Tmp1);
2663 case ISD::EXTRACT_ELEMENT: {
2664 MVT OpTy = Node->getOperand(0).getValueType();
2665 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2667 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2668 DAG.getConstant(OpTy.getSizeInBits()/2,
2669 TLI.getShiftAmountTy()));
2670 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2673 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2674 Node->getOperand(0));
2676 Results.push_back(Tmp1);
2679 case ISD::STACKSAVE:
2680 // Expand to CopyFromReg if the target set
2681 // StackPointerRegisterToSaveRestore.
2682 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2683 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2684 Node->getValueType(0)));
2685 Results.push_back(Results[0].getValue(1));
2687 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2688 Results.push_back(Node->getOperand(0));
2691 case ISD::STACKRESTORE:
2692 // Expand to CopyToReg if the target set
2693 // StackPointerRegisterToSaveRestore.
2694 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2695 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2696 Node->getOperand(1)));
2698 Results.push_back(Node->getOperand(0));
2701 case ISD::FCOPYSIGN:
2702 Results.push_back(ExpandFCOPYSIGN(Node));
2705 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2706 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2707 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2708 Node->getOperand(0));
2709 Results.push_back(Tmp1);
2712 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2713 MVT VT = Node->getValueType(0);
2714 Tmp1 = Node->getOperand(0);
2715 Tmp2 = DAG.getConstantFP(0.0, VT);
2716 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2717 Tmp1, Tmp2, ISD::SETUGT);
2718 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2719 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2720 Results.push_back(Tmp1);
2724 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2725 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2728 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2729 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2732 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2733 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2736 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2737 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2740 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2741 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2744 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2745 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2748 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2749 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2752 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2753 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2756 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2757 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2760 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2761 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2764 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2765 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2768 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2769 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2771 case ISD::FNEARBYINT:
2772 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2773 RTLIB::NEARBYINT_F64,
2774 RTLIB::NEARBYINT_F80,
2775 RTLIB::NEARBYINT_PPCF128));
2778 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2779 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2782 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2783 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2786 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2787 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2790 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2791 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2793 case ISD::ConstantFP: {
2794 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2795 // Check to see if this FP immediate is already legal.
2796 bool isLegal = false;
2797 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
2798 E = TLI.legal_fpimm_end(); I != E; ++I) {
2799 if (CFP->isExactlyValue(*I)) {
2804 // If this is a legal constant, turn it into a TargetConstantFP node.
2806 Results.push_back(SDValue(Node, 0));
2808 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2811 case ISD::EHSELECTION: {
2812 unsigned Reg = TLI.getExceptionSelectorRegister();
2813 assert(Reg && "Can't expand to unknown register!");
2814 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2815 Node->getValueType(0)));
2816 Results.push_back(Results[0].getValue(1));
2819 case ISD::EXCEPTIONADDR: {
2820 unsigned Reg = TLI.getExceptionAddressRegister();
2821 assert(Reg && "Can't expand to unknown register!");
2822 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2823 Node->getValueType(0)));
2824 Results.push_back(Results[0].getValue(1));
2828 MVT VT = Node->getValueType(0);
2829 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2830 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2831 "Don't know how to expand this subtraction!");
2832 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2833 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2834 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2835 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2840 MVT VT = Node->getValueType(0);
2841 SDVTList VTs = DAG.getVTList(VT, VT);
2842 bool isSigned = Node->getOpcode() == ISD::SREM;
2843 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2844 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2845 Tmp2 = Node->getOperand(0);
2846 Tmp3 = Node->getOperand(1);
2847 if (TLI.getOperationAction(DivOpc, VT) == TargetLowering::Legal) {
2849 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2850 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2851 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2852 } else if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2853 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2854 } else if (isSigned) {
2855 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
2856 RTLIB::SREM_I64, RTLIB::SREM_I128);
2858 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32,
2859 RTLIB::UREM_I64, RTLIB::UREM_I128);
2861 Results.push_back(Tmp1);
2866 bool isSigned = Node->getOpcode() == ISD::SDIV;
2867 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2868 MVT VT = Node->getValueType(0);
2869 SDVTList VTs = DAG.getVTList(VT, VT);
2870 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2871 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2872 Node->getOperand(1));
2874 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2875 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2877 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2878 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2879 Results.push_back(Tmp1);
2884 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2886 MVT VT = Node->getValueType(0);
2887 SDVTList VTs = DAG.getVTList(VT, VT);
2888 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2889 "If this wasn't legal, it shouldn't have been created!");
2890 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2891 Node->getOperand(1));
2892 Results.push_back(Tmp1.getValue(1));
2896 MVT VT = Node->getValueType(0);
2897 SDVTList VTs = DAG.getVTList(VT, VT);
2898 // See if multiply or divide can be lowered using two-result operations.
2899 // We just need the low half of the multiply; try both the signed
2900 // and unsigned forms. If the target supports both SMUL_LOHI and
2901 // UMUL_LOHI, form a preference by checking which forms of plain
2902 // MULH it supports.
2903 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2904 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2905 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2906 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2907 unsigned OpToUse = 0;
2908 if (HasSMUL_LOHI && !HasMULHS) {
2909 OpToUse = ISD::SMUL_LOHI;
2910 } else if (HasUMUL_LOHI && !HasMULHU) {
2911 OpToUse = ISD::UMUL_LOHI;
2912 } else if (HasSMUL_LOHI) {
2913 OpToUse = ISD::SMUL_LOHI;
2914 } else if (HasUMUL_LOHI) {
2915 OpToUse = ISD::UMUL_LOHI;
2918 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2919 Node->getOperand(1)));
2922 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32,
2923 RTLIB::MUL_I64, RTLIB::MUL_I128);
2924 Results.push_back(Tmp1);
2929 SDValue LHS = Node->getOperand(0);
2930 SDValue RHS = Node->getOperand(1);
2931 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2932 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2934 Results.push_back(Sum);
2935 MVT OType = Node->getValueType(1);
2937 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2939 // LHSSign -> LHS >= 0
2940 // RHSSign -> RHS >= 0
2941 // SumSign -> Sum >= 0
2944 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2946 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2948 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2949 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2950 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2951 Node->getOpcode() == ISD::SADDO ?
2952 ISD::SETEQ : ISD::SETNE);
2954 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2955 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2957 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2958 Results.push_back(Cmp);
2963 SDValue LHS = Node->getOperand(0);
2964 SDValue RHS = Node->getOperand(1);
2965 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2966 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2968 Results.push_back(Sum);
2969 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2970 Node->getOpcode () == ISD::UADDO ?
2971 ISD::SETULT : ISD::SETUGT));
2974 case ISD::BUILD_PAIR: {
2975 MVT PairTy = Node->getValueType(0);
2976 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2977 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2978 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2979 DAG.getConstant(PairTy.getSizeInBits()/2,
2980 TLI.getShiftAmountTy()));
2981 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2985 Tmp1 = Node->getOperand(0);
2986 Tmp2 = Node->getOperand(1);
2987 Tmp3 = Node->getOperand(2);
2988 if (Tmp1.getOpcode() == ISD::SETCC) {
2989 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2991 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2993 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2994 DAG.getConstant(0, Tmp1.getValueType()),
2995 Tmp2, Tmp3, ISD::SETNE);
2997 Results.push_back(Tmp1);
3000 SDValue Chain = Node->getOperand(0);
3001 SDValue Table = Node->getOperand(1);
3002 SDValue Index = Node->getOperand(2);
3004 MVT PTy = TLI.getPointerTy();
3005 MachineFunction &MF = DAG.getMachineFunction();
3006 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
3007 Index= DAG.getNode(ISD::MUL, dl, PTy,
3008 Index, DAG.getConstant(EntrySize, PTy));
3009 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3011 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
3012 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
3013 PseudoSourceValue::getJumpTable(), 0, MemVT);
3015 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3016 // For PIC, the sequence is:
3017 // BRIND(load(Jumptable + index) + RelocBase)
3018 // RelocBase can be JumpTable, GOT or some sort of global base.
3019 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
3020 TLI.getPICJumpTableRelocBase(Table, DAG));
3022 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
3023 Results.push_back(Tmp1);
3027 // Expand brcond's setcc into its constituent parts and create a BR_CC
3029 Tmp1 = Node->getOperand(0);
3030 Tmp2 = Node->getOperand(1);
3031 if (Tmp2.getOpcode() == ISD::SETCC) {
3032 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
3033 Tmp1, Tmp2.getOperand(2),
3034 Tmp2.getOperand(0), Tmp2.getOperand(1),
3035 Node->getOperand(2));
3037 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
3038 DAG.getCondCode(ISD::SETNE), Tmp2,
3039 DAG.getConstant(0, Tmp2.getValueType()),
3040 Node->getOperand(2));
3042 Results.push_back(Tmp1);
3044 case ISD::GLOBAL_OFFSET_TABLE:
3045 case ISD::GlobalAddress:
3046 case ISD::GlobalTLSAddress:
3047 case ISD::ExternalSymbol:
3048 case ISD::ConstantPool:
3049 case ISD::JumpTable:
3050 case ISD::INTRINSIC_W_CHAIN:
3051 case ISD::INTRINSIC_WO_CHAIN:
3052 case ISD::INTRINSIC_VOID:
3053 // FIXME: Custom lowering for these operations shouldn't return null!
3054 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
3055 Results.push_back(SDValue(Node, i));
3059 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
3060 SmallVectorImpl<SDValue> &Results) {
3061 MVT OVT = Node->getValueType(0);
3062 if (Node->getOpcode() == ISD::UINT_TO_FP ||
3063 Node->getOpcode() == ISD::SINT_TO_FP) {
3064 OVT = Node->getOperand(0).getValueType();
3066 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
3067 DebugLoc dl = Node->getDebugLoc();
3068 SDValue Tmp1, Tmp2, Tmp3;
3069 switch (Node->getOpcode()) {
3073 // Zero extend the argument.
3074 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
3075 // Perform the larger operation.
3076 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
3077 if (Node->getOpcode() == ISD::CTTZ) {
3078 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3079 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
3080 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
3082 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
3083 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
3084 } else if (Node->getOpcode() == ISD::CTLZ) {
3085 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3086 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
3087 DAG.getConstant(NVT.getSizeInBits() -
3088 OVT.getSizeInBits(), NVT));
3090 Results.push_back(Tmp1);
3093 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3094 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3095 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3096 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3097 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3098 Results.push_back(Tmp1);
3101 case ISD::FP_TO_UINT:
3102 case ISD::FP_TO_SINT:
3103 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3104 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3105 Results.push_back(Tmp1);
3107 case ISD::UINT_TO_FP:
3108 case ISD::SINT_TO_FP:
3109 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3110 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3111 Results.push_back(Tmp1);
3116 assert(OVT.isVector() && "Don't know how to promote scalar logic ops");
3117 // Bit convert each of the values to the new type.
3118 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3119 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3120 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3121 // Bit convert the result back the original type.
3122 Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1));
3125 unsigned ExtOp, TruncOp;
3126 if (Node->getValueType(0).isVector()) {
3127 ExtOp = ISD::BIT_CONVERT;
3128 TruncOp = ISD::BIT_CONVERT;
3129 } else if (Node->getValueType(0).isInteger()) {
3130 ExtOp = ISD::ANY_EXTEND;
3131 TruncOp = ISD::TRUNCATE;
3133 ExtOp = ISD::FP_EXTEND;
3134 TruncOp = ISD::FP_ROUND;
3136 Tmp1 = Node->getOperand(0);
3137 // Promote each of the values to the new type.
3138 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3139 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3140 // Perform the larger operation, then round down.
3141 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3142 if (TruncOp != ISD::FP_ROUND)
3143 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3145 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3146 DAG.getIntPtrConstant(0));
3147 Results.push_back(Tmp1);
3149 case ISD::VECTOR_SHUFFLE: {
3150 SmallVector<int, 8> Mask;
3151 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3153 // Cast the two input vectors.
3154 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3155 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3157 // Convert the shuffle mask to the right # elements.
3158 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3159 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3160 Results.push_back(Tmp1);
3166 // SelectionDAG::Legalize - This is the entry point for the file.
3168 void SelectionDAG::Legalize(bool TypesNeedLegalizing,
3169 CodeGenOpt::Level OptLevel) {
3170 /// run - This is the main entry point to this class.
3172 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();