1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 CodeGenOpt::Level OptLevel;
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDValue LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDValue, SDValue> LegalizedNodes;
88 void AddLegalizedOperand(SDValue From, SDValue To) {
89 LegalizedNodes.insert(std::make_pair(From, To));
90 // If someone requests legalization of the new node, return itself.
92 LegalizedNodes.insert(std::make_pair(To, To));
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(MVT VT) const {
102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
105 /// isTypeLegal - Return true if this type is legal on this target.
107 bool isTypeLegal(MVT VT) const {
108 return getTypeAction(VT) == Legal;
114 /// LegalizeOp - We know that the specified value has a legal type.
115 /// Recursively ensure that the operands have legal types, then return the
117 SDValue LegalizeOp(SDValue O);
119 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
120 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
121 /// is necessary to spill the vector being inserted into to memory, perform
122 /// the insert there, and then read the result back.
123 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
124 SDValue Idx, DebugLoc dl);
125 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
126 SDValue Idx, DebugLoc dl);
128 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
129 /// performs the same shuffe in terms of order or result bytes, but on a type
130 /// whose vector element type is narrower than the original shuffle type.
131 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
132 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
133 SDValue N1, SDValue N2,
134 SmallVectorImpl<int> &Mask) const;
136 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
137 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
139 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
142 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
143 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
144 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
145 RTLIB::Libcall Call_PPCF128);
146 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16,
147 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
148 RTLIB::Libcall Call_I128);
150 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
151 SDValue ExpandBUILD_VECTOR(SDNode *Node);
152 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
153 SDValue ExpandDBG_STOPPOINT(SDNode *Node);
154 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
155 SmallVectorImpl<SDValue> &Results);
156 SDValue ExpandFCOPYSIGN(SDNode *Node);
157 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
159 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
161 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
164 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
165 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
167 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
169 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
170 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
174 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
175 /// performs the same shuffe in terms of order or result bytes, but on a type
176 /// whose vector element type is narrower than the original shuffle type.
177 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
179 SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
180 SDValue N1, SDValue N2,
181 SmallVectorImpl<int> &Mask) const {
182 MVT EltVT = NVT.getVectorElementType();
183 unsigned NumMaskElts = VT.getVectorNumElements();
184 unsigned NumDestElts = NVT.getVectorNumElements();
185 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
187 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
189 if (NumEltsGrowth == 1)
190 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
192 SmallVector<int, 8> NewMask;
193 for (unsigned i = 0; i != NumMaskElts; ++i) {
195 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
197 NewMask.push_back(-1);
199 NewMask.push_back(Idx * NumEltsGrowth + j);
202 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
203 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
204 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
207 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
208 CodeGenOpt::Level ol)
209 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
210 ValueTypeActions(TLI.getValueTypeActions()) {
211 assert(MVT::LAST_VALUETYPE <= 32 &&
212 "Too many value types for ValueTypeActions to hold!");
215 void SelectionDAGLegalize::LegalizeDAG() {
216 LastCALLSEQ_END = DAG.getEntryNode();
217 IsLegalizingCall = false;
219 // The legalize process is inherently a bottom-up recursive process (users
220 // legalize their uses before themselves). Given infinite stack space, we
221 // could just start legalizing on the root and traverse the whole graph. In
222 // practice however, this causes us to run out of stack space on large basic
223 // blocks. To avoid this problem, compute an ordering of the nodes where each
224 // node is only legalized after all of its operands are legalized.
225 DAG.AssignTopologicalOrder();
226 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
227 E = prior(DAG.allnodes_end()); I != next(E); ++I)
228 LegalizeOp(SDValue(I, 0));
230 // Finally, it's possible the root changed. Get the new root.
231 SDValue OldRoot = DAG.getRoot();
232 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
233 DAG.setRoot(LegalizedNodes[OldRoot]);
235 LegalizedNodes.clear();
237 // Remove dead nodes now.
238 DAG.RemoveDeadNodes();
242 /// FindCallEndFromCallStart - Given a chained node that is part of a call
243 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
244 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
245 if (Node->getOpcode() == ISD::CALLSEQ_END)
247 if (Node->use_empty())
248 return 0; // No CallSeqEnd
250 // The chain is usually at the end.
251 SDValue TheChain(Node, Node->getNumValues()-1);
252 if (TheChain.getValueType() != MVT::Other) {
253 // Sometimes it's at the beginning.
254 TheChain = SDValue(Node, 0);
255 if (TheChain.getValueType() != MVT::Other) {
256 // Otherwise, hunt for it.
257 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
258 if (Node->getValueType(i) == MVT::Other) {
259 TheChain = SDValue(Node, i);
263 // Otherwise, we walked into a node without a chain.
264 if (TheChain.getValueType() != MVT::Other)
269 for (SDNode::use_iterator UI = Node->use_begin(),
270 E = Node->use_end(); UI != E; ++UI) {
272 // Make sure to only follow users of our token chain.
274 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
275 if (User->getOperand(i) == TheChain)
276 if (SDNode *Result = FindCallEndFromCallStart(User))
282 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
283 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
284 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
285 assert(Node && "Didn't find callseq_start for a call??");
286 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
288 assert(Node->getOperand(0).getValueType() == MVT::Other &&
289 "Node doesn't have a token chain argument!");
290 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
293 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
294 /// see if any uses can reach Dest. If no dest operands can get to dest,
295 /// legalize them, legalize ourself, and return false, otherwise, return true.
297 /// Keep track of the nodes we fine that actually do lead to Dest in
298 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
300 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
301 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
302 if (N == Dest) return true; // N certainly leads to Dest :)
304 // If we've already processed this node and it does lead to Dest, there is no
305 // need to reprocess it.
306 if (NodesLeadingTo.count(N)) return true;
308 // If the first result of this node has been already legalized, then it cannot
310 if (LegalizedNodes.count(SDValue(N, 0))) return false;
312 // Okay, this node has not already been legalized. Check and legalize all
313 // operands. If none lead to Dest, then we can legalize this node.
314 bool OperandsLeadToDest = false;
315 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
316 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
317 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
319 if (OperandsLeadToDest) {
320 NodesLeadingTo.insert(N);
324 // Okay, this node looks safe, legalize it and return false.
325 LegalizeOp(SDValue(N, 0));
329 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
330 /// a load from the constant pool.
331 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
332 SelectionDAG &DAG, const TargetLowering &TLI) {
334 DebugLoc dl = CFP->getDebugLoc();
336 // If a FP immediate is precise when represented as a float and if the
337 // target can do an extending load from float to double, we put it into
338 // the constant pool as a float, even if it's is statically typed as a
339 // double. This shrinks FP constants and canonicalizes them for targets where
340 // an FP extending load is the same cost as a normal load (such as on the x87
341 // fp stack or PPC FP unit).
342 MVT VT = CFP->getValueType(0);
343 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
345 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
346 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
347 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
352 while (SVT != MVT::f32) {
353 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
354 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
355 // Only do this if the target has a native EXTLOAD instruction from
357 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
358 TLI.ShouldShrinkFPConstant(OrigVT)) {
359 const Type *SType = SVT.getTypeForMVT();
360 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
366 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
367 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
369 return DAG.getExtLoad(ISD::EXTLOAD, dl,
370 OrigVT, DAG.getEntryNode(),
371 CPIdx, PseudoSourceValue::getConstantPool(),
372 0, VT, false, Alignment);
373 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
374 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
377 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
379 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
380 const TargetLowering &TLI) {
381 SDValue Chain = ST->getChain();
382 SDValue Ptr = ST->getBasePtr();
383 SDValue Val = ST->getValue();
384 MVT VT = Val.getValueType();
385 int Alignment = ST->getAlignment();
386 int SVOffset = ST->getSrcValueOffset();
387 DebugLoc dl = ST->getDebugLoc();
388 if (ST->getMemoryVT().isFloatingPoint() ||
389 ST->getMemoryVT().isVector()) {
390 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
391 if (TLI.isTypeLegal(intVT)) {
392 // Expand to a bitconvert of the value to the integer type of the
393 // same size, then a (misaligned) int store.
394 // FIXME: Does not handle truncating floating point stores!
395 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
396 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
397 SVOffset, ST->isVolatile(), Alignment);
399 // Do a (aligned) store to a stack slot, then copy from the stack slot
400 // to the final destination using (unaligned) integer loads and stores.
401 MVT StoredVT = ST->getMemoryVT();
403 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
404 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
405 unsigned RegBytes = RegVT.getSizeInBits() / 8;
406 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
408 // Make sure the stack slot is also aligned for the register type.
409 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
411 // Perform the original store, only redirected to the stack slot.
412 SDValue Store = DAG.getTruncStore(Chain, dl,
413 Val, StackPtr, NULL, 0, StoredVT);
414 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
415 SmallVector<SDValue, 8> Stores;
418 // Do all but one copies using the full register width.
419 for (unsigned i = 1; i < NumRegs; i++) {
420 // Load one integer register's worth from the stack slot.
421 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
422 // Store it to the final location. Remember the store.
423 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
424 ST->getSrcValue(), SVOffset + Offset,
426 MinAlign(ST->getAlignment(), Offset)));
427 // Increment the pointers.
429 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
431 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
434 // The last store may be partial. Do a truncating store. On big-endian
435 // machines this requires an extending load from the stack slot to ensure
436 // that the bits are in the right place.
437 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
439 // Load from the stack slot.
440 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
443 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
444 ST->getSrcValue(), SVOffset + Offset,
445 MemVT, ST->isVolatile(),
446 MinAlign(ST->getAlignment(), Offset)));
447 // The order of the stores doesn't matter - say it with a TokenFactor.
448 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
452 assert(ST->getMemoryVT().isInteger() &&
453 !ST->getMemoryVT().isVector() &&
454 "Unaligned store of unknown type.");
455 // Get the half-size VT
457 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
458 int NumBits = NewStoredVT.getSizeInBits();
459 int IncrementSize = NumBits / 8;
461 // Divide the stored value in two parts.
462 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
464 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
466 // Store the two parts
467 SDValue Store1, Store2;
468 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
469 ST->getSrcValue(), SVOffset, NewStoredVT,
470 ST->isVolatile(), Alignment);
471 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
472 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
473 Alignment = MinAlign(Alignment, IncrementSize);
474 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
475 ST->getSrcValue(), SVOffset + IncrementSize,
476 NewStoredVT, ST->isVolatile(), Alignment);
478 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
481 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
483 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
484 const TargetLowering &TLI) {
485 int SVOffset = LD->getSrcValueOffset();
486 SDValue Chain = LD->getChain();
487 SDValue Ptr = LD->getBasePtr();
488 MVT VT = LD->getValueType(0);
489 MVT LoadedVT = LD->getMemoryVT();
490 DebugLoc dl = LD->getDebugLoc();
491 if (VT.isFloatingPoint() || VT.isVector()) {
492 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
493 if (TLI.isTypeLegal(intVT)) {
494 // Expand to a (misaligned) integer load of the same size,
495 // then bitconvert to floating point or vector.
496 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
497 SVOffset, LD->isVolatile(),
499 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
500 if (VT.isFloatingPoint() && LoadedVT != VT)
501 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
503 SDValue Ops[] = { Result, Chain };
504 return DAG.getMergeValues(Ops, 2, dl);
506 // Copy the value to a (aligned) stack slot using (unaligned) integer
507 // loads and stores, then do a (aligned) load from the stack slot.
508 MVT RegVT = TLI.getRegisterType(intVT);
509 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
510 unsigned RegBytes = RegVT.getSizeInBits() / 8;
511 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
513 // Make sure the stack slot is also aligned for the register type.
514 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
516 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
517 SmallVector<SDValue, 8> Stores;
518 SDValue StackPtr = StackBase;
521 // Do all but one copies using the full register width.
522 for (unsigned i = 1; i < NumRegs; i++) {
523 // Load one integer register's worth from the original location.
524 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
525 SVOffset + Offset, LD->isVolatile(),
526 MinAlign(LD->getAlignment(), Offset));
527 // Follow the load with a store to the stack slot. Remember the store.
528 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
530 // Increment the pointers.
532 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
533 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
537 // The last copy may be partial. Do an extending load.
538 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
539 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
540 LD->getSrcValue(), SVOffset + Offset,
541 MemVT, LD->isVolatile(),
542 MinAlign(LD->getAlignment(), Offset));
543 // Follow the load with a store to the stack slot. Remember the store.
544 // On big-endian machines this requires a truncating store to ensure
545 // that the bits end up in the right place.
546 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
549 // The order of the stores doesn't matter - say it with a TokenFactor.
550 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
553 // Finally, perform the original load only redirected to the stack slot.
554 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
557 // Callers expect a MERGE_VALUES node.
558 SDValue Ops[] = { Load, TF };
559 return DAG.getMergeValues(Ops, 2, dl);
562 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
563 "Unaligned load of unsupported type.");
565 // Compute the new VT that is half the size of the old one. This is an
567 unsigned NumBits = LoadedVT.getSizeInBits();
569 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
572 unsigned Alignment = LD->getAlignment();
573 unsigned IncrementSize = NumBits / 8;
574 ISD::LoadExtType HiExtType = LD->getExtensionType();
576 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
577 if (HiExtType == ISD::NON_EXTLOAD)
578 HiExtType = ISD::ZEXTLOAD;
580 // Load the value in two parts
582 if (TLI.isLittleEndian()) {
583 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
584 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
585 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
586 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
587 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
588 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
589 MinAlign(Alignment, IncrementSize));
591 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
592 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
593 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
594 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
595 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
596 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
597 MinAlign(Alignment, IncrementSize));
600 // aggregate the two parts
601 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
602 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
603 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
605 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
608 SDValue Ops[] = { Result, TF };
609 return DAG.getMergeValues(Ops, 2, dl);
612 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
613 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
614 /// is necessary to spill the vector being inserted into to memory, perform
615 /// the insert there, and then read the result back.
616 SDValue SelectionDAGLegalize::
617 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
623 // If the target doesn't support this, we have to spill the input vector
624 // to a temporary stack slot, update the element, then reload it. This is
625 // badness. We could also load the value into a vector register (either
626 // with a "move to register" or "extload into register" instruction, then
627 // permute it into place, if the idx is a constant and if the idx is
628 // supported by the target.
629 MVT VT = Tmp1.getValueType();
630 MVT EltVT = VT.getVectorElementType();
631 MVT IdxVT = Tmp3.getValueType();
632 MVT PtrVT = TLI.getPointerTy();
633 SDValue StackPtr = DAG.CreateStackTemporary(VT);
635 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
638 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
639 PseudoSourceValue::getFixedStack(SPFI), 0);
641 // Truncate or zero extend offset to target pointer type.
642 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
643 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
644 // Add the offset to the index.
645 unsigned EltSize = EltVT.getSizeInBits()/8;
646 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
647 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
648 // Store the scalar value.
649 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
650 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
651 // Load the updated vector.
652 return DAG.getLoad(VT, dl, Ch, StackPtr,
653 PseudoSourceValue::getFixedStack(SPFI), 0);
657 SDValue SelectionDAGLegalize::
658 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
659 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
660 // SCALAR_TO_VECTOR requires that the type of the value being inserted
661 // match the element type of the vector being created, except for
662 // integers in which case the inserted value can be over width.
663 MVT EltVT = Vec.getValueType().getVectorElementType();
664 if (Val.getValueType() == EltVT ||
665 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
666 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
667 Vec.getValueType(), Val);
669 unsigned NumElts = Vec.getValueType().getVectorNumElements();
670 // We generate a shuffle of InVec and ScVec, so the shuffle mask
671 // should be 0,1,2,3,4,5... with the appropriate element replaced with
673 SmallVector<int, 8> ShufOps;
674 for (unsigned i = 0; i != NumElts; ++i)
675 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
677 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
681 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
684 /// LegalizeOp - We know that the specified value has a legal type, and
685 /// that its operands are legal. Now ensure that the operation itself
686 /// is legal, recursively ensuring that the operands' operations remain
688 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
689 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
692 SDNode *Node = Op.getNode();
693 DebugLoc dl = Node->getDebugLoc();
695 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
696 assert(getTypeAction(Node->getValueType(i)) == Legal &&
697 "Unexpected illegal type!");
699 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
700 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
701 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
702 "Unexpected illegal type!");
704 // Note that LegalizeOp may be reentered even from single-use nodes, which
705 // means that we always must cache transformed nodes.
706 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
707 if (I != LegalizedNodes.end()) return I->second;
709 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
711 bool isCustom = false;
713 // Figure out the correct action; the way to query this varies by opcode
714 TargetLowering::LegalizeAction Action;
715 bool SimpleFinishLegalizing = true;
716 switch (Node->getOpcode()) {
717 case ISD::INTRINSIC_W_CHAIN:
718 case ISD::INTRINSIC_WO_CHAIN:
719 case ISD::INTRINSIC_VOID:
722 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
724 case ISD::SINT_TO_FP:
725 case ISD::UINT_TO_FP:
726 case ISD::EXTRACT_VECTOR_ELT:
727 Action = TLI.getOperationAction(Node->getOpcode(),
728 Node->getOperand(0).getValueType());
730 case ISD::FP_ROUND_INREG:
731 case ISD::SIGN_EXTEND_INREG: {
732 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
733 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
739 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
740 Node->getOpcode() == ISD::SETCC ? 2 : 1;
741 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
742 MVT OpVT = Node->getOperand(CompareOperand).getValueType();
743 ISD::CondCode CCCode =
744 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
745 Action = TLI.getCondCodeAction(CCCode, OpVT);
746 if (Action == TargetLowering::Legal) {
747 if (Node->getOpcode() == ISD::SELECT_CC)
748 Action = TLI.getOperationAction(Node->getOpcode(),
749 Node->getValueType(0));
751 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
757 // FIXME: Model these properly. LOAD and STORE are complicated, and
758 // STORE expects the unlegalized operand in some cases.
759 SimpleFinishLegalizing = false;
761 case ISD::CALLSEQ_START:
762 case ISD::CALLSEQ_END:
763 // FIXME: This shouldn't be necessary. These nodes have special properties
764 // dealing with the recursive nature of legalization. Removing this
765 // special case should be done as part of making LegalizeDAG non-recursive.
766 SimpleFinishLegalizing = false;
769 // FIXME: Legalization for calls requires custom-lowering the call before
770 // legalizing the operands! (I haven't looked into precisely why.)
771 SimpleFinishLegalizing = false;
773 case ISD::EXTRACT_ELEMENT:
774 case ISD::FLT_ROUNDS_:
782 case ISD::MERGE_VALUES:
784 case ISD::FRAME_TO_ARGS_OFFSET:
785 // These operations lie about being legal: when they claim to be legal,
786 // they should actually be expanded.
787 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
788 if (Action == TargetLowering::Legal)
789 Action = TargetLowering::Expand;
791 case ISD::TRAMPOLINE:
793 case ISD::RETURNADDR:
794 case ISD::FORMAL_ARGUMENTS:
795 // These operations lie about being legal: when they claim to be legal,
796 // they should actually be custom-lowered.
797 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
798 if (Action == TargetLowering::Legal)
799 Action = TargetLowering::Custom;
801 case ISD::BUILD_VECTOR:
802 // A weird case: legalization for BUILD_VECTOR never legalizes the
804 // FIXME: This really sucks... changing it isn't semantically incorrect,
805 // but it massively pessimizes the code for floating-point BUILD_VECTORs
806 // because ConstantFP operands get legalized into constant pool loads
807 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
808 // though, because BUILD_VECTORS usually get lowered into other nodes
809 // which get legalized properly.
810 SimpleFinishLegalizing = false;
813 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
814 Action = TargetLowering::Legal;
816 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
821 if (SimpleFinishLegalizing) {
822 SmallVector<SDValue, 8> Ops, ResultVals;
823 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
824 Ops.push_back(LegalizeOp(Node->getOperand(i)));
825 switch (Node->getOpcode()) {
833 // Branches tweak the chain to include LastCALLSEQ_END
834 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
836 Ops[0] = LegalizeOp(Ops[0]);
837 LastCALLSEQ_END = DAG.getEntryNode();
844 // Legalizing shifts/rotates requires adjusting the shift amount
845 // to the appropriate width.
846 if (!Ops[1].getValueType().isVector())
847 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
851 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
854 case TargetLowering::Legal:
855 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
856 ResultVals.push_back(Result.getValue(i));
858 case TargetLowering::Custom:
859 // FIXME: The handling for custom lowering with multiple results is
861 Tmp1 = TLI.LowerOperation(Result, DAG);
862 if (Tmp1.getNode()) {
863 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
865 ResultVals.push_back(Tmp1);
867 ResultVals.push_back(Tmp1.getValue(i));
873 case TargetLowering::Expand:
874 ExpandNode(Result.getNode(), ResultVals);
876 case TargetLowering::Promote:
877 PromoteNode(Result.getNode(), ResultVals);
880 if (!ResultVals.empty()) {
881 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
882 if (ResultVals[i] != SDValue(Node, i))
883 ResultVals[i] = LegalizeOp(ResultVals[i]);
884 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
886 return ResultVals[Op.getResNo()];
890 switch (Node->getOpcode()) {
893 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
895 assert(0 && "Do not know how to legalize this operator!");
898 // The only option for this is to custom lower it.
899 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
900 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
901 // A call within a calling sequence must be legalized to something
902 // other than the normal CALLSEQ_END. Violating this gets Legalize
903 // into an infinite loop.
904 assert ((!IsLegalizingCall ||
905 Node->getOpcode() != ISD::CALL ||
906 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
907 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
909 // The number of incoming and outgoing values should match; unless the final
910 // outgoing value is a flag.
911 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
912 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
913 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
915 "Lowering call/formal_arguments produced unexpected # results!");
917 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
918 // remember that we legalized all of them, so it doesn't get relegalized.
919 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
920 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
922 Tmp1 = LegalizeOp(Tmp3.getValue(i));
923 if (Op.getResNo() == i)
925 AddLegalizedOperand(SDValue(Node, i), Tmp1);
928 case ISD::BUILD_VECTOR:
929 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
930 default: assert(0 && "This action is not supported yet!");
931 case TargetLowering::Custom:
932 Tmp3 = TLI.LowerOperation(Result, DAG);
933 if (Tmp3.getNode()) {
938 case TargetLowering::Expand:
939 Result = ExpandBUILD_VECTOR(Result.getNode());
943 case ISD::CALLSEQ_START: {
944 SDNode *CallEnd = FindCallEndFromCallStart(Node);
946 // Recursively Legalize all of the inputs of the call end that do not lead
947 // to this call start. This ensures that any libcalls that need be inserted
948 // are inserted *before* the CALLSEQ_START.
949 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
950 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
951 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
955 // Now that we legalized all of the inputs (which may have inserted
956 // libcalls) create the new CALLSEQ_START node.
957 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
959 // Merge in the last call, to ensure that this call start after the last
961 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
962 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
963 Tmp1, LastCALLSEQ_END);
964 Tmp1 = LegalizeOp(Tmp1);
967 // Do not try to legalize the target-specific arguments (#1+).
968 if (Tmp1 != Node->getOperand(0)) {
969 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
971 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
974 // Remember that the CALLSEQ_START is legalized.
975 AddLegalizedOperand(Op.getValue(0), Result);
976 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
977 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
979 // Now that the callseq_start and all of the non-call nodes above this call
980 // sequence have been legalized, legalize the call itself. During this
981 // process, no libcalls can/will be inserted, guaranteeing that no calls
983 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
984 // Note that we are selecting this call!
985 LastCALLSEQ_END = SDValue(CallEnd, 0);
986 IsLegalizingCall = true;
988 // Legalize the call, starting from the CALLSEQ_END.
989 LegalizeOp(LastCALLSEQ_END);
990 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
993 case ISD::CALLSEQ_END:
994 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
995 // will cause this node to be legalized as well as handling libcalls right.
996 if (LastCALLSEQ_END.getNode() != Node) {
997 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
998 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
999 assert(I != LegalizedNodes.end() &&
1000 "Legalizing the call start should have legalized this node!");
1004 // Otherwise, the call start has been legalized and everything is going
1005 // according to plan. Just legalize ourselves normally here.
1006 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1007 // Do not try to legalize the target-specific arguments (#1+), except for
1008 // an optional flag input.
1009 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1010 if (Tmp1 != Node->getOperand(0)) {
1011 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1013 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1016 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1017 if (Tmp1 != Node->getOperand(0) ||
1018 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1019 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1022 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1025 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1026 // This finishes up call legalization.
1027 IsLegalizingCall = false;
1029 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1030 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1031 if (Node->getNumValues() == 2)
1032 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1033 return Result.getValue(Op.getResNo());
1035 LoadSDNode *LD = cast<LoadSDNode>(Node);
1036 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1037 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1039 ISD::LoadExtType ExtType = LD->getExtensionType();
1040 if (ExtType == ISD::NON_EXTLOAD) {
1041 MVT VT = Node->getValueType(0);
1042 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1043 Tmp3 = Result.getValue(0);
1044 Tmp4 = Result.getValue(1);
1046 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1047 default: assert(0 && "This action is not supported yet!");
1048 case TargetLowering::Legal:
1049 // If this is an unaligned load and the target doesn't support it,
1051 if (!TLI.allowsUnalignedMemoryAccesses()) {
1052 unsigned ABIAlignment = TLI.getTargetData()->
1053 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1054 if (LD->getAlignment() < ABIAlignment){
1055 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1057 Tmp3 = Result.getOperand(0);
1058 Tmp4 = Result.getOperand(1);
1059 Tmp3 = LegalizeOp(Tmp3);
1060 Tmp4 = LegalizeOp(Tmp4);
1064 case TargetLowering::Custom:
1065 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1066 if (Tmp1.getNode()) {
1067 Tmp3 = LegalizeOp(Tmp1);
1068 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1071 case TargetLowering::Promote: {
1072 // Only promote a load of vector type to another.
1073 assert(VT.isVector() && "Cannot promote this load!");
1074 // Change base type to a different vector type.
1075 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1077 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1078 LD->getSrcValueOffset(),
1079 LD->isVolatile(), LD->getAlignment());
1080 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1081 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1085 // Since loads produce two values, make sure to remember that we
1086 // legalized both of them.
1087 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1088 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1089 return Op.getResNo() ? Tmp4 : Tmp3;
1091 MVT SrcVT = LD->getMemoryVT();
1092 unsigned SrcWidth = SrcVT.getSizeInBits();
1093 int SVOffset = LD->getSrcValueOffset();
1094 unsigned Alignment = LD->getAlignment();
1095 bool isVolatile = LD->isVolatile();
1097 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1098 // Some targets pretend to have an i1 loading operation, and actually
1099 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1100 // bits are guaranteed to be zero; it helps the optimizers understand
1101 // that these bits are zero. It is also useful for EXTLOAD, since it
1102 // tells the optimizers that those bits are undefined. It would be
1103 // nice to have an effective generic way of getting these benefits...
1104 // Until such a way is found, don't insist on promoting i1 here.
1105 (SrcVT != MVT::i1 ||
1106 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1107 // Promote to a byte-sized load if not loading an integral number of
1108 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1109 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1110 MVT NVT = MVT::getIntegerVT(NewWidth);
1113 // The extra bits are guaranteed to be zero, since we stored them that
1114 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1116 ISD::LoadExtType NewExtType =
1117 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1119 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1120 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1121 NVT, isVolatile, Alignment);
1123 Ch = Result.getValue(1); // The chain.
1125 if (ExtType == ISD::SEXTLOAD)
1126 // Having the top bits zero doesn't help when sign extending.
1127 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1128 Result.getValueType(),
1129 Result, DAG.getValueType(SrcVT));
1130 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1131 // All the top bits are guaranteed to be zero - inform the optimizers.
1132 Result = DAG.getNode(ISD::AssertZext, dl,
1133 Result.getValueType(), Result,
1134 DAG.getValueType(SrcVT));
1136 Tmp1 = LegalizeOp(Result);
1137 Tmp2 = LegalizeOp(Ch);
1138 } else if (SrcWidth & (SrcWidth - 1)) {
1139 // If not loading a power-of-2 number of bits, expand as two loads.
1140 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
1141 "Unsupported extload!");
1142 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1143 assert(RoundWidth < SrcWidth);
1144 unsigned ExtraWidth = SrcWidth - RoundWidth;
1145 assert(ExtraWidth < RoundWidth);
1146 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1147 "Load size not an integral number of bytes!");
1148 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1149 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1151 unsigned IncrementSize;
1153 if (TLI.isLittleEndian()) {
1154 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1155 // Load the bottom RoundWidth bits.
1156 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1157 Node->getValueType(0), Tmp1, Tmp2,
1158 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1161 // Load the remaining ExtraWidth bits.
1162 IncrementSize = RoundWidth / 8;
1163 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1164 DAG.getIntPtrConstant(IncrementSize));
1165 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1166 LD->getSrcValue(), SVOffset + IncrementSize,
1167 ExtraVT, isVolatile,
1168 MinAlign(Alignment, IncrementSize));
1170 // Build a factor node to remember that this load is independent of the
1172 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1175 // Move the top bits to the right place.
1176 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1177 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1179 // Join the hi and lo parts.
1180 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1182 // Big endian - avoid unaligned loads.
1183 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1184 // Load the top RoundWidth bits.
1185 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1186 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1189 // Load the remaining ExtraWidth bits.
1190 IncrementSize = RoundWidth / 8;
1191 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1192 DAG.getIntPtrConstant(IncrementSize));
1193 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1194 Node->getValueType(0), Tmp1, Tmp2,
1195 LD->getSrcValue(), SVOffset + IncrementSize,
1196 ExtraVT, isVolatile,
1197 MinAlign(Alignment, IncrementSize));
1199 // Build a factor node to remember that this load is independent of the
1201 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1204 // Move the top bits to the right place.
1205 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1206 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1208 // Join the hi and lo parts.
1209 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1212 Tmp1 = LegalizeOp(Result);
1213 Tmp2 = LegalizeOp(Ch);
1215 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1216 default: assert(0 && "This action is not supported yet!");
1217 case TargetLowering::Custom:
1220 case TargetLowering::Legal:
1221 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1222 Tmp1 = Result.getValue(0);
1223 Tmp2 = Result.getValue(1);
1226 Tmp3 = TLI.LowerOperation(Result, DAG);
1227 if (Tmp3.getNode()) {
1228 Tmp1 = LegalizeOp(Tmp3);
1229 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1232 // If this is an unaligned load and the target doesn't support it,
1234 if (!TLI.allowsUnalignedMemoryAccesses()) {
1235 unsigned ABIAlignment = TLI.getTargetData()->
1236 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
1237 if (LD->getAlignment() < ABIAlignment){
1238 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1240 Tmp1 = Result.getOperand(0);
1241 Tmp2 = Result.getOperand(1);
1242 Tmp1 = LegalizeOp(Tmp1);
1243 Tmp2 = LegalizeOp(Tmp2);
1248 case TargetLowering::Expand:
1249 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1250 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1251 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1252 LD->getSrcValueOffset(),
1253 LD->isVolatile(), LD->getAlignment());
1254 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1255 Node->getValueType(0), Load);
1256 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1257 Tmp2 = LegalizeOp(Load.getValue(1));
1260 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1261 // Turn the unsupported load into an EXTLOAD followed by an explicit
1262 // zero/sign extend inreg.
1263 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1264 Tmp1, Tmp2, LD->getSrcValue(),
1265 LD->getSrcValueOffset(), SrcVT,
1266 LD->isVolatile(), LD->getAlignment());
1268 if (ExtType == ISD::SEXTLOAD)
1269 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1270 Result.getValueType(),
1271 Result, DAG.getValueType(SrcVT));
1273 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1274 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1275 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1280 // Since loads produce two values, make sure to remember that we legalized
1282 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1283 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1284 return Op.getResNo() ? Tmp2 : Tmp1;
1288 StoreSDNode *ST = cast<StoreSDNode>(Node);
1289 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1290 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1291 int SVOffset = ST->getSrcValueOffset();
1292 unsigned Alignment = ST->getAlignment();
1293 bool isVolatile = ST->isVolatile();
1295 if (!ST->isTruncatingStore()) {
1296 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1297 // FIXME: We shouldn't do this for TargetConstantFP's.
1298 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1299 // to phase ordering between legalized code and the dag combiner. This
1300 // probably means that we need to integrate dag combiner and legalizer
1302 // We generally can't do this one for long doubles.
1303 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1304 if (CFP->getValueType(0) == MVT::f32 &&
1305 getTypeAction(MVT::i32) == Legal) {
1306 Tmp3 = DAG.getConstant(CFP->getValueAPF().
1307 bitcastToAPInt().zextOrTrunc(32),
1309 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1310 SVOffset, isVolatile, Alignment);
1312 } else if (CFP->getValueType(0) == MVT::f64) {
1313 // If this target supports 64-bit registers, do a single 64-bit store.
1314 if (getTypeAction(MVT::i64) == Legal) {
1315 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
1316 zextOrTrunc(64), MVT::i64);
1317 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1318 SVOffset, isVolatile, Alignment);
1320 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
1321 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
1322 // stores. If the target supports neither 32- nor 64-bits, this
1323 // xform is certainly not worth it.
1324 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
1325 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
1326 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
1327 if (TLI.isBigEndian()) std::swap(Lo, Hi);
1329 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
1330 SVOffset, isVolatile, Alignment);
1331 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1332 DAG.getIntPtrConstant(4));
1333 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
1334 isVolatile, MinAlign(Alignment, 4U));
1336 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1343 Tmp3 = LegalizeOp(ST->getValue());
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1347 MVT VT = Tmp3.getValueType();
1348 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1349 default: assert(0 && "This action is not supported yet!");
1350 case TargetLowering::Legal:
1351 // If this is an unaligned store and the target doesn't support it,
1353 if (!TLI.allowsUnalignedMemoryAccesses()) {
1354 unsigned ABIAlignment = TLI.getTargetData()->
1355 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
1356 if (ST->getAlignment() < ABIAlignment)
1357 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1361 case TargetLowering::Custom:
1362 Tmp1 = TLI.LowerOperation(Result, DAG);
1363 if (Tmp1.getNode()) Result = Tmp1;
1365 case TargetLowering::Promote:
1366 assert(VT.isVector() && "Unknown legal promote case!");
1367 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1368 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1369 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1370 ST->getSrcValue(), SVOffset, isVolatile,
1377 Tmp3 = LegalizeOp(ST->getValue());
1379 MVT StVT = ST->getMemoryVT();
1380 unsigned StWidth = StVT.getSizeInBits();
1382 if (StWidth != StVT.getStoreSizeInBits()) {
1383 // Promote to a byte-sized store with upper bits zero if not
1384 // storing an integral number of bytes. For example, promote
1385 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1386 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
1387 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1388 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1389 SVOffset, NVT, isVolatile, Alignment);
1390 } else if (StWidth & (StWidth - 1)) {
1391 // If not storing a power-of-2 number of bits, expand as two stores.
1392 assert(StVT.isExtended() && !StVT.isVector() &&
1393 "Unsupported truncstore!");
1394 unsigned RoundWidth = 1 << Log2_32(StWidth);
1395 assert(RoundWidth < StWidth);
1396 unsigned ExtraWidth = StWidth - RoundWidth;
1397 assert(ExtraWidth < RoundWidth);
1398 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1399 "Store size not an integral number of bytes!");
1400 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1401 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1403 unsigned IncrementSize;
1405 if (TLI.isLittleEndian()) {
1406 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1407 // Store the bottom RoundWidth bits.
1408 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1410 isVolatile, Alignment);
1412 // Store the remaining ExtraWidth bits.
1413 IncrementSize = RoundWidth / 8;
1414 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1415 DAG.getIntPtrConstant(IncrementSize));
1416 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1417 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1418 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1419 SVOffset + IncrementSize, ExtraVT, isVolatile,
1420 MinAlign(Alignment, IncrementSize));
1422 // Big endian - avoid unaligned stores.
1423 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1424 // Store the top RoundWidth bits.
1425 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1426 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1427 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1428 SVOffset, RoundVT, isVolatile, Alignment);
1430 // Store the remaining ExtraWidth bits.
1431 IncrementSize = RoundWidth / 8;
1432 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1433 DAG.getIntPtrConstant(IncrementSize));
1434 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1435 SVOffset + IncrementSize, ExtraVT, isVolatile,
1436 MinAlign(Alignment, IncrementSize));
1439 // The order of the stores doesn't matter.
1440 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1442 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1443 Tmp2 != ST->getBasePtr())
1444 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1447 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1448 default: assert(0 && "This action is not supported yet!");
1449 case TargetLowering::Legal:
1450 // If this is an unaligned store and the target doesn't support it,
1452 if (!TLI.allowsUnalignedMemoryAccesses()) {
1453 unsigned ABIAlignment = TLI.getTargetData()->
1454 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
1455 if (ST->getAlignment() < ABIAlignment)
1456 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1460 case TargetLowering::Custom:
1461 Result = TLI.LowerOperation(Result, DAG);
1464 // TRUNCSTORE:i16 i32 -> STORE i16
1465 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1466 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1467 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1468 SVOffset, isVolatile, Alignment);
1476 assert(Result.getValueType() == Op.getValueType() &&
1477 "Bad legalization!");
1479 // Make sure that the generated code is itself legal.
1481 Result = LegalizeOp(Result);
1483 // Note that LegalizeOp may be reentered even from single-use nodes, which
1484 // means that we always must cache transformed nodes.
1485 AddLegalizedOperand(Op, Result);
1489 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1490 SDValue Vec = Op.getOperand(0);
1491 SDValue Idx = Op.getOperand(1);
1492 DebugLoc dl = Op.getDebugLoc();
1493 // Store the value to a temporary stack slot, then LOAD the returned part.
1494 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1495 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
1497 // Add the offset to the index.
1499 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1500 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1501 DAG.getConstant(EltSize, Idx.getValueType()));
1503 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1504 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1506 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1508 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1510 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
1513 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1514 DebugLoc dl = Node->getDebugLoc();
1515 SDValue Tmp1 = Node->getOperand(0);
1516 SDValue Tmp2 = Node->getOperand(1);
1517 assert((Tmp2.getValueType() == MVT::f32 ||
1518 Tmp2.getValueType() == MVT::f64) &&
1519 "Ugly special-cased code!");
1520 // Get the sign bit of the RHS.
1522 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1523 if (isTypeLegal(IVT)) {
1524 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1526 assert(isTypeLegal(TLI.getPointerTy()) &&
1527 (TLI.getPointerTy() == MVT::i32 ||
1528 TLI.getPointerTy() == MVT::i64) &&
1529 "Legal type for load?!");
1530 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1531 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1533 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1534 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1535 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1536 LoadPtr, DAG.getIntPtrConstant(4));
1537 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1538 Ch, LoadPtr, NULL, 0, MVT::i32);
1541 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1542 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1544 // Get the absolute value of the result.
1545 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1546 // Select between the nabs and abs value based on the sign bit of
1548 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1549 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1553 SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
1554 DebugLoc dl = Node->getDebugLoc();
1555 DwarfWriter *DW = DAG.getDwarfWriter();
1556 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1558 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1560 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1561 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1562 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1563 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1565 unsigned Line = DSP->getLine();
1566 unsigned Col = DSP->getColumn();
1568 if (OptLevel == CodeGenOpt::None) {
1569 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1570 // won't hurt anything.
1572 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
1573 DAG.getConstant(Line, MVT::i32),
1574 DAG.getConstant(Col, MVT::i32),
1575 DAG.getSrcValue(CU.getGV()));
1577 unsigned ID = DW->RecordSourceLine(Line, Col, CU);
1578 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID);
1582 return Node->getOperand(0);
1585 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1586 SmallVectorImpl<SDValue> &Results) {
1587 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1588 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1589 " not tell us which reg is the stack pointer!");
1590 DebugLoc dl = Node->getDebugLoc();
1591 MVT VT = Node->getValueType(0);
1592 SDValue Tmp1 = SDValue(Node, 0);
1593 SDValue Tmp2 = SDValue(Node, 1);
1594 SDValue Tmp3 = Node->getOperand(2);
1595 SDValue Chain = Tmp1.getOperand(0);
1597 // Chain the dynamic stack allocation so that it doesn't modify the stack
1598 // pointer when other instructions are using the stack.
1599 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1601 SDValue Size = Tmp2.getOperand(1);
1602 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1603 Chain = SP.getValue(1);
1604 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1605 unsigned StackAlign =
1606 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1607 if (Align > StackAlign)
1608 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1609 DAG.getConstant(-(uint64_t)Align, VT));
1610 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1611 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1613 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1614 DAG.getIntPtrConstant(0, true), SDValue());
1616 Results.push_back(Tmp1);
1617 Results.push_back(Tmp2);
1620 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1621 /// condition code CC on the current target. This routine assumes LHS and rHS
1622 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
1623 /// illegal condition code into AND / OR of multiple SETCC values.
1624 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
1625 SDValue &LHS, SDValue &RHS,
1628 MVT OpVT = LHS.getValueType();
1629 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1630 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1631 default: assert(0 && "Unknown condition code action!");
1632 case TargetLowering::Legal:
1635 case TargetLowering::Expand: {
1636 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1639 default: assert(0 && "Don't know how to expand this condition!"); abort();
1640 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1641 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1642 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1643 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1644 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1645 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1646 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1647 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1648 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1649 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1650 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1651 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1652 // FIXME: Implement more expansions.
1655 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1656 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1657 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1665 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1666 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1667 /// a load from the stack slot to DestVT, extending it if needed.
1668 /// The resultant code need not be legal.
1669 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1673 // Create the stack frame object.
1675 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1677 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1679 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1680 int SPFI = StackPtrFI->getIndex();
1681 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1683 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1684 unsigned SlotSize = SlotVT.getSizeInBits();
1685 unsigned DestSize = DestVT.getSizeInBits();
1686 unsigned DestAlign =
1687 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
1689 // Emit a store to the stack slot. Use a truncstore if the input value is
1690 // later than DestVT.
1693 if (SrcSize > SlotSize)
1694 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1695 SV, 0, SlotVT, false, SrcAlign);
1697 assert(SrcSize == SlotSize && "Invalid store");
1698 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1699 SV, 0, false, SrcAlign);
1702 // Result is a load from the stack slot.
1703 if (SlotSize == DestSize)
1704 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
1706 assert(SlotSize < DestSize && "Unknown extension!");
1707 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1711 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1712 DebugLoc dl = Node->getDebugLoc();
1713 // Create a vector sized/aligned stack slot, store the value to element #0,
1714 // then load the whole vector back out.
1715 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1717 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1718 int SPFI = StackPtrFI->getIndex();
1720 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1722 PseudoSourceValue::getFixedStack(SPFI), 0,
1723 Node->getValueType(0).getVectorElementType());
1724 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1725 PseudoSourceValue::getFixedStack(SPFI), 0);
1729 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1730 /// support the operation, but do support the resultant vector type.
1731 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1732 unsigned NumElems = Node->getNumOperands();
1733 SDValue SplatValue = Node->getOperand(0);
1734 DebugLoc dl = Node->getDebugLoc();
1735 MVT VT = Node->getValueType(0);
1736 MVT OpVT = SplatValue.getValueType();
1737 MVT EltVT = VT.getVectorElementType();
1739 // If the only non-undef value is the low element, turn this into a
1740 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1741 bool isOnlyLowElement = true;
1743 // FIXME: it would be far nicer to change this into map<SDValue,uint64_t>
1744 // and use a bitmask instead of a list of elements.
1745 // FIXME: this doesn't treat <0, u, 0, u> for example, as a splat.
1746 std::map<SDValue, std::vector<unsigned> > Values;
1747 Values[SplatValue].push_back(0);
1748 bool isConstant = true;
1749 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
1750 SplatValue.getOpcode() != ISD::UNDEF)
1753 for (unsigned i = 1; i < NumElems; ++i) {
1754 SDValue V = Node->getOperand(i);
1755 Values[V].push_back(i);
1756 if (V.getOpcode() != ISD::UNDEF)
1757 isOnlyLowElement = false;
1758 if (SplatValue != V)
1759 SplatValue = SDValue(0, 0);
1761 // If this isn't a constant element or an undef, we can't use a constant
1763 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
1764 V.getOpcode() != ISD::UNDEF)
1768 if (isOnlyLowElement) {
1769 // If the low element is an undef too, then this whole things is an undef.
1770 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
1771 return DAG.getUNDEF(VT);
1772 // Otherwise, turn this into a scalar_to_vector node.
1773 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1776 // If all elements are constants, create a load from the constant pool.
1778 std::vector<Constant*> CV;
1779 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1780 if (ConstantFPSDNode *V =
1781 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1782 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1783 } else if (ConstantSDNode *V =
1784 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1785 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1787 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1788 const Type *OpNTy = OpVT.getTypeForMVT();
1789 CV.push_back(UndefValue::get(OpNTy));
1792 Constant *CP = ConstantVector::get(CV);
1793 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1794 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1795 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1796 PseudoSourceValue::getConstantPool(), 0,
1800 if (SplatValue.getNode()) { // Splat of one value?
1801 // Build the shuffle constant vector: <0, 0, 0, 0>
1802 SmallVector<int, 8> ZeroVec(NumElems, 0);
1804 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
1805 if (TLI.isShuffleMaskLegal(ZeroVec, Node->getValueType(0))) {
1806 // Get the splatted value into the low element of a vector register.
1808 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, SplatValue);
1810 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1811 return DAG.getVectorShuffle(VT, dl, LowValVec, DAG.getUNDEF(VT),
1816 // If there are only two unique elements, we may be able to turn this into a
1818 if (Values.size() == 2) {
1819 // Get the two values in deterministic order.
1820 SDValue Val1 = Node->getOperand(1);
1822 std::map<SDValue, std::vector<unsigned> >::iterator MI = Values.begin();
1823 if (MI->first != Val1)
1826 Val2 = (++MI)->first;
1828 // If Val1 is an undef, make sure it ends up as Val2, to ensure that our
1829 // vector shuffle has the undef vector on the RHS.
1830 if (Val1.getOpcode() == ISD::UNDEF)
1831 std::swap(Val1, Val2);
1833 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
1834 SmallVector<int, 8> ShuffleMask(NumElems, -1);
1836 // Set elements of the shuffle mask for Val1.
1837 std::vector<unsigned> &Val1Elts = Values[Val1];
1838 for (unsigned i = 0, e = Val1Elts.size(); i != e; ++i)
1839 ShuffleMask[Val1Elts[i]] = 0;
1841 // Set elements of the shuffle mask for Val2.
1842 std::vector<unsigned> &Val2Elts = Values[Val2];
1843 for (unsigned i = 0, e = Val2Elts.size(); i != e; ++i)
1844 if (Val2.getOpcode() != ISD::UNDEF)
1845 ShuffleMask[Val2Elts[i]] = NumElems;
1847 // If the target supports SCALAR_TO_VECTOR and this shuffle mask, use it.
1848 if (TLI.isOperationLegalOrCustom(ISD::SCALAR_TO_VECTOR, VT) &&
1849 TLI.isShuffleMaskLegal(ShuffleMask, VT)) {
1850 Val1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val1);
1851 Val2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Val2);
1852 return DAG.getVectorShuffle(VT, dl, Val1, Val2, &ShuffleMask[0]);
1856 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
1857 // aligned object on the stack, store each element into it, then load
1858 // the result as a vector.
1859 // Create the stack frame object.
1860 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1861 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1862 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1864 // Emit a store of each element to the stack slot.
1865 SmallVector<SDValue, 8> Stores;
1866 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
1867 // Store (in the right endianness) the elements to memory.
1868 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1869 // Ignore undef elements.
1870 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1872 unsigned Offset = TypeByteSize*i;
1874 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1875 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1877 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1882 if (!Stores.empty()) // Not all undef elements?
1883 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1884 &Stores[0], Stores.size());
1886 StoreChain = DAG.getEntryNode();
1888 // Result is a load from the stack slot.
1889 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
1892 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1893 // does not fit into a register, return the lo part and set the hi part to the
1894 // by-reg argument. If it does fit into a single register, return the result
1895 // and leave the Hi part unset.
1896 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1898 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1899 // The input chain to this libcall is the entry node of the function.
1900 // Legalizing the call will automatically add the previous call to the
1902 SDValue InChain = DAG.getEntryNode();
1904 TargetLowering::ArgListTy Args;
1905 TargetLowering::ArgListEntry Entry;
1906 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1907 MVT ArgVT = Node->getOperand(i).getValueType();
1908 const Type *ArgTy = ArgVT.getTypeForMVT();
1909 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1910 Entry.isSExt = isSigned;
1911 Entry.isZExt = !isSigned;
1912 Args.push_back(Entry);
1914 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1915 TLI.getPointerTy());
1917 // Splice the libcall in wherever FindInputOutputChains tells us to.
1918 const Type *RetTy = Node->getValueType(0).getTypeForMVT();
1919 std::pair<SDValue, SDValue> CallInfo =
1920 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1921 CallingConv::C, false, Callee, Args, DAG,
1922 Node->getDebugLoc());
1924 // Legalize the call sequence, starting with the chain. This will advance
1925 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1926 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1927 LegalizeOp(CallInfo.second);
1928 return CallInfo.first;
1931 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1932 RTLIB::Libcall Call_F32,
1933 RTLIB::Libcall Call_F64,
1934 RTLIB::Libcall Call_F80,
1935 RTLIB::Libcall Call_PPCF128) {
1937 switch (Node->getValueType(0).getSimpleVT()) {
1938 default: assert(0 && "Unexpected request for libcall!");
1939 case MVT::f32: LC = Call_F32; break;
1940 case MVT::f64: LC = Call_F64; break;
1941 case MVT::f80: LC = Call_F80; break;
1942 case MVT::ppcf128: LC = Call_PPCF128; break;
1944 return ExpandLibCall(LC, Node, false);
1947 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1948 RTLIB::Libcall Call_I16,
1949 RTLIB::Libcall Call_I32,
1950 RTLIB::Libcall Call_I64,
1951 RTLIB::Libcall Call_I128) {
1953 switch (Node->getValueType(0).getSimpleVT()) {
1954 default: assert(0 && "Unexpected request for libcall!");
1955 case MVT::i16: LC = Call_I16; break;
1956 case MVT::i32: LC = Call_I32; break;
1957 case MVT::i64: LC = Call_I64; break;
1958 case MVT::i128: LC = Call_I128; break;
1960 return ExpandLibCall(LC, Node, isSigned);
1963 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1964 /// INT_TO_FP operation of the specified operand when the target requests that
1965 /// we expand it. At this point, we know that the result and operand types are
1966 /// legal for the target.
1967 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1971 if (Op0.getValueType() == MVT::i32) {
1972 // simple 32-bit [signed|unsigned] integer to float/double expansion
1974 // Get the stack frame index of a 8 byte buffer.
1975 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1977 // word offset constant for Hi/Lo address computation
1978 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1979 // set up Hi and Lo (into buffer) address based on endian
1980 SDValue Hi = StackSlot;
1981 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1982 TLI.getPointerTy(), StackSlot, WordOff);
1983 if (TLI.isLittleEndian())
1986 // if signed map to unsigned space
1989 // constant used to invert sign bit (signed to unsigned mapping)
1990 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1991 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1995 // store the lo of the constructed double - based on integer input
1996 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1997 Op0Mapped, Lo, NULL, 0);
1998 // initial hi portion of constructed double
1999 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
2000 // store the hi of the constructed double - biased exponent
2001 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
2002 // load the constructed double
2003 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
2004 // FP constant to bias correct the final result
2005 SDValue Bias = DAG.getConstantFP(isSigned ?
2006 BitsToDouble(0x4330000080000000ULL) :
2007 BitsToDouble(0x4330000000000000ULL),
2009 // subtract the bias
2010 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2013 // handle final rounding
2014 if (DestVT == MVT::f64) {
2017 } else if (DestVT.bitsLT(MVT::f64)) {
2018 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2019 DAG.getIntPtrConstant(0));
2020 } else if (DestVT.bitsGT(MVT::f64)) {
2021 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2025 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2026 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2028 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2029 Op0, DAG.getConstant(0, Op0.getValueType()),
2031 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2032 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2033 SignSet, Four, Zero);
2035 // If the sign bit of the integer is set, the large number will be treated
2036 // as a negative number. To counteract this, the dynamic code adds an
2037 // offset depending on the data type.
2039 switch (Op0.getValueType().getSimpleVT()) {
2040 default: assert(0 && "Unsupported integer type!");
2041 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2042 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2043 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2044 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2046 if (TLI.isLittleEndian()) FF <<= 32;
2047 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
2049 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2050 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2051 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2052 Alignment = std::min(Alignment, 4u);
2054 if (DestVT == MVT::f32)
2055 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2056 PseudoSourceValue::getConstantPool(), 0,
2060 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2061 DAG.getEntryNode(), CPIdx,
2062 PseudoSourceValue::getConstantPool(), 0,
2063 MVT::f32, false, Alignment));
2066 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2069 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2070 /// *INT_TO_FP operation of the specified operand when the target requests that
2071 /// we promote it. At this point, we know that the result and operand types are
2072 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2073 /// operation that takes a larger input.
2074 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2078 // First step, figure out the appropriate *INT_TO_FP operation to use.
2079 MVT NewInTy = LegalOp.getValueType();
2081 unsigned OpToUse = 0;
2083 // Scan for the appropriate larger type to use.
2085 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2086 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2088 // If the target supports SINT_TO_FP of this type, use it.
2089 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2090 OpToUse = ISD::SINT_TO_FP;
2093 if (isSigned) continue;
2095 // If the target supports UINT_TO_FP of this type, use it.
2096 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2097 OpToUse = ISD::UINT_TO_FP;
2101 // Otherwise, try a larger type.
2104 // Okay, we found the operation and type to use. Zero extend our input to the
2105 // desired type then run the operation on it.
2106 return DAG.getNode(OpToUse, dl, DestVT,
2107 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2108 dl, NewInTy, LegalOp));
2111 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2112 /// FP_TO_*INT operation of the specified operand when the target requests that
2113 /// we promote it. At this point, we know that the result and operand types are
2114 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2115 /// operation that returns a larger result.
2116 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2120 // First step, figure out the appropriate FP_TO*INT operation to use.
2121 MVT NewOutTy = DestVT;
2123 unsigned OpToUse = 0;
2125 // Scan for the appropriate larger type to use.
2127 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
2128 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2130 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2131 OpToUse = ISD::FP_TO_SINT;
2135 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2136 OpToUse = ISD::FP_TO_UINT;
2140 // Otherwise, try a larger type.
2144 // Okay, we found the operation and type to use.
2145 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2147 // Truncate the result of the extended FP_TO_*INT operation to the desired
2149 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2152 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2154 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2155 MVT VT = Op.getValueType();
2156 MVT SHVT = TLI.getShiftAmountTy();
2157 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2158 switch (VT.getSimpleVT()) {
2159 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
2161 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2162 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2163 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2165 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2166 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2167 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2168 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2169 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2170 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2171 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2172 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2173 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2175 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2176 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2177 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2178 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2179 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2180 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2181 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2182 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2183 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2184 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2185 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2186 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2187 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2188 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2189 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2190 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2191 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2192 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2193 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2194 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2195 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2199 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2201 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2204 default: assert(0 && "Cannot expand this yet!");
2206 static const uint64_t mask[6] = {
2207 0x5555555555555555ULL, 0x3333333333333333ULL,
2208 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2209 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2211 MVT VT = Op.getValueType();
2212 MVT ShVT = TLI.getShiftAmountTy();
2213 unsigned len = VT.getSizeInBits();
2214 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2215 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2216 unsigned EltSize = VT.isVector() ?
2217 VT.getVectorElementType().getSizeInBits() : len;
2218 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2219 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2220 Op = DAG.getNode(ISD::ADD, dl, VT,
2221 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2222 DAG.getNode(ISD::AND, dl, VT,
2223 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2229 // for now, we do this:
2230 // x = x | (x >> 1);
2231 // x = x | (x >> 2);
2233 // x = x | (x >>16);
2234 // x = x | (x >>32); // for 64-bit input
2235 // return popcount(~x);
2237 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2238 MVT VT = Op.getValueType();
2239 MVT ShVT = TLI.getShiftAmountTy();
2240 unsigned len = VT.getSizeInBits();
2241 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2242 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2243 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2244 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2246 Op = DAG.getNOT(dl, Op, VT);
2247 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2250 // for now, we use: { return popcount(~x & (x - 1)); }
2251 // unless the target has ctlz but not ctpop, in which case we use:
2252 // { return 32 - nlz(~x & (x-1)); }
2253 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2254 MVT VT = Op.getValueType();
2255 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2256 DAG.getNOT(dl, Op, VT),
2257 DAG.getNode(ISD::SUB, dl, VT, Op,
2258 DAG.getConstant(1, VT)));
2259 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2260 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2261 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2262 return DAG.getNode(ISD::SUB, dl, VT,
2263 DAG.getConstant(VT.getSizeInBits(), VT),
2264 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2265 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2270 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2271 SmallVectorImpl<SDValue> &Results) {
2272 DebugLoc dl = Node->getDebugLoc();
2273 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2274 switch (Node->getOpcode()) {
2278 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2279 Results.push_back(Tmp1);
2282 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2284 case ISD::FRAMEADDR:
2285 case ISD::RETURNADDR:
2286 case ISD::FRAME_TO_ARGS_OFFSET:
2287 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2289 case ISD::FLT_ROUNDS_:
2290 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2292 case ISD::EH_RETURN:
2294 case ISD::DBG_LABEL:
2297 case ISD::MEMBARRIER:
2299 Results.push_back(Node->getOperand(0));
2301 case ISD::DBG_STOPPOINT:
2302 Results.push_back(ExpandDBG_STOPPOINT(Node));
2304 case ISD::DYNAMIC_STACKALLOC:
2305 ExpandDYNAMIC_STACKALLOC(Node, Results);
2307 case ISD::MERGE_VALUES:
2308 for (unsigned i = 0; i < Node->getNumValues(); i++)
2309 Results.push_back(Node->getOperand(i));
2312 MVT VT = Node->getValueType(0);
2314 Results.push_back(DAG.getConstant(0, VT));
2315 else if (VT.isFloatingPoint())
2316 Results.push_back(DAG.getConstantFP(0, VT));
2318 assert(0 && "Unknown value type!");
2322 // If this operation is not supported, lower it to 'abort()' call
2323 TargetLowering::ArgListTy Args;
2324 std::pair<SDValue, SDValue> CallResult =
2325 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy,
2326 false, false, false, false, CallingConv::C, false,
2327 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2329 Results.push_back(CallResult.second);
2333 case ISD::BIT_CONVERT:
2334 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2335 Node->getValueType(0), dl);
2336 Results.push_back(Tmp1);
2338 case ISD::FP_EXTEND:
2339 Tmp1 = EmitStackConvert(Node->getOperand(0),
2340 Node->getOperand(0).getValueType(),
2341 Node->getValueType(0), dl);
2342 Results.push_back(Tmp1);
2344 case ISD::SIGN_EXTEND_INREG: {
2345 // NOTE: we could fall back on load/store here too for targets without
2346 // SAR. However, it is doubtful that any exist.
2347 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2348 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
2349 ExtraVT.getSizeInBits();
2350 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2351 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2352 Node->getOperand(0), ShiftCst);
2353 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2354 Results.push_back(Tmp1);
2357 case ISD::FP_ROUND_INREG: {
2358 // The only way we can lower this is to turn it into a TRUNCSTORE,
2359 // EXTLOAD pair, targetting a temporary location (a stack slot).
2361 // NOTE: there is a choice here between constantly creating new stack
2362 // slots and always reusing the same one. We currently always create
2363 // new ones, as reuse may inhibit scheduling.
2364 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2365 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2366 Node->getValueType(0), dl);
2367 Results.push_back(Tmp1);
2370 case ISD::SINT_TO_FP:
2371 case ISD::UINT_TO_FP:
2372 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2373 Node->getOperand(0), Node->getValueType(0), dl);
2374 Results.push_back(Tmp1);
2376 case ISD::FP_TO_UINT: {
2377 SDValue True, False;
2378 MVT VT = Node->getOperand(0).getValueType();
2379 MVT NVT = Node->getValueType(0);
2380 const uint64_t zero[] = {0, 0};
2381 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2382 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2383 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2384 Tmp1 = DAG.getConstantFP(apf, VT);
2385 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2386 Node->getOperand(0),
2388 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2389 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2390 DAG.getNode(ISD::FSUB, dl, VT,
2391 Node->getOperand(0), Tmp1));
2392 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2393 DAG.getConstant(x, NVT));
2394 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2395 Results.push_back(Tmp1);
2399 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2400 MVT VT = Node->getValueType(0);
2401 Tmp1 = Node->getOperand(0);
2402 Tmp2 = Node->getOperand(1);
2403 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
2404 // Increment the pointer, VAList, to the next vaarg
2405 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2406 DAG.getConstant(TLI.getTargetData()->
2407 getTypeAllocSize(VT.getTypeForMVT()),
2408 TLI.getPointerTy()));
2409 // Store the incremented VAList to the legalized pointer
2410 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
2411 // Load the actual argument out of the pointer VAList
2412 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
2413 Results.push_back(Results[0].getValue(1));
2417 // This defaults to loading a pointer from the input and storing it to the
2418 // output, returning the chain.
2419 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2420 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2421 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2422 Node->getOperand(2), VS, 0);
2423 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
2424 Results.push_back(Tmp1);
2427 case ISD::EXTRACT_VECTOR_ELT:
2428 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2429 // This must be an access of the only element. Return it.
2430 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2431 Node->getOperand(0));
2433 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2434 Results.push_back(Tmp1);
2436 case ISD::EXTRACT_SUBVECTOR:
2437 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2439 case ISD::CONCAT_VECTORS: {
2440 // Use extract/insert/build vector for now. We might try to be
2441 // more clever later.
2442 SmallVector<SDValue, 8> Ops;
2443 unsigned NumOperands = Node->getNumOperands();
2444 for (unsigned i=0; i < NumOperands; ++i) {
2445 SDValue SubOp = Node->getOperand(i);
2446 MVT VVT = SubOp.getNode()->getValueType(0);
2447 MVT EltVT = VVT.getVectorElementType();
2448 unsigned NumSubElem = VVT.getVectorNumElements();
2449 for (unsigned j=0; j < NumSubElem; ++j) {
2450 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
2451 DAG.getIntPtrConstant(j)));
2454 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
2455 &Ops[0], Ops.size());
2456 Results.push_back(Tmp1);
2459 case ISD::SCALAR_TO_VECTOR:
2460 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2462 case ISD::INSERT_VECTOR_ELT:
2463 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2464 Node->getOperand(1),
2465 Node->getOperand(2), dl));
2467 case ISD::VECTOR_SHUFFLE: {
2468 SmallVector<int, 8> Mask;
2469 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2471 MVT VT = Node->getValueType(0);
2472 MVT EltVT = VT.getVectorElementType();
2473 unsigned NumElems = VT.getVectorNumElements();
2474 SmallVector<SDValue, 8> Ops;
2475 for (unsigned i = 0; i != NumElems; ++i) {
2477 Ops.push_back(DAG.getUNDEF(EltVT));
2480 unsigned Idx = Mask[i];
2482 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2483 Node->getOperand(0),
2484 DAG.getIntPtrConstant(Idx)));
2486 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2487 Node->getOperand(1),
2488 DAG.getIntPtrConstant(Idx - NumElems)));
2490 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2491 Results.push_back(Tmp1);
2494 case ISD::EXTRACT_ELEMENT: {
2495 MVT OpTy = Node->getOperand(0).getValueType();
2496 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2498 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2499 DAG.getConstant(OpTy.getSizeInBits()/2,
2500 TLI.getShiftAmountTy()));
2501 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2504 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2505 Node->getOperand(0));
2507 Results.push_back(Tmp1);
2510 case ISD::STACKSAVE:
2511 // Expand to CopyFromReg if the target set
2512 // StackPointerRegisterToSaveRestore.
2513 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2514 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2515 Node->getValueType(0)));
2516 Results.push_back(Results[0].getValue(1));
2518 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2519 Results.push_back(Node->getOperand(0));
2522 case ISD::STACKRESTORE:
2523 // Expand to CopyToReg if the target set
2524 // StackPointerRegisterToSaveRestore.
2525 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2526 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2527 Node->getOperand(1)));
2529 Results.push_back(Node->getOperand(0));
2532 case ISD::FCOPYSIGN:
2533 Results.push_back(ExpandFCOPYSIGN(Node));
2536 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2537 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2538 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2539 Node->getOperand(0));
2540 Results.push_back(Tmp1);
2543 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2544 MVT VT = Node->getValueType(0);
2545 Tmp1 = Node->getOperand(0);
2546 Tmp2 = DAG.getConstantFP(0.0, VT);
2547 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2548 Tmp1, Tmp2, ISD::SETUGT);
2549 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2550 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2551 Results.push_back(Tmp1);
2555 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2556 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2559 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2560 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2563 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2564 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2567 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2568 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2571 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2572 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2575 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2576 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2579 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2580 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2583 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2584 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2587 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2588 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2591 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2592 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2595 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2596 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2599 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2600 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2602 case ISD::FNEARBYINT:
2603 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2604 RTLIB::NEARBYINT_F64,
2605 RTLIB::NEARBYINT_F80,
2606 RTLIB::NEARBYINT_PPCF128));
2609 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2610 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2613 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2614 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2617 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2618 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2621 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2622 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2624 case ISD::ConstantFP: {
2625 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2626 // Check to see if this FP immediate is already legal.
2627 bool isLegal = false;
2628 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
2629 E = TLI.legal_fpimm_end(); I != E; ++I) {
2630 if (CFP->isExactlyValue(*I)) {
2635 // If this is a legal constant, turn it into a TargetConstantFP node.
2637 Results.push_back(SDValue(Node, 0));
2639 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2642 case ISD::EHSELECTION: {
2643 unsigned Reg = TLI.getExceptionSelectorRegister();
2644 assert(Reg && "Can't expand to unknown register!");
2645 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2646 Node->getValueType(0)));
2647 Results.push_back(Results[0].getValue(1));
2650 case ISD::EXCEPTIONADDR: {
2651 unsigned Reg = TLI.getExceptionAddressRegister();
2652 assert(Reg && "Can't expand to unknown register!");
2653 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2654 Node->getValueType(0)));
2655 Results.push_back(Results[0].getValue(1));
2659 MVT VT = Node->getValueType(0);
2660 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2661 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2662 "Don't know how to expand this subtraction!");
2663 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2664 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2665 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2666 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2671 MVT VT = Node->getValueType(0);
2672 SDVTList VTs = DAG.getVTList(VT, VT);
2673 bool isSigned = Node->getOpcode() == ISD::SREM;
2674 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2675 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2676 Tmp2 = Node->getOperand(0);
2677 Tmp3 = Node->getOperand(1);
2678 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2679 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2680 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2682 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2683 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2684 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2685 } else if (isSigned) {
2686 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
2687 RTLIB::SREM_I64, RTLIB::SREM_I128);
2689 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32,
2690 RTLIB::UREM_I64, RTLIB::UREM_I128);
2692 Results.push_back(Tmp1);
2697 bool isSigned = Node->getOpcode() == ISD::SDIV;
2698 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2699 MVT VT = Node->getValueType(0);
2700 SDVTList VTs = DAG.getVTList(VT, VT);
2701 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2702 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2703 Node->getOperand(1));
2705 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2706 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2708 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2709 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2710 Results.push_back(Tmp1);
2715 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2717 MVT VT = Node->getValueType(0);
2718 SDVTList VTs = DAG.getVTList(VT, VT);
2719 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2720 "If this wasn't legal, it shouldn't have been created!");
2721 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2722 Node->getOperand(1));
2723 Results.push_back(Tmp1.getValue(1));
2727 MVT VT = Node->getValueType(0);
2728 SDVTList VTs = DAG.getVTList(VT, VT);
2729 // See if multiply or divide can be lowered using two-result operations.
2730 // We just need the low half of the multiply; try both the signed
2731 // and unsigned forms. If the target supports both SMUL_LOHI and
2732 // UMUL_LOHI, form a preference by checking which forms of plain
2733 // MULH it supports.
2734 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2735 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2736 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2737 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2738 unsigned OpToUse = 0;
2739 if (HasSMUL_LOHI && !HasMULHS) {
2740 OpToUse = ISD::SMUL_LOHI;
2741 } else if (HasUMUL_LOHI && !HasMULHU) {
2742 OpToUse = ISD::UMUL_LOHI;
2743 } else if (HasSMUL_LOHI) {
2744 OpToUse = ISD::SMUL_LOHI;
2745 } else if (HasUMUL_LOHI) {
2746 OpToUse = ISD::UMUL_LOHI;
2749 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2750 Node->getOperand(1)));
2753 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32,
2754 RTLIB::MUL_I64, RTLIB::MUL_I128);
2755 Results.push_back(Tmp1);
2760 SDValue LHS = Node->getOperand(0);
2761 SDValue RHS = Node->getOperand(1);
2762 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2763 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2765 Results.push_back(Sum);
2766 MVT OType = Node->getValueType(1);
2768 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2770 // LHSSign -> LHS >= 0
2771 // RHSSign -> RHS >= 0
2772 // SumSign -> Sum >= 0
2775 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2777 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2779 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2780 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2781 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2782 Node->getOpcode() == ISD::SADDO ?
2783 ISD::SETEQ : ISD::SETNE);
2785 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2786 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2788 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2789 Results.push_back(Cmp);
2794 SDValue LHS = Node->getOperand(0);
2795 SDValue RHS = Node->getOperand(1);
2796 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2797 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2799 Results.push_back(Sum);
2800 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2801 Node->getOpcode () == ISD::UADDO ?
2802 ISD::SETULT : ISD::SETUGT));
2805 case ISD::BUILD_PAIR: {
2806 MVT PairTy = Node->getValueType(0);
2807 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2808 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2809 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2810 DAG.getConstant(PairTy.getSizeInBits()/2,
2811 TLI.getShiftAmountTy()));
2812 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2816 Tmp1 = Node->getOperand(0);
2817 Tmp2 = Node->getOperand(1);
2818 Tmp3 = Node->getOperand(2);
2819 if (Tmp1.getOpcode() == ISD::SETCC) {
2820 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2822 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2824 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2825 DAG.getConstant(0, Tmp1.getValueType()),
2826 Tmp2, Tmp3, ISD::SETNE);
2828 Results.push_back(Tmp1);
2831 SDValue Chain = Node->getOperand(0);
2832 SDValue Table = Node->getOperand(1);
2833 SDValue Index = Node->getOperand(2);
2835 MVT PTy = TLI.getPointerTy();
2836 MachineFunction &MF = DAG.getMachineFunction();
2837 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2838 Index= DAG.getNode(ISD::MUL, dl, PTy,
2839 Index, DAG.getConstant(EntrySize, PTy));
2840 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2842 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2843 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2844 PseudoSourceValue::getJumpTable(), 0, MemVT);
2846 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2847 // For PIC, the sequence is:
2848 // BRIND(load(Jumptable + index) + RelocBase)
2849 // RelocBase can be JumpTable, GOT or some sort of global base.
2850 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2851 TLI.getPICJumpTableRelocBase(Table, DAG));
2853 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2854 Results.push_back(Tmp1);
2858 // Expand brcond's setcc into its constituent parts and create a BR_CC
2860 Tmp1 = Node->getOperand(0);
2861 Tmp2 = Node->getOperand(1);
2862 if (Tmp2.getOpcode() == ISD::SETCC) {
2863 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2864 Tmp1, Tmp2.getOperand(2),
2865 Tmp2.getOperand(0), Tmp2.getOperand(1),
2866 Node->getOperand(2));
2868 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2869 DAG.getCondCode(ISD::SETNE), Tmp2,
2870 DAG.getConstant(0, Tmp2.getValueType()),
2871 Node->getOperand(2));
2873 Results.push_back(Tmp1);
2876 Tmp1 = Node->getOperand(0);
2877 Tmp2 = Node->getOperand(1);
2878 Tmp3 = Node->getOperand(2);
2879 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2881 // If we expanded the SETCC into an AND/OR, return the new node
2882 if (Tmp2.getNode() == 0) {
2883 Results.push_back(Tmp1);
2887 // Otherwise, SETCC for the given comparison type must be completely
2888 // illegal; expand it into a SELECT_CC.
2889 MVT VT = Node->getValueType(0);
2890 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2891 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2892 Results.push_back(Tmp1);
2895 case ISD::SELECT_CC: {
2896 Tmp1 = Node->getOperand(0); // LHS
2897 Tmp2 = Node->getOperand(1); // RHS
2898 Tmp3 = Node->getOperand(2); // True
2899 Tmp4 = Node->getOperand(3); // False
2900 SDValue CC = Node->getOperand(4);
2902 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2903 Tmp1, Tmp2, CC, dl);
2905 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2906 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2907 CC = DAG.getCondCode(ISD::SETNE);
2908 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2910 Results.push_back(Tmp1);
2914 Tmp1 = Node->getOperand(0); // Chain
2915 Tmp2 = Node->getOperand(2); // LHS
2916 Tmp3 = Node->getOperand(3); // RHS
2917 Tmp4 = Node->getOperand(1); // CC
2919 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2920 Tmp2, Tmp3, Tmp4, dl);
2921 LastCALLSEQ_END = DAG.getEntryNode();
2923 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2924 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2925 Tmp4 = DAG.getCondCode(ISD::SETNE);
2926 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2927 Tmp3, Node->getOperand(4));
2928 Results.push_back(Tmp1);
2931 case ISD::GLOBAL_OFFSET_TABLE:
2932 case ISD::GlobalAddress:
2933 case ISD::GlobalTLSAddress:
2934 case ISD::ExternalSymbol:
2935 case ISD::ConstantPool:
2936 case ISD::JumpTable:
2937 case ISD::INTRINSIC_W_CHAIN:
2938 case ISD::INTRINSIC_WO_CHAIN:
2939 case ISD::INTRINSIC_VOID:
2940 // FIXME: Custom lowering for these operations shouldn't return null!
2941 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2942 Results.push_back(SDValue(Node, i));
2946 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2947 SmallVectorImpl<SDValue> &Results) {
2948 MVT OVT = Node->getValueType(0);
2949 if (Node->getOpcode() == ISD::UINT_TO_FP ||
2950 Node->getOpcode() == ISD::SINT_TO_FP) {
2951 OVT = Node->getOperand(0).getValueType();
2953 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2954 DebugLoc dl = Node->getDebugLoc();
2955 SDValue Tmp1, Tmp2, Tmp3;
2956 switch (Node->getOpcode()) {
2960 // Zero extend the argument.
2961 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2962 // Perform the larger operation.
2963 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
2964 if (Node->getOpcode() == ISD::CTTZ) {
2965 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2966 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2967 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
2969 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
2970 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
2971 } else if (Node->getOpcode() == ISD::CTLZ) {
2972 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2973 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
2974 DAG.getConstant(NVT.getSizeInBits() -
2975 OVT.getSizeInBits(), NVT));
2977 Results.push_back(Tmp1);
2980 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
2981 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
2982 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
2983 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
2984 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2985 Results.push_back(Tmp1);
2988 case ISD::FP_TO_UINT:
2989 case ISD::FP_TO_SINT:
2990 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
2991 Node->getOpcode() == ISD::FP_TO_SINT, dl);
2992 Results.push_back(Tmp1);
2994 case ISD::UINT_TO_FP:
2995 case ISD::SINT_TO_FP:
2996 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
2997 Node->getOpcode() == ISD::SINT_TO_FP, dl);
2998 Results.push_back(Tmp1);
3003 assert(OVT.isVector() && "Don't know how to promote scalar logic ops");
3004 // Bit convert each of the values to the new type.
3005 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3006 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3007 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3008 // Bit convert the result back the original type.
3009 Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1));
3012 unsigned ExtOp, TruncOp;
3013 if (Node->getValueType(0).isVector()) {
3014 ExtOp = ISD::BIT_CONVERT;
3015 TruncOp = ISD::BIT_CONVERT;
3016 } else if (Node->getValueType(0).isInteger()) {
3017 ExtOp = ISD::ANY_EXTEND;
3018 TruncOp = ISD::TRUNCATE;
3020 ExtOp = ISD::FP_EXTEND;
3021 TruncOp = ISD::FP_ROUND;
3023 Tmp1 = Node->getOperand(0);
3024 // Promote each of the values to the new type.
3025 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3026 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3027 // Perform the larger operation, then round down.
3028 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3029 if (TruncOp != ISD::FP_ROUND)
3030 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3032 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3033 DAG.getIntPtrConstant(0));
3034 Results.push_back(Tmp1);
3036 case ISD::VECTOR_SHUFFLE: {
3037 SmallVector<int, 8> Mask;
3038 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3040 // Cast the two input vectors.
3041 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3042 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3044 // Convert the shuffle mask to the right # elements.
3045 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3046 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3047 Results.push_back(Tmp1);
3051 // First step, figure out the appropriate operation to use.
3052 // Allow SETCC to not be supported for all legal data types
3053 // Mostly this targets FP
3054 MVT NewInTy = Node->getOperand(0).getValueType();
3055 MVT OldVT = NewInTy; OldVT = OldVT;
3057 // Scan for the appropriate larger type to use.
3059 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3061 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3062 "Fell off of the edge of the integer world");
3063 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3064 "Fell off of the edge of the floating point world");
3066 // If the target supports SETCC of this type, use it.
3067 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3070 if (NewInTy.isInteger())
3071 assert(0 && "Cannot promote Legal Integer SETCC yet");
3073 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3074 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3076 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3077 Tmp1, Tmp2, Node->getOperand(2)));
3083 // SelectionDAG::Legalize - This is the entry point for the file.
3085 void SelectionDAG::Legalize(bool TypesNeedLegalizing,
3086 CodeGenOpt::Level OptLevel) {
3087 /// run - This is the main entry point to this class.
3089 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();