1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/Target/TargetData.h"
20 #include "llvm/Target/TargetMachine.h"
21 #include "llvm/Target/TargetOptions.h"
22 #include "llvm/CallingConv.h"
23 #include "llvm/Constants.h"
24 #include "llvm/DerivedTypes.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/CommandLine.h"
27 #include "llvm/Support/Compiler.h"
28 #include "llvm/ADT/DenseMap.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/SmallPtrSet.h"
36 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
37 cl::desc("Pop up a window to show dags before legalize"));
39 static const bool ViewLegalizeDAGs = 0;
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
59 // Libcall insertion helpers.
61 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
62 /// legalized. We use this to ensure that calls are properly serialized
63 /// against each other, including inserted libcalls.
64 SDOperand LastCALLSEQ_END;
66 /// IsLegalizingCall - This member is used *only* for purposes of providing
67 /// helpful assertions that a libcall isn't created while another call is
68 /// being legalized (which could lead to non-serialized call sequences).
69 bool IsLegalizingCall;
72 Legal, // The target natively supports this operation.
73 Promote, // This operation should be executed in a larger type.
74 Expand // Try to expand this to other ops, otherwise use a libcall.
77 /// ValueTypeActions - This is a bitvector that contains two bits for each
78 /// value type, where the two bits correspond to the LegalizeAction enum.
79 /// This can be queried with "getTypeAction(VT)".
80 TargetLowering::ValueTypeActionImpl ValueTypeActions;
82 /// LegalizedNodes - For nodes that are of legal width, and that have more
83 /// than one use, this map indicates what regularized operand to use. This
84 /// allows us to avoid legalizing the same thing more than once.
85 DenseMap<SDOperand, SDOperand> LegalizedNodes;
87 /// PromotedNodes - For nodes that are below legal width, and that have more
88 /// than one use, this map indicates what promoted value to use. This allows
89 /// us to avoid promoting the same thing more than once.
90 DenseMap<SDOperand, SDOperand> PromotedNodes;
92 /// ExpandedNodes - For nodes that need to be expanded this map indicates
93 /// which which operands are the expanded version of the input. This allows
94 /// us to avoid expanding the same node more than once.
95 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> > ExpandedNodes;
97 /// SplitNodes - For vector nodes that need to be split, this map indicates
98 /// which which operands are the split version of the input. This allows us
99 /// to avoid splitting the same node more than once.
100 std::map<SDOperand, std::pair<SDOperand, SDOperand> > SplitNodes;
102 /// ScalarizedNodes - For nodes that need to be converted from vector types to
103 /// scalar types, this contains the mapping of ones we have already
104 /// processed to the result.
105 std::map<SDOperand, SDOperand> ScalarizedNodes;
107 void AddLegalizedOperand(SDOperand From, SDOperand To) {
108 LegalizedNodes.insert(std::make_pair(From, To));
109 // If someone requests legalization of the new node, return itself.
111 LegalizedNodes.insert(std::make_pair(To, To));
113 void AddPromotedOperand(SDOperand From, SDOperand To) {
114 bool isNew = PromotedNodes.insert(std::make_pair(From, To));
115 assert(isNew && "Got into the map somehow?");
116 // If someone requests legalization of the new node, return itself.
117 LegalizedNodes.insert(std::make_pair(To, To));
122 SelectionDAGLegalize(SelectionDAG &DAG);
124 /// getTypeAction - Return how we should legalize values of this type, either
125 /// it is already legal or we need to expand it into multiple registers of
126 /// smaller integer type, or we need to promote it to a larger type.
127 LegalizeAction getTypeAction(MVT::ValueType VT) const {
128 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
131 /// isTypeLegal - Return true if this type is legal on this target.
133 bool isTypeLegal(MVT::ValueType VT) const {
134 return getTypeAction(VT) == Legal;
140 /// HandleOp - Legalize, Promote, or Expand the specified operand as
141 /// appropriate for its type.
142 void HandleOp(SDOperand Op);
144 /// LegalizeOp - We know that the specified value has a legal type.
145 /// Recursively ensure that the operands have legal types, then return the
147 SDOperand LegalizeOp(SDOperand O);
149 /// PromoteOp - Given an operation that produces a value in an invalid type,
150 /// promote it to compute the value into a larger type. The produced value
151 /// will have the correct bits for the low portion of the register, but no
152 /// guarantee is made about the top bits: it may be zero, sign-extended, or
154 SDOperand PromoteOp(SDOperand O);
156 /// ExpandOp - Expand the specified SDOperand into its two component pieces
157 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this,
158 /// the LegalizeNodes map is filled in for any results that are not expanded,
159 /// the ExpandedNodes map is filled in for any results that are expanded, and
160 /// the Lo/Hi values are returned. This applies to integer types and Vector
162 void ExpandOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
164 /// SplitVectorOp - Given an operand of vector type, break it down into
165 /// two smaller values.
166 void SplitVectorOp(SDOperand O, SDOperand &Lo, SDOperand &Hi);
168 /// ScalarizeVectorOp - Given an operand of single-element vector type
169 /// (e.g. v1f32), convert it into the equivalent operation that returns a
170 /// scalar (e.g. f32) value.
171 SDOperand ScalarizeVectorOp(SDOperand O);
173 /// isShuffleLegal - Return true if a vector shuffle is legal with the
174 /// specified mask and type. Targets can specify exactly which masks they
175 /// support and the code generator is tasked with not creating illegal masks.
177 /// Note that this will also return true for shuffles that are promoted to a
180 /// If this is a legal shuffle, this method returns the (possibly promoted)
181 /// build_vector Mask. If it's not a legal shuffle, it returns null.
182 SDNode *isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const;
184 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
185 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
187 void LegalizeSetCCOperands(SDOperand &LHS, SDOperand &RHS, SDOperand &CC);
189 SDOperand CreateStackTemporary(MVT::ValueType VT);
191 SDOperand ExpandLibCall(const char *Name, SDNode *Node, bool isSigned,
193 SDOperand ExpandIntToFP(bool isSigned, MVT::ValueType DestTy,
196 SDOperand ExpandBIT_CONVERT(MVT::ValueType DestVT, SDOperand SrcOp);
197 SDOperand ExpandBUILD_VECTOR(SDNode *Node);
198 SDOperand ExpandSCALAR_TO_VECTOR(SDNode *Node);
199 SDOperand ExpandLegalINT_TO_FP(bool isSigned,
201 MVT::ValueType DestVT);
202 SDOperand PromoteLegalINT_TO_FP(SDOperand LegalOp, MVT::ValueType DestVT,
204 SDOperand PromoteLegalFP_TO_INT(SDOperand LegalOp, MVT::ValueType DestVT,
207 SDOperand ExpandBSWAP(SDOperand Op);
208 SDOperand ExpandBitCount(unsigned Opc, SDOperand Op);
209 bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
210 SDOperand &Lo, SDOperand &Hi);
211 void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
212 SDOperand &Lo, SDOperand &Hi);
214 SDOperand ExpandEXTRACT_SUBVECTOR(SDOperand Op);
215 SDOperand ExpandEXTRACT_VECTOR_ELT(SDOperand Op);
217 SDOperand getIntPtrConstant(uint64_t Val) {
218 return DAG.getConstant(Val, TLI.getPointerTy());
223 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
224 /// specified mask and type. Targets can specify exactly which masks they
225 /// support and the code generator is tasked with not creating illegal masks.
227 /// Note that this will also return true for shuffles that are promoted to a
229 SDNode *SelectionDAGLegalize::isShuffleLegal(MVT::ValueType VT,
230 SDOperand Mask) const {
231 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE, VT)) {
233 case TargetLowering::Legal:
234 case TargetLowering::Custom:
236 case TargetLowering::Promote: {
237 // If this is promoted to a different type, convert the shuffle mask and
238 // ask if it is legal in the promoted type!
239 MVT::ValueType NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
241 // If we changed # elements, change the shuffle mask.
242 unsigned NumEltsGrowth =
243 MVT::getVectorNumElements(NVT) / MVT::getVectorNumElements(VT);
244 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
245 if (NumEltsGrowth > 1) {
246 // Renumber the elements.
247 SmallVector<SDOperand, 8> Ops;
248 for (unsigned i = 0, e = Mask.getNumOperands(); i != e; ++i) {
249 SDOperand InOp = Mask.getOperand(i);
250 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
251 if (InOp.getOpcode() == ISD::UNDEF)
252 Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
254 unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
255 Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
259 Mask = DAG.getNode(ISD::BUILD_VECTOR, NVT, &Ops[0], Ops.size());
265 return TLI.isShuffleMaskLegal(Mask, VT) ? Mask.Val : 0;
268 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag)
269 : TLI(dag.getTargetLoweringInfo()), DAG(dag),
270 ValueTypeActions(TLI.getValueTypeActions()) {
271 assert(MVT::LAST_VALUETYPE <= 32 &&
272 "Too many value types for ValueTypeActions to hold!");
275 /// ComputeTopDownOrdering - Compute a top-down ordering of the dag, where Order
276 /// contains all of a nodes operands before it contains the node.
277 static void ComputeTopDownOrdering(SelectionDAG &DAG,
278 SmallVector<SDNode*, 64> &Order) {
280 DenseMap<SDNode*, unsigned> Visited;
281 std::vector<SDNode*> Worklist;
282 Worklist.reserve(128);
284 // Compute ordering from all of the leaves in the graphs, those (like the
285 // entry node) that have no operands.
286 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
287 E = DAG.allnodes_end(); I != E; ++I) {
288 if (I->getNumOperands() == 0) {
290 Worklist.push_back(I);
294 while (!Worklist.empty()) {
295 SDNode *N = Worklist.back();
298 if (++Visited[N] != N->getNumOperands())
299 continue; // Haven't visited all operands yet
303 // Now that we have N in, add anything that uses it if all of their operands
305 for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
307 Worklist.push_back(*UI);
310 assert(Order.size() == Visited.size() &&
312 (unsigned)std::distance(DAG.allnodes_begin(), DAG.allnodes_end()) &&
313 "Error: DAG is cyclic!");
317 void SelectionDAGLegalize::LegalizeDAG() {
318 LastCALLSEQ_END = DAG.getEntryNode();
319 IsLegalizingCall = false;
321 // The legalize process is inherently a bottom-up recursive process (users
322 // legalize their uses before themselves). Given infinite stack space, we
323 // could just start legalizing on the root and traverse the whole graph. In
324 // practice however, this causes us to run out of stack space on large basic
325 // blocks. To avoid this problem, compute an ordering of the nodes where each
326 // node is only legalized after all of its operands are legalized.
327 SmallVector<SDNode*, 64> Order;
328 ComputeTopDownOrdering(DAG, Order);
330 for (unsigned i = 0, e = Order.size(); i != e; ++i)
331 HandleOp(SDOperand(Order[i], 0));
333 // Finally, it's possible the root changed. Get the new root.
334 SDOperand OldRoot = DAG.getRoot();
335 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
336 DAG.setRoot(LegalizedNodes[OldRoot]);
338 ExpandedNodes.clear();
339 LegalizedNodes.clear();
340 PromotedNodes.clear();
342 ScalarizedNodes.clear();
344 // Remove dead nodes now.
345 DAG.RemoveDeadNodes();
349 /// FindCallEndFromCallStart - Given a chained node that is part of a call
350 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
351 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
352 if (Node->getOpcode() == ISD::CALLSEQ_END)
354 if (Node->use_empty())
355 return 0; // No CallSeqEnd
357 // The chain is usually at the end.
358 SDOperand TheChain(Node, Node->getNumValues()-1);
359 if (TheChain.getValueType() != MVT::Other) {
360 // Sometimes it's at the beginning.
361 TheChain = SDOperand(Node, 0);
362 if (TheChain.getValueType() != MVT::Other) {
363 // Otherwise, hunt for it.
364 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
365 if (Node->getValueType(i) == MVT::Other) {
366 TheChain = SDOperand(Node, i);
370 // Otherwise, we walked into a node without a chain.
371 if (TheChain.getValueType() != MVT::Other)
376 for (SDNode::use_iterator UI = Node->use_begin(),
377 E = Node->use_end(); UI != E; ++UI) {
379 // Make sure to only follow users of our token chain.
381 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
382 if (User->getOperand(i) == TheChain)
383 if (SDNode *Result = FindCallEndFromCallStart(User))
389 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
390 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
391 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
392 assert(Node && "Didn't find callseq_start for a call??");
393 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
395 assert(Node->getOperand(0).getValueType() == MVT::Other &&
396 "Node doesn't have a token chain argument!");
397 return FindCallStartFromCallEnd(Node->getOperand(0).Val);
400 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
401 /// see if any uses can reach Dest. If no dest operands can get to dest,
402 /// legalize them, legalize ourself, and return false, otherwise, return true.
404 /// Keep track of the nodes we fine that actually do lead to Dest in
405 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
407 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
408 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
409 if (N == Dest) return true; // N certainly leads to Dest :)
411 // If we've already processed this node and it does lead to Dest, there is no
412 // need to reprocess it.
413 if (NodesLeadingTo.count(N)) return true;
415 // If the first result of this node has been already legalized, then it cannot
417 switch (getTypeAction(N->getValueType(0))) {
419 if (LegalizedNodes.count(SDOperand(N, 0))) return false;
422 if (PromotedNodes.count(SDOperand(N, 0))) return false;
425 if (ExpandedNodes.count(SDOperand(N, 0))) return false;
429 // Okay, this node has not already been legalized. Check and legalize all
430 // operands. If none lead to Dest, then we can legalize this node.
431 bool OperandsLeadToDest = false;
432 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
433 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
434 LegalizeAllNodesNotLeadingTo(N->getOperand(i).Val, Dest, NodesLeadingTo);
436 if (OperandsLeadToDest) {
437 NodesLeadingTo.insert(N);
441 // Okay, this node looks safe, legalize it and return false.
442 HandleOp(SDOperand(N, 0));
446 /// HandleOp - Legalize, Promote, or Expand the specified operand as
447 /// appropriate for its type.
448 void SelectionDAGLegalize::HandleOp(SDOperand Op) {
449 MVT::ValueType VT = Op.getValueType();
450 switch (getTypeAction(VT)) {
451 default: assert(0 && "Bad type action!");
452 case Legal: (void)LegalizeOp(Op); break;
453 case Promote: (void)PromoteOp(Op); break;
455 if (!MVT::isVector(VT)) {
456 // If this is an illegal scalar, expand it into its two component
460 } else if (MVT::getVectorNumElements(VT) == 1) {
461 // If this is an illegal single element vector, convert it to a
463 (void)ScalarizeVectorOp(Op);
465 // Otherwise, this is an illegal multiple element vector.
466 // Split it in half and legalize both parts.
468 SplitVectorOp(Op, X, Y);
474 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
475 /// a load from the constant pool.
476 static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
477 SelectionDAG &DAG, TargetLowering &TLI) {
480 // If a FP immediate is precise when represented as a float and if the
481 // target can do an extending load from float to double, we put it into
482 // the constant pool as a float, even if it's is statically typed as a
484 MVT::ValueType VT = CFP->getValueType(0);
485 bool isDouble = VT == MVT::f64;
486 ConstantFP *LLVMC = ConstantFP::get(isDouble ? Type::DoubleTy :
487 Type::FloatTy, CFP->getValue());
489 double Val = LLVMC->getValue();
491 ? DAG.getConstant(DoubleToBits(Val), MVT::i64)
492 : DAG.getConstant(FloatToBits(Val), MVT::i32);
495 if (isDouble && CFP->isExactlyValue((float)CFP->getValue()) &&
496 // Only do this if the target has a native EXTLOAD instruction from f32.
497 TLI.isLoadXLegal(ISD::EXTLOAD, MVT::f32)) {
498 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC,Type::FloatTy));
503 SDOperand CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
505 return DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
506 CPIdx, NULL, 0, MVT::f32);
508 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
513 /// ExpandFCOPYSIGNToBitwiseOps - Expands fcopysign to a series of bitwise
516 SDOperand ExpandFCOPYSIGNToBitwiseOps(SDNode *Node, MVT::ValueType NVT,
517 SelectionDAG &DAG, TargetLowering &TLI) {
518 MVT::ValueType VT = Node->getValueType(0);
519 MVT::ValueType SrcVT = Node->getOperand(1).getValueType();
520 assert((SrcVT == MVT::f32 || SrcVT == MVT::f64) &&
521 "fcopysign expansion only supported for f32 and f64");
522 MVT::ValueType SrcNVT = (SrcVT == MVT::f64) ? MVT::i64 : MVT::i32;
524 // First get the sign bit of second operand.
525 SDOperand Mask1 = (SrcVT == MVT::f64)
526 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
527 : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
528 Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
529 SDOperand SignBit= DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Node->getOperand(1));
530 SignBit = DAG.getNode(ISD::AND, SrcNVT, SignBit, Mask1);
531 // Shift right or sign-extend it if the two operands have different types.
532 int SizeDiff = MVT::getSizeInBits(SrcNVT) - MVT::getSizeInBits(NVT);
534 SignBit = DAG.getNode(ISD::SRL, SrcNVT, SignBit,
535 DAG.getConstant(SizeDiff, TLI.getShiftAmountTy()));
536 SignBit = DAG.getNode(ISD::TRUNCATE, NVT, SignBit);
537 } else if (SizeDiff < 0)
538 SignBit = DAG.getNode(ISD::SIGN_EXTEND, NVT, SignBit);
540 // Clear the sign bit of first operand.
541 SDOperand Mask2 = (VT == MVT::f64)
542 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
543 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
544 Mask2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask2);
545 SDOperand Result = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
546 Result = DAG.getNode(ISD::AND, NVT, Result, Mask2);
548 // Or the value with the sign bit.
549 Result = DAG.getNode(ISD::OR, NVT, Result, SignBit);
554 /// LegalizeOp - We know that the specified value has a legal type, and
555 /// that its operands are legal. Now ensure that the operation itself
556 /// is legal, recursively ensuring that the operands' operations remain
558 SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
559 assert(isTypeLegal(Op.getValueType()) &&
560 "Caller should expand or promote operands that are not legal!");
561 SDNode *Node = Op.Val;
563 // If this operation defines any values that cannot be represented in a
564 // register on this target, make sure to expand or promote them.
565 if (Node->getNumValues() > 1) {
566 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
567 if (getTypeAction(Node->getValueType(i)) != Legal) {
568 HandleOp(Op.getValue(i));
569 assert(LegalizedNodes.count(Op) &&
570 "Handling didn't add legal operands!");
571 return LegalizedNodes[Op];
575 // Note that LegalizeOp may be reentered even from single-use nodes, which
576 // means that we always must cache transformed nodes.
577 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
578 if (I != LegalizedNodes.end()) return I->second;
580 SDOperand Tmp1, Tmp2, Tmp3, Tmp4;
581 SDOperand Result = Op;
582 bool isCustom = false;
584 switch (Node->getOpcode()) {
585 case ISD::FrameIndex:
586 case ISD::EntryToken:
588 case ISD::BasicBlock:
589 case ISD::TargetFrameIndex:
590 case ISD::TargetJumpTable:
591 case ISD::TargetConstant:
592 case ISD::TargetConstantFP:
593 case ISD::TargetConstantPool:
594 case ISD::TargetGlobalAddress:
595 case ISD::TargetGlobalTLSAddress:
596 case ISD::TargetExternalSymbol:
601 // Primitives must all be legal.
602 assert(TLI.isOperationLegal(Node->getValueType(0), Node->getValueType(0)) &&
603 "This must be legal!");
606 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
607 // If this is a target node, legalize it by legalizing the operands then
608 // passing it through.
609 SmallVector<SDOperand, 8> Ops;
610 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
611 Ops.push_back(LegalizeOp(Node->getOperand(i)));
613 Result = DAG.UpdateNodeOperands(Result.getValue(0), &Ops[0], Ops.size());
615 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
616 AddLegalizedOperand(Op.getValue(i), Result.getValue(i));
617 return Result.getValue(Op.ResNo);
619 // Otherwise this is an unhandled builtin node. splat.
621 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
623 assert(0 && "Do not know how to legalize this operator!");
625 case ISD::GLOBAL_OFFSET_TABLE:
626 case ISD::GlobalAddress:
627 case ISD::GlobalTLSAddress:
628 case ISD::ExternalSymbol:
629 case ISD::ConstantPool:
630 case ISD::JumpTable: // Nothing to do.
631 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
632 default: assert(0 && "This action is not supported yet!");
633 case TargetLowering::Custom:
634 Tmp1 = TLI.LowerOperation(Op, DAG);
635 if (Tmp1.Val) Result = Tmp1;
636 // FALLTHROUGH if the target doesn't want to lower this op after all.
637 case TargetLowering::Legal:
642 case ISD::RETURNADDR:
643 case ISD::FRAME_TO_ARGS_OFFSET:
644 // The only option for these nodes is to custom lower them. If the target
645 // does not custom lower them, then return zero.
646 Tmp1 = TLI.LowerOperation(Op, DAG);
650 Result = DAG.getConstant(0, TLI.getPointerTy());
652 case ISD::EXCEPTIONADDR: {
653 Tmp1 = LegalizeOp(Node->getOperand(0));
654 MVT::ValueType VT = Node->getValueType(0);
655 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
656 default: assert(0 && "This action is not supported yet!");
657 case TargetLowering::Expand: {
658 unsigned Reg = TLI.getExceptionAddressRegister();
659 Result = DAG.getCopyFromReg(Tmp1, Reg, VT).getValue(Op.ResNo);
662 case TargetLowering::Custom:
663 Result = TLI.LowerOperation(Op, DAG);
664 if (Result.Val) break;
666 case TargetLowering::Legal: {
667 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp1 };
668 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
669 Ops, 2).getValue(Op.ResNo);
675 case ISD::EHSELECTION: {
676 Tmp1 = LegalizeOp(Node->getOperand(0));
677 Tmp2 = LegalizeOp(Node->getOperand(1));
678 MVT::ValueType VT = Node->getValueType(0);
679 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
680 default: assert(0 && "This action is not supported yet!");
681 case TargetLowering::Expand: {
682 unsigned Reg = TLI.getExceptionSelectorRegister();
683 Result = DAG.getCopyFromReg(Tmp2, Reg, VT).getValue(Op.ResNo);
686 case TargetLowering::Custom:
687 Result = TLI.LowerOperation(Op, DAG);
688 if (Result.Val) break;
690 case TargetLowering::Legal: {
691 SDOperand Ops[] = { DAG.getConstant(0, VT), Tmp2 };
692 Result = DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, MVT::Other),
693 Ops, 2).getValue(Op.ResNo);
699 case ISD::EH_RETURN: {
700 MVT::ValueType VT = Node->getValueType(0);
701 // The only "good" option for this node is to custom lower it.
702 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
703 default: assert(0 && "This action is not supported at all!");
704 case TargetLowering::Custom:
705 Result = TLI.LowerOperation(Op, DAG);
706 if (Result.Val) break;
708 case TargetLowering::Legal:
709 // Target does not know, how to lower this, lower to noop
710 Result = LegalizeOp(Node->getOperand(0));
715 case ISD::AssertSext:
716 case ISD::AssertZext:
717 Tmp1 = LegalizeOp(Node->getOperand(0));
718 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
720 case ISD::MERGE_VALUES:
721 // Legalize eliminates MERGE_VALUES nodes.
722 Result = Node->getOperand(Op.ResNo);
724 case ISD::CopyFromReg:
725 Tmp1 = LegalizeOp(Node->getOperand(0));
726 Result = Op.getValue(0);
727 if (Node->getNumValues() == 2) {
728 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
730 assert(Node->getNumValues() == 3 && "Invalid copyfromreg!");
731 if (Node->getNumOperands() == 3) {
732 Tmp2 = LegalizeOp(Node->getOperand(2));
733 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
735 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
737 AddLegalizedOperand(Op.getValue(2), Result.getValue(2));
739 // Since CopyFromReg produces two values, make sure to remember that we
740 // legalized both of them.
741 AddLegalizedOperand(Op.getValue(0), Result);
742 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
743 return Result.getValue(Op.ResNo);
745 MVT::ValueType VT = Op.getValueType();
746 switch (TLI.getOperationAction(ISD::UNDEF, VT)) {
747 default: assert(0 && "This action is not supported yet!");
748 case TargetLowering::Expand:
749 if (MVT::isInteger(VT))
750 Result = DAG.getConstant(0, VT);
751 else if (MVT::isFloatingPoint(VT))
752 Result = DAG.getConstantFP(0, VT);
754 assert(0 && "Unknown value type!");
756 case TargetLowering::Legal:
762 case ISD::INTRINSIC_W_CHAIN:
763 case ISD::INTRINSIC_WO_CHAIN:
764 case ISD::INTRINSIC_VOID: {
765 SmallVector<SDOperand, 8> Ops;
766 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
767 Ops.push_back(LegalizeOp(Node->getOperand(i)));
768 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
770 // Allow the target to custom lower its intrinsics if it wants to.
771 if (TLI.getOperationAction(Node->getOpcode(), MVT::Other) ==
772 TargetLowering::Custom) {
773 Tmp3 = TLI.LowerOperation(Result, DAG);
774 if (Tmp3.Val) Result = Tmp3;
777 if (Result.Val->getNumValues() == 1) break;
779 // Must have return value and chain result.
780 assert(Result.Val->getNumValues() == 2 &&
781 "Cannot return more than two values!");
783 // Since loads produce two values, make sure to remember that we
784 // legalized both of them.
785 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
786 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
787 return Result.getValue(Op.ResNo);
791 assert(Node->getNumOperands() == 5 && "Invalid LOCATION node!");
792 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input chain.
794 switch (TLI.getOperationAction(ISD::LOCATION, MVT::Other)) {
795 case TargetLowering::Promote:
796 default: assert(0 && "This action is not supported yet!");
797 case TargetLowering::Expand: {
798 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
799 bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
800 bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
802 if (MMI && (useDEBUG_LOC || useLABEL)) {
803 const std::string &FName =
804 cast<StringSDNode>(Node->getOperand(3))->getValue();
805 const std::string &DirName =
806 cast<StringSDNode>(Node->getOperand(4))->getValue();
807 unsigned SrcFile = MMI->RecordSource(DirName, FName);
809 SmallVector<SDOperand, 8> Ops;
810 Ops.push_back(Tmp1); // chain
811 SDOperand LineOp = Node->getOperand(1);
812 SDOperand ColOp = Node->getOperand(2);
815 Ops.push_back(LineOp); // line #
816 Ops.push_back(ColOp); // col #
817 Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
818 Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
820 unsigned Line = cast<ConstantSDNode>(LineOp)->getValue();
821 unsigned Col = cast<ConstantSDNode>(ColOp)->getValue();
822 unsigned ID = MMI->RecordLabel(Line, Col, SrcFile);
823 Ops.push_back(DAG.getConstant(ID, MVT::i32));
824 Result = DAG.getNode(ISD::LABEL, MVT::Other,&Ops[0],Ops.size());
827 Result = Tmp1; // chain
831 case TargetLowering::Legal:
832 if (Tmp1 != Node->getOperand(0) ||
833 getTypeAction(Node->getOperand(1).getValueType()) == Promote) {
834 SmallVector<SDOperand, 8> Ops;
836 if (getTypeAction(Node->getOperand(1).getValueType()) == Legal) {
837 Ops.push_back(Node->getOperand(1)); // line # must be legal.
838 Ops.push_back(Node->getOperand(2)); // col # must be legal.
840 // Otherwise promote them.
841 Ops.push_back(PromoteOp(Node->getOperand(1)));
842 Ops.push_back(PromoteOp(Node->getOperand(2)));
844 Ops.push_back(Node->getOperand(3)); // filename must be legal.
845 Ops.push_back(Node->getOperand(4)); // working dir # must be legal.
846 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
853 assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
854 switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
855 default: assert(0 && "This action is not supported yet!");
856 case TargetLowering::Legal:
857 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
858 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
859 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
860 Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
861 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4);
867 assert(Node->getNumOperands() == 2 && "Invalid LABEL node!");
868 switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
869 default: assert(0 && "This action is not supported yet!");
870 case TargetLowering::Legal:
871 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
872 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
873 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
875 case TargetLowering::Expand:
876 Result = LegalizeOp(Node->getOperand(0));
882 // We know we don't need to expand constants here, constants only have one
883 // value and we check that it is fine above.
885 // FIXME: Maybe we should handle things like targets that don't support full
886 // 32-bit immediates?
888 case ISD::ConstantFP: {
889 // Spill FP immediates to the constant pool if the target cannot directly
890 // codegen them. Targets often have some immediate values that can be
891 // efficiently generated into an FP register without a load. We explicitly
892 // leave these constants as ConstantFP nodes for the target to deal with.
893 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
895 // Check to see if this FP immediate is already legal.
896 bool isLegal = false;
897 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
898 E = TLI.legal_fpimm_end(); I != E; ++I)
899 if (CFP->isExactlyValue(*I)) {
904 // If this is a legal constant, turn it into a TargetConstantFP node.
906 Result = DAG.getTargetConstantFP(CFP->getValue(), CFP->getValueType(0));
910 switch (TLI.getOperationAction(ISD::ConstantFP, CFP->getValueType(0))) {
911 default: assert(0 && "This action is not supported yet!");
912 case TargetLowering::Custom:
913 Tmp3 = TLI.LowerOperation(Result, DAG);
919 case TargetLowering::Expand:
920 Result = ExpandConstantFP(CFP, true, DAG, TLI);
924 case ISD::TokenFactor:
925 if (Node->getNumOperands() == 2) {
926 Tmp1 = LegalizeOp(Node->getOperand(0));
927 Tmp2 = LegalizeOp(Node->getOperand(1));
928 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
929 } else if (Node->getNumOperands() == 3) {
930 Tmp1 = LegalizeOp(Node->getOperand(0));
931 Tmp2 = LegalizeOp(Node->getOperand(1));
932 Tmp3 = LegalizeOp(Node->getOperand(2));
933 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
935 SmallVector<SDOperand, 8> Ops;
936 // Legalize the operands.
937 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
938 Ops.push_back(LegalizeOp(Node->getOperand(i)));
939 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
943 case ISD::FORMAL_ARGUMENTS:
945 // The only option for this is to custom lower it.
946 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
947 assert(Tmp3.Val && "Target didn't custom lower this node!");
948 assert(Tmp3.Val->getNumValues() == Result.Val->getNumValues() &&
949 "Lowering call/formal_arguments produced unexpected # results!");
951 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
952 // remember that we legalized all of them, so it doesn't get relegalized.
953 for (unsigned i = 0, e = Tmp3.Val->getNumValues(); i != e; ++i) {
954 Tmp1 = LegalizeOp(Tmp3.getValue(i));
957 AddLegalizedOperand(SDOperand(Node, i), Tmp1);
961 case ISD::BUILD_VECTOR:
962 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
963 default: assert(0 && "This action is not supported yet!");
964 case TargetLowering::Custom:
965 Tmp3 = TLI.LowerOperation(Result, DAG);
971 case TargetLowering::Expand:
972 Result = ExpandBUILD_VECTOR(Result.Val);
976 case ISD::INSERT_VECTOR_ELT:
977 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVec
978 Tmp2 = LegalizeOp(Node->getOperand(1)); // InVal
979 Tmp3 = LegalizeOp(Node->getOperand(2)); // InEltNo
980 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
982 switch (TLI.getOperationAction(ISD::INSERT_VECTOR_ELT,
983 Node->getValueType(0))) {
984 default: assert(0 && "This action is not supported yet!");
985 case TargetLowering::Legal:
987 case TargetLowering::Custom:
988 Tmp3 = TLI.LowerOperation(Result, DAG);
994 case TargetLowering::Expand: {
995 // If the insert index is a constant, codegen this as a scalar_to_vector,
996 // then a shuffle that inserts it into the right position in the vector.
997 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Tmp3)) {
998 SDOperand ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR,
999 Tmp1.getValueType(), Tmp2);
1001 unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
1002 MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
1003 MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
1005 // We generate a shuffle of InVec and ScVec, so the shuffle mask should
1006 // be 0,1,2,3,4,5... with the appropriate element replaced with elt 0 of
1008 SmallVector<SDOperand, 8> ShufOps;
1009 for (unsigned i = 0; i != NumElts; ++i) {
1010 if (i != InsertPos->getValue())
1011 ShufOps.push_back(DAG.getConstant(i, ShufMaskEltVT));
1013 ShufOps.push_back(DAG.getConstant(NumElts, ShufMaskEltVT));
1015 SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMaskVT,
1016 &ShufOps[0], ShufOps.size());
1018 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, Tmp1.getValueType(),
1019 Tmp1, ScVec, ShufMask);
1020 Result = LegalizeOp(Result);
1024 // If the target doesn't support this, we have to spill the input vector
1025 // to a temporary stack slot, update the element, then reload it. This is
1026 // badness. We could also load the value into a vector register (either
1027 // with a "move to register" or "extload into register" instruction, then
1028 // permute it into place, if the idx is a constant and if the idx is
1029 // supported by the target.
1030 MVT::ValueType VT = Tmp1.getValueType();
1031 MVT::ValueType EltVT = Tmp2.getValueType();
1032 MVT::ValueType IdxVT = Tmp3.getValueType();
1033 MVT::ValueType PtrVT = TLI.getPointerTy();
1034 SDOperand StackPtr = CreateStackTemporary(VT);
1035 // Store the vector.
1036 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Tmp1, StackPtr, NULL, 0);
1038 // Truncate or zero extend offset to target pointer type.
1039 unsigned CastOpc = (IdxVT > PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
1040 Tmp3 = DAG.getNode(CastOpc, PtrVT, Tmp3);
1041 // Add the offset to the index.
1042 unsigned EltSize = MVT::getSizeInBits(EltVT)/8;
1043 Tmp3 = DAG.getNode(ISD::MUL, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
1044 SDOperand StackPtr2 = DAG.getNode(ISD::ADD, IdxVT, Tmp3, StackPtr);
1045 // Store the scalar value.
1046 Ch = DAG.getStore(Ch, Tmp2, StackPtr2, NULL, 0);
1047 // Load the updated vector.
1048 Result = DAG.getLoad(VT, Ch, StackPtr, NULL, 0);
1053 case ISD::SCALAR_TO_VECTOR:
1054 if (!TLI.isTypeLegal(Node->getOperand(0).getValueType())) {
1055 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1059 Tmp1 = LegalizeOp(Node->getOperand(0)); // InVal
1060 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1061 switch (TLI.getOperationAction(ISD::SCALAR_TO_VECTOR,
1062 Node->getValueType(0))) {
1063 default: assert(0 && "This action is not supported yet!");
1064 case TargetLowering::Legal:
1066 case TargetLowering::Custom:
1067 Tmp3 = TLI.LowerOperation(Result, DAG);
1073 case TargetLowering::Expand:
1074 Result = LegalizeOp(ExpandSCALAR_TO_VECTOR(Node));
1078 case ISD::VECTOR_SHUFFLE:
1079 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the input vectors,
1080 Tmp2 = LegalizeOp(Node->getOperand(1)); // but not the shuffle mask.
1081 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1083 // Allow targets to custom lower the SHUFFLEs they support.
1084 switch (TLI.getOperationAction(ISD::VECTOR_SHUFFLE,Result.getValueType())) {
1085 default: assert(0 && "Unknown operation action!");
1086 case TargetLowering::Legal:
1087 assert(isShuffleLegal(Result.getValueType(), Node->getOperand(2)) &&
1088 "vector shuffle should not be created if not legal!");
1090 case TargetLowering::Custom:
1091 Tmp3 = TLI.LowerOperation(Result, DAG);
1097 case TargetLowering::Expand: {
1098 MVT::ValueType VT = Node->getValueType(0);
1099 MVT::ValueType EltVT = MVT::getVectorElementType(VT);
1100 MVT::ValueType PtrVT = TLI.getPointerTy();
1101 SDOperand Mask = Node->getOperand(2);
1102 unsigned NumElems = Mask.getNumOperands();
1103 SmallVector<SDOperand,8> Ops;
1104 for (unsigned i = 0; i != NumElems; ++i) {
1105 SDOperand Arg = Mask.getOperand(i);
1106 if (Arg.getOpcode() == ISD::UNDEF) {
1107 Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
1109 assert(isa<ConstantSDNode>(Arg) && "Invalid VECTOR_SHUFFLE mask!");
1110 unsigned Idx = cast<ConstantSDNode>(Arg)->getValue();
1112 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1,
1113 DAG.getConstant(Idx, PtrVT)));
1115 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2,
1116 DAG.getConstant(Idx - NumElems, PtrVT)));
1119 Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
1122 case TargetLowering::Promote: {
1123 // Change base type to a different vector type.
1124 MVT::ValueType OVT = Node->getValueType(0);
1125 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
1127 // Cast the two input vectors.
1128 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
1129 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
1131 // Convert the shuffle mask to the right # elements.
1132 Tmp3 = SDOperand(isShuffleLegal(OVT, Node->getOperand(2)), 0);
1133 assert(Tmp3.Val && "Shuffle not legal?");
1134 Result = DAG.getNode(ISD::VECTOR_SHUFFLE, NVT, Tmp1, Tmp2, Tmp3);
1135 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
1141 case ISD::EXTRACT_VECTOR_ELT:
1142 Tmp1 = Node->getOperand(0);
1143 Tmp2 = LegalizeOp(Node->getOperand(1));
1144 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1145 Result = ExpandEXTRACT_VECTOR_ELT(Result);
1148 case ISD::EXTRACT_SUBVECTOR:
1149 Tmp1 = Node->getOperand(0);
1150 Tmp2 = LegalizeOp(Node->getOperand(1));
1151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1152 Result = ExpandEXTRACT_SUBVECTOR(Result);
1155 case ISD::CALLSEQ_START: {
1156 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1158 // Recursively Legalize all of the inputs of the call end that do not lead
1159 // to this call start. This ensures that any libcalls that need be inserted
1160 // are inserted *before* the CALLSEQ_START.
1161 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1162 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1163 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).Val, Node,
1167 // Now that we legalized all of the inputs (which may have inserted
1168 // libcalls) create the new CALLSEQ_START node.
1169 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1171 // Merge in the last call, to ensure that this call start after the last
1173 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1174 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1175 Tmp1 = LegalizeOp(Tmp1);
1178 // Do not try to legalize the target-specific arguments (#1+).
1179 if (Tmp1 != Node->getOperand(0)) {
1180 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1182 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1185 // Remember that the CALLSEQ_START is legalized.
1186 AddLegalizedOperand(Op.getValue(0), Result);
1187 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1188 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1190 // Now that the callseq_start and all of the non-call nodes above this call
1191 // sequence have been legalized, legalize the call itself. During this
1192 // process, no libcalls can/will be inserted, guaranteeing that no calls
1194 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1195 SDOperand InCallSEQ = LastCALLSEQ_END;
1196 // Note that we are selecting this call!
1197 LastCALLSEQ_END = SDOperand(CallEnd, 0);
1198 IsLegalizingCall = true;
1200 // Legalize the call, starting from the CALLSEQ_END.
1201 LegalizeOp(LastCALLSEQ_END);
1202 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1205 case ISD::CALLSEQ_END:
1206 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1207 // will cause this node to be legalized as well as handling libcalls right.
1208 if (LastCALLSEQ_END.Val != Node) {
1209 LegalizeOp(SDOperand(FindCallStartFromCallEnd(Node), 0));
1210 DenseMap<SDOperand, SDOperand>::iterator I = LegalizedNodes.find(Op);
1211 assert(I != LegalizedNodes.end() &&
1212 "Legalizing the call start should have legalized this node!");
1216 // Otherwise, the call start has been legalized and everything is going
1217 // according to plan. Just legalize ourselves normally here.
1218 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1219 // Do not try to legalize the target-specific arguments (#1+), except for
1220 // an optional flag input.
1221 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1222 if (Tmp1 != Node->getOperand(0)) {
1223 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1225 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1228 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1229 if (Tmp1 != Node->getOperand(0) ||
1230 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1231 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1234 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1237 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1238 // This finishes up call legalization.
1239 IsLegalizingCall = false;
1241 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1242 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1243 if (Node->getNumValues() == 2)
1244 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1245 return Result.getValue(Op.ResNo);
1246 case ISD::DYNAMIC_STACKALLOC: {
1247 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1248 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the size.
1249 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the alignment.
1250 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1252 Tmp1 = Result.getValue(0);
1253 Tmp2 = Result.getValue(1);
1254 switch (TLI.getOperationAction(Node->getOpcode(),
1255 Node->getValueType(0))) {
1256 default: assert(0 && "This action is not supported yet!");
1257 case TargetLowering::Expand: {
1258 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1259 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1260 " not tell us which reg is the stack pointer!");
1261 SDOperand Chain = Tmp1.getOperand(0);
1262 SDOperand Size = Tmp2.getOperand(1);
1263 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, Node->getValueType(0));
1264 Tmp1 = DAG.getNode(ISD::SUB, Node->getValueType(0), SP, Size); // Value
1265 Tmp2 = DAG.getCopyToReg(SP.getValue(1), SPReg, Tmp1); // Output chain
1266 Tmp1 = LegalizeOp(Tmp1);
1267 Tmp2 = LegalizeOp(Tmp2);
1270 case TargetLowering::Custom:
1271 Tmp3 = TLI.LowerOperation(Tmp1, DAG);
1273 Tmp1 = LegalizeOp(Tmp3);
1274 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1277 case TargetLowering::Legal:
1280 // Since this op produce two values, make sure to remember that we
1281 // legalized both of them.
1282 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1283 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1284 return Op.ResNo ? Tmp2 : Tmp1;
1286 case ISD::INLINEASM: {
1287 SmallVector<SDOperand, 8> Ops(Node->op_begin(), Node->op_end());
1288 bool Changed = false;
1289 // Legalize all of the operands of the inline asm, in case they are nodes
1290 // that need to be expanded or something. Note we skip the asm string and
1291 // all of the TargetConstant flags.
1292 SDOperand Op = LegalizeOp(Ops[0]);
1293 Changed = Op != Ops[0];
1296 bool HasInFlag = Ops.back().getValueType() == MVT::Flag;
1297 for (unsigned i = 2, e = Ops.size()-HasInFlag; i < e; ) {
1298 unsigned NumVals = cast<ConstantSDNode>(Ops[i])->getValue() >> 3;
1299 for (++i; NumVals; ++i, --NumVals) {
1300 SDOperand Op = LegalizeOp(Ops[i]);
1309 Op = LegalizeOp(Ops.back());
1310 Changed |= Op != Ops.back();
1315 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1317 // INLINE asm returns a chain and flag, make sure to add both to the map.
1318 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1319 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1320 return Result.getValue(Op.ResNo);
1323 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1324 // Ensure that libcalls are emitted before a branch.
1325 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1326 Tmp1 = LegalizeOp(Tmp1);
1327 LastCALLSEQ_END = DAG.getEntryNode();
1329 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1332 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1333 // Ensure that libcalls are emitted before a branch.
1334 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1335 Tmp1 = LegalizeOp(Tmp1);
1336 LastCALLSEQ_END = DAG.getEntryNode();
1338 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1339 default: assert(0 && "Indirect target must be legal type (pointer)!");
1341 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1344 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1347 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1348 // Ensure that libcalls are emitted before a branch.
1349 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1350 Tmp1 = LegalizeOp(Tmp1);
1351 LastCALLSEQ_END = DAG.getEntryNode();
1353 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the jumptable node.
1354 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1356 switch (TLI.getOperationAction(ISD::BR_JT, MVT::Other)) {
1357 default: assert(0 && "This action is not supported yet!");
1358 case TargetLowering::Legal: break;
1359 case TargetLowering::Custom:
1360 Tmp1 = TLI.LowerOperation(Result, DAG);
1361 if (Tmp1.Val) Result = Tmp1;
1363 case TargetLowering::Expand: {
1364 SDOperand Chain = Result.getOperand(0);
1365 SDOperand Table = Result.getOperand(1);
1366 SDOperand Index = Result.getOperand(2);
1368 MVT::ValueType PTy = TLI.getPointerTy();
1369 MachineFunction &MF = DAG.getMachineFunction();
1370 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
1371 Index= DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(EntrySize, PTy));
1372 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1375 switch (EntrySize) {
1376 default: assert(0 && "Size of jump table not supported yet."); break;
1377 case 4: LD = DAG.getLoad(MVT::i32, Chain, Addr, NULL, 0); break;
1378 case 8: LD = DAG.getLoad(MVT::i64, Chain, Addr, NULL, 0); break;
1381 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1382 // For PIC, the sequence is:
1383 // BRIND(load(Jumptable + index) + RelocBase)
1384 // RelocBase is the JumpTable on PPC and X86, GOT on Alpha
1386 if (TLI.usesGlobalOffsetTable())
1387 Reloc = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PTy);
1390 Addr = (PTy != MVT::i32) ? DAG.getNode(ISD::SIGN_EXTEND, PTy, LD) : LD;
1391 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Reloc);
1392 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), Addr);
1394 Result = DAG.getNode(ISD::BRIND, MVT::Other, LD.getValue(1), LD);
1400 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1401 // Ensure that libcalls are emitted before a return.
1402 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1403 Tmp1 = LegalizeOp(Tmp1);
1404 LastCALLSEQ_END = DAG.getEntryNode();
1406 switch (getTypeAction(Node->getOperand(1).getValueType())) {
1407 case Expand: assert(0 && "It's impossible to expand bools");
1409 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the condition.
1412 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the condition.
1414 // The top bits of the promoted condition are not necessarily zero, ensure
1415 // that the value is properly zero extended.
1416 if (!DAG.MaskedValueIsZero(Tmp2,
1417 MVT::getIntVTBitMask(Tmp2.getValueType())^1))
1418 Tmp2 = DAG.getZeroExtendInReg(Tmp2, MVT::i1);
1422 // Basic block destination (Op#2) is always legal.
1423 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
1425 switch (TLI.getOperationAction(ISD::BRCOND, MVT::Other)) {
1426 default: assert(0 && "This action is not supported yet!");
1427 case TargetLowering::Legal: break;
1428 case TargetLowering::Custom:
1429 Tmp1 = TLI.LowerOperation(Result, DAG);
1430 if (Tmp1.Val) Result = Tmp1;
1432 case TargetLowering::Expand:
1433 // Expand brcond's setcc into its constituent parts and create a BR_CC
1435 if (Tmp2.getOpcode() == ISD::SETCC) {
1436 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1, Tmp2.getOperand(2),
1437 Tmp2.getOperand(0), Tmp2.getOperand(1),
1438 Node->getOperand(2));
1440 Result = DAG.getNode(ISD::BR_CC, MVT::Other, Tmp1,
1441 DAG.getCondCode(ISD::SETNE), Tmp2,
1442 DAG.getConstant(0, Tmp2.getValueType()),
1443 Node->getOperand(2));
1449 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1450 // Ensure that libcalls are emitted before a branch.
1451 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1452 Tmp1 = LegalizeOp(Tmp1);
1453 Tmp2 = Node->getOperand(2); // LHS
1454 Tmp3 = Node->getOperand(3); // RHS
1455 Tmp4 = Node->getOperand(1); // CC
1457 LegalizeSetCCOperands(Tmp2, Tmp3, Tmp4);
1458 LastCALLSEQ_END = DAG.getEntryNode();
1460 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
1461 // the LHS is a legal SETCC itself. In this case, we need to compare
1462 // the result against zero to select between true and false values.
1463 if (Tmp3.Val == 0) {
1464 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
1465 Tmp4 = DAG.getCondCode(ISD::SETNE);
1468 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp4, Tmp2, Tmp3,
1469 Node->getOperand(4));
1471 switch (TLI.getOperationAction(ISD::BR_CC, Tmp3.getValueType())) {
1472 default: assert(0 && "Unexpected action for BR_CC!");
1473 case TargetLowering::Legal: break;
1474 case TargetLowering::Custom:
1475 Tmp4 = TLI.LowerOperation(Result, DAG);
1476 if (Tmp4.Val) Result = Tmp4;
1481 LoadSDNode *LD = cast<LoadSDNode>(Node);
1482 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1483 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1485 ISD::LoadExtType ExtType = LD->getExtensionType();
1486 if (ExtType == ISD::NON_EXTLOAD) {
1487 MVT::ValueType VT = Node->getValueType(0);
1488 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1489 Tmp3 = Result.getValue(0);
1490 Tmp4 = Result.getValue(1);
1492 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1493 default: assert(0 && "This action is not supported yet!");
1494 case TargetLowering::Legal: break;
1495 case TargetLowering::Custom:
1496 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1498 Tmp3 = LegalizeOp(Tmp1);
1499 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1502 case TargetLowering::Promote: {
1503 // Only promote a load of vector type to another.
1504 assert(MVT::isVector(VT) && "Cannot promote this load!");
1505 // Change base type to a different vector type.
1506 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1508 Tmp1 = DAG.getLoad(NVT, Tmp1, Tmp2, LD->getSrcValue(),
1509 LD->getSrcValueOffset(),
1510 LD->isVolatile(), LD->getAlignment());
1511 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp1));
1512 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1516 // Since loads produce two values, make sure to remember that we
1517 // legalized both of them.
1518 AddLegalizedOperand(SDOperand(Node, 0), Tmp3);
1519 AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
1520 return Op.ResNo ? Tmp4 : Tmp3;
1522 MVT::ValueType SrcVT = LD->getLoadedVT();
1523 switch (TLI.getLoadXAction(ExtType, SrcVT)) {
1524 default: assert(0 && "This action is not supported yet!");
1525 case TargetLowering::Promote:
1526 assert(SrcVT == MVT::i1 &&
1527 "Can only promote extending LOAD from i1 -> i8!");
1528 Result = DAG.getExtLoad(ExtType, Node->getValueType(0), Tmp1, Tmp2,
1529 LD->getSrcValue(), LD->getSrcValueOffset(),
1530 MVT::i8, LD->isVolatile(), LD->getAlignment());
1531 Tmp1 = Result.getValue(0);
1532 Tmp2 = Result.getValue(1);
1534 case TargetLowering::Custom:
1537 case TargetLowering::Legal:
1538 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1539 Tmp1 = Result.getValue(0);
1540 Tmp2 = Result.getValue(1);
1543 Tmp3 = TLI.LowerOperation(Result, DAG);
1545 Tmp1 = LegalizeOp(Tmp3);
1546 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1550 case TargetLowering::Expand:
1551 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1552 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1553 SDOperand Load = DAG.getLoad(SrcVT, Tmp1, Tmp2, LD->getSrcValue(),
1554 LD->getSrcValueOffset(),
1555 LD->isVolatile(), LD->getAlignment());
1556 Result = DAG.getNode(ISD::FP_EXTEND, Node->getValueType(0), Load);
1557 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1558 Tmp2 = LegalizeOp(Load.getValue(1));
1561 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1562 // Turn the unsupported load into an EXTLOAD followed by an explicit
1563 // zero/sign extend inreg.
1564 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
1565 Tmp1, Tmp2, LD->getSrcValue(),
1566 LD->getSrcValueOffset(), SrcVT,
1567 LD->isVolatile(), LD->getAlignment());
1569 if (ExtType == ISD::SEXTLOAD)
1570 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
1571 Result, DAG.getValueType(SrcVT));
1573 ValRes = DAG.getZeroExtendInReg(Result, SrcVT);
1574 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1575 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1578 // Since loads produce two values, make sure to remember that we legalized
1580 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1581 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1582 return Op.ResNo ? Tmp2 : Tmp1;
1585 case ISD::EXTRACT_ELEMENT: {
1586 MVT::ValueType OpTy = Node->getOperand(0).getValueType();
1587 switch (getTypeAction(OpTy)) {
1588 default: assert(0 && "EXTRACT_ELEMENT action for type unimplemented!");
1590 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue()) {
1592 Result = DAG.getNode(ISD::SRL, OpTy, Node->getOperand(0),
1593 DAG.getConstant(MVT::getSizeInBits(OpTy)/2,
1594 TLI.getShiftAmountTy()));
1595 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Result);
1598 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0),
1599 Node->getOperand(0));
1603 // Get both the low and high parts.
1604 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
1605 if (cast<ConstantSDNode>(Node->getOperand(1))->getValue())
1606 Result = Tmp2; // 1 -> Hi
1608 Result = Tmp1; // 0 -> Lo
1614 case ISD::CopyToReg:
1615 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1617 assert(isTypeLegal(Node->getOperand(2).getValueType()) &&
1618 "Register type must be legal!");
1619 // Legalize the incoming value (must be a legal type).
1620 Tmp2 = LegalizeOp(Node->getOperand(2));
1621 if (Node->getNumValues() == 1) {
1622 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2);
1624 assert(Node->getNumValues() == 2 && "Unknown CopyToReg");
1625 if (Node->getNumOperands() == 4) {
1626 Tmp3 = LegalizeOp(Node->getOperand(3));
1627 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1), Tmp2,
1630 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1),Tmp2);
1633 // Since this produces two values, make sure to remember that we legalized
1635 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
1636 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
1642 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1644 // Ensure that libcalls are emitted before a return.
1645 Tmp1 = DAG.getNode(ISD::TokenFactor, MVT::Other, Tmp1, LastCALLSEQ_END);
1646 Tmp1 = LegalizeOp(Tmp1);
1647 LastCALLSEQ_END = DAG.getEntryNode();
1649 switch (Node->getNumOperands()) {
1651 Tmp2 = Node->getOperand(1);
1652 Tmp3 = Node->getOperand(2); // Signness
1653 switch (getTypeAction(Tmp2.getValueType())) {
1655 Result = DAG.UpdateNodeOperands(Result, Tmp1, LegalizeOp(Tmp2), Tmp3);
1658 if (!MVT::isVector(Tmp2.getValueType())) {
1660 ExpandOp(Tmp2, Lo, Hi);
1662 // Big endian systems want the hi reg first.
1663 if (!TLI.isLittleEndian())
1667 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1669 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3);
1670 Result = LegalizeOp(Result);
1672 SDNode *InVal = Tmp2.Val;
1673 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1674 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1676 // Figure out if there is a simple type corresponding to this Vector
1677 // type. If so, convert to the vector type.
1678 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1679 if (TLI.isTypeLegal(TVT)) {
1680 // Turn this into a return of the vector type.
1681 Tmp2 = LegalizeOp(Tmp2);
1682 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1683 } else if (NumElems == 1) {
1684 // Turn this into a return of the scalar type.
1685 Tmp2 = ScalarizeVectorOp(Tmp2);
1686 Tmp2 = LegalizeOp(Tmp2);
1687 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1689 // FIXME: Returns of gcc generic vectors smaller than a legal type
1690 // should be returned in integer registers!
1692 // The scalarized value type may not be legal, e.g. it might require
1693 // promotion or expansion. Relegalize the return.
1694 Result = LegalizeOp(Result);
1696 // FIXME: Returns of gcc generic vectors larger than a legal vector
1697 // type should be returned by reference!
1699 SplitVectorOp(Tmp2, Lo, Hi);
1700 Result = DAG.getNode(ISD::RET, MVT::Other, Tmp1, Lo, Tmp3, Hi,Tmp3);
1701 Result = LegalizeOp(Result);
1706 Tmp2 = PromoteOp(Node->getOperand(1));
1707 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
1708 Result = LegalizeOp(Result);
1713 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1715 default: { // ret <values>
1716 SmallVector<SDOperand, 8> NewValues;
1717 NewValues.push_back(Tmp1);
1718 for (unsigned i = 1, e = Node->getNumOperands(); i < e; i += 2)
1719 switch (getTypeAction(Node->getOperand(i).getValueType())) {
1721 NewValues.push_back(LegalizeOp(Node->getOperand(i)));
1722 NewValues.push_back(Node->getOperand(i+1));
1726 assert(!MVT::isExtendedVT(Node->getOperand(i).getValueType()) &&
1727 "FIXME: TODO: implement returning non-legal vector types!");
1728 ExpandOp(Node->getOperand(i), Lo, Hi);
1729 NewValues.push_back(Lo);
1730 NewValues.push_back(Node->getOperand(i+1));
1732 NewValues.push_back(Hi);
1733 NewValues.push_back(Node->getOperand(i+1));
1738 assert(0 && "Can't promote multiple return value yet!");
1741 if (NewValues.size() == Node->getNumOperands())
1742 Result = DAG.UpdateNodeOperands(Result, &NewValues[0],NewValues.size());
1744 Result = DAG.getNode(ISD::RET, MVT::Other,
1745 &NewValues[0], NewValues.size());
1750 if (Result.getOpcode() == ISD::RET) {
1751 switch (TLI.getOperationAction(Result.getOpcode(), MVT::Other)) {
1752 default: assert(0 && "This action is not supported yet!");
1753 case TargetLowering::Legal: break;
1754 case TargetLowering::Custom:
1755 Tmp1 = TLI.LowerOperation(Result, DAG);
1756 if (Tmp1.Val) Result = Tmp1;
1762 StoreSDNode *ST = cast<StoreSDNode>(Node);
1763 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1764 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1765 int SVOffset = ST->getSrcValueOffset();
1766 unsigned Alignment = ST->getAlignment();
1767 bool isVolatile = ST->isVolatile();
1769 if (!ST->isTruncatingStore()) {
1770 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
1771 // FIXME: We shouldn't do this for TargetConstantFP's.
1772 // FIXME: move this to the DAG Combiner! Note that we can't regress due
1773 // to phase ordering between legalized code and the dag combiner. This
1774 // probably means that we need to integrate dag combiner and legalizer
1776 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
1777 if (CFP->getValueType(0) == MVT::f32) {
1778 Tmp3 = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
1780 assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
1781 Tmp3 = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
1783 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1784 SVOffset, isVolatile, Alignment);
1788 switch (getTypeAction(ST->getStoredVT())) {
1790 Tmp3 = LegalizeOp(ST->getValue());
1791 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1794 MVT::ValueType VT = Tmp3.getValueType();
1795 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1796 default: assert(0 && "This action is not supported yet!");
1797 case TargetLowering::Legal: break;
1798 case TargetLowering::Custom:
1799 Tmp1 = TLI.LowerOperation(Result, DAG);
1800 if (Tmp1.Val) Result = Tmp1;
1802 case TargetLowering::Promote:
1803 assert(MVT::isVector(VT) && "Unknown legal promote case!");
1804 Tmp3 = DAG.getNode(ISD::BIT_CONVERT,
1805 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1806 Result = DAG.getStore(Tmp1, Tmp3, Tmp2,
1807 ST->getSrcValue(), SVOffset, isVolatile,
1814 // Truncate the value and store the result.
1815 Tmp3 = PromoteOp(ST->getValue());
1816 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1817 SVOffset, ST->getStoredVT(),
1818 isVolatile, Alignment);
1822 unsigned IncrementSize = 0;
1825 // If this is a vector type, then we have to calculate the increment as
1826 // the product of the element size in bytes, and the number of elements
1827 // in the high half of the vector.
1828 if (MVT::isVector(ST->getValue().getValueType())) {
1829 SDNode *InVal = ST->getValue().Val;
1830 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
1831 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
1833 // Figure out if there is a simple type corresponding to this Vector
1834 // type. If so, convert to the vector type.
1835 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
1836 if (TLI.isTypeLegal(TVT)) {
1837 // Turn this into a normal store of the vector type.
1838 Tmp3 = LegalizeOp(Node->getOperand(1));
1839 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1840 SVOffset, isVolatile, Alignment);
1841 Result = LegalizeOp(Result);
1843 } else if (NumElems == 1) {
1844 // Turn this into a normal store of the scalar type.
1845 Tmp3 = ScalarizeVectorOp(Node->getOperand(1));
1846 Result = DAG.getStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1847 SVOffset, isVolatile, Alignment);
1848 // The scalarized value type may not be legal, e.g. it might require
1849 // promotion or expansion. Relegalize the scalar store.
1850 Result = LegalizeOp(Result);
1853 SplitVectorOp(Node->getOperand(1), Lo, Hi);
1854 IncrementSize = NumElems/2 * MVT::getSizeInBits(EVT)/8;
1857 ExpandOp(Node->getOperand(1), Lo, Hi);
1858 IncrementSize = Hi.Val ? MVT::getSizeInBits(Hi.getValueType())/8 : 0;
1860 if (!TLI.isLittleEndian())
1864 Lo = DAG.getStore(Tmp1, Lo, Tmp2, ST->getSrcValue(),
1865 SVOffset, isVolatile, Alignment);
1867 if (Hi.Val == NULL) {
1868 // Must be int <-> float one-to-one expansion.
1873 Tmp2 = DAG.getNode(ISD::ADD, Tmp2.getValueType(), Tmp2,
1874 getIntPtrConstant(IncrementSize));
1875 assert(isTypeLegal(Tmp2.getValueType()) &&
1876 "Pointers must be legal!");
1877 SVOffset += IncrementSize;
1878 if (Alignment > IncrementSize)
1879 Alignment = IncrementSize;
1880 Hi = DAG.getStore(Tmp1, Hi, Tmp2, ST->getSrcValue(),
1881 SVOffset, isVolatile, Alignment);
1882 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo, Hi);
1887 assert(isTypeLegal(ST->getValue().getValueType()) &&
1888 "Cannot handle illegal TRUNCSTORE yet!");
1889 Tmp3 = LegalizeOp(ST->getValue());
1891 // The only promote case we handle is TRUNCSTORE:i1 X into
1892 // -> TRUNCSTORE:i8 (and X, 1)
1893 if (ST->getStoredVT() == MVT::i1 &&
1894 TLI.getStoreXAction(MVT::i1) == TargetLowering::Promote) {
1895 // Promote the bool to a mask then store.
1896 Tmp3 = DAG.getNode(ISD::AND, Tmp3.getValueType(), Tmp3,
1897 DAG.getConstant(1, Tmp3.getValueType()));
1898 Result = DAG.getTruncStore(Tmp1, Tmp3, Tmp2, ST->getSrcValue(),
1900 isVolatile, Alignment);
1901 } else if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1902 Tmp2 != ST->getBasePtr()) {
1903 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1907 MVT::ValueType StVT = cast<StoreSDNode>(Result.Val)->getStoredVT();
1908 switch (TLI.getStoreXAction(StVT)) {
1909 default: assert(0 && "This action is not supported yet!");
1910 case TargetLowering::Legal: break;
1911 case TargetLowering::Custom:
1912 Tmp1 = TLI.LowerOperation(Result, DAG);
1913 if (Tmp1.Val) Result = Tmp1;
1920 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1921 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
1923 case ISD::STACKSAVE:
1924 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1925 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1926 Tmp1 = Result.getValue(0);
1927 Tmp2 = Result.getValue(1);
1929 switch (TLI.getOperationAction(ISD::STACKSAVE, MVT::Other)) {
1930 default: assert(0 && "This action is not supported yet!");
1931 case TargetLowering::Legal: break;
1932 case TargetLowering::Custom:
1933 Tmp3 = TLI.LowerOperation(Result, DAG);
1935 Tmp1 = LegalizeOp(Tmp3);
1936 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1939 case TargetLowering::Expand:
1940 // Expand to CopyFromReg if the target set
1941 // StackPointerRegisterToSaveRestore.
1942 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1943 Tmp1 = DAG.getCopyFromReg(Result.getOperand(0), SP,
1944 Node->getValueType(0));
1945 Tmp2 = Tmp1.getValue(1);
1947 Tmp1 = DAG.getNode(ISD::UNDEF, Node->getValueType(0));
1948 Tmp2 = Node->getOperand(0);
1953 // Since stacksave produce two values, make sure to remember that we
1954 // legalized both of them.
1955 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
1956 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
1957 return Op.ResNo ? Tmp2 : Tmp1;
1959 case ISD::STACKRESTORE:
1960 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1961 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
1962 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
1964 switch (TLI.getOperationAction(ISD::STACKRESTORE, MVT::Other)) {
1965 default: assert(0 && "This action is not supported yet!");
1966 case TargetLowering::Legal: break;
1967 case TargetLowering::Custom:
1968 Tmp1 = TLI.LowerOperation(Result, DAG);
1969 if (Tmp1.Val) Result = Tmp1;
1971 case TargetLowering::Expand:
1972 // Expand to CopyToReg if the target set
1973 // StackPointerRegisterToSaveRestore.
1974 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
1975 Result = DAG.getCopyToReg(Tmp1, SP, Tmp2);
1983 case ISD::READCYCLECOUNTER:
1984 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain
1985 Result = DAG.UpdateNodeOperands(Result, Tmp1);
1986 switch (TLI.getOperationAction(ISD::READCYCLECOUNTER,
1987 Node->getValueType(0))) {
1988 default: assert(0 && "This action is not supported yet!");
1989 case TargetLowering::Legal:
1990 Tmp1 = Result.getValue(0);
1991 Tmp2 = Result.getValue(1);
1993 case TargetLowering::Custom:
1994 Result = TLI.LowerOperation(Result, DAG);
1995 Tmp1 = LegalizeOp(Result.getValue(0));
1996 Tmp2 = LegalizeOp(Result.getValue(1));
2000 // Since rdcc produce two values, make sure to remember that we legalized
2002 AddLegalizedOperand(SDOperand(Node, 0), Tmp1);
2003 AddLegalizedOperand(SDOperand(Node, 1), Tmp2);
2007 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2008 case Expand: assert(0 && "It's impossible to expand bools");
2010 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the condition.
2013 Tmp1 = PromoteOp(Node->getOperand(0)); // Promote the condition.
2014 // Make sure the condition is either zero or one.
2015 if (!DAG.MaskedValueIsZero(Tmp1,
2016 MVT::getIntVTBitMask(Tmp1.getValueType())^1))
2017 Tmp1 = DAG.getZeroExtendInReg(Tmp1, MVT::i1);
2020 Tmp2 = LegalizeOp(Node->getOperand(1)); // TrueVal
2021 Tmp3 = LegalizeOp(Node->getOperand(2)); // FalseVal
2023 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2025 switch (TLI.getOperationAction(ISD::SELECT, Tmp2.getValueType())) {
2026 default: assert(0 && "This action is not supported yet!");
2027 case TargetLowering::Legal: break;
2028 case TargetLowering::Custom: {
2029 Tmp1 = TLI.LowerOperation(Result, DAG);
2030 if (Tmp1.Val) Result = Tmp1;
2033 case TargetLowering::Expand:
2034 if (Tmp1.getOpcode() == ISD::SETCC) {
2035 Result = DAG.getSelectCC(Tmp1.getOperand(0), Tmp1.getOperand(1),
2037 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2039 Result = DAG.getSelectCC(Tmp1,
2040 DAG.getConstant(0, Tmp1.getValueType()),
2041 Tmp2, Tmp3, ISD::SETNE);
2044 case TargetLowering::Promote: {
2045 MVT::ValueType NVT =
2046 TLI.getTypeToPromoteTo(ISD::SELECT, Tmp2.getValueType());
2047 unsigned ExtOp, TruncOp;
2048 if (MVT::isVector(Tmp2.getValueType())) {
2049 ExtOp = ISD::BIT_CONVERT;
2050 TruncOp = ISD::BIT_CONVERT;
2051 } else if (MVT::isInteger(Tmp2.getValueType())) {
2052 ExtOp = ISD::ANY_EXTEND;
2053 TruncOp = ISD::TRUNCATE;
2055 ExtOp = ISD::FP_EXTEND;
2056 TruncOp = ISD::FP_ROUND;
2058 // Promote each of the values to the new type.
2059 Tmp2 = DAG.getNode(ExtOp, NVT, Tmp2);
2060 Tmp3 = DAG.getNode(ExtOp, NVT, Tmp3);
2061 // Perform the larger operation, then round down.
2062 Result = DAG.getNode(ISD::SELECT, NVT, Tmp1, Tmp2,Tmp3);
2063 Result = DAG.getNode(TruncOp, Node->getValueType(0), Result);
2068 case ISD::SELECT_CC: {
2069 Tmp1 = Node->getOperand(0); // LHS
2070 Tmp2 = Node->getOperand(1); // RHS
2071 Tmp3 = LegalizeOp(Node->getOperand(2)); // True
2072 Tmp4 = LegalizeOp(Node->getOperand(3)); // False
2073 SDOperand CC = Node->getOperand(4);
2075 LegalizeSetCCOperands(Tmp1, Tmp2, CC);
2077 // If we didn't get both a LHS and RHS back from LegalizeSetCCOperands,
2078 // the LHS is a legal SETCC itself. In this case, we need to compare
2079 // the result against zero to select between true and false values.
2080 if (Tmp2.Val == 0) {
2081 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2082 CC = DAG.getCondCode(ISD::SETNE);
2084 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, CC);
2086 // Everything is legal, see if we should expand this op or something.
2087 switch (TLI.getOperationAction(ISD::SELECT_CC, Tmp3.getValueType())) {
2088 default: assert(0 && "This action is not supported yet!");
2089 case TargetLowering::Legal: break;
2090 case TargetLowering::Custom:
2091 Tmp1 = TLI.LowerOperation(Result, DAG);
2092 if (Tmp1.Val) Result = Tmp1;
2098 Tmp1 = Node->getOperand(0);
2099 Tmp2 = Node->getOperand(1);
2100 Tmp3 = Node->getOperand(2);
2101 LegalizeSetCCOperands(Tmp1, Tmp2, Tmp3);
2103 // If we had to Expand the SetCC operands into a SELECT node, then it may
2104 // not always be possible to return a true LHS & RHS. In this case, just
2105 // return the value we legalized, returned in the LHS
2106 if (Tmp2.Val == 0) {
2111 switch (TLI.getOperationAction(ISD::SETCC, Tmp1.getValueType())) {
2112 default: assert(0 && "Cannot handle this action for SETCC yet!");
2113 case TargetLowering::Custom:
2116 case TargetLowering::Legal:
2117 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2119 Tmp4 = TLI.LowerOperation(Result, DAG);
2120 if (Tmp4.Val) Result = Tmp4;
2123 case TargetLowering::Promote: {
2124 // First step, figure out the appropriate operation to use.
2125 // Allow SETCC to not be supported for all legal data types
2126 // Mostly this targets FP
2127 MVT::ValueType NewInTy = Node->getOperand(0).getValueType();
2128 MVT::ValueType OldVT = NewInTy; OldVT = OldVT;
2130 // Scan for the appropriate larger type to use.
2132 NewInTy = (MVT::ValueType)(NewInTy+1);
2134 assert(MVT::isInteger(NewInTy) == MVT::isInteger(OldVT) &&
2135 "Fell off of the edge of the integer world");
2136 assert(MVT::isFloatingPoint(NewInTy) == MVT::isFloatingPoint(OldVT) &&
2137 "Fell off of the edge of the floating point world");
2139 // If the target supports SETCC of this type, use it.
2140 if (TLI.isOperationLegal(ISD::SETCC, NewInTy))
2143 if (MVT::isInteger(NewInTy))
2144 assert(0 && "Cannot promote Legal Integer SETCC yet");
2146 Tmp1 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp1);
2147 Tmp2 = DAG.getNode(ISD::FP_EXTEND, NewInTy, Tmp2);
2149 Tmp1 = LegalizeOp(Tmp1);
2150 Tmp2 = LegalizeOp(Tmp2);
2151 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2152 Result = LegalizeOp(Result);
2155 case TargetLowering::Expand:
2156 // Expand a setcc node into a select_cc of the same condition, lhs, and
2157 // rhs that selects between const 1 (true) and const 0 (false).
2158 MVT::ValueType VT = Node->getValueType(0);
2159 Result = DAG.getNode(ISD::SELECT_CC, VT, Tmp1, Tmp2,
2160 DAG.getConstant(1, VT), DAG.getConstant(0, VT),
2167 case ISD::MEMMOVE: {
2168 Tmp1 = LegalizeOp(Node->getOperand(0)); // Chain
2169 Tmp2 = LegalizeOp(Node->getOperand(1)); // Pointer
2171 if (Node->getOpcode() == ISD::MEMSET) { // memset = ubyte
2172 switch (getTypeAction(Node->getOperand(2).getValueType())) {
2173 case Expand: assert(0 && "Cannot expand a byte!");
2175 Tmp3 = LegalizeOp(Node->getOperand(2));
2178 Tmp3 = PromoteOp(Node->getOperand(2));
2182 Tmp3 = LegalizeOp(Node->getOperand(2)); // memcpy/move = pointer,
2186 switch (getTypeAction(Node->getOperand(3).getValueType())) {
2188 // Length is too big, just take the lo-part of the length.
2190 ExpandOp(Node->getOperand(3), Tmp4, HiPart);
2194 Tmp4 = LegalizeOp(Node->getOperand(3));
2197 Tmp4 = PromoteOp(Node->getOperand(3));
2202 switch (getTypeAction(Node->getOperand(4).getValueType())) { // uint
2203 case Expand: assert(0 && "Cannot expand this yet!");
2205 Tmp5 = LegalizeOp(Node->getOperand(4));
2208 Tmp5 = PromoteOp(Node->getOperand(4));
2212 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2213 default: assert(0 && "This action not implemented for this operation!");
2214 case TargetLowering::Custom:
2217 case TargetLowering::Legal:
2218 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
2220 Tmp1 = TLI.LowerOperation(Result, DAG);
2221 if (Tmp1.Val) Result = Tmp1;
2224 case TargetLowering::Expand: {
2225 // Otherwise, the target does not support this operation. Lower the
2226 // operation to an explicit libcall as appropriate.
2227 MVT::ValueType IntPtr = TLI.getPointerTy();
2228 const Type *IntPtrTy = TLI.getTargetData()->getIntPtrType();
2229 TargetLowering::ArgListTy Args;
2230 TargetLowering::ArgListEntry Entry;
2232 const char *FnName = 0;
2233 if (Node->getOpcode() == ISD::MEMSET) {
2234 Entry.Node = Tmp2; Entry.Ty = IntPtrTy;
2235 Args.push_back(Entry);
2236 // Extend the (previously legalized) ubyte argument to be an int value
2238 if (Tmp3.getValueType() > MVT::i32)
2239 Tmp3 = DAG.getNode(ISD::TRUNCATE, MVT::i32, Tmp3);
2241 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Tmp3);
2242 Entry.Node = Tmp3; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
2243 Args.push_back(Entry);
2244 Entry.Node = Tmp4; Entry.Ty = IntPtrTy; Entry.isSExt = false;
2245 Args.push_back(Entry);
2248 } else if (Node->getOpcode() == ISD::MEMCPY ||
2249 Node->getOpcode() == ISD::MEMMOVE) {
2250 Entry.Ty = IntPtrTy;
2251 Entry.Node = Tmp2; Args.push_back(Entry);
2252 Entry.Node = Tmp3; Args.push_back(Entry);
2253 Entry.Node = Tmp4; Args.push_back(Entry);
2254 FnName = Node->getOpcode() == ISD::MEMMOVE ? "memmove" : "memcpy";
2256 assert(0 && "Unknown op!");
2259 std::pair<SDOperand,SDOperand> CallResult =
2260 TLI.LowerCallTo(Tmp1, Type::VoidTy, false, false, CallingConv::C, false,
2261 DAG.getExternalSymbol(FnName, IntPtr), Args, DAG);
2262 Result = CallResult.second;
2269 case ISD::SHL_PARTS:
2270 case ISD::SRA_PARTS:
2271 case ISD::SRL_PARTS: {
2272 SmallVector<SDOperand, 8> Ops;
2273 bool Changed = false;
2274 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
2275 Ops.push_back(LegalizeOp(Node->getOperand(i)));
2276 Changed |= Ops.back() != Node->getOperand(i);
2279 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
2281 switch (TLI.getOperationAction(Node->getOpcode(),
2282 Node->getValueType(0))) {
2283 default: assert(0 && "This action is not supported yet!");
2284 case TargetLowering::Legal: break;
2285 case TargetLowering::Custom:
2286 Tmp1 = TLI.LowerOperation(Result, DAG);
2288 SDOperand Tmp2, RetVal(0, 0);
2289 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
2290 Tmp2 = LegalizeOp(Tmp1.getValue(i));
2291 AddLegalizedOperand(SDOperand(Node, i), Tmp2);
2295 assert(RetVal.Val && "Illegal result number");
2301 // Since these produce multiple values, make sure to remember that we
2302 // legalized all of them.
2303 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2304 AddLegalizedOperand(SDOperand(Node, i), Result.getValue(i));
2305 return Result.getValue(Op.ResNo);
2326 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2327 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2328 case Expand: assert(0 && "Not possible");
2330 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2333 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2337 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2339 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2340 default: assert(0 && "BinOp legalize operation not supported");
2341 case TargetLowering::Legal: break;
2342 case TargetLowering::Custom:
2343 Tmp1 = TLI.LowerOperation(Result, DAG);
2344 if (Tmp1.Val) Result = Tmp1;
2346 case TargetLowering::Expand: {
2347 if (Node->getValueType(0) == MVT::i32) {
2348 switch (Node->getOpcode()) {
2349 default: assert(0 && "Do not know how to expand this integer BinOp!");
2352 RTLIB::Libcall LC = Node->getOpcode() == ISD::UDIV
2353 ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
2355 bool isSigned = Node->getOpcode() == ISD::SDIV;
2356 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2361 assert(MVT::isVector(Node->getValueType(0)) &&
2362 "Cannot expand this binary operator!");
2363 // Expand the operation into a bunch of nasty scalar code.
2364 SmallVector<SDOperand, 8> Ops;
2365 MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
2366 MVT::ValueType PtrVT = TLI.getPointerTy();
2367 for (unsigned i = 0, e = MVT::getVectorNumElements(Node->getValueType(0));
2369 SDOperand Idx = DAG.getConstant(i, PtrVT);
2370 SDOperand LHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp1, Idx);
2371 SDOperand RHS = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, EltVT, Tmp2, Idx);
2372 Ops.push_back(DAG.getNode(Node->getOpcode(), EltVT, LHS, RHS));
2374 Result = DAG.getNode(ISD::BUILD_VECTOR, Node->getValueType(0),
2375 &Ops[0], Ops.size());
2378 case TargetLowering::Promote: {
2379 switch (Node->getOpcode()) {
2380 default: assert(0 && "Do not know how to promote this BinOp!");
2384 MVT::ValueType OVT = Node->getValueType(0);
2385 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2386 assert(MVT::isVector(OVT) && "Cannot promote this BinOp!");
2387 // Bit convert each of the values to the new type.
2388 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp1);
2389 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, NVT, Tmp2);
2390 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
2391 // Bit convert the result back the original type.
2392 Result = DAG.getNode(ISD::BIT_CONVERT, OVT, Result);
2400 case ISD::FCOPYSIGN: // FCOPYSIGN does not require LHS/RHS to match type!
2401 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2402 switch (getTypeAction(Node->getOperand(1).getValueType())) {
2403 case Expand: assert(0 && "Not possible");
2405 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the RHS.
2408 Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
2412 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2414 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2415 default: assert(0 && "Operation not supported");
2416 case TargetLowering::Custom:
2417 Tmp1 = TLI.LowerOperation(Result, DAG);
2418 if (Tmp1.Val) Result = Tmp1;
2420 case TargetLowering::Legal: break;
2421 case TargetLowering::Expand: {
2422 // If this target supports fabs/fneg natively and select is cheap,
2423 // do this efficiently.
2424 if (!TLI.isSelectExpensive() &&
2425 TLI.getOperationAction(ISD::FABS, Tmp1.getValueType()) ==
2426 TargetLowering::Legal &&
2427 TLI.getOperationAction(ISD::FNEG, Tmp1.getValueType()) ==
2428 TargetLowering::Legal) {
2429 // Get the sign bit of the RHS.
2430 MVT::ValueType IVT =
2431 Tmp2.getValueType() == MVT::f32 ? MVT::i32 : MVT::i64;
2432 SDOperand SignBit = DAG.getNode(ISD::BIT_CONVERT, IVT, Tmp2);
2433 SignBit = DAG.getSetCC(TLI.getSetCCResultTy(),
2434 SignBit, DAG.getConstant(0, IVT), ISD::SETLT);
2435 // Get the absolute value of the result.
2436 SDOperand AbsVal = DAG.getNode(ISD::FABS, Tmp1.getValueType(), Tmp1);
2437 // Select between the nabs and abs value based on the sign bit of
2439 Result = DAG.getNode(ISD::SELECT, AbsVal.getValueType(), SignBit,
2440 DAG.getNode(ISD::FNEG, AbsVal.getValueType(),
2443 Result = LegalizeOp(Result);
2447 // Otherwise, do bitwise ops!
2448 MVT::ValueType NVT =
2449 Node->getValueType(0) == MVT::f32 ? MVT::i32 : MVT::i64;
2450 Result = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
2451 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0), Result);
2452 Result = LegalizeOp(Result);
2460 Tmp1 = LegalizeOp(Node->getOperand(0));
2461 Tmp2 = LegalizeOp(Node->getOperand(1));
2462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2463 // Since this produces two values, make sure to remember that we legalized
2465 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2466 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2471 Tmp1 = LegalizeOp(Node->getOperand(0));
2472 Tmp2 = LegalizeOp(Node->getOperand(1));
2473 Tmp3 = LegalizeOp(Node->getOperand(2));
2474 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
2475 // Since this produces two values, make sure to remember that we legalized
2477 AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
2478 AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
2481 case ISD::BUILD_PAIR: {
2482 MVT::ValueType PairTy = Node->getValueType(0);
2483 // TODO: handle the case where the Lo and Hi operands are not of legal type
2484 Tmp1 = LegalizeOp(Node->getOperand(0)); // Lo
2485 Tmp2 = LegalizeOp(Node->getOperand(1)); // Hi
2486 switch (TLI.getOperationAction(ISD::BUILD_PAIR, PairTy)) {
2487 case TargetLowering::Promote:
2488 case TargetLowering::Custom:
2489 assert(0 && "Cannot promote/custom this yet!");
2490 case TargetLowering::Legal:
2491 if (Tmp1 != Node->getOperand(0) || Tmp2 != Node->getOperand(1))
2492 Result = DAG.getNode(ISD::BUILD_PAIR, PairTy, Tmp1, Tmp2);
2494 case TargetLowering::Expand:
2495 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, PairTy, Tmp1);
2496 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, PairTy, Tmp2);
2497 Tmp2 = DAG.getNode(ISD::SHL, PairTy, Tmp2,
2498 DAG.getConstant(MVT::getSizeInBits(PairTy)/2,
2499 TLI.getShiftAmountTy()));
2500 Result = DAG.getNode(ISD::OR, PairTy, Tmp1, Tmp2);
2509 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2510 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2512 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2513 case TargetLowering::Promote: assert(0 && "Cannot promote this yet!");
2514 case TargetLowering::Custom:
2517 case TargetLowering::Legal:
2518 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2520 Tmp1 = TLI.LowerOperation(Result, DAG);
2521 if (Tmp1.Val) Result = Tmp1;
2524 case TargetLowering::Expand:
2525 unsigned DivOpc= (Node->getOpcode() == ISD::UREM) ? ISD::UDIV : ISD::SDIV;
2526 bool isSigned = DivOpc == ISD::SDIV;
2527 if (MVT::isInteger(Node->getValueType(0))) {
2528 if (TLI.getOperationAction(DivOpc, Node->getValueType(0)) ==
2529 TargetLowering::Legal) {
2531 MVT::ValueType VT = Node->getValueType(0);
2532 Result = DAG.getNode(DivOpc, VT, Tmp1, Tmp2);
2533 Result = DAG.getNode(ISD::MUL, VT, Result, Tmp2);
2534 Result = DAG.getNode(ISD::SUB, VT, Tmp1, Result);
2536 assert(Node->getValueType(0) == MVT::i32 &&
2537 "Cannot expand this binary operator!");
2538 RTLIB::Libcall LC = Node->getOpcode() == ISD::UREM
2539 ? RTLIB::UREM_I32 : RTLIB::SREM_I32;
2541 Result = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Dummy);
2544 // Floating point mod -> fmod libcall.
2545 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2546 ? RTLIB::REM_F32 : RTLIB::REM_F64;
2548 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2549 false/*sign irrelevant*/, Dummy);
2555 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2556 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2558 MVT::ValueType VT = Node->getValueType(0);
2559 switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
2560 default: assert(0 && "This action is not supported yet!");
2561 case TargetLowering::Custom:
2564 case TargetLowering::Legal:
2565 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2566 Result = Result.getValue(0);
2567 Tmp1 = Result.getValue(1);
2570 Tmp2 = TLI.LowerOperation(Result, DAG);
2572 Result = LegalizeOp(Tmp2);
2573 Tmp1 = LegalizeOp(Tmp2.getValue(1));
2577 case TargetLowering::Expand: {
2578 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
2579 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
2580 SV->getValue(), SV->getOffset());
2581 // Increment the pointer, VAList, to the next vaarg
2582 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
2583 DAG.getConstant(MVT::getSizeInBits(VT)/8,
2584 TLI.getPointerTy()));
2585 // Store the incremented VAList to the legalized pointer
2586 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
2588 // Load the actual argument out of the pointer VAList
2589 Result = DAG.getLoad(VT, Tmp3, VAList, NULL, 0);
2590 Tmp1 = LegalizeOp(Result.getValue(1));
2591 Result = LegalizeOp(Result);
2595 // Since VAARG produces two values, make sure to remember that we
2596 // legalized both of them.
2597 AddLegalizedOperand(SDOperand(Node, 0), Result);
2598 AddLegalizedOperand(SDOperand(Node, 1), Tmp1);
2599 return Op.ResNo ? Tmp1 : Result;
2603 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2604 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the dest pointer.
2605 Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the source pointer.
2607 switch (TLI.getOperationAction(ISD::VACOPY, MVT::Other)) {
2608 default: assert(0 && "This action is not supported yet!");
2609 case TargetLowering::Custom:
2612 case TargetLowering::Legal:
2613 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3,
2614 Node->getOperand(3), Node->getOperand(4));
2616 Tmp1 = TLI.LowerOperation(Result, DAG);
2617 if (Tmp1.Val) Result = Tmp1;
2620 case TargetLowering::Expand:
2621 // This defaults to loading a pointer from the input and storing it to the
2622 // output, returning the chain.
2623 SrcValueSDNode *SVD = cast<SrcValueSDNode>(Node->getOperand(3));
2624 SrcValueSDNode *SVS = cast<SrcValueSDNode>(Node->getOperand(4));
2625 Tmp4 = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp3, SVD->getValue(),
2627 Result = DAG.getStore(Tmp4.getValue(1), Tmp4, Tmp2, SVS->getValue(),
2634 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2635 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2637 switch (TLI.getOperationAction(ISD::VAEND, MVT::Other)) {
2638 default: assert(0 && "This action is not supported yet!");
2639 case TargetLowering::Custom:
2642 case TargetLowering::Legal:
2643 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2645 Tmp1 = TLI.LowerOperation(Tmp1, DAG);
2646 if (Tmp1.Val) Result = Tmp1;
2649 case TargetLowering::Expand:
2650 Result = Tmp1; // Default to a no-op, return the chain
2656 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
2657 Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
2659 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Node->getOperand(2));
2661 switch (TLI.getOperationAction(ISD::VASTART, MVT::Other)) {
2662 default: assert(0 && "This action is not supported yet!");
2663 case TargetLowering::Legal: break;
2664 case TargetLowering::Custom:
2665 Tmp1 = TLI.LowerOperation(Result, DAG);
2666 if (Tmp1.Val) Result = Tmp1;
2673 Tmp1 = LegalizeOp(Node->getOperand(0)); // LHS
2674 Tmp2 = LegalizeOp(Node->getOperand(1)); // RHS
2675 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
2676 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2678 assert(0 && "ROTL/ROTR legalize operation not supported");
2680 case TargetLowering::Legal:
2682 case TargetLowering::Custom:
2683 Tmp1 = TLI.LowerOperation(Result, DAG);
2684 if (Tmp1.Val) Result = Tmp1;
2686 case TargetLowering::Promote:
2687 assert(0 && "Do not know how to promote ROTL/ROTR");
2689 case TargetLowering::Expand:
2690 assert(0 && "Do not know how to expand ROTL/ROTR");
2696 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2697 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2698 case TargetLowering::Custom:
2699 assert(0 && "Cannot custom legalize this yet!");
2700 case TargetLowering::Legal:
2701 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2703 case TargetLowering::Promote: {
2704 MVT::ValueType OVT = Tmp1.getValueType();
2705 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2706 unsigned DiffBits = MVT::getSizeInBits(NVT) - MVT::getSizeInBits(OVT);
2708 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2709 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
2710 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
2711 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
2714 case TargetLowering::Expand:
2715 Result = ExpandBSWAP(Tmp1);
2723 Tmp1 = LegalizeOp(Node->getOperand(0)); // Op
2724 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2725 case TargetLowering::Custom: assert(0 && "Cannot custom handle this yet!");
2726 case TargetLowering::Legal:
2727 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2729 case TargetLowering::Promote: {
2730 MVT::ValueType OVT = Tmp1.getValueType();
2731 MVT::ValueType NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2733 // Zero extend the argument.
2734 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
2735 // Perform the larger operation, then subtract if needed.
2736 Tmp1 = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1);
2737 switch (Node->getOpcode()) {
2742 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2743 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
2744 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
2746 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
2747 DAG.getConstant(MVT::getSizeInBits(OVT),NVT), Tmp1);
2750 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2751 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
2752 DAG.getConstant(MVT::getSizeInBits(NVT) -
2753 MVT::getSizeInBits(OVT), NVT));
2758 case TargetLowering::Expand:
2759 Result = ExpandBitCount(Node->getOpcode(), Tmp1);
2770 Tmp1 = LegalizeOp(Node->getOperand(0));
2771 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
2772 case TargetLowering::Promote:
2773 case TargetLowering::Custom:
2776 case TargetLowering::Legal:
2777 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2779 Tmp1 = TLI.LowerOperation(Result, DAG);
2780 if (Tmp1.Val) Result = Tmp1;
2783 case TargetLowering::Expand:
2784 switch (Node->getOpcode()) {
2785 default: assert(0 && "Unreachable!");
2787 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2788 Tmp2 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2789 Result = DAG.getNode(ISD::FSUB, Node->getValueType(0), Tmp2, Tmp1);
2792 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2793 MVT::ValueType VT = Node->getValueType(0);
2794 Tmp2 = DAG.getConstantFP(0.0, VT);
2795 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1, Tmp2, ISD::SETUGT);
2796 Tmp3 = DAG.getNode(ISD::FNEG, VT, Tmp1);
2797 Result = DAG.getNode(ISD::SELECT, VT, Tmp2, Tmp1, Tmp3);
2803 MVT::ValueType VT = Node->getValueType(0);
2804 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2805 switch(Node->getOpcode()) {
2807 LC = VT == MVT::f32 ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
2810 LC = VT == MVT::f32 ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
2813 LC = VT == MVT::f32 ? RTLIB::COS_F32 : RTLIB::COS_F64;
2815 default: assert(0 && "Unreachable!");
2818 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2819 false/*sign irrelevant*/, Dummy);
2827 // We always lower FPOWI into a libcall. No target support it yet.
2828 RTLIB::Libcall LC = Node->getValueType(0) == MVT::f32
2829 ? RTLIB::POWI_F32 : RTLIB::POWI_F64;
2831 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
2832 false/*sign irrelevant*/, Dummy);
2835 case ISD::BIT_CONVERT:
2836 if (!isTypeLegal(Node->getOperand(0).getValueType())) {
2837 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2838 } else if (MVT::isVector(Op.getOperand(0).getValueType())) {
2839 // The input has to be a vector type, we have to either scalarize it, pack
2840 // it, or convert it based on whether the input vector type is legal.
2841 SDNode *InVal = Node->getOperand(0).Val;
2842 unsigned NumElems = MVT::getVectorNumElements(InVal->getValueType(0));
2843 MVT::ValueType EVT = MVT::getVectorElementType(InVal->getValueType(0));
2845 // Figure out if there is a simple type corresponding to this Vector
2846 // type. If so, convert to the vector type.
2847 MVT::ValueType TVT = MVT::getVectorType(EVT, NumElems);
2848 if (TLI.isTypeLegal(TVT)) {
2849 // Turn this into a bit convert of the vector input.
2850 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2851 LegalizeOp(Node->getOperand(0)));
2853 } else if (NumElems == 1) {
2854 // Turn this into a bit convert of the scalar input.
2855 Result = DAG.getNode(ISD::BIT_CONVERT, Node->getValueType(0),
2856 ScalarizeVectorOp(Node->getOperand(0)));
2859 // FIXME: UNIMP! Store then reload
2860 assert(0 && "Cast from unsupported vector type not implemented yet!");
2863 switch (TLI.getOperationAction(ISD::BIT_CONVERT,
2864 Node->getOperand(0).getValueType())) {
2865 default: assert(0 && "Unknown operation action!");
2866 case TargetLowering::Expand:
2867 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
2869 case TargetLowering::Legal:
2870 Tmp1 = LegalizeOp(Node->getOperand(0));
2871 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2877 // Conversion operators. The source and destination have different types.
2878 case ISD::SINT_TO_FP:
2879 case ISD::UINT_TO_FP: {
2880 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
2881 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2883 switch (TLI.getOperationAction(Node->getOpcode(),
2884 Node->getOperand(0).getValueType())) {
2885 default: assert(0 && "Unknown operation action!");
2886 case TargetLowering::Custom:
2889 case TargetLowering::Legal:
2890 Tmp1 = LegalizeOp(Node->getOperand(0));
2891 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2893 Tmp1 = TLI.LowerOperation(Result, DAG);
2894 if (Tmp1.Val) Result = Tmp1;
2897 case TargetLowering::Expand:
2898 Result = ExpandLegalINT_TO_FP(isSigned,
2899 LegalizeOp(Node->getOperand(0)),
2900 Node->getValueType(0));
2902 case TargetLowering::Promote:
2903 Result = PromoteLegalINT_TO_FP(LegalizeOp(Node->getOperand(0)),
2904 Node->getValueType(0),
2910 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP,
2911 Node->getValueType(0), Node->getOperand(0));
2914 Tmp1 = PromoteOp(Node->getOperand(0));
2916 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp1.getValueType(),
2917 Tmp1, DAG.getValueType(Node->getOperand(0).getValueType()));
2919 Tmp1 = DAG.getZeroExtendInReg(Tmp1,
2920 Node->getOperand(0).getValueType());
2922 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2923 Result = LegalizeOp(Result); // The 'op' is not necessarily legal!
2929 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2931 Tmp1 = LegalizeOp(Node->getOperand(0));
2932 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2935 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
2937 // Since the result is legal, we should just be able to truncate the low
2938 // part of the source.
2939 Result = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), Tmp1);
2942 Result = PromoteOp(Node->getOperand(0));
2943 Result = DAG.getNode(ISD::TRUNCATE, Op.getValueType(), Result);
2948 case ISD::FP_TO_SINT:
2949 case ISD::FP_TO_UINT:
2950 switch (getTypeAction(Node->getOperand(0).getValueType())) {
2952 Tmp1 = LegalizeOp(Node->getOperand(0));
2954 switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))){
2955 default: assert(0 && "Unknown operation action!");
2956 case TargetLowering::Custom:
2959 case TargetLowering::Legal:
2960 Result = DAG.UpdateNodeOperands(Result, Tmp1);
2962 Tmp1 = TLI.LowerOperation(Result, DAG);
2963 if (Tmp1.Val) Result = Tmp1;
2966 case TargetLowering::Promote:
2967 Result = PromoteLegalFP_TO_INT(Tmp1, Node->getValueType(0),
2968 Node->getOpcode() == ISD::FP_TO_SINT);
2970 case TargetLowering::Expand:
2971 if (Node->getOpcode() == ISD::FP_TO_UINT) {
2972 SDOperand True, False;
2973 MVT::ValueType VT = Node->getOperand(0).getValueType();
2974 MVT::ValueType NVT = Node->getValueType(0);
2975 unsigned ShiftAmt = MVT::getSizeInBits(Node->getValueType(0))-1;
2976 Tmp2 = DAG.getConstantFP((double)(1ULL << ShiftAmt), VT);
2977 Tmp3 = DAG.getSetCC(TLI.getSetCCResultTy(),
2978 Node->getOperand(0), Tmp2, ISD::SETLT);
2979 True = DAG.getNode(ISD::FP_TO_SINT, NVT, Node->getOperand(0));
2980 False = DAG.getNode(ISD::FP_TO_SINT, NVT,
2981 DAG.getNode(ISD::FSUB, VT, Node->getOperand(0),
2983 False = DAG.getNode(ISD::XOR, NVT, False,
2984 DAG.getConstant(1ULL << ShiftAmt, NVT));
2985 Result = DAG.getNode(ISD::SELECT, NVT, Tmp3, True, False);
2988 assert(0 && "Do not know how to expand FP_TO_SINT yet!");
2994 // Convert f32 / f64 to i32 / i64.
2995 MVT::ValueType VT = Op.getValueType();
2996 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
2997 switch (Node->getOpcode()) {
2998 case ISD::FP_TO_SINT:
2999 if (Node->getOperand(0).getValueType() == MVT::f32)
3000 LC = (VT == MVT::i32)
3001 ? RTLIB::FPTOSINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3003 LC = (VT == MVT::i32)
3004 ? RTLIB::FPTOSINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3006 case ISD::FP_TO_UINT:
3007 if (Node->getOperand(0).getValueType() == MVT::f32)
3008 LC = (VT == MVT::i32)
3009 ? RTLIB::FPTOUINT_F32_I32 : RTLIB::FPTOSINT_F32_I64;
3011 LC = (VT == MVT::i32)
3012 ? RTLIB::FPTOUINT_F64_I32 : RTLIB::FPTOSINT_F64_I64;
3014 default: assert(0 && "Unreachable!");
3017 Result = ExpandLibCall(TLI.getLibcallName(LC), Node,
3018 false/*sign irrelevant*/, Dummy);
3022 Tmp1 = PromoteOp(Node->getOperand(0));
3023 Result = DAG.UpdateNodeOperands(Result, LegalizeOp(Tmp1));
3024 Result = LegalizeOp(Result);
3030 if (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)) ==
3031 TargetLowering::Expand) {
3032 // The only way we can lower this is to turn it into a TRUNCSTORE,
3033 // EXTLOAD pair, targetting a temporary location (a stack slot).
3035 // NOTE: there is a choice here between constantly creating new stack
3036 // slots and always reusing the same one. We currently always create
3037 // new ones, as reuse may inhibit scheduling.
3038 MVT::ValueType VT = Op.getValueType(); // 32
3039 const Type *Ty = MVT::getTypeForValueType(VT);
3040 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3041 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3042 MachineFunction &MF = DAG.getMachineFunction();
3044 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3045 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3046 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3047 StackSlot, NULL, 0, VT);
3048 Result = DAG.getLoad(VT, Result, StackSlot, NULL, 0, VT);
3052 case ISD::ANY_EXTEND:
3053 case ISD::ZERO_EXTEND:
3054 case ISD::SIGN_EXTEND:
3055 case ISD::FP_EXTEND:
3056 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3057 case Expand: assert(0 && "Shouldn't need to expand other operators here!");
3059 Tmp1 = LegalizeOp(Node->getOperand(0));
3060 Result = DAG.UpdateNodeOperands(Result, Tmp1);
3063 switch (Node->getOpcode()) {
3064 case ISD::ANY_EXTEND:
3065 Tmp1 = PromoteOp(Node->getOperand(0));
3066 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Tmp1);
3068 case ISD::ZERO_EXTEND:
3069 Result = PromoteOp(Node->getOperand(0));
3070 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3071 Result = DAG.getZeroExtendInReg(Result,
3072 Node->getOperand(0).getValueType());
3074 case ISD::SIGN_EXTEND:
3075 Result = PromoteOp(Node->getOperand(0));
3076 Result = DAG.getNode(ISD::ANY_EXTEND, Op.getValueType(), Result);
3077 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3079 DAG.getValueType(Node->getOperand(0).getValueType()));
3081 case ISD::FP_EXTEND:
3082 Result = PromoteOp(Node->getOperand(0));
3083 if (Result.getValueType() != Op.getValueType())
3084 // Dynamically dead while we have only 2 FP types.
3085 Result = DAG.getNode(ISD::FP_EXTEND, Op.getValueType(), Result);
3088 Result = PromoteOp(Node->getOperand(0));
3089 Result = DAG.getNode(Node->getOpcode(), Op.getValueType(), Result);
3094 case ISD::FP_ROUND_INREG:
3095 case ISD::SIGN_EXTEND_INREG: {
3096 Tmp1 = LegalizeOp(Node->getOperand(0));
3097 MVT::ValueType ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
3099 // If this operation is not supported, convert it to a shl/shr or load/store
3101 switch (TLI.getOperationAction(Node->getOpcode(), ExtraVT)) {
3102 default: assert(0 && "This action not supported for this op yet!");
3103 case TargetLowering::Legal:
3104 Result = DAG.UpdateNodeOperands(Result, Tmp1, Node->getOperand(1));
3106 case TargetLowering::Expand:
3107 // If this is an integer extend and shifts are supported, do that.
3108 if (Node->getOpcode() == ISD::SIGN_EXTEND_INREG) {
3109 // NOTE: we could fall back on load/store here too for targets without
3110 // SAR. However, it is doubtful that any exist.
3111 unsigned BitsDiff = MVT::getSizeInBits(Node->getValueType(0)) -
3112 MVT::getSizeInBits(ExtraVT);
3113 SDOperand ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
3114 Result = DAG.getNode(ISD::SHL, Node->getValueType(0),
3115 Node->getOperand(0), ShiftCst);
3116 Result = DAG.getNode(ISD::SRA, Node->getValueType(0),
3118 } else if (Node->getOpcode() == ISD::FP_ROUND_INREG) {
3119 // The only way we can lower this is to turn it into a TRUNCSTORE,
3120 // EXTLOAD pair, targetting a temporary location (a stack slot).
3122 // NOTE: there is a choice here between constantly creating new stack
3123 // slots and always reusing the same one. We currently always create
3124 // new ones, as reuse may inhibit scheduling.
3125 const Type *Ty = MVT::getTypeForValueType(ExtraVT);
3126 uint64_t TySize = TLI.getTargetData()->getTypeSize(Ty);
3127 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty);
3128 MachineFunction &MF = DAG.getMachineFunction();
3130 MF.getFrameInfo()->CreateStackObject(TySize, Align);
3131 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
3132 Result = DAG.getTruncStore(DAG.getEntryNode(), Node->getOperand(0),
3133 StackSlot, NULL, 0, ExtraVT);
3134 Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
3135 Result, StackSlot, NULL, 0, ExtraVT);
3137 assert(0 && "Unknown op");
3145 assert(Result.getValueType() == Op.getValueType() &&
3146 "Bad legalization!");
3148 // Make sure that the generated code is itself legal.
3150 Result = LegalizeOp(Result);
3152 // Note that LegalizeOp may be reentered even from single-use nodes, which
3153 // means that we always must cache transformed nodes.
3154 AddLegalizedOperand(Op, Result);
3158 /// PromoteOp - Given an operation that produces a value in an invalid type,
3159 /// promote it to compute the value into a larger type. The produced value will
3160 /// have the correct bits for the low portion of the register, but no guarantee
3161 /// is made about the top bits: it may be zero, sign-extended, or garbage.
3162 SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
3163 MVT::ValueType VT = Op.getValueType();
3164 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3165 assert(getTypeAction(VT) == Promote &&
3166 "Caller should expand or legalize operands that are not promotable!");
3167 assert(NVT > VT && MVT::isInteger(NVT) == MVT::isInteger(VT) &&
3168 "Cannot promote to smaller type!");
3170 SDOperand Tmp1, Tmp2, Tmp3;
3172 SDNode *Node = Op.Val;
3174 DenseMap<SDOperand, SDOperand>::iterator I = PromotedNodes.find(Op);
3175 if (I != PromotedNodes.end()) return I->second;
3177 switch (Node->getOpcode()) {
3178 case ISD::CopyFromReg:
3179 assert(0 && "CopyFromReg must be legal!");
3182 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
3184 assert(0 && "Do not know how to promote this operator!");
3187 Result = DAG.getNode(ISD::UNDEF, NVT);
3191 Result = DAG.getNode(ISD::SIGN_EXTEND, NVT, Op);
3193 Result = DAG.getNode(ISD::ZERO_EXTEND, NVT, Op);
3194 assert(isa<ConstantSDNode>(Result) && "Didn't constant fold zext?");
3196 case ISD::ConstantFP:
3197 Result = DAG.getNode(ISD::FP_EXTEND, NVT, Op);
3198 assert(isa<ConstantFPSDNode>(Result) && "Didn't constant fold fp_extend?");
3202 assert(isTypeLegal(TLI.getSetCCResultTy()) && "SetCC type is not legal??");
3203 Result = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(),Node->getOperand(0),
3204 Node->getOperand(1), Node->getOperand(2));
3208 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3210 Result = LegalizeOp(Node->getOperand(0));
3211 assert(Result.getValueType() >= NVT &&
3212 "This truncation doesn't make sense!");
3213 if (Result.getValueType() > NVT) // Truncate to NVT instead of VT
3214 Result = DAG.getNode(ISD::TRUNCATE, NVT, Result);
3217 // The truncation is not required, because we don't guarantee anything
3218 // about high bits anyway.
3219 Result = PromoteOp(Node->getOperand(0));
3222 ExpandOp(Node->getOperand(0), Tmp1, Tmp2);
3223 // Truncate the low part of the expanded value to the result type
3224 Result = DAG.getNode(ISD::TRUNCATE, NVT, Tmp1);
3227 case ISD::SIGN_EXTEND:
3228 case ISD::ZERO_EXTEND:
3229 case ISD::ANY_EXTEND:
3230 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3231 case Expand: assert(0 && "BUG: Smaller reg should have been promoted!");
3233 // Input is legal? Just do extend all the way to the larger type.
3234 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3237 // Promote the reg if it's smaller.
3238 Result = PromoteOp(Node->getOperand(0));
3239 // The high bits are not guaranteed to be anything. Insert an extend.
3240 if (Node->getOpcode() == ISD::SIGN_EXTEND)
3241 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3242 DAG.getValueType(Node->getOperand(0).getValueType()));
3243 else if (Node->getOpcode() == ISD::ZERO_EXTEND)
3244 Result = DAG.getZeroExtendInReg(Result,
3245 Node->getOperand(0).getValueType());
3249 case ISD::BIT_CONVERT:
3250 Result = ExpandBIT_CONVERT(Node->getValueType(0), Node->getOperand(0));
3251 Result = PromoteOp(Result);
3254 case ISD::FP_EXTEND:
3255 assert(0 && "Case not implemented. Dynamically dead with 2 FP types!");
3257 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3258 case Expand: assert(0 && "BUG: Cannot expand FP regs!");
3259 case Promote: assert(0 && "Unreachable with 2 FP types!");
3261 // Input is legal? Do an FP_ROUND_INREG.
3262 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Node->getOperand(0),
3263 DAG.getValueType(VT));
3268 case ISD::SINT_TO_FP:
3269 case ISD::UINT_TO_FP:
3270 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3272 // No extra round required here.
3273 Result = DAG.getNode(Node->getOpcode(), NVT, Node->getOperand(0));
3277 Result = PromoteOp(Node->getOperand(0));
3278 if (Node->getOpcode() == ISD::SINT_TO_FP)
3279 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
3281 DAG.getValueType(Node->getOperand(0).getValueType()));
3283 Result = DAG.getZeroExtendInReg(Result,
3284 Node->getOperand(0).getValueType());
3285 // No extra round required here.
3286 Result = DAG.getNode(Node->getOpcode(), NVT, Result);
3289 Result = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, NVT,
3290 Node->getOperand(0));
3291 // Round if we cannot tolerate excess precision.
3292 if (NoExcessFPPrecision)
3293 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3294 DAG.getValueType(VT));
3299 case ISD::SIGN_EXTEND_INREG:
3300 Result = PromoteOp(Node->getOperand(0));
3301 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Result,
3302 Node->getOperand(1));
3304 case ISD::FP_TO_SINT:
3305 case ISD::FP_TO_UINT:
3306 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3309 Tmp1 = Node->getOperand(0);
3312 // The input result is prerounded, so we don't have to do anything
3314 Tmp1 = PromoteOp(Node->getOperand(0));
3317 // If we're promoting a UINT to a larger size, check to see if the new node
3318 // will be legal. If it isn't, check to see if FP_TO_SINT is legal, since
3319 // we can use that instead. This allows us to generate better code for
3320 // FP_TO_UINT for small destination sizes on targets where FP_TO_UINT is not
3321 // legal, such as PowerPC.
3322 if (Node->getOpcode() == ISD::FP_TO_UINT &&
3323 !TLI.isOperationLegal(ISD::FP_TO_UINT, NVT) &&
3324 (TLI.isOperationLegal(ISD::FP_TO_SINT, NVT) ||
3325 TLI.getOperationAction(ISD::FP_TO_SINT, NVT)==TargetLowering::Custom)){
3326 Result = DAG.getNode(ISD::FP_TO_SINT, NVT, Tmp1);
3328 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3334 Tmp1 = PromoteOp(Node->getOperand(0));
3335 assert(Tmp1.getValueType() == NVT);
3336 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3337 // NOTE: we do not have to do any extra rounding here for
3338 // NoExcessFPPrecision, because we know the input will have the appropriate
3339 // precision, and these operations don't modify precision at all.
3345 Tmp1 = PromoteOp(Node->getOperand(0));
3346 assert(Tmp1.getValueType() == NVT);
3347 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3348 if (NoExcessFPPrecision)
3349 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3350 DAG.getValueType(VT));
3354 // Promote f32 powi to f64 powi. Note that this could insert a libcall
3355 // directly as well, which may be better.
3356 Tmp1 = PromoteOp(Node->getOperand(0));
3357 assert(Tmp1.getValueType() == NVT);
3358 Result = DAG.getNode(ISD::FPOWI, NVT, Tmp1, Node->getOperand(1));
3359 if (NoExcessFPPrecision)
3360 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3361 DAG.getValueType(VT));
3371 // The input may have strange things in the top bits of the registers, but
3372 // these operations don't care. They may have weird bits going out, but
3373 // that too is okay if they are integer operations.
3374 Tmp1 = PromoteOp(Node->getOperand(0));
3375 Tmp2 = PromoteOp(Node->getOperand(1));
3376 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3377 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3382 Tmp1 = PromoteOp(Node->getOperand(0));
3383 Tmp2 = PromoteOp(Node->getOperand(1));
3384 assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
3385 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3387 // Floating point operations will give excess precision that we may not be
3388 // able to tolerate. If we DO allow excess precision, just leave it,
3389 // otherwise excise it.
3390 // FIXME: Why would we need to round FP ops more than integer ones?
3391 // Is Round(Add(Add(A,B),C)) != Round(Add(Round(Add(A,B)), C))
3392 if (NoExcessFPPrecision)
3393 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3394 DAG.getValueType(VT));
3399 // These operators require that their input be sign extended.
3400 Tmp1 = PromoteOp(Node->getOperand(0));
3401 Tmp2 = PromoteOp(Node->getOperand(1));
3402 if (MVT::isInteger(NVT)) {
3403 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3404 DAG.getValueType(VT));
3405 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3406 DAG.getValueType(VT));
3408 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3410 // Perform FP_ROUND: this is probably overly pessimistic.
3411 if (MVT::isFloatingPoint(NVT) && NoExcessFPPrecision)
3412 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3413 DAG.getValueType(VT));
3417 case ISD::FCOPYSIGN:
3418 // These operators require that their input be fp extended.
3419 switch (getTypeAction(Node->getOperand(0).getValueType())) {
3421 Tmp1 = LegalizeOp(Node->getOperand(0));
3424 Tmp1 = PromoteOp(Node->getOperand(0));
3427 assert(0 && "not implemented");
3429 switch (getTypeAction(Node->getOperand(1).getValueType())) {
3431 Tmp2 = LegalizeOp(Node->getOperand(1));
3434 Tmp2 = PromoteOp(Node->getOperand(1));
3437 assert(0 && "not implemented");
3439 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3441 // Perform FP_ROUND: this is probably overly pessimistic.
3442 if (NoExcessFPPrecision && Node->getOpcode() != ISD::FCOPYSIGN)
3443 Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result,
3444 DAG.getValueType(VT));
3449 // These operators require that their input be zero extended.
3450 Tmp1 = PromoteOp(Node->getOperand(0));
3451 Tmp2 = PromoteOp(Node->getOperand(1));
3452 assert(MVT::isInteger(NVT) && "Operators don't apply to FP!");
3453 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3454 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3455 Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
3459 Tmp1 = PromoteOp(Node->getOperand(0));
3460 Result = DAG.getNode(ISD::SHL, NVT, Tmp1, Node->getOperand(1));
3463 // The input value must be properly sign extended.
3464 Tmp1 = PromoteOp(Node->getOperand(0));
3465 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3466 DAG.getValueType(VT));
3467 Result = DAG.getNode(ISD::SRA, NVT, Tmp1, Node->getOperand(1));
3470 // The input value must be properly zero extended.
3471 Tmp1 = PromoteOp(Node->getOperand(0));
3472 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3473 Result = DAG.getNode(ISD::SRL, NVT, Tmp1, Node->getOperand(1));
3477 Tmp1 = Node->getOperand(0); // Get the chain.
3478 Tmp2 = Node->getOperand(1); // Get the pointer.
3479 if (TLI.getOperationAction(ISD::VAARG, VT) == TargetLowering::Custom) {
3480 Tmp3 = DAG.getVAArg(VT, Tmp1, Tmp2, Node->getOperand(2));
3481 Result = TLI.CustomPromoteOperation(Tmp3, DAG);
3483 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
3484 SDOperand VAList = DAG.getLoad(TLI.getPointerTy(), Tmp1, Tmp2,
3485 SV->getValue(), SV->getOffset());
3486 // Increment the pointer, VAList, to the next vaarg
3487 Tmp3 = DAG.getNode(ISD::ADD, TLI.getPointerTy(), VAList,
3488 DAG.getConstant(MVT::getSizeInBits(VT)/8,
3489 TLI.getPointerTy()));
3490 // Store the incremented VAList to the legalized pointer
3491 Tmp3 = DAG.getStore(VAList.getValue(1), Tmp3, Tmp2, SV->getValue(),
3493 // Load the actual argument out of the pointer VAList
3494 Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp3, VAList, NULL, 0, VT);
3496 // Remember that we legalized the chain.
3497 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3501 LoadSDNode *LD = cast<LoadSDNode>(Node);
3502 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
3503 ? ISD::EXTLOAD : LD->getExtensionType();
3504 Result = DAG.getExtLoad(ExtType, NVT,
3505 LD->getChain(), LD->getBasePtr(),
3506 LD->getSrcValue(), LD->getSrcValueOffset(),
3509 LD->getAlignment());
3510 // Remember that we legalized the chain.
3511 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
3515 Tmp2 = PromoteOp(Node->getOperand(1)); // Legalize the op0
3516 Tmp3 = PromoteOp(Node->getOperand(2)); // Legalize the op1
3517 Result = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), Tmp2, Tmp3);
3519 case ISD::SELECT_CC:
3520 Tmp2 = PromoteOp(Node->getOperand(2)); // True
3521 Tmp3 = PromoteOp(Node->getOperand(3)); // False
3522 Result = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
3523 Node->getOperand(1), Tmp2, Tmp3, Node->getOperand(4));
3526 Tmp1 = Node->getOperand(0);
3527 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Tmp1);
3528 Tmp1 = DAG.getNode(ISD::BSWAP, NVT, Tmp1);
3529 Result = DAG.getNode(ISD::SRL, NVT, Tmp1,
3530 DAG.getConstant(MVT::getSizeInBits(NVT) -
3531 MVT::getSizeInBits(VT),
3532 TLI.getShiftAmountTy()));
3537 // Zero extend the argument
3538 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
3539 // Perform the larger operation, then subtract if needed.
3540 Tmp1 = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
3541 switch(Node->getOpcode()) {
3546 // if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
3547 Tmp2 = DAG.getSetCC(TLI.getSetCCResultTy(), Tmp1,
3548 DAG.getConstant(MVT::getSizeInBits(NVT), NVT),
3550 Result = DAG.getNode(ISD::SELECT, NVT, Tmp2,
3551 DAG.getConstant(MVT::getSizeInBits(VT), NVT), Tmp1);
3554 //Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
3555 Result = DAG.getNode(ISD::SUB, NVT, Tmp1,
3556 DAG.getConstant(MVT::getSizeInBits(NVT) -
3557 MVT::getSizeInBits(VT), NVT));
3561 case ISD::EXTRACT_SUBVECTOR:
3562 Result = PromoteOp(ExpandEXTRACT_SUBVECTOR(Op));
3564 case ISD::EXTRACT_VECTOR_ELT:
3565 Result = PromoteOp(ExpandEXTRACT_VECTOR_ELT(Op));
3569 assert(Result.Val && "Didn't set a result!");
3571 // Make sure the result is itself legal.
3572 Result = LegalizeOp(Result);
3574 // Remember that we promoted this!
3575 AddPromotedOperand(Op, Result);
3579 /// ExpandEXTRACT_VECTOR_ELT - Expand an EXTRACT_VECTOR_ELT operation into
3580 /// a legal EXTRACT_VECTOR_ELT operation, scalar code, or memory traffic,
3581 /// based on the vector type. The return type of this matches the element type
3582 /// of the vector, which may not be legal for the target.
3583 SDOperand SelectionDAGLegalize::ExpandEXTRACT_VECTOR_ELT(SDOperand Op) {
3584 // We know that operand #0 is the Vec vector. If the index is a constant
3585 // or if the invec is a supported hardware type, we can use it. Otherwise,
3586 // lower to a store then an indexed load.
3587 SDOperand Vec = Op.getOperand(0);
3588 SDOperand Idx = Op.getOperand(1);
3590 SDNode *InVal = Vec.Val;
3591 MVT::ValueType TVT = InVal->getValueType(0);
3592 unsigned NumElems = MVT::getVectorNumElements(TVT);
3594 switch (TLI.getOperationAction(ISD::EXTRACT_VECTOR_ELT, TVT)) {
3595 default: assert(0 && "This action is not supported yet!");
3596 case TargetLowering::Custom: {
3597 Vec = LegalizeOp(Vec);
3598 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3599 SDOperand Tmp3 = TLI.LowerOperation(Op, DAG);
3604 case TargetLowering::Legal:
3605 if (isTypeLegal(TVT)) {
3606 Vec = LegalizeOp(Vec);
3607 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3611 case TargetLowering::Expand:
3615 if (NumElems == 1) {
3616 // This must be an access of the only element. Return it.
3617 Op = ScalarizeVectorOp(Vec);
3618 } else if (!TLI.isTypeLegal(TVT) && isa<ConstantSDNode>(Idx)) {
3619 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3621 SplitVectorOp(Vec, Lo, Hi);
3622 if (CIdx->getValue() < NumElems/2) {
3626 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2,
3627 Idx.getValueType());
3630 // It's now an extract from the appropriate high or low part. Recurse.
3631 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3632 Op = ExpandEXTRACT_VECTOR_ELT(Op);
3634 // Store the value to a temporary stack slot, then LOAD the scalar
3635 // element back out.
3636 SDOperand StackPtr = CreateStackTemporary(Vec.getValueType());
3637 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Vec, StackPtr, NULL, 0);
3639 // Add the offset to the index.
3640 unsigned EltSize = MVT::getSizeInBits(Op.getValueType())/8;
3641 Idx = DAG.getNode(ISD::MUL, Idx.getValueType(), Idx,
3642 DAG.getConstant(EltSize, Idx.getValueType()));
3643 StackPtr = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, StackPtr);
3645 Op = DAG.getLoad(Op.getValueType(), Ch, StackPtr, NULL, 0);
3650 /// ExpandEXTRACT_SUBVECTOR - Expand a EXTRACT_SUBVECTOR operation. For now
3651 /// we assume the operation can be split if it is not already legal.
3652 SDOperand SelectionDAGLegalize::ExpandEXTRACT_SUBVECTOR(SDOperand Op) {
3653 // We know that operand #0 is the Vec vector. For now we assume the index
3654 // is a constant and that the extracted result is a supported hardware type.
3655 SDOperand Vec = Op.getOperand(0);
3656 SDOperand Idx = LegalizeOp(Op.getOperand(1));
3658 unsigned NumElems = MVT::getVectorNumElements(Vec.getValueType());
3660 if (NumElems == MVT::getVectorNumElements(Op.getValueType())) {
3661 // This must be an access of the desired vector length. Return it.
3665 ConstantSDNode *CIdx = cast<ConstantSDNode>(Idx);
3667 SplitVectorOp(Vec, Lo, Hi);
3668 if (CIdx->getValue() < NumElems/2) {
3672 Idx = DAG.getConstant(CIdx->getValue() - NumElems/2, Idx.getValueType());
3675 // It's now an extract from the appropriate high or low part. Recurse.
3676 Op = DAG.UpdateNodeOperands(Op, Vec, Idx);
3677 return ExpandEXTRACT_SUBVECTOR(Op);
3680 /// LegalizeSetCCOperands - Attempts to create a legal LHS and RHS for a SETCC
3681 /// with condition CC on the current target. This usually involves legalizing
3682 /// or promoting the arguments. In the case where LHS and RHS must be expanded,
3683 /// there may be no choice but to create a new SetCC node to represent the
3684 /// legalized value of setcc lhs, rhs. In this case, the value is returned in
3685 /// LHS, and the SDOperand returned in RHS has a nil SDNode value.
3686 void SelectionDAGLegalize::LegalizeSetCCOperands(SDOperand &LHS,
3689 SDOperand Tmp1, Tmp2, Result;
3691 switch (getTypeAction(LHS.getValueType())) {
3693 Tmp1 = LegalizeOp(LHS); // LHS
3694 Tmp2 = LegalizeOp(RHS); // RHS
3697 Tmp1 = PromoteOp(LHS); // LHS
3698 Tmp2 = PromoteOp(RHS); // RHS
3700 // If this is an FP compare, the operands have already been extended.
3701 if (MVT::isInteger(LHS.getValueType())) {
3702 MVT::ValueType VT = LHS.getValueType();
3703 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
3705 // Otherwise, we have to insert explicit sign or zero extends. Note
3706 // that we could insert sign extends for ALL conditions, but zero extend
3707 // is cheaper on many machines (an AND instead of two shifts), so prefer
3709 switch (cast<CondCodeSDNode>(CC)->get()) {
3710 default: assert(0 && "Unknown integer comparison!");
3717 // ALL of these operations will work if we either sign or zero extend
3718 // the operands (including the unsigned comparisons!). Zero extend is
3719 // usually a simpler/cheaper operation, so prefer it.
3720 Tmp1 = DAG.getZeroExtendInReg(Tmp1, VT);
3721 Tmp2 = DAG.getZeroExtendInReg(Tmp2, VT);
3727 Tmp1 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp1,
3728 DAG.getValueType(VT));
3729 Tmp2 = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Tmp2,
3730 DAG.getValueType(VT));
3736 MVT::ValueType VT = LHS.getValueType();
3737 if (VT == MVT::f32 || VT == MVT::f64) {
3738 // Expand into one or more soft-fp libcall(s).
3739 RTLIB::Libcall LC1, LC2 = RTLIB::UNKNOWN_LIBCALL;
3740 switch (cast<CondCodeSDNode>(CC)->get()) {
3743 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3747 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
3751 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3755 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3759 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3763 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3766 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3769 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
3772 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
3773 switch (cast<CondCodeSDNode>(CC)->get()) {
3775 // SETONE = SETOLT | SETOGT
3776 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3779 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
3782 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
3785 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
3788 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
3791 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
3793 default: assert(0 && "Unsupported FP setcc!");
3798 Tmp1 = ExpandLibCall(TLI.getLibcallName(LC1),
3799 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3800 false /*sign irrelevant*/, Dummy);
3801 Tmp2 = DAG.getConstant(0, MVT::i32);
3802 CC = DAG.getCondCode(TLI.getCmpLibcallCC(LC1));
3803 if (LC2 != RTLIB::UNKNOWN_LIBCALL) {
3804 Tmp1 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), Tmp1, Tmp2, CC);
3805 LHS = ExpandLibCall(TLI.getLibcallName(LC2),
3806 DAG.getNode(ISD::MERGE_VALUES, VT, LHS, RHS).Val,
3807 false /*sign irrelevant*/, Dummy);
3808 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHS, Tmp2,
3809 DAG.getCondCode(TLI.getCmpLibcallCC(LC2)));
3810 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3818 SDOperand LHSLo, LHSHi, RHSLo, RHSHi;
3819 ExpandOp(LHS, LHSLo, LHSHi);
3820 ExpandOp(RHS, RHSLo, RHSHi);
3821 switch (cast<CondCodeSDNode>(CC)->get()) {
3825 if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo))
3826 if (RHSCST->isAllOnesValue()) {
3827 // Comparison to -1.
3828 Tmp1 = DAG.getNode(ISD::AND, LHSLo.getValueType(), LHSLo, LHSHi);
3833 Tmp1 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSLo, RHSLo);
3834 Tmp2 = DAG.getNode(ISD::XOR, LHSLo.getValueType(), LHSHi, RHSHi);
3835 Tmp1 = DAG.getNode(ISD::OR, Tmp1.getValueType(), Tmp1, Tmp2);
3836 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
3839 // If this is a comparison of the sign bit, just look at the top part.
3841 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(RHS))
3842 if ((cast<CondCodeSDNode>(CC)->get() == ISD::SETLT &&
3843 CST->getValue() == 0) || // X < 0
3844 (cast<CondCodeSDNode>(CC)->get() == ISD::SETGT &&
3845 CST->isAllOnesValue())) { // X > -1
3851 // FIXME: This generated code sucks.
3852 ISD::CondCode LowCC;
3853 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
3855 default: assert(0 && "Unknown integer setcc!");
3857 case ISD::SETULT: LowCC = ISD::SETULT; break;
3859 case ISD::SETUGT: LowCC = ISD::SETUGT; break;
3861 case ISD::SETULE: LowCC = ISD::SETULE; break;
3863 case ISD::SETUGE: LowCC = ISD::SETUGE; break;
3866 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
3867 // Tmp2 = hi(op1) < hi(op2) // Signedness depends on operands
3868 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
3870 // NOTE: on targets without efficient SELECT of bools, we can always use
3871 // this identity: (B1 ? B2 : B3) --> (B1 & B2)|(!B1&B3)
3872 TargetLowering::DAGCombinerInfo DagCombineInfo(DAG, false, true, NULL);
3873 Tmp1 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC,
3874 false, DagCombineInfo);
3876 Tmp1 = DAG.getSetCC(TLI.getSetCCResultTy(), LHSLo, RHSLo, LowCC);
3877 Tmp2 = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3878 CCCode, false, DagCombineInfo);
3880 Tmp2 = DAG.getNode(ISD::SETCC, TLI.getSetCCResultTy(), LHSHi, RHSHi, CC);
3882 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.Val);
3883 ConstantSDNode *Tmp2C = dyn_cast<ConstantSDNode>(Tmp2.Val);
3884 if ((Tmp1C && Tmp1C->getValue() == 0) ||
3885 (Tmp2C && Tmp2C->getValue() == 0 &&
3886 (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
3887 CCCode == ISD::SETUGE || CCCode == ISD::SETULE)) ||
3888 (Tmp2C && Tmp2C->getValue() == 1 &&
3889 (CCCode == ISD::SETLT || CCCode == ISD::SETGT ||
3890 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) {
3891 // low part is known false, returns high part.
3892 // For LE / GE, if high part is known false, ignore the low part.
3893 // For LT / GT, if high part is known true, ignore the low part.
3897 Result = TLI.SimplifySetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi,
3898 ISD::SETEQ, false, DagCombineInfo);
3900 Result=DAG.getSetCC(TLI.getSetCCResultTy(), LHSHi, RHSHi, ISD::SETEQ);
3901 Result = LegalizeOp(DAG.getNode(ISD::SELECT, Tmp1.getValueType(),
3902 Result, Tmp1, Tmp2));
3913 /// ExpandBIT_CONVERT - Expand a BIT_CONVERT node into a store/load combination.
3914 /// The resultant code need not be legal. Note that SrcOp is the input operand
3915 /// to the BIT_CONVERT, not the BIT_CONVERT node itself.
3916 SDOperand SelectionDAGLegalize::ExpandBIT_CONVERT(MVT::ValueType DestVT,
3918 // Create the stack frame object.
3919 SDOperand FIPtr = CreateStackTemporary(DestVT);
3921 // Emit a store to the stack slot.
3922 SDOperand Store = DAG.getStore(DAG.getEntryNode(), SrcOp, FIPtr, NULL, 0);
3923 // Result is a load from the stack slot.
3924 return DAG.getLoad(DestVT, Store, FIPtr, NULL, 0);
3927 SDOperand SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
3928 // Create a vector sized/aligned stack slot, store the value to element #0,
3929 // then load the whole vector back out.
3930 SDOperand StackPtr = CreateStackTemporary(Node->getValueType(0));
3931 SDOperand Ch = DAG.getStore(DAG.getEntryNode(), Node->getOperand(0), StackPtr,
3933 return DAG.getLoad(Node->getValueType(0), Ch, StackPtr, NULL, 0);
3937 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
3938 /// support the operation, but do support the resultant vector type.
3939 SDOperand SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
3941 // If the only non-undef value is the low element, turn this into a
3942 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
3943 unsigned NumElems = Node->getNumOperands();
3944 bool isOnlyLowElement = true;
3945 SDOperand SplatValue = Node->getOperand(0);
3946 std::map<SDOperand, std::vector<unsigned> > Values;
3947 Values[SplatValue].push_back(0);
3948 bool isConstant = true;
3949 if (!isa<ConstantFPSDNode>(SplatValue) && !isa<ConstantSDNode>(SplatValue) &&
3950 SplatValue.getOpcode() != ISD::UNDEF)
3953 for (unsigned i = 1; i < NumElems; ++i) {
3954 SDOperand V = Node->getOperand(i);
3955 Values[V].push_back(i);
3956 if (V.getOpcode() != ISD::UNDEF)
3957 isOnlyLowElement = false;
3958 if (SplatValue != V)
3959 SplatValue = SDOperand(0,0);
3961 // If this isn't a constant element or an undef, we can't use a constant
3963 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V) &&
3964 V.getOpcode() != ISD::UNDEF)
3968 if (isOnlyLowElement) {
3969 // If the low element is an undef too, then this whole things is an undef.
3970 if (Node->getOperand(0).getOpcode() == ISD::UNDEF)
3971 return DAG.getNode(ISD::UNDEF, Node->getValueType(0));
3972 // Otherwise, turn this into a scalar_to_vector node.
3973 return DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
3974 Node->getOperand(0));
3977 // If all elements are constants, create a load from the constant pool.
3979 MVT::ValueType VT = Node->getValueType(0);
3981 MVT::getTypeForValueType(Node->getOperand(0).getValueType());
3982 std::vector<Constant*> CV;
3983 for (unsigned i = 0, e = NumElems; i != e; ++i) {
3984 if (ConstantFPSDNode *V =
3985 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
3986 CV.push_back(ConstantFP::get(OpNTy, V->getValue()));
3987 } else if (ConstantSDNode *V =
3988 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
3989 CV.push_back(ConstantInt::get(OpNTy, V->getValue()));
3991 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
3992 CV.push_back(UndefValue::get(OpNTy));
3995 Constant *CP = ConstantVector::get(CV);
3996 SDOperand CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
3997 return DAG.getLoad(VT, DAG.getEntryNode(), CPIdx, NULL, 0);
4000 if (SplatValue.Val) { // Splat of one value?
4001 // Build the shuffle constant vector: <0, 0, 0, 0>
4002 MVT::ValueType MaskVT =
4003 MVT::getIntVectorWithNumElements(NumElems);
4004 SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
4005 std::vector<SDOperand> ZeroVec(NumElems, Zero);
4006 SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4007 &ZeroVec[0], ZeroVec.size());
4009 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4010 if (isShuffleLegal(Node->getValueType(0), SplatMask)) {
4011 // Get the splatted value into the low element of a vector register.
4012 SDOperand LowValVec =
4013 DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0), SplatValue);
4015 // Return shuffle(LowValVec, undef, <0,0,0,0>)
4016 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0), LowValVec,
4017 DAG.getNode(ISD::UNDEF, Node->getValueType(0)),
4022 // If there are only two unique elements, we may be able to turn this into a
4024 if (Values.size() == 2) {
4025 // Build the shuffle constant vector: e.g. <0, 4, 0, 4>
4026 MVT::ValueType MaskVT =
4027 MVT::getIntVectorWithNumElements(NumElems);
4028 std::vector<SDOperand> MaskVec(NumElems);
4030 for (std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4031 E = Values.end(); I != E; ++I) {
4032 for (std::vector<unsigned>::iterator II = I->second.begin(),
4033 EE = I->second.end(); II != EE; ++II)
4034 MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
4037 SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
4038 &MaskVec[0], MaskVec.size());
4040 // If the target supports VECTOR_SHUFFLE and this shuffle mask, use it.
4041 if (TLI.isOperationLegal(ISD::SCALAR_TO_VECTOR, Node->getValueType(0)) &&
4042 isShuffleLegal(Node->getValueType(0), ShuffleMask)) {
4043 SmallVector<SDOperand, 8> Ops;
4044 for(std::map<SDOperand,std::vector<unsigned> >::iterator I=Values.begin(),
4045 E = Values.end(); I != E; ++I) {
4046 SDOperand Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, Node->getValueType(0),
4050 Ops.push_back(ShuffleMask);
4052 // Return shuffle(LoValVec, HiValVec, <0,1,0,1>)
4053 return DAG.getNode(ISD::VECTOR_SHUFFLE, Node->getValueType(0),
4054 &Ops[0], Ops.size());
4058 // Otherwise, we can't handle this case efficiently. Allocate a sufficiently
4059 // aligned object on the stack, store each element into it, then load
4060 // the result as a vector.
4061 MVT::ValueType VT = Node->getValueType(0);
4062 // Create the stack frame object.
4063 SDOperand FIPtr = CreateStackTemporary(VT);
4065 // Emit a store of each element to the stack slot.
4066 SmallVector<SDOperand, 8> Stores;
4067 unsigned TypeByteSize =
4068 MVT::getSizeInBits(Node->getOperand(0).getValueType())/8;
4069 // Store (in the right endianness) the elements to memory.
4070 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4071 // Ignore undef elements.
4072 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
4074 unsigned Offset = TypeByteSize*i;
4076 SDOperand Idx = DAG.getConstant(Offset, FIPtr.getValueType());
4077 Idx = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr, Idx);
4079 Stores.push_back(DAG.getStore(DAG.getEntryNode(), Node->getOperand(i), Idx,
4083 SDOperand StoreChain;
4084 if (!Stores.empty()) // Not all undef elements?
4085 StoreChain = DAG.getNode(ISD::TokenFactor, MVT::Other,
4086 &Stores[0], Stores.size());
4088 StoreChain = DAG.getEntryNode();
4090 // Result is a load from the stack slot.
4091 return DAG.getLoad(VT, StoreChain, FIPtr, NULL, 0);
4094 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
4095 /// specified value type.
4096 SDOperand SelectionDAGLegalize::CreateStackTemporary(MVT::ValueType VT) {
4097 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4098 unsigned ByteSize = MVT::getSizeInBits(VT)/8;
4099 const Type *Ty = MVT::getTypeForValueType(VT);
4100 unsigned StackAlign = (unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty);
4101 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign);
4102 return DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
4105 void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
4106 SDOperand Op, SDOperand Amt,
4107 SDOperand &Lo, SDOperand &Hi) {
4108 // Expand the subcomponents.
4109 SDOperand LHSL, LHSH;
4110 ExpandOp(Op, LHSL, LHSH);
4112 SDOperand Ops[] = { LHSL, LHSH, Amt };
4113 MVT::ValueType VT = LHSL.getValueType();
4114 Lo = DAG.getNode(NodeOp, DAG.getNodeValueTypes(VT, VT), 2, Ops, 3);
4115 Hi = Lo.getValue(1);
4119 /// ExpandShift - Try to find a clever way to expand this shift operation out to
4120 /// smaller elements. If we can't find a way that is more efficient than a
4121 /// libcall on this target, return false. Otherwise, return true with the
4122 /// low-parts expanded into Lo and Hi.
4123 bool SelectionDAGLegalize::ExpandShift(unsigned Opc, SDOperand Op,SDOperand Amt,
4124 SDOperand &Lo, SDOperand &Hi) {
4125 assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) &&
4126 "This is not a shift!");
4128 MVT::ValueType NVT = TLI.getTypeToTransformTo(Op.getValueType());
4129 SDOperand ShAmt = LegalizeOp(Amt);
4130 MVT::ValueType ShTy = ShAmt.getValueType();
4131 unsigned VTBits = MVT::getSizeInBits(Op.getValueType());
4132 unsigned NVTBits = MVT::getSizeInBits(NVT);
4134 // Handle the case when Amt is an immediate. Other cases are currently broken
4135 // and are disabled.
4136 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Amt.Val)) {
4137 unsigned Cst = CN->getValue();
4138 // Expand the incoming operand to be shifted, so that we have its parts
4140 ExpandOp(Op, InL, InH);
4144 Lo = DAG.getConstant(0, NVT);
4145 Hi = DAG.getConstant(0, NVT);
4146 } else if (Cst > NVTBits) {
4147 Lo = DAG.getConstant(0, NVT);
4148 Hi = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst-NVTBits,ShTy));
4149 } else if (Cst == NVTBits) {
4150 Lo = DAG.getConstant(0, NVT);
4153 Lo = DAG.getNode(ISD::SHL, NVT, InL, DAG.getConstant(Cst, ShTy));
4154 Hi = DAG.getNode(ISD::OR, NVT,
4155 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(Cst, ShTy)),
4156 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(NVTBits-Cst, ShTy)));
4161 Lo = DAG.getConstant(0, NVT);
4162 Hi = DAG.getConstant(0, NVT);
4163 } else if (Cst > NVTBits) {
4164 Lo = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst-NVTBits,ShTy));
4165 Hi = DAG.getConstant(0, NVT);
4166 } else if (Cst == NVTBits) {
4168 Hi = DAG.getConstant(0, NVT);
4170 Lo = DAG.getNode(ISD::OR, NVT,
4171 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4172 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4173 Hi = DAG.getNode(ISD::SRL, NVT, InH, DAG.getConstant(Cst, ShTy));
4178 Hi = Lo = DAG.getNode(ISD::SRA, NVT, InH,
4179 DAG.getConstant(NVTBits-1, ShTy));
4180 } else if (Cst > NVTBits) {
4181 Lo = DAG.getNode(ISD::SRA, NVT, InH,
4182 DAG.getConstant(Cst-NVTBits, ShTy));
4183 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4184 DAG.getConstant(NVTBits-1, ShTy));
4185 } else if (Cst == NVTBits) {
4187 Hi = DAG.getNode(ISD::SRA, NVT, InH,
4188 DAG.getConstant(NVTBits-1, ShTy));
4190 Lo = DAG.getNode(ISD::OR, NVT,
4191 DAG.getNode(ISD::SRL, NVT, InL, DAG.getConstant(Cst, ShTy)),
4192 DAG.getNode(ISD::SHL, NVT, InH, DAG.getConstant(NVTBits-Cst, ShTy)));
4193 Hi = DAG.getNode(ISD::SRA, NVT, InH, DAG.getConstant(Cst, ShTy));
4199 // Okay, the shift amount isn't constant. However, if we can tell that it is
4200 // >= 32 or < 32, we can still simplify it, without knowing the actual value.
4201 uint64_t Mask = NVTBits, KnownZero, KnownOne;
4202 DAG.ComputeMaskedBits(Amt, Mask, KnownZero, KnownOne);
4204 // If we know that the high bit of the shift amount is one, then we can do
4205 // this as a couple of simple shifts.
4206 if (KnownOne & Mask) {
4207 // Mask out the high bit, which we know is set.
4208 Amt = DAG.getNode(ISD::AND, Amt.getValueType(), Amt,
4209 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4211 // Expand the incoming operand to be shifted, so that we have its parts
4213 ExpandOp(Op, InL, InH);
4216 Lo = DAG.getConstant(0, NVT); // Low part is zero.
4217 Hi = DAG.getNode(ISD::SHL, NVT, InL, Amt); // High part from Lo part.
4220 Hi = DAG.getConstant(0, NVT); // Hi part is zero.
4221 Lo = DAG.getNode(ISD::SRL, NVT, InH, Amt); // Lo part from Hi part.
4224 Hi = DAG.getNode(ISD::SRA, NVT, InH, // Sign extend high part.
4225 DAG.getConstant(NVTBits-1, Amt.getValueType()));
4226 Lo = DAG.getNode(ISD::SRA, NVT, InH, Amt); // Lo part from Hi part.
4231 // If we know that the high bit of the shift amount is zero, then we can do
4232 // this as a couple of simple shifts.
4233 if (KnownZero & Mask) {
4235 SDOperand Amt2 = DAG.getNode(ISD::SUB, Amt.getValueType(),
4236 DAG.getConstant(NVTBits, Amt.getValueType()),
4239 // Expand the incoming operand to be shifted, so that we have its parts
4241 ExpandOp(Op, InL, InH);
4244 Lo = DAG.getNode(ISD::SHL, NVT, InL, Amt);
4245 Hi = DAG.getNode(ISD::OR, NVT,
4246 DAG.getNode(ISD::SHL, NVT, InH, Amt),
4247 DAG.getNode(ISD::SRL, NVT, InL, Amt2));
4250 Hi = DAG.getNode(ISD::SRL, NVT, InH, Amt);
4251 Lo = DAG.getNode(ISD::OR, NVT,
4252 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4253 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4256 Hi = DAG.getNode(ISD::SRA, NVT, InH, Amt);
4257 Lo = DAG.getNode(ISD::OR, NVT,
4258 DAG.getNode(ISD::SRL, NVT, InL, Amt),
4259 DAG.getNode(ISD::SHL, NVT, InH, Amt2));
4268 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
4269 // does not fit into a register, return the lo part and set the hi part to the
4270 // by-reg argument. If it does fit into a single register, return the result
4271 // and leave the Hi part unset.
4272 SDOperand SelectionDAGLegalize::ExpandLibCall(const char *Name, SDNode *Node,
4273 bool isSigned, SDOperand &Hi) {
4274 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
4275 // The input chain to this libcall is the entry node of the function.
4276 // Legalizing the call will automatically add the previous call to the
4278 SDOperand InChain = DAG.getEntryNode();
4280 TargetLowering::ArgListTy Args;
4281 TargetLowering::ArgListEntry Entry;
4282 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
4283 MVT::ValueType ArgVT = Node->getOperand(i).getValueType();
4284 const Type *ArgTy = MVT::getTypeForValueType(ArgVT);
4285 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
4286 Entry.isSExt = isSigned;
4287 Args.push_back(Entry);
4289 SDOperand Callee = DAG.getExternalSymbol(Name, TLI.getPointerTy());
4291 // Splice the libcall in wherever FindInputOutputChains tells us to.
4292 const Type *RetTy = MVT::getTypeForValueType(Node->getValueType(0));
4293 std::pair<SDOperand,SDOperand> CallInfo =
4294 TLI.LowerCallTo(InChain, RetTy, isSigned, false, CallingConv::C, false,
4297 // Legalize the call sequence, starting with the chain. This will advance
4298 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
4299 // was added by LowerCallTo (guaranteeing proper serialization of calls).
4300 LegalizeOp(CallInfo.second);
4302 switch (getTypeAction(CallInfo.first.getValueType())) {
4303 default: assert(0 && "Unknown thing");
4305 Result = CallInfo.first;
4308 ExpandOp(CallInfo.first, Result, Hi);
4315 /// ExpandIntToFP - Expand a [US]INT_TO_FP operation.
4317 SDOperand SelectionDAGLegalize::
4318 ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
4319 assert(getTypeAction(Source.getValueType()) == Expand &&
4320 "This is not an expansion!");
4321 assert(Source.getValueType() == MVT::i64 && "Only handle expand from i64!");
4324 assert(Source.getValueType() == MVT::i64 &&
4325 "This only works for 64-bit -> FP");
4326 // The 64-bit value loaded will be incorrectly if the 'sign bit' of the
4327 // incoming integer is set. To handle this, we dynamically test to see if
4328 // it is set, and, if so, add a fudge factor.
4330 ExpandOp(Source, Lo, Hi);
4332 // If this is unsigned, and not supported, first perform the conversion to
4333 // signed, then adjust the result if the sign bit is set.
4334 SDOperand SignedConv = ExpandIntToFP(true, DestTy,
4335 DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), Lo, Hi));
4337 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Hi,
4338 DAG.getConstant(0, Hi.getValueType()),
4340 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4341 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4342 SignSet, Four, Zero);
4343 uint64_t FF = 0x5f800000ULL;
4344 if (TLI.isLittleEndian()) FF <<= 32;
4345 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4347 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4348 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4349 SDOperand FudgeInReg;
4350 if (DestTy == MVT::f32)
4351 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4353 assert(DestTy == MVT::f64 && "Unexpected conversion");
4354 // FIXME: Avoid the extend by construction the right constantpool?
4355 FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
4356 CPIdx, NULL, 0, MVT::f32);
4358 MVT::ValueType SCVT = SignedConv.getValueType();
4359 if (SCVT != DestTy) {
4360 // Destination type needs to be expanded as well. The FADD now we are
4361 // constructing will be expanded into a libcall.
4362 if (MVT::getSizeInBits(SCVT) != MVT::getSizeInBits(DestTy)) {
4363 assert(SCVT == MVT::i32 && DestTy == MVT::f64);
4364 SignedConv = DAG.getNode(ISD::BUILD_PAIR, MVT::i64,
4365 SignedConv, SignedConv.getValue(1));
4367 SignedConv = DAG.getNode(ISD::BIT_CONVERT, DestTy, SignedConv);
4369 return DAG.getNode(ISD::FADD, DestTy, SignedConv, FudgeInReg);
4372 // Check to see if the target has a custom way to lower this. If so, use it.
4373 switch (TLI.getOperationAction(ISD::SINT_TO_FP, Source.getValueType())) {
4374 default: assert(0 && "This action not implemented for this operation!");
4375 case TargetLowering::Legal:
4376 case TargetLowering::Expand:
4377 break; // This case is handled below.
4378 case TargetLowering::Custom: {
4379 SDOperand NV = TLI.LowerOperation(DAG.getNode(ISD::SINT_TO_FP, DestTy,
4382 return LegalizeOp(NV);
4383 break; // The target decided this was legal after all
4387 // Expand the source, then glue it back together for the call. We must expand
4388 // the source in case it is shared (this pass of legalize must traverse it).
4389 SDOperand SrcLo, SrcHi;
4390 ExpandOp(Source, SrcLo, SrcHi);
4391 Source = DAG.getNode(ISD::BUILD_PAIR, Source.getValueType(), SrcLo, SrcHi);
4394 if (DestTy == MVT::f32)
4395 LC = RTLIB::SINTTOFP_I64_F32;
4397 assert(DestTy == MVT::f64 && "Unknown fp value type!");
4398 LC = RTLIB::SINTTOFP_I64_F64;
4401 assert(TLI.getLibcallName(LC) && "Don't know how to expand this SINT_TO_FP!");
4402 Source = DAG.getNode(ISD::SINT_TO_FP, DestTy, Source);
4403 SDOperand UnusedHiPart;
4404 return ExpandLibCall(TLI.getLibcallName(LC), Source.Val, isSigned,
4408 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
4409 /// INT_TO_FP operation of the specified operand when the target requests that
4410 /// we expand it. At this point, we know that the result and operand types are
4411 /// legal for the target.
4412 SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
4414 MVT::ValueType DestVT) {
4415 if (Op0.getValueType() == MVT::i32) {
4416 // simple 32-bit [signed|unsigned] integer to float/double expansion
4418 // get the stack frame index of a 8 byte buffer, pessimistically aligned
4419 MachineFunction &MF = DAG.getMachineFunction();
4420 const Type *F64Type = MVT::getTypeForValueType(MVT::f64);
4421 unsigned StackAlign =
4422 (unsigned)TLI.getTargetData()->getPrefTypeAlignment(F64Type);
4423 int SSFI = MF.getFrameInfo()->CreateStackObject(8, StackAlign);
4424 // get address of 8 byte buffer
4425 SDOperand StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy());
4426 // word offset constant for Hi/Lo address computation
4427 SDOperand WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
4428 // set up Hi and Lo (into buffer) address based on endian
4429 SDOperand Hi = StackSlot;
4430 SDOperand Lo = DAG.getNode(ISD::ADD, TLI.getPointerTy(), StackSlot,WordOff);
4431 if (TLI.isLittleEndian())
4434 // if signed map to unsigned space
4435 SDOperand Op0Mapped;
4437 // constant used to invert sign bit (signed to unsigned mapping)
4438 SDOperand SignBit = DAG.getConstant(0x80000000u, MVT::i32);
4439 Op0Mapped = DAG.getNode(ISD::XOR, MVT::i32, Op0, SignBit);
4443 // store the lo of the constructed double - based on integer input
4444 SDOperand Store1 = DAG.getStore(DAG.getEntryNode(),
4445 Op0Mapped, Lo, NULL, 0);
4446 // initial hi portion of constructed double
4447 SDOperand InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
4448 // store the hi of the constructed double - biased exponent
4449 SDOperand Store2=DAG.getStore(Store1, InitialHi, Hi, NULL, 0);
4450 // load the constructed double
4451 SDOperand Load = DAG.getLoad(MVT::f64, Store2, StackSlot, NULL, 0);
4452 // FP constant to bias correct the final result
4453 SDOperand Bias = DAG.getConstantFP(isSigned ?
4454 BitsToDouble(0x4330000080000000ULL)
4455 : BitsToDouble(0x4330000000000000ULL),
4457 // subtract the bias
4458 SDOperand Sub = DAG.getNode(ISD::FSUB, MVT::f64, Load, Bias);
4461 // handle final rounding
4462 if (DestVT == MVT::f64) {
4466 // if f32 then cast to f32
4467 Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub);
4471 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
4472 SDOperand Tmp1 = DAG.getNode(ISD::SINT_TO_FP, DestVT, Op0);
4474 SDOperand SignSet = DAG.getSetCC(TLI.getSetCCResultTy(), Op0,
4475 DAG.getConstant(0, Op0.getValueType()),
4477 SDOperand Zero = getIntPtrConstant(0), Four = getIntPtrConstant(4);
4478 SDOperand CstOffset = DAG.getNode(ISD::SELECT, Zero.getValueType(),
4479 SignSet, Four, Zero);
4481 // If the sign bit of the integer is set, the large number will be treated
4482 // as a negative number. To counteract this, the dynamic code adds an
4483 // offset depending on the data type.
4485 switch (Op0.getValueType()) {
4486 default: assert(0 && "Unsupported integer type!");
4487 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
4488 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
4489 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
4490 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
4492 if (TLI.isLittleEndian()) FF <<= 32;
4493 static Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
4495 SDOperand CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
4496 CPIdx = DAG.getNode(ISD::ADD, TLI.getPointerTy(), CPIdx, CstOffset);
4497 SDOperand FudgeInReg;
4498 if (DestVT == MVT::f32)
4499 FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
4501 assert(DestVT == MVT::f64 && "Unexpected conversion");
4502 FudgeInReg = LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
4503 DAG.getEntryNode(), CPIdx,
4504 NULL, 0, MVT::f32));
4507 return DAG.getNode(ISD::FADD, DestVT, Tmp1, FudgeInReg);
4510 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
4511 /// *INT_TO_FP operation of the specified operand when the target requests that
4512 /// we promote it. At this point, we know that the result and operand types are
4513 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
4514 /// operation that takes a larger input.
4515 SDOperand SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDOperand LegalOp,
4516 MVT::ValueType DestVT,
4518 // First step, figure out the appropriate *INT_TO_FP operation to use.
4519 MVT::ValueType NewInTy = LegalOp.getValueType();
4521 unsigned OpToUse = 0;
4523 // Scan for the appropriate larger type to use.
4525 NewInTy = (MVT::ValueType)(NewInTy+1);
4526 assert(MVT::isInteger(NewInTy) && "Ran out of possibilities!");
4528 // If the target supports SINT_TO_FP of this type, use it.
4529 switch (TLI.getOperationAction(ISD::SINT_TO_FP, NewInTy)) {
4531 case TargetLowering::Legal:
4532 if (!TLI.isTypeLegal(NewInTy))
4533 break; // Can't use this datatype.
4535 case TargetLowering::Custom:
4536 OpToUse = ISD::SINT_TO_FP;
4540 if (isSigned) continue;
4542 // If the target supports UINT_TO_FP of this type, use it.
4543 switch (TLI.getOperationAction(ISD::UINT_TO_FP, NewInTy)) {
4545 case TargetLowering::Legal:
4546 if (!TLI.isTypeLegal(NewInTy))
4547 break; // Can't use this datatype.
4549 case TargetLowering::Custom:
4550 OpToUse = ISD::UINT_TO_FP;
4555 // Otherwise, try a larger type.
4558 // Okay, we found the operation and type to use. Zero extend our input to the
4559 // desired type then run the operation on it.
4560 return DAG.getNode(OpToUse, DestVT,
4561 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
4565 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
4566 /// FP_TO_*INT operation of the specified operand when the target requests that
4567 /// we promote it. At this point, we know that the result and operand types are
4568 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
4569 /// operation that returns a larger result.
4570 SDOperand SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDOperand LegalOp,
4571 MVT::ValueType DestVT,
4573 // First step, figure out the appropriate FP_TO*INT operation to use.
4574 MVT::ValueType NewOutTy = DestVT;
4576 unsigned OpToUse = 0;
4578 // Scan for the appropriate larger type to use.
4580 NewOutTy = (MVT::ValueType)(NewOutTy+1);
4581 assert(MVT::isInteger(NewOutTy) && "Ran out of possibilities!");
4583 // If the target supports FP_TO_SINT returning this type, use it.
4584 switch (TLI.getOperationAction(ISD::FP_TO_SINT, NewOutTy)) {
4586 case TargetLowering::Legal:
4587 if (!TLI.isTypeLegal(NewOutTy))
4588 break; // Can't use this datatype.
4590 case TargetLowering::Custom:
4591 OpToUse = ISD::FP_TO_SINT;
4596 // If the target supports FP_TO_UINT of this type, use it.
4597 switch (TLI.getOperationAction(ISD::FP_TO_UINT, NewOutTy)) {
4599 case TargetLowering::Legal:
4600 if (!TLI.isTypeLegal(NewOutTy))
4601 break; // Can't use this datatype.
4603 case TargetLowering::Custom:
4604 OpToUse = ISD::FP_TO_UINT;
4609 // Otherwise, try a larger type.
4612 // Okay, we found the operation and type to use. Truncate the result of the
4613 // extended FP_TO_*INT operation to the desired size.
4614 return DAG.getNode(ISD::TRUNCATE, DestVT,
4615 DAG.getNode(OpToUse, NewOutTy, LegalOp));
4618 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
4620 SDOperand SelectionDAGLegalize::ExpandBSWAP(SDOperand Op) {
4621 MVT::ValueType VT = Op.getValueType();
4622 MVT::ValueType SHVT = TLI.getShiftAmountTy();
4623 SDOperand Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
4625 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
4627 Tmp2 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4628 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4629 return DAG.getNode(ISD::OR, VT, Tmp1, Tmp2);
4631 Tmp4 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4632 Tmp3 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4633 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4634 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4635 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
4636 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(0xFF00, VT));
4637 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4638 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4639 return DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4641 Tmp8 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(56, SHVT));
4642 Tmp7 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(40, SHVT));
4643 Tmp6 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(24, SHVT));
4644 Tmp5 = DAG.getNode(ISD::SHL, VT, Op, DAG.getConstant(8, SHVT));
4645 Tmp4 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(8, SHVT));
4646 Tmp3 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(24, SHVT));
4647 Tmp2 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(40, SHVT));
4648 Tmp1 = DAG.getNode(ISD::SRL, VT, Op, DAG.getConstant(56, SHVT));
4649 Tmp7 = DAG.getNode(ISD::AND, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
4650 Tmp6 = DAG.getNode(ISD::AND, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
4651 Tmp5 = DAG.getNode(ISD::AND, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
4652 Tmp4 = DAG.getNode(ISD::AND, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
4653 Tmp3 = DAG.getNode(ISD::AND, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
4654 Tmp2 = DAG.getNode(ISD::AND, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
4655 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp7);
4656 Tmp6 = DAG.getNode(ISD::OR, VT, Tmp6, Tmp5);
4657 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp3);
4658 Tmp2 = DAG.getNode(ISD::OR, VT, Tmp2, Tmp1);
4659 Tmp8 = DAG.getNode(ISD::OR, VT, Tmp8, Tmp6);
4660 Tmp4 = DAG.getNode(ISD::OR, VT, Tmp4, Tmp2);
4661 return DAG.getNode(ISD::OR, VT, Tmp8, Tmp4);
4665 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
4667 SDOperand SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDOperand Op) {
4669 default: assert(0 && "Cannot expand this yet!");
4671 static const uint64_t mask[6] = {
4672 0x5555555555555555ULL, 0x3333333333333333ULL,
4673 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
4674 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
4676 MVT::ValueType VT = Op.getValueType();
4677 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4678 unsigned len = MVT::getSizeInBits(VT);
4679 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4680 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
4681 SDOperand Tmp2 = DAG.getConstant(mask[i], VT);
4682 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4683 Op = DAG.getNode(ISD::ADD, VT, DAG.getNode(ISD::AND, VT, Op, Tmp2),
4684 DAG.getNode(ISD::AND, VT,
4685 DAG.getNode(ISD::SRL, VT, Op, Tmp3),Tmp2));
4690 // for now, we do this:
4691 // x = x | (x >> 1);
4692 // x = x | (x >> 2);
4694 // x = x | (x >>16);
4695 // x = x | (x >>32); // for 64-bit input
4696 // return popcount(~x);
4698 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
4699 MVT::ValueType VT = Op.getValueType();
4700 MVT::ValueType ShVT = TLI.getShiftAmountTy();
4701 unsigned len = MVT::getSizeInBits(VT);
4702 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
4703 SDOperand Tmp3 = DAG.getConstant(1ULL << i, ShVT);
4704 Op = DAG.getNode(ISD::OR, VT, Op, DAG.getNode(ISD::SRL, VT, Op, Tmp3));
4706 Op = DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(~0ULL, VT));
4707 return DAG.getNode(ISD::CTPOP, VT, Op);
4710 // for now, we use: { return popcount(~x & (x - 1)); }
4711 // unless the target has ctlz but not ctpop, in which case we use:
4712 // { return 32 - nlz(~x & (x-1)); }
4713 // see also http://www.hackersdelight.org/HDcode/ntz.cc
4714 MVT::ValueType VT = Op.getValueType();
4715 SDOperand Tmp2 = DAG.getConstant(~0ULL, VT);
4716 SDOperand Tmp3 = DAG.getNode(ISD::AND, VT,
4717 DAG.getNode(ISD::XOR, VT, Op, Tmp2),
4718 DAG.getNode(ISD::SUB, VT, Op, DAG.getConstant(1, VT)));
4719 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
4720 if (!TLI.isOperationLegal(ISD::CTPOP, VT) &&
4721 TLI.isOperationLegal(ISD::CTLZ, VT))
4722 return DAG.getNode(ISD::SUB, VT,
4723 DAG.getConstant(MVT::getSizeInBits(VT), VT),
4724 DAG.getNode(ISD::CTLZ, VT, Tmp3));
4725 return DAG.getNode(ISD::CTPOP, VT, Tmp3);
4730 /// ExpandOp - Expand the specified SDOperand into its two component pieces
4731 /// Lo&Hi. Note that the Op MUST be an expanded type. As a result of this, the
4732 /// LegalizeNodes map is filled in for any results that are not expanded, the
4733 /// ExpandedNodes map is filled in for any results that are expanded, and the
4734 /// Lo/Hi values are returned.
4735 void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
4736 MVT::ValueType VT = Op.getValueType();
4737 MVT::ValueType NVT = TLI.getTypeToTransformTo(VT);
4738 SDNode *Node = Op.Val;
4739 assert(getTypeAction(VT) == Expand && "Not an expanded type!");
4740 assert(((MVT::isInteger(NVT) && NVT < VT) || MVT::isFloatingPoint(VT) ||
4741 MVT::isVector(VT)) &&
4742 "Cannot expand to FP value or to larger int value!");
4744 // See if we already expanded it.
4745 DenseMap<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
4746 = ExpandedNodes.find(Op);
4747 if (I != ExpandedNodes.end()) {
4748 Lo = I->second.first;
4749 Hi = I->second.second;
4753 switch (Node->getOpcode()) {
4754 case ISD::CopyFromReg:
4755 assert(0 && "CopyFromReg must be legal!");
4758 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
4760 assert(0 && "Do not know how to expand this operator!");
4763 NVT = TLI.getTypeToExpandTo(VT);
4764 Lo = DAG.getNode(ISD::UNDEF, NVT);
4765 Hi = DAG.getNode(ISD::UNDEF, NVT);
4767 case ISD::Constant: {
4768 uint64_t Cst = cast<ConstantSDNode>(Node)->getValue();
4769 Lo = DAG.getConstant(Cst, NVT);
4770 Hi = DAG.getConstant(Cst >> MVT::getSizeInBits(NVT), NVT);
4773 case ISD::ConstantFP: {
4774 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
4775 Lo = ExpandConstantFP(CFP, false, DAG, TLI);
4776 if (getTypeAction(Lo.getValueType()) == Expand)
4777 ExpandOp(Lo, Lo, Hi);
4780 case ISD::BUILD_PAIR:
4781 // Return the operands.
4782 Lo = Node->getOperand(0);
4783 Hi = Node->getOperand(1);
4786 case ISD::SIGN_EXTEND_INREG:
4787 ExpandOp(Node->getOperand(0), Lo, Hi);
4788 // sext_inreg the low part if needed.
4789 Lo = DAG.getNode(ISD::SIGN_EXTEND_INREG, NVT, Lo, Node->getOperand(1));
4791 // The high part gets the sign extension from the lo-part. This handles
4792 // things like sextinreg V:i64 from i8.
4793 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4794 DAG.getConstant(MVT::getSizeInBits(NVT)-1,
4795 TLI.getShiftAmountTy()));
4799 ExpandOp(Node->getOperand(0), Lo, Hi);
4800 SDOperand TempLo = DAG.getNode(ISD::BSWAP, NVT, Hi);
4801 Hi = DAG.getNode(ISD::BSWAP, NVT, Lo);
4807 ExpandOp(Node->getOperand(0), Lo, Hi);
4808 Lo = DAG.getNode(ISD::ADD, NVT, // ctpop(HL) -> ctpop(H)+ctpop(L)
4809 DAG.getNode(ISD::CTPOP, NVT, Lo),
4810 DAG.getNode(ISD::CTPOP, NVT, Hi));
4811 Hi = DAG.getConstant(0, NVT);
4815 // ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
4816 ExpandOp(Node->getOperand(0), Lo, Hi);
4817 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4818 SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
4819 SDOperand TopNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), HLZ, BitsC,
4821 SDOperand LowPart = DAG.getNode(ISD::CTLZ, NVT, Lo);
4822 LowPart = DAG.getNode(ISD::ADD, NVT, LowPart, BitsC);
4824 Lo = DAG.getNode(ISD::SELECT, NVT, TopNotZero, HLZ, LowPart);
4825 Hi = DAG.getConstant(0, NVT);
4830 // cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
4831 ExpandOp(Node->getOperand(0), Lo, Hi);
4832 SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
4833 SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
4834 SDOperand BotNotZero = DAG.getSetCC(TLI.getSetCCResultTy(), LTZ, BitsC,
4836 SDOperand HiPart = DAG.getNode(ISD::CTTZ, NVT, Hi);
4837 HiPart = DAG.getNode(ISD::ADD, NVT, HiPart, BitsC);
4839 Lo = DAG.getNode(ISD::SELECT, NVT, BotNotZero, LTZ, HiPart);
4840 Hi = DAG.getConstant(0, NVT);
4845 SDOperand Ch = Node->getOperand(0); // Legalize the chain.
4846 SDOperand Ptr = Node->getOperand(1); // Legalize the pointer.
4847 Lo = DAG.getVAArg(NVT, Ch, Ptr, Node->getOperand(2));
4848 Hi = DAG.getVAArg(NVT, Lo.getValue(1), Ptr, Node->getOperand(2));
4850 // Remember that we legalized the chain.
4851 Hi = LegalizeOp(Hi);
4852 AddLegalizedOperand(Op.getValue(1), Hi.getValue(1));
4853 if (!TLI.isLittleEndian())
4859 LoadSDNode *LD = cast<LoadSDNode>(Node);
4860 SDOperand Ch = LD->getChain(); // Legalize the chain.
4861 SDOperand Ptr = LD->getBasePtr(); // Legalize the pointer.
4862 ISD::LoadExtType ExtType = LD->getExtensionType();
4863 int SVOffset = LD->getSrcValueOffset();
4864 unsigned Alignment = LD->getAlignment();
4865 bool isVolatile = LD->isVolatile();
4867 if (ExtType == ISD::NON_EXTLOAD) {
4868 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
4869 isVolatile, Alignment);
4870 if (VT == MVT::f32 || VT == MVT::f64) {
4871 // f32->i32 or f64->i64 one to one expansion.
4872 // Remember that we legalized the chain.
4873 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4874 // Recursively expand the new load.
4875 if (getTypeAction(NVT) == Expand)
4876 ExpandOp(Lo, Lo, Hi);
4880 // Increment the pointer to the other half.
4881 unsigned IncrementSize = MVT::getSizeInBits(Lo.getValueType())/8;
4882 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
4883 getIntPtrConstant(IncrementSize));
4884 SVOffset += IncrementSize;
4885 if (Alignment > IncrementSize)
4886 Alignment = IncrementSize;
4887 Hi = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), SVOffset,
4888 isVolatile, Alignment);
4890 // Build a factor node to remember that this load is independent of the
4892 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
4895 // Remember that we legalized the chain.
4896 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
4897 if (!TLI.isLittleEndian())
4900 MVT::ValueType EVT = LD->getLoadedVT();
4902 if (VT == MVT::f64 && EVT == MVT::f32) {
4903 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
4904 SDOperand Load = DAG.getLoad(EVT, Ch, Ptr, LD->getSrcValue(),
4905 SVOffset, isVolatile, Alignment);
4906 // Remember that we legalized the chain.
4907 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Load.getValue(1)));
4908 ExpandOp(DAG.getNode(ISD::FP_EXTEND, VT, Load), Lo, Hi);
4913 Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),
4914 SVOffset, isVolatile, Alignment);
4916 Lo = DAG.getExtLoad(ExtType, NVT, Ch, Ptr, LD->getSrcValue(),
4917 SVOffset, EVT, isVolatile,
4920 // Remember that we legalized the chain.
4921 AddLegalizedOperand(SDOperand(Node, 1), LegalizeOp(Lo.getValue(1)));
4923 if (ExtType == ISD::SEXTLOAD) {
4924 // The high part is obtained by SRA'ing all but one of the bits of the
4926 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4927 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4928 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4929 } else if (ExtType == ISD::ZEXTLOAD) {
4930 // The high part is just a zero.
4931 Hi = DAG.getConstant(0, NVT);
4932 } else /* if (ExtType == ISD::EXTLOAD) */ {
4933 // The high part is undefined.
4934 Hi = DAG.getNode(ISD::UNDEF, NVT);
4941 case ISD::XOR: { // Simple logical operators -> two trivial pieces.
4942 SDOperand LL, LH, RL, RH;
4943 ExpandOp(Node->getOperand(0), LL, LH);
4944 ExpandOp(Node->getOperand(1), RL, RH);
4945 Lo = DAG.getNode(Node->getOpcode(), NVT, LL, RL);
4946 Hi = DAG.getNode(Node->getOpcode(), NVT, LH, RH);
4950 SDOperand LL, LH, RL, RH;
4951 ExpandOp(Node->getOperand(1), LL, LH);
4952 ExpandOp(Node->getOperand(2), RL, RH);
4953 if (getTypeAction(NVT) == Expand)
4954 NVT = TLI.getTypeToExpandTo(NVT);
4955 Lo = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LL, RL);
4957 Hi = DAG.getNode(ISD::SELECT, NVT, Node->getOperand(0), LH, RH);
4960 case ISD::SELECT_CC: {
4961 SDOperand TL, TH, FL, FH;
4962 ExpandOp(Node->getOperand(2), TL, TH);
4963 ExpandOp(Node->getOperand(3), FL, FH);
4964 if (getTypeAction(NVT) == Expand)
4965 NVT = TLI.getTypeToExpandTo(NVT);
4966 Lo = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4967 Node->getOperand(1), TL, FL, Node->getOperand(4));
4969 Hi = DAG.getNode(ISD::SELECT_CC, NVT, Node->getOperand(0),
4970 Node->getOperand(1), TH, FH, Node->getOperand(4));
4973 case ISD::ANY_EXTEND:
4974 // The low part is any extension of the input (which degenerates to a copy).
4975 Lo = DAG.getNode(ISD::ANY_EXTEND, NVT, Node->getOperand(0));
4976 // The high part is undefined.
4977 Hi = DAG.getNode(ISD::UNDEF, NVT);
4979 case ISD::SIGN_EXTEND: {
4980 // The low part is just a sign extension of the input (which degenerates to
4982 Lo = DAG.getNode(ISD::SIGN_EXTEND, NVT, Node->getOperand(0));
4984 // The high part is obtained by SRA'ing all but one of the bits of the lo
4986 unsigned LoSize = MVT::getSizeInBits(Lo.getValueType());
4987 Hi = DAG.getNode(ISD::SRA, NVT, Lo,
4988 DAG.getConstant(LoSize-1, TLI.getShiftAmountTy()));
4991 case ISD::ZERO_EXTEND:
4992 // The low part is just a zero extension of the input (which degenerates to
4994 Lo = DAG.getNode(ISD::ZERO_EXTEND, NVT, Node->getOperand(0));
4996 // The high part is just a zero.
4997 Hi = DAG.getConstant(0, NVT);
5000 case ISD::TRUNCATE: {
5001 // The input value must be larger than this value. Expand *it*.
5003 ExpandOp(Node->getOperand(0), NewLo, Hi);
5005 // The low part is now either the right size, or it is closer. If not the
5006 // right size, make an illegal truncate so we recursively expand it.
5007 if (NewLo.getValueType() != Node->getValueType(0))
5008 NewLo = DAG.getNode(ISD::TRUNCATE, Node->getValueType(0), NewLo);
5009 ExpandOp(NewLo, Lo, Hi);
5013 case ISD::BIT_CONVERT: {
5015 if (TLI.getOperationAction(ISD::BIT_CONVERT, VT) == TargetLowering::Custom){
5016 // If the target wants to, allow it to lower this itself.
5017 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5018 case Expand: assert(0 && "cannot expand FP!");
5019 case Legal: Tmp = LegalizeOp(Node->getOperand(0)); break;
5020 case Promote: Tmp = PromoteOp (Node->getOperand(0)); break;
5022 Tmp = TLI.LowerOperation(DAG.getNode(ISD::BIT_CONVERT, VT, Tmp), DAG);
5025 // f32 / f64 must be expanded to i32 / i64.
5026 if (VT == MVT::f32 || VT == MVT::f64) {
5027 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5028 if (getTypeAction(NVT) == Expand)
5029 ExpandOp(Lo, Lo, Hi);
5033 // If source operand will be expanded to the same type as VT, i.e.
5034 // i64 <- f64, i32 <- f32, expand the source operand instead.
5035 MVT::ValueType VT0 = Node->getOperand(0).getValueType();
5036 if (getTypeAction(VT0) == Expand && TLI.getTypeToTransformTo(VT0) == VT) {
5037 ExpandOp(Node->getOperand(0), Lo, Hi);
5041 // Turn this into a load/store pair by default.
5043 Tmp = ExpandBIT_CONVERT(VT, Node->getOperand(0));
5045 ExpandOp(Tmp, Lo, Hi);
5049 case ISD::READCYCLECOUNTER:
5050 assert(TLI.getOperationAction(ISD::READCYCLECOUNTER, VT) ==
5051 TargetLowering::Custom &&
5052 "Must custom expand ReadCycleCounter");
5053 Lo = TLI.LowerOperation(Op, DAG);
5054 assert(Lo.Val && "Node must be custom expanded!");
5055 Hi = Lo.getValue(1);
5056 AddLegalizedOperand(SDOperand(Node, 1), // Remember we legalized the chain.
5057 LegalizeOp(Lo.getValue(2)));
5060 // These operators cannot be expanded directly, emit them as calls to
5061 // library functions.
5062 case ISD::FP_TO_SINT: {
5063 if (TLI.getOperationAction(ISD::FP_TO_SINT, VT) == TargetLowering::Custom) {
5065 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5066 case Expand: assert(0 && "cannot expand FP!");
5067 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5068 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5071 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_SINT, VT, Op), DAG);
5073 // Now that the custom expander is done, expand the result, which is still
5076 ExpandOp(Op, Lo, Hi);
5082 if (Node->getOperand(0).getValueType() == MVT::f32)
5083 LC = RTLIB::FPTOSINT_F32_I64;
5085 LC = RTLIB::FPTOSINT_F64_I64;
5086 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5087 false/*sign irrelevant*/, Hi);
5091 case ISD::FP_TO_UINT: {
5092 if (TLI.getOperationAction(ISD::FP_TO_UINT, VT) == TargetLowering::Custom) {
5094 switch (getTypeAction(Node->getOperand(0).getValueType())) {
5095 case Expand: assert(0 && "cannot expand FP!");
5096 case Legal: Op = LegalizeOp(Node->getOperand(0)); break;
5097 case Promote: Op = PromoteOp (Node->getOperand(0)); break;
5100 Op = TLI.LowerOperation(DAG.getNode(ISD::FP_TO_UINT, VT, Op), DAG);
5102 // Now that the custom expander is done, expand the result.
5104 ExpandOp(Op, Lo, Hi);
5110 if (Node->getOperand(0).getValueType() == MVT::f32)
5111 LC = RTLIB::FPTOUINT_F32_I64;
5113 LC = RTLIB::FPTOUINT_F64_I64;
5114 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node,
5115 false/*sign irrelevant*/, Hi);
5120 // If the target wants custom lowering, do so.
5121 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5122 if (TLI.getOperationAction(ISD::SHL, VT) == TargetLowering::Custom) {
5123 SDOperand Op = DAG.getNode(ISD::SHL, VT, Node->getOperand(0), ShiftAmt);
5124 Op = TLI.LowerOperation(Op, DAG);
5126 // Now that the custom expander is done, expand the result, which is
5128 ExpandOp(Op, Lo, Hi);
5133 // If ADDC/ADDE are supported and if the shift amount is a constant 1, emit
5134 // this X << 1 as X+X.
5135 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(ShiftAmt)) {
5136 if (ShAmt->getValue() == 1 && TLI.isOperationLegal(ISD::ADDC, NVT) &&
5137 TLI.isOperationLegal(ISD::ADDE, NVT)) {
5138 SDOperand LoOps[2], HiOps[3];
5139 ExpandOp(Node->getOperand(0), LoOps[0], HiOps[0]);
5140 SDVTList VTList = DAG.getVTList(LoOps[0].getValueType(), MVT::Flag);
5141 LoOps[1] = LoOps[0];
5142 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5144 HiOps[1] = HiOps[0];
5145 HiOps[2] = Lo.getValue(1);
5146 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5151 // If we can emit an efficient shift operation, do so now.
5152 if (ExpandShift(ISD::SHL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5155 // If this target supports SHL_PARTS, use it.
5156 TargetLowering::LegalizeAction Action =
5157 TLI.getOperationAction(ISD::SHL_PARTS, NVT);
5158 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5159 Action == TargetLowering::Custom) {
5160 ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5164 // Otherwise, emit a libcall.
5165 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SHL_I64), Node,
5166 false/*left shift=unsigned*/, Hi);
5171 // If the target wants custom lowering, do so.
5172 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5173 if (TLI.getOperationAction(ISD::SRA, VT) == TargetLowering::Custom) {
5174 SDOperand Op = DAG.getNode(ISD::SRA, VT, Node->getOperand(0), ShiftAmt);
5175 Op = TLI.LowerOperation(Op, DAG);
5177 // Now that the custom expander is done, expand the result, which is
5179 ExpandOp(Op, Lo, Hi);
5184 // If we can emit an efficient shift operation, do so now.
5185 if (ExpandShift(ISD::SRA, Node->getOperand(0), ShiftAmt, Lo, Hi))
5188 // If this target supports SRA_PARTS, use it.
5189 TargetLowering::LegalizeAction Action =
5190 TLI.getOperationAction(ISD::SRA_PARTS, NVT);
5191 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5192 Action == TargetLowering::Custom) {
5193 ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5197 // Otherwise, emit a libcall.
5198 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRA_I64), Node,
5199 true/*ashr is signed*/, Hi);
5204 // If the target wants custom lowering, do so.
5205 SDOperand ShiftAmt = LegalizeOp(Node->getOperand(1));
5206 if (TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Custom) {
5207 SDOperand Op = DAG.getNode(ISD::SRL, VT, Node->getOperand(0), ShiftAmt);
5208 Op = TLI.LowerOperation(Op, DAG);
5210 // Now that the custom expander is done, expand the result, which is
5212 ExpandOp(Op, Lo, Hi);
5217 // If we can emit an efficient shift operation, do so now.
5218 if (ExpandShift(ISD::SRL, Node->getOperand(0), ShiftAmt, Lo, Hi))
5221 // If this target supports SRL_PARTS, use it.
5222 TargetLowering::LegalizeAction Action =
5223 TLI.getOperationAction(ISD::SRL_PARTS, NVT);
5224 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
5225 Action == TargetLowering::Custom) {
5226 ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), ShiftAmt, Lo, Hi);
5230 // Otherwise, emit a libcall.
5231 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SRL_I64), Node,
5232 false/*lshr is unsigned*/, Hi);
5238 // If the target wants to custom expand this, let them.
5239 if (TLI.getOperationAction(Node->getOpcode(), VT) ==
5240 TargetLowering::Custom) {
5241 Op = TLI.LowerOperation(Op, DAG);
5243 ExpandOp(Op, Lo, Hi);
5248 // Expand the subcomponents.
5249 SDOperand LHSL, LHSH, RHSL, RHSH;
5250 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5251 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5252 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5253 SDOperand LoOps[2], HiOps[3];
5258 if (Node->getOpcode() == ISD::ADD) {
5259 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5260 HiOps[2] = Lo.getValue(1);
5261 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5263 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5264 HiOps[2] = Lo.getValue(1);
5265 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5272 // Expand the subcomponents.
5273 SDOperand LHSL, LHSH, RHSL, RHSH;
5274 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5275 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5276 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5277 SDOperand LoOps[2] = { LHSL, RHSL };
5278 SDOperand HiOps[3] = { LHSH, RHSH };
5280 if (Node->getOpcode() == ISD::ADDC) {
5281 Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
5282 HiOps[2] = Lo.getValue(1);
5283 Hi = DAG.getNode(ISD::ADDE, VTList, HiOps, 3);
5285 Lo = DAG.getNode(ISD::SUBC, VTList, LoOps, 2);
5286 HiOps[2] = Lo.getValue(1);
5287 Hi = DAG.getNode(ISD::SUBE, VTList, HiOps, 3);
5289 // Remember that we legalized the flag.
5290 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5295 // Expand the subcomponents.
5296 SDOperand LHSL, LHSH, RHSL, RHSH;
5297 ExpandOp(Node->getOperand(0), LHSL, LHSH);
5298 ExpandOp(Node->getOperand(1), RHSL, RHSH);
5299 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
5300 SDOperand LoOps[3] = { LHSL, RHSL, Node->getOperand(2) };
5301 SDOperand HiOps[3] = { LHSH, RHSH };
5303 Lo = DAG.getNode(Node->getOpcode(), VTList, LoOps, 3);
5304 HiOps[2] = Lo.getValue(1);
5305 Hi = DAG.getNode(Node->getOpcode(), VTList, HiOps, 3);
5307 // Remember that we legalized the flag.
5308 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Hi.getValue(1)));
5312 // If the target wants to custom expand this, let them.
5313 if (TLI.getOperationAction(ISD::MUL, VT) == TargetLowering::Custom) {
5314 SDOperand New = TLI.LowerOperation(Op, DAG);
5316 ExpandOp(New, Lo, Hi);
5321 bool HasMULHS = TLI.isOperationLegal(ISD::MULHS, NVT);
5322 bool HasMULHU = TLI.isOperationLegal(ISD::MULHU, NVT);
5323 if (HasMULHS || HasMULHU) {
5324 SDOperand LL, LH, RL, RH;
5325 ExpandOp(Node->getOperand(0), LL, LH);
5326 ExpandOp(Node->getOperand(1), RL, RH);
5327 unsigned SH = MVT::getSizeInBits(RH.getValueType())-1;
5328 // FIXME: Move this to the dag combiner.
5329 // MULHS implicitly sign extends its inputs. Check to see if ExpandOp
5330 // extended the sign bit of the low half through the upper half, and if so
5331 // emit a MULHS instead of the alternate sequence that is valid for any
5332 // i64 x i64 multiply.
5334 // is RH an extension of the sign bit of RL?
5335 RH.getOpcode() == ISD::SRA && RH.getOperand(0) == RL &&
5336 RH.getOperand(1).getOpcode() == ISD::Constant &&
5337 cast<ConstantSDNode>(RH.getOperand(1))->getValue() == SH &&
5338 // is LH an extension of the sign bit of LL?
5339 LH.getOpcode() == ISD::SRA && LH.getOperand(0) == LL &&
5340 LH.getOperand(1).getOpcode() == ISD::Constant &&
5341 cast<ConstantSDNode>(LH.getOperand(1))->getValue() == SH) {
5343 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5345 Hi = DAG.getNode(ISD::MULHS, NVT, LL, RL);
5347 } else if (HasMULHU) {
5349 Lo = DAG.getNode(ISD::MUL, NVT, LL, RL);
5352 Hi = DAG.getNode(ISD::MULHU, NVT, LL, RL);
5353 RH = DAG.getNode(ISD::MUL, NVT, LL, RH);
5354 LH = DAG.getNode(ISD::MUL, NVT, LH, RL);
5355 Hi = DAG.getNode(ISD::ADD, NVT, Hi, RH);
5356 Hi = DAG.getNode(ISD::ADD, NVT, Hi, LH);
5361 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::MUL_I64), Node,
5362 false/*sign irrelevant*/, Hi);
5366 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SDIV_I64), Node, true, Hi);
5369 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UDIV_I64), Node, true, Hi);
5372 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::SREM_I64), Node, true, Hi);
5375 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::UREM_I64), Node, true, Hi);
5379 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5380 ? RTLIB::ADD_F32 : RTLIB::ADD_F64),
5384 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5385 ? RTLIB::SUB_F32 : RTLIB::SUB_F64),
5389 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5390 ? RTLIB::MUL_F32 : RTLIB::MUL_F64),
5394 Lo = ExpandLibCall(TLI.getLibcallName((VT == MVT::f32)
5395 ? RTLIB::DIV_F32 : RTLIB::DIV_F64),
5398 case ISD::FP_EXTEND:
5399 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPEXT_F32_F64), Node, true,Hi);
5402 Lo = ExpandLibCall(TLI.getLibcallName(RTLIB::FPROUND_F64_F32),Node,true,Hi);
5407 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
5408 switch(Node->getOpcode()) {
5410 LC = (VT == MVT::f32) ? RTLIB::SQRT_F32 : RTLIB::SQRT_F64;
5413 LC = (VT == MVT::f32) ? RTLIB::SIN_F32 : RTLIB::SIN_F64;
5416 LC = (VT == MVT::f32) ? RTLIB::COS_F32 : RTLIB::COS_F64;
5418 default: assert(0 && "Unreachable!");
5420 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, false, Hi);
5424 SDOperand Mask = (VT == MVT::f64)
5425 ? DAG.getConstantFP(BitsToDouble(~(1ULL << 63)), VT)
5426 : DAG.getConstantFP(BitsToFloat(~(1U << 31)), VT);
5427 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5428 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5429 Lo = DAG.getNode(ISD::AND, NVT, Lo, Mask);
5430 if (getTypeAction(NVT) == Expand)
5431 ExpandOp(Lo, Lo, Hi);
5435 SDOperand Mask = (VT == MVT::f64)
5436 ? DAG.getConstantFP(BitsToDouble(1ULL << 63), VT)
5437 : DAG.getConstantFP(BitsToFloat(1U << 31), VT);
5438 Mask = DAG.getNode(ISD::BIT_CONVERT, NVT, Mask);
5439 Lo = DAG.getNode(ISD::BIT_CONVERT, NVT, Node->getOperand(0));
5440 Lo = DAG.getNode(ISD::XOR, NVT, Lo, Mask);
5441 if (getTypeAction(NVT) == Expand)
5442 ExpandOp(Lo, Lo, Hi);
5445 case ISD::FCOPYSIGN: {
5446 Lo = ExpandFCOPYSIGNToBitwiseOps(Node, NVT, DAG, TLI);
5447 if (getTypeAction(NVT) == Expand)
5448 ExpandOp(Lo, Lo, Hi);
5451 case ISD::SINT_TO_FP:
5452 case ISD::UINT_TO_FP: {
5453 bool isSigned = Node->getOpcode() == ISD::SINT_TO_FP;
5454 MVT::ValueType SrcVT = Node->getOperand(0).getValueType();
5456 if (Node->getOperand(0).getValueType() == MVT::i64) {
5458 LC = isSigned ? RTLIB::SINTTOFP_I64_F32 : RTLIB::UINTTOFP_I64_F32;
5460 LC = isSigned ? RTLIB::SINTTOFP_I64_F64 : RTLIB::UINTTOFP_I64_F64;
5463 LC = isSigned ? RTLIB::SINTTOFP_I32_F32 : RTLIB::UINTTOFP_I32_F32;
5465 LC = isSigned ? RTLIB::SINTTOFP_I32_F64 : RTLIB::UINTTOFP_I32_F64;
5468 // Promote the operand if needed.
5469 if (getTypeAction(SrcVT) == Promote) {
5470 SDOperand Tmp = PromoteOp(Node->getOperand(0));
5472 ? DAG.getNode(ISD::SIGN_EXTEND_INREG, Tmp.getValueType(), Tmp,
5473 DAG.getValueType(SrcVT))
5474 : DAG.getZeroExtendInReg(Tmp, SrcVT);
5475 Node = DAG.UpdateNodeOperands(Op, Tmp).Val;
5478 const char *LibCall = TLI.getLibcallName(LC);
5480 Lo = ExpandLibCall(TLI.getLibcallName(LC), Node, isSigned, Hi);
5482 Lo = ExpandIntToFP(Node->getOpcode() == ISD::SINT_TO_FP, VT,
5483 Node->getOperand(0));
5484 if (getTypeAction(Lo.getValueType()) == Expand)
5485 ExpandOp(Lo, Lo, Hi);
5491 // Make sure the resultant values have been legalized themselves, unless this
5492 // is a type that requires multi-step expansion.
5493 if (getTypeAction(NVT) != Expand && NVT != MVT::isVoid) {
5494 Lo = LegalizeOp(Lo);
5496 // Don't legalize the high part if it is expanded to a single node.
5497 Hi = LegalizeOp(Hi);
5500 // Remember in a map if the values will be reused later.
5501 bool isNew = ExpandedNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi)));
5502 assert(isNew && "Value already expanded?!?");
5505 /// SplitVectorOp - Given an operand of vector type, break it down into
5506 /// two smaller values, still of vector type.
5507 void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
5509 assert(MVT::isVector(Op.getValueType()) && "Cannot split non-vector type!");
5510 SDNode *Node = Op.Val;
5511 unsigned NumElements = MVT::getVectorNumElements(Node->getValueType(0));
5512 assert(NumElements > 1 && "Cannot split a single element vector!");
5513 unsigned NewNumElts = NumElements/2;
5514 MVT::ValueType NewEltVT = MVT::getVectorElementType(Node->getValueType(0));
5515 MVT::ValueType NewVT = MVT::getVectorType(NewEltVT, NewNumElts);
5517 // See if we already split it.
5518 std::map<SDOperand, std::pair<SDOperand, SDOperand> >::iterator I
5519 = SplitNodes.find(Op);
5520 if (I != SplitNodes.end()) {
5521 Lo = I->second.first;
5522 Hi = I->second.second;
5526 switch (Node->getOpcode()) {
5531 assert(0 && "Unhandled operation in SplitVectorOp!");
5532 case ISD::BUILD_PAIR:
5533 Lo = Node->getOperand(0);
5534 Hi = Node->getOperand(1);
5536 case ISD::BUILD_VECTOR: {
5537 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5538 Node->op_begin()+NewNumElts);
5539 Lo = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &LoOps[0], LoOps.size());
5541 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumElts,
5543 Hi = DAG.getNode(ISD::BUILD_VECTOR, NewVT, &HiOps[0], HiOps.size());
5546 case ISD::CONCAT_VECTORS: {
5547 unsigned NewNumSubvectors = Node->getNumOperands() / 2;
5548 if (NewNumSubvectors == 1) {
5549 Lo = Node->getOperand(0);
5550 Hi = Node->getOperand(1);
5552 SmallVector<SDOperand, 8> LoOps(Node->op_begin(),
5553 Node->op_begin()+NewNumSubvectors);
5554 Lo = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &LoOps[0], LoOps.size());
5556 SmallVector<SDOperand, 8> HiOps(Node->op_begin()+NewNumSubvectors,
5558 Hi = DAG.getNode(ISD::CONCAT_VECTORS, NewVT, &HiOps[0], HiOps.size());
5574 SDOperand LL, LH, RL, RH;
5575 SplitVectorOp(Node->getOperand(0), LL, LH);
5576 SplitVectorOp(Node->getOperand(1), RL, RH);
5578 Lo = DAG.getNode(Node->getOpcode(), NewVT, LL, RL);
5579 Hi = DAG.getNode(Node->getOpcode(), NewVT, LH, RH);
5583 LoadSDNode *LD = cast<LoadSDNode>(Node);
5584 SDOperand Ch = LD->getChain();
5585 SDOperand Ptr = LD->getBasePtr();
5586 const Value *SV = LD->getSrcValue();
5587 int SVOffset = LD->getSrcValueOffset();
5588 unsigned Alignment = LD->getAlignment();
5589 bool isVolatile = LD->isVolatile();
5591 Lo = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5592 unsigned IncrementSize = NewNumElts * MVT::getSizeInBits(NewEltVT)/8;
5593 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
5594 getIntPtrConstant(IncrementSize));
5595 SVOffset += IncrementSize;
5596 if (Alignment > IncrementSize)
5597 Alignment = IncrementSize;
5598 Hi = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset, isVolatile, Alignment);
5600 // Build a factor node to remember that this load is independent of the
5602 SDOperand TF = DAG.getNode(ISD::TokenFactor, MVT::Other, Lo.getValue(1),
5605 // Remember that we legalized the chain.
5606 AddLegalizedOperand(Op.getValue(1), LegalizeOp(TF));
5609 case ISD::BIT_CONVERT: {
5610 // We know the result is a vector. The input may be either a vector or a
5612 SDOperand InOp = Node->getOperand(0);
5613 if (!MVT::isVector(InOp.getValueType()) ||
5614 MVT::getVectorNumElements(InOp.getValueType()) == 1) {
5615 // The input is a scalar or single-element vector.
5616 // Lower to a store/load so that it can be split.
5617 // FIXME: this could be improved probably.
5618 SDOperand Ptr = CreateStackTemporary(InOp.getValueType());
5620 SDOperand St = DAG.getStore(DAG.getEntryNode(),
5621 InOp, Ptr, NULL, 0);
5622 InOp = DAG.getLoad(Op.getValueType(), St, Ptr, NULL, 0);
5624 // Split the vector and convert each of the pieces now.
5625 SplitVectorOp(InOp, Lo, Hi);
5626 Lo = DAG.getNode(ISD::BIT_CONVERT, NewVT, Lo);
5627 Hi = DAG.getNode(ISD::BIT_CONVERT, NewVT, Hi);
5632 // Remember in a map if the values will be reused later.
5634 SplitNodes.insert(std::make_pair(Op, std::make_pair(Lo, Hi))).second;
5635 assert(isNew && "Value already split?!?");
5639 /// ScalarizeVectorOp - Given an operand of single-element vector type
5640 /// (e.g. v1f32), convert it into the equivalent operation that returns a
5641 /// scalar (e.g. f32) value.
5642 SDOperand SelectionDAGLegalize::ScalarizeVectorOp(SDOperand Op) {
5643 assert(MVT::isVector(Op.getValueType()) &&
5644 "Bad ScalarizeVectorOp invocation!");
5645 SDNode *Node = Op.Val;
5646 MVT::ValueType NewVT = MVT::getVectorElementType(Op.getValueType());
5647 assert(MVT::getVectorNumElements(Op.getValueType()) == 1);
5649 // See if we already scalarized it.
5650 std::map<SDOperand, SDOperand>::iterator I = ScalarizedNodes.find(Op);
5651 if (I != ScalarizedNodes.end()) return I->second;
5654 switch (Node->getOpcode()) {
5657 Node->dump(&DAG); cerr << "\n";
5659 assert(0 && "Unknown vector operation in ScalarizeVectorOp!");
5675 Result = DAG.getNode(Node->getOpcode(),
5677 ScalarizeVectorOp(Node->getOperand(0)),
5678 ScalarizeVectorOp(Node->getOperand(1)));
5685 Result = DAG.getNode(Node->getOpcode(),
5687 ScalarizeVectorOp(Node->getOperand(0)));
5690 LoadSDNode *LD = cast<LoadSDNode>(Node);
5691 SDOperand Ch = LegalizeOp(LD->getChain()); // Legalize the chain.
5692 SDOperand Ptr = LegalizeOp(LD->getBasePtr()); // Legalize the pointer.
5694 const Value *SV = LD->getSrcValue();
5695 int SVOffset = LD->getSrcValueOffset();
5696 Result = DAG.getLoad(NewVT, Ch, Ptr, SV, SVOffset,
5697 LD->isVolatile(), LD->getAlignment());
5699 // Remember that we legalized the chain.
5700 AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
5703 case ISD::BUILD_VECTOR:
5704 Result = Node->getOperand(0);
5706 case ISD::INSERT_VECTOR_ELT:
5707 // Returning the inserted scalar element.
5708 Result = Node->getOperand(1);
5710 case ISD::CONCAT_VECTORS:
5711 assert(Node->getOperand(0).getValueType() == NewVT &&
5712 "Concat of non-legal vectors not yet supported!");
5713 Result = Node->getOperand(0);
5715 case ISD::VECTOR_SHUFFLE: {
5716 // Figure out if the scalar is the LHS or RHS and return it.
5717 SDOperand EltNum = Node->getOperand(2).getOperand(0);
5718 if (cast<ConstantSDNode>(EltNum)->getValue())
5719 Result = ScalarizeVectorOp(Node->getOperand(1));
5721 Result = ScalarizeVectorOp(Node->getOperand(0));
5724 case ISD::EXTRACT_SUBVECTOR:
5725 Result = Node->getOperand(0);
5726 assert(Result.getValueType() == NewVT);
5728 case ISD::BIT_CONVERT:
5729 Result = DAG.getNode(ISD::BIT_CONVERT, NewVT, Op.getOperand(0));
5732 Result = DAG.getNode(ISD::SELECT, NewVT, Op.getOperand(0),
5733 ScalarizeVectorOp(Op.getOperand(1)),
5734 ScalarizeVectorOp(Op.getOperand(2)));
5738 if (TLI.isTypeLegal(NewVT))
5739 Result = LegalizeOp(Result);
5740 bool isNew = ScalarizedNodes.insert(std::make_pair(Op, Result)).second;
5741 assert(isNew && "Value already scalarized?");
5746 // SelectionDAG::Legalize - This is the entry point for the file.
5748 void SelectionDAG::Legalize() {
5749 if (ViewLegalizeDAGs) viewGraph();
5751 /// run - This is the main entry point to this class.
5753 SelectionDAGLegalize(*this).LegalizeDAG();