1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SelectionDAG::Legalize method.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/SelectionDAG.h"
15 #include "llvm/CodeGen/MachineFunction.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineJumpTableInfo.h"
18 #include "llvm/CodeGen/MachineModuleInfo.h"
19 #include "llvm/CodeGen/DwarfWriter.h"
20 #include "llvm/Analysis/DebugInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/Target/TargetFrameInfo.h"
23 #include "llvm/Target/TargetLowering.h"
24 #include "llvm/Target/TargetData.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetSubtarget.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/DerivedTypes.h"
31 #include "llvm/Function.h"
32 #include "llvm/GlobalVariable.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Compiler.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallVector.h"
38 #include "llvm/ADT/SmallPtrSet.h"
42 //===----------------------------------------------------------------------===//
43 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and
44 /// hacks on it until the target machine can handle it. This involves
45 /// eliminating value sizes the machine cannot handle (promoting small sizes to
46 /// large sizes or splitting up large values into small values) as well as
47 /// eliminating operations the machine cannot handle.
49 /// This code also does a small amount of optimization and recognition of idioms
50 /// as part of its processing. For example, if a target does not support a
51 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
52 /// will attempt merge setcc and brc instructions into brcc's.
55 class VISIBILITY_HIDDEN SelectionDAGLegalize {
58 CodeGenOpt::Level OptLevel;
60 // Libcall insertion helpers.
62 /// LastCALLSEQ_END - This keeps track of the CALLSEQ_END node that has been
63 /// legalized. We use this to ensure that calls are properly serialized
64 /// against each other, including inserted libcalls.
65 SDValue LastCALLSEQ_END;
67 /// IsLegalizingCall - This member is used *only* for purposes of providing
68 /// helpful assertions that a libcall isn't created while another call is
69 /// being legalized (which could lead to non-serialized call sequences).
70 bool IsLegalizingCall;
73 Legal, // The target natively supports this operation.
74 Promote, // This operation should be executed in a larger type.
75 Expand // Try to expand this to other ops, otherwise use a libcall.
78 /// ValueTypeActions - This is a bitvector that contains two bits for each
79 /// value type, where the two bits correspond to the LegalizeAction enum.
80 /// This can be queried with "getTypeAction(VT)".
81 TargetLowering::ValueTypeActionImpl ValueTypeActions;
83 /// LegalizedNodes - For nodes that are of legal width, and that have more
84 /// than one use, this map indicates what regularized operand to use. This
85 /// allows us to avoid legalizing the same thing more than once.
86 DenseMap<SDValue, SDValue> LegalizedNodes;
88 void AddLegalizedOperand(SDValue From, SDValue To) {
89 LegalizedNodes.insert(std::make_pair(From, To));
90 // If someone requests legalization of the new node, return itself.
92 LegalizedNodes.insert(std::make_pair(To, To));
96 SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol);
98 /// getTypeAction - Return how we should legalize values of this type, either
99 /// it is already legal or we need to expand it into multiple registers of
100 /// smaller integer type, or we need to promote it to a larger type.
101 LegalizeAction getTypeAction(MVT VT) const {
102 return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
105 /// isTypeLegal - Return true if this type is legal on this target.
107 bool isTypeLegal(MVT VT) const {
108 return getTypeAction(VT) == Legal;
114 /// LegalizeOp - We know that the specified value has a legal type.
115 /// Recursively ensure that the operands have legal types, then return the
117 SDValue LegalizeOp(SDValue O);
119 SDValue OptimizeFloatStore(StoreSDNode *ST);
121 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
122 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
123 /// is necessary to spill the vector being inserted into to memory, perform
124 /// the insert there, and then read the result back.
125 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val,
126 SDValue Idx, DebugLoc dl);
127 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
128 SDValue Idx, DebugLoc dl);
130 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
131 /// performs the same shuffe in terms of order or result bytes, but on a type
132 /// whose vector element type is narrower than the original shuffle type.
133 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
134 SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
135 SDValue N1, SDValue N2,
136 SmallVectorImpl<int> &Mask) const;
138 bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
139 SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
141 void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
144 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
145 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32,
146 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80,
147 RTLIB::Libcall Call_PPCF128);
148 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, RTLIB::Libcall Call_I16,
149 RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
150 RTLIB::Libcall Call_I128);
152 SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
153 SDValue ExpandBUILD_VECTOR(SDNode *Node);
154 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
155 SDValue ExpandDBG_STOPPOINT(SDNode *Node);
156 void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
157 SmallVectorImpl<SDValue> &Results);
158 SDValue ExpandFCOPYSIGN(SDNode *Node);
159 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
161 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
163 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
166 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
167 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl);
169 SDValue ExpandExtractFromVectorThroughStack(SDValue Op);
170 SDValue ExpandVectorBuildThroughStack(SDNode* Node);
172 void ExpandNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
173 void PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results);
177 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which
178 /// performs the same shuffe in terms of order or result bytes, but on a type
179 /// whose vector element type is narrower than the original shuffle type.
180 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
182 SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
183 SDValue N1, SDValue N2,
184 SmallVectorImpl<int> &Mask) const {
185 MVT EltVT = NVT.getVectorElementType();
186 unsigned NumMaskElts = VT.getVectorNumElements();
187 unsigned NumDestElts = NVT.getVectorNumElements();
188 unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
190 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!");
192 if (NumEltsGrowth == 1)
193 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
195 SmallVector<int, 8> NewMask;
196 for (unsigned i = 0; i != NumMaskElts; ++i) {
198 for (unsigned j = 0; j != NumEltsGrowth; ++j) {
200 NewMask.push_back(-1);
202 NewMask.push_back(Idx * NumEltsGrowth + j);
205 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?");
206 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?");
207 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
210 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag,
211 CodeGenOpt::Level ol)
212 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
213 ValueTypeActions(TLI.getValueTypeActions()) {
214 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
215 "Too many value types for ValueTypeActions to hold!");
218 void SelectionDAGLegalize::LegalizeDAG() {
219 LastCALLSEQ_END = DAG.getEntryNode();
220 IsLegalizingCall = false;
222 // The legalize process is inherently a bottom-up recursive process (users
223 // legalize their uses before themselves). Given infinite stack space, we
224 // could just start legalizing on the root and traverse the whole graph. In
225 // practice however, this causes us to run out of stack space on large basic
226 // blocks. To avoid this problem, compute an ordering of the nodes where each
227 // node is only legalized after all of its operands are legalized.
228 DAG.AssignTopologicalOrder();
229 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
230 E = prior(DAG.allnodes_end()); I != next(E); ++I)
231 LegalizeOp(SDValue(I, 0));
233 // Finally, it's possible the root changed. Get the new root.
234 SDValue OldRoot = DAG.getRoot();
235 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?");
236 DAG.setRoot(LegalizedNodes[OldRoot]);
238 LegalizedNodes.clear();
240 // Remove dead nodes now.
241 DAG.RemoveDeadNodes();
245 /// FindCallEndFromCallStart - Given a chained node that is part of a call
246 /// sequence, find the CALLSEQ_END node that terminates the call sequence.
247 static SDNode *FindCallEndFromCallStart(SDNode *Node) {
248 if (Node->getOpcode() == ISD::CALLSEQ_END)
250 if (Node->use_empty())
251 return 0; // No CallSeqEnd
253 // The chain is usually at the end.
254 SDValue TheChain(Node, Node->getNumValues()-1);
255 if (TheChain.getValueType() != MVT::Other) {
256 // Sometimes it's at the beginning.
257 TheChain = SDValue(Node, 0);
258 if (TheChain.getValueType() != MVT::Other) {
259 // Otherwise, hunt for it.
260 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
261 if (Node->getValueType(i) == MVT::Other) {
262 TheChain = SDValue(Node, i);
266 // Otherwise, we walked into a node without a chain.
267 if (TheChain.getValueType() != MVT::Other)
272 for (SDNode::use_iterator UI = Node->use_begin(),
273 E = Node->use_end(); UI != E; ++UI) {
275 // Make sure to only follow users of our token chain.
277 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i)
278 if (User->getOperand(i) == TheChain)
279 if (SDNode *Result = FindCallEndFromCallStart(User))
285 /// FindCallStartFromCallEnd - Given a chained node that is part of a call
286 /// sequence, find the CALLSEQ_START node that initiates the call sequence.
287 static SDNode *FindCallStartFromCallEnd(SDNode *Node) {
288 assert(Node && "Didn't find callseq_start for a call??");
289 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
291 assert(Node->getOperand(0).getValueType() == MVT::Other &&
292 "Node doesn't have a token chain argument!");
293 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
296 /// LegalizeAllNodesNotLeadingTo - Recursively walk the uses of N, looking to
297 /// see if any uses can reach Dest. If no dest operands can get to dest,
298 /// legalize them, legalize ourself, and return false, otherwise, return true.
300 /// Keep track of the nodes we fine that actually do lead to Dest in
301 /// NodesLeadingTo. This avoids retraversing them exponential number of times.
303 bool SelectionDAGLegalize::LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
304 SmallPtrSet<SDNode*, 32> &NodesLeadingTo) {
305 if (N == Dest) return true; // N certainly leads to Dest :)
307 // If we've already processed this node and it does lead to Dest, there is no
308 // need to reprocess it.
309 if (NodesLeadingTo.count(N)) return true;
311 // If the first result of this node has been already legalized, then it cannot
313 if (LegalizedNodes.count(SDValue(N, 0))) return false;
315 // Okay, this node has not already been legalized. Check and legalize all
316 // operands. If none lead to Dest, then we can legalize this node.
317 bool OperandsLeadToDest = false;
318 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
319 OperandsLeadToDest |= // If an operand leads to Dest, so do we.
320 LegalizeAllNodesNotLeadingTo(N->getOperand(i).getNode(), Dest, NodesLeadingTo);
322 if (OperandsLeadToDest) {
323 NodesLeadingTo.insert(N);
327 // Okay, this node looks safe, legalize it and return false.
328 LegalizeOp(SDValue(N, 0));
332 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or
333 /// a load from the constant pool.
334 static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
335 SelectionDAG &DAG, const TargetLowering &TLI) {
337 DebugLoc dl = CFP->getDebugLoc();
339 // If a FP immediate is precise when represented as a float and if the
340 // target can do an extending load from float to double, we put it into
341 // the constant pool as a float, even if it's is statically typed as a
342 // double. This shrinks FP constants and canonicalizes them for targets where
343 // an FP extending load is the same cost as a normal load (such as on the x87
344 // fp stack or PPC FP unit).
345 MVT VT = CFP->getValueType(0);
346 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
348 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
349 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
350 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
355 while (SVT != MVT::f32) {
356 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
357 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
358 // Only do this if the target has a native EXTLOAD instruction from
360 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
361 TLI.ShouldShrinkFPConstant(OrigVT)) {
362 const Type *SType = SVT.getTypeForMVT(*DAG.getContext());
363 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
369 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy());
370 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
372 return DAG.getExtLoad(ISD::EXTLOAD, dl,
373 OrigVT, DAG.getEntryNode(),
374 CPIdx, PseudoSourceValue::getConstantPool(),
375 0, VT, false, Alignment);
376 return DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx,
377 PseudoSourceValue::getConstantPool(), 0, false, Alignment);
380 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores.
382 SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG,
383 const TargetLowering &TLI) {
384 SDValue Chain = ST->getChain();
385 SDValue Ptr = ST->getBasePtr();
386 SDValue Val = ST->getValue();
387 MVT VT = Val.getValueType();
388 int Alignment = ST->getAlignment();
389 int SVOffset = ST->getSrcValueOffset();
390 DebugLoc dl = ST->getDebugLoc();
391 if (ST->getMemoryVT().isFloatingPoint() ||
392 ST->getMemoryVT().isVector()) {
393 MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
394 if (TLI.isTypeLegal(intVT)) {
395 // Expand to a bitconvert of the value to the integer type of the
396 // same size, then a (misaligned) int store.
397 // FIXME: Does not handle truncating floating point stores!
398 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, intVT, Val);
399 return DAG.getStore(Chain, dl, Result, Ptr, ST->getSrcValue(),
400 SVOffset, ST->isVolatile(), Alignment);
402 // Do a (aligned) store to a stack slot, then copy from the stack slot
403 // to the final destination using (unaligned) integer loads and stores.
404 MVT StoredVT = ST->getMemoryVT();
406 TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
407 unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
408 unsigned RegBytes = RegVT.getSizeInBits() / 8;
409 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
411 // Make sure the stack slot is also aligned for the register type.
412 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT);
414 // Perform the original store, only redirected to the stack slot.
415 SDValue Store = DAG.getTruncStore(Chain, dl,
416 Val, StackPtr, NULL, 0, StoredVT);
417 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
418 SmallVector<SDValue, 8> Stores;
421 // Do all but one copies using the full register width.
422 for (unsigned i = 1; i < NumRegs; i++) {
423 // Load one integer register's worth from the stack slot.
424 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, NULL, 0);
425 // Store it to the final location. Remember the store.
426 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr,
427 ST->getSrcValue(), SVOffset + Offset,
429 MinAlign(ST->getAlignment(), Offset)));
430 // Increment the pointers.
432 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
434 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
437 // The last store may be partial. Do a truncating store. On big-endian
438 // machines this requires an extending load from the stack slot to ensure
439 // that the bits are in the right place.
440 MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
442 // Load from the stack slot.
443 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
446 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr,
447 ST->getSrcValue(), SVOffset + Offset,
448 MemVT, ST->isVolatile(),
449 MinAlign(ST->getAlignment(), Offset)));
450 // The order of the stores doesn't matter - say it with a TokenFactor.
451 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
455 assert(ST->getMemoryVT().isInteger() &&
456 !ST->getMemoryVT().isVector() &&
457 "Unaligned store of unknown type.");
458 // Get the half-size VT
460 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
461 int NumBits = NewStoredVT.getSizeInBits();
462 int IncrementSize = NumBits / 8;
464 // Divide the stored value in two parts.
465 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
467 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
469 // Store the two parts
470 SDValue Store1, Store2;
471 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr,
472 ST->getSrcValue(), SVOffset, NewStoredVT,
473 ST->isVolatile(), Alignment);
474 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
475 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
476 Alignment = MinAlign(Alignment, IncrementSize);
477 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr,
478 ST->getSrcValue(), SVOffset + IncrementSize,
479 NewStoredVT, ST->isVolatile(), Alignment);
481 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
484 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
486 SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG,
487 const TargetLowering &TLI) {
488 int SVOffset = LD->getSrcValueOffset();
489 SDValue Chain = LD->getChain();
490 SDValue Ptr = LD->getBasePtr();
491 MVT VT = LD->getValueType(0);
492 MVT LoadedVT = LD->getMemoryVT();
493 DebugLoc dl = LD->getDebugLoc();
494 if (VT.isFloatingPoint() || VT.isVector()) {
495 MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
496 if (TLI.isTypeLegal(intVT)) {
497 // Expand to a (misaligned) integer load of the same size,
498 // then bitconvert to floating point or vector.
499 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getSrcValue(),
500 SVOffset, LD->isVolatile(),
502 SDValue Result = DAG.getNode(ISD::BIT_CONVERT, dl, LoadedVT, newLoad);
503 if (VT.isFloatingPoint() && LoadedVT != VT)
504 Result = DAG.getNode(ISD::FP_EXTEND, dl, VT, Result);
506 SDValue Ops[] = { Result, Chain };
507 return DAG.getMergeValues(Ops, 2, dl);
509 // Copy the value to a (aligned) stack slot using (unaligned) integer
510 // loads and stores, then do a (aligned) load from the stack slot.
511 MVT RegVT = TLI.getRegisterType(intVT);
512 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
513 unsigned RegBytes = RegVT.getSizeInBits() / 8;
514 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
516 // Make sure the stack slot is also aligned for the register type.
517 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT);
519 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy());
520 SmallVector<SDValue, 8> Stores;
521 SDValue StackPtr = StackBase;
524 // Do all but one copies using the full register width.
525 for (unsigned i = 1; i < NumRegs; i++) {
526 // Load one integer register's worth from the original location.
527 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, LD->getSrcValue(),
528 SVOffset + Offset, LD->isVolatile(),
529 MinAlign(LD->getAlignment(), Offset));
530 // Follow the load with a store to the stack slot. Remember the store.
531 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr,
533 // Increment the pointers.
535 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
536 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
540 // The last copy may be partial. Do an extending load.
541 MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
542 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
543 LD->getSrcValue(), SVOffset + Offset,
544 MemVT, LD->isVolatile(),
545 MinAlign(LD->getAlignment(), Offset));
546 // Follow the load with a store to the stack slot. Remember the store.
547 // On big-endian machines this requires a truncating store to ensure
548 // that the bits end up in the right place.
549 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr,
552 // The order of the stores doesn't matter - say it with a TokenFactor.
553 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
556 // Finally, perform the original load only redirected to the stack slot.
557 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
560 // Callers expect a MERGE_VALUES node.
561 SDValue Ops[] = { Load, TF };
562 return DAG.getMergeValues(Ops, 2, dl);
565 assert(LoadedVT.isInteger() && !LoadedVT.isVector() &&
566 "Unaligned load of unsupported type.");
568 // Compute the new VT that is half the size of the old one. This is an
570 unsigned NumBits = LoadedVT.getSizeInBits();
572 NewLoadedVT = MVT::getIntegerVT(NumBits/2);
575 unsigned Alignment = LD->getAlignment();
576 unsigned IncrementSize = NumBits / 8;
577 ISD::LoadExtType HiExtType = LD->getExtensionType();
579 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD.
580 if (HiExtType == ISD::NON_EXTLOAD)
581 HiExtType = ISD::ZEXTLOAD;
583 // Load the value in two parts
585 if (TLI.isLittleEndian()) {
586 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
587 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
588 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
589 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
590 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
591 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
592 MinAlign(Alignment, IncrementSize));
594 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getSrcValue(),
595 SVOffset, NewLoadedVT, LD->isVolatile(), Alignment);
596 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr,
597 DAG.getConstant(IncrementSize, TLI.getPointerTy()));
598 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getSrcValue(),
599 SVOffset + IncrementSize, NewLoadedVT, LD->isVolatile(),
600 MinAlign(Alignment, IncrementSize));
603 // aggregate the two parts
604 SDValue ShiftAmount = DAG.getConstant(NumBits, TLI.getShiftAmountTy());
605 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
606 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
608 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
611 SDValue Ops[] = { Result, TF };
612 return DAG.getMergeValues(Ops, 2, dl);
615 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable
616 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
617 /// is necessary to spill the vector being inserted into to memory, perform
618 /// the insert there, and then read the result back.
619 SDValue SelectionDAGLegalize::
620 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx,
626 // If the target doesn't support this, we have to spill the input vector
627 // to a temporary stack slot, update the element, then reload it. This is
628 // badness. We could also load the value into a vector register (either
629 // with a "move to register" or "extload into register" instruction, then
630 // permute it into place, if the idx is a constant and if the idx is
631 // supported by the target.
632 MVT VT = Tmp1.getValueType();
633 MVT EltVT = VT.getVectorElementType();
634 MVT IdxVT = Tmp3.getValueType();
635 MVT PtrVT = TLI.getPointerTy();
636 SDValue StackPtr = DAG.CreateStackTemporary(VT);
638 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
641 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
642 PseudoSourceValue::getFixedStack(SPFI), 0);
644 // Truncate or zero extend offset to target pointer type.
645 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
646 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3);
647 // Add the offset to the index.
648 unsigned EltSize = EltVT.getSizeInBits()/8;
649 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT));
650 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr);
651 // Store the scalar value.
652 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2,
653 PseudoSourceValue::getFixedStack(SPFI), 0, EltVT);
654 // Load the updated vector.
655 return DAG.getLoad(VT, dl, Ch, StackPtr,
656 PseudoSourceValue::getFixedStack(SPFI), 0);
660 SDValue SelectionDAGLegalize::
661 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) {
662 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
663 // SCALAR_TO_VECTOR requires that the type of the value being inserted
664 // match the element type of the vector being created, except for
665 // integers in which case the inserted value can be over width.
666 MVT EltVT = Vec.getValueType().getVectorElementType();
667 if (Val.getValueType() == EltVT ||
668 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
669 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
670 Vec.getValueType(), Val);
672 unsigned NumElts = Vec.getValueType().getVectorNumElements();
673 // We generate a shuffle of InVec and ScVec, so the shuffle mask
674 // should be 0,1,2,3,4,5... with the appropriate element replaced with
676 SmallVector<int, 8> ShufOps;
677 for (unsigned i = 0; i != NumElts; ++i)
678 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts);
680 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
684 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl);
687 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
688 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
689 // FIXME: We shouldn't do this for TargetConstantFP's.
690 // FIXME: move this to the DAG Combiner! Note that we can't regress due
691 // to phase ordering between legalized code and the dag combiner. This
692 // probably means that we need to integrate dag combiner and legalizer
694 // We generally can't do this one for long doubles.
695 SDValue Tmp1 = ST->getChain();
696 SDValue Tmp2 = ST->getBasePtr();
698 int SVOffset = ST->getSrcValueOffset();
699 unsigned Alignment = ST->getAlignment();
700 bool isVolatile = ST->isVolatile();
701 DebugLoc dl = ST->getDebugLoc();
702 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
703 if (CFP->getValueType(0) == MVT::f32 &&
704 getTypeAction(MVT::i32) == Legal) {
705 Tmp3 = DAG.getConstant(CFP->getValueAPF().
706 bitcastToAPInt().zextOrTrunc(32),
708 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
709 SVOffset, isVolatile, Alignment);
710 } else if (CFP->getValueType(0) == MVT::f64) {
711 // If this target supports 64-bit registers, do a single 64-bit store.
712 if (getTypeAction(MVT::i64) == Legal) {
713 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
714 zextOrTrunc(64), MVT::i64);
715 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
716 SVOffset, isVolatile, Alignment);
717 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
718 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
719 // stores. If the target supports neither 32- nor 64-bits, this
720 // xform is certainly not worth it.
721 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
722 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
723 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
724 if (TLI.isBigEndian()) std::swap(Lo, Hi);
726 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
727 SVOffset, isVolatile, Alignment);
728 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
729 DAG.getIntPtrConstant(4));
730 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
731 isVolatile, MinAlign(Alignment, 4U));
733 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
740 /// LegalizeOp - We know that the specified value has a legal type, and
741 /// that its operands are legal. Now ensure that the operation itself
742 /// is legal, recursively ensuring that the operands' operations remain
744 SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
745 if (Op.getOpcode() == ISD::TargetConstant) // Allow illegal target nodes.
748 SDNode *Node = Op.getNode();
749 DebugLoc dl = Node->getDebugLoc();
751 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
752 assert(getTypeAction(Node->getValueType(i)) == Legal &&
753 "Unexpected illegal type!");
755 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
756 assert((isTypeLegal(Node->getOperand(i).getValueType()) ||
757 Node->getOperand(i).getOpcode() == ISD::TargetConstant) &&
758 "Unexpected illegal type!");
760 // Note that LegalizeOp may be reentered even from single-use nodes, which
761 // means that we always must cache transformed nodes.
762 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
763 if (I != LegalizedNodes.end()) return I->second;
765 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
767 bool isCustom = false;
769 // Figure out the correct action; the way to query this varies by opcode
770 TargetLowering::LegalizeAction Action;
771 bool SimpleFinishLegalizing = true;
772 switch (Node->getOpcode()) {
773 case ISD::INTRINSIC_W_CHAIN:
774 case ISD::INTRINSIC_WO_CHAIN:
775 case ISD::INTRINSIC_VOID:
778 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
780 case ISD::SINT_TO_FP:
781 case ISD::UINT_TO_FP:
782 case ISD::EXTRACT_VECTOR_ELT:
783 Action = TLI.getOperationAction(Node->getOpcode(),
784 Node->getOperand(0).getValueType());
786 case ISD::FP_ROUND_INREG:
787 case ISD::SIGN_EXTEND_INREG: {
788 MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
789 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
795 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
796 Node->getOpcode() == ISD::SETCC ? 2 : 1;
797 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
798 MVT OpVT = Node->getOperand(CompareOperand).getValueType();
799 ISD::CondCode CCCode =
800 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
801 Action = TLI.getCondCodeAction(CCCode, OpVT);
802 if (Action == TargetLowering::Legal) {
803 if (Node->getOpcode() == ISD::SELECT_CC)
804 Action = TLI.getOperationAction(Node->getOpcode(),
805 Node->getValueType(0));
807 Action = TLI.getOperationAction(Node->getOpcode(), OpVT);
813 // FIXME: Model these properly. LOAD and STORE are complicated, and
814 // STORE expects the unlegalized operand in some cases.
815 SimpleFinishLegalizing = false;
817 case ISD::CALLSEQ_START:
818 case ISD::CALLSEQ_END:
819 // FIXME: This shouldn't be necessary. These nodes have special properties
820 // dealing with the recursive nature of legalization. Removing this
821 // special case should be done as part of making LegalizeDAG non-recursive.
822 SimpleFinishLegalizing = false;
825 // FIXME: Legalization for calls requires custom-lowering the call before
826 // legalizing the operands! (I haven't looked into precisely why.)
827 SimpleFinishLegalizing = false;
829 case ISD::EXTRACT_ELEMENT:
830 case ISD::FLT_ROUNDS_:
838 case ISD::MERGE_VALUES:
840 case ISD::FRAME_TO_ARGS_OFFSET:
841 // These operations lie about being legal: when they claim to be legal,
842 // they should actually be expanded.
843 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
844 if (Action == TargetLowering::Legal)
845 Action = TargetLowering::Expand;
847 case ISD::TRAMPOLINE:
849 case ISD::RETURNADDR:
850 case ISD::FORMAL_ARGUMENTS:
851 // These operations lie about being legal: when they claim to be legal,
852 // they should actually be custom-lowered.
853 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
854 if (Action == TargetLowering::Legal)
855 Action = TargetLowering::Custom;
857 case ISD::BUILD_VECTOR:
858 // A weird case: legalization for BUILD_VECTOR never legalizes the
860 // FIXME: This really sucks... changing it isn't semantically incorrect,
861 // but it massively pessimizes the code for floating-point BUILD_VECTORs
862 // because ConstantFP operands get legalized into constant pool loads
863 // before the BUILD_VECTOR code can see them. It doesn't usually bite,
864 // though, because BUILD_VECTORS usually get lowered into other nodes
865 // which get legalized properly.
866 SimpleFinishLegalizing = false;
869 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) {
870 Action = TargetLowering::Legal;
872 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
877 if (SimpleFinishLegalizing) {
878 SmallVector<SDValue, 8> Ops, ResultVals;
879 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
880 Ops.push_back(LegalizeOp(Node->getOperand(i)));
881 switch (Node->getOpcode()) {
889 // Branches tweak the chain to include LastCALLSEQ_END
890 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
892 Ops[0] = LegalizeOp(Ops[0]);
893 LastCALLSEQ_END = DAG.getEntryNode();
900 // Legalizing shifts/rotates requires adjusting the shift amount
901 // to the appropriate width.
902 if (!Ops[1].getValueType().isVector())
903 Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
907 Result = DAG.UpdateNodeOperands(Result.getValue(0), Ops.data(),
910 case TargetLowering::Legal:
911 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
912 ResultVals.push_back(Result.getValue(i));
914 case TargetLowering::Custom:
915 // FIXME: The handling for custom lowering with multiple results is
917 Tmp1 = TLI.LowerOperation(Result, DAG);
918 if (Tmp1.getNode()) {
919 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) {
921 ResultVals.push_back(Tmp1);
923 ResultVals.push_back(Tmp1.getValue(i));
929 case TargetLowering::Expand:
930 ExpandNode(Result.getNode(), ResultVals);
932 case TargetLowering::Promote:
933 PromoteNode(Result.getNode(), ResultVals);
936 if (!ResultVals.empty()) {
937 for (unsigned i = 0, e = ResultVals.size(); i != e; ++i) {
938 if (ResultVals[i] != SDValue(Node, i))
939 ResultVals[i] = LegalizeOp(ResultVals[i]);
940 AddLegalizedOperand(SDValue(Node, i), ResultVals[i]);
942 return ResultVals[Op.getResNo()];
946 switch (Node->getOpcode()) {
949 cerr << "NODE: "; Node->dump(&DAG); cerr << "\n";
951 assert(0 && "Do not know how to legalize this operator!");
954 // The only option for this is to custom lower it.
955 Tmp3 = TLI.LowerOperation(Result.getValue(0), DAG);
956 assert(Tmp3.getNode() && "Target didn't custom lower this node!");
957 // A call within a calling sequence must be legalized to something
958 // other than the normal CALLSEQ_END. Violating this gets Legalize
959 // into an infinite loop.
960 assert ((!IsLegalizingCall ||
961 Node->getOpcode() != ISD::CALL ||
962 Tmp3.getNode()->getOpcode() != ISD::CALLSEQ_END) &&
963 "Nested CALLSEQ_START..CALLSEQ_END not supported.");
965 // The number of incoming and outgoing values should match; unless the final
966 // outgoing value is a flag.
967 assert((Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() ||
968 (Tmp3.getNode()->getNumValues() == Result.getNode()->getNumValues() + 1 &&
969 Tmp3.getNode()->getValueType(Tmp3.getNode()->getNumValues() - 1) ==
971 "Lowering call/formal_arguments produced unexpected # results!");
973 // Since CALL/FORMAL_ARGUMENTS nodes produce multiple values, make sure to
974 // remember that we legalized all of them, so it doesn't get relegalized.
975 for (unsigned i = 0, e = Tmp3.getNode()->getNumValues(); i != e; ++i) {
976 if (Tmp3.getNode()->getValueType(i) == MVT::Flag)
978 Tmp1 = LegalizeOp(Tmp3.getValue(i));
979 if (Op.getResNo() == i)
981 AddLegalizedOperand(SDValue(Node, i), Tmp1);
984 case ISD::BUILD_VECTOR:
985 switch (TLI.getOperationAction(ISD::BUILD_VECTOR, Node->getValueType(0))) {
986 default: assert(0 && "This action is not supported yet!");
987 case TargetLowering::Custom:
988 Tmp3 = TLI.LowerOperation(Result, DAG);
989 if (Tmp3.getNode()) {
994 case TargetLowering::Expand:
995 Result = ExpandBUILD_VECTOR(Result.getNode());
999 case ISD::CALLSEQ_START: {
1000 SDNode *CallEnd = FindCallEndFromCallStart(Node);
1002 // Recursively Legalize all of the inputs of the call end that do not lead
1003 // to this call start. This ensures that any libcalls that need be inserted
1004 // are inserted *before* the CALLSEQ_START.
1005 {SmallPtrSet<SDNode*, 32> NodesLeadingTo;
1006 for (unsigned i = 0, e = CallEnd->getNumOperands(); i != e; ++i)
1007 LegalizeAllNodesNotLeadingTo(CallEnd->getOperand(i).getNode(), Node,
1011 // Now that we legalized all of the inputs (which may have inserted
1012 // libcalls) create the new CALLSEQ_START node.
1013 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1015 // Merge in the last call, to ensure that this call start after the last
1017 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
1018 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1019 Tmp1, LastCALLSEQ_END);
1020 Tmp1 = LegalizeOp(Tmp1);
1023 // Do not try to legalize the target-specific arguments (#1+).
1024 if (Tmp1 != Node->getOperand(0)) {
1025 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1027 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1030 // Remember that the CALLSEQ_START is legalized.
1031 AddLegalizedOperand(Op.getValue(0), Result);
1032 if (Node->getNumValues() == 2) // If this has a flag result, remember it.
1033 AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
1035 // Now that the callseq_start and all of the non-call nodes above this call
1036 // sequence have been legalized, legalize the call itself. During this
1037 // process, no libcalls can/will be inserted, guaranteeing that no calls
1039 assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
1040 // Note that we are selecting this call!
1041 LastCALLSEQ_END = SDValue(CallEnd, 0);
1042 IsLegalizingCall = true;
1044 // Legalize the call, starting from the CALLSEQ_END.
1045 LegalizeOp(LastCALLSEQ_END);
1046 assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
1049 case ISD::CALLSEQ_END:
1050 // If the CALLSEQ_START node hasn't been legalized first, legalize it. This
1051 // will cause this node to be legalized as well as handling libcalls right.
1052 if (LastCALLSEQ_END.getNode() != Node) {
1053 LegalizeOp(SDValue(FindCallStartFromCallEnd(Node), 0));
1054 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op);
1055 assert(I != LegalizedNodes.end() &&
1056 "Legalizing the call start should have legalized this node!");
1060 // Otherwise, the call start has been legalized and everything is going
1061 // according to plan. Just legalize ourselves normally here.
1062 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
1063 // Do not try to legalize the target-specific arguments (#1+), except for
1064 // an optional flag input.
1065 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
1066 if (Tmp1 != Node->getOperand(0)) {
1067 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1069 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1072 Tmp2 = LegalizeOp(Node->getOperand(Node->getNumOperands()-1));
1073 if (Tmp1 != Node->getOperand(0) ||
1074 Tmp2 != Node->getOperand(Node->getNumOperands()-1)) {
1075 SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1078 Result = DAG.UpdateNodeOperands(Result, &Ops[0], Ops.size());
1081 assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
1082 // This finishes up call legalization.
1083 IsLegalizingCall = false;
1085 // If the CALLSEQ_END node has a flag, remember that we legalized it.
1086 AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
1087 if (Node->getNumValues() == 2)
1088 AddLegalizedOperand(SDValue(Node, 1), Result.getValue(1));
1089 return Result.getValue(Op.getResNo());
1091 LoadSDNode *LD = cast<LoadSDNode>(Node);
1092 Tmp1 = LegalizeOp(LD->getChain()); // Legalize the chain.
1093 Tmp2 = LegalizeOp(LD->getBasePtr()); // Legalize the base pointer.
1095 ISD::LoadExtType ExtType = LD->getExtensionType();
1096 if (ExtType == ISD::NON_EXTLOAD) {
1097 MVT VT = Node->getValueType(0);
1098 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1099 Tmp3 = Result.getValue(0);
1100 Tmp4 = Result.getValue(1);
1102 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
1103 default: assert(0 && "This action is not supported yet!");
1104 case TargetLowering::Legal:
1105 // If this is an unaligned load and the target doesn't support it,
1107 if (!TLI.allowsUnalignedMemoryAccesses()) {
1108 unsigned ABIAlignment = TLI.getTargetData()->
1109 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT(
1110 *DAG.getContext()));
1111 if (LD->getAlignment() < ABIAlignment){
1112 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1114 Tmp3 = Result.getOperand(0);
1115 Tmp4 = Result.getOperand(1);
1116 Tmp3 = LegalizeOp(Tmp3);
1117 Tmp4 = LegalizeOp(Tmp4);
1121 case TargetLowering::Custom:
1122 Tmp1 = TLI.LowerOperation(Tmp3, DAG);
1123 if (Tmp1.getNode()) {
1124 Tmp3 = LegalizeOp(Tmp1);
1125 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1128 case TargetLowering::Promote: {
1129 // Only promote a load of vector type to another.
1130 assert(VT.isVector() && "Cannot promote this load!");
1131 // Change base type to a different vector type.
1132 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
1134 Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1135 LD->getSrcValueOffset(),
1136 LD->isVolatile(), LD->getAlignment());
1137 Tmp3 = LegalizeOp(DAG.getNode(ISD::BIT_CONVERT, dl, VT, Tmp1));
1138 Tmp4 = LegalizeOp(Tmp1.getValue(1));
1142 // Since loads produce two values, make sure to remember that we
1143 // legalized both of them.
1144 AddLegalizedOperand(SDValue(Node, 0), Tmp3);
1145 AddLegalizedOperand(SDValue(Node, 1), Tmp4);
1146 return Op.getResNo() ? Tmp4 : Tmp3;
1148 MVT SrcVT = LD->getMemoryVT();
1149 unsigned SrcWidth = SrcVT.getSizeInBits();
1150 int SVOffset = LD->getSrcValueOffset();
1151 unsigned Alignment = LD->getAlignment();
1152 bool isVolatile = LD->isVolatile();
1154 if (SrcWidth != SrcVT.getStoreSizeInBits() &&
1155 // Some targets pretend to have an i1 loading operation, and actually
1156 // load an i8. This trick is correct for ZEXTLOAD because the top 7
1157 // bits are guaranteed to be zero; it helps the optimizers understand
1158 // that these bits are zero. It is also useful for EXTLOAD, since it
1159 // tells the optimizers that those bits are undefined. It would be
1160 // nice to have an effective generic way of getting these benefits...
1161 // Until such a way is found, don't insist on promoting i1 here.
1162 (SrcVT != MVT::i1 ||
1163 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
1164 // Promote to a byte-sized load if not loading an integral number of
1165 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
1166 unsigned NewWidth = SrcVT.getStoreSizeInBits();
1167 MVT NVT = MVT::getIntegerVT(NewWidth);
1170 // The extra bits are guaranteed to be zero, since we stored them that
1171 // way. A zext load from NVT thus automatically gives zext from SrcVT.
1173 ISD::LoadExtType NewExtType =
1174 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
1176 Result = DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
1177 Tmp1, Tmp2, LD->getSrcValue(), SVOffset,
1178 NVT, isVolatile, Alignment);
1180 Ch = Result.getValue(1); // The chain.
1182 if (ExtType == ISD::SEXTLOAD)
1183 // Having the top bits zero doesn't help when sign extending.
1184 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1185 Result.getValueType(),
1186 Result, DAG.getValueType(SrcVT));
1187 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
1188 // All the top bits are guaranteed to be zero - inform the optimizers.
1189 Result = DAG.getNode(ISD::AssertZext, dl,
1190 Result.getValueType(), Result,
1191 DAG.getValueType(SrcVT));
1193 Tmp1 = LegalizeOp(Result);
1194 Tmp2 = LegalizeOp(Ch);
1195 } else if (SrcWidth & (SrcWidth - 1)) {
1196 // If not loading a power-of-2 number of bits, expand as two loads.
1197 assert(SrcVT.isExtended() && !SrcVT.isVector() &&
1198 "Unsupported extload!");
1199 unsigned RoundWidth = 1 << Log2_32(SrcWidth);
1200 assert(RoundWidth < SrcWidth);
1201 unsigned ExtraWidth = SrcWidth - RoundWidth;
1202 assert(ExtraWidth < RoundWidth);
1203 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1204 "Load size not an integral number of bytes!");
1205 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1206 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1208 unsigned IncrementSize;
1210 if (TLI.isLittleEndian()) {
1211 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
1212 // Load the bottom RoundWidth bits.
1213 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1214 Node->getValueType(0), Tmp1, Tmp2,
1215 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1218 // Load the remaining ExtraWidth bits.
1219 IncrementSize = RoundWidth / 8;
1220 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1221 DAG.getIntPtrConstant(IncrementSize));
1222 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1223 LD->getSrcValue(), SVOffset + IncrementSize,
1224 ExtraVT, isVolatile,
1225 MinAlign(Alignment, IncrementSize));
1227 // Build a factor node to remember that this load is independent of the
1229 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1232 // Move the top bits to the right place.
1233 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1234 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1236 // Join the hi and lo parts.
1237 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1239 // Big endian - avoid unaligned loads.
1240 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
1241 // Load the top RoundWidth bits.
1242 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
1243 LD->getSrcValue(), SVOffset, RoundVT, isVolatile,
1246 // Load the remaining ExtraWidth bits.
1247 IncrementSize = RoundWidth / 8;
1248 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1249 DAG.getIntPtrConstant(IncrementSize));
1250 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl,
1251 Node->getValueType(0), Tmp1, Tmp2,
1252 LD->getSrcValue(), SVOffset + IncrementSize,
1253 ExtraVT, isVolatile,
1254 MinAlign(Alignment, IncrementSize));
1256 // Build a factor node to remember that this load is independent of the
1258 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
1261 // Move the top bits to the right place.
1262 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
1263 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1265 // Join the hi and lo parts.
1266 Result = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
1269 Tmp1 = LegalizeOp(Result);
1270 Tmp2 = LegalizeOp(Ch);
1272 switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
1273 default: assert(0 && "This action is not supported yet!");
1274 case TargetLowering::Custom:
1277 case TargetLowering::Legal:
1278 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
1279 Tmp1 = Result.getValue(0);
1280 Tmp2 = Result.getValue(1);
1283 Tmp3 = TLI.LowerOperation(Result, DAG);
1284 if (Tmp3.getNode()) {
1285 Tmp1 = LegalizeOp(Tmp3);
1286 Tmp2 = LegalizeOp(Tmp3.getValue(1));
1289 // If this is an unaligned load and the target doesn't support it,
1291 if (!TLI.allowsUnalignedMemoryAccesses()) {
1292 unsigned ABIAlignment = TLI.getTargetData()->
1293 getABITypeAlignment(LD->getMemoryVT().getTypeForMVT(
1294 *DAG.getContext()));
1295 if (LD->getAlignment() < ABIAlignment){
1296 Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
1298 Tmp1 = Result.getOperand(0);
1299 Tmp2 = Result.getOperand(1);
1300 Tmp1 = LegalizeOp(Tmp1);
1301 Tmp2 = LegalizeOp(Tmp2);
1306 case TargetLowering::Expand:
1307 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1308 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
1309 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
1310 LD->getSrcValueOffset(),
1311 LD->isVolatile(), LD->getAlignment());
1312 Result = DAG.getNode(ISD::FP_EXTEND, dl,
1313 Node->getValueType(0), Load);
1314 Tmp1 = LegalizeOp(Result); // Relegalize new nodes.
1315 Tmp2 = LegalizeOp(Load.getValue(1));
1318 assert(ExtType != ISD::EXTLOAD &&"EXTLOAD should always be supported!");
1319 // Turn the unsupported load into an EXTLOAD followed by an explicit
1320 // zero/sign extend inreg.
1321 Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
1322 Tmp1, Tmp2, LD->getSrcValue(),
1323 LD->getSrcValueOffset(), SrcVT,
1324 LD->isVolatile(), LD->getAlignment());
1326 if (ExtType == ISD::SEXTLOAD)
1327 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
1328 Result.getValueType(),
1329 Result, DAG.getValueType(SrcVT));
1331 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT);
1332 Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
1333 Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes.
1338 // Since loads produce two values, make sure to remember that we legalized
1340 AddLegalizedOperand(SDValue(Node, 0), Tmp1);
1341 AddLegalizedOperand(SDValue(Node, 1), Tmp2);
1342 return Op.getResNo() ? Tmp2 : Tmp1;
1346 StoreSDNode *ST = cast<StoreSDNode>(Node);
1347 Tmp1 = LegalizeOp(ST->getChain()); // Legalize the chain.
1348 Tmp2 = LegalizeOp(ST->getBasePtr()); // Legalize the pointer.
1349 int SVOffset = ST->getSrcValueOffset();
1350 unsigned Alignment = ST->getAlignment();
1351 bool isVolatile = ST->isVolatile();
1353 if (!ST->isTruncatingStore()) {
1354 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
1355 Result = SDValue(OptStore, 0);
1360 Tmp3 = LegalizeOp(ST->getValue());
1361 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1364 MVT VT = Tmp3.getValueType();
1365 switch (TLI.getOperationAction(ISD::STORE, VT)) {
1366 default: assert(0 && "This action is not supported yet!");
1367 case TargetLowering::Legal:
1368 // If this is an unaligned store and the target doesn't support it,
1370 if (!TLI.allowsUnalignedMemoryAccesses()) {
1371 unsigned ABIAlignment = TLI.getTargetData()->
1372 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT(
1373 *DAG.getContext()));
1374 if (ST->getAlignment() < ABIAlignment)
1375 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1379 case TargetLowering::Custom:
1380 Tmp1 = TLI.LowerOperation(Result, DAG);
1381 if (Tmp1.getNode()) Result = Tmp1;
1383 case TargetLowering::Promote:
1384 assert(VT.isVector() && "Unknown legal promote case!");
1385 Tmp3 = DAG.getNode(ISD::BIT_CONVERT, dl,
1386 TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
1387 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
1388 ST->getSrcValue(), SVOffset, isVolatile,
1395 Tmp3 = LegalizeOp(ST->getValue());
1397 MVT StVT = ST->getMemoryVT();
1398 unsigned StWidth = StVT.getSizeInBits();
1400 if (StWidth != StVT.getStoreSizeInBits()) {
1401 // Promote to a byte-sized store with upper bits zero if not
1402 // storing an integral number of bytes. For example, promote
1403 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
1404 MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
1405 Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
1406 Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1407 SVOffset, NVT, isVolatile, Alignment);
1408 } else if (StWidth & (StWidth - 1)) {
1409 // If not storing a power-of-2 number of bits, expand as two stores.
1410 assert(StVT.isExtended() && !StVT.isVector() &&
1411 "Unsupported truncstore!");
1412 unsigned RoundWidth = 1 << Log2_32(StWidth);
1413 assert(RoundWidth < StWidth);
1414 unsigned ExtraWidth = StWidth - RoundWidth;
1415 assert(ExtraWidth < RoundWidth);
1416 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
1417 "Store size not an integral number of bytes!");
1418 MVT RoundVT = MVT::getIntegerVT(RoundWidth);
1419 MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
1421 unsigned IncrementSize;
1423 if (TLI.isLittleEndian()) {
1424 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
1425 // Store the bottom RoundWidth bits.
1426 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1428 isVolatile, Alignment);
1430 // Store the remaining ExtraWidth bits.
1431 IncrementSize = RoundWidth / 8;
1432 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1433 DAG.getIntPtrConstant(IncrementSize));
1434 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1435 DAG.getConstant(RoundWidth, TLI.getShiftAmountTy()));
1436 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1437 SVOffset + IncrementSize, ExtraVT, isVolatile,
1438 MinAlign(Alignment, IncrementSize));
1440 // Big endian - avoid unaligned stores.
1441 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
1442 // Store the top RoundWidth bits.
1443 Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
1444 DAG.getConstant(ExtraWidth, TLI.getShiftAmountTy()));
1445 Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(),
1446 SVOffset, RoundVT, isVolatile, Alignment);
1448 // Store the remaining ExtraWidth bits.
1449 IncrementSize = RoundWidth / 8;
1450 Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
1451 DAG.getIntPtrConstant(IncrementSize));
1452 Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1453 SVOffset + IncrementSize, ExtraVT, isVolatile,
1454 MinAlign(Alignment, IncrementSize));
1457 // The order of the stores doesn't matter.
1458 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
1460 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
1461 Tmp2 != ST->getBasePtr())
1462 Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
1465 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
1466 default: assert(0 && "This action is not supported yet!");
1467 case TargetLowering::Legal:
1468 // If this is an unaligned store and the target doesn't support it,
1470 if (!TLI.allowsUnalignedMemoryAccesses()) {
1471 unsigned ABIAlignment = TLI.getTargetData()->
1472 getABITypeAlignment(ST->getMemoryVT().getTypeForMVT(
1473 *DAG.getContext()));
1474 if (ST->getAlignment() < ABIAlignment)
1475 Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
1479 case TargetLowering::Custom:
1480 Result = TLI.LowerOperation(Result, DAG);
1483 // TRUNCSTORE:i16 i32 -> STORE i16
1484 assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
1485 Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
1486 Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
1487 SVOffset, isVolatile, Alignment);
1495 assert(Result.getValueType() == Op.getValueType() &&
1496 "Bad legalization!");
1498 // Make sure that the generated code is itself legal.
1500 Result = LegalizeOp(Result);
1502 // Note that LegalizeOp may be reentered even from single-use nodes, which
1503 // means that we always must cache transformed nodes.
1504 AddLegalizedOperand(Op, Result);
1508 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) {
1509 SDValue Vec = Op.getOperand(0);
1510 SDValue Idx = Op.getOperand(1);
1511 DebugLoc dl = Op.getDebugLoc();
1512 // Store the value to a temporary stack slot, then LOAD the returned part.
1513 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType());
1514 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
1516 // Add the offset to the index.
1518 Vec.getValueType().getVectorElementType().getSizeInBits()/8;
1519 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx,
1520 DAG.getConstant(EltSize, Idx.getValueType()));
1522 if (Idx.getValueType().bitsGT(TLI.getPointerTy()))
1523 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx);
1525 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
1527 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr);
1529 if (Op.getValueType().isVector())
1530 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, NULL, 0);
1532 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr,
1533 NULL, 0, Vec.getValueType().getVectorElementType());
1536 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) {
1537 // We can't handle this case efficiently. Allocate a sufficiently
1538 // aligned object on the stack, store each element into it, then load
1539 // the result as a vector.
1540 // Create the stack frame object.
1541 MVT VT = Node->getValueType(0);
1542 MVT OpVT = Node->getOperand(0).getValueType();
1543 DebugLoc dl = Node->getDebugLoc();
1544 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1545 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
1546 const Value *SV = PseudoSourceValue::getFixedStack(FI);
1548 // Emit a store of each element to the stack slot.
1549 SmallVector<SDValue, 8> Stores;
1550 unsigned TypeByteSize = OpVT.getSizeInBits() / 8;
1551 // Store (in the right endianness) the elements to memory.
1552 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1553 // Ignore undef elements.
1554 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1556 unsigned Offset = TypeByteSize*i;
1558 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType());
1559 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx);
1561 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, Node->getOperand(i),
1566 if (!Stores.empty()) // Not all undef elements?
1567 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1568 &Stores[0], Stores.size());
1570 StoreChain = DAG.getEntryNode();
1572 // Result is a load from the stack slot.
1573 return DAG.getLoad(VT, dl, StoreChain, FIPtr, SV, 0);
1576 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) {
1577 DebugLoc dl = Node->getDebugLoc();
1578 SDValue Tmp1 = Node->getOperand(0);
1579 SDValue Tmp2 = Node->getOperand(1);
1580 assert((Tmp2.getValueType() == MVT::f32 ||
1581 Tmp2.getValueType() == MVT::f64) &&
1582 "Ugly special-cased code!");
1583 // Get the sign bit of the RHS.
1585 MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
1586 if (isTypeLegal(IVT)) {
1587 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
1589 assert(isTypeLegal(TLI.getPointerTy()) &&
1590 (TLI.getPointerTy() == MVT::i32 ||
1591 TLI.getPointerTy() == MVT::i64) &&
1592 "Legal type for load?!");
1593 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
1594 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
1596 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1597 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
1598 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
1599 LoadPtr, DAG.getIntPtrConstant(4));
1600 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1601 Ch, LoadPtr, NULL, 0, MVT::i32);
1604 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
1605 SignBit, DAG.getConstant(0, SignBit.getValueType()),
1607 // Get the absolute value of the result.
1608 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1609 // Select between the nabs and abs value based on the sign bit of
1611 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit,
1612 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal),
1616 SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) {
1617 DebugLoc dl = Node->getDebugLoc();
1618 DwarfWriter *DW = DAG.getDwarfWriter();
1619 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1621 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
1623 const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
1624 GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
1625 if (DW && (useDEBUG_LOC || useLABEL) && !CU_GV->isDeclaration()) {
1626 DICompileUnit CU(cast<GlobalVariable>(DSP->getCompileUnit()));
1628 unsigned Line = DSP->getLine();
1629 unsigned Col = DSP->getColumn();
1631 if (OptLevel == CodeGenOpt::None) {
1632 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
1633 // won't hurt anything.
1635 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
1636 DAG.getConstant(Line, MVT::i32),
1637 DAG.getConstant(Col, MVT::i32),
1638 DAG.getSrcValue(CU.getGV()));
1640 unsigned ID = DW->RecordSourceLine(Line, Col, CU);
1641 return DAG.getLabel(ISD::DBG_LABEL, dl, Node->getOperand(0), ID);
1645 return Node->getOperand(0);
1648 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node,
1649 SmallVectorImpl<SDValue> &Results) {
1650 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1651 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
1652 " not tell us which reg is the stack pointer!");
1653 DebugLoc dl = Node->getDebugLoc();
1654 MVT VT = Node->getValueType(0);
1655 SDValue Tmp1 = SDValue(Node, 0);
1656 SDValue Tmp2 = SDValue(Node, 1);
1657 SDValue Tmp3 = Node->getOperand(2);
1658 SDValue Chain = Tmp1.getOperand(0);
1660 // Chain the dynamic stack allocation so that it doesn't modify the stack
1661 // pointer when other instructions are using the stack.
1662 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1664 SDValue Size = Tmp2.getOperand(1);
1665 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1666 Chain = SP.getValue(1);
1667 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
1668 unsigned StackAlign =
1669 TLI.getTargetMachine().getFrameInfo()->getStackAlignment();
1670 if (Align > StackAlign)
1671 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1672 DAG.getConstant(-(uint64_t)Align, VT));
1673 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1674 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain
1676 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1677 DAG.getIntPtrConstant(0, true), SDValue());
1679 Results.push_back(Tmp1);
1680 Results.push_back(Tmp2);
1683 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and
1684 /// condition code CC on the current target. This routine assumes LHS and rHS
1685 /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
1686 /// illegal condition code into AND / OR of multiple SETCC values.
1687 void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
1688 SDValue &LHS, SDValue &RHS,
1691 MVT OpVT = LHS.getValueType();
1692 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
1693 switch (TLI.getCondCodeAction(CCCode, OpVT)) {
1694 default: assert(0 && "Unknown condition code action!");
1695 case TargetLowering::Legal:
1698 case TargetLowering::Expand: {
1699 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID;
1702 default: assert(0 && "Don't know how to expand this condition!"); abort();
1703 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break;
1704 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1705 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1706 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break;
1707 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1708 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break;
1709 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1710 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1711 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1712 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1713 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1714 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break;
1715 // FIXME: Implement more expansions.
1718 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1719 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1720 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1728 /// EmitStackConvert - Emit a store/load combination to the stack. This stores
1729 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does
1730 /// a load from the stack slot to DestVT, extending it if needed.
1731 /// The resultant code need not be legal.
1732 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
1736 // Create the stack frame object.
1738 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
1739 getTypeForMVT(*DAG.getContext()));
1740 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
1742 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
1743 int SPFI = StackPtrFI->getIndex();
1744 const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
1746 unsigned SrcSize = SrcOp.getValueType().getSizeInBits();
1747 unsigned SlotSize = SlotVT.getSizeInBits();
1748 unsigned DestSize = DestVT.getSizeInBits();
1749 unsigned DestAlign =
1750 TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT(
1751 *DAG.getContext()));
1753 // Emit a store to the stack slot. Use a truncstore if the input value is
1754 // later than DestVT.
1757 if (SrcSize > SlotSize)
1758 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1759 SV, 0, SlotVT, false, SrcAlign);
1761 assert(SrcSize == SlotSize && "Invalid store");
1762 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr,
1763 SV, 0, false, SrcAlign);
1766 // Result is a load from the stack slot.
1767 if (SlotSize == DestSize)
1768 return DAG.getLoad(DestVT, dl, Store, FIPtr, SV, 0, false, DestAlign);
1770 assert(SlotSize < DestSize && "Unknown extension!");
1771 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, SV, 0, SlotVT,
1775 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) {
1776 DebugLoc dl = Node->getDebugLoc();
1777 // Create a vector sized/aligned stack slot, store the value to element #0,
1778 // then load the whole vector back out.
1779 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0));
1781 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr);
1782 int SPFI = StackPtrFI->getIndex();
1784 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0),
1786 PseudoSourceValue::getFixedStack(SPFI), 0,
1787 Node->getValueType(0).getVectorElementType());
1788 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr,
1789 PseudoSourceValue::getFixedStack(SPFI), 0);
1793 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't
1794 /// support the operation, but do support the resultant vector type.
1795 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
1796 unsigned NumElems = Node->getNumOperands();
1797 SDValue Value1, Value2;
1798 DebugLoc dl = Node->getDebugLoc();
1799 MVT VT = Node->getValueType(0);
1800 MVT OpVT = Node->getOperand(0).getValueType();
1801 MVT EltVT = VT.getVectorElementType();
1803 // If the only non-undef value is the low element, turn this into a
1804 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
1805 bool isOnlyLowElement = true;
1806 bool MoreThanTwoValues = false;
1807 bool isConstant = true;
1808 for (unsigned i = 0; i < NumElems; ++i) {
1809 SDValue V = Node->getOperand(i);
1810 if (V.getOpcode() == ISD::UNDEF)
1813 isOnlyLowElement = false;
1814 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
1817 if (!Value1.getNode()) {
1819 } else if (!Value2.getNode()) {
1822 } else if (V != Value1 && V != Value2) {
1823 MoreThanTwoValues = true;
1827 if (!Value1.getNode())
1828 return DAG.getUNDEF(VT);
1830 if (isOnlyLowElement)
1831 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1833 // If all elements are constants, create a load from the constant pool.
1835 std::vector<Constant*> CV;
1836 for (unsigned i = 0, e = NumElems; i != e; ++i) {
1837 if (ConstantFPSDNode *V =
1838 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
1839 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
1840 } else if (ConstantSDNode *V =
1841 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
1842 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
1844 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
1845 const Type *OpNTy = OpVT.getTypeForMVT(*DAG.getContext());
1846 CV.push_back(UndefValue::get(OpNTy));
1849 Constant *CP = ConstantVector::get(CV);
1850 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy());
1851 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
1852 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1853 PseudoSourceValue::getConstantPool(), 0,
1857 if (!MoreThanTwoValues) {
1858 SmallVector<int, 8> ShuffleVec(NumElems, -1);
1859 for (unsigned i = 0; i < NumElems; ++i) {
1860 SDValue V = Node->getOperand(i);
1861 if (V.getOpcode() == ISD::UNDEF)
1863 ShuffleVec[i] = V == Value1 ? 0 : NumElems;
1865 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) {
1866 // Get the splatted value into the low element of a vector register.
1867 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1869 if (Value2.getNode())
1870 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1872 Vec2 = DAG.getUNDEF(VT);
1874 // Return shuffle(LowValVec, undef, <0,0,0,0>)
1875 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
1879 // Otherwise, we can't handle this case efficiently.
1880 return ExpandVectorBuildThroughStack(Node);
1883 // ExpandLibCall - Expand a node into a call to a libcall. If the result value
1884 // does not fit into a register, return the lo part and set the hi part to the
1885 // by-reg argument. If it does fit into a single register, return the result
1886 // and leave the Hi part unset.
1887 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
1889 assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
1890 // The input chain to this libcall is the entry node of the function.
1891 // Legalizing the call will automatically add the previous call to the
1893 SDValue InChain = DAG.getEntryNode();
1895 TargetLowering::ArgListTy Args;
1896 TargetLowering::ArgListEntry Entry;
1897 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
1898 MVT ArgVT = Node->getOperand(i).getValueType();
1899 const Type *ArgTy = ArgVT.getTypeForMVT(*DAG.getContext());
1900 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
1901 Entry.isSExt = isSigned;
1902 Entry.isZExt = !isSigned;
1903 Args.push_back(Entry);
1905 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
1906 TLI.getPointerTy());
1908 // Splice the libcall in wherever FindInputOutputChains tells us to.
1909 const Type *RetTy = Node->getValueType(0).getTypeForMVT(*DAG.getContext());
1910 std::pair<SDValue, SDValue> CallInfo =
1911 TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
1912 0, CallingConv::C, false, Callee, Args, DAG,
1913 Node->getDebugLoc());
1915 // Legalize the call sequence, starting with the chain. This will advance
1916 // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that
1917 // was added by LowerCallTo (guaranteeing proper serialization of calls).
1918 LegalizeOp(CallInfo.second);
1919 return CallInfo.first;
1922 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
1923 RTLIB::Libcall Call_F32,
1924 RTLIB::Libcall Call_F64,
1925 RTLIB::Libcall Call_F80,
1926 RTLIB::Libcall Call_PPCF128) {
1928 switch (Node->getValueType(0).getSimpleVT()) {
1929 default: assert(0 && "Unexpected request for libcall!");
1930 case MVT::f32: LC = Call_F32; break;
1931 case MVT::f64: LC = Call_F64; break;
1932 case MVT::f80: LC = Call_F80; break;
1933 case MVT::ppcf128: LC = Call_PPCF128; break;
1935 return ExpandLibCall(LC, Node, false);
1938 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
1939 RTLIB::Libcall Call_I16,
1940 RTLIB::Libcall Call_I32,
1941 RTLIB::Libcall Call_I64,
1942 RTLIB::Libcall Call_I128) {
1944 switch (Node->getValueType(0).getSimpleVT()) {
1945 default: assert(0 && "Unexpected request for libcall!");
1946 case MVT::i16: LC = Call_I16; break;
1947 case MVT::i32: LC = Call_I32; break;
1948 case MVT::i64: LC = Call_I64; break;
1949 case MVT::i128: LC = Call_I128; break;
1951 return ExpandLibCall(LC, Node, isSigned);
1954 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a
1955 /// INT_TO_FP operation of the specified operand when the target requests that
1956 /// we expand it. At this point, we know that the result and operand types are
1957 /// legal for the target.
1958 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
1962 if (Op0.getValueType() == MVT::i32) {
1963 // simple 32-bit [signed|unsigned] integer to float/double expansion
1965 // Get the stack frame index of a 8 byte buffer.
1966 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
1968 // word offset constant for Hi/Lo address computation
1969 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
1970 // set up Hi and Lo (into buffer) address based on endian
1971 SDValue Hi = StackSlot;
1972 SDValue Lo = DAG.getNode(ISD::ADD, dl,
1973 TLI.getPointerTy(), StackSlot, WordOff);
1974 if (TLI.isLittleEndian())
1977 // if signed map to unsigned space
1980 // constant used to invert sign bit (signed to unsigned mapping)
1981 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1982 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
1986 // store the lo of the constructed double - based on integer input
1987 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
1988 Op0Mapped, Lo, NULL, 0);
1989 // initial hi portion of constructed double
1990 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
1991 // store the hi of the constructed double - biased exponent
1992 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
1993 // load the constructed double
1994 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
1995 // FP constant to bias correct the final result
1996 SDValue Bias = DAG.getConstantFP(isSigned ?
1997 BitsToDouble(0x4330000080000000ULL) :
1998 BitsToDouble(0x4330000000000000ULL),
2000 // subtract the bias
2001 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
2004 // handle final rounding
2005 if (DestVT == MVT::f64) {
2008 } else if (DestVT.bitsLT(MVT::f64)) {
2009 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
2010 DAG.getIntPtrConstant(0));
2011 } else if (DestVT.bitsGT(MVT::f64)) {
2012 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
2016 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet");
2017 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
2019 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()),
2020 Op0, DAG.getConstant(0, Op0.getValueType()),
2022 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4);
2023 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(),
2024 SignSet, Four, Zero);
2026 // If the sign bit of the integer is set, the large number will be treated
2027 // as a negative number. To counteract this, the dynamic code adds an
2028 // offset depending on the data type.
2030 switch (Op0.getValueType().getSimpleVT()) {
2031 default: assert(0 && "Unsupported integer type!");
2032 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
2033 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
2034 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
2035 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
2037 if (TLI.isLittleEndian()) FF <<= 32;
2038 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
2040 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy());
2041 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();
2042 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
2043 Alignment = std::min(Alignment, 4u);
2045 if (DestVT == MVT::f32)
2046 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
2047 PseudoSourceValue::getConstantPool(), 0,
2051 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
2052 DAG.getEntryNode(), CPIdx,
2053 PseudoSourceValue::getConstantPool(), 0,
2054 MVT::f32, false, Alignment));
2057 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
2060 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a
2061 /// *INT_TO_FP operation of the specified operand when the target requests that
2062 /// we promote it. At this point, we know that the result and operand types are
2063 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
2064 /// operation that takes a larger input.
2065 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
2069 // First step, figure out the appropriate *INT_TO_FP operation to use.
2070 MVT NewInTy = LegalOp.getValueType();
2072 unsigned OpToUse = 0;
2074 // Scan for the appropriate larger type to use.
2076 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2077 assert(NewInTy.isInteger() && "Ran out of possibilities!");
2079 // If the target supports SINT_TO_FP of this type, use it.
2080 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) {
2081 OpToUse = ISD::SINT_TO_FP;
2084 if (isSigned) continue;
2086 // If the target supports UINT_TO_FP of this type, use it.
2087 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) {
2088 OpToUse = ISD::UINT_TO_FP;
2092 // Otherwise, try a larger type.
2095 // Okay, we found the operation and type to use. Zero extend our input to the
2096 // desired type then run the operation on it.
2097 return DAG.getNode(OpToUse, dl, DestVT,
2098 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
2099 dl, NewInTy, LegalOp));
2102 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a
2103 /// FP_TO_*INT operation of the specified operand when the target requests that
2104 /// we promote it. At this point, we know that the result and operand types are
2105 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
2106 /// operation that returns a larger result.
2107 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
2111 // First step, figure out the appropriate FP_TO*INT operation to use.
2112 MVT NewOutTy = DestVT;
2114 unsigned OpToUse = 0;
2116 // Scan for the appropriate larger type to use.
2118 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
2119 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
2121 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
2122 OpToUse = ISD::FP_TO_SINT;
2126 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) {
2127 OpToUse = ISD::FP_TO_UINT;
2131 // Otherwise, try a larger type.
2135 // Okay, we found the operation and type to use.
2136 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp);
2138 // Truncate the result of the extended FP_TO_*INT operation to the desired
2140 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation);
2143 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
2145 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
2146 MVT VT = Op.getValueType();
2147 MVT SHVT = TLI.getShiftAmountTy();
2148 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2149 switch (VT.getSimpleVT()) {
2150 default: assert(0 && "Unhandled Expand type in BSWAP!"); abort();
2152 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2153 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2154 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2156 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2157 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2158 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2159 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2160 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2161 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2162 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2163 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2164 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2166 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2167 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2168 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2169 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2170 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2171 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2172 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2173 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2174 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2175 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2176 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2177 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2178 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2179 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2180 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2181 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2182 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2183 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2184 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2185 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2186 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2190 /// ExpandBitCount - Expand the specified bitcount instruction into operations.
2192 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op,
2195 default: assert(0 && "Cannot expand this yet!");
2197 static const uint64_t mask[6] = {
2198 0x5555555555555555ULL, 0x3333333333333333ULL,
2199 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
2200 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
2202 MVT VT = Op.getValueType();
2203 MVT ShVT = TLI.getShiftAmountTy();
2204 unsigned len = VT.getSizeInBits();
2205 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2206 //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
2207 unsigned EltSize = VT.isVector() ?
2208 VT.getVectorElementType().getSizeInBits() : len;
2209 SDValue Tmp2 = DAG.getConstant(APInt(EltSize, mask[i]), VT);
2210 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2211 Op = DAG.getNode(ISD::ADD, dl, VT,
2212 DAG.getNode(ISD::AND, dl, VT, Op, Tmp2),
2213 DAG.getNode(ISD::AND, dl, VT,
2214 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3),
2220 // for now, we do this:
2221 // x = x | (x >> 1);
2222 // x = x | (x >> 2);
2224 // x = x | (x >>16);
2225 // x = x | (x >>32); // for 64-bit input
2226 // return popcount(~x);
2228 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc
2229 MVT VT = Op.getValueType();
2230 MVT ShVT = TLI.getShiftAmountTy();
2231 unsigned len = VT.getSizeInBits();
2232 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
2233 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
2234 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2235 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2237 Op = DAG.getNOT(dl, Op, VT);
2238 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2241 // for now, we use: { return popcount(~x & (x - 1)); }
2242 // unless the target has ctlz but not ctpop, in which case we use:
2243 // { return 32 - nlz(~x & (x-1)); }
2244 // see also http://www.hackersdelight.org/HDcode/ntz.cc
2245 MVT VT = Op.getValueType();
2246 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2247 DAG.getNOT(dl, Op, VT),
2248 DAG.getNode(ISD::SUB, dl, VT, Op,
2249 DAG.getConstant(1, VT)));
2250 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead.
2251 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2252 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2253 return DAG.getNode(ISD::SUB, dl, VT,
2254 DAG.getConstant(VT.getSizeInBits(), VT),
2255 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2256 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2261 void SelectionDAGLegalize::ExpandNode(SDNode *Node,
2262 SmallVectorImpl<SDValue> &Results) {
2263 DebugLoc dl = Node->getDebugLoc();
2264 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
2265 switch (Node->getOpcode()) {
2269 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl);
2270 Results.push_back(Tmp1);
2273 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl));
2275 case ISD::FRAMEADDR:
2276 case ISD::RETURNADDR:
2277 case ISD::FRAME_TO_ARGS_OFFSET:
2278 Results.push_back(DAG.getConstant(0, Node->getValueType(0)));
2280 case ISD::FLT_ROUNDS_:
2281 Results.push_back(DAG.getConstant(1, Node->getValueType(0)));
2283 case ISD::EH_RETURN:
2285 case ISD::DBG_LABEL:
2288 case ISD::MEMBARRIER:
2290 Results.push_back(Node->getOperand(0));
2292 case ISD::DBG_STOPPOINT:
2293 Results.push_back(ExpandDBG_STOPPOINT(Node));
2295 case ISD::DYNAMIC_STACKALLOC:
2296 ExpandDYNAMIC_STACKALLOC(Node, Results);
2298 case ISD::MERGE_VALUES:
2299 for (unsigned i = 0; i < Node->getNumValues(); i++)
2300 Results.push_back(Node->getOperand(i));
2303 MVT VT = Node->getValueType(0);
2305 Results.push_back(DAG.getConstant(0, VT));
2306 else if (VT.isFloatingPoint())
2307 Results.push_back(DAG.getConstantFP(0, VT));
2309 assert(0 && "Unknown value type!");
2313 // If this operation is not supported, lower it to 'abort()' call
2314 TargetLowering::ArgListTy Args;
2315 std::pair<SDValue, SDValue> CallResult =
2316 TLI.LowerCallTo(Node->getOperand(0), Type::VoidTy,
2317 false, false, false, false, 0, CallingConv::C, false,
2318 DAG.getExternalSymbol("abort", TLI.getPointerTy()),
2320 Results.push_back(CallResult.second);
2324 case ISD::BIT_CONVERT:
2325 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0),
2326 Node->getValueType(0), dl);
2327 Results.push_back(Tmp1);
2329 case ISD::FP_EXTEND:
2330 Tmp1 = EmitStackConvert(Node->getOperand(0),
2331 Node->getOperand(0).getValueType(),
2332 Node->getValueType(0), dl);
2333 Results.push_back(Tmp1);
2335 case ISD::SIGN_EXTEND_INREG: {
2336 // NOTE: we could fall back on load/store here too for targets without
2337 // SAR. However, it is doubtful that any exist.
2338 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2339 unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
2340 ExtraVT.getSizeInBits();
2341 SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
2342 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0),
2343 Node->getOperand(0), ShiftCst);
2344 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst);
2345 Results.push_back(Tmp1);
2348 case ISD::FP_ROUND_INREG: {
2349 // The only way we can lower this is to turn it into a TRUNCSTORE,
2350 // EXTLOAD pair, targetting a temporary location (a stack slot).
2352 // NOTE: there is a choice here between constantly creating new stack
2353 // slots and always reusing the same one. We currently always create
2354 // new ones, as reuse may inhibit scheduling.
2355 MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
2356 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2357 Node->getValueType(0), dl);
2358 Results.push_back(Tmp1);
2361 case ISD::SINT_TO_FP:
2362 case ISD::UINT_TO_FP:
2363 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP,
2364 Node->getOperand(0), Node->getValueType(0), dl);
2365 Results.push_back(Tmp1);
2367 case ISD::FP_TO_UINT: {
2368 SDValue True, False;
2369 MVT VT = Node->getOperand(0).getValueType();
2370 MVT NVT = Node->getValueType(0);
2371 const uint64_t zero[] = {0, 0};
2372 APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
2373 APInt x = APInt::getSignBit(NVT.getSizeInBits());
2374 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven);
2375 Tmp1 = DAG.getConstantFP(apf, VT);
2376 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2377 Node->getOperand(0),
2379 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0));
2380 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT,
2381 DAG.getNode(ISD::FSUB, dl, VT,
2382 Node->getOperand(0), Tmp1));
2383 False = DAG.getNode(ISD::XOR, dl, NVT, False,
2384 DAG.getConstant(x, NVT));
2385 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False);
2386 Results.push_back(Tmp1);
2390 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2391 MVT VT = Node->getValueType(0);
2392 Tmp1 = Node->getOperand(0);
2393 Tmp2 = Node->getOperand(1);
2394 SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
2395 // Increment the pointer, VAList, to the next vaarg
2396 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
2397 DAG.getConstant(TLI.getTargetData()->
2398 getTypeAllocSize(VT.getTypeForMVT(
2399 *DAG.getContext())),
2400 TLI.getPointerTy()));
2401 // Store the incremented VAList to the legalized pointer
2402 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
2403 // Load the actual argument out of the pointer VAList
2404 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0));
2405 Results.push_back(Results[0].getValue(1));
2409 // This defaults to loading a pointer from the input and storing it to the
2410 // output, returning the chain.
2411 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2412 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2413 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0),
2414 Node->getOperand(2), VS, 0);
2415 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), VD, 0);
2416 Results.push_back(Tmp1);
2419 case ISD::EXTRACT_VECTOR_ELT:
2420 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1)
2421 // This must be an access of the only element. Return it.
2422 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
2423 Node->getOperand(0));
2425 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0));
2426 Results.push_back(Tmp1);
2428 case ISD::EXTRACT_SUBVECTOR:
2429 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0)));
2431 case ISD::CONCAT_VECTORS: {
2432 Results.push_back(ExpandVectorBuildThroughStack(Node));
2435 case ISD::SCALAR_TO_VECTOR:
2436 Results.push_back(ExpandSCALAR_TO_VECTOR(Node));
2438 case ISD::INSERT_VECTOR_ELT:
2439 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0),
2440 Node->getOperand(1),
2441 Node->getOperand(2), dl));
2443 case ISD::VECTOR_SHUFFLE: {
2444 SmallVector<int, 8> Mask;
2445 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
2447 MVT VT = Node->getValueType(0);
2448 MVT EltVT = VT.getVectorElementType();
2449 unsigned NumElems = VT.getVectorNumElements();
2450 SmallVector<SDValue, 8> Ops;
2451 for (unsigned i = 0; i != NumElems; ++i) {
2453 Ops.push_back(DAG.getUNDEF(EltVT));
2456 unsigned Idx = Mask[i];
2458 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2459 Node->getOperand(0),
2460 DAG.getIntPtrConstant(Idx)));
2462 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
2463 Node->getOperand(1),
2464 DAG.getIntPtrConstant(Idx - NumElems)));
2466 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
2467 Results.push_back(Tmp1);
2470 case ISD::EXTRACT_ELEMENT: {
2471 MVT OpTy = Node->getOperand(0).getValueType();
2472 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
2474 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
2475 DAG.getConstant(OpTy.getSizeInBits()/2,
2476 TLI.getShiftAmountTy()));
2477 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1);
2480 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0),
2481 Node->getOperand(0));
2483 Results.push_back(Tmp1);
2486 case ISD::STACKSAVE:
2487 // Expand to CopyFromReg if the target set
2488 // StackPointerRegisterToSaveRestore.
2489 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2490 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP,
2491 Node->getValueType(0)));
2492 Results.push_back(Results[0].getValue(1));
2494 Results.push_back(DAG.getUNDEF(Node->getValueType(0)));
2495 Results.push_back(Node->getOperand(0));
2498 case ISD::STACKRESTORE:
2499 // Expand to CopyToReg if the target set
2500 // StackPointerRegisterToSaveRestore.
2501 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) {
2502 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP,
2503 Node->getOperand(1)));
2505 Results.push_back(Node->getOperand(0));
2508 case ISD::FCOPYSIGN:
2509 Results.push_back(ExpandFCOPYSIGN(Node));
2512 // Expand Y = FNEG(X) -> Y = SUB -0.0, X
2513 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0));
2514 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1,
2515 Node->getOperand(0));
2516 Results.push_back(Tmp1);
2519 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
2520 MVT VT = Node->getValueType(0);
2521 Tmp1 = Node->getOperand(0);
2522 Tmp2 = DAG.getConstantFP(0.0, VT);
2523 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2524 Tmp1, Tmp2, ISD::SETUGT);
2525 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
2526 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
2527 Results.push_back(Tmp1);
2531 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64,
2532 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128));
2535 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64,
2536 RTLIB::SIN_F80, RTLIB::SIN_PPCF128));
2539 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64,
2540 RTLIB::COS_F80, RTLIB::COS_PPCF128));
2543 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64,
2544 RTLIB::LOG_F80, RTLIB::LOG_PPCF128));
2547 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64,
2548 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128));
2551 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64,
2552 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128));
2555 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64,
2556 RTLIB::EXP_F80, RTLIB::EXP_PPCF128));
2559 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64,
2560 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128));
2563 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64,
2564 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128));
2567 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64,
2568 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128));
2571 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64,
2572 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128));
2575 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64,
2576 RTLIB::RINT_F80, RTLIB::RINT_PPCF128));
2578 case ISD::FNEARBYINT:
2579 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32,
2580 RTLIB::NEARBYINT_F64,
2581 RTLIB::NEARBYINT_F80,
2582 RTLIB::NEARBYINT_PPCF128));
2585 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64,
2586 RTLIB::POWI_F80, RTLIB::POWI_PPCF128));
2589 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64,
2590 RTLIB::POW_F80, RTLIB::POW_PPCF128));
2593 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64,
2594 RTLIB::DIV_F80, RTLIB::DIV_PPCF128));
2597 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64,
2598 RTLIB::REM_F80, RTLIB::REM_PPCF128));
2600 case ISD::ConstantFP: {
2601 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node);
2602 // Check to see if this FP immediate is already legal.
2603 bool isLegal = false;
2604 for (TargetLowering::legal_fpimm_iterator I = TLI.legal_fpimm_begin(),
2605 E = TLI.legal_fpimm_end(); I != E; ++I) {
2606 if (CFP->isExactlyValue(*I)) {
2611 // If this is a legal constant, turn it into a TargetConstantFP node.
2613 Results.push_back(SDValue(Node, 0));
2615 Results.push_back(ExpandConstantFP(CFP, true, DAG, TLI));
2618 case ISD::EHSELECTION: {
2619 unsigned Reg = TLI.getExceptionSelectorRegister();
2620 assert(Reg && "Can't expand to unknown register!");
2621 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg,
2622 Node->getValueType(0)));
2623 Results.push_back(Results[0].getValue(1));
2626 case ISD::EXCEPTIONADDR: {
2627 unsigned Reg = TLI.getExceptionAddressRegister();
2628 assert(Reg && "Can't expand to unknown register!");
2629 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg,
2630 Node->getValueType(0)));
2631 Results.push_back(Results[0].getValue(1));
2635 MVT VT = Node->getValueType(0);
2636 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
2637 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
2638 "Don't know how to expand this subtraction!");
2639 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
2640 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
2641 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp2, DAG.getConstant(1, VT));
2642 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
2647 MVT VT = Node->getValueType(0);
2648 SDVTList VTs = DAG.getVTList(VT, VT);
2649 bool isSigned = Node->getOpcode() == ISD::SREM;
2650 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
2651 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2652 Tmp2 = Node->getOperand(0);
2653 Tmp3 = Node->getOperand(1);
2654 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) {
2655 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1);
2656 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
2658 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
2659 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
2660 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
2661 } else if (isSigned) {
2662 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SREM_I16, RTLIB::SREM_I32,
2663 RTLIB::SREM_I64, RTLIB::SREM_I128);
2665 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UREM_I16, RTLIB::UREM_I32,
2666 RTLIB::UREM_I64, RTLIB::UREM_I128);
2668 Results.push_back(Tmp1);
2673 bool isSigned = Node->getOpcode() == ISD::SDIV;
2674 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
2675 MVT VT = Node->getValueType(0);
2676 SDVTList VTs = DAG.getVTList(VT, VT);
2677 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
2678 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
2679 Node->getOperand(1));
2681 Tmp1 = ExpandIntLibCall(Node, true, RTLIB::SDIV_I16, RTLIB::SDIV_I32,
2682 RTLIB::SDIV_I64, RTLIB::SDIV_I128);
2684 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::UDIV_I16, RTLIB::UDIV_I32,
2685 RTLIB::UDIV_I64, RTLIB::UDIV_I128);
2686 Results.push_back(Tmp1);
2691 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
2693 MVT VT = Node->getValueType(0);
2694 SDVTList VTs = DAG.getVTList(VT, VT);
2695 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
2696 "If this wasn't legal, it shouldn't have been created!");
2697 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0),
2698 Node->getOperand(1));
2699 Results.push_back(Tmp1.getValue(1));
2703 MVT VT = Node->getValueType(0);
2704 SDVTList VTs = DAG.getVTList(VT, VT);
2705 // See if multiply or divide can be lowered using two-result operations.
2706 // We just need the low half of the multiply; try both the signed
2707 // and unsigned forms. If the target supports both SMUL_LOHI and
2708 // UMUL_LOHI, form a preference by checking which forms of plain
2709 // MULH it supports.
2710 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
2711 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
2712 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
2713 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
2714 unsigned OpToUse = 0;
2715 if (HasSMUL_LOHI && !HasMULHS) {
2716 OpToUse = ISD::SMUL_LOHI;
2717 } else if (HasUMUL_LOHI && !HasMULHU) {
2718 OpToUse = ISD::UMUL_LOHI;
2719 } else if (HasSMUL_LOHI) {
2720 OpToUse = ISD::SMUL_LOHI;
2721 } else if (HasUMUL_LOHI) {
2722 OpToUse = ISD::UMUL_LOHI;
2725 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0),
2726 Node->getOperand(1)));
2729 Tmp1 = ExpandIntLibCall(Node, false, RTLIB::MUL_I16, RTLIB::MUL_I32,
2730 RTLIB::MUL_I64, RTLIB::MUL_I128);
2731 Results.push_back(Tmp1);
2736 SDValue LHS = Node->getOperand(0);
2737 SDValue RHS = Node->getOperand(1);
2738 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ?
2739 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2741 Results.push_back(Sum);
2742 MVT OType = Node->getValueType(1);
2744 SDValue Zero = DAG.getConstant(0, LHS.getValueType());
2746 // LHSSign -> LHS >= 0
2747 // RHSSign -> RHS >= 0
2748 // SumSign -> Sum >= 0
2751 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign)
2753 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign)
2755 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE);
2756 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE);
2757 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign,
2758 Node->getOpcode() == ISD::SADDO ?
2759 ISD::SETEQ : ISD::SETNE);
2761 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE);
2762 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE);
2764 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE);
2765 Results.push_back(Cmp);
2770 SDValue LHS = Node->getOperand(0);
2771 SDValue RHS = Node->getOperand(1);
2772 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ?
2773 ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
2775 Results.push_back(Sum);
2776 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS,
2777 Node->getOpcode () == ISD::UADDO ?
2778 ISD::SETULT : ISD::SETUGT));
2783 MVT VT = Node->getValueType(0);
2784 SDValue LHS = Node->getOperand(0);
2785 SDValue RHS = Node->getOperand(1);
2788 static unsigned Ops[2][3] =
2789 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND },
2790 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }};
2791 bool isSigned = Node->getOpcode() == ISD::SMULO;
2792 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
2793 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
2794 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
2795 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
2796 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
2798 TopHalf = BottomHalf.getValue(1);
2799 } else if (TLI.isTypeLegal(MVT::getIntegerVT(VT.getSizeInBits() * 2))) {
2800 MVT WideVT = MVT::getIntegerVT(VT.getSizeInBits() * 2);
2801 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
2802 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
2803 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
2804 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2805 DAG.getIntPtrConstant(0));
2806 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
2807 DAG.getIntPtrConstant(1));
2809 // FIXME: We should be able to fall back to a libcall with an illegal
2810 // type in some cases cases.
2811 // Also, we can fall back to a division in some cases, but that's a big
2812 // performance hit in the general case.
2813 assert(0 && "Don't know how to expand this operation yet!");
2816 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy());
2817 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
2818 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
2821 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
2822 DAG.getConstant(0, VT), ISD::SETNE);
2824 Results.push_back(BottomHalf);
2825 Results.push_back(TopHalf);
2828 case ISD::BUILD_PAIR: {
2829 MVT PairTy = Node->getValueType(0);
2830 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
2831 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
2832 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
2833 DAG.getConstant(PairTy.getSizeInBits()/2,
2834 TLI.getShiftAmountTy()));
2835 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2));
2839 Tmp1 = Node->getOperand(0);
2840 Tmp2 = Node->getOperand(1);
2841 Tmp3 = Node->getOperand(2);
2842 if (Tmp1.getOpcode() == ISD::SETCC) {
2843 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1),
2845 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get());
2847 Tmp1 = DAG.getSelectCC(dl, Tmp1,
2848 DAG.getConstant(0, Tmp1.getValueType()),
2849 Tmp2, Tmp3, ISD::SETNE);
2851 Results.push_back(Tmp1);
2854 SDValue Chain = Node->getOperand(0);
2855 SDValue Table = Node->getOperand(1);
2856 SDValue Index = Node->getOperand(2);
2858 MVT PTy = TLI.getPointerTy();
2859 MachineFunction &MF = DAG.getMachineFunction();
2860 unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
2861 Index= DAG.getNode(ISD::MUL, dl, PTy,
2862 Index, DAG.getConstant(EntrySize, PTy));
2863 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2865 MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
2866 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
2867 PseudoSourceValue::getJumpTable(), 0, MemVT);
2869 if (TLI.getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2870 // For PIC, the sequence is:
2871 // BRIND(load(Jumptable + index) + RelocBase)
2872 // RelocBase can be JumpTable, GOT or some sort of global base.
2873 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
2874 TLI.getPICJumpTableRelocBase(Table, DAG));
2876 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
2877 Results.push_back(Tmp1);
2881 // Expand brcond's setcc into its constituent parts and create a BR_CC
2883 Tmp1 = Node->getOperand(0);
2884 Tmp2 = Node->getOperand(1);
2885 if (Tmp2.getOpcode() == ISD::SETCC) {
2886 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
2887 Tmp1, Tmp2.getOperand(2),
2888 Tmp2.getOperand(0), Tmp2.getOperand(1),
2889 Node->getOperand(2));
2891 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
2892 DAG.getCondCode(ISD::SETNE), Tmp2,
2893 DAG.getConstant(0, Tmp2.getValueType()),
2894 Node->getOperand(2));
2896 Results.push_back(Tmp1);
2899 Tmp1 = Node->getOperand(0);
2900 Tmp2 = Node->getOperand(1);
2901 Tmp3 = Node->getOperand(2);
2902 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl);
2904 // If we expanded the SETCC into an AND/OR, return the new node
2905 if (Tmp2.getNode() == 0) {
2906 Results.push_back(Tmp1);
2910 // Otherwise, SETCC for the given comparison type must be completely
2911 // illegal; expand it into a SELECT_CC.
2912 MVT VT = Node->getValueType(0);
2913 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
2914 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
2915 Results.push_back(Tmp1);
2918 case ISD::SELECT_CC: {
2919 Tmp1 = Node->getOperand(0); // LHS
2920 Tmp2 = Node->getOperand(1); // RHS
2921 Tmp3 = Node->getOperand(2); // True
2922 Tmp4 = Node->getOperand(3); // False
2923 SDValue CC = Node->getOperand(4);
2925 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()),
2926 Tmp1, Tmp2, CC, dl);
2928 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!");
2929 Tmp2 = DAG.getConstant(0, Tmp1.getValueType());
2930 CC = DAG.getCondCode(ISD::SETNE);
2931 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2,
2933 Results.push_back(Tmp1);
2937 Tmp1 = Node->getOperand(0); // Chain
2938 Tmp2 = Node->getOperand(2); // LHS
2939 Tmp3 = Node->getOperand(3); // RHS
2940 Tmp4 = Node->getOperand(1); // CC
2942 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()),
2943 Tmp2, Tmp3, Tmp4, dl);
2944 LastCALLSEQ_END = DAG.getEntryNode();
2946 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!");
2947 Tmp3 = DAG.getConstant(0, Tmp2.getValueType());
2948 Tmp4 = DAG.getCondCode(ISD::SETNE);
2949 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2,
2950 Tmp3, Node->getOperand(4));
2951 Results.push_back(Tmp1);
2954 case ISD::GLOBAL_OFFSET_TABLE:
2955 case ISD::GlobalAddress:
2956 case ISD::GlobalTLSAddress:
2957 case ISD::ExternalSymbol:
2958 case ISD::ConstantPool:
2959 case ISD::JumpTable:
2960 case ISD::INTRINSIC_W_CHAIN:
2961 case ISD::INTRINSIC_WO_CHAIN:
2962 case ISD::INTRINSIC_VOID:
2963 // FIXME: Custom lowering for these operations shouldn't return null!
2964 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i)
2965 Results.push_back(SDValue(Node, i));
2969 void SelectionDAGLegalize::PromoteNode(SDNode *Node,
2970 SmallVectorImpl<SDValue> &Results) {
2971 MVT OVT = Node->getValueType(0);
2972 if (Node->getOpcode() == ISD::UINT_TO_FP ||
2973 Node->getOpcode() == ISD::SINT_TO_FP) {
2974 OVT = Node->getOperand(0).getValueType();
2976 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
2977 DebugLoc dl = Node->getDebugLoc();
2978 SDValue Tmp1, Tmp2, Tmp3;
2979 switch (Node->getOpcode()) {
2983 // Zero extend the argument.
2984 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0));
2985 // Perform the larger operation.
2986 Tmp1 = DAG.getNode(Node->getOpcode(), dl, Node->getValueType(0), Tmp1);
2987 if (Node->getOpcode() == ISD::CTTZ) {
2988 //if Tmp1 == sizeinbits(NVT) then Tmp1 = sizeinbits(Old VT)
2989 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
2990 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT),
2992 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2,
2993 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1);
2994 } else if (Node->getOpcode() == ISD::CTLZ) {
2995 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
2996 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1,
2997 DAG.getConstant(NVT.getSizeInBits() -
2998 OVT.getSizeInBits(), NVT));
3000 Results.push_back(Tmp1);
3003 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
3004 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Tmp1);
3005 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1);
3006 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1,
3007 DAG.getConstant(DiffBits, TLI.getShiftAmountTy()));
3008 Results.push_back(Tmp1);
3011 case ISD::FP_TO_UINT:
3012 case ISD::FP_TO_SINT:
3013 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0),
3014 Node->getOpcode() == ISD::FP_TO_SINT, dl);
3015 Results.push_back(Tmp1);
3017 case ISD::UINT_TO_FP:
3018 case ISD::SINT_TO_FP:
3019 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0),
3020 Node->getOpcode() == ISD::SINT_TO_FP, dl);
3021 Results.push_back(Tmp1);
3026 assert(OVT.isVector() && "Don't know how to promote scalar logic ops");
3027 // Bit convert each of the values to the new type.
3028 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3029 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3030 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2);
3031 // Bit convert the result back the original type.
3032 Results.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1));
3035 unsigned ExtOp, TruncOp;
3036 if (Node->getValueType(0).isVector()) {
3037 ExtOp = ISD::BIT_CONVERT;
3038 TruncOp = ISD::BIT_CONVERT;
3039 } else if (Node->getValueType(0).isInteger()) {
3040 ExtOp = ISD::ANY_EXTEND;
3041 TruncOp = ISD::TRUNCATE;
3043 ExtOp = ISD::FP_EXTEND;
3044 TruncOp = ISD::FP_ROUND;
3046 Tmp1 = Node->getOperand(0);
3047 // Promote each of the values to the new type.
3048 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1));
3049 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2));
3050 // Perform the larger operation, then round down.
3051 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3);
3052 if (TruncOp != ISD::FP_ROUND)
3053 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1);
3055 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1,
3056 DAG.getIntPtrConstant(0));
3057 Results.push_back(Tmp1);
3059 case ISD::VECTOR_SHUFFLE: {
3060 SmallVector<int, 8> Mask;
3061 cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
3063 // Cast the two input vectors.
3064 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(0));
3065 Tmp2 = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, Node->getOperand(1));
3067 // Convert the shuffle mask to the right # elements.
3068 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask);
3069 Tmp1 = DAG.getNode(ISD::BIT_CONVERT, dl, OVT, Tmp1);
3070 Results.push_back(Tmp1);
3074 // First step, figure out the appropriate operation to use.
3075 // Allow SETCC to not be supported for all legal data types
3076 // Mostly this targets FP
3077 MVT NewInTy = Node->getOperand(0).getValueType();
3078 MVT OldVT = NewInTy; OldVT = OldVT;
3080 // Scan for the appropriate larger type to use.
3082 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
3084 assert(NewInTy.isInteger() == OldVT.isInteger() &&
3085 "Fell off of the edge of the integer world");
3086 assert(NewInTy.isFloatingPoint() == OldVT.isFloatingPoint() &&
3087 "Fell off of the edge of the floating point world");
3089 // If the target supports SETCC of this type, use it.
3090 if (TLI.isOperationLegalOrCustom(ISD::SETCC, NewInTy))
3093 if (NewInTy.isInteger())
3094 assert(0 && "Cannot promote Legal Integer SETCC yet");
3096 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp1);
3097 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NewInTy, Tmp2);
3099 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0),
3100 Tmp1, Tmp2, Node->getOperand(2)));
3106 // SelectionDAG::Legalize - This is the entry point for the file.
3108 void SelectionDAG::Legalize(bool TypesNeedLegalizing,
3109 CodeGenOpt::Level OptLevel) {
3110 /// run - This is the main entry point to this class.
3112 SelectionDAGLegalize(*this, OptLevel).LegalizeDAG();