1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "SDNodeDbgValue.h"
19 #include "llvm/CodeGen/MachineConstantPool.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/Target/TargetData.h"
24 #include "llvm/Target/TargetMachine.h"
25 #include "llvm/Target/TargetInstrInfo.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/ADT/Statistic.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/MathExtras.h"
33 /// MinRCSize - Smallest register class we allow when constraining virtual
34 /// registers. If satisfying all register class constraints would require
35 /// using a smaller register class, emit a COPY to a new virtual register
37 const unsigned MinRCSize = 4;
39 /// CountResults - The results of target nodes have register or immediate
40 /// operands first, then an optional chain, and optional glue operands (which do
41 /// not go into the resulting MachineInstr).
42 unsigned InstrEmitter::CountResults(SDNode *Node) {
43 unsigned N = Node->getNumValues();
44 while (N && Node->getValueType(N - 1) == MVT::Glue)
46 if (N && Node->getValueType(N - 1) == MVT::Other)
47 --N; // Skip over chain result.
51 /// countOperands - The inputs to target nodes have any actual inputs first,
52 /// followed by an optional chain operand, then an optional glue operand.
53 /// Compute the number of actual operands that will go into the resulting
56 /// Also count physreg RegisterSDNode and RegisterMaskSDNode operands preceding
57 /// the chain and glue. These operands may be implicit on the machine instr.
58 static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
59 unsigned &NumImpUses) {
60 unsigned N = Node->getNumOperands();
61 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue)
63 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
64 --N; // Ignore chain if it exists.
66 // Count RegisterSDNode and RegisterMaskSDNode operands for NumImpUses.
67 NumImpUses = N - NumExpUses;
68 for (unsigned I = N; I > NumExpUses; --I) {
69 if (isa<RegisterMaskSDNode>(Node->getOperand(I - 1)))
71 if (RegisterSDNode *RN = dyn_cast<RegisterSDNode>(Node->getOperand(I - 1)))
72 if (TargetRegisterInfo::isPhysicalRegister(RN->getReg()))
81 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
82 /// implicit physical register output.
84 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
85 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
87 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
88 // Just use the input register directly!
89 SDValue Op(Node, ResNo);
92 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
93 (void)isNew; // Silence compiler warning.
94 assert(isNew && "Node emitted out of order - early");
98 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
99 // the CopyToReg'd destination register instead of creating a new vreg.
100 bool MatchReg = true;
101 const TargetRegisterClass *UseRC = NULL;
102 EVT VT = Node->getValueType(ResNo);
104 // Stick to the preferred register classes for legal types.
105 if (TLI->isTypeLegal(VT))
106 UseRC = TLI->getRegClassFor(VT);
108 if (!IsClone && !IsCloned)
109 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
113 if (User->getOpcode() == ISD::CopyToReg &&
114 User->getOperand(2).getNode() == Node &&
115 User->getOperand(2).getResNo() == ResNo) {
116 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
117 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
120 } else if (DestReg != SrcReg)
123 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
124 SDValue Op = User->getOperand(i);
125 if (Op.getNode() != Node || Op.getResNo() != ResNo)
127 EVT VT = Node->getValueType(Op.getResNo());
128 if (VT == MVT::Other || VT == MVT::Glue)
131 if (User->isMachineOpcode()) {
132 const MCInstrDesc &II = TII->get(User->getMachineOpcode());
133 const TargetRegisterClass *RC = 0;
134 if (i+II.getNumDefs() < II.getNumOperands()) {
135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
141 const TargetRegisterClass *ComRC =
142 TRI->getCommonSubClass(UseRC, RC);
143 // If multiple uses expect disjoint register classes, we emit
144 // copies in AddRegisterOperand.
156 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
159 // Figure out the register class to create for the destreg.
161 DstRC = MRI->getRegClass(VRBase);
163 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
166 DstRC = TLI->getRegClassFor(VT);
169 // If all uses are reading from the src physical register and copying the
170 // register is either impossible or very expensive, then don't create a copy.
171 if (MatchReg && SrcRC->getCopyCost() < 0) {
174 // Create the reg, emit the copy.
175 VRBase = MRI->createVirtualRegister(DstRC);
176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
177 VRBase).addReg(SrcReg);
180 SDValue Op(Node, ResNo);
183 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
184 (void)isNew; // Silence compiler warning.
185 assert(isNew && "Node emitted out of order - early");
188 /// getDstOfCopyToRegUse - If the only use of the specified result number of
189 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
190 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
191 unsigned ResNo) const {
192 if (!Node->hasOneUse())
195 SDNode *User = *Node->use_begin();
196 if (User->getOpcode() == ISD::CopyToReg &&
197 User->getOperand(2).getNode() == Node &&
198 User->getOperand(2).getResNo() == ResNo) {
199 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
200 if (TargetRegisterInfo::isVirtualRegister(Reg))
206 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
207 const MCInstrDesc &II,
208 bool IsClone, bool IsCloned,
209 DenseMap<SDValue, unsigned> &VRBaseMap) {
210 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
211 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
213 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
214 // If the specific node value is only used by a CopyToReg and the dest reg
215 // is a vreg in the same register class, use the CopyToReg'd destination
216 // register instead of creating a new vreg.
218 const TargetRegisterClass *RC =
219 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
220 if (II.OpInfo[i].isOptionalDef()) {
221 // Optional def must be a physical register.
222 unsigned NumResults = CountResults(Node);
223 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
224 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
225 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
228 if (!VRBase && !IsClone && !IsCloned)
229 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
232 if (User->getOpcode() == ISD::CopyToReg &&
233 User->getOperand(2).getNode() == Node &&
234 User->getOperand(2).getResNo() == i) {
235 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
236 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
237 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
240 MI->addOperand(MachineOperand::CreateReg(Reg, true));
247 // Create the result registers for this node and add the result regs to
248 // the machine instruction.
250 assert(RC && "Isn't a register operand!");
251 VRBase = MRI->createVirtualRegister(RC);
252 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
258 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
259 (void)isNew; // Silence compiler warning.
260 assert(isNew && "Node emitted out of order - early");
264 /// getVR - Return the virtual register corresponding to the specified result
265 /// of the specified node.
266 unsigned InstrEmitter::getVR(SDValue Op,
267 DenseMap<SDValue, unsigned> &VRBaseMap) {
268 if (Op.isMachineOpcode() &&
269 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270 // Add an IMPLICIT_DEF instruction before every use.
271 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
272 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
273 // does not include operand register class info.
275 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
276 VReg = MRI->createVirtualRegister(RC);
278 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
279 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
283 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
284 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
289 /// AddRegisterOperand - Add the specified register as an operand to the
290 /// specified machine instr. Insert register copies if the register is
291 /// not in the required register class.
293 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
295 const MCInstrDesc *II,
296 DenseMap<SDValue, unsigned> &VRBaseMap,
297 bool IsDebug, bool IsClone, bool IsCloned) {
298 assert(Op.getValueType() != MVT::Other &&
299 Op.getValueType() != MVT::Glue &&
300 "Chain and glue operands should occur at end of operand list!");
301 // Get/emit the operand.
302 unsigned VReg = getVR(Op, VRBaseMap);
303 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
305 const MCInstrDesc &MCID = MI->getDesc();
306 bool isOptDef = IIOpNum < MCID.getNumOperands() &&
307 MCID.OpInfo[IIOpNum].isOptionalDef();
309 // If the instruction requires a register in a different class, create
310 // a new virtual register and copy the value into it, but first attempt to
311 // shrink VReg's register class within reason. For example, if VReg == GR32
312 // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP.
314 const TargetRegisterClass *DstRC = 0;
315 if (IIOpNum < II->getNumOperands())
316 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
317 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
318 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
319 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
320 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
325 // If this value has only one use, that use is a kill. This is a
326 // conservative approximation. InstrEmitter does trivial coalescing
327 // with CopyFromReg nodes, so don't emit kill flags for them.
328 // Avoid kill flags on Schedule cloned nodes, since there will be
330 // Tied operands are never killed, so we need to check that. And that
331 // means we need to determine the index of the operand.
332 bool isKill = Op.hasOneUse() &&
333 Op.getNode()->getOpcode() != ISD::CopyFromReg &&
335 !(IsClone || IsCloned);
337 unsigned Idx = MI->getNumOperands();
339 MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit())
341 bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1;
346 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef,
347 false/*isImp*/, isKill,
348 false/*isDead*/, false/*isUndef*/,
349 false/*isEarlyClobber*/,
350 0/*SubReg*/, IsDebug));
353 /// AddOperand - Add the specified operand to the specified machine instr. II
354 /// specifies the instruction information for the node, and IIOpNum is the
355 /// operand number (in the II) that we are adding.
356 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
358 const MCInstrDesc *II,
359 DenseMap<SDValue, unsigned> &VRBaseMap,
360 bool IsDebug, bool IsClone, bool IsCloned) {
361 if (Op.isMachineOpcode()) {
362 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
363 IsDebug, IsClone, IsCloned);
364 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
365 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
366 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
367 const ConstantFP *CFP = F->getConstantFPValue();
368 MI->addOperand(MachineOperand::CreateFPImm(CFP));
369 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
370 // Turn additional physreg operands into implicit uses on non-variadic
371 // instructions. This is used by call and return instructions passing
372 // arguments in registers.
373 bool Imp = II && (IIOpNum >= II->getNumOperands() && !II->isVariadic());
374 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp));
375 } else if (RegisterMaskSDNode *RM = dyn_cast<RegisterMaskSDNode>(Op)) {
376 MI->addOperand(MachineOperand::CreateRegMask(RM->getRegMask()));
377 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
378 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
379 TGA->getTargetFlags()));
380 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
381 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
382 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
383 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
384 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
385 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
386 JT->getTargetFlags()));
387 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
388 int Offset = CP->getOffset();
389 unsigned Align = CP->getAlignment();
390 Type *Type = CP->getType();
391 // MachineConstantPool wants an explicit alignment.
393 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
395 // Alignment of vector types. FIXME!
396 Align = TM->getTargetData()->getTypeAllocSize(Type);
401 MachineConstantPool *MCP = MF->getConstantPool();
402 if (CP->isMachineConstantPoolEntry())
403 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
405 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
406 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
407 CP->getTargetFlags()));
408 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
409 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
410 ES->getTargetFlags()));
411 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
412 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
414 BA->getTargetFlags()));
415 } else if (TargetIndexSDNode *TI = dyn_cast<TargetIndexSDNode>(Op)) {
416 MI->addOperand(MachineOperand::CreateTargetIndex(TI->getIndex(),
418 TI->getTargetFlags()));
420 assert(Op.getValueType() != MVT::Other &&
421 Op.getValueType() != MVT::Glue &&
422 "Chain and glue operands should occur at end of operand list!");
423 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap,
424 IsDebug, IsClone, IsCloned);
428 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
429 EVT VT, DebugLoc DL) {
430 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
431 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
433 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
436 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
438 // VReg has been adjusted. It can be used with SubIdx operands now.
442 // VReg couldn't be reasonably constrained. Emit a COPY to a new virtual
444 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
445 assert(RC && "No legal register class for VT supports that SubIdx");
446 unsigned NewReg = MRI->createVirtualRegister(RC);
447 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
452 /// EmitSubregNode - Generate machine code for subreg nodes.
454 void InstrEmitter::EmitSubregNode(SDNode *Node,
455 DenseMap<SDValue, unsigned> &VRBaseMap,
456 bool IsClone, bool IsCloned) {
458 unsigned Opc = Node->getMachineOpcode();
460 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
461 // the CopyToReg'd destination register instead of creating a new vreg.
462 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
465 if (User->getOpcode() == ISD::CopyToReg &&
466 User->getOperand(2).getNode() == Node) {
467 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
468 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
475 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
476 // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
477 // constraints on the %dst register, COPY can target all legal register
479 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
480 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0));
482 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
483 MachineInstr *DefMI = MRI->getVRegDef(VReg);
484 unsigned SrcReg, DstReg, DefSubIdx;
486 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) &&
487 SubIdx == DefSubIdx &&
488 TRC == MRI->getRegClass(SrcReg)) {
490 // r1025 = s/zext r1024, 4
491 // r1026 = extract_subreg r1025, 4
493 // r1026 = copy r1024
494 VRBase = MRI->createVirtualRegister(TRC);
495 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
496 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
497 MRI->clearKillFlags(SrcReg);
499 // VReg may not support a SubIdx sub-register, and we may need to
500 // constrain its register class or issue a COPY to a compatible register
502 VReg = ConstrainForSubReg(VReg, SubIdx,
503 Node->getOperand(0).getValueType(),
504 Node->getDebugLoc());
506 // Create the destreg if it is missing.
508 VRBase = MRI->createVirtualRegister(TRC);
510 // Create the extract_subreg machine instruction.
511 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
512 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
514 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
515 Opc == TargetOpcode::SUBREG_TO_REG) {
516 SDValue N0 = Node->getOperand(0);
517 SDValue N1 = Node->getOperand(1);
518 SDValue N2 = Node->getOperand(2);
519 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
521 // Figure out the register class to create for the destreg. It should be
522 // the largest legal register class supporting SubIdx sub-registers.
523 // RegisterCoalescer will constrain it further if it decides to eliminate
524 // the INSERT_SUBREG instruction.
526 // %dst = INSERT_SUBREG %src, %sub, SubIdx
528 // is lowered by TwoAddressInstructionPass to:
531 // %dst:SubIdx = COPY %sub
533 // There is no constraint on the %src register class.
535 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0));
536 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
537 assert(SRC && "No register class supports VT and SubIdx for INSERT_SUBREG");
539 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
540 VRBase = MRI->createVirtualRegister(SRC);
542 // Create the insert_subreg or subreg_to_reg machine instruction.
543 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
544 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
546 // If creating a subreg_to_reg, then the first input operand
547 // is an implicit value immediate, otherwise it's a register
548 if (Opc == TargetOpcode::SUBREG_TO_REG) {
549 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
550 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
552 AddOperand(MI, N0, 0, 0, VRBaseMap, /*IsDebug=*/false,
554 // Add the subregster being inserted
555 AddOperand(MI, N1, 0, 0, VRBaseMap, /*IsDebug=*/false,
557 MI->addOperand(MachineOperand::CreateImm(SubIdx));
558 MBB->insert(InsertPos, MI);
560 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
563 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
564 (void)isNew; // Silence compiler warning.
565 assert(isNew && "Node emitted out of order - early");
568 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
569 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
570 /// register is constrained to be in a particular register class.
573 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
574 DenseMap<SDValue, unsigned> &VRBaseMap) {
575 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
577 // Create the new VReg in the destination class and emit a copy.
578 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
579 const TargetRegisterClass *DstRC =
580 TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
581 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
582 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
583 NewVReg).addReg(VReg);
586 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
587 (void)isNew; // Silence compiler warning.
588 assert(isNew && "Node emitted out of order - early");
591 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
593 void InstrEmitter::EmitRegSequence(SDNode *Node,
594 DenseMap<SDValue, unsigned> &VRBaseMap,
595 bool IsClone, bool IsCloned) {
596 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
597 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
598 unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
599 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
600 TII->get(TargetOpcode::REG_SEQUENCE), NewVReg);
601 unsigned NumOps = Node->getNumOperands();
602 assert((NumOps & 1) == 1 &&
603 "REG_SEQUENCE must have an odd number of operands!");
604 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
605 for (unsigned i = 1; i != NumOps; ++i) {
606 SDValue Op = Node->getOperand(i);
608 RegisterSDNode *R = dyn_cast<RegisterSDNode>(Node->getOperand(i-1));
609 // Skip physical registers as they don't have a vreg to get and we'll
610 // insert copies for them in TwoAddressInstructionPass anyway.
611 if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
612 unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
613 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
614 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
615 const TargetRegisterClass *SRC =
616 TRI->getMatchingSuperRegClass(RC, TRC, SubIdx);
617 if (SRC && SRC != RC) {
618 MRI->setRegClass(NewVReg, SRC);
623 AddOperand(MI, Op, i+1, &II, VRBaseMap, /*IsDebug=*/false,
627 MBB->insert(InsertPos, MI);
629 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
630 (void)isNew; // Silence compiler warning.
631 assert(isNew && "Node emitted out of order - early");
634 /// EmitDbgValue - Generate machine instruction for a dbg_value node.
637 InstrEmitter::EmitDbgValue(SDDbgValue *SD,
638 DenseMap<SDValue, unsigned> &VRBaseMap) {
639 uint64_t Offset = SD->getOffset();
640 MDNode* MDPtr = SD->getMDPtr();
641 DebugLoc DL = SD->getDebugLoc();
643 if (SD->getKind() == SDDbgValue::FRAMEIX) {
644 // Stack address; this needs to be lowered in target-dependent fashion.
645 // EmitTargetCodeForFrameDebugValue is responsible for allocation.
646 unsigned FrameIx = SD->getFrameIx();
647 return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL);
649 // Otherwise, we're going to create an instruction here.
650 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE);
651 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
652 if (SD->getKind() == SDDbgValue::SDNODE) {
653 SDNode *Node = SD->getSDNode();
654 SDValue Op = SDValue(Node, SD->getResNo());
655 // It's possible we replaced this SDNode with other(s) and therefore
656 // didn't generate code for it. It's better to catch these cases where
657 // they happen and transfer the debug info, but trying to guarantee that
658 // in all cases would be very fragile; this is a safeguard for any
660 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
661 if (I==VRBaseMap.end())
662 MIB.addReg(0U); // undef
664 AddOperand(&*MIB, Op, (*MIB).getNumOperands(), &II, VRBaseMap,
665 /*IsDebug=*/true, /*IsClone=*/false, /*IsCloned=*/false);
666 } else if (SD->getKind() == SDDbgValue::CONST) {
667 const Value *V = SD->getConst();
668 if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
669 if (CI->getBitWidth() > 64)
672 MIB.addImm(CI->getSExtValue());
673 } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
676 // Could be an Undef. In any case insert an Undef so we can see what we
681 // Insert an Undef so we can see what we dropped.
685 MIB.addImm(Offset).addMetadata(MDPtr);
689 /// EmitMachineNode - Generate machine code for a target-specific node and
690 /// needed dependencies.
693 EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
694 DenseMap<SDValue, unsigned> &VRBaseMap) {
695 unsigned Opc = Node->getMachineOpcode();
697 // Handle subreg insert/extract specially
698 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
699 Opc == TargetOpcode::INSERT_SUBREG ||
700 Opc == TargetOpcode::SUBREG_TO_REG) {
701 EmitSubregNode(Node, VRBaseMap, IsClone, IsCloned);
705 // Handle COPY_TO_REGCLASS specially.
706 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
707 EmitCopyToRegClassNode(Node, VRBaseMap);
711 // Handle REG_SEQUENCE specially.
712 if (Opc == TargetOpcode::REG_SEQUENCE) {
713 EmitRegSequence(Node, VRBaseMap, IsClone, IsCloned);
717 if (Opc == TargetOpcode::IMPLICIT_DEF)
718 // We want a unique VR for each IMPLICIT_DEF use.
721 const MCInstrDesc &II = TII->get(Opc);
722 unsigned NumResults = CountResults(Node);
723 unsigned NumImpUses = 0;
724 unsigned NodeOperands =
725 countOperands(Node, II.getNumOperands() - II.getNumDefs(), NumImpUses);
726 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0;
728 unsigned NumMIOperands = NodeOperands + NumResults;
730 assert(NumMIOperands >= II.getNumOperands() &&
731 "Too few operands for a variadic node!");
733 assert(NumMIOperands >= II.getNumOperands() &&
734 NumMIOperands <= II.getNumOperands() + II.getNumImplicitDefs() +
736 "#operands for dag node doesn't match .td file!");
739 // Create the new machine instruction.
740 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
742 // Add result register values for things that are defined by this
745 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
747 // Emit all of the actual operands of this instruction, adding them to the
748 // instruction as appropriate.
749 bool HasOptPRefs = II.getNumDefs() > NumResults;
750 assert((!HasOptPRefs || !HasPhysRegOuts) &&
751 "Unable to cope with optional defs and phys regs defs!");
752 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
753 for (unsigned i = NumSkip; i != NodeOperands; ++i)
754 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
755 VRBaseMap, /*IsDebug=*/false, IsClone, IsCloned);
757 // Transfer all of the memory reference descriptions of this instruction.
758 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
759 cast<MachineSDNode>(Node)->memoperands_end());
761 // Insert the instruction into position in the block. This needs to
762 // happen before any custom inserter hook is called so that the
763 // hook knows where in the block to insert the replacement code.
764 MBB->insert(InsertPos, MI);
766 // The MachineInstr may also define physregs instead of virtregs. These
767 // physreg values can reach other instructions in different ways:
769 // 1. When there is a use of a Node value beyond the explicitly defined
770 // virtual registers, we emit a CopyFromReg for one of the implicitly
771 // defined physregs. This only happens when HasPhysRegOuts is true.
773 // 2. A CopyFromReg reading a physreg may be glued to this instruction.
775 // 3. A glued instruction may implicitly use a physreg.
777 // 4. A glued instruction may use a RegisterSDNode operand.
779 // Collect all the used physreg defs, and make sure that any unused physreg
780 // defs are marked as dead.
781 SmallVector<unsigned, 8> UsedRegs;
783 // Additional results must be physical register defs.
784 if (HasPhysRegOuts) {
785 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
786 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
787 if (!Node->hasAnyUseOfValue(i))
789 // This implicitly defined physreg has a use.
790 UsedRegs.push_back(Reg);
791 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
795 // Scan the glue chain for any used physregs.
796 if (Node->getValueType(Node->getNumValues()-1) == MVT::Glue) {
797 for (SDNode *F = Node->getGluedUser(); F; F = F->getGluedUser()) {
798 if (F->getOpcode() == ISD::CopyFromReg) {
799 UsedRegs.push_back(cast<RegisterSDNode>(F->getOperand(1))->getReg());
801 } else if (F->getOpcode() == ISD::CopyToReg) {
802 // Skip CopyToReg nodes that are internal to the glue chain.
805 // Collect declared implicit uses.
806 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode());
807 UsedRegs.append(MCID.getImplicitUses(),
808 MCID.getImplicitUses() + MCID.getNumImplicitUses());
809 // In addition to declared implicit uses, we must also check for
810 // direct RegisterSDNode operands.
811 for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i)
812 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(F->getOperand(i))) {
813 unsigned Reg = R->getReg();
814 if (TargetRegisterInfo::isPhysicalRegister(Reg))
815 UsedRegs.push_back(Reg);
820 // Finally mark unused registers as dead.
821 if (!UsedRegs.empty() || II.getImplicitDefs())
822 MI->setPhysRegsDeadExcept(UsedRegs, *TRI);
824 // Run post-isel target hook to adjust this instruction if needed.
826 if (II.hasPostISelHook())
828 TLI->AdjustInstrPostInstrSelection(MI, Node);
831 /// EmitSpecialNode - Generate machine code for a target-independent node and
832 /// needed dependencies.
834 EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
835 DenseMap<SDValue, unsigned> &VRBaseMap) {
836 switch (Node->getOpcode()) {
841 llvm_unreachable("This target-independent node should have been selected!");
842 case ISD::EntryToken:
843 llvm_unreachable("EntryToken should have been excluded from the schedule!");
844 case ISD::MERGE_VALUES:
845 case ISD::TokenFactor: // fall thru
847 case ISD::CopyToReg: {
849 SDValue SrcVal = Node->getOperand(2);
850 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
851 SrcReg = R->getReg();
853 SrcReg = getVR(SrcVal, VRBaseMap);
855 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
856 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
859 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
860 DestReg).addReg(SrcReg);
863 case ISD::CopyFromReg: {
864 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
865 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
868 case ISD::EH_LABEL: {
869 MCSymbol *S = cast<EHLabelSDNode>(Node)->getLabel();
870 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
871 TII->get(TargetOpcode::EH_LABEL)).addSym(S);
875 case ISD::LIFETIME_START:
876 case ISD::LIFETIME_END: {
877 unsigned TarOp = (Node->getOpcode() == ISD::LIFETIME_START) ?
878 TargetOpcode::LIFETIME_START : TargetOpcode::LIFETIME_END;
880 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Node->getOperand(1));
881 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TarOp))
882 .addFrameIndex(FI->getIndex());
886 case ISD::INLINEASM: {
887 unsigned NumOps = Node->getNumOperands();
888 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
889 --NumOps; // Ignore the glue operand.
891 // Create the inline asm machine instruction.
892 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
893 TII->get(TargetOpcode::INLINEASM));
895 // Add the asm string as an external symbol operand.
896 SDValue AsmStrV = Node->getOperand(InlineAsm::Op_AsmString);
897 const char *AsmStr = cast<ExternalSymbolSDNode>(AsmStrV)->getSymbol();
898 MI->addOperand(MachineOperand::CreateES(AsmStr));
900 // Add the HasSideEffect and isAlignStack bits.
902 cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
904 MI->addOperand(MachineOperand::CreateImm(ExtraInfo));
906 // Remember to operand index of the group flags.
907 SmallVector<unsigned, 8> GroupIdx;
909 // Add all of the operand registers to the instruction.
910 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
912 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
913 const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
915 GroupIdx.push_back(MI->getNumOperands());
916 MI->addOperand(MachineOperand::CreateImm(Flags));
917 ++i; // Skip the ID value.
919 switch (InlineAsm::getKind(Flags)) {
920 default: llvm_unreachable("Bad flags!");
921 case InlineAsm::Kind_RegDef:
922 for (unsigned j = 0; j != NumVals; ++j, ++i) {
923 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
924 // FIXME: Add dead flags for physical and virtual registers defined.
925 // For now, mark physical register defs as implicit to help fast
926 // regalloc. This makes inline asm look a lot like calls.
927 MI->addOperand(MachineOperand::CreateReg(Reg, true,
928 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg)));
931 case InlineAsm::Kind_RegDefEarlyClobber:
932 case InlineAsm::Kind_Clobber:
933 for (unsigned j = 0; j != NumVals; ++j, ++i) {
934 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
935 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
936 /*isImp=*/ TargetRegisterInfo::isPhysicalRegister(Reg),
940 /*isEarlyClobber=*/ true));
943 case InlineAsm::Kind_RegUse: // Use of register.
944 case InlineAsm::Kind_Imm: // Immediate.
945 case InlineAsm::Kind_Mem: // Addressing mode.
946 // The addressing mode has been selected, just add all of the
947 // operands to the machine instruction.
948 for (unsigned j = 0; j != NumVals; ++j, ++i)
949 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap,
950 /*IsDebug=*/false, IsClone, IsCloned);
952 // Manually set isTied bits.
953 if (InlineAsm::getKind(Flags) == InlineAsm::Kind_RegUse) {
954 unsigned DefGroup = 0;
955 if (InlineAsm::isUseOperandTiedToDef(Flags, DefGroup)) {
956 unsigned DefIdx = GroupIdx[DefGroup] + 1;
957 unsigned UseIdx = GroupIdx.back() + 1;
958 for (unsigned j = 0; j != NumVals; ++j)
959 MI->tieOperands(DefIdx + j, UseIdx + j);
966 // Get the mdnode from the asm if it exists and add it to the instruction.
967 SDValue MDV = Node->getOperand(InlineAsm::Op_MDNode);
968 const MDNode *MD = cast<MDNodeSDNode>(MDV)->getMD();
970 MI->addOperand(MachineOperand::CreateMetadata(MD));
972 MBB->insert(InsertPos, MI);
978 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
979 /// at the given position in the given block.
980 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
981 MachineBasicBlock::iterator insertpos)
982 : MF(mbb->getParent()),
983 MRI(&MF->getRegInfo()),
984 TM(&MF->getTarget()),
985 TII(TM->getInstrInfo()),
986 TRI(TM->getRegisterInfo()),
987 TLI(TM->getTargetLowering()),
988 MBB(mbb), InsertPos(insertpos) {