1 //==--- InstrEmitter.cpp - Emit MachineInstrs for the SelectionDAG class ---==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements the Emit routines for the SelectionDAG class, which creates
11 // MachineInstrs based on the decisions of the SelectionDAG instruction
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "instr-emitter"
17 #include "InstrEmitter.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Target/TargetData.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/Support/Debug.h"
28 #include "llvm/Support/ErrorHandling.h"
29 #include "llvm/Support/MathExtras.h"
32 /// CountResults - The results of target nodes have register or immediate
33 /// operands first, then an optional chain, and optional flag operands (which do
34 /// not go into the resulting MachineInstr).
35 unsigned InstrEmitter::CountResults(SDNode *Node) {
36 unsigned N = Node->getNumValues();
37 while (N && Node->getValueType(N - 1) == MVT::Flag)
39 if (N && Node->getValueType(N - 1) == MVT::Other)
40 --N; // Skip over chain result.
44 /// CountOperands - The inputs to target nodes have any actual inputs first,
45 /// followed by an optional chain operand, then an optional flag operand.
46 /// Compute the number of actual operands that will go into the resulting
48 unsigned InstrEmitter::CountOperands(SDNode *Node) {
49 unsigned N = Node->getNumOperands();
50 while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
52 if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
53 --N; // Ignore chain if it exists.
57 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
58 /// implicit physical register output.
60 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned,
61 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) {
63 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
64 // Just use the input register directly!
65 SDValue Op(Node, ResNo);
68 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second;
69 isNew = isNew; // Silence compiler warning.
70 assert(isNew && "Node emitted out of order - early");
74 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
75 // the CopyToReg'd destination register instead of creating a new vreg.
77 const TargetRegisterClass *UseRC = NULL;
78 if (!IsClone && !IsCloned)
79 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
83 if (User->getOpcode() == ISD::CopyToReg &&
84 User->getOperand(2).getNode() == Node &&
85 User->getOperand(2).getResNo() == ResNo) {
86 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
87 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
90 } else if (DestReg != SrcReg)
93 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
94 SDValue Op = User->getOperand(i);
95 if (Op.getNode() != Node || Op.getResNo() != ResNo)
97 EVT VT = Node->getValueType(Op.getResNo());
98 if (VT == MVT::Other || VT == MVT::Flag)
101 if (User->isMachineOpcode()) {
102 const TargetInstrDesc &II = TII->get(User->getMachineOpcode());
103 const TargetRegisterClass *RC = 0;
104 if (i+II.getNumDefs() < II.getNumOperands())
105 RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI);
109 const TargetRegisterClass *ComRC = getCommonSubClass(UseRC, RC);
110 // If multiple uses expect disjoint register classes, we emit
111 // copies in AddRegisterOperand.
123 EVT VT = Node->getValueType(ResNo);
124 const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
125 SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
127 // Figure out the register class to create for the destreg.
129 DstRC = MRI->getRegClass(VRBase);
131 assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
134 DstRC = TLI->getRegClassFor(VT);
137 // If all uses are reading from the src physical register and copying the
138 // register is either impossible or very expensive, then don't create a copy.
139 if (MatchReg && SrcRC->getCopyCost() < 0) {
142 // Create the reg, emit the copy.
143 VRBase = MRI->createVirtualRegister(DstRC);
144 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, VRBase, SrcReg,
147 assert(Emitted && "Unable to issue a copy instruction!\n");
151 SDValue Op(Node, ResNo);
154 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
155 isNew = isNew; // Silence compiler warning.
156 assert(isNew && "Node emitted out of order - early");
159 /// getDstOfCopyToRegUse - If the only use of the specified result number of
160 /// node is a CopyToReg, return its destination register. Return 0 otherwise.
161 unsigned InstrEmitter::getDstOfOnlyCopyToRegUse(SDNode *Node,
162 unsigned ResNo) const {
163 if (!Node->hasOneUse())
166 SDNode *User = *Node->use_begin();
167 if (User->getOpcode() == ISD::CopyToReg &&
168 User->getOperand(2).getNode() == Node &&
169 User->getOperand(2).getResNo() == ResNo) {
170 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
171 if (TargetRegisterInfo::isVirtualRegister(Reg))
177 void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
178 const TargetInstrDesc &II,
179 bool IsClone, bool IsCloned,
180 DenseMap<SDValue, unsigned> &VRBaseMap) {
181 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
182 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
184 for (unsigned i = 0; i < II.getNumDefs(); ++i) {
185 // If the specific node value is only used by a CopyToReg and the dest reg
186 // is a vreg in the same register class, use the CopyToReg'd destination
187 // register instead of creating a new vreg.
189 const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI);
190 if (II.OpInfo[i].isOptionalDef()) {
191 // Optional def must be a physical register.
192 unsigned NumResults = CountResults(Node);
193 VRBase = cast<RegisterSDNode>(Node->getOperand(i-NumResults))->getReg();
194 assert(TargetRegisterInfo::isPhysicalRegister(VRBase));
195 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
198 if (!VRBase && !IsClone && !IsCloned)
199 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
202 if (User->getOpcode() == ISD::CopyToReg &&
203 User->getOperand(2).getNode() == Node &&
204 User->getOperand(2).getResNo() == i) {
205 unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
206 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
207 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
210 MI->addOperand(MachineOperand::CreateReg(Reg, true));
217 // Create the result registers for this node and add the result regs to
218 // the machine instruction.
220 assert(RC && "Isn't a register operand!");
221 VRBase = MRI->createVirtualRegister(RC);
222 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
228 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
229 isNew = isNew; // Silence compiler warning.
230 assert(isNew && "Node emitted out of order - early");
234 /// getVR - Return the virtual register corresponding to the specified result
235 /// of the specified node.
236 unsigned InstrEmitter::getVR(SDValue Op,
237 DenseMap<SDValue, unsigned> &VRBaseMap) {
238 if (Op.isMachineOpcode() &&
239 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
240 // Add an IMPLICIT_DEF instruction before every use.
241 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
242 // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc
243 // does not include operand register class info.
245 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType());
246 VReg = MRI->createVirtualRegister(RC);
248 BuildMI(MBB, Op.getDebugLoc(),
249 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
253 DenseMap<SDValue, unsigned>::iterator I = VRBaseMap.find(Op);
254 assert(I != VRBaseMap.end() && "Node emitted out of order - late");
259 /// AddRegisterOperand - Add the specified register as an operand to the
260 /// specified machine instr. Insert register copies if the register is
261 /// not in the required register class.
263 InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op,
265 const TargetInstrDesc *II,
266 DenseMap<SDValue, unsigned> &VRBaseMap) {
267 assert(Op.getValueType() != MVT::Other &&
268 Op.getValueType() != MVT::Flag &&
269 "Chain and flag operands should occur at end of operand list!");
270 // Get/emit the operand.
271 unsigned VReg = getVR(Op, VRBaseMap);
272 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
274 const TargetInstrDesc &TID = MI->getDesc();
275 bool isOptDef = IIOpNum < TID.getNumOperands() &&
276 TID.OpInfo[IIOpNum].isOptionalDef();
278 // If the instruction requires a register in a different class, create
279 // a new virtual register and copy the value into it.
281 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
282 const TargetRegisterClass *DstRC = 0;
283 if (IIOpNum < II->getNumOperands())
284 DstRC = II->OpInfo[IIOpNum].getRegClass(TRI);
285 assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) &&
286 "Don't have operand info for this instruction!");
287 if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) {
288 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
289 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
291 assert(Emitted && "Unable to issue a copy instruction!\n");
297 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
300 /// AddOperand - Add the specified operand to the specified machine instr. II
301 /// specifies the instruction information for the node, and IIOpNum is the
302 /// operand number (in the II) that we are adding. IIOpNum and II are used for
304 void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op,
306 const TargetInstrDesc *II,
307 DenseMap<SDValue, unsigned> &VRBaseMap) {
308 if (Op.isMachineOpcode()) {
309 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
310 } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
311 MI->addOperand(MachineOperand::CreateImm(C->getSExtValue()));
312 } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
313 const ConstantFP *CFP = F->getConstantFPValue();
314 MI->addOperand(MachineOperand::CreateFPImm(CFP));
315 } else if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op)) {
316 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false));
317 } else if (GlobalAddressSDNode *TGA = dyn_cast<GlobalAddressSDNode>(Op)) {
318 MI->addOperand(MachineOperand::CreateGA(TGA->getGlobal(), TGA->getOffset(),
319 TGA->getTargetFlags()));
320 } else if (BasicBlockSDNode *BBNode = dyn_cast<BasicBlockSDNode>(Op)) {
321 MI->addOperand(MachineOperand::CreateMBB(BBNode->getBasicBlock()));
322 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Op)) {
323 MI->addOperand(MachineOperand::CreateFI(FI->getIndex()));
324 } else if (JumpTableSDNode *JT = dyn_cast<JumpTableSDNode>(Op)) {
325 MI->addOperand(MachineOperand::CreateJTI(JT->getIndex(),
326 JT->getTargetFlags()));
327 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) {
328 int Offset = CP->getOffset();
329 unsigned Align = CP->getAlignment();
330 const Type *Type = CP->getType();
331 // MachineConstantPool wants an explicit alignment.
333 Align = TM->getTargetData()->getPrefTypeAlignment(Type);
335 // Alignment of vector types. FIXME!
336 Align = TM->getTargetData()->getTypeAllocSize(Type);
341 MachineConstantPool *MCP = MF->getConstantPool();
342 if (CP->isMachineConstantPoolEntry())
343 Idx = MCP->getConstantPoolIndex(CP->getMachineCPVal(), Align);
345 Idx = MCP->getConstantPoolIndex(CP->getConstVal(), Align);
346 MI->addOperand(MachineOperand::CreateCPI(Idx, Offset,
347 CP->getTargetFlags()));
348 } else if (ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) {
349 MI->addOperand(MachineOperand::CreateES(ES->getSymbol(),
350 ES->getTargetFlags()));
351 } else if (BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
352 MI->addOperand(MachineOperand::CreateBA(BA->getBlockAddress(),
353 BA->getTargetFlags()));
355 assert(Op.getValueType() != MVT::Other &&
356 Op.getValueType() != MVT::Flag &&
357 "Chain and flag operands should occur at end of operand list!");
358 AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
362 /// getSuperRegisterRegClass - Returns the register class of a superreg A whose
363 /// "SubIdx"'th sub-register class is the specified register class and whose
364 /// type matches the specified type.
365 static const TargetRegisterClass*
366 getSuperRegisterRegClass(const TargetRegisterClass *TRC,
367 unsigned SubIdx, EVT VT) {
368 // Pick the register class of the superegister for this type
369 for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
370 E = TRC->superregclasses_end(); I != E; ++I)
371 if ((*I)->hasType(VT) && (*I)->getSubRegisterRegClass(SubIdx) == TRC)
373 assert(false && "Couldn't find the register class");
377 /// EmitSubregNode - Generate machine code for subreg nodes.
379 void InstrEmitter::EmitSubregNode(SDNode *Node,
380 DenseMap<SDValue, unsigned> &VRBaseMap){
382 unsigned Opc = Node->getMachineOpcode();
384 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
385 // the CopyToReg'd destination register instead of creating a new vreg.
386 for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
389 if (User->getOpcode() == ISD::CopyToReg &&
390 User->getOperand(2).getNode() == Node) {
391 unsigned DestReg = cast<RegisterSDNode>(User->getOperand(1))->getReg();
392 if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
399 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
400 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
402 // Create the extract_subreg machine instruction.
403 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
404 TII->get(TargetOpcode::EXTRACT_SUBREG));
406 // Figure out the register class to create for the destreg.
407 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
408 const TargetRegisterClass *TRC = MRI->getRegClass(VReg);
409 const TargetRegisterClass *SRC = TRC->getSubRegisterRegClass(SubIdx);
410 assert(SRC && "Invalid subregister index in EXTRACT_SUBREG");
412 // Figure out the register class to create for the destreg.
413 // Note that if we're going to directly use an existing register,
414 // it must be precisely the required class, and not a subclass
416 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
418 assert(SRC && "Couldn't find source register class");
419 VRBase = MRI->createVirtualRegister(SRC);
422 // Add def, source, and subreg index
423 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
424 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
425 MI->addOperand(MachineOperand::CreateImm(SubIdx));
426 MBB->insert(InsertPos, MI);
427 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
428 Opc == TargetOpcode::SUBREG_TO_REG) {
429 SDValue N0 = Node->getOperand(0);
430 SDValue N1 = Node->getOperand(1);
431 SDValue N2 = Node->getOperand(2);
432 unsigned SubReg = getVR(N1, VRBaseMap);
433 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
434 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
435 const TargetRegisterClass *SRC =
436 getSuperRegisterRegClass(TRC, SubIdx,
437 Node->getValueType(0));
439 // Figure out the register class to create for the destreg.
440 // Note that if we're going to directly use an existing register,
441 // it must be precisely the required class, and not a subclass
443 if (VRBase == 0 || SRC != MRI->getRegClass(VRBase)) {
445 assert(SRC && "Couldn't find source register class");
446 VRBase = MRI->createVirtualRegister(SRC);
449 // Create the insert_subreg or subreg_to_reg machine instruction.
450 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc));
451 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
453 // If creating a subreg_to_reg, then the first input operand
454 // is an implicit value immediate, otherwise it's a register
455 if (Opc == TargetOpcode::SUBREG_TO_REG) {
456 const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
457 MI->addOperand(MachineOperand::CreateImm(SD->getZExtValue()));
459 AddOperand(MI, N0, 0, 0, VRBaseMap);
460 // Add the subregster being inserted
461 AddOperand(MI, N1, 0, 0, VRBaseMap);
462 MI->addOperand(MachineOperand::CreateImm(SubIdx));
463 MBB->insert(InsertPos, MI);
465 llvm_unreachable("Node is not insert_subreg, extract_subreg, or subreg_to_reg");
468 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBase)).second;
469 isNew = isNew; // Silence compiler warning.
470 assert(isNew && "Node emitted out of order - early");
473 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes.
474 /// COPY_TO_REGCLASS is just a normal copy, except that the destination
475 /// register is constrained to be in a particular register class.
478 InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
479 DenseMap<SDValue, unsigned> &VRBaseMap) {
480 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
481 const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg);
483 unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
484 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
486 // Create the new VReg in the destination class and emit a copy.
487 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
488 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, NewVReg, VReg,
491 "Unable to issue a copy instruction for a COPY_TO_REGCLASS node!\n");
495 bool isNew = VRBaseMap.insert(std::make_pair(Op, NewVReg)).second;
496 isNew = isNew; // Silence compiler warning.
497 assert(isNew && "Node emitted out of order - early");
500 /// EmitNode - Generate machine code for a node and needed dependencies.
502 void InstrEmitter::EmitNode(SDNode *Node, bool IsClone, bool IsCloned,
503 DenseMap<SDValue, unsigned> &VRBaseMap,
504 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) {
505 // If machine instruction
506 if (Node->isMachineOpcode()) {
507 unsigned Opc = Node->getMachineOpcode();
509 // Handle subreg insert/extract specially
510 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
511 Opc == TargetOpcode::INSERT_SUBREG ||
512 Opc == TargetOpcode::SUBREG_TO_REG) {
513 EmitSubregNode(Node, VRBaseMap);
517 // Handle COPY_TO_REGCLASS specially.
518 if (Opc == TargetOpcode::COPY_TO_REGCLASS) {
519 EmitCopyToRegClassNode(Node, VRBaseMap);
523 if (Opc == TargetOpcode::IMPLICIT_DEF)
524 // We want a unique VR for each IMPLICIT_DEF use.
527 const TargetInstrDesc &II = TII->get(Opc);
528 unsigned NumResults = CountResults(Node);
529 unsigned NodeOperands = CountOperands(Node);
530 bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
531 II.getImplicitDefs() != 0;
533 unsigned NumMIOperands = NodeOperands + NumResults;
534 assert((II.getNumOperands() == NumMIOperands ||
535 HasPhysRegOuts || II.isVariadic()) &&
536 "#operands for dag node doesn't match .td file!");
539 // Create the new machine instruction.
540 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(), II);
542 // Add result register values for things that are defined by this
545 CreateVirtualRegisters(Node, MI, II, IsClone, IsCloned, VRBaseMap);
547 // Emit all of the actual operands of this instruction, adding them to the
548 // instruction as appropriate.
549 bool HasOptPRefs = II.getNumDefs() > NumResults;
550 assert((!HasOptPRefs || !HasPhysRegOuts) &&
551 "Unable to cope with optional defs and phys regs defs!");
552 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0;
553 for (unsigned i = NumSkip; i != NodeOperands; ++i)
554 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II,
557 // Transfer all of the memory reference descriptions of this instruction.
558 MI->setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(),
559 cast<MachineSDNode>(Node)->memoperands_end());
561 if (II.usesCustomInsertionHook()) {
562 // Insert this instruction into the basic block using a target
563 // specific inserter which may returns a new basic block.
564 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB, EM);
565 InsertPos = MBB->end();
567 MBB->insert(InsertPos, MI);
570 // Additional results must be an physical register def.
571 if (HasPhysRegOuts) {
572 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
573 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
574 if (Node->hasAnyUseOfValue(i))
575 EmitCopyFromReg(Node, i, IsClone, IsCloned, Reg, VRBaseMap);
576 // If there are no uses, mark the register as dead now, so that
577 // MachineLICM/Sink can see that it's dead. Don't do this if the
578 // node has a Flag value, for the benefit of targets still using
579 // Flag for values in physregs.
580 else if (Node->getValueType(Node->getNumValues()-1) != MVT::Flag)
581 MI->addRegisterDead(Reg, TRI);
587 switch (Node->getOpcode()) {
592 llvm_unreachable("This target-independent node should have been selected!");
594 case ISD::EntryToken:
595 llvm_unreachable("EntryToken should have been excluded from the schedule!");
597 case ISD::MERGE_VALUES:
598 case ISD::TokenFactor: // fall thru
600 case ISD::CopyToReg: {
602 SDValue SrcVal = Node->getOperand(2);
603 if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(SrcVal))
604 SrcReg = R->getReg();
606 SrcReg = getVR(SrcVal, VRBaseMap);
608 unsigned DestReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
609 if (SrcReg == DestReg) // Coalesced away the copy? Ignore.
612 const TargetRegisterClass *SrcTRC = 0, *DstTRC = 0;
613 // Get the register classes of the src/dst.
614 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
615 SrcTRC = MRI->getRegClass(SrcReg);
617 SrcTRC = TRI->getPhysicalRegisterRegClass(SrcReg,SrcVal.getValueType());
619 if (TargetRegisterInfo::isVirtualRegister(DestReg))
620 DstTRC = MRI->getRegClass(DestReg);
622 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
623 Node->getOperand(1).getValueType());
625 bool Emitted = TII->copyRegToReg(*MBB, InsertPos, DestReg, SrcReg,
627 assert(Emitted && "Unable to issue a copy instruction!\n");
631 case ISD::CopyFromReg: {
632 unsigned SrcReg = cast<RegisterSDNode>(Node->getOperand(1))->getReg();
633 EmitCopyFromReg(Node, 0, IsClone, IsCloned, SrcReg, VRBaseMap);
636 case ISD::INLINEASM: {
637 unsigned NumOps = Node->getNumOperands();
638 if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
639 --NumOps; // Ignore the flag operand.
641 // Create the inline asm machine instruction.
642 MachineInstr *MI = BuildMI(*MF, Node->getDebugLoc(),
643 TII->get(TargetOpcode::INLINEASM));
645 // Add the asm string as an external symbol operand.
647 cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
648 MI->addOperand(MachineOperand::CreateES(AsmStr));
650 // Add all of the operand registers to the instruction.
651 for (unsigned i = 2; i != NumOps;) {
653 cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
654 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
656 MI->addOperand(MachineOperand::CreateImm(Flags));
657 ++i; // Skip the ID value.
660 default: llvm_unreachable("Bad flags!");
661 case 2: // Def of register.
662 for (; NumVals; --NumVals, ++i) {
663 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
664 MI->addOperand(MachineOperand::CreateReg(Reg, true));
667 case 6: // Def of earlyclobber register.
668 for (; NumVals; --NumVals, ++i) {
669 unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
670 MI->addOperand(MachineOperand::CreateReg(Reg, true, false, false,
671 false, false, true));
674 case 1: // Use of register.
675 case 3: // Immediate.
676 case 4: // Addressing mode.
677 // The addressing mode has been selected, just add all of the
678 // operands to the machine instruction.
679 for (; NumVals; --NumVals, ++i)
680 AddOperand(MI, Node->getOperand(i), 0, 0, VRBaseMap);
684 MBB->insert(InsertPos, MI);
690 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting
691 /// at the given position in the given block.
692 InstrEmitter::InstrEmitter(MachineBasicBlock *mbb,
693 MachineBasicBlock::iterator insertpos)
694 : MF(mbb->getParent()),
695 MRI(&MF->getRegInfo()),
696 TM(&MF->getTarget()),
697 TII(TM->getInstrInfo()),
698 TRI(TM->getRegisterInfo()),
699 TLI(TM->getTargetLowering()),
700 MBB(mbb), InsertPos(insertpos) {