1 //===-- FunctionLoweringInfo.cpp ------------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This implements routines for translating functions from LLVM IR into
13 //===----------------------------------------------------------------------===//
15 #include "llvm/CodeGen/FunctionLoweringInfo.h"
16 #include "llvm/ADT/PostOrderIterator.h"
17 #include "llvm/CodeGen/Analysis.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/WinEHFuncInfo.h"
24 #include "llvm/IR/DataLayout.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/LLVMContext.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/Target/TargetRegisterInfo.h"
41 #include "llvm/Target/TargetSubtargetInfo.h"
45 #define DEBUG_TYPE "function-lowering-info"
47 /// isUsedOutsideOfDefiningBlock - Return true if this instruction is used by
48 /// PHI nodes or outside of the basic block that defines it, or used by a
49 /// switch or atomic instruction, which may expand to multiple basic blocks.
50 static bool isUsedOutsideOfDefiningBlock(const Instruction *I) {
51 if (I->use_empty()) return false;
52 if (isa<PHINode>(I)) return true;
53 const BasicBlock *BB = I->getParent();
54 for (const User *U : I->users())
55 if (cast<Instruction>(U)->getParent() != BB || isa<PHINode>(U))
61 static ISD::NodeType getPreferredExtendForValue(const Value *V) {
62 // For the users of the source value being used for compare instruction, if
63 // the number of signed predicate is greater than unsigned predicate, we
64 // prefer to use SIGN_EXTEND.
66 // With this optimization, we would be able to reduce some redundant sign or
67 // zero extension instruction, and eventually more machine CSE opportunities
69 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
70 unsigned NumOfSigned = 0, NumOfUnsigned = 0;
71 for (const User *U : V->users()) {
72 if (const auto *CI = dyn_cast<CmpInst>(U)) {
73 NumOfSigned += CI->isSigned();
74 NumOfUnsigned += CI->isUnsigned();
77 if (NumOfSigned > NumOfUnsigned)
78 ExtendKind = ISD::SIGN_EXTEND;
83 void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf,
87 TLI = MF->getSubtarget().getTargetLowering();
88 RegInfo = &MF->getRegInfo();
89 MachineModuleInfo &MMI = MF->getMMI();
91 // Check whether the function can return without sret-demotion.
92 SmallVector<ISD::OutputArg, 4> Outs;
93 GetReturnInfo(Fn->getReturnType(), Fn->getAttributes(), Outs, *TLI,
95 CanLowerReturn = TLI->CanLowerReturn(Fn->getCallingConv(), *MF,
96 Fn->isVarArg(), Outs, Fn->getContext());
98 // Initialize the mapping of values to registers. This is only set up for
99 // instruction values that are used outside of the block that defines
101 Function::const_iterator BB = Fn->begin(), EB = Fn->end();
102 for (; BB != EB; ++BB)
103 for (BasicBlock::const_iterator I = BB->begin(), E = BB->end();
105 if (const AllocaInst *AI = dyn_cast<AllocaInst>(I)) {
106 // Static allocas can be folded into the initial stack frame adjustment.
107 if (AI->isStaticAlloca()) {
108 const ConstantInt *CUI = cast<ConstantInt>(AI->getArraySize());
109 Type *Ty = AI->getAllocatedType();
110 uint64_t TySize = MF->getDataLayout().getTypeAllocSize(Ty);
112 std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(Ty),
115 TySize *= CUI->getZExtValue(); // Get total allocated size.
116 if (TySize == 0) TySize = 1; // Don't create zero-sized stack objects.
118 StaticAllocaMap[AI] =
119 MF->getFrameInfo()->CreateStackObject(TySize, Align, false, AI);
123 std::max((unsigned)MF->getDataLayout().getPrefTypeAlignment(
124 AI->getAllocatedType()),
126 unsigned StackAlign =
127 MF->getSubtarget().getFrameLowering()->getStackAlignment();
128 if (Align <= StackAlign)
130 // Inform the Frame Information that we have variable-sized objects.
131 MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1, AI);
135 // Look for inline asm that clobbers the SP register.
136 if (isa<CallInst>(I) || isa<InvokeInst>(I)) {
137 ImmutableCallSite CS(I);
138 if (isa<InlineAsm>(CS.getCalledValue())) {
139 unsigned SP = TLI->getStackPointerRegisterToSaveRestore();
140 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
141 std::vector<TargetLowering::AsmOperandInfo> Ops =
142 TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
143 for (size_t I = 0, E = Ops.size(); I != E; ++I) {
144 TargetLowering::AsmOperandInfo &Op = Ops[I];
145 if (Op.Type == InlineAsm::isClobber) {
146 // Clobbers don't have SDValue operands, hence SDValue().
147 TLI->ComputeConstraintToUse(Op, SDValue(), DAG);
148 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
149 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
151 if (PhysReg.first == SP)
152 MF->getFrameInfo()->setHasOpaqueSPAdjustment(true);
158 // Look for calls to the @llvm.va_start intrinsic. We can omit some
159 // prologue boilerplate for variadic functions that don't examine their
161 if (const auto *II = dyn_cast<IntrinsicInst>(I)) {
162 if (II->getIntrinsicID() == Intrinsic::vastart)
163 MF->getFrameInfo()->setHasVAStart(true);
166 // If we have a musttail call in a variadic funciton, we need to ensure we
167 // forward implicit register parameters.
168 if (const auto *CI = dyn_cast<CallInst>(I)) {
169 if (CI->isMustTailCall() && Fn->isVarArg())
170 MF->getFrameInfo()->setHasMustTailInVarArgFunc(true);
173 // Mark values used outside their block as exported, by allocating
174 // a virtual register for them.
175 if (isUsedOutsideOfDefiningBlock(I))
176 if (!isa<AllocaInst>(I) ||
177 !StaticAllocaMap.count(cast<AllocaInst>(I)))
178 InitializeRegForValue(I);
180 // Collect llvm.dbg.declare information. This is done now instead of
181 // during the initial isel pass through the IR so that it is done
182 // in a predictable order.
183 if (const DbgDeclareInst *DI = dyn_cast<DbgDeclareInst>(I)) {
184 assert(DI->getVariable() && "Missing variable");
185 assert(DI->getDebugLoc() && "Missing location");
186 if (MMI.hasDebugInfo()) {
187 // Don't handle byval struct arguments or VLAs, for example.
188 // Non-byval arguments are handled here (they refer to the stack
189 // temporary alloca at this point).
190 const Value *Address = DI->getAddress();
192 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
193 Address = BCI->getOperand(0);
194 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) {
195 DenseMap<const AllocaInst *, int>::iterator SI =
196 StaticAllocaMap.find(AI);
197 if (SI != StaticAllocaMap.end()) { // Check for VLAs.
199 MMI.setVariableDbgInfo(DI->getVariable(), DI->getExpression(),
200 FI, DI->getDebugLoc());
207 // Decide the preferred extend type for a value.
208 PreferredExtendType[I] = getPreferredExtendForValue(I);
211 // Create an initial MachineBasicBlock for each LLVM BasicBlock in F. This
212 // also creates the initial PHI MachineInstrs, though none of the input
213 // operands are populated.
214 for (BB = Fn->begin(); BB != EB; ++BB) {
215 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(BB);
219 // Transfer the address-taken flag. This is necessary because there could
220 // be multiple MachineBasicBlocks corresponding to one BasicBlock, and only
221 // the first one should be marked.
222 if (BB->hasAddressTaken())
223 MBB->setHasAddressTaken();
225 // Create Machine PHI nodes for LLVM PHI nodes, lowering them as
227 for (BasicBlock::const_iterator I = BB->begin();
228 const PHINode *PN = dyn_cast<PHINode>(I); ++I) {
229 if (PN->use_empty()) continue;
232 if (PN->getType()->isEmptyTy())
235 DebugLoc DL = PN->getDebugLoc();
236 unsigned PHIReg = ValueMap[PN];
237 assert(PHIReg && "PHI node does not have an assigned virtual register!");
239 SmallVector<EVT, 4> ValueVTs;
240 ComputeValueVTs(*TLI, MF->getDataLayout(), PN->getType(), ValueVTs);
241 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
242 EVT VT = ValueVTs[vti];
243 unsigned NumRegisters = TLI->getNumRegisters(Fn->getContext(), VT);
244 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
245 for (unsigned i = 0; i != NumRegisters; ++i)
246 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
247 PHIReg += NumRegisters;
252 // Mark landing pad blocks.
253 SmallVector<const LandingPadInst *, 4> LPads;
254 for (BB = Fn->begin(); BB != EB; ++BB) {
256 MBBMap[BB]->setIsEHPad();
257 const Instruction *FNP = BB->getFirstNonPHI();
258 if (const auto *LPI = dyn_cast<LandingPadInst>(FNP))
259 LPads.push_back(LPI);
262 // If this is an MSVC EH personality, we need to do a bit more work.
263 if (!Fn->hasPersonalityFn())
265 EHPersonality Personality = classifyEHPersonality(Fn->getPersonalityFn());
266 if (!isMSVCEHPersonality(Personality))
269 if (Personality == EHPersonality::MSVC_Win64SEH ||
270 Personality == EHPersonality::MSVC_X86SEH) {
271 addSEHHandlersForLPads(LPads);
274 WinEHFuncInfo &EHInfo = MMI.getWinEHFuncInfo(&fn);
275 if (Personality == EHPersonality::MSVC_CXX) {
276 // Calculate state numbers and then map from funclet BBs to MBBs.
277 const Function *WinEHParentFn = MMI.getWinEHParent(&fn);
278 calculateWinCXXEHStateNumbers(WinEHParentFn, EHInfo);
279 for (WinEHTryBlockMapEntry &TBME : EHInfo.TryBlockMap)
280 for (WinEHHandlerType &H : TBME.HandlerArray)
281 if (const auto *BB = dyn_cast<BasicBlock>(H.Handler))
282 H.HandlerMBB = MBBMap[BB];
283 // If there's an explicit EH registration node on the stack, record its
285 if (EHInfo.EHRegNode && EHInfo.EHRegNode->getParent()->getParent() == Fn) {
286 assert(StaticAllocaMap.count(EHInfo.EHRegNode));
287 EHInfo.EHRegNodeFrameIndex = StaticAllocaMap[EHInfo.EHRegNode];
291 // Copy the state numbers to LandingPadInfo for the current function, which
292 // could be a handler or the parent. This should happen for 32-bit SEH and
294 if (Personality == EHPersonality::MSVC_CXX ||
295 Personality == EHPersonality::MSVC_X86SEH) {
296 for (const LandingPadInst *LP : LPads) {
297 MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
298 MMI.addWinEHState(LPadMBB, EHInfo.EHPadStateMap[LP]);
303 void FunctionLoweringInfo::addSEHHandlersForLPads(
304 ArrayRef<const LandingPadInst *> LPads) {
305 MachineModuleInfo &MMI = MF->getMMI();
307 // Iterate over all landing pads with llvm.eh.actions calls.
308 for (const LandingPadInst *LP : LPads) {
309 const IntrinsicInst *ActionsCall =
310 dyn_cast<IntrinsicInst>(LP->getNextNode());
312 ActionsCall->getIntrinsicID() != Intrinsic::eh_actions)
315 // Parse the llvm.eh.actions call we found.
316 MachineBasicBlock *LPadMBB = MBBMap[LP->getParent()];
317 SmallVector<std::unique_ptr<ActionHandler>, 4> Actions;
318 parseEHActions(ActionsCall, Actions);
320 // Iterate EH actions from most to least precedence, which means
321 // iterating in reverse.
322 for (auto I = Actions.rbegin(), E = Actions.rend(); I != E; ++I) {
323 ActionHandler *Action = I->get();
324 if (auto *CH = dyn_cast<CatchHandler>(Action)) {
326 dyn_cast<Function>(CH->getSelector()->stripPointerCasts());
327 assert((Filter || CH->getSelector()->isNullValue()) &&
328 "expected function or catch-all");
329 const auto *RecoverBA =
330 cast<BlockAddress>(CH->getHandlerBlockOrFunc());
331 MMI.addSEHCatchHandler(LPadMBB, Filter, RecoverBA);
333 assert(isa<CleanupHandler>(Action));
334 const auto *Fini = cast<Function>(Action->getHandlerBlockOrFunc());
335 MMI.addSEHCleanupHandler(LPadMBB, Fini);
341 /// clear - Clear out all the function-specific state. This returns this
342 /// FunctionLoweringInfo to an empty state, ready to be used for a
343 /// different function.
344 void FunctionLoweringInfo::clear() {
345 assert(CatchInfoFound.size() == CatchInfoLost.size() &&
346 "Not all catch info was assigned to a landing pad!");
350 StaticAllocaMap.clear();
352 CatchInfoLost.clear();
353 CatchInfoFound.clear();
355 LiveOutRegInfo.clear();
357 ArgDbgValues.clear();
358 ByValArgFrameIndexMap.clear();
360 StatepointStackSlots.clear();
361 StatepointRelocatedValues.clear();
362 PreferredExtendType.clear();
365 /// CreateReg - Allocate a single virtual register for the given type.
366 unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
367 return RegInfo->createVirtualRegister(
368 MF->getSubtarget().getTargetLowering()->getRegClassFor(VT));
371 /// CreateRegs - Allocate the appropriate number of virtual registers of
372 /// the correctly promoted or expanded types. Assign these registers
373 /// consecutive vreg numbers and return the first assigned number.
375 /// In the case that the given value has struct or array type, this function
376 /// will assign registers for each member or element.
378 unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
379 const TargetLowering *TLI = MF->getSubtarget().getTargetLowering();
381 SmallVector<EVT, 4> ValueVTs;
382 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
384 unsigned FirstReg = 0;
385 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
386 EVT ValueVT = ValueVTs[Value];
387 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT);
389 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT);
390 for (unsigned i = 0; i != NumRegs; ++i) {
391 unsigned R = CreateReg(RegisterVT);
392 if (!FirstReg) FirstReg = R;
398 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
399 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
400 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
401 /// the larger bit width by zero extension. The bit width must be no smaller
402 /// than the LiveOutInfo's existing bit width.
403 const FunctionLoweringInfo::LiveOutInfo *
404 FunctionLoweringInfo::GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth) {
405 if (!LiveOutRegInfo.inBounds(Reg))
408 LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
412 if (BitWidth > LOI->KnownZero.getBitWidth()) {
413 LOI->NumSignBits = 1;
414 LOI->KnownZero = LOI->KnownZero.zextOrTrunc(BitWidth);
415 LOI->KnownOne = LOI->KnownOne.zextOrTrunc(BitWidth);
421 /// ComputePHILiveOutRegInfo - Compute LiveOutInfo for a PHI's destination
422 /// register based on the LiveOutInfo of its operands.
423 void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) {
424 Type *Ty = PN->getType();
425 if (!Ty->isIntegerTy() || Ty->isVectorTy())
428 SmallVector<EVT, 1> ValueVTs;
429 ComputeValueVTs(*TLI, MF->getDataLayout(), Ty, ValueVTs);
430 assert(ValueVTs.size() == 1 &&
431 "PHIs with non-vector integer types should have a single VT.");
432 EVT IntVT = ValueVTs[0];
434 if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1)
436 IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT);
437 unsigned BitWidth = IntVT.getSizeInBits();
439 unsigned DestReg = ValueMap[PN];
440 if (!TargetRegisterInfo::isVirtualRegister(DestReg))
442 LiveOutRegInfo.grow(DestReg);
443 LiveOutInfo &DestLOI = LiveOutRegInfo[DestReg];
445 Value *V = PN->getIncomingValue(0);
446 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
447 DestLOI.NumSignBits = 1;
448 APInt Zero(BitWidth, 0);
449 DestLOI.KnownZero = Zero;
450 DestLOI.KnownOne = Zero;
454 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
455 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
456 DestLOI.NumSignBits = Val.getNumSignBits();
457 DestLOI.KnownZero = ~Val;
458 DestLOI.KnownOne = Val;
460 assert(ValueMap.count(V) && "V should have been placed in ValueMap when its"
461 "CopyToReg node was created.");
462 unsigned SrcReg = ValueMap[V];
463 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
464 DestLOI.IsValid = false;
467 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
469 DestLOI.IsValid = false;
475 assert(DestLOI.KnownZero.getBitWidth() == BitWidth &&
476 DestLOI.KnownOne.getBitWidth() == BitWidth &&
477 "Masks should have the same bit width as the type.");
479 for (unsigned i = 1, e = PN->getNumIncomingValues(); i != e; ++i) {
480 Value *V = PN->getIncomingValue(i);
481 if (isa<UndefValue>(V) || isa<ConstantExpr>(V)) {
482 DestLOI.NumSignBits = 1;
483 APInt Zero(BitWidth, 0);
484 DestLOI.KnownZero = Zero;
485 DestLOI.KnownOne = Zero;
489 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
490 APInt Val = CI->getValue().zextOrTrunc(BitWidth);
491 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, Val.getNumSignBits());
492 DestLOI.KnownZero &= ~Val;
493 DestLOI.KnownOne &= Val;
497 assert(ValueMap.count(V) && "V should have been placed in ValueMap when "
498 "its CopyToReg node was created.");
499 unsigned SrcReg = ValueMap[V];
500 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) {
501 DestLOI.IsValid = false;
504 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
506 DestLOI.IsValid = false;
509 DestLOI.NumSignBits = std::min(DestLOI.NumSignBits, SrcLOI->NumSignBits);
510 DestLOI.KnownZero &= SrcLOI->KnownZero;
511 DestLOI.KnownOne &= SrcLOI->KnownOne;
515 /// setArgumentFrameIndex - Record frame index for the byval
516 /// argument. This overrides previous frame index entry for this argument,
518 void FunctionLoweringInfo::setArgumentFrameIndex(const Argument *A,
520 ByValArgFrameIndexMap[A] = FI;
523 /// getArgumentFrameIndex - Get frame index for the byval argument.
524 /// If the argument does not have any assigned frame index then 0 is
526 int FunctionLoweringInfo::getArgumentFrameIndex(const Argument *A) {
527 DenseMap<const Argument *, int>::iterator I =
528 ByValArgFrameIndexMap.find(A);
529 if (I != ByValArgFrameIndexMap.end())
531 DEBUG(dbgs() << "Argument does not have assigned frame index!\n");
535 /// ComputeUsesVAFloatArgument - Determine if any floating-point values are
536 /// being passed to this variadic function, and set the MachineModuleInfo's
537 /// usesVAFloatArgument flag if so. This flag is used to emit an undefined
538 /// reference to _fltused on Windows, which will link in MSVCRT's
539 /// floating-point support.
540 void llvm::ComputeUsesVAFloatArgument(const CallInst &I,
541 MachineModuleInfo *MMI)
543 FunctionType *FT = cast<FunctionType>(
544 I.getCalledValue()->getType()->getContainedType(0));
545 if (FT->isVarArg() && !MMI->usesVAFloatArgument()) {
546 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) {
547 Type* T = I.getArgOperand(i)->getType();
548 for (auto i : post_order(T)) {
549 if (i->isFloatingPointTy()) {
550 MMI->setUsesVAFloatArgument(true);
558 /// AddLandingPadInfo - Extract the exception handling information from the
559 /// landingpad instruction and add them to the specified machine module info.
560 void llvm::AddLandingPadInfo(const LandingPadInst &I, MachineModuleInfo &MMI,
561 MachineBasicBlock *MBB) {
562 if (const auto *PF = dyn_cast<Function>(
563 I.getParent()->getParent()->getPersonalityFn()->stripPointerCasts()))
564 MMI.addPersonality(PF);
569 // FIXME: New EH - Add the clauses in reverse order. This isn't 100% correct,
570 // but we need to do it this way because of how the DWARF EH emitter
571 // processes the clauses.
572 for (unsigned i = I.getNumClauses(); i != 0; --i) {
573 Value *Val = I.getClause(i - 1);
574 if (I.isCatch(i - 1)) {
575 MMI.addCatchTypeInfo(MBB,
576 dyn_cast<GlobalValue>(Val->stripPointerCasts()));
578 // Add filters in a list.
579 Constant *CVal = cast<Constant>(Val);
580 SmallVector<const GlobalValue*, 4> FilterList;
581 for (User::op_iterator
582 II = CVal->op_begin(), IE = CVal->op_end(); II != IE; ++II)
583 FilterList.push_back(cast<GlobalValue>((*II)->stripPointerCasts()));
585 MMI.addFilterTypeInfo(MBB, FilterList);