1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DebugLoc.h"
51 #include "llvm/CodeGen/DwarfWriter.h"
52 #include "llvm/Analysis/DebugInfo.h"
53 #include "llvm/Target/TargetData.h"
54 #include "llvm/Target/TargetInstrInfo.h"
55 #include "llvm/Target/TargetLowering.h"
56 #include "llvm/Target/TargetMachine.h"
57 #include "SelectionDAGBuild.h"
60 unsigned FastISel::getRegForValue(Value *V) {
61 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
62 // Don't handle non-simple values in FastISel.
63 if (!RealVT.isSimple())
66 // Ignore illegal types. We must do this before looking up the value
67 // in ValueMap because Arguments are given virtual registers regardless
68 // of whether FastISel can handle them.
69 MVT::SimpleValueType VT = RealVT.getSimpleVT();
70 if (!TLI.isTypeLegal(VT)) {
71 // Promote MVT::i1 to a legal type though, because it's common and easy.
73 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
78 // Look up the value to see if we already have a register for it. We
79 // cache values defined by Instructions across blocks, and other values
80 // only locally. This is because Instructions already have the SSA
81 // def-dominatess-use requirement enforced.
82 if (ValueMap.count(V))
84 unsigned Reg = LocalValueMap[V];
88 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
89 if (CI->getValue().getActiveBits() <= 64)
90 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
91 } else if (isa<AllocaInst>(V)) {
92 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
93 } else if (isa<ConstantPointerNull>(V)) {
94 // Translate this as an integer zero so that it can be
95 // local-CSE'd with actual integer zeros.
96 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
101 const APFloat &Flt = CF->getValueAPF();
102 MVT IntVT = TLI.getPointerTy();
105 uint32_t IntBitWidth = IntVT.getSizeInBits();
107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
108 APFloat::rmTowardZero, &isExact);
110 APInt IntVal(IntBitWidth, 2, x);
112 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
114 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
117 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
118 if (!SelectOperator(CE, CE->getOpcode())) return 0;
119 Reg = LocalValueMap[CE];
120 } else if (isa<UndefValue>(V)) {
121 Reg = createResultReg(TLI.getRegClassFor(VT));
122 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
125 // If target-independent code couldn't handle the value, give target-specific
127 if (!Reg && isa<Constant>(V))
128 Reg = TargetMaterializeConstant(cast<Constant>(V));
130 // Don't cache constant materializations in the general ValueMap.
131 // To do so would require tracking what uses they dominate.
133 LocalValueMap[V] = Reg;
137 unsigned FastISel::lookUpRegForValue(Value *V) {
138 // Look up the value to see if we already have a register for it. We
139 // cache values defined by Instructions across blocks, and other values
140 // only locally. This is because Instructions already have the SSA
141 // def-dominatess-use requirement enforced.
142 if (ValueMap.count(V))
144 return LocalValueMap[V];
147 /// UpdateValueMap - Update the value map to include the new mapping for this
148 /// instruction, or insert an extra copy to get the result in a previous
149 /// determined register.
150 /// NOTE: This is only necessary because we might select a block that uses
151 /// a value before we select the block that defines the value. It might be
152 /// possible to fix this by selecting blocks in reverse postorder.
153 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
154 if (!isa<Instruction>(I)) {
155 LocalValueMap[I] = Reg;
159 unsigned &AssignedReg = ValueMap[I];
160 if (AssignedReg == 0)
162 else if (Reg != AssignedReg) {
163 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
164 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
165 Reg, RegClass, RegClass);
170 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
171 unsigned IdxN = getRegForValue(Idx);
173 // Unhandled operand. Halt "fast" selection and bail.
176 // If the index is smaller or larger than intptr_t, truncate or extend it.
177 MVT PtrVT = TLI.getPointerTy();
178 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
179 if (IdxVT.bitsLT(PtrVT))
180 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
181 ISD::SIGN_EXTEND, IdxN);
182 else if (IdxVT.bitsGT(PtrVT))
183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
184 ISD::TRUNCATE, IdxN);
188 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
189 /// which has an opcode which directly corresponds to the given ISD opcode.
191 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
192 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
193 if (VT == MVT::Other || !VT.isSimple())
194 // Unhandled type. Halt "fast" selection and bail.
197 // We only handle legal types. For example, on x86-32 the instruction
198 // selector contains all of the 64-bit instructions from x86-64,
199 // under the assumption that i64 won't be used if the target doesn't
201 if (!TLI.isTypeLegal(VT)) {
202 // MVT::i1 is special. Allow AND, OR, or XOR because they
203 // don't require additional zeroing, which makes them easy.
205 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
206 ISDOpcode == ISD::XOR))
207 VT = TLI.getTypeToTransformTo(VT);
212 unsigned Op0 = getRegForValue(I->getOperand(0));
214 // Unhandled operand. Halt "fast" selection and bail.
217 // Check if the second operand is a constant and handle it appropriately.
218 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
219 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
220 ISDOpcode, Op0, CI->getZExtValue());
221 if (ResultReg != 0) {
222 // We successfully emitted code for the given LLVM Instruction.
223 UpdateValueMap(I, ResultReg);
228 // Check if the second operand is a constant float.
229 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
230 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
232 if (ResultReg != 0) {
233 // We successfully emitted code for the given LLVM Instruction.
234 UpdateValueMap(I, ResultReg);
239 unsigned Op1 = getRegForValue(I->getOperand(1));
241 // Unhandled operand. Halt "fast" selection and bail.
244 // Now we have both operands in registers. Emit the instruction.
245 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
246 ISDOpcode, Op0, Op1);
248 // Target-specific code wasn't able to find a machine opcode for
249 // the given ISD opcode and type. Halt "fast" selection and bail.
252 // We successfully emitted code for the given LLVM Instruction.
253 UpdateValueMap(I, ResultReg);
257 bool FastISel::SelectGetElementPtr(User *I) {
258 unsigned N = getRegForValue(I->getOperand(0));
260 // Unhandled operand. Halt "fast" selection and bail.
263 const Type *Ty = I->getOperand(0)->getType();
264 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
265 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
268 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
269 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
272 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
273 // FIXME: This can be optimized by combining the add with a
275 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
277 // Unhandled operand. Halt "fast" selection and bail.
280 Ty = StTy->getElementType(Field);
282 Ty = cast<SequentialType>(Ty)->getElementType();
284 // If this is a constant subscript, handle it quickly.
285 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
286 if (CI->getZExtValue() == 0) continue;
288 TD.getTypePaddedSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
289 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
291 // Unhandled operand. Halt "fast" selection and bail.
296 // N = N + Idx * ElementSize;
297 uint64_t ElementSize = TD.getTypePaddedSize(Ty);
298 unsigned IdxN = getRegForGEPIndex(Idx);
300 // Unhandled operand. Halt "fast" selection and bail.
303 if (ElementSize != 1) {
304 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
306 // Unhandled operand. Halt "fast" selection and bail.
309 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
311 // Unhandled operand. Halt "fast" selection and bail.
316 // We successfully emitted code for the given LLVM Instruction.
317 UpdateValueMap(I, N);
321 bool FastISel::SelectCall(User *I) {
322 Function *F = cast<CallInst>(I)->getCalledFunction();
323 if (!F) return false;
325 unsigned IID = F->getIntrinsicID();
328 case Intrinsic::dbg_stoppoint: {
329 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
330 if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
331 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
332 unsigned Line = SPI->getLine();
333 unsigned Col = SPI->getColumn();
334 unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col);
335 setCurDebugLoc(DebugLoc::get(Idx));
339 case Intrinsic::dbg_region_start: {
340 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
341 if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) &&
342 DW && DW->ShouldEmitDwarfDebug()) {
344 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
345 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
346 BuildMI(MBB, DL, II).addImm(ID);
350 case Intrinsic::dbg_region_end: {
351 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
352 if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) &&
353 DW && DW->ShouldEmitDwarfDebug()) {
355 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
356 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
357 // This is end of an inlined function.
358 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
359 ID = DW->RecordInlinedFnEnd(Subprogram);
361 // Returned ID is 0 if this is unbalanced "end of inlined
362 // scope". This could happen if optimizer eats dbg intrinsics
363 // or "beginning of inlined scope" is not recoginized due to
364 // missing location info. In such cases, do ignore this region.end.
365 BuildMI(MBB, DL, II).addImm(ID);
367 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
368 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
369 BuildMI(MBB, DL, II).addImm(ID);
374 case Intrinsic::dbg_func_start: {
375 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
376 Value *SP = FSI->getSubprogram();
377 if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None))
380 // llvm.dbg.func.start implicitly defines a dbg_stoppoint which is what
381 // (most?) gdb expects.
382 DebugLoc PrevLoc = DL;
383 DISubprogram Subprogram(cast<GlobalVariable>(SP));
384 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
386 if (!Subprogram.describes(MF.getFunction())) {
387 // This is a beginning of an inlined function.
389 // If llvm.dbg.func.start is seen in a new block before any
390 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
391 // FIXME : Why DebugLoc is reset at the beginning of each block ?
392 if (PrevLoc.isUnknown())
394 // Record the source line.
395 unsigned Line = Subprogram.getLineNumber();
396 setCurDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
397 CompileUnit.getGV(), Line, 0)));
399 if (DW && DW->ShouldEmitDwarfDebug()) {
400 unsigned LabelID = MMI->NextLabelID();
401 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
402 BuildMI(MBB, DL, II).addImm(LabelID);
403 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
404 DW->RecordInlinedFnStart(FSI, Subprogram, LabelID,
405 DICompileUnit(PrevLocTpl.CompileUnit),
410 // Record the source line.
411 unsigned Line = Subprogram.getLineNumber();
412 MF.setDefaultDebugLoc(DebugLoc::get(MF.getOrCreateDebugLocID(
413 CompileUnit.getGV(), Line, 0)));
414 if (DW && DW->ShouldEmitDwarfDebug()) {
415 // llvm.dbg.func_start also defines beginning of function scope.
416 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
422 case Intrinsic::dbg_declare: {
423 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
424 Value *Variable = DI->getVariable();
425 if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) &&
426 DW && DW->ShouldEmitDwarfDebug()) {
427 // Determine the address of the declared object.
428 Value *Address = DI->getAddress();
429 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
430 Address = BCI->getOperand(0);
431 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
432 // Don't handle byval struct arguments or VLAs, for example.
434 DenseMap<const AllocaInst*, int>::iterator SI =
435 StaticAllocaMap.find(AI);
436 if (SI == StaticAllocaMap.end()) break; // VLAs.
439 // Determine the debug globalvariable.
440 GlobalValue *GV = cast<GlobalVariable>(Variable);
442 // Build the DECLARE instruction.
443 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
444 MachineInstr *DeclareMI
445 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
446 DIVariable DV(cast<GlobalVariable>(GV));
448 // This is a local variable
449 DW->RecordVariableScope(DV, DeclareMI);
454 case Intrinsic::eh_exception: {
455 MVT VT = TLI.getValueType(I->getType());
456 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
458 case TargetLowering::Expand: {
459 if (!MBB->isLandingPad()) {
460 // FIXME: Mark exception register as live in. Hack for PR1508.
461 unsigned Reg = TLI.getExceptionAddressRegister();
462 if (Reg) MBB->addLiveIn(Reg);
464 unsigned Reg = TLI.getExceptionAddressRegister();
465 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
466 unsigned ResultReg = createResultReg(RC);
467 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
469 assert(InsertedCopy && "Can't copy address registers!");
470 InsertedCopy = InsertedCopy;
471 UpdateValueMap(I, ResultReg);
477 case Intrinsic::eh_selector_i32:
478 case Intrinsic::eh_selector_i64: {
479 MVT VT = TLI.getValueType(I->getType());
480 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
482 case TargetLowering::Expand: {
483 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
484 MVT::i32 : MVT::i64);
487 if (MBB->isLandingPad())
488 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
491 CatchInfoLost.insert(cast<CallInst>(I));
493 // FIXME: Mark exception selector register as live in. Hack for PR1508.
494 unsigned Reg = TLI.getExceptionSelectorRegister();
495 if (Reg) MBB->addLiveIn(Reg);
498 unsigned Reg = TLI.getExceptionSelectorRegister();
499 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
500 unsigned ResultReg = createResultReg(RC);
501 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
503 assert(InsertedCopy && "Can't copy address registers!");
504 InsertedCopy = InsertedCopy;
505 UpdateValueMap(I, ResultReg);
508 getRegForValue(Constant::getNullValue(I->getType()));
509 UpdateValueMap(I, ResultReg);
520 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
521 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
522 MVT DstVT = TLI.getValueType(I->getType());
524 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
525 DstVT == MVT::Other || !DstVT.isSimple())
526 // Unhandled type. Halt "fast" selection and bail.
529 // Check if the destination type is legal. Or as a special case,
530 // it may be i1 if we're doing a truncate because that's
531 // easy and somewhat common.
532 if (!TLI.isTypeLegal(DstVT))
533 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
534 // Unhandled type. Halt "fast" selection and bail.
537 // Check if the source operand is legal. Or as a special case,
538 // it may be i1 if we're doing zero-extension because that's
539 // easy and somewhat common.
540 if (!TLI.isTypeLegal(SrcVT))
541 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
542 // Unhandled type. Halt "fast" selection and bail.
545 unsigned InputReg = getRegForValue(I->getOperand(0));
547 // Unhandled operand. Halt "fast" selection and bail.
550 // If the operand is i1, arrange for the high bits in the register to be zero.
551 if (SrcVT == MVT::i1) {
552 SrcVT = TLI.getTypeToTransformTo(SrcVT);
553 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
557 // If the result is i1, truncate to the target's type for i1 first.
558 if (DstVT == MVT::i1)
559 DstVT = TLI.getTypeToTransformTo(DstVT);
561 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
568 UpdateValueMap(I, ResultReg);
572 bool FastISel::SelectBitCast(User *I) {
573 // If the bitcast doesn't change the type, just use the operand value.
574 if (I->getType() == I->getOperand(0)->getType()) {
575 unsigned Reg = getRegForValue(I->getOperand(0));
578 UpdateValueMap(I, Reg);
582 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
583 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
584 MVT DstVT = TLI.getValueType(I->getType());
586 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
587 DstVT == MVT::Other || !DstVT.isSimple() ||
588 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
589 // Unhandled type. Halt "fast" selection and bail.
592 unsigned Op0 = getRegForValue(I->getOperand(0));
594 // Unhandled operand. Halt "fast" selection and bail.
597 // First, try to perform the bitcast by inserting a reg-reg copy.
598 unsigned ResultReg = 0;
599 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
600 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
601 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
602 ResultReg = createResultReg(DstClass);
604 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
605 Op0, DstClass, SrcClass);
610 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
612 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
613 ISD::BIT_CONVERT, Op0);
618 UpdateValueMap(I, ResultReg);
623 FastISel::SelectInstruction(Instruction *I) {
624 return SelectOperator(I, I->getOpcode());
627 /// FastEmitBranch - Emit an unconditional branch to the given block,
628 /// unless it is the immediate (fall-through) successor, and update
631 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
632 MachineFunction::iterator NextMBB =
633 next(MachineFunction::iterator(MBB));
635 if (MBB->isLayoutSuccessor(MSucc)) {
636 // The unconditional fall-through case, which needs no instructions.
638 // The unconditional branch case.
639 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
641 MBB->addSuccessor(MSucc);
645 FastISel::SelectOperator(User *I, unsigned Opcode) {
647 case Instruction::Add: {
648 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
649 return SelectBinaryOp(I, Opc);
651 case Instruction::Sub: {
652 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
653 return SelectBinaryOp(I, Opc);
655 case Instruction::Mul: {
656 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
657 return SelectBinaryOp(I, Opc);
659 case Instruction::SDiv:
660 return SelectBinaryOp(I, ISD::SDIV);
661 case Instruction::UDiv:
662 return SelectBinaryOp(I, ISD::UDIV);
663 case Instruction::FDiv:
664 return SelectBinaryOp(I, ISD::FDIV);
665 case Instruction::SRem:
666 return SelectBinaryOp(I, ISD::SREM);
667 case Instruction::URem:
668 return SelectBinaryOp(I, ISD::UREM);
669 case Instruction::FRem:
670 return SelectBinaryOp(I, ISD::FREM);
671 case Instruction::Shl:
672 return SelectBinaryOp(I, ISD::SHL);
673 case Instruction::LShr:
674 return SelectBinaryOp(I, ISD::SRL);
675 case Instruction::AShr:
676 return SelectBinaryOp(I, ISD::SRA);
677 case Instruction::And:
678 return SelectBinaryOp(I, ISD::AND);
679 case Instruction::Or:
680 return SelectBinaryOp(I, ISD::OR);
681 case Instruction::Xor:
682 return SelectBinaryOp(I, ISD::XOR);
684 case Instruction::GetElementPtr:
685 return SelectGetElementPtr(I);
687 case Instruction::Br: {
688 BranchInst *BI = cast<BranchInst>(I);
690 if (BI->isUnconditional()) {
691 BasicBlock *LLVMSucc = BI->getSuccessor(0);
692 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
693 FastEmitBranch(MSucc);
697 // Conditional branches are not handed yet.
698 // Halt "fast" selection and bail.
702 case Instruction::Unreachable:
706 case Instruction::PHI:
707 // PHI nodes are already emitted.
710 case Instruction::Alloca:
711 // FunctionLowering has the static-sized case covered.
712 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
715 // Dynamic-sized alloca is not handled yet.
718 case Instruction::Call:
719 return SelectCall(I);
721 case Instruction::BitCast:
722 return SelectBitCast(I);
724 case Instruction::FPToSI:
725 return SelectCast(I, ISD::FP_TO_SINT);
726 case Instruction::ZExt:
727 return SelectCast(I, ISD::ZERO_EXTEND);
728 case Instruction::SExt:
729 return SelectCast(I, ISD::SIGN_EXTEND);
730 case Instruction::Trunc:
731 return SelectCast(I, ISD::TRUNCATE);
732 case Instruction::SIToFP:
733 return SelectCast(I, ISD::SINT_TO_FP);
735 case Instruction::IntToPtr: // Deliberate fall-through.
736 case Instruction::PtrToInt: {
737 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
738 MVT DstVT = TLI.getValueType(I->getType());
739 if (DstVT.bitsGT(SrcVT))
740 return SelectCast(I, ISD::ZERO_EXTEND);
741 if (DstVT.bitsLT(SrcVT))
742 return SelectCast(I, ISD::TRUNCATE);
743 unsigned Reg = getRegForValue(I->getOperand(0));
744 if (Reg == 0) return false;
745 UpdateValueMap(I, Reg);
750 // Unhandled instruction. Halt "fast" selection and bail.
755 FastISel::FastISel(MachineFunction &mf,
756 MachineModuleInfo *mmi,
758 DenseMap<const Value *, unsigned> &vm,
759 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
760 DenseMap<const AllocaInst *, int> &am
762 , SmallSet<Instruction*, 8> &cil
775 MRI(MF.getRegInfo()),
776 MFI(*MF.getFrameInfo()),
777 MCP(*MF.getConstantPool()),
779 TD(*TM.getTargetData()),
780 TII(*TM.getInstrInfo()),
781 TLI(*TM.getTargetLowering()) {
784 FastISel::~FastISel() {}
786 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
791 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
792 ISD::NodeType, unsigned /*Op0*/) {
796 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
797 ISD::NodeType, unsigned /*Op0*/,
802 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
803 ISD::NodeType, uint64_t /*Imm*/) {
807 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
808 ISD::NodeType, ConstantFP * /*FPImm*/) {
812 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
813 ISD::NodeType, unsigned /*Op0*/,
818 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
819 ISD::NodeType, unsigned /*Op0*/,
820 ConstantFP * /*FPImm*/) {
824 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
826 unsigned /*Op0*/, unsigned /*Op1*/,
831 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
832 /// to emit an instruction with an immediate operand using FastEmit_ri.
833 /// If that fails, it materializes the immediate into a register and try
834 /// FastEmit_rr instead.
835 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
836 unsigned Op0, uint64_t Imm,
837 MVT::SimpleValueType ImmType) {
838 // First check if immediate type is legal. If not, we can't use the ri form.
839 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
842 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
843 if (MaterialReg == 0)
845 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
848 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
849 /// to emit an instruction with a floating-point immediate operand using
850 /// FastEmit_rf. If that fails, it materializes the immediate into a register
851 /// and try FastEmit_rr instead.
852 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
853 unsigned Op0, ConstantFP *FPImm,
854 MVT::SimpleValueType ImmType) {
855 // First check if immediate type is legal. If not, we can't use the rf form.
856 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
860 // Materialize the constant in a register.
861 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
862 if (MaterialReg == 0) {
863 // If the target doesn't have a way to directly enter a floating-point
864 // value into a register, use an alternate approach.
865 // TODO: The current approach only supports floating-point constants
866 // that can be constructed by conversion from integer values. This should
867 // be replaced by code that creates a load from a constant-pool entry,
868 // which will require some target-specific work.
869 const APFloat &Flt = FPImm->getValueAPF();
870 MVT IntVT = TLI.getPointerTy();
873 uint32_t IntBitWidth = IntVT.getSizeInBits();
875 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
876 APFloat::rmTowardZero, &isExact);
879 APInt IntVal(IntBitWidth, 2, x);
881 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
882 ISD::Constant, IntVal.getZExtValue());
885 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
886 ISD::SINT_TO_FP, IntegerReg);
887 if (MaterialReg == 0)
890 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
893 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
894 return MRI.createVirtualRegister(RC);
897 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
898 const TargetRegisterClass* RC) {
899 unsigned ResultReg = createResultReg(RC);
900 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
902 BuildMI(MBB, DL, II, ResultReg);
906 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
907 const TargetRegisterClass *RC,
909 unsigned ResultReg = createResultReg(RC);
910 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
912 if (II.getNumDefs() >= 1)
913 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
915 BuildMI(MBB, DL, II).addReg(Op0);
916 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
917 II.ImplicitDefs[0], RC, RC);
925 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
926 const TargetRegisterClass *RC,
927 unsigned Op0, unsigned Op1) {
928 unsigned ResultReg = createResultReg(RC);
929 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
931 if (II.getNumDefs() >= 1)
932 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
934 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
935 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
936 II.ImplicitDefs[0], RC, RC);
943 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
944 const TargetRegisterClass *RC,
945 unsigned Op0, uint64_t Imm) {
946 unsigned ResultReg = createResultReg(RC);
947 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
949 if (II.getNumDefs() >= 1)
950 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
952 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
953 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
954 II.ImplicitDefs[0], RC, RC);
961 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
962 const TargetRegisterClass *RC,
963 unsigned Op0, ConstantFP *FPImm) {
964 unsigned ResultReg = createResultReg(RC);
965 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
967 if (II.getNumDefs() >= 1)
968 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
970 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
971 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
972 II.ImplicitDefs[0], RC, RC);
979 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
980 const TargetRegisterClass *RC,
981 unsigned Op0, unsigned Op1, uint64_t Imm) {
982 unsigned ResultReg = createResultReg(RC);
983 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
985 if (II.getNumDefs() >= 1)
986 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
988 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
989 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
990 II.ImplicitDefs[0], RC, RC);
997 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
998 const TargetRegisterClass *RC,
1000 unsigned ResultReg = createResultReg(RC);
1001 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1003 if (II.getNumDefs() >= 1)
1004 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1006 BuildMI(MBB, DL, II).addImm(Imm);
1007 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1008 II.ImplicitDefs[0], RC, RC);
1015 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
1016 unsigned Op0, uint32_t Idx) {
1017 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1019 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1020 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1022 if (II.getNumDefs() >= 1)
1023 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1025 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1026 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1027 II.ImplicitDefs[0], RC, RC);
1034 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1035 /// with all but the least significant bit set to zero.
1036 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
1037 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);