1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
61 // Don't handle non-simple values in FastISel.
62 if (!RealVT.isSimple())
65 // Ignore illegal types. We must do this before looking up the value
66 // in ValueMap because Arguments are given virtual registers regardless
67 // of whether FastISel can handle them.
68 MVT VT = RealVT.getSimpleVT();
69 if (!TLI.isTypeLegal(VT)) {
70 // Promote MVT::i1 to a legal type though, because it's common and easy.
72 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT();
77 // Look up the value to see if we already have a register for it. We
78 // cache values defined by Instructions across blocks, and other values
79 // only locally. This is because Instructions already have the SSA
80 // def-dominatess-use requirement enforced.
81 if (ValueMap.count(V))
83 unsigned Reg = LocalValueMap[V];
87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
88 if (CI->getValue().getActiveBits() <= 64)
89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
90 } else if (isa<AllocaInst>(V)) {
91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
92 } else if (isa<ConstantPointerNull>(V)) {
93 // Translate this as an integer zero so that it can be
94 // local-CSE'd with actual integer zeros.
96 getRegForValue(Constant::getNullValue(TD.getIntPtrType(V->getContext())));
97 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
98 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
101 const APFloat &Flt = CF->getValueAPF();
102 EVT IntVT = TLI.getPointerTy();
105 uint32_t IntBitWidth = IntVT.getSizeInBits();
107 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
108 APFloat::rmTowardZero, &isExact);
110 APInt IntVal(IntBitWidth, 2, x);
112 unsigned IntegerReg =
113 getRegForValue(ConstantInt::get(V->getContext(), IntVal));
115 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
118 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
119 if (!SelectOperator(CE, CE->getOpcode())) return 0;
120 Reg = LocalValueMap[CE];
121 } else if (isa<UndefValue>(V)) {
122 Reg = createResultReg(TLI.getRegClassFor(VT));
123 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
126 // If target-independent code couldn't handle the value, give target-specific
128 if (!Reg && isa<Constant>(V))
129 Reg = TargetMaterializeConstant(cast<Constant>(V));
131 // Don't cache constant materializations in the general ValueMap.
132 // To do so would require tracking what uses they dominate.
134 LocalValueMap[V] = Reg;
138 unsigned FastISel::lookUpRegForValue(Value *V) {
139 // Look up the value to see if we already have a register for it. We
140 // cache values defined by Instructions across blocks, and other values
141 // only locally. This is because Instructions already have the SSA
142 // def-dominatess-use requirement enforced.
143 if (ValueMap.count(V))
145 return LocalValueMap[V];
148 /// UpdateValueMap - Update the value map to include the new mapping for this
149 /// instruction, or insert an extra copy to get the result in a previous
150 /// determined register.
151 /// NOTE: This is only necessary because we might select a block that uses
152 /// a value before we select the block that defines the value. It might be
153 /// possible to fix this by selecting blocks in reverse postorder.
154 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
155 if (!isa<Instruction>(I)) {
156 LocalValueMap[I] = Reg;
160 unsigned &AssignedReg = ValueMap[I];
161 if (AssignedReg == 0)
163 else if (Reg != AssignedReg) {
164 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
165 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
166 Reg, RegClass, RegClass);
171 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
172 unsigned IdxN = getRegForValue(Idx);
174 // Unhandled operand. Halt "fast" selection and bail.
177 // If the index is smaller or larger than intptr_t, truncate or extend it.
178 MVT PtrVT = TLI.getPointerTy();
179 EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
180 if (IdxVT.bitsLT(PtrVT))
181 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN);
182 else if (IdxVT.bitsGT(PtrVT))
183 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN);
187 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
188 /// which has an opcode which directly corresponds to the given ISD opcode.
190 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
191 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
192 if (VT == MVT::Other || !VT.isSimple())
193 // Unhandled type. Halt "fast" selection and bail.
196 // We only handle legal types. For example, on x86-32 the instruction
197 // selector contains all of the 64-bit instructions from x86-64,
198 // under the assumption that i64 won't be used if the target doesn't
200 if (!TLI.isTypeLegal(VT)) {
201 // MVT::i1 is special. Allow AND, OR, or XOR because they
202 // don't require additional zeroing, which makes them easy.
204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
205 ISDOpcode == ISD::XOR))
206 VT = TLI.getTypeToTransformTo(I->getContext(), VT);
211 unsigned Op0 = getRegForValue(I->getOperand(0));
213 // Unhandled operand. Halt "fast" selection and bail.
216 // Check if the second operand is a constant and handle it appropriately.
217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
219 ISDOpcode, Op0, CI->getZExtValue());
220 if (ResultReg != 0) {
221 // We successfully emitted code for the given LLVM Instruction.
222 UpdateValueMap(I, ResultReg);
227 // Check if the second operand is a constant float.
228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
231 if (ResultReg != 0) {
232 // We successfully emitted code for the given LLVM Instruction.
233 UpdateValueMap(I, ResultReg);
238 unsigned Op1 = getRegForValue(I->getOperand(1));
240 // Unhandled operand. Halt "fast" selection and bail.
243 // Now we have both operands in registers. Emit the instruction.
244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
245 ISDOpcode, Op0, Op1);
247 // Target-specific code wasn't able to find a machine opcode for
248 // the given ISD opcode and type. Halt "fast" selection and bail.
251 // We successfully emitted code for the given LLVM Instruction.
252 UpdateValueMap(I, ResultReg);
256 bool FastISel::SelectGetElementPtr(User *I) {
257 unsigned N = getRegForValue(I->getOperand(0));
259 // Unhandled operand. Halt "fast" selection and bail.
262 const Type *Ty = I->getOperand(0)->getType();
263 MVT VT = TLI.getPointerTy();
264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
272 // FIXME: This can be optimized by combining the add with a
274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
276 // Unhandled operand. Halt "fast" selection and bail.
279 Ty = StTy->getElementType(Field);
281 Ty = cast<SequentialType>(Ty)->getElementType();
283 // If this is a constant subscript, handle it quickly.
284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
285 if (CI->getZExtValue() == 0) continue;
287 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
290 // Unhandled operand. Halt "fast" selection and bail.
295 // N = N + Idx * ElementSize;
296 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
297 unsigned IdxN = getRegForGEPIndex(Idx);
299 // Unhandled operand. Halt "fast" selection and bail.
302 if (ElementSize != 1) {
303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
305 // Unhandled operand. Halt "fast" selection and bail.
308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
310 // Unhandled operand. Halt "fast" selection and bail.
315 // We successfully emitted code for the given LLVM Instruction.
316 UpdateValueMap(I, N);
320 bool FastISel::SelectCall(User *I) {
321 Function *F = cast<CallInst>(I)->getCalledFunction();
322 if (!F) return false;
324 unsigned IID = F->getIntrinsicID();
327 case Intrinsic::dbg_stoppoint: {
328 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
329 if (isValidDebugInfoIntrinsic(*SPI, CodeGenOpt::None))
330 setCurDebugLoc(ExtractDebugLocation(*SPI, MF.getDebugLocInfo()));
333 case Intrinsic::dbg_region_start: {
334 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
335 if (isValidDebugInfoIntrinsic(*RSI, CodeGenOpt::None) && DW
336 && DW->ShouldEmitDwarfDebug()) {
338 DW->RecordRegionStart(RSI->getContext());
339 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
340 BuildMI(MBB, DL, II).addImm(ID);
344 case Intrinsic::dbg_region_end: {
345 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
346 if (isValidDebugInfoIntrinsic(*REI, CodeGenOpt::None) && DW
347 && DW->ShouldEmitDwarfDebug()) {
349 DISubprogram Subprogram(REI->getContext());
350 if (isInlinedFnEnd(*REI, MF.getFunction())) {
351 // This is end of an inlined function.
352 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
353 ID = DW->RecordInlinedFnEnd(Subprogram);
355 // Returned ID is 0 if this is unbalanced "end of inlined
356 // scope". This could happen if optimizer eats dbg intrinsics
357 // or "beginning of inlined scope" is not recoginized due to
358 // missing location info. In such cases, ignore this region.end.
359 BuildMI(MBB, DL, II).addImm(ID);
361 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
362 ID = DW->RecordRegionEnd(REI->getContext());
363 BuildMI(MBB, DL, II).addImm(ID);
368 case Intrinsic::dbg_func_start: {
369 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
370 if (!isValidDebugInfoIntrinsic(*FSI, CodeGenOpt::None) || !DW
371 || !DW->ShouldEmitDwarfDebug())
374 if (isInlinedFnStart(*FSI, MF.getFunction())) {
375 // This is a beginning of an inlined function.
377 // If llvm.dbg.func.start is seen in a new block before any
378 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
379 // FIXME : Why DebugLoc is reset at the beginning of each block ?
380 DebugLoc PrevLoc = DL;
381 if (PrevLoc.isUnknown())
383 // Record the source line.
384 setCurDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
386 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
387 DISubprogram SP(FSI->getSubprogram());
388 unsigned LabelID = DW->RecordInlinedFnStart(SP,
389 DICompileUnit(PrevLocTpl.CompileUnit),
392 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
393 BuildMI(MBB, DL, II).addImm(LabelID);
397 // This is a beginning of a new function.
398 MF.setDefaultDebugLoc(ExtractDebugLocation(*FSI, MF.getDebugLocInfo()));
400 // llvm.dbg.func_start also defines beginning of function scope.
401 DW->RecordRegionStart(FSI->getSubprogram());
404 case Intrinsic::dbg_declare: {
405 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
406 if (!isValidDebugInfoIntrinsic(*DI, CodeGenOpt::None) || !DW
407 || !DW->ShouldEmitDwarfDebug())
410 Value *Address = DI->getAddress();
411 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
412 Address = BCI->getOperand(0);
413 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
414 // Don't handle byval struct arguments or VLAs, for example.
416 DenseMap<const AllocaInst*, int>::iterator SI =
417 StaticAllocaMap.find(AI);
418 if (SI == StaticAllocaMap.end()) break; // VLAs.
421 MetadataContext &TheMetadata = AI->getContext().getMetadata();
422 unsigned MDDbgKind = TheMetadata.getMDKind("dbg");
423 MDNode *AllocaLocation =
424 dyn_cast_or_null<MDNode>(TheMetadata.getMD(MDDbgKind, AI));
426 MMI->setVariableDbgInfo(DI->getVariable(), AllocaLocation, FI);
428 #ifndef ATTACH_DEBUG_INFO_TO_AN_INSN
429 DW->RecordVariable(DI->getVariable(), FI);
433 case Intrinsic::eh_exception: {
434 EVT VT = TLI.getValueType(I->getType());
435 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
437 case TargetLowering::Expand: {
438 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
439 unsigned Reg = TLI.getExceptionAddressRegister();
440 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
441 unsigned ResultReg = createResultReg(RC);
442 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
444 assert(InsertedCopy && "Can't copy address registers!");
445 InsertedCopy = InsertedCopy;
446 UpdateValueMap(I, ResultReg);
452 case Intrinsic::eh_selector_i32:
453 case Intrinsic::eh_selector_i64: {
454 EVT VT = TLI.getValueType(I->getType());
455 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
457 case TargetLowering::Expand: {
458 EVT VT = (IID == Intrinsic::eh_selector_i32 ?
459 MVT::i32 : MVT::i64);
462 if (MBB->isLandingPad())
463 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
466 CatchInfoLost.insert(cast<CallInst>(I));
468 // FIXME: Mark exception selector register as live in. Hack for PR1508.
469 unsigned Reg = TLI.getExceptionSelectorRegister();
470 if (Reg) MBB->addLiveIn(Reg);
473 unsigned Reg = TLI.getExceptionSelectorRegister();
474 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
475 unsigned ResultReg = createResultReg(RC);
476 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
478 assert(InsertedCopy && "Can't copy address registers!");
479 InsertedCopy = InsertedCopy;
480 UpdateValueMap(I, ResultReg);
483 getRegForValue(Constant::getNullValue(I->getType()));
484 UpdateValueMap(I, ResultReg);
495 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
496 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
497 EVT DstVT = TLI.getValueType(I->getType());
499 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
500 DstVT == MVT::Other || !DstVT.isSimple())
501 // Unhandled type. Halt "fast" selection and bail.
504 // Check if the destination type is legal. Or as a special case,
505 // it may be i1 if we're doing a truncate because that's
506 // easy and somewhat common.
507 if (!TLI.isTypeLegal(DstVT))
508 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
509 // Unhandled type. Halt "fast" selection and bail.
512 // Check if the source operand is legal. Or as a special case,
513 // it may be i1 if we're doing zero-extension because that's
514 // easy and somewhat common.
515 if (!TLI.isTypeLegal(SrcVT))
516 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
517 // Unhandled type. Halt "fast" selection and bail.
520 unsigned InputReg = getRegForValue(I->getOperand(0));
522 // Unhandled operand. Halt "fast" selection and bail.
525 // If the operand is i1, arrange for the high bits in the register to be zero.
526 if (SrcVT == MVT::i1) {
527 SrcVT = TLI.getTypeToTransformTo(I->getContext(), SrcVT);
528 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
532 // If the result is i1, truncate to the target's type for i1 first.
533 if (DstVT == MVT::i1)
534 DstVT = TLI.getTypeToTransformTo(I->getContext(), DstVT);
536 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
543 UpdateValueMap(I, ResultReg);
547 bool FastISel::SelectBitCast(User *I) {
548 // If the bitcast doesn't change the type, just use the operand value.
549 if (I->getType() == I->getOperand(0)->getType()) {
550 unsigned Reg = getRegForValue(I->getOperand(0));
553 UpdateValueMap(I, Reg);
557 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
558 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
559 EVT DstVT = TLI.getValueType(I->getType());
561 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
562 DstVT == MVT::Other || !DstVT.isSimple() ||
563 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
564 // Unhandled type. Halt "fast" selection and bail.
567 unsigned Op0 = getRegForValue(I->getOperand(0));
569 // Unhandled operand. Halt "fast" selection and bail.
572 // First, try to perform the bitcast by inserting a reg-reg copy.
573 unsigned ResultReg = 0;
574 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
575 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
576 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
577 ResultReg = createResultReg(DstClass);
579 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
580 Op0, DstClass, SrcClass);
585 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
587 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
588 ISD::BIT_CONVERT, Op0);
593 UpdateValueMap(I, ResultReg);
598 FastISel::SelectInstruction(Instruction *I) {
599 return SelectOperator(I, I->getOpcode());
602 /// FastEmitBranch - Emit an unconditional branch to the given block,
603 /// unless it is the immediate (fall-through) successor, and update
606 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
607 MachineFunction::iterator NextMBB =
608 next(MachineFunction::iterator(MBB));
610 if (MBB->isLayoutSuccessor(MSucc)) {
611 // The unconditional fall-through case, which needs no instructions.
613 // The unconditional branch case.
614 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
616 MBB->addSuccessor(MSucc);
619 /// SelectFNeg - Emit an FNeg operation.
622 FastISel::SelectFNeg(User *I) {
623 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
624 if (OpReg == 0) return false;
626 // If the target has ISD::FNEG, use it.
627 EVT VT = TLI.getValueType(I->getType());
628 unsigned ResultReg = FastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(),
630 if (ResultReg != 0) {
631 UpdateValueMap(I, ResultReg);
635 // Bitcast the value to integer, twiddle the sign bit with xor,
636 // and then bitcast it back to floating-point.
637 if (VT.getSizeInBits() > 64) return false;
638 EVT IntVT = EVT::getIntegerVT(I->getContext(), VT.getSizeInBits());
639 if (!TLI.isTypeLegal(IntVT))
642 unsigned IntReg = FastEmit_r(VT.getSimpleVT(), IntVT.getSimpleVT(),
643 ISD::BIT_CONVERT, OpReg);
647 unsigned IntResultReg = FastEmit_ri_(IntVT.getSimpleVT(), ISD::XOR, IntReg,
648 UINT64_C(1) << (VT.getSizeInBits()-1),
649 IntVT.getSimpleVT());
650 if (IntResultReg == 0)
653 ResultReg = FastEmit_r(IntVT.getSimpleVT(), VT.getSimpleVT(),
654 ISD::BIT_CONVERT, IntResultReg);
658 UpdateValueMap(I, ResultReg);
663 FastISel::SelectOperator(User *I, unsigned Opcode) {
665 case Instruction::Add:
666 return SelectBinaryOp(I, ISD::ADD);
667 case Instruction::FAdd:
668 return SelectBinaryOp(I, ISD::FADD);
669 case Instruction::Sub:
670 return SelectBinaryOp(I, ISD::SUB);
671 case Instruction::FSub:
672 // FNeg is currently represented in LLVM IR as a special case of FSub.
673 if (BinaryOperator::isFNeg(I))
674 return SelectFNeg(I);
675 return SelectBinaryOp(I, ISD::FSUB);
676 case Instruction::Mul:
677 return SelectBinaryOp(I, ISD::MUL);
678 case Instruction::FMul:
679 return SelectBinaryOp(I, ISD::FMUL);
680 case Instruction::SDiv:
681 return SelectBinaryOp(I, ISD::SDIV);
682 case Instruction::UDiv:
683 return SelectBinaryOp(I, ISD::UDIV);
684 case Instruction::FDiv:
685 return SelectBinaryOp(I, ISD::FDIV);
686 case Instruction::SRem:
687 return SelectBinaryOp(I, ISD::SREM);
688 case Instruction::URem:
689 return SelectBinaryOp(I, ISD::UREM);
690 case Instruction::FRem:
691 return SelectBinaryOp(I, ISD::FREM);
692 case Instruction::Shl:
693 return SelectBinaryOp(I, ISD::SHL);
694 case Instruction::LShr:
695 return SelectBinaryOp(I, ISD::SRL);
696 case Instruction::AShr:
697 return SelectBinaryOp(I, ISD::SRA);
698 case Instruction::And:
699 return SelectBinaryOp(I, ISD::AND);
700 case Instruction::Or:
701 return SelectBinaryOp(I, ISD::OR);
702 case Instruction::Xor:
703 return SelectBinaryOp(I, ISD::XOR);
705 case Instruction::GetElementPtr:
706 return SelectGetElementPtr(I);
708 case Instruction::Br: {
709 BranchInst *BI = cast<BranchInst>(I);
711 if (BI->isUnconditional()) {
712 BasicBlock *LLVMSucc = BI->getSuccessor(0);
713 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
714 FastEmitBranch(MSucc);
718 // Conditional branches are not handed yet.
719 // Halt "fast" selection and bail.
723 case Instruction::Unreachable:
727 case Instruction::PHI:
728 // PHI nodes are already emitted.
731 case Instruction::Alloca:
732 // FunctionLowering has the static-sized case covered.
733 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
736 // Dynamic-sized alloca is not handled yet.
739 case Instruction::Call:
740 return SelectCall(I);
742 case Instruction::BitCast:
743 return SelectBitCast(I);
745 case Instruction::FPToSI:
746 return SelectCast(I, ISD::FP_TO_SINT);
747 case Instruction::ZExt:
748 return SelectCast(I, ISD::ZERO_EXTEND);
749 case Instruction::SExt:
750 return SelectCast(I, ISD::SIGN_EXTEND);
751 case Instruction::Trunc:
752 return SelectCast(I, ISD::TRUNCATE);
753 case Instruction::SIToFP:
754 return SelectCast(I, ISD::SINT_TO_FP);
756 case Instruction::IntToPtr: // Deliberate fall-through.
757 case Instruction::PtrToInt: {
758 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
759 EVT DstVT = TLI.getValueType(I->getType());
760 if (DstVT.bitsGT(SrcVT))
761 return SelectCast(I, ISD::ZERO_EXTEND);
762 if (DstVT.bitsLT(SrcVT))
763 return SelectCast(I, ISD::TRUNCATE);
764 unsigned Reg = getRegForValue(I->getOperand(0));
765 if (Reg == 0) return false;
766 UpdateValueMap(I, Reg);
771 // Unhandled instruction. Halt "fast" selection and bail.
776 FastISel::FastISel(MachineFunction &mf,
777 MachineModuleInfo *mmi,
779 DenseMap<const Value *, unsigned> &vm,
780 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
781 DenseMap<const AllocaInst *, int> &am
783 , SmallSet<Instruction*, 8> &cil
796 MRI(MF.getRegInfo()),
797 MFI(*MF.getFrameInfo()),
798 MCP(*MF.getConstantPool()),
800 TD(*TM.getTargetData()),
801 TII(*TM.getInstrInfo()),
802 TLI(*TM.getTargetLowering()) {
805 FastISel::~FastISel() {}
807 unsigned FastISel::FastEmit_(MVT, MVT,
812 unsigned FastISel::FastEmit_r(MVT, MVT,
813 ISD::NodeType, unsigned /*Op0*/) {
817 unsigned FastISel::FastEmit_rr(MVT, MVT,
818 ISD::NodeType, unsigned /*Op0*/,
823 unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
827 unsigned FastISel::FastEmit_f(MVT, MVT,
828 ISD::NodeType, ConstantFP * /*FPImm*/) {
832 unsigned FastISel::FastEmit_ri(MVT, MVT,
833 ISD::NodeType, unsigned /*Op0*/,
838 unsigned FastISel::FastEmit_rf(MVT, MVT,
839 ISD::NodeType, unsigned /*Op0*/,
840 ConstantFP * /*FPImm*/) {
844 unsigned FastISel::FastEmit_rri(MVT, MVT,
846 unsigned /*Op0*/, unsigned /*Op1*/,
851 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
852 /// to emit an instruction with an immediate operand using FastEmit_ri.
853 /// If that fails, it materializes the immediate into a register and try
854 /// FastEmit_rr instead.
855 unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
856 unsigned Op0, uint64_t Imm,
858 // First check if immediate type is legal. If not, we can't use the ri form.
859 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
862 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
863 if (MaterialReg == 0)
865 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
868 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
869 /// to emit an instruction with a floating-point immediate operand using
870 /// FastEmit_rf. If that fails, it materializes the immediate into a register
871 /// and try FastEmit_rr instead.
872 unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
873 unsigned Op0, ConstantFP *FPImm,
875 // First check if immediate type is legal. If not, we can't use the rf form.
876 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
880 // Materialize the constant in a register.
881 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
882 if (MaterialReg == 0) {
883 // If the target doesn't have a way to directly enter a floating-point
884 // value into a register, use an alternate approach.
885 // TODO: The current approach only supports floating-point constants
886 // that can be constructed by conversion from integer values. This should
887 // be replaced by code that creates a load from a constant-pool entry,
888 // which will require some target-specific work.
889 const APFloat &Flt = FPImm->getValueAPF();
890 EVT IntVT = TLI.getPointerTy();
893 uint32_t IntBitWidth = IntVT.getSizeInBits();
895 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
896 APFloat::rmTowardZero, &isExact);
899 APInt IntVal(IntBitWidth, 2, x);
901 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
902 ISD::Constant, IntVal.getZExtValue());
905 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
906 ISD::SINT_TO_FP, IntegerReg);
907 if (MaterialReg == 0)
910 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
913 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
914 return MRI.createVirtualRegister(RC);
917 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
918 const TargetRegisterClass* RC) {
919 unsigned ResultReg = createResultReg(RC);
920 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
922 BuildMI(MBB, DL, II, ResultReg);
926 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
927 const TargetRegisterClass *RC,
929 unsigned ResultReg = createResultReg(RC);
930 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
932 if (II.getNumDefs() >= 1)
933 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
935 BuildMI(MBB, DL, II).addReg(Op0);
936 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
937 II.ImplicitDefs[0], RC, RC);
945 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
946 const TargetRegisterClass *RC,
947 unsigned Op0, unsigned Op1) {
948 unsigned ResultReg = createResultReg(RC);
949 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
951 if (II.getNumDefs() >= 1)
952 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
954 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
955 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
956 II.ImplicitDefs[0], RC, RC);
963 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
964 const TargetRegisterClass *RC,
965 unsigned Op0, uint64_t Imm) {
966 unsigned ResultReg = createResultReg(RC);
967 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
969 if (II.getNumDefs() >= 1)
970 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
972 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
973 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
974 II.ImplicitDefs[0], RC, RC);
981 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
982 const TargetRegisterClass *RC,
983 unsigned Op0, ConstantFP *FPImm) {
984 unsigned ResultReg = createResultReg(RC);
985 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
987 if (II.getNumDefs() >= 1)
988 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
990 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
991 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
992 II.ImplicitDefs[0], RC, RC);
999 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
1000 const TargetRegisterClass *RC,
1001 unsigned Op0, unsigned Op1, uint64_t Imm) {
1002 unsigned ResultReg = createResultReg(RC);
1003 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1005 if (II.getNumDefs() >= 1)
1006 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
1008 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
1009 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1010 II.ImplicitDefs[0], RC, RC);
1017 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
1018 const TargetRegisterClass *RC,
1020 unsigned ResultReg = createResultReg(RC);
1021 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1023 if (II.getNumDefs() >= 1)
1024 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1026 BuildMI(MBB, DL, II).addImm(Imm);
1027 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1028 II.ImplicitDefs[0], RC, RC);
1035 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
1036 unsigned Op0, uint32_t Idx) {
1037 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1039 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1040 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1042 if (II.getNumDefs() >= 1)
1043 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1045 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1046 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1047 II.ImplicitDefs[0], RC, RC);
1054 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1055 /// with all but the least significant bit set to zero.
1056 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
1057 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);