1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/Instructions.h"
15 #include "llvm/CodeGen/FastISel.h"
16 #include "llvm/CodeGen/MachineInstrBuilder.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Target/TargetData.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/Target/TargetMachine.h"
24 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
25 /// which has an opcode which directly corresponds to the given ISD opcode.
27 bool FastISel::SelectBinaryOp(Instruction *I, ISD::NodeType ISDOpcode,
28 DenseMap<const Value*, unsigned> &ValueMap) {
29 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
30 if (VT == MVT::Other || !VT.isSimple())
31 // Unhandled type. Halt "fast" selection and bail.
33 // We only handle legal types. For example, on x86-32 the instruction
34 // selector contains all of the 64-bit instructions from x86-64,
35 // under the assumption that i64 won't be used if the target doesn't
37 if (!TLI.isTypeLegal(VT))
40 unsigned Op0 = ValueMap[I->getOperand(0)];
42 // Unhandled operand. Halt "fast" selection and bail.
45 // Check if the second operand is a constant and handle it appropriately.
46 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
47 unsigned ResultReg = FastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0,
48 CI->getZExtValue(), VT.getSimpleVT());
50 // Target-specific code wasn't able to find a machine opcode for
51 // the given ISD opcode and type. Halt "fast" selection and bail.
54 // We successfully emitted code for the given LLVM Instruction.
55 ValueMap[I] = ResultReg;
59 // Check if the second operand is a constant float.
60 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
61 unsigned ResultReg = FastEmit_rf_(VT.getSimpleVT(), ISDOpcode, Op0,
62 CF, VT.getSimpleVT());
64 // Target-specific code wasn't able to find a machine opcode for
65 // the given ISD opcode and type. Halt "fast" selection and bail.
68 // We successfully emitted code for the given LLVM Instruction.
69 ValueMap[I] = ResultReg;
73 unsigned Op1 = ValueMap[I->getOperand(1)];
75 // Unhandled operand. Halt "fast" selection and bail.
78 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
81 // Target-specific code wasn't able to find a machine opcode for
82 // the given ISD opcode and type. Halt "fast" selection and bail.
85 // We successfully emitted code for the given LLVM Instruction.
86 ValueMap[I] = ResultReg;
90 bool FastISel::SelectGetElementPtr(Instruction *I,
91 DenseMap<const Value*, unsigned> &ValueMap) {
92 unsigned N = ValueMap[I->getOperand(0)];
94 // Unhandled operand. Halt "fast" selection and bail.
97 const Type *Ty = I->getOperand(0)->getType();
98 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
99 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
102 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
103 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
106 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
107 // FIXME: This can be optimized by combining the add with a
109 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
111 // Unhandled operand. Halt "fast" selection and bail.
114 Ty = StTy->getElementType(Field);
116 Ty = cast<SequentialType>(Ty)->getElementType();
118 // If this is a constant subscript, handle it quickly.
119 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
120 if (CI->getZExtValue() == 0) continue;
122 TD.getABITypeSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
123 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
125 // Unhandled operand. Halt "fast" selection and bail.
130 // N = N + Idx * ElementSize;
131 uint64_t ElementSize = TD.getABITypeSize(Ty);
132 unsigned IdxN = ValueMap[Idx];
134 // Unhandled operand. Halt "fast" selection and bail.
137 // If the index is smaller or larger than intptr_t, truncate or extend
139 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
140 if (IdxVT.bitsLT(VT))
141 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::SIGN_EXTEND, IdxN);
142 else if (IdxVT.bitsGT(VT))
143 IdxN = FastEmit_r(IdxVT.getSimpleVT(), VT, ISD::TRUNCATE, IdxN);
145 // Unhandled operand. Halt "fast" selection and bail.
148 if (ElementSize != 1) {
149 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
151 // Unhandled operand. Halt "fast" selection and bail.
154 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
156 // Unhandled operand. Halt "fast" selection and bail.
161 // We successfully emitted code for the given LLVM Instruction.
166 bool FastISel::SelectCast(Instruction *I, ISD::NodeType Opcode,
167 DenseMap<const Value*, unsigned> &ValueMap) {
168 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
169 MVT DstVT = MVT::getMVT(I->getType());
171 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
172 DstVT == MVT::Other || !DstVT.isSimple() ||
173 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
174 // Unhandled type. Halt "fast" selection and bail.
177 unsigned InputReg = ValueMap[I->getOperand(0)];
179 // Unhandled operand. Halt "fast" selection and bail.
182 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
189 ValueMap[I] = ResultReg;
193 bool FastISel::SelectConstantCast(Instruction* I, ISD::NodeType Opcode,
194 DenseMap<const Value*, unsigned> &ValueMap) {
195 // Materialize constant and convert.
196 ConstantInt* CI = cast<ConstantInt>(I->getOperand(0));
197 MVT SrcVT = MVT::getMVT(CI->getType());
198 MVT DstVT = MVT::getMVT(I->getType());
200 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
201 DstVT == MVT::Other || !DstVT.isSimple() ||
202 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
203 // Unhandled type. Halt "fast" selection and bail.
206 unsigned ResultReg1 = FastEmit_i(SrcVT.getSimpleVT(),
208 ISD::Constant, CI->getZExtValue());
212 unsigned ResultReg2 = FastEmit_r(SrcVT.getSimpleVT(),
219 ValueMap[I] = ResultReg2;
223 bool FastISel::SelectConstantFPCast(Instruction* I, ISD::NodeType Opcode,
224 DenseMap<const Value*, unsigned> &ValueMap) {
225 // TODO: Implement casting of FP constants by materialization
226 // followed by conversion.
230 bool FastISel::SelectBitCast(Instruction *I,
231 DenseMap<const Value*, unsigned> &ValueMap) {
232 // BitCast consists of either an immediate to register move
233 // or a register to register move.
234 if (ConstantInt* CI = dyn_cast<ConstantInt>(I->getOperand(0))) {
235 if (I->getType()->isInteger()) {
236 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/false);
237 unsigned result = FastEmit_i(VT.getSimpleVT(), VT.getSimpleVT(),
243 ValueMap[I] = result;
247 // TODO: Support vector and fp constants.
251 if (!isa<Constant>(I->getOperand(0))) {
252 // Bitcasts of non-constant values become reg-reg copies.
253 MVT SrcVT = MVT::getMVT(I->getOperand(0)->getType());
254 MVT DstVT = MVT::getMVT(I->getType());
256 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
257 DstVT == MVT::Other || !DstVT.isSimple() ||
258 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
259 // Unhandled type. Halt "fast" selection and bail.
262 unsigned Op0 = ValueMap[I->getOperand(0)];
264 // Unhandled operand. Halt "fast" selection and bail.
267 // First, try to perform the bitcast by inserting a reg-reg copy.
268 unsigned ResultReg = 0;
269 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
270 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
271 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
272 ResultReg = createResultReg(DstClass);
274 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
275 Op0, DstClass, SrcClass);
280 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
282 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
283 ISD::BIT_CONVERT, Op0);
288 ValueMap[I] = ResultReg;
292 // TODO: Casting a non-integral constant?
297 FastISel::SelectInstructions(BasicBlock::iterator Begin,
298 BasicBlock::iterator End,
299 DenseMap<const Value*, unsigned> &ValueMap,
300 DenseMap<const BasicBlock*,
301 MachineBasicBlock *> &MBBMap,
302 MachineBasicBlock *mbb) {
304 BasicBlock::iterator I = Begin;
306 for (; I != End; ++I) {
307 switch (I->getOpcode()) {
308 case Instruction::Add: {
309 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FADD : ISD::ADD;
310 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
312 case Instruction::Sub: {
313 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FSUB : ISD::SUB;
314 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
316 case Instruction::Mul: {
317 ISD::NodeType Opc = I->getType()->isFPOrFPVector() ? ISD::FMUL : ISD::MUL;
318 if (!SelectBinaryOp(I, Opc, ValueMap)) return I; break;
320 case Instruction::SDiv:
321 if (!SelectBinaryOp(I, ISD::SDIV, ValueMap)) return I; break;
322 case Instruction::UDiv:
323 if (!SelectBinaryOp(I, ISD::UDIV, ValueMap)) return I; break;
324 case Instruction::FDiv:
325 if (!SelectBinaryOp(I, ISD::FDIV, ValueMap)) return I; break;
326 case Instruction::SRem:
327 if (!SelectBinaryOp(I, ISD::SREM, ValueMap)) return I; break;
328 case Instruction::URem:
329 if (!SelectBinaryOp(I, ISD::UREM, ValueMap)) return I; break;
330 case Instruction::FRem:
331 if (!SelectBinaryOp(I, ISD::FREM, ValueMap)) return I; break;
332 case Instruction::Shl:
333 if (!SelectBinaryOp(I, ISD::SHL, ValueMap)) return I; break;
334 case Instruction::LShr:
335 if (!SelectBinaryOp(I, ISD::SRL, ValueMap)) return I; break;
336 case Instruction::AShr:
337 if (!SelectBinaryOp(I, ISD::SRA, ValueMap)) return I; break;
338 case Instruction::And:
339 if (!SelectBinaryOp(I, ISD::AND, ValueMap)) return I; break;
340 case Instruction::Or:
341 if (!SelectBinaryOp(I, ISD::OR, ValueMap)) return I; break;
342 case Instruction::Xor:
343 if (!SelectBinaryOp(I, ISD::XOR, ValueMap)) return I; break;
345 case Instruction::GetElementPtr:
346 if (!SelectGetElementPtr(I, ValueMap)) return I;
349 case Instruction::Br: {
350 BranchInst *BI = cast<BranchInst>(I);
352 if (BI->isUnconditional()) {
353 MachineFunction::iterator NextMBB =
354 next(MachineFunction::iterator(MBB));
355 BasicBlock *LLVMSucc = BI->getSuccessor(0);
356 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
358 if (NextMBB != MF.end() && MSucc == NextMBB) {
359 // The unconditional fall-through case, which needs no instructions.
361 // The unconditional branch case.
362 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
364 MBB->addSuccessor(MSucc);
368 // Conditional branches are not handed yet.
369 // Halt "fast" selection and bail.
373 case Instruction::PHI:
374 // PHI nodes are already emitted.
377 case Instruction::BitCast:
378 if (!SelectBitCast(I, ValueMap)) return I; break;
380 case Instruction::FPToSI:
381 if (!isa<ConstantFP>(I->getOperand(0))) {
382 if (!SelectCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
384 if (!SelectConstantFPCast(I, ISD::FP_TO_SINT, ValueMap)) return I;
386 case Instruction::ZExt:
387 if (!isa<ConstantInt>(I->getOperand(0))) {
388 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
390 if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
392 case Instruction::SExt:
393 if (!isa<ConstantInt>(I->getOperand(0))) {
394 if (!SelectCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
396 if (!SelectConstantCast(I, ISD::SIGN_EXTEND, ValueMap)) return I;
398 case Instruction::SIToFP:
399 if (!isa<ConstantInt>(I->getOperand(0))) {
400 if (!SelectCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
402 if (!SelectConstantCast(I, ISD::SINT_TO_FP, ValueMap)) return I;
405 case Instruction::IntToPtr: // Deliberate fall-through.
406 case Instruction::PtrToInt: {
407 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
408 MVT DstVT = TLI.getValueType(I->getType());
409 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
410 if (ValueMap[I->getOperand(0)]) {
411 ValueMap[I] = ValueMap[I->getOperand(0)];
416 } else if (DstVT.bitsGT(SrcVT)) {
417 if (!isa<ConstantInt>(I->getOperand(0))) {
418 if (!SelectCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
420 if (!SelectConstantCast(I, ISD::ZERO_EXTEND, ValueMap)) return I;
423 // TODO: Handle SrcVT > DstVT, where truncation is needed.
429 // Unhandled instruction. Halt "fast" selection and bail.
437 FastISel::FastISel(MachineFunction &mf)
439 MRI(mf.getRegInfo()),
441 TD(*TM.getTargetData()),
442 TII(*TM.getInstrInfo()),
443 TLI(*TM.getTargetLowering()) {
446 FastISel::~FastISel() {}
448 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, ISD::NodeType) {
452 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
453 ISD::NodeType, unsigned /*Op0*/) {
457 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
458 ISD::NodeType, unsigned /*Op0*/,
463 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
464 ISD::NodeType, uint64_t /*Imm*/) {
468 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
469 ISD::NodeType, ConstantFP * /*FPImm*/) {
473 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
474 ISD::NodeType, unsigned /*Op0*/,
479 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
480 ISD::NodeType, unsigned /*Op0*/,
481 ConstantFP * /*FPImm*/) {
485 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
487 unsigned /*Op0*/, unsigned /*Op1*/,
492 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
493 /// to emit an instruction with an immediate operand using FastEmit_ri.
494 /// If that fails, it materializes the immediate into a register and try
495 /// FastEmit_rr instead.
496 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
497 unsigned Op0, uint64_t Imm,
498 MVT::SimpleValueType ImmType) {
499 unsigned ResultReg = 0;
500 // First check if immediate type is legal. If not, we can't use the ri form.
501 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
502 ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
505 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
506 if (MaterialReg == 0)
508 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
511 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
512 /// to emit an instruction with a floating-point immediate operand using
513 /// FastEmit_rf. If that fails, it materializes the immediate into a register
514 /// and try FastEmit_rr instead.
515 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
516 unsigned Op0, ConstantFP *FPImm,
517 MVT::SimpleValueType ImmType) {
518 unsigned ResultReg = 0;
519 // First check if immediate type is legal. If not, we can't use the rf form.
520 if (TLI.getOperationAction(ISD::Constant, ImmType) == TargetLowering::Legal)
521 ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
525 // Materialize the constant in a register.
526 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
527 if (MaterialReg == 0) {
528 const APFloat &Flt = FPImm->getValueAPF();
529 MVT IntVT = TLI.getPointerTy();
532 uint32_t IntBitWidth = IntVT.getSizeInBits();
533 if (Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
534 APFloat::rmTowardZero) != APFloat::opOK)
536 APInt IntVal(IntBitWidth, 2, x);
538 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
539 ISD::Constant, IntVal.getZExtValue());
542 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
543 ISD::SINT_TO_FP, IntegerReg);
544 if (MaterialReg == 0)
547 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
550 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
551 return MRI.createVirtualRegister(RC);
554 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
555 const TargetRegisterClass* RC) {
556 unsigned ResultReg = createResultReg(RC);
557 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
559 BuildMI(MBB, II, ResultReg);
563 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
564 const TargetRegisterClass *RC,
566 unsigned ResultReg = createResultReg(RC);
567 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
569 BuildMI(MBB, II, ResultReg).addReg(Op0);
573 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
574 const TargetRegisterClass *RC,
575 unsigned Op0, unsigned Op1) {
576 unsigned ResultReg = createResultReg(RC);
577 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
579 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1);
583 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
584 const TargetRegisterClass *RC,
585 unsigned Op0, uint64_t Imm) {
586 unsigned ResultReg = createResultReg(RC);
587 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
589 BuildMI(MBB, II, ResultReg).addReg(Op0).addImm(Imm);
593 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
594 const TargetRegisterClass *RC,
595 unsigned Op0, ConstantFP *FPImm) {
596 unsigned ResultReg = createResultReg(RC);
597 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
599 BuildMI(MBB, II, ResultReg).addReg(Op0).addFPImm(FPImm);
603 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
604 const TargetRegisterClass *RC,
605 unsigned Op0, unsigned Op1, uint64_t Imm) {
606 unsigned ResultReg = createResultReg(RC);
607 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
609 BuildMI(MBB, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
613 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
614 const TargetRegisterClass *RC,
616 unsigned ResultReg = createResultReg(RC);
617 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
619 BuildMI(MBB, II, ResultReg).addImm(Imm);