1 ///===-- FastISel.cpp - Implementation of the FastISel class --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the implementation of the FastISel class.
12 // "Fast" instruction selection is designed to emit very poor code quickly.
13 // Also, it is not designed to be able to do much lowering, so most illegal
14 // types (e.g. i64 on 32-bit targets) and operations are not supported. It is
15 // also not intended to be able to do much optimization, except in a few cases
16 // where doing optimizations reduces overall compile time. For example, folding
17 // constants into immediate fields is often done, because it's cheap and it
18 // reduces the number of instructions later phases have to examine.
20 // "Fast" instruction selection is able to fail gracefully and transfer
21 // control to the SelectionDAG selector for operations that it doesn't
22 // support. In many cases, this allows us to avoid duplicating a lot of
23 // the complicated lowering logic that SelectionDAG currently has.
25 // The intended use for "fast" instruction selection is "-O0" mode
26 // compilation, where the quality of the generated code is irrelevant when
27 // weighed against the speed at which the code can be generated. Also,
28 // at -O0, the LLVM optimizers are not running, and this makes the
29 // compile time of codegen a much higher portion of the overall compile
30 // time. Despite its limitations, "fast" instruction selection is able to
31 // handle enough code on its own to provide noticeable overall speedups
34 // Basic operations are supported in a target-independent way, by reading
35 // the same instruction descriptions that the SelectionDAG selector reads,
36 // and identifying simple arithmetic operations that can be directly selected
37 // from simple operators. More complicated operations currently require
38 // target-specific code.
40 //===----------------------------------------------------------------------===//
42 #include "llvm/Function.h"
43 #include "llvm/GlobalVariable.h"
44 #include "llvm/Instructions.h"
45 #include "llvm/IntrinsicInst.h"
46 #include "llvm/CodeGen/FastISel.h"
47 #include "llvm/CodeGen/MachineInstrBuilder.h"
48 #include "llvm/CodeGen/MachineModuleInfo.h"
49 #include "llvm/CodeGen/MachineRegisterInfo.h"
50 #include "llvm/CodeGen/DwarfWriter.h"
51 #include "llvm/Analysis/DebugInfo.h"
52 #include "llvm/Target/TargetData.h"
53 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetLowering.h"
55 #include "llvm/Target/TargetMachine.h"
56 #include "SelectionDAGBuild.h"
59 unsigned FastISel::getRegForValue(Value *V) {
60 MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
61 // Don't handle non-simple values in FastISel.
62 if (!RealVT.isSimple())
65 // Ignore illegal types. We must do this before looking up the value
66 // in ValueMap because Arguments are given virtual registers regardless
67 // of whether FastISel can handle them.
68 MVT::SimpleValueType VT = RealVT.getSimpleVT();
69 if (!TLI.isTypeLegal(VT)) {
70 // Promote MVT::i1 to a legal type though, because it's common and easy.
72 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
77 // Look up the value to see if we already have a register for it. We
78 // cache values defined by Instructions across blocks, and other values
79 // only locally. This is because Instructions already have the SSA
80 // def-dominatess-use requirement enforced.
81 if (ValueMap.count(V))
83 unsigned Reg = LocalValueMap[V];
87 if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
88 if (CI->getValue().getActiveBits() <= 64)
89 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
90 } else if (isa<AllocaInst>(V)) {
91 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V));
92 } else if (isa<ConstantPointerNull>(V)) {
93 // Translate this as an integer zero so that it can be
94 // local-CSE'd with actual integer zeros.
95 Reg = getRegForValue(Constant::getNullValue(TD.getIntPtrType()));
96 } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
97 Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
100 const APFloat &Flt = CF->getValueAPF();
101 MVT IntVT = TLI.getPointerTy();
104 uint32_t IntBitWidth = IntVT.getSizeInBits();
106 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
107 APFloat::rmTowardZero, &isExact);
109 APInt IntVal(IntBitWidth, 2, x);
111 unsigned IntegerReg = getRegForValue(ConstantInt::get(IntVal));
113 Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
116 } else if (ConstantExpr *CE = dyn_cast<ConstantExpr>(V)) {
117 if (!SelectOperator(CE, CE->getOpcode())) return 0;
118 Reg = LocalValueMap[CE];
119 } else if (isa<UndefValue>(V)) {
120 Reg = createResultReg(TLI.getRegClassFor(VT));
121 BuildMI(MBB, DL, TII.get(TargetInstrInfo::IMPLICIT_DEF), Reg);
124 // If target-independent code couldn't handle the value, give target-specific
126 if (!Reg && isa<Constant>(V))
127 Reg = TargetMaterializeConstant(cast<Constant>(V));
129 // Don't cache constant materializations in the general ValueMap.
130 // To do so would require tracking what uses they dominate.
132 LocalValueMap[V] = Reg;
136 unsigned FastISel::lookUpRegForValue(Value *V) {
137 // Look up the value to see if we already have a register for it. We
138 // cache values defined by Instructions across blocks, and other values
139 // only locally. This is because Instructions already have the SSA
140 // def-dominatess-use requirement enforced.
141 if (ValueMap.count(V))
143 return LocalValueMap[V];
146 /// UpdateValueMap - Update the value map to include the new mapping for this
147 /// instruction, or insert an extra copy to get the result in a previous
148 /// determined register.
149 /// NOTE: This is only necessary because we might select a block that uses
150 /// a value before we select the block that defines the value. It might be
151 /// possible to fix this by selecting blocks in reverse postorder.
152 unsigned FastISel::UpdateValueMap(Value* I, unsigned Reg) {
153 if (!isa<Instruction>(I)) {
154 LocalValueMap[I] = Reg;
158 unsigned &AssignedReg = ValueMap[I];
159 if (AssignedReg == 0)
161 else if (Reg != AssignedReg) {
162 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
163 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
164 Reg, RegClass, RegClass);
169 unsigned FastISel::getRegForGEPIndex(Value *Idx) {
170 unsigned IdxN = getRegForValue(Idx);
172 // Unhandled operand. Halt "fast" selection and bail.
175 // If the index is smaller or larger than intptr_t, truncate or extend it.
176 MVT PtrVT = TLI.getPointerTy();
177 MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
178 if (IdxVT.bitsLT(PtrVT))
179 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
180 ISD::SIGN_EXTEND, IdxN);
181 else if (IdxVT.bitsGT(PtrVT))
182 IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
183 ISD::TRUNCATE, IdxN);
187 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
188 /// which has an opcode which directly corresponds to the given ISD opcode.
190 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
191 MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
192 if (VT == MVT::Other || !VT.isSimple())
193 // Unhandled type. Halt "fast" selection and bail.
196 // We only handle legal types. For example, on x86-32 the instruction
197 // selector contains all of the 64-bit instructions from x86-64,
198 // under the assumption that i64 won't be used if the target doesn't
200 if (!TLI.isTypeLegal(VT)) {
201 // MVT::i1 is special. Allow AND, OR, or XOR because they
202 // don't require additional zeroing, which makes them easy.
204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
205 ISDOpcode == ISD::XOR))
206 VT = TLI.getTypeToTransformTo(VT);
211 unsigned Op0 = getRegForValue(I->getOperand(0));
213 // Unhandled operand. Halt "fast" selection and bail.
216 // Check if the second operand is a constant and handle it appropriately.
217 if (ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
218 unsigned ResultReg = FastEmit_ri(VT.getSimpleVT(), VT.getSimpleVT(),
219 ISDOpcode, Op0, CI->getZExtValue());
220 if (ResultReg != 0) {
221 // We successfully emitted code for the given LLVM Instruction.
222 UpdateValueMap(I, ResultReg);
227 // Check if the second operand is a constant float.
228 if (ConstantFP *CF = dyn_cast<ConstantFP>(I->getOperand(1))) {
229 unsigned ResultReg = FastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(),
231 if (ResultReg != 0) {
232 // We successfully emitted code for the given LLVM Instruction.
233 UpdateValueMap(I, ResultReg);
238 unsigned Op1 = getRegForValue(I->getOperand(1));
240 // Unhandled operand. Halt "fast" selection and bail.
243 // Now we have both operands in registers. Emit the instruction.
244 unsigned ResultReg = FastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(),
245 ISDOpcode, Op0, Op1);
247 // Target-specific code wasn't able to find a machine opcode for
248 // the given ISD opcode and type. Halt "fast" selection and bail.
251 // We successfully emitted code for the given LLVM Instruction.
252 UpdateValueMap(I, ResultReg);
256 bool FastISel::SelectGetElementPtr(User *I) {
257 unsigned N = getRegForValue(I->getOperand(0));
259 // Unhandled operand. Halt "fast" selection and bail.
262 const Type *Ty = I->getOperand(0)->getType();
263 MVT::SimpleValueType VT = TLI.getPointerTy().getSimpleVT();
264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
267 if (const StructType *StTy = dyn_cast<StructType>(Ty)) {
268 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue();
271 uint64_t Offs = TD.getStructLayout(StTy)->getElementOffset(Field);
272 // FIXME: This can be optimized by combining the add with a
274 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
276 // Unhandled operand. Halt "fast" selection and bail.
279 Ty = StTy->getElementType(Field);
281 Ty = cast<SequentialType>(Ty)->getElementType();
283 // If this is a constant subscript, handle it quickly.
284 if (ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) {
285 if (CI->getZExtValue() == 0) continue;
287 TD.getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
288 N = FastEmit_ri_(VT, ISD::ADD, N, Offs, VT);
290 // Unhandled operand. Halt "fast" selection and bail.
295 // N = N + Idx * ElementSize;
296 uint64_t ElementSize = TD.getTypeAllocSize(Ty);
297 unsigned IdxN = getRegForGEPIndex(Idx);
299 // Unhandled operand. Halt "fast" selection and bail.
302 if (ElementSize != 1) {
303 IdxN = FastEmit_ri_(VT, ISD::MUL, IdxN, ElementSize, VT);
305 // Unhandled operand. Halt "fast" selection and bail.
308 N = FastEmit_rr(VT, VT, ISD::ADD, N, IdxN);
310 // Unhandled operand. Halt "fast" selection and bail.
315 // We successfully emitted code for the given LLVM Instruction.
316 UpdateValueMap(I, N);
320 bool FastISel::SelectCall(User *I) {
321 Function *F = cast<CallInst>(I)->getCalledFunction();
322 if (!F) return false;
324 unsigned IID = F->getIntrinsicID();
327 case Intrinsic::dbg_stoppoint: {
328 DbgStopPointInst *SPI = cast<DbgStopPointInst>(I);
329 if (DIDescriptor::ValidDebugInfo(SPI->getContext(), CodeGenOpt::None)) {
330 DICompileUnit CU(cast<GlobalVariable>(SPI->getContext()));
331 unsigned Line = SPI->getLine();
332 unsigned Col = SPI->getColumn();
333 unsigned Idx = MF.getOrCreateDebugLocID(CU.getGV(), Line, Col);
334 setCurDebugLoc(DebugLoc::get(Idx));
338 case Intrinsic::dbg_region_start: {
339 DbgRegionStartInst *RSI = cast<DbgRegionStartInst>(I);
340 if (DIDescriptor::ValidDebugInfo(RSI->getContext(), CodeGenOpt::None) &&
341 DW && DW->ShouldEmitDwarfDebug()) {
343 DW->RecordRegionStart(cast<GlobalVariable>(RSI->getContext()));
344 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
345 BuildMI(MBB, DL, II).addImm(ID);
349 case Intrinsic::dbg_region_end: {
350 DbgRegionEndInst *REI = cast<DbgRegionEndInst>(I);
351 if (DIDescriptor::ValidDebugInfo(REI->getContext(), CodeGenOpt::None) &&
352 DW && DW->ShouldEmitDwarfDebug()) {
354 DISubprogram Subprogram(cast<GlobalVariable>(REI->getContext()));
355 if (!Subprogram.isNull() && !Subprogram.describes(MF.getFunction())) {
356 // This is end of an inlined function.
357 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
358 ID = DW->RecordInlinedFnEnd(Subprogram);
360 // Returned ID is 0 if this is unbalanced "end of inlined
361 // scope". This could happen if optimizer eats dbg intrinsics
362 // or "beginning of inlined scope" is not recoginized due to
363 // missing location info. In such cases, ignore this region.end.
364 BuildMI(MBB, DL, II).addImm(ID);
366 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
367 ID = DW->RecordRegionEnd(cast<GlobalVariable>(REI->getContext()));
368 BuildMI(MBB, DL, II).addImm(ID);
373 case Intrinsic::dbg_func_start: {
374 DbgFuncStartInst *FSI = cast<DbgFuncStartInst>(I);
375 Value *SP = FSI->getSubprogram();
376 if (!DIDescriptor::ValidDebugInfo(SP, CodeGenOpt::None))
379 DISubprogram Subprogram(cast<GlobalVariable>(SP));
380 DICompileUnit CompileUnit = Subprogram.getCompileUnit();
381 unsigned Line = Subprogram.getLineNumber();
383 // If this subprogram does not describe current function then this is
384 // beginning of a inlined function.
385 if (!Subprogram.describes(MF.getFunction())) {
386 // This is a beginning of an inlined function.
388 // If llvm.dbg.func.start is seen in a new block before any
389 // llvm.dbg.stoppoint intrinsic then the location info is unknown.
390 // FIXME : Why DebugLoc is reset at the beginning of each block ?
391 DebugLoc PrevLoc = DL;
392 if (PrevLoc.isUnknown())
394 // Record the source line.
395 unsigned LocID = MF.getOrCreateDebugLocID(CompileUnit.getGV(), Line, 0);
396 setCurDebugLoc(DebugLoc::get(LocID));
398 if (DW && DW->ShouldEmitDwarfDebug()) {
399 DebugLocTuple PrevLocTpl = MF.getDebugLocTuple(PrevLoc);
400 unsigned LabelID = DW->RecordInlinedFnStart(Subprogram,
401 DICompileUnit(PrevLocTpl.CompileUnit),
404 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DBG_LABEL);
405 BuildMI(MBB, DL, II).addImm(LabelID);
410 // This is a beginning of a new function.
411 // Record the source line.
412 unsigned LocID = MF.getOrCreateDebugLocID(CompileUnit.getGV(), Line, 0);
413 MF.setDefaultDebugLoc(DebugLoc::get(LocID));
415 if (DW && DW->ShouldEmitDwarfDebug())
416 // llvm.dbg.func_start also defines beginning of function scope.
417 DW->RecordRegionStart(cast<GlobalVariable>(FSI->getSubprogram()));
421 case Intrinsic::dbg_declare: {
422 DbgDeclareInst *DI = cast<DbgDeclareInst>(I);
423 Value *Variable = DI->getVariable();
424 if (DIDescriptor::ValidDebugInfo(Variable, CodeGenOpt::None) &&
425 DW && DW->ShouldEmitDwarfDebug()) {
426 // Determine the address of the declared object.
427 Value *Address = DI->getAddress();
428 if (BitCastInst *BCI = dyn_cast<BitCastInst>(Address))
429 Address = BCI->getOperand(0);
430 AllocaInst *AI = dyn_cast<AllocaInst>(Address);
431 // Don't handle byval struct arguments or VLAs, for example.
433 DenseMap<const AllocaInst*, int>::iterator SI =
434 StaticAllocaMap.find(AI);
435 if (SI == StaticAllocaMap.end()) break; // VLAs.
438 // Determine the debug globalvariable.
439 GlobalValue *GV = cast<GlobalVariable>(Variable);
441 // Build the DECLARE instruction.
442 const TargetInstrDesc &II = TII.get(TargetInstrInfo::DECLARE);
443 MachineInstr *DeclareMI
444 = BuildMI(MBB, DL, II).addFrameIndex(FI).addGlobalAddress(GV);
445 DIVariable DV(cast<GlobalVariable>(GV));
446 DW->RecordVariableScope(DV, DeclareMI);
450 case Intrinsic::eh_exception: {
451 MVT VT = TLI.getValueType(I->getType());
452 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
454 case TargetLowering::Expand: {
455 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
456 unsigned Reg = TLI.getExceptionAddressRegister();
457 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
458 unsigned ResultReg = createResultReg(RC);
459 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
461 assert(InsertedCopy && "Can't copy address registers!");
462 InsertedCopy = InsertedCopy;
463 UpdateValueMap(I, ResultReg);
469 case Intrinsic::eh_selector_i32:
470 case Intrinsic::eh_selector_i64: {
471 MVT VT = TLI.getValueType(I->getType());
472 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
474 case TargetLowering::Expand: {
475 MVT VT = (IID == Intrinsic::eh_selector_i32 ?
476 MVT::i32 : MVT::i64);
479 if (MBB->isLandingPad())
480 AddCatchInfo(*cast<CallInst>(I), MMI, MBB);
483 CatchInfoLost.insert(cast<CallInst>(I));
485 // FIXME: Mark exception selector register as live in. Hack for PR1508.
486 unsigned Reg = TLI.getExceptionSelectorRegister();
487 if (Reg) MBB->addLiveIn(Reg);
490 unsigned Reg = TLI.getExceptionSelectorRegister();
491 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
492 unsigned ResultReg = createResultReg(RC);
493 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
495 assert(InsertedCopy && "Can't copy address registers!");
496 InsertedCopy = InsertedCopy;
497 UpdateValueMap(I, ResultReg);
500 getRegForValue(Constant::getNullValue(I->getType()));
501 UpdateValueMap(I, ResultReg);
512 bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
513 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
514 MVT DstVT = TLI.getValueType(I->getType());
516 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
517 DstVT == MVT::Other || !DstVT.isSimple())
518 // Unhandled type. Halt "fast" selection and bail.
521 // Check if the destination type is legal. Or as a special case,
522 // it may be i1 if we're doing a truncate because that's
523 // easy and somewhat common.
524 if (!TLI.isTypeLegal(DstVT))
525 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
526 // Unhandled type. Halt "fast" selection and bail.
529 // Check if the source operand is legal. Or as a special case,
530 // it may be i1 if we're doing zero-extension because that's
531 // easy and somewhat common.
532 if (!TLI.isTypeLegal(SrcVT))
533 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
534 // Unhandled type. Halt "fast" selection and bail.
537 unsigned InputReg = getRegForValue(I->getOperand(0));
539 // Unhandled operand. Halt "fast" selection and bail.
542 // If the operand is i1, arrange for the high bits in the register to be zero.
543 if (SrcVT == MVT::i1) {
544 SrcVT = TLI.getTypeToTransformTo(SrcVT);
545 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
549 // If the result is i1, truncate to the target's type for i1 first.
550 if (DstVT == MVT::i1)
551 DstVT = TLI.getTypeToTransformTo(DstVT);
553 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
560 UpdateValueMap(I, ResultReg);
564 bool FastISel::SelectBitCast(User *I) {
565 // If the bitcast doesn't change the type, just use the operand value.
566 if (I->getType() == I->getOperand(0)->getType()) {
567 unsigned Reg = getRegForValue(I->getOperand(0));
570 UpdateValueMap(I, Reg);
574 // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
575 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
576 MVT DstVT = TLI.getValueType(I->getType());
578 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
579 DstVT == MVT::Other || !DstVT.isSimple() ||
580 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
581 // Unhandled type. Halt "fast" selection and bail.
584 unsigned Op0 = getRegForValue(I->getOperand(0));
586 // Unhandled operand. Halt "fast" selection and bail.
589 // First, try to perform the bitcast by inserting a reg-reg copy.
590 unsigned ResultReg = 0;
591 if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
592 TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT);
593 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
594 ResultReg = createResultReg(DstClass);
596 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
597 Op0, DstClass, SrcClass);
602 // If the reg-reg copy failed, select a BIT_CONVERT opcode.
604 ResultReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(),
605 ISD::BIT_CONVERT, Op0);
610 UpdateValueMap(I, ResultReg);
615 FastISel::SelectInstruction(Instruction *I) {
616 return SelectOperator(I, I->getOpcode());
619 /// FastEmitBranch - Emit an unconditional branch to the given block,
620 /// unless it is the immediate (fall-through) successor, and update
623 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
624 MachineFunction::iterator NextMBB =
625 next(MachineFunction::iterator(MBB));
627 if (MBB->isLayoutSuccessor(MSucc)) {
628 // The unconditional fall-through case, which needs no instructions.
630 // The unconditional branch case.
631 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector<MachineOperand, 0>());
633 MBB->addSuccessor(MSucc);
637 FastISel::SelectOperator(User *I, unsigned Opcode) {
639 case Instruction::Add:
640 return SelectBinaryOp(I, ISD::ADD);
641 case Instruction::FAdd:
642 return SelectBinaryOp(I, ISD::FADD);
643 case Instruction::Sub:
644 return SelectBinaryOp(I, ISD::SUB);
645 case Instruction::FSub:
646 return SelectBinaryOp(I, ISD::FSUB);
647 case Instruction::Mul:
648 return SelectBinaryOp(I, ISD::MUL);
649 case Instruction::FMul:
650 return SelectBinaryOp(I, ISD::FMUL);
651 case Instruction::SDiv:
652 return SelectBinaryOp(I, ISD::SDIV);
653 case Instruction::UDiv:
654 return SelectBinaryOp(I, ISD::UDIV);
655 case Instruction::FDiv:
656 return SelectBinaryOp(I, ISD::FDIV);
657 case Instruction::SRem:
658 return SelectBinaryOp(I, ISD::SREM);
659 case Instruction::URem:
660 return SelectBinaryOp(I, ISD::UREM);
661 case Instruction::FRem:
662 return SelectBinaryOp(I, ISD::FREM);
663 case Instruction::Shl:
664 return SelectBinaryOp(I, ISD::SHL);
665 case Instruction::LShr:
666 return SelectBinaryOp(I, ISD::SRL);
667 case Instruction::AShr:
668 return SelectBinaryOp(I, ISD::SRA);
669 case Instruction::And:
670 return SelectBinaryOp(I, ISD::AND);
671 case Instruction::Or:
672 return SelectBinaryOp(I, ISD::OR);
673 case Instruction::Xor:
674 return SelectBinaryOp(I, ISD::XOR);
676 case Instruction::GetElementPtr:
677 return SelectGetElementPtr(I);
679 case Instruction::Br: {
680 BranchInst *BI = cast<BranchInst>(I);
682 if (BI->isUnconditional()) {
683 BasicBlock *LLVMSucc = BI->getSuccessor(0);
684 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
685 FastEmitBranch(MSucc);
689 // Conditional branches are not handed yet.
690 // Halt "fast" selection and bail.
694 case Instruction::Unreachable:
698 case Instruction::PHI:
699 // PHI nodes are already emitted.
702 case Instruction::Alloca:
703 // FunctionLowering has the static-sized case covered.
704 if (StaticAllocaMap.count(cast<AllocaInst>(I)))
707 // Dynamic-sized alloca is not handled yet.
710 case Instruction::Call:
711 return SelectCall(I);
713 case Instruction::BitCast:
714 return SelectBitCast(I);
716 case Instruction::FPToSI:
717 return SelectCast(I, ISD::FP_TO_SINT);
718 case Instruction::ZExt:
719 return SelectCast(I, ISD::ZERO_EXTEND);
720 case Instruction::SExt:
721 return SelectCast(I, ISD::SIGN_EXTEND);
722 case Instruction::Trunc:
723 return SelectCast(I, ISD::TRUNCATE);
724 case Instruction::SIToFP:
725 return SelectCast(I, ISD::SINT_TO_FP);
727 case Instruction::IntToPtr: // Deliberate fall-through.
728 case Instruction::PtrToInt: {
729 MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
730 MVT DstVT = TLI.getValueType(I->getType());
731 if (DstVT.bitsGT(SrcVT))
732 return SelectCast(I, ISD::ZERO_EXTEND);
733 if (DstVT.bitsLT(SrcVT))
734 return SelectCast(I, ISD::TRUNCATE);
735 unsigned Reg = getRegForValue(I->getOperand(0));
736 if (Reg == 0) return false;
737 UpdateValueMap(I, Reg);
742 // Unhandled instruction. Halt "fast" selection and bail.
747 FastISel::FastISel(MachineFunction &mf,
748 MachineModuleInfo *mmi,
750 DenseMap<const Value *, unsigned> &vm,
751 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
752 DenseMap<const AllocaInst *, int> &am
754 , SmallSet<Instruction*, 8> &cil
767 MRI(MF.getRegInfo()),
768 MFI(*MF.getFrameInfo()),
769 MCP(*MF.getConstantPool()),
771 TD(*TM.getTargetData()),
772 TII(*TM.getInstrInfo()),
773 TLI(*TM.getTargetLowering()) {
776 FastISel::~FastISel() {}
778 unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
783 unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
784 ISD::NodeType, unsigned /*Op0*/) {
788 unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
789 ISD::NodeType, unsigned /*Op0*/,
794 unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
795 ISD::NodeType, uint64_t /*Imm*/) {
799 unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
800 ISD::NodeType, ConstantFP * /*FPImm*/) {
804 unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
805 ISD::NodeType, unsigned /*Op0*/,
810 unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
811 ISD::NodeType, unsigned /*Op0*/,
812 ConstantFP * /*FPImm*/) {
816 unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
818 unsigned /*Op0*/, unsigned /*Op1*/,
823 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
824 /// to emit an instruction with an immediate operand using FastEmit_ri.
825 /// If that fails, it materializes the immediate into a register and try
826 /// FastEmit_rr instead.
827 unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
828 unsigned Op0, uint64_t Imm,
829 MVT::SimpleValueType ImmType) {
830 // First check if immediate type is legal. If not, we can't use the ri form.
831 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
834 unsigned MaterialReg = FastEmit_i(ImmType, ImmType, ISD::Constant, Imm);
835 if (MaterialReg == 0)
837 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
840 /// FastEmit_rf_ - This method is a wrapper of FastEmit_ri. It first tries
841 /// to emit an instruction with a floating-point immediate operand using
842 /// FastEmit_rf. If that fails, it materializes the immediate into a register
843 /// and try FastEmit_rr instead.
844 unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
845 unsigned Op0, ConstantFP *FPImm,
846 MVT::SimpleValueType ImmType) {
847 // First check if immediate type is legal. If not, we can't use the rf form.
848 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
852 // Materialize the constant in a register.
853 unsigned MaterialReg = FastEmit_f(ImmType, ImmType, ISD::ConstantFP, FPImm);
854 if (MaterialReg == 0) {
855 // If the target doesn't have a way to directly enter a floating-point
856 // value into a register, use an alternate approach.
857 // TODO: The current approach only supports floating-point constants
858 // that can be constructed by conversion from integer values. This should
859 // be replaced by code that creates a load from a constant-pool entry,
860 // which will require some target-specific work.
861 const APFloat &Flt = FPImm->getValueAPF();
862 MVT IntVT = TLI.getPointerTy();
865 uint32_t IntBitWidth = IntVT.getSizeInBits();
867 (void) Flt.convertToInteger(x, IntBitWidth, /*isSigned=*/true,
868 APFloat::rmTowardZero, &isExact);
871 APInt IntVal(IntBitWidth, 2, x);
873 unsigned IntegerReg = FastEmit_i(IntVT.getSimpleVT(), IntVT.getSimpleVT(),
874 ISD::Constant, IntVal.getZExtValue());
877 MaterialReg = FastEmit_r(IntVT.getSimpleVT(), VT,
878 ISD::SINT_TO_FP, IntegerReg);
879 if (MaterialReg == 0)
882 return FastEmit_rr(VT, VT, Opcode, Op0, MaterialReg);
885 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) {
886 return MRI.createVirtualRegister(RC);
889 unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode,
890 const TargetRegisterClass* RC) {
891 unsigned ResultReg = createResultReg(RC);
892 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
894 BuildMI(MBB, DL, II, ResultReg);
898 unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
899 const TargetRegisterClass *RC,
901 unsigned ResultReg = createResultReg(RC);
902 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
904 if (II.getNumDefs() >= 1)
905 BuildMI(MBB, DL, II, ResultReg).addReg(Op0);
907 BuildMI(MBB, DL, II).addReg(Op0);
908 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
909 II.ImplicitDefs[0], RC, RC);
917 unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
918 const TargetRegisterClass *RC,
919 unsigned Op0, unsigned Op1) {
920 unsigned ResultReg = createResultReg(RC);
921 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
923 if (II.getNumDefs() >= 1)
924 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1);
926 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1);
927 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
928 II.ImplicitDefs[0], RC, RC);
935 unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
936 const TargetRegisterClass *RC,
937 unsigned Op0, uint64_t Imm) {
938 unsigned ResultReg = createResultReg(RC);
939 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
941 if (II.getNumDefs() >= 1)
942 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Imm);
944 BuildMI(MBB, DL, II).addReg(Op0).addImm(Imm);
945 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
946 II.ImplicitDefs[0], RC, RC);
953 unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
954 const TargetRegisterClass *RC,
955 unsigned Op0, ConstantFP *FPImm) {
956 unsigned ResultReg = createResultReg(RC);
957 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
959 if (II.getNumDefs() >= 1)
960 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addFPImm(FPImm);
962 BuildMI(MBB, DL, II).addReg(Op0).addFPImm(FPImm);
963 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
964 II.ImplicitDefs[0], RC, RC);
971 unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
972 const TargetRegisterClass *RC,
973 unsigned Op0, unsigned Op1, uint64_t Imm) {
974 unsigned ResultReg = createResultReg(RC);
975 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
977 if (II.getNumDefs() >= 1)
978 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addReg(Op1).addImm(Imm);
980 BuildMI(MBB, DL, II).addReg(Op0).addReg(Op1).addImm(Imm);
981 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
982 II.ImplicitDefs[0], RC, RC);
989 unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
990 const TargetRegisterClass *RC,
992 unsigned ResultReg = createResultReg(RC);
993 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
995 if (II.getNumDefs() >= 1)
996 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
998 BuildMI(MBB, DL, II).addImm(Imm);
999 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1000 II.ImplicitDefs[0], RC, RC);
1007 unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
1008 unsigned Op0, uint32_t Idx) {
1009 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
1011 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1012 const TargetInstrDesc &II = TII.get(TargetInstrInfo::EXTRACT_SUBREG);
1014 if (II.getNumDefs() >= 1)
1015 BuildMI(MBB, DL, II, ResultReg).addReg(Op0).addImm(Idx);
1017 BuildMI(MBB, DL, II).addReg(Op0).addImm(Idx);
1018 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1019 II.ImplicitDefs[0], RC, RC);
1026 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
1027 /// with all but the least significant bit set to zero.
1028 unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
1029 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);